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pinctrl: sunxi: use gpiolib API to mark a GPIO used as an IRQ
[deliverable/linux.git] / drivers / pinctrl / sunxi / pinctrl-sunxi.c
1 /*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13 #include <linux/io.h>
14 #include <linux/clk.h>
15 #include <linux/gpio.h>
16 #include <linux/irqdomain.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/pinctrl/pinmux.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30
31 #include "../core.h"
32 #include "pinctrl-sunxi.h"
33
34 static struct irq_chip sunxi_pinctrl_edge_irq_chip;
35 static struct irq_chip sunxi_pinctrl_level_irq_chip;
36
37 static struct sunxi_pinctrl_group *
38 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
39 {
40 int i;
41
42 for (i = 0; i < pctl->ngroups; i++) {
43 struct sunxi_pinctrl_group *grp = pctl->groups + i;
44
45 if (!strcmp(grp->name, group))
46 return grp;
47 }
48
49 return NULL;
50 }
51
52 static struct sunxi_pinctrl_function *
53 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
54 const char *name)
55 {
56 struct sunxi_pinctrl_function *func = pctl->functions;
57 int i;
58
59 for (i = 0; i < pctl->nfunctions; i++) {
60 if (!func[i].name)
61 break;
62
63 if (!strcmp(func[i].name, name))
64 return func + i;
65 }
66
67 return NULL;
68 }
69
70 static struct sunxi_desc_function *
71 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
72 const char *pin_name,
73 const char *func_name)
74 {
75 int i;
76
77 for (i = 0; i < pctl->desc->npins; i++) {
78 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
79
80 if (!strcmp(pin->pin.name, pin_name)) {
81 struct sunxi_desc_function *func = pin->functions;
82
83 while (func->name) {
84 if (!strcmp(func->name, func_name))
85 return func;
86
87 func++;
88 }
89 }
90 }
91
92 return NULL;
93 }
94
95 static struct sunxi_desc_function *
96 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
97 const u16 pin_num,
98 const char *func_name)
99 {
100 int i;
101
102 for (i = 0; i < pctl->desc->npins; i++) {
103 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
104
105 if (pin->pin.number == pin_num) {
106 struct sunxi_desc_function *func = pin->functions;
107
108 while (func->name) {
109 if (!strcmp(func->name, func_name))
110 return func;
111
112 func++;
113 }
114 }
115 }
116
117 return NULL;
118 }
119
120 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
121 {
122 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
123
124 return pctl->ngroups;
125 }
126
127 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
128 unsigned group)
129 {
130 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
131
132 return pctl->groups[group].name;
133 }
134
135 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
136 unsigned group,
137 const unsigned **pins,
138 unsigned *num_pins)
139 {
140 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
141
142 *pins = (unsigned *)&pctl->groups[group].pin;
143 *num_pins = 1;
144
145 return 0;
146 }
147
148 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
149 struct device_node *node,
150 struct pinctrl_map **map,
151 unsigned *num_maps)
152 {
153 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
154 unsigned long *pinconfig;
155 struct property *prop;
156 const char *function;
157 const char *group;
158 int ret, nmaps, i = 0;
159 u32 val;
160
161 *map = NULL;
162 *num_maps = 0;
163
164 ret = of_property_read_string(node, "allwinner,function", &function);
165 if (ret) {
166 dev_err(pctl->dev,
167 "missing allwinner,function property in node %s\n",
168 node->name);
169 return -EINVAL;
170 }
171
172 nmaps = of_property_count_strings(node, "allwinner,pins") * 2;
173 if (nmaps < 0) {
174 dev_err(pctl->dev,
175 "missing allwinner,pins property in node %s\n",
176 node->name);
177 return -EINVAL;
178 }
179
180 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
181 if (!*map)
182 return -ENOMEM;
183
184 of_property_for_each_string(node, "allwinner,pins", prop, group) {
185 struct sunxi_pinctrl_group *grp =
186 sunxi_pinctrl_find_group_by_name(pctl, group);
187 int j = 0, configlen = 0;
188
189 if (!grp) {
190 dev_err(pctl->dev, "unknown pin %s", group);
191 continue;
192 }
193
194 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
195 grp->name,
196 function)) {
197 dev_err(pctl->dev, "unsupported function %s on pin %s",
198 function, group);
199 continue;
200 }
201
202 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
203 (*map)[i].data.mux.group = group;
204 (*map)[i].data.mux.function = function;
205
206 i++;
207
208 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
209 (*map)[i].data.configs.group_or_pin = group;
210
211 if (of_find_property(node, "allwinner,drive", NULL))
212 configlen++;
213 if (of_find_property(node, "allwinner,pull", NULL))
214 configlen++;
215
216 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
217
218 if (!of_property_read_u32(node, "allwinner,drive", &val)) {
219 u16 strength = (val + 1) * 10;
220 pinconfig[j++] =
221 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
222 strength);
223 }
224
225 if (!of_property_read_u32(node, "allwinner,pull", &val)) {
226 enum pin_config_param pull = PIN_CONFIG_END;
227 if (val == 1)
228 pull = PIN_CONFIG_BIAS_PULL_UP;
229 else if (val == 2)
230 pull = PIN_CONFIG_BIAS_PULL_DOWN;
231 pinconfig[j++] = pinconf_to_config_packed(pull, 0);
232 }
233
234 (*map)[i].data.configs.configs = pinconfig;
235 (*map)[i].data.configs.num_configs = configlen;
236
237 i++;
238 }
239
240 *num_maps = nmaps;
241
242 return 0;
243 }
244
245 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
246 struct pinctrl_map *map,
247 unsigned num_maps)
248 {
249 int i;
250
251 for (i = 0; i < num_maps; i++) {
252 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
253 kfree(map[i].data.configs.configs);
254 }
255
256 kfree(map);
257 }
258
259 static const struct pinctrl_ops sunxi_pctrl_ops = {
260 .dt_node_to_map = sunxi_pctrl_dt_node_to_map,
261 .dt_free_map = sunxi_pctrl_dt_free_map,
262 .get_groups_count = sunxi_pctrl_get_groups_count,
263 .get_group_name = sunxi_pctrl_get_group_name,
264 .get_group_pins = sunxi_pctrl_get_group_pins,
265 };
266
267 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
268 unsigned group,
269 unsigned long *config)
270 {
271 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
272
273 *config = pctl->groups[group].config;
274
275 return 0;
276 }
277
278 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
279 unsigned group,
280 unsigned long *configs,
281 unsigned num_configs)
282 {
283 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
284 struct sunxi_pinctrl_group *g = &pctl->groups[group];
285 unsigned long flags;
286 unsigned pin = g->pin - pctl->desc->pin_base;
287 u32 val, mask;
288 u16 strength;
289 u8 dlevel;
290 int i;
291
292 spin_lock_irqsave(&pctl->lock, flags);
293
294 for (i = 0; i < num_configs; i++) {
295 switch (pinconf_to_config_param(configs[i])) {
296 case PIN_CONFIG_DRIVE_STRENGTH:
297 strength = pinconf_to_config_argument(configs[i]);
298 if (strength > 40) {
299 spin_unlock_irqrestore(&pctl->lock, flags);
300 return -EINVAL;
301 }
302 /*
303 * We convert from mA to what the register expects:
304 * 0: 10mA
305 * 1: 20mA
306 * 2: 30mA
307 * 3: 40mA
308 */
309 dlevel = strength / 10 - 1;
310 val = readl(pctl->membase + sunxi_dlevel_reg(pin));
311 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin);
312 writel((val & ~mask)
313 | dlevel << sunxi_dlevel_offset(pin),
314 pctl->membase + sunxi_dlevel_reg(pin));
315 break;
316 case PIN_CONFIG_BIAS_PULL_UP:
317 val = readl(pctl->membase + sunxi_pull_reg(pin));
318 mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
319 writel((val & ~mask) | 1 << sunxi_pull_offset(pin),
320 pctl->membase + sunxi_pull_reg(pin));
321 break;
322 case PIN_CONFIG_BIAS_PULL_DOWN:
323 val = readl(pctl->membase + sunxi_pull_reg(pin));
324 mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
325 writel((val & ~mask) | 2 << sunxi_pull_offset(pin),
326 pctl->membase + sunxi_pull_reg(pin));
327 break;
328 default:
329 break;
330 }
331 /* cache the config value */
332 g->config = configs[i];
333 } /* for each config */
334
335 spin_unlock_irqrestore(&pctl->lock, flags);
336
337 return 0;
338 }
339
340 static const struct pinconf_ops sunxi_pconf_ops = {
341 .pin_config_group_get = sunxi_pconf_group_get,
342 .pin_config_group_set = sunxi_pconf_group_set,
343 };
344
345 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
346 {
347 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
348
349 return pctl->nfunctions;
350 }
351
352 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
353 unsigned function)
354 {
355 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
356
357 return pctl->functions[function].name;
358 }
359
360 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
361 unsigned function,
362 const char * const **groups,
363 unsigned * const num_groups)
364 {
365 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
366
367 *groups = pctl->functions[function].groups;
368 *num_groups = pctl->functions[function].ngroups;
369
370 return 0;
371 }
372
373 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
374 unsigned pin,
375 u8 config)
376 {
377 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
378 unsigned long flags;
379 u32 val, mask;
380
381 spin_lock_irqsave(&pctl->lock, flags);
382
383 pin -= pctl->desc->pin_base;
384 val = readl(pctl->membase + sunxi_mux_reg(pin));
385 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
386 writel((val & ~mask) | config << sunxi_mux_offset(pin),
387 pctl->membase + sunxi_mux_reg(pin));
388
389 spin_unlock_irqrestore(&pctl->lock, flags);
390 }
391
392 static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,
393 unsigned function,
394 unsigned group)
395 {
396 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
397 struct sunxi_pinctrl_group *g = pctl->groups + group;
398 struct sunxi_pinctrl_function *func = pctl->functions + function;
399 struct sunxi_desc_function *desc =
400 sunxi_pinctrl_desc_find_function_by_name(pctl,
401 g->name,
402 func->name);
403
404 if (!desc)
405 return -EINVAL;
406
407 sunxi_pmx_set(pctldev, g->pin, desc->muxval);
408
409 return 0;
410 }
411
412 static int
413 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
414 struct pinctrl_gpio_range *range,
415 unsigned offset,
416 bool input)
417 {
418 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
419 struct sunxi_desc_function *desc;
420 const char *func;
421
422 if (input)
423 func = "gpio_in";
424 else
425 func = "gpio_out";
426
427 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
428 if (!desc)
429 return -EINVAL;
430
431 sunxi_pmx_set(pctldev, offset, desc->muxval);
432
433 return 0;
434 }
435
436 static const struct pinmux_ops sunxi_pmx_ops = {
437 .get_functions_count = sunxi_pmx_get_funcs_cnt,
438 .get_function_name = sunxi_pmx_get_func_name,
439 .get_function_groups = sunxi_pmx_get_func_groups,
440 .enable = sunxi_pmx_enable,
441 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
442 };
443
444 static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset)
445 {
446 return pinctrl_request_gpio(chip->base + offset);
447 }
448
449 static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset)
450 {
451 pinctrl_free_gpio(chip->base + offset);
452 }
453
454 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
455 unsigned offset)
456 {
457 return pinctrl_gpio_direction_input(chip->base + offset);
458 }
459
460 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
461 {
462 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
463
464 u32 reg = sunxi_data_reg(offset);
465 u8 index = sunxi_data_offset(offset);
466 u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
467
468 return val;
469 }
470
471 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
472 unsigned offset, int value)
473 {
474 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
475 u32 reg = sunxi_data_reg(offset);
476 u8 index = sunxi_data_offset(offset);
477 unsigned long flags;
478 u32 regval;
479
480 spin_lock_irqsave(&pctl->lock, flags);
481
482 regval = readl(pctl->membase + reg);
483
484 if (value)
485 regval |= BIT(index);
486 else
487 regval &= ~(BIT(index));
488
489 writel(regval, pctl->membase + reg);
490
491 spin_unlock_irqrestore(&pctl->lock, flags);
492 }
493
494 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
495 unsigned offset, int value)
496 {
497 sunxi_pinctrl_gpio_set(chip, offset, value);
498 return pinctrl_gpio_direction_output(chip->base + offset);
499 }
500
501 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
502 const struct of_phandle_args *gpiospec,
503 u32 *flags)
504 {
505 int pin, base;
506
507 base = PINS_PER_BANK * gpiospec->args[0];
508 pin = base + gpiospec->args[1];
509
510 if (pin > (gc->base + gc->ngpio))
511 return -EINVAL;
512
513 if (flags)
514 *flags = gpiospec->args[2];
515
516 return pin;
517 }
518
519 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
520 {
521 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
522 struct sunxi_desc_function *desc;
523 unsigned irqnum;
524
525 if (offset >= chip->ngpio)
526 return -ENXIO;
527
528 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq");
529 if (!desc)
530 return -EINVAL;
531
532 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
533
534 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
535 chip->label, offset + chip->base, irqnum);
536
537 return irq_find_mapping(pctl->domain, irqnum);
538 }
539
540 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
541 {
542 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
543 struct sunxi_desc_function *func;
544 int ret;
545
546 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
547 pctl->irq_array[d->hwirq], "irq");
548 if (!func)
549 return -EINVAL;
550
551 ret = gpio_lock_as_irq(pctl->chip, pctl->irq_array[d->hwirq]);
552 if (ret) {
553 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
554 irqd_to_hwirq(d));
555 return ret;
556 }
557
558 /* Change muxing to INT mode */
559 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
560
561 return 0;
562 }
563
564 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
565 {
566 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
567
568 gpio_unlock_as_irq(pctl->chip, pctl->irq_array[d->hwirq]);
569 }
570
571 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
572 {
573 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
574 struct irq_desc *desc = container_of(d, struct irq_desc, irq_data);
575 u32 reg = sunxi_irq_cfg_reg(d->hwirq);
576 u8 index = sunxi_irq_cfg_offset(d->hwirq);
577 unsigned long flags;
578 u32 regval;
579 u8 mode;
580
581 switch (type) {
582 case IRQ_TYPE_EDGE_RISING:
583 mode = IRQ_EDGE_RISING;
584 break;
585 case IRQ_TYPE_EDGE_FALLING:
586 mode = IRQ_EDGE_FALLING;
587 break;
588 case IRQ_TYPE_EDGE_BOTH:
589 mode = IRQ_EDGE_BOTH;
590 break;
591 case IRQ_TYPE_LEVEL_HIGH:
592 mode = IRQ_LEVEL_HIGH;
593 break;
594 case IRQ_TYPE_LEVEL_LOW:
595 mode = IRQ_LEVEL_LOW;
596 break;
597 default:
598 return -EINVAL;
599 }
600
601 if (type & IRQ_TYPE_LEVEL_MASK) {
602 d->chip = &sunxi_pinctrl_level_irq_chip;
603 desc->handle_irq = handle_fasteoi_irq;
604 } else {
605 d->chip = &sunxi_pinctrl_edge_irq_chip;
606 desc->handle_irq = handle_edge_irq;
607 }
608
609 spin_lock_irqsave(&pctl->lock, flags);
610
611 regval = readl(pctl->membase + reg);
612 regval &= ~(IRQ_CFG_IRQ_MASK << index);
613 writel(regval | (mode << index), pctl->membase + reg);
614
615 spin_unlock_irqrestore(&pctl->lock, flags);
616
617 return 0;
618 }
619
620 static void sunxi_pinctrl_irq_ack(struct irq_data *d)
621 {
622 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
623 u32 status_reg = sunxi_irq_status_reg(d->hwirq);
624 u8 status_idx = sunxi_irq_status_offset(d->hwirq);
625
626 /* Clear the IRQ */
627 writel(1 << status_idx, pctl->membase + status_reg);
628 }
629
630 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
631 {
632 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
633 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
634 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
635 unsigned long flags;
636 u32 val;
637
638 spin_lock_irqsave(&pctl->lock, flags);
639
640 /* Mask the IRQ */
641 val = readl(pctl->membase + reg);
642 writel(val & ~(1 << idx), pctl->membase + reg);
643
644 spin_unlock_irqrestore(&pctl->lock, flags);
645 }
646
647 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
648 {
649 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
650 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
651 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
652 unsigned long flags;
653 u32 val;
654
655 spin_lock_irqsave(&pctl->lock, flags);
656
657 /* Unmask the IRQ */
658 val = readl(pctl->membase + reg);
659 writel(val | (1 << idx), pctl->membase + reg);
660
661 spin_unlock_irqrestore(&pctl->lock, flags);
662 }
663
664 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
665 {
666 sunxi_pinctrl_irq_ack(d);
667 sunxi_pinctrl_irq_unmask(d);
668 }
669
670 static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
671 .irq_ack = sunxi_pinctrl_irq_ack,
672 .irq_mask = sunxi_pinctrl_irq_mask,
673 .irq_unmask = sunxi_pinctrl_irq_unmask,
674 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
675 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
676 .irq_set_type = sunxi_pinctrl_irq_set_type,
677 .flags = IRQCHIP_SKIP_SET_WAKE,
678 };
679
680 static struct irq_chip sunxi_pinctrl_level_irq_chip = {
681 .irq_eoi = sunxi_pinctrl_irq_ack,
682 .irq_mask = sunxi_pinctrl_irq_mask,
683 .irq_unmask = sunxi_pinctrl_irq_unmask,
684 /* Define irq_enable / disable to avoid spurious irqs for drivers
685 * using these to suppress irqs while they clear the irq source */
686 .irq_enable = sunxi_pinctrl_irq_ack_unmask,
687 .irq_disable = sunxi_pinctrl_irq_mask,
688 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
689 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
690 .irq_set_type = sunxi_pinctrl_irq_set_type,
691 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED |
692 IRQCHIP_EOI_IF_HANDLED,
693 };
694
695 static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
696 {
697 struct irq_chip *chip = irq_get_chip(irq);
698 struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
699 unsigned long bank, reg, val;
700
701 for (bank = 0; bank < pctl->desc->irq_banks; bank++)
702 if (irq == pctl->irq[bank])
703 break;
704
705 if (bank == pctl->desc->irq_banks)
706 return;
707
708 reg = sunxi_irq_status_reg_from_bank(bank);
709 val = readl(pctl->membase + reg);
710
711 if (val) {
712 int irqoffset;
713
714 chained_irq_enter(chip, desc);
715 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
716 int pin_irq = irq_find_mapping(pctl->domain,
717 bank * IRQ_PER_BANK + irqoffset);
718 generic_handle_irq(pin_irq);
719 }
720 chained_irq_exit(chip, desc);
721 }
722 }
723
724 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
725 const char *name)
726 {
727 struct sunxi_pinctrl_function *func = pctl->functions;
728
729 while (func->name) {
730 /* function already there */
731 if (strcmp(func->name, name) == 0) {
732 func->ngroups++;
733 return -EEXIST;
734 }
735 func++;
736 }
737
738 func->name = name;
739 func->ngroups = 1;
740
741 pctl->nfunctions++;
742
743 return 0;
744 }
745
746 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
747 {
748 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
749 int i;
750
751 pctl->ngroups = pctl->desc->npins;
752
753 /* Allocate groups */
754 pctl->groups = devm_kzalloc(&pdev->dev,
755 pctl->ngroups * sizeof(*pctl->groups),
756 GFP_KERNEL);
757 if (!pctl->groups)
758 return -ENOMEM;
759
760 for (i = 0; i < pctl->desc->npins; i++) {
761 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
762 struct sunxi_pinctrl_group *group = pctl->groups + i;
763
764 group->name = pin->pin.name;
765 group->pin = pin->pin.number;
766 }
767
768 /*
769 * We suppose that we won't have any more functions than pins,
770 * we'll reallocate that later anyway
771 */
772 pctl->functions = devm_kzalloc(&pdev->dev,
773 pctl->desc->npins * sizeof(*pctl->functions),
774 GFP_KERNEL);
775 if (!pctl->functions)
776 return -ENOMEM;
777
778 /* Count functions and their associated groups */
779 for (i = 0; i < pctl->desc->npins; i++) {
780 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
781 struct sunxi_desc_function *func = pin->functions;
782
783 while (func->name) {
784 /* Create interrupt mapping while we're at it */
785 if (!strcmp(func->name, "irq")) {
786 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
787 pctl->irq_array[irqnum] = pin->pin.number;
788 }
789
790 sunxi_pinctrl_add_function(pctl, func->name);
791 func++;
792 }
793 }
794
795 pctl->functions = krealloc(pctl->functions,
796 pctl->nfunctions * sizeof(*pctl->functions),
797 GFP_KERNEL);
798
799 for (i = 0; i < pctl->desc->npins; i++) {
800 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
801 struct sunxi_desc_function *func = pin->functions;
802
803 while (func->name) {
804 struct sunxi_pinctrl_function *func_item;
805 const char **func_grp;
806
807 func_item = sunxi_pinctrl_find_function_by_name(pctl,
808 func->name);
809 if (!func_item)
810 return -EINVAL;
811
812 if (!func_item->groups) {
813 func_item->groups =
814 devm_kzalloc(&pdev->dev,
815 func_item->ngroups * sizeof(*func_item->groups),
816 GFP_KERNEL);
817 if (!func_item->groups)
818 return -ENOMEM;
819 }
820
821 func_grp = func_item->groups;
822 while (*func_grp)
823 func_grp++;
824
825 *func_grp = pin->pin.name;
826 func++;
827 }
828 }
829
830 return 0;
831 }
832
833 int sunxi_pinctrl_init(struct platform_device *pdev,
834 const struct sunxi_pinctrl_desc *desc)
835 {
836 struct device_node *node = pdev->dev.of_node;
837 struct pinctrl_desc *pctrl_desc;
838 struct pinctrl_pin_desc *pins;
839 struct sunxi_pinctrl *pctl;
840 struct resource *res;
841 int i, ret, last_pin;
842 struct clk *clk;
843
844 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
845 if (!pctl)
846 return -ENOMEM;
847 platform_set_drvdata(pdev, pctl);
848
849 spin_lock_init(&pctl->lock);
850
851 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
852 pctl->membase = devm_ioremap_resource(&pdev->dev, res);
853 if (IS_ERR(pctl->membase))
854 return PTR_ERR(pctl->membase);
855
856 pctl->dev = &pdev->dev;
857 pctl->desc = desc;
858
859 pctl->irq_array = devm_kcalloc(&pdev->dev,
860 IRQ_PER_BANK * pctl->desc->irq_banks,
861 sizeof(*pctl->irq_array),
862 GFP_KERNEL);
863 if (!pctl->irq_array)
864 return -ENOMEM;
865
866 ret = sunxi_pinctrl_build_state(pdev);
867 if (ret) {
868 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
869 return ret;
870 }
871
872 pins = devm_kzalloc(&pdev->dev,
873 pctl->desc->npins * sizeof(*pins),
874 GFP_KERNEL);
875 if (!pins)
876 return -ENOMEM;
877
878 for (i = 0; i < pctl->desc->npins; i++)
879 pins[i] = pctl->desc->pins[i].pin;
880
881 pctrl_desc = devm_kzalloc(&pdev->dev,
882 sizeof(*pctrl_desc),
883 GFP_KERNEL);
884 if (!pctrl_desc)
885 return -ENOMEM;
886
887 pctrl_desc->name = dev_name(&pdev->dev);
888 pctrl_desc->owner = THIS_MODULE;
889 pctrl_desc->pins = pins;
890 pctrl_desc->npins = pctl->desc->npins;
891 pctrl_desc->confops = &sunxi_pconf_ops;
892 pctrl_desc->pctlops = &sunxi_pctrl_ops;
893 pctrl_desc->pmxops = &sunxi_pmx_ops;
894
895 pctl->pctl_dev = pinctrl_register(pctrl_desc,
896 &pdev->dev, pctl);
897 if (!pctl->pctl_dev) {
898 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
899 return -EINVAL;
900 }
901
902 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
903 if (!pctl->chip) {
904 ret = -ENOMEM;
905 goto pinctrl_error;
906 }
907
908 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
909 pctl->chip->owner = THIS_MODULE;
910 pctl->chip->request = sunxi_pinctrl_gpio_request,
911 pctl->chip->free = sunxi_pinctrl_gpio_free,
912 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input,
913 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output,
914 pctl->chip->get = sunxi_pinctrl_gpio_get,
915 pctl->chip->set = sunxi_pinctrl_gpio_set,
916 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate,
917 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq,
918 pctl->chip->of_gpio_n_cells = 3,
919 pctl->chip->can_sleep = false,
920 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
921 pctl->desc->pin_base;
922 pctl->chip->label = dev_name(&pdev->dev);
923 pctl->chip->dev = &pdev->dev;
924 pctl->chip->base = pctl->desc->pin_base;
925
926 ret = gpiochip_add(pctl->chip);
927 if (ret)
928 goto pinctrl_error;
929
930 for (i = 0; i < pctl->desc->npins; i++) {
931 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
932
933 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
934 pin->pin.number,
935 pin->pin.number, 1);
936 if (ret)
937 goto gpiochip_error;
938 }
939
940 clk = devm_clk_get(&pdev->dev, NULL);
941 if (IS_ERR(clk)) {
942 ret = PTR_ERR(clk);
943 goto gpiochip_error;
944 }
945
946 ret = clk_prepare_enable(clk);
947 if (ret)
948 goto gpiochip_error;
949
950 pctl->irq = devm_kcalloc(&pdev->dev,
951 pctl->desc->irq_banks,
952 sizeof(*pctl->irq),
953 GFP_KERNEL);
954 if (!pctl->irq) {
955 ret = -ENOMEM;
956 goto clk_error;
957 }
958
959 for (i = 0; i < pctl->desc->irq_banks; i++) {
960 pctl->irq[i] = platform_get_irq(pdev, i);
961 if (pctl->irq[i] < 0) {
962 ret = pctl->irq[i];
963 goto clk_error;
964 }
965 }
966
967 pctl->domain = irq_domain_add_linear(node,
968 pctl->desc->irq_banks * IRQ_PER_BANK,
969 &irq_domain_simple_ops,
970 NULL);
971 if (!pctl->domain) {
972 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
973 ret = -ENOMEM;
974 goto clk_error;
975 }
976
977 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
978 int irqno = irq_create_mapping(pctl->domain, i);
979
980 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
981 handle_edge_irq);
982 irq_set_chip_data(irqno, pctl);
983 };
984
985 for (i = 0; i < pctl->desc->irq_banks; i++) {
986 /* Mask and clear all IRQs before registering a handler */
987 writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i));
988 writel(0xffffffff,
989 pctl->membase + sunxi_irq_status_reg_from_bank(i));
990
991 irq_set_chained_handler(pctl->irq[i],
992 sunxi_pinctrl_irq_handler);
993 irq_set_handler_data(pctl->irq[i], pctl);
994 }
995
996 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
997
998 return 0;
999
1000 clk_error:
1001 clk_disable_unprepare(clk);
1002 gpiochip_error:
1003 gpiochip_remove(pctl->chip);
1004 pinctrl_error:
1005 pinctrl_unregister(pctl->pctl_dev);
1006 return ret;
1007 }
Linux kernel - Deliverables
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