drivers/pinctrl/sunxi/pinctrl-sunxi.h

   1 /*
   2  * Allwinner A1X SoCs pinctrl driver.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #ifndef __PINCTRL_SUNXI_H
  14 #define __PINCTRL_SUNXI_H
  15
  16 #include <linux/kernel.h>
  17 #include <linux/spinlock.h>
  18
  19 #define PA_BASE 0
  20 #define PB_BASE 32
  21 #define PC_BASE 64
  22 #define PD_BASE 96
  23 #define PE_BASE 128
  24 #define PF_BASE 160
  25 #define PG_BASE 192
  26 #define PH_BASE 224
  27 #define PI_BASE 256
  28 #define PL_BASE 352
  29 #define PM_BASE 384
  30
  31 #define SUNXI_PINCTRL_PIN_PA0   PINCTRL_PIN(PA_BASE + 0, "PA0")
  32 #define SUNXI_PINCTRL_PIN_PA1   PINCTRL_PIN(PA_BASE + 1, "PA1")
  33 #define SUNXI_PINCTRL_PIN_PA2   PINCTRL_PIN(PA_BASE + 2, "PA2")
  34 #define SUNXI_PINCTRL_PIN_PA3   PINCTRL_PIN(PA_BASE + 3, "PA3")
  35 #define SUNXI_PINCTRL_PIN_PA4   PINCTRL_PIN(PA_BASE + 4, "PA4")
  36 #define SUNXI_PINCTRL_PIN_PA5   PINCTRL_PIN(PA_BASE + 5, "PA5")
  37 #define SUNXI_PINCTRL_PIN_PA6   PINCTRL_PIN(PA_BASE + 6, "PA6")
  38 #define SUNXI_PINCTRL_PIN_PA7   PINCTRL_PIN(PA_BASE + 7, "PA7")
  39 #define SUNXI_PINCTRL_PIN_PA8   PINCTRL_PIN(PA_BASE + 8, "PA8")
  40 #define SUNXI_PINCTRL_PIN_PA9   PINCTRL_PIN(PA_BASE + 9, "PA9")
  41 #define SUNXI_PINCTRL_PIN_PA10  PINCTRL_PIN(PA_BASE + 10, "PA10")
  42 #define SUNXI_PINCTRL_PIN_PA11  PINCTRL_PIN(PA_BASE + 11, "PA11")
  43 #define SUNXI_PINCTRL_PIN_PA12  PINCTRL_PIN(PA_BASE + 12, "PA12")
  44 #define SUNXI_PINCTRL_PIN_PA13  PINCTRL_PIN(PA_BASE + 13, "PA13")
  45 #define SUNXI_PINCTRL_PIN_PA14  PINCTRL_PIN(PA_BASE + 14, "PA14")
  46 #define SUNXI_PINCTRL_PIN_PA15  PINCTRL_PIN(PA_BASE + 15, "PA15")
  47 #define SUNXI_PINCTRL_PIN_PA16  PINCTRL_PIN(PA_BASE + 16, "PA16")
  48 #define SUNXI_PINCTRL_PIN_PA17  PINCTRL_PIN(PA_BASE + 17, "PA17")
  49 #define SUNXI_PINCTRL_PIN_PA18  PINCTRL_PIN(PA_BASE + 18, "PA18")
  50 #define SUNXI_PINCTRL_PIN_PA19  PINCTRL_PIN(PA_BASE + 19, "PA19")
  51 #define SUNXI_PINCTRL_PIN_PA20  PINCTRL_PIN(PA_BASE + 20, "PA20")
  52 #define SUNXI_PINCTRL_PIN_PA21  PINCTRL_PIN(PA_BASE + 21, "PA21")
  53 #define SUNXI_PINCTRL_PIN_PA22  PINCTRL_PIN(PA_BASE + 22, "PA22")
  54 #define SUNXI_PINCTRL_PIN_PA23  PINCTRL_PIN(PA_BASE + 23, "PA23")
  55 #define SUNXI_PINCTRL_PIN_PA24  PINCTRL_PIN(PA_BASE + 24, "PA24")
  56 #define SUNXI_PINCTRL_PIN_PA25  PINCTRL_PIN(PA_BASE + 25, "PA25")
  57 #define SUNXI_PINCTRL_PIN_PA26  PINCTRL_PIN(PA_BASE + 26, "PA26")
  58 #define SUNXI_PINCTRL_PIN_PA27  PINCTRL_PIN(PA_BASE + 27, "PA27")
  59 #define SUNXI_PINCTRL_PIN_PA28  PINCTRL_PIN(PA_BASE + 28, "PA28")
  60 #define SUNXI_PINCTRL_PIN_PA29  PINCTRL_PIN(PA_BASE + 29, "PA29")
  61 #define SUNXI_PINCTRL_PIN_PA30  PINCTRL_PIN(PA_BASE + 30, "PA30")
  62 #define SUNXI_PINCTRL_PIN_PA31  PINCTRL_PIN(PA_BASE + 31, "PA31")
  63
  64 #define SUNXI_PINCTRL_PIN_PB0   PINCTRL_PIN(PB_BASE + 0, "PB0")
  65 #define SUNXI_PINCTRL_PIN_PB1   PINCTRL_PIN(PB_BASE + 1, "PB1")
  66 #define SUNXI_PINCTRL_PIN_PB2   PINCTRL_PIN(PB_BASE + 2, "PB2")
  67 #define SUNXI_PINCTRL_PIN_PB3   PINCTRL_PIN(PB_BASE + 3, "PB3")
  68 #define SUNXI_PINCTRL_PIN_PB4   PINCTRL_PIN(PB_BASE + 4, "PB4")
  69 #define SUNXI_PINCTRL_PIN_PB5   PINCTRL_PIN(PB_BASE + 5, "PB5")
  70 #define SUNXI_PINCTRL_PIN_PB6   PINCTRL_PIN(PB_BASE + 6, "PB6")
  71 #define SUNXI_PINCTRL_PIN_PB7   PINCTRL_PIN(PB_BASE + 7, "PB7")
  72 #define SUNXI_PINCTRL_PIN_PB8   PINCTRL_PIN(PB_BASE + 8, "PB8")
  73 #define SUNXI_PINCTRL_PIN_PB9   PINCTRL_PIN(PB_BASE + 9, "PB9")
  74 #define SUNXI_PINCTRL_PIN_PB10  PINCTRL_PIN(PB_BASE + 10, "PB10")
  75 #define SUNXI_PINCTRL_PIN_PB11  PINCTRL_PIN(PB_BASE + 11, "PB11")
  76 #define SUNXI_PINCTRL_PIN_PB12  PINCTRL_PIN(PB_BASE + 12, "PB12")
  77 #define SUNXI_PINCTRL_PIN_PB13  PINCTRL_PIN(PB_BASE + 13, "PB13")
  78 #define SUNXI_PINCTRL_PIN_PB14  PINCTRL_PIN(PB_BASE + 14, "PB14")
  79 #define SUNXI_PINCTRL_PIN_PB15  PINCTRL_PIN(PB_BASE + 15, "PB15")
  80 #define SUNXI_PINCTRL_PIN_PB16  PINCTRL_PIN(PB_BASE + 16, "PB16")
  81 #define SUNXI_PINCTRL_PIN_PB17  PINCTRL_PIN(PB_BASE + 17, "PB17")
  82 #define SUNXI_PINCTRL_PIN_PB18  PINCTRL_PIN(PB_BASE + 18, "PB18")
  83 #define SUNXI_PINCTRL_PIN_PB19  PINCTRL_PIN(PB_BASE + 19, "PB19")
  84 #define SUNXI_PINCTRL_PIN_PB20  PINCTRL_PIN(PB_BASE + 20, "PB20")
  85 #define SUNXI_PINCTRL_PIN_PB21  PINCTRL_PIN(PB_BASE + 21, "PB21")
  86 #define SUNXI_PINCTRL_PIN_PB22  PINCTRL_PIN(PB_BASE + 22, "PB22")
  87 #define SUNXI_PINCTRL_PIN_PB23  PINCTRL_PIN(PB_BASE + 23, "PB23")
  88 #define SUNXI_PINCTRL_PIN_PB24  PINCTRL_PIN(PB_BASE + 24, "PB24")
  89 #define SUNXI_PINCTRL_PIN_PB25  PINCTRL_PIN(PB_BASE + 25, "PB25")
  90 #define SUNXI_PINCTRL_PIN_PB26  PINCTRL_PIN(PB_BASE + 26, "PB26")
  91 #define SUNXI_PINCTRL_PIN_PB27  PINCTRL_PIN(PB_BASE + 27, "PB27")
  92 #define SUNXI_PINCTRL_PIN_PB28  PINCTRL_PIN(PB_BASE + 28, "PB28")
  93 #define SUNXI_PINCTRL_PIN_PB29  PINCTRL_PIN(PB_BASE + 29, "PB29")
  94 #define SUNXI_PINCTRL_PIN_PB30  PINCTRL_PIN(PB_BASE + 30, "PB30")
  95 #define SUNXI_PINCTRL_PIN_PB31  PINCTRL_PIN(PB_BASE + 31, "PB31")
  96
  97 #define SUNXI_PINCTRL_PIN_PC0   PINCTRL_PIN(PC_BASE + 0, "PC0")
  98 #define SUNXI_PINCTRL_PIN_PC1   PINCTRL_PIN(PC_BASE + 1, "PC1")
  99 #define SUNXI_PINCTRL_PIN_PC2   PINCTRL_PIN(PC_BASE + 2, "PC2")
 100 #define SUNXI_PINCTRL_PIN_PC3   PINCTRL_PIN(PC_BASE + 3, "PC3")
 101 #define SUNXI_PINCTRL_PIN_PC4   PINCTRL_PIN(PC_BASE + 4, "PC4")
 102 #define SUNXI_PINCTRL_PIN_PC5   PINCTRL_PIN(PC_BASE + 5, "PC5")
 103 #define SUNXI_PINCTRL_PIN_PC6   PINCTRL_PIN(PC_BASE + 6, "PC6")
 104 #define SUNXI_PINCTRL_PIN_PC7   PINCTRL_PIN(PC_BASE + 7, "PC7")
 105 #define SUNXI_PINCTRL_PIN_PC8   PINCTRL_PIN(PC_BASE + 8, "PC8")
 106 #define SUNXI_PINCTRL_PIN_PC9   PINCTRL_PIN(PC_BASE + 9, "PC9")
 107 #define SUNXI_PINCTRL_PIN_PC10  PINCTRL_PIN(PC_BASE + 10, "PC10")
 108 #define SUNXI_PINCTRL_PIN_PC11  PINCTRL_PIN(PC_BASE + 11, "PC11")
 109 #define SUNXI_PINCTRL_PIN_PC12  PINCTRL_PIN(PC_BASE + 12, "PC12")
 110 #define SUNXI_PINCTRL_PIN_PC13  PINCTRL_PIN(PC_BASE + 13, "PC13")
 111 #define SUNXI_PINCTRL_PIN_PC14  PINCTRL_PIN(PC_BASE + 14, "PC14")
 112 #define SUNXI_PINCTRL_PIN_PC15  PINCTRL_PIN(PC_BASE + 15, "PC15")
 113 #define SUNXI_PINCTRL_PIN_PC16  PINCTRL_PIN(PC_BASE + 16, "PC16")
 114 #define SUNXI_PINCTRL_PIN_PC17  PINCTRL_PIN(PC_BASE + 17, "PC17")
 115 #define SUNXI_PINCTRL_PIN_PC18  PINCTRL_PIN(PC_BASE + 18, "PC18")
 116 #define SUNXI_PINCTRL_PIN_PC19  PINCTRL_PIN(PC_BASE + 19, "PC19")
 117 #define SUNXI_PINCTRL_PIN_PC20  PINCTRL_PIN(PC_BASE + 20, "PC20")
 118 #define SUNXI_PINCTRL_PIN_PC21  PINCTRL_PIN(PC_BASE + 21, "PC21")
 119 #define SUNXI_PINCTRL_PIN_PC22  PINCTRL_PIN(PC_BASE + 22, "PC22")
 120 #define SUNXI_PINCTRL_PIN_PC23  PINCTRL_PIN(PC_BASE + 23, "PC23")
 121 #define SUNXI_PINCTRL_PIN_PC24  PINCTRL_PIN(PC_BASE + 24, "PC24")
 122 #define SUNXI_PINCTRL_PIN_PC25  PINCTRL_PIN(PC_BASE + 25, "PC25")
 123 #define SUNXI_PINCTRL_PIN_PC26  PINCTRL_PIN(PC_BASE + 26, "PC26")
 124 #define SUNXI_PINCTRL_PIN_PC27  PINCTRL_PIN(PC_BASE + 27, "PC27")
 125 #define SUNXI_PINCTRL_PIN_PC28  PINCTRL_PIN(PC_BASE + 28, "PC28")
 126 #define SUNXI_PINCTRL_PIN_PC29  PINCTRL_PIN(PC_BASE + 29, "PC29")
 127 #define SUNXI_PINCTRL_PIN_PC30  PINCTRL_PIN(PC_BASE + 30, "PC30")
 128 #define SUNXI_PINCTRL_PIN_PC31  PINCTRL_PIN(PC_BASE + 31, "PC31")
 129
 130 #define SUNXI_PINCTRL_PIN_PD0   PINCTRL_PIN(PD_BASE + 0, "PD0")
 131 #define SUNXI_PINCTRL_PIN_PD1   PINCTRL_PIN(PD_BASE + 1, "PD1")
 132 #define SUNXI_PINCTRL_PIN_PD2   PINCTRL_PIN(PD_BASE + 2, "PD2")
 133 #define SUNXI_PINCTRL_PIN_PD3   PINCTRL_PIN(PD_BASE + 3, "PD3")
 134 #define SUNXI_PINCTRL_PIN_PD4   PINCTRL_PIN(PD_BASE + 4, "PD4")
 135 #define SUNXI_PINCTRL_PIN_PD5   PINCTRL_PIN(PD_BASE + 5, "PD5")
 136 #define SUNXI_PINCTRL_PIN_PD6   PINCTRL_PIN(PD_BASE + 6, "PD6")
 137 #define SUNXI_PINCTRL_PIN_PD7   PINCTRL_PIN(PD_BASE + 7, "PD7")
 138 #define SUNXI_PINCTRL_PIN_PD8   PINCTRL_PIN(PD_BASE + 8, "PD8")
 139 #define SUNXI_PINCTRL_PIN_PD9   PINCTRL_PIN(PD_BASE + 9, "PD9")
 140 #define SUNXI_PINCTRL_PIN_PD10  PINCTRL_PIN(PD_BASE + 10, "PD10")
 141 #define SUNXI_PINCTRL_PIN_PD11  PINCTRL_PIN(PD_BASE + 11, "PD11")
 142 #define SUNXI_PINCTRL_PIN_PD12  PINCTRL_PIN(PD_BASE + 12, "PD12")
 143 #define SUNXI_PINCTRL_PIN_PD13  PINCTRL_PIN(PD_BASE + 13, "PD13")
 144 #define SUNXI_PINCTRL_PIN_PD14  PINCTRL_PIN(PD_BASE + 14, "PD14")
 145 #define SUNXI_PINCTRL_PIN_PD15  PINCTRL_PIN(PD_BASE + 15, "PD15")
 146 #define SUNXI_PINCTRL_PIN_PD16  PINCTRL_PIN(PD_BASE + 16, "PD16")
 147 #define SUNXI_PINCTRL_PIN_PD17  PINCTRL_PIN(PD_BASE + 17, "PD17")
 148 #define SUNXI_PINCTRL_PIN_PD18  PINCTRL_PIN(PD_BASE + 18, "PD18")
 149 #define SUNXI_PINCTRL_PIN_PD19  PINCTRL_PIN(PD_BASE + 19, "PD19")
 150 #define SUNXI_PINCTRL_PIN_PD20  PINCTRL_PIN(PD_BASE + 20, "PD20")
 151 #define SUNXI_PINCTRL_PIN_PD21  PINCTRL_PIN(PD_BASE + 21, "PD21")
 152 #define SUNXI_PINCTRL_PIN_PD22  PINCTRL_PIN(PD_BASE + 22, "PD22")
 153 #define SUNXI_PINCTRL_PIN_PD23  PINCTRL_PIN(PD_BASE + 23, "PD23")
 154 #define SUNXI_PINCTRL_PIN_PD24  PINCTRL_PIN(PD_BASE + 24, "PD24")
 155 #define SUNXI_PINCTRL_PIN_PD25  PINCTRL_PIN(PD_BASE + 25, "PD25")
 156 #define SUNXI_PINCTRL_PIN_PD26  PINCTRL_PIN(PD_BASE + 26, "PD26")
 157 #define SUNXI_PINCTRL_PIN_PD27  PINCTRL_PIN(PD_BASE + 27, "PD27")
 158 #define SUNXI_PINCTRL_PIN_PD28  PINCTRL_PIN(PD_BASE + 28, "PD28")
 159 #define SUNXI_PINCTRL_PIN_PD29  PINCTRL_PIN(PD_BASE + 29, "PD29")
 160 #define SUNXI_PINCTRL_PIN_PD30  PINCTRL_PIN(PD_BASE + 30, "PD30")
 161 #define SUNXI_PINCTRL_PIN_PD31  PINCTRL_PIN(PD_BASE + 31, "PD31")
 162
 163 #define SUNXI_PINCTRL_PIN_PE0   PINCTRL_PIN(PE_BASE + 0, "PE0")
 164 #define SUNXI_PINCTRL_PIN_PE1   PINCTRL_PIN(PE_BASE + 1, "PE1")
 165 #define SUNXI_PINCTRL_PIN_PE2   PINCTRL_PIN(PE_BASE + 2, "PE2")
 166 #define SUNXI_PINCTRL_PIN_PE3   PINCTRL_PIN(PE_BASE + 3, "PE3")
 167 #define SUNXI_PINCTRL_PIN_PE4   PINCTRL_PIN(PE_BASE + 4, "PE4")
 168 #define SUNXI_PINCTRL_PIN_PE5   PINCTRL_PIN(PE_BASE + 5, "PE5")
 169 #define SUNXI_PINCTRL_PIN_PE6   PINCTRL_PIN(PE_BASE + 6, "PE6")
 170 #define SUNXI_PINCTRL_PIN_PE7   PINCTRL_PIN(PE_BASE + 7, "PE7")
 171 #define SUNXI_PINCTRL_PIN_PE8   PINCTRL_PIN(PE_BASE + 8, "PE8")
 172 #define SUNXI_PINCTRL_PIN_PE9   PINCTRL_PIN(PE_BASE + 9, "PE9")
 173 #define SUNXI_PINCTRL_PIN_PE10  PINCTRL_PIN(PE_BASE + 10, "PE10")
 174 #define SUNXI_PINCTRL_PIN_PE11  PINCTRL_PIN(PE_BASE + 11, "PE11")
 175 #define SUNXI_PINCTRL_PIN_PE12  PINCTRL_PIN(PE_BASE + 12, "PE12")
 176 #define SUNXI_PINCTRL_PIN_PE13  PINCTRL_PIN(PE_BASE + 13, "PE13")
 177 #define SUNXI_PINCTRL_PIN_PE14  PINCTRL_PIN(PE_BASE + 14, "PE14")
 178 #define SUNXI_PINCTRL_PIN_PE15  PINCTRL_PIN(PE_BASE + 15, "PE15")
 179 #define SUNXI_PINCTRL_PIN_PE16  PINCTRL_PIN(PE_BASE + 16, "PE16")
 180 #define SUNXI_PINCTRL_PIN_PE17  PINCTRL_PIN(PE_BASE + 17, "PE17")
 181 #define SUNXI_PINCTRL_PIN_PE18  PINCTRL_PIN(PE_BASE + 18, "PE18")
 182 #define SUNXI_PINCTRL_PIN_PE19  PINCTRL_PIN(PE_BASE + 19, "PE19")
 183 #define SUNXI_PINCTRL_PIN_PE20  PINCTRL_PIN(PE_BASE + 20, "PE20")
 184 #define SUNXI_PINCTRL_PIN_PE21  PINCTRL_PIN(PE_BASE + 21, "PE21")
 185 #define SUNXI_PINCTRL_PIN_PE22  PINCTRL_PIN(PE_BASE + 22, "PE22")
 186 #define SUNXI_PINCTRL_PIN_PE23  PINCTRL_PIN(PE_BASE + 23, "PE23")
 187 #define SUNXI_PINCTRL_PIN_PE24  PINCTRL_PIN(PE_BASE + 24, "PE24")
 188 #define SUNXI_PINCTRL_PIN_PE25  PINCTRL_PIN(PE_BASE + 25, "PE25")
 189 #define SUNXI_PINCTRL_PIN_PE26  PINCTRL_PIN(PE_BASE + 26, "PE26")
 190 #define SUNXI_PINCTRL_PIN_PE27  PINCTRL_PIN(PE_BASE + 27, "PE27")
 191 #define SUNXI_PINCTRL_PIN_PE28  PINCTRL_PIN(PE_BASE + 28, "PE28")
 192 #define SUNXI_PINCTRL_PIN_PE29  PINCTRL_PIN(PE_BASE + 29, "PE29")
 193 #define SUNXI_PINCTRL_PIN_PE30  PINCTRL_PIN(PE_BASE + 30, "PE30")
 194 #define SUNXI_PINCTRL_PIN_PE31  PINCTRL_PIN(PE_BASE + 31, "PE31")
 195
 196 #define SUNXI_PINCTRL_PIN_PF0   PINCTRL_PIN(PF_BASE + 0, "PF0")
 197 #define SUNXI_PINCTRL_PIN_PF1   PINCTRL_PIN(PF_BASE + 1, "PF1")
 198 #define SUNXI_PINCTRL_PIN_PF2   PINCTRL_PIN(PF_BASE + 2, "PF2")
 199 #define SUNXI_PINCTRL_PIN_PF3   PINCTRL_PIN(PF_BASE + 3, "PF3")
 200 #define SUNXI_PINCTRL_PIN_PF4   PINCTRL_PIN(PF_BASE + 4, "PF4")
 201 #define SUNXI_PINCTRL_PIN_PF5   PINCTRL_PIN(PF_BASE + 5, "PF5")
 202 #define SUNXI_PINCTRL_PIN_PF6   PINCTRL_PIN(PF_BASE + 6, "PF6")
 203 #define SUNXI_PINCTRL_PIN_PF7   PINCTRL_PIN(PF_BASE + 7, "PF7")
 204 #define SUNXI_PINCTRL_PIN_PF8   PINCTRL_PIN(PF_BASE + 8, "PF8")
 205 #define SUNXI_PINCTRL_PIN_PF9   PINCTRL_PIN(PF_BASE + 9, "PF9")
 206 #define SUNXI_PINCTRL_PIN_PF10  PINCTRL_PIN(PF_BASE + 10, "PF10")
 207 #define SUNXI_PINCTRL_PIN_PF11  PINCTRL_PIN(PF_BASE + 11, "PF11")
 208 #define SUNXI_PINCTRL_PIN_PF12  PINCTRL_PIN(PF_BASE + 12, "PF12")
 209 #define SUNXI_PINCTRL_PIN_PF13  PINCTRL_PIN(PF_BASE + 13, "PF13")
 210 #define SUNXI_PINCTRL_PIN_PF14  PINCTRL_PIN(PF_BASE + 14, "PF14")
 211 #define SUNXI_PINCTRL_PIN_PF15  PINCTRL_PIN(PF_BASE + 15, "PF15")
 212 #define SUNXI_PINCTRL_PIN_PF16  PINCTRL_PIN(PF_BASE + 16, "PF16")
 213 #define SUNXI_PINCTRL_PIN_PF17  PINCTRL_PIN(PF_BASE + 17, "PF17")
 214 #define SUNXI_PINCTRL_PIN_PF18  PINCTRL_PIN(PF_BASE + 18, "PF18")
 215 #define SUNXI_PINCTRL_PIN_PF19  PINCTRL_PIN(PF_BASE + 19, "PF19")
 216 #define SUNXI_PINCTRL_PIN_PF20  PINCTRL_PIN(PF_BASE + 20, "PF20")
 217 #define SUNXI_PINCTRL_PIN_PF21  PINCTRL_PIN(PF_BASE + 21, "PF21")
 218 #define SUNXI_PINCTRL_PIN_PF22  PINCTRL_PIN(PF_BASE + 22, "PF22")
 219 #define SUNXI_PINCTRL_PIN_PF23  PINCTRL_PIN(PF_BASE + 23, "PF23")
 220 #define SUNXI_PINCTRL_PIN_PF24  PINCTRL_PIN(PF_BASE + 24, "PF24")
 221 #define SUNXI_PINCTRL_PIN_PF25  PINCTRL_PIN(PF_BASE + 25, "PF25")
 222 #define SUNXI_PINCTRL_PIN_PF26  PINCTRL_PIN(PF_BASE + 26, "PF26")
 223 #define SUNXI_PINCTRL_PIN_PF27  PINCTRL_PIN(PF_BASE + 27, "PF27")
 224 #define SUNXI_PINCTRL_PIN_PF28  PINCTRL_PIN(PF_BASE + 28, "PF28")
 225 #define SUNXI_PINCTRL_PIN_PF29  PINCTRL_PIN(PF_BASE + 29, "PF29")
 226 #define SUNXI_PINCTRL_PIN_PF30  PINCTRL_PIN(PF_BASE + 30, "PF30")
 227 #define SUNXI_PINCTRL_PIN_PF31  PINCTRL_PIN(PF_BASE + 31, "PF31")
 228
 229 #define SUNXI_PINCTRL_PIN_PG0   PINCTRL_PIN(PG_BASE + 0, "PG0")
 230 #define SUNXI_PINCTRL_PIN_PG1   PINCTRL_PIN(PG_BASE + 1, "PG1")
 231 #define SUNXI_PINCTRL_PIN_PG2   PINCTRL_PIN(PG_BASE + 2, "PG2")
 232 #define SUNXI_PINCTRL_PIN_PG3   PINCTRL_PIN(PG_BASE + 3, "PG3")
 233 #define SUNXI_PINCTRL_PIN_PG4   PINCTRL_PIN(PG_BASE + 4, "PG4")
 234 #define SUNXI_PINCTRL_PIN_PG5   PINCTRL_PIN(PG_BASE + 5, "PG5")
 235 #define SUNXI_PINCTRL_PIN_PG6   PINCTRL_PIN(PG_BASE + 6, "PG6")
 236 #define SUNXI_PINCTRL_PIN_PG7   PINCTRL_PIN(PG_BASE + 7, "PG7")
 237 #define SUNXI_PINCTRL_PIN_PG8   PINCTRL_PIN(PG_BASE + 8, "PG8")
 238 #define SUNXI_PINCTRL_PIN_PG9   PINCTRL_PIN(PG_BASE + 9, "PG9")
 239 #define SUNXI_PINCTRL_PIN_PG10  PINCTRL_PIN(PG_BASE + 10, "PG10")
 240 #define SUNXI_PINCTRL_PIN_PG11  PINCTRL_PIN(PG_BASE + 11, "PG11")
 241 #define SUNXI_PINCTRL_PIN_PG12  PINCTRL_PIN(PG_BASE + 12, "PG12")
 242 #define SUNXI_PINCTRL_PIN_PG13  PINCTRL_PIN(PG_BASE + 13, "PG13")
 243 #define SUNXI_PINCTRL_PIN_PG14  PINCTRL_PIN(PG_BASE + 14, "PG14")
 244 #define SUNXI_PINCTRL_PIN_PG15  PINCTRL_PIN(PG_BASE + 15, "PG15")
 245 #define SUNXI_PINCTRL_PIN_PG16  PINCTRL_PIN(PG_BASE + 16, "PG16")
 246 #define SUNXI_PINCTRL_PIN_PG17  PINCTRL_PIN(PG_BASE + 17, "PG17")
 247 #define SUNXI_PINCTRL_PIN_PG18  PINCTRL_PIN(PG_BASE + 18, "PG18")
 248 #define SUNXI_PINCTRL_PIN_PG19  PINCTRL_PIN(PG_BASE + 19, "PG19")
 249 #define SUNXI_PINCTRL_PIN_PG20  PINCTRL_PIN(PG_BASE + 20, "PG20")
 250 #define SUNXI_PINCTRL_PIN_PG21  PINCTRL_PIN(PG_BASE + 21, "PG21")
 251 #define SUNXI_PINCTRL_PIN_PG22  PINCTRL_PIN(PG_BASE + 22, "PG22")
 252 #define SUNXI_PINCTRL_PIN_PG23  PINCTRL_PIN(PG_BASE + 23, "PG23")
 253 #define SUNXI_PINCTRL_PIN_PG24  PINCTRL_PIN(PG_BASE + 24, "PG24")
 254 #define SUNXI_PINCTRL_PIN_PG25  PINCTRL_PIN(PG_BASE + 25, "PG25")
 255 #define SUNXI_PINCTRL_PIN_PG26  PINCTRL_PIN(PG_BASE + 26, "PG26")
 256 #define SUNXI_PINCTRL_PIN_PG27  PINCTRL_PIN(PG_BASE + 27, "PG27")
 257 #define SUNXI_PINCTRL_PIN_PG28  PINCTRL_PIN(PG_BASE + 28, "PG28")
 258 #define SUNXI_PINCTRL_PIN_PG29  PINCTRL_PIN(PG_BASE + 29, "PG29")
 259 #define SUNXI_PINCTRL_PIN_PG30  PINCTRL_PIN(PG_BASE + 30, "PG30")
 260 #define SUNXI_PINCTRL_PIN_PG31  PINCTRL_PIN(PG_BASE + 31, "PG31")
 261
 262 #define SUNXI_PINCTRL_PIN_PH0   PINCTRL_PIN(PH_BASE + 0, "PH0")
 263 #define SUNXI_PINCTRL_PIN_PH1   PINCTRL_PIN(PH_BASE + 1, "PH1")
 264 #define SUNXI_PINCTRL_PIN_PH2   PINCTRL_PIN(PH_BASE + 2, "PH2")
 265 #define SUNXI_PINCTRL_PIN_PH3   PINCTRL_PIN(PH_BASE + 3, "PH3")
 266 #define SUNXI_PINCTRL_PIN_PH4   PINCTRL_PIN(PH_BASE + 4, "PH4")
 267 #define SUNXI_PINCTRL_PIN_PH5   PINCTRL_PIN(PH_BASE + 5, "PH5")
 268 #define SUNXI_PINCTRL_PIN_PH6   PINCTRL_PIN(PH_BASE + 6, "PH6")
 269 #define SUNXI_PINCTRL_PIN_PH7   PINCTRL_PIN(PH_BASE + 7, "PH7")
 270 #define SUNXI_PINCTRL_PIN_PH8   PINCTRL_PIN(PH_BASE + 8, "PH8")
 271 #define SUNXI_PINCTRL_PIN_PH9   PINCTRL_PIN(PH_BASE + 9, "PH9")
 272 #define SUNXI_PINCTRL_PIN_PH10  PINCTRL_PIN(PH_BASE + 10, "PH10")
 273 #define SUNXI_PINCTRL_PIN_PH11  PINCTRL_PIN(PH_BASE + 11, "PH11")
 274 #define SUNXI_PINCTRL_PIN_PH12  PINCTRL_PIN(PH_BASE + 12, "PH12")
 275 #define SUNXI_PINCTRL_PIN_PH13  PINCTRL_PIN(PH_BASE + 13, "PH13")
 276 #define SUNXI_PINCTRL_PIN_PH14  PINCTRL_PIN(PH_BASE + 14, "PH14")
 277 #define SUNXI_PINCTRL_PIN_PH15  PINCTRL_PIN(PH_BASE + 15, "PH15")
 278 #define SUNXI_PINCTRL_PIN_PH16  PINCTRL_PIN(PH_BASE + 16, "PH16")
 279 #define SUNXI_PINCTRL_PIN_PH17  PINCTRL_PIN(PH_BASE + 17, "PH17")
 280 #define SUNXI_PINCTRL_PIN_PH18  PINCTRL_PIN(PH_BASE + 18, "PH18")
 281 #define SUNXI_PINCTRL_PIN_PH19  PINCTRL_PIN(PH_BASE + 19, "PH19")
 282 #define SUNXI_PINCTRL_PIN_PH20  PINCTRL_PIN(PH_BASE + 20, "PH20")
 283 #define SUNXI_PINCTRL_PIN_PH21  PINCTRL_PIN(PH_BASE + 21, "PH21")
 284 #define SUNXI_PINCTRL_PIN_PH22  PINCTRL_PIN(PH_BASE + 22, "PH22")
 285 #define SUNXI_PINCTRL_PIN_PH23  PINCTRL_PIN(PH_BASE + 23, "PH23")
 286 #define SUNXI_PINCTRL_PIN_PH24  PINCTRL_PIN(PH_BASE + 24, "PH24")
 287 #define SUNXI_PINCTRL_PIN_PH25  PINCTRL_PIN(PH_BASE + 25, "PH25")
 288 #define SUNXI_PINCTRL_PIN_PH26  PINCTRL_PIN(PH_BASE + 26, "PH26")
 289 #define SUNXI_PINCTRL_PIN_PH27  PINCTRL_PIN(PH_BASE + 27, "PH27")
 290 #define SUNXI_PINCTRL_PIN_PH28  PINCTRL_PIN(PH_BASE + 28, "PH28")
 291 #define SUNXI_PINCTRL_PIN_PH29  PINCTRL_PIN(PH_BASE + 29, "PH29")
 292 #define SUNXI_PINCTRL_PIN_PH30  PINCTRL_PIN(PH_BASE + 30, "PH30")
 293 #define SUNXI_PINCTRL_PIN_PH31  PINCTRL_PIN(PH_BASE + 31, "PH31")
 294
 295 #define SUNXI_PINCTRL_PIN_PI0   PINCTRL_PIN(PI_BASE + 0, "PI0")
 296 #define SUNXI_PINCTRL_PIN_PI1   PINCTRL_PIN(PI_BASE + 1, "PI1")
 297 #define SUNXI_PINCTRL_PIN_PI2   PINCTRL_PIN(PI_BASE + 2, "PI2")
 298 #define SUNXI_PINCTRL_PIN_PI3   PINCTRL_PIN(PI_BASE + 3, "PI3")
 299 #define SUNXI_PINCTRL_PIN_PI4   PINCTRL_PIN(PI_BASE + 4, "PI4")
 300 #define SUNXI_PINCTRL_PIN_PI5   PINCTRL_PIN(PI_BASE + 5, "PI5")
 301 #define SUNXI_PINCTRL_PIN_PI6   PINCTRL_PIN(PI_BASE + 6, "PI6")
 302 #define SUNXI_PINCTRL_PIN_PI7   PINCTRL_PIN(PI_BASE + 7, "PI7")
 303 #define SUNXI_PINCTRL_PIN_PI8   PINCTRL_PIN(PI_BASE + 8, "PI8")
 304 #define SUNXI_PINCTRL_PIN_PI9   PINCTRL_PIN(PI_BASE + 9, "PI9")
 305 #define SUNXI_PINCTRL_PIN_PI10  PINCTRL_PIN(PI_BASE + 10, "PI10")
 306 #define SUNXI_PINCTRL_PIN_PI11  PINCTRL_PIN(PI_BASE + 11, "PI11")
 307 #define SUNXI_PINCTRL_PIN_PI12  PINCTRL_PIN(PI_BASE + 12, "PI12")
 308 #define SUNXI_PINCTRL_PIN_PI13  PINCTRL_PIN(PI_BASE + 13, "PI13")
 309 #define SUNXI_PINCTRL_PIN_PI14  PINCTRL_PIN(PI_BASE + 14, "PI14")
 310 #define SUNXI_PINCTRL_PIN_PI15  PINCTRL_PIN(PI_BASE + 15, "PI15")
 311 #define SUNXI_PINCTRL_PIN_PI16  PINCTRL_PIN(PI_BASE + 16, "PI16")
 312 #define SUNXI_PINCTRL_PIN_PI17  PINCTRL_PIN(PI_BASE + 17, "PI17")
 313 #define SUNXI_PINCTRL_PIN_PI18  PINCTRL_PIN(PI_BASE + 18, "PI18")
 314 #define SUNXI_PINCTRL_PIN_PI19  PINCTRL_PIN(PI_BASE + 19, "PI19")
 315 #define SUNXI_PINCTRL_PIN_PI20  PINCTRL_PIN(PI_BASE + 20, "PI20")
 316 #define SUNXI_PINCTRL_PIN_PI21  PINCTRL_PIN(PI_BASE + 21, "PI21")
 317 #define SUNXI_PINCTRL_PIN_PI22  PINCTRL_PIN(PI_BASE + 22, "PI22")
 318 #define SUNXI_PINCTRL_PIN_PI23  PINCTRL_PIN(PI_BASE + 23, "PI23")
 319 #define SUNXI_PINCTRL_PIN_PI24  PINCTRL_PIN(PI_BASE + 24, "PI24")
 320 #define SUNXI_PINCTRL_PIN_PI25  PINCTRL_PIN(PI_BASE + 25, "PI25")
 321 #define SUNXI_PINCTRL_PIN_PI26  PINCTRL_PIN(PI_BASE + 26, "PI26")
 322 #define SUNXI_PINCTRL_PIN_PI27  PINCTRL_PIN(PI_BASE + 27, "PI27")
 323 #define SUNXI_PINCTRL_PIN_PI28  PINCTRL_PIN(PI_BASE + 28, "PI28")
 324 #define SUNXI_PINCTRL_PIN_PI29  PINCTRL_PIN(PI_BASE + 29, "PI29")
 325 #define SUNXI_PINCTRL_PIN_PI30  PINCTRL_PIN(PI_BASE + 30, "PI30")
 326 #define SUNXI_PINCTRL_PIN_PI31  PINCTRL_PIN(PI_BASE + 31, "PI31")
 327
 328 #define SUNXI_PINCTRL_PIN_PL0   PINCTRL_PIN(PL_BASE + 0, "PL0")
 329 #define SUNXI_PINCTRL_PIN_PL1   PINCTRL_PIN(PL_BASE + 1, "PL1")
 330 #define SUNXI_PINCTRL_PIN_PL2   PINCTRL_PIN(PL_BASE + 2, "PL2")
 331 #define SUNXI_PINCTRL_PIN_PL3   PINCTRL_PIN(PL_BASE + 3, "PL3")
 332 #define SUNXI_PINCTRL_PIN_PL4   PINCTRL_PIN(PL_BASE + 4, "PL4")
 333 #define SUNXI_PINCTRL_PIN_PL5   PINCTRL_PIN(PL_BASE + 5, "PL5")
 334 #define SUNXI_PINCTRL_PIN_PL6   PINCTRL_PIN(PL_BASE + 6, "PL6")
 335 #define SUNXI_PINCTRL_PIN_PL7   PINCTRL_PIN(PL_BASE + 7, "PL7")
 336 #define SUNXI_PINCTRL_PIN_PL8   PINCTRL_PIN(PL_BASE + 8, "PL8")
 337 #define SUNXI_PINCTRL_PIN_PL9   PINCTRL_PIN(PL_BASE + 9, "PL9")
 338 #define SUNXI_PINCTRL_PIN_PL10  PINCTRL_PIN(PL_BASE + 10, "PL10")
 339 #define SUNXI_PINCTRL_PIN_PL11  PINCTRL_PIN(PL_BASE + 11, "PL11")
 340 #define SUNXI_PINCTRL_PIN_PL12  PINCTRL_PIN(PL_BASE + 12, "PL12")
 341 #define SUNXI_PINCTRL_PIN_PL13  PINCTRL_PIN(PL_BASE + 13, "PL13")
 342 #define SUNXI_PINCTRL_PIN_PL14  PINCTRL_PIN(PL_BASE + 14, "PL14")
 343 #define SUNXI_PINCTRL_PIN_PL15  PINCTRL_PIN(PL_BASE + 15, "PL15")
 344 #define SUNXI_PINCTRL_PIN_PL16  PINCTRL_PIN(PL_BASE + 16, "PL16")
 345 #define SUNXI_PINCTRL_PIN_PL17  PINCTRL_PIN(PL_BASE + 17, "PL17")
 346 #define SUNXI_PINCTRL_PIN_PL18  PINCTRL_PIN(PL_BASE + 18, "PL18")
 347 #define SUNXI_PINCTRL_PIN_PL19  PINCTRL_PIN(PL_BASE + 19, "PL19")
 348 #define SUNXI_PINCTRL_PIN_PL20  PINCTRL_PIN(PL_BASE + 20, "PL20")
 349 #define SUNXI_PINCTRL_PIN_PL21  PINCTRL_PIN(PL_BASE + 21, "PL21")
 350 #define SUNXI_PINCTRL_PIN_PL22  PINCTRL_PIN(PL_BASE + 22, "PL22")
 351 #define SUNXI_PINCTRL_PIN_PL23  PINCTRL_PIN(PL_BASE + 23, "PL23")
 352 #define SUNXI_PINCTRL_PIN_PL24  PINCTRL_PIN(PL_BASE + 24, "PL24")
 353 #define SUNXI_PINCTRL_PIN_PL25  PINCTRL_PIN(PL_BASE + 25, "PL25")
 354 #define SUNXI_PINCTRL_PIN_PL26  PINCTRL_PIN(PL_BASE + 26, "PL26")
 355 #define SUNXI_PINCTRL_PIN_PL27  PINCTRL_PIN(PL_BASE + 27, "PL27")
 356 #define SUNXI_PINCTRL_PIN_PL28  PINCTRL_PIN(PL_BASE + 28, "PL28")
 357 #define SUNXI_PINCTRL_PIN_PL29  PINCTRL_PIN(PL_BASE + 29, "PL29")
 358 #define SUNXI_PINCTRL_PIN_PL30  PINCTRL_PIN(PL_BASE + 30, "PL30")
 359 #define SUNXI_PINCTRL_PIN_PL31  PINCTRL_PIN(PL_BASE + 31, "PL31")
 360
 361 #define SUNXI_PINCTRL_PIN_PM0   PINCTRL_PIN(PM_BASE + 0, "PM0")
 362 #define SUNXI_PINCTRL_PIN_PM1   PINCTRL_PIN(PM_BASE + 1, "PM1")
 363 #define SUNXI_PINCTRL_PIN_PM2   PINCTRL_PIN(PM_BASE + 2, "PM2")
 364 #define SUNXI_PINCTRL_PIN_PM3   PINCTRL_PIN(PM_BASE + 3, "PM3")
 365 #define SUNXI_PINCTRL_PIN_PM4   PINCTRL_PIN(PM_BASE + 4, "PM4")
 366 #define SUNXI_PINCTRL_PIN_PM5   PINCTRL_PIN(PM_BASE + 5, "PM5")
 367 #define SUNXI_PINCTRL_PIN_PM6   PINCTRL_PIN(PM_BASE + 6, "PM6")
 368 #define SUNXI_PINCTRL_PIN_PM7   PINCTRL_PIN(PM_BASE + 7, "PM7")
 369 #define SUNXI_PINCTRL_PIN_PM8   PINCTRL_PIN(PM_BASE + 8, "PM8")
 370 #define SUNXI_PINCTRL_PIN_PM9   PINCTRL_PIN(PM_BASE + 9, "PM9")
 371 #define SUNXI_PINCTRL_PIN_PM10  PINCTRL_PIN(PM_BASE + 10, "PM10")
 372 #define SUNXI_PINCTRL_PIN_PM11  PINCTRL_PIN(PM_BASE + 11, "PM11")
 373 #define SUNXI_PINCTRL_PIN_PM12  PINCTRL_PIN(PM_BASE + 12, "PM12")
 374 #define SUNXI_PINCTRL_PIN_PM13  PINCTRL_PIN(PM_BASE + 13, "PM13")
 375 #define SUNXI_PINCTRL_PIN_PM14  PINCTRL_PIN(PM_BASE + 14, "PM14")
 376 #define SUNXI_PINCTRL_PIN_PM15  PINCTRL_PIN(PM_BASE + 15, "PM15")
 377 #define SUNXI_PINCTRL_PIN_PM16  PINCTRL_PIN(PM_BASE + 16, "PM16")
 378 #define SUNXI_PINCTRL_PIN_PM17  PINCTRL_PIN(PM_BASE + 17, "PM17")
 379 #define SUNXI_PINCTRL_PIN_PM18  PINCTRL_PIN(PM_BASE + 18, "PM18")
 380 #define SUNXI_PINCTRL_PIN_PM19  PINCTRL_PIN(PM_BASE + 19, "PM19")
 381 #define SUNXI_PINCTRL_PIN_PM20  PINCTRL_PIN(PM_BASE + 20, "PM20")
 382 #define SUNXI_PINCTRL_PIN_PM21  PINCTRL_PIN(PM_BASE + 21, "PM21")
 383 #define SUNXI_PINCTRL_PIN_PM22  PINCTRL_PIN(PM_BASE + 22, "PM22")
 384 #define SUNXI_PINCTRL_PIN_PM23  PINCTRL_PIN(PM_BASE + 23, "PM23")
 385 #define SUNXI_PINCTRL_PIN_PM24  PINCTRL_PIN(PM_BASE + 24, "PM24")
 386 #define SUNXI_PINCTRL_PIN_PM25  PINCTRL_PIN(PM_BASE + 25, "PM25")
 387 #define SUNXI_PINCTRL_PIN_PM26  PINCTRL_PIN(PM_BASE + 26, "PM26")
 388 #define SUNXI_PINCTRL_PIN_PM27  PINCTRL_PIN(PM_BASE + 27, "PM27")
 389 #define SUNXI_PINCTRL_PIN_PM28  PINCTRL_PIN(PM_BASE + 28, "PM28")
 390 #define SUNXI_PINCTRL_PIN_PM29  PINCTRL_PIN(PM_BASE + 29, "PM29")
 391 #define SUNXI_PINCTRL_PIN_PM30  PINCTRL_PIN(PM_BASE + 30, "PM30")
 392 #define SUNXI_PINCTRL_PIN_PM31  PINCTRL_PIN(PM_BASE + 31, "PM31")
 393
 394 #define SUNXI_PIN_NAME_MAX_LEN  5
 395
 396 #define BANK_MEM_SIZE           0x24
 397 #define MUX_REGS_OFFSET         0x0
 398 #define DATA_REGS_OFFSET        0x10
 399 #define DLEVEL_REGS_OFFSET      0x14
 400 #define PULL_REGS_OFFSET        0x1c
 401
 402 #define PINS_PER_BANK           32
 403 #define MUX_PINS_PER_REG        8
 404 #define MUX_PINS_BITS           4
 405 #define MUX_PINS_MASK           0x0f
 406 #define DATA_PINS_PER_REG       32
 407 #define DATA_PINS_BITS          1
 408 #define DATA_PINS_MASK          0x01
 409 #define DLEVEL_PINS_PER_REG     16
 410 #define DLEVEL_PINS_BITS        2
 411 #define DLEVEL_PINS_MASK        0x03
 412 #define PULL_PINS_PER_REG       16
 413 #define PULL_PINS_BITS          2
 414 #define PULL_PINS_MASK          0x03
 415
 416 #define SUNXI_IRQ_NUMBER        32
 417
 418 #define IRQ_CFG_REG             0x200
 419 #define IRQ_CFG_IRQ_PER_REG             8
 420 #define IRQ_CFG_IRQ_BITS                4
 421 #define IRQ_CFG_IRQ_MASK                ((1 << IRQ_CFG_IRQ_BITS) - 1)
 422 #define IRQ_CTRL_REG            0x210
 423 #define IRQ_CTRL_IRQ_PER_REG            32
 424 #define IRQ_CTRL_IRQ_BITS               1
 425 #define IRQ_CTRL_IRQ_MASK               ((1 << IRQ_CTRL_IRQ_BITS) - 1)
 426 #define IRQ_STATUS_REG          0x214
 427 #define IRQ_STATUS_IRQ_PER_REG          32
 428 #define IRQ_STATUS_IRQ_BITS             1
 429 #define IRQ_STATUS_IRQ_MASK             ((1 << IRQ_STATUS_IRQ_BITS) - 1)
 430
 431 #define IRQ_EDGE_RISING         0x00
 432 #define IRQ_EDGE_FALLING        0x01
 433 #define IRQ_LEVEL_HIGH          0x02
 434 #define IRQ_LEVEL_LOW           0x03
 435 #define IRQ_EDGE_BOTH           0x04
 436
 437 struct sunxi_desc_function {
 438         const char      *name;
 439         u8              muxval;
 440         u8              irqnum;
 441 };
 442
 443 struct sunxi_desc_pin {
 444         struct pinctrl_pin_desc         pin;
 445         struct sunxi_desc_function      *functions;
 446 };
 447
 448 struct sunxi_pinctrl_desc {
 449         const struct sunxi_desc_pin     *pins;
 450         int                             npins;
 451         unsigned                        pin_base;
 452 };
 453
 454 struct sunxi_pinctrl_function {
 455         const char      *name;
 456         const char      **groups;
 457         unsigned        ngroups;
 458 };
 459
 460 struct sunxi_pinctrl_group {
 461         const char      *name;
 462         unsigned long   config;
 463         unsigned        pin;
 464 };
 465
 466 struct sunxi_pinctrl {
 467         void __iomem                    *membase;
 468         struct gpio_chip                *chip;
 469         const struct sunxi_pinctrl_desc *desc;
 470         struct device                   *dev;
 471         struct irq_domain               *domain;
 472         struct sunxi_pinctrl_function   *functions;
 473         unsigned                        nfunctions;
 474         struct sunxi_pinctrl_group      *groups;
 475         unsigned                        ngroups;
 476         int                             irq;
 477         int                             irq_array[SUNXI_IRQ_NUMBER];
 478         spinlock_t                      lock;
 479         struct pinctrl_dev              *pctl_dev;
 480 };
 481
 482 #define SUNXI_PIN(_pin, ...)                                    \
 483         {                                                       \
 484                 .pin = _pin,                                    \
 485                 .functions = (struct sunxi_desc_function[]){    \
 486                         __VA_ARGS__, { } },                     \
 487         }
 488
 489 #define SUNXI_FUNCTION(_val, _name)                             \
 490         {                                                       \
 491                 .name = _name,                                  \
 492                 .muxval = _val,                                 \
 493         }
 494
 495 #define SUNXI_FUNCTION_IRQ(_val, _irq)                          \
 496         {                                                       \
 497                 .name = "irq",                                  \
 498                 .muxval = _val,                                 \
 499                 .irqnum = _irq,                                 \
 500         }
 501
 502 /*
 503  * The sunXi PIO registers are organized as is:
 504  * 0x00 - 0x0c  Muxing values.
 505  *              8 pins per register, each pin having a 4bits value
 506  * 0x10         Pin values
 507  *              32 bits per register, each pin corresponding to one bit
 508  * 0x14 - 0x18  Drive level
 509  *              16 pins per register, each pin having a 2bits value
 510  * 0x1c - 0x20  Pull-Up values
 511  *              16 pins per register, each pin having a 2bits value
 512  *
 513  * This is for the first bank. Each bank will have the same layout,
 514  * with an offset being a multiple of 0x24.
 515  *
 516  * The following functions calculate from the pin number the register
 517  * and the bit offset that we should access.
 518  */
 519 static inline u32 sunxi_mux_reg(u16 pin)
 520 {
 521         u8 bank = pin / PINS_PER_BANK;
 522         u32 offset = bank * BANK_MEM_SIZE;
 523         offset += MUX_REGS_OFFSET;
 524         offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
 525         return round_down(offset, 4);
 526 }
 527
 528 static inline u32 sunxi_mux_offset(u16 pin)
 529 {
 530         u32 pin_num = pin % MUX_PINS_PER_REG;
 531         return pin_num * MUX_PINS_BITS;
 532 }
 533
 534 static inline u32 sunxi_data_reg(u16 pin)
 535 {
 536         u8 bank = pin / PINS_PER_BANK;
 537         u32 offset = bank * BANK_MEM_SIZE;
 538         offset += DATA_REGS_OFFSET;
 539         offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
 540         return round_down(offset, 4);
 541 }
 542
 543 static inline u32 sunxi_data_offset(u16 pin)
 544 {
 545         u32 pin_num = pin % DATA_PINS_PER_REG;
 546         return pin_num * DATA_PINS_BITS;
 547 }
 548
 549 static inline u32 sunxi_dlevel_reg(u16 pin)
 550 {
 551         u8 bank = pin / PINS_PER_BANK;
 552         u32 offset = bank * BANK_MEM_SIZE;
 553         offset += DLEVEL_REGS_OFFSET;
 554         offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
 555         return round_down(offset, 4);
 556 }
 557
 558 static inline u32 sunxi_dlevel_offset(u16 pin)
 559 {
 560         u32 pin_num = pin % DLEVEL_PINS_PER_REG;
 561         return pin_num * DLEVEL_PINS_BITS;
 562 }
 563
 564 static inline u32 sunxi_pull_reg(u16 pin)
 565 {
 566         u8 bank = pin / PINS_PER_BANK;
 567         u32 offset = bank * BANK_MEM_SIZE;
 568         offset += PULL_REGS_OFFSET;
 569         offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
 570         return round_down(offset, 4);
 571 }
 572
 573 static inline u32 sunxi_pull_offset(u16 pin)
 574 {
 575         u32 pin_num = pin % PULL_PINS_PER_REG;
 576         return pin_num * PULL_PINS_BITS;
 577 }
 578
 579 static inline u32 sunxi_irq_cfg_reg(u16 irq)
 580 {
 581         u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04;
 582         return reg + IRQ_CFG_REG;
 583 }
 584
 585 static inline u32 sunxi_irq_cfg_offset(u16 irq)
 586 {
 587         u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
 588         return irq_num * IRQ_CFG_IRQ_BITS;
 589 }
 590
 591 static inline u32 sunxi_irq_ctrl_reg(u16 irq)
 592 {
 593         u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04;
 594         return reg + IRQ_CTRL_REG;
 595 }
 596
 597 static inline u32 sunxi_irq_ctrl_offset(u16 irq)
 598 {
 599         u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
 600         return irq_num * IRQ_CTRL_IRQ_BITS;
 601 }
 602
 603 static inline u32 sunxi_irq_status_reg(u16 irq)
 604 {
 605         u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04;
 606         return reg + IRQ_STATUS_REG;
 607 }
 608
 609 static inline u32 sunxi_irq_status_offset(u16 irq)
 610 {
 611         u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
 612         return irq_num * IRQ_STATUS_IRQ_BITS;
 613 }
 614
 615 #endif /* __PINCTRL_SUNXI_H */