drivers/pinctrl/sunxi/pinctrl-sunxi.h

   1 /*
   2  * Allwinner A1X SoCs pinctrl driver.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #ifndef __PINCTRL_SUNXI_H
  14 #define __PINCTRL_SUNXI_H
  15
  16 #include <linux/kernel.h>
  17 #include <linux/spinlock.h>
  18
  19 #define PA_BASE 0
  20 #define PB_BASE 32
  21 #define PC_BASE 64
  22 #define PD_BASE 96
  23 #define PE_BASE 128
  24 #define PF_BASE 160
  25 #define PG_BASE 192
  26 #define PH_BASE 224
  27 #define PI_BASE 256
  28 #define PL_BASE 352
  29 #define PM_BASE 384
  30
  31 #define SUNXI_PINCTRL_PIN(bank, pin)            \
  32         PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
  33
  34 #define SUNXI_PIN_NAME_MAX_LEN  5
  35
  36 #define BANK_MEM_SIZE           0x24
  37 #define MUX_REGS_OFFSET         0x0
  38 #define DATA_REGS_OFFSET        0x10
  39 #define DLEVEL_REGS_OFFSET      0x14
  40 #define PULL_REGS_OFFSET        0x1c
  41
  42 #define PINS_PER_BANK           32
  43 #define MUX_PINS_PER_REG        8
  44 #define MUX_PINS_BITS           4
  45 #define MUX_PINS_MASK           0x0f
  46 #define DATA_PINS_PER_REG       32
  47 #define DATA_PINS_BITS          1
  48 #define DATA_PINS_MASK          0x01
  49 #define DLEVEL_PINS_PER_REG     16
  50 #define DLEVEL_PINS_BITS        2
  51 #define DLEVEL_PINS_MASK        0x03
  52 #define PULL_PINS_PER_REG       16
  53 #define PULL_PINS_BITS          2
  54 #define PULL_PINS_MASK          0x03
  55
  56 #define SUNXI_IRQ_NUMBER        32
  57
  58 #define IRQ_CFG_REG             0x200
  59 #define IRQ_CFG_IRQ_PER_REG             8
  60 #define IRQ_CFG_IRQ_BITS                4
  61 #define IRQ_CFG_IRQ_MASK                ((1 << IRQ_CFG_IRQ_BITS) - 1)
  62 #define IRQ_CTRL_REG            0x210
  63 #define IRQ_CTRL_IRQ_PER_REG            32
  64 #define IRQ_CTRL_IRQ_BITS               1
  65 #define IRQ_CTRL_IRQ_MASK               ((1 << IRQ_CTRL_IRQ_BITS) - 1)
  66 #define IRQ_STATUS_REG          0x214
  67 #define IRQ_STATUS_IRQ_PER_REG          32
  68 #define IRQ_STATUS_IRQ_BITS             1
  69 #define IRQ_STATUS_IRQ_MASK             ((1 << IRQ_STATUS_IRQ_BITS) - 1)
  70
  71 #define IRQ_EDGE_RISING         0x00
  72 #define IRQ_EDGE_FALLING        0x01
  73 #define IRQ_LEVEL_HIGH          0x02
  74 #define IRQ_LEVEL_LOW           0x03
  75 #define IRQ_EDGE_BOTH           0x04
  76
  77 struct sunxi_desc_function {
  78         const char      *name;
  79         u8              muxval;
  80         u8              irqnum;
  81 };
  82
  83 struct sunxi_desc_pin {
  84         struct pinctrl_pin_desc         pin;
  85         struct sunxi_desc_function      *functions;
  86 };
  87
  88 struct sunxi_pinctrl_desc {
  89         const struct sunxi_desc_pin     *pins;
  90         int                             npins;
  91         unsigned                        pin_base;
  92 };
  93
  94 struct sunxi_pinctrl_function {
  95         const char      *name;
  96         const char      **groups;
  97         unsigned        ngroups;
  98 };
  99
 100 struct sunxi_pinctrl_group {
 101         const char      *name;
 102         unsigned long   config;
 103         unsigned        pin;
 104 };
 105
 106 struct sunxi_pinctrl {
 107         void __iomem                    *membase;
 108         struct gpio_chip                *chip;
 109         const struct sunxi_pinctrl_desc *desc;
 110         struct device                   *dev;
 111         struct irq_domain               *domain;
 112         struct sunxi_pinctrl_function   *functions;
 113         unsigned                        nfunctions;
 114         struct sunxi_pinctrl_group      *groups;
 115         unsigned                        ngroups;
 116         int                             irq;
 117         int                             irq_array[SUNXI_IRQ_NUMBER];
 118         spinlock_t                      lock;
 119         struct pinctrl_dev              *pctl_dev;
 120 };
 121
 122 #define SUNXI_PIN(_pin, ...)                                    \
 123         {                                                       \
 124                 .pin = _pin,                                    \
 125                 .functions = (struct sunxi_desc_function[]){    \
 126                         __VA_ARGS__, { } },                     \
 127         }
 128
 129 #define SUNXI_FUNCTION(_val, _name)                             \
 130         {                                                       \
 131                 .name = _name,                                  \
 132                 .muxval = _val,                                 \
 133         }
 134
 135 #define SUNXI_FUNCTION_IRQ(_val, _irq)                          \
 136         {                                                       \
 137                 .name = "irq",                                  \
 138                 .muxval = _val,                                 \
 139                 .irqnum = _irq,                                 \
 140         }
 141
 142 /*
 143  * The sunXi PIO registers are organized as is:
 144  * 0x00 - 0x0c  Muxing values.
 145  *              8 pins per register, each pin having a 4bits value
 146  * 0x10         Pin values
 147  *              32 bits per register, each pin corresponding to one bit
 148  * 0x14 - 0x18  Drive level
 149  *              16 pins per register, each pin having a 2bits value
 150  * 0x1c - 0x20  Pull-Up values
 151  *              16 pins per register, each pin having a 2bits value
 152  *
 153  * This is for the first bank. Each bank will have the same layout,
 154  * with an offset being a multiple of 0x24.
 155  *
 156  * The following functions calculate from the pin number the register
 157  * and the bit offset that we should access.
 158  */
 159 static inline u32 sunxi_mux_reg(u16 pin)
 160 {
 161         u8 bank = pin / PINS_PER_BANK;
 162         u32 offset = bank * BANK_MEM_SIZE;
 163         offset += MUX_REGS_OFFSET;
 164         offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
 165         return round_down(offset, 4);
 166 }
 167
 168 static inline u32 sunxi_mux_offset(u16 pin)
 169 {
 170         u32 pin_num = pin % MUX_PINS_PER_REG;
 171         return pin_num * MUX_PINS_BITS;
 172 }
 173
 174 static inline u32 sunxi_data_reg(u16 pin)
 175 {
 176         u8 bank = pin / PINS_PER_BANK;
 177         u32 offset = bank * BANK_MEM_SIZE;
 178         offset += DATA_REGS_OFFSET;
 179         offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
 180         return round_down(offset, 4);
 181 }
 182
 183 static inline u32 sunxi_data_offset(u16 pin)
 184 {
 185         u32 pin_num = pin % DATA_PINS_PER_REG;
 186         return pin_num * DATA_PINS_BITS;
 187 }
 188
 189 static inline u32 sunxi_dlevel_reg(u16 pin)
 190 {
 191         u8 bank = pin / PINS_PER_BANK;
 192         u32 offset = bank * BANK_MEM_SIZE;
 193         offset += DLEVEL_REGS_OFFSET;
 194         offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
 195         return round_down(offset, 4);
 196 }
 197
 198 static inline u32 sunxi_dlevel_offset(u16 pin)
 199 {
 200         u32 pin_num = pin % DLEVEL_PINS_PER_REG;
 201         return pin_num * DLEVEL_PINS_BITS;
 202 }
 203
 204 static inline u32 sunxi_pull_reg(u16 pin)
 205 {
 206         u8 bank = pin / PINS_PER_BANK;
 207         u32 offset = bank * BANK_MEM_SIZE;
 208         offset += PULL_REGS_OFFSET;
 209         offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
 210         return round_down(offset, 4);
 211 }
 212
 213 static inline u32 sunxi_pull_offset(u16 pin)
 214 {
 215         u32 pin_num = pin % PULL_PINS_PER_REG;
 216         return pin_num * PULL_PINS_BITS;
 217 }
 218
 219 static inline u32 sunxi_irq_cfg_reg(u16 irq)
 220 {
 221         u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04;
 222         return reg + IRQ_CFG_REG;
 223 }
 224
 225 static inline u32 sunxi_irq_cfg_offset(u16 irq)
 226 {
 227         u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
 228         return irq_num * IRQ_CFG_IRQ_BITS;
 229 }
 230
 231 static inline u32 sunxi_irq_ctrl_reg(u16 irq)
 232 {
 233         u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04;
 234         return reg + IRQ_CTRL_REG;
 235 }
 236
 237 static inline u32 sunxi_irq_ctrl_offset(u16 irq)
 238 {
 239         u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
 240         return irq_num * IRQ_CTRL_IRQ_BITS;
 241 }
 242
 243 static inline u32 sunxi_irq_status_reg(u16 irq)
 244 {
 245         u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04;
 246         return reg + IRQ_STATUS_REG;
 247 }
 248
 249 static inline u32 sunxi_irq_status_offset(u16 irq)
 250 {
 251         u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
 252         return irq_num * IRQ_STATUS_IRQ_BITS;
 253 }
 254
 255 int sunxi_pinctrl_init(struct platform_device *pdev,
 256                        const struct sunxi_pinctrl_desc *desc);
 257
 258 #endif /* __PINCTRL_SUNXI_H */