Merge tag 'media/v4.8-6' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab...
[deliverable/linux.git] / drivers / pinctrl / uniphier / pinctrl-uniphier.h
1 /*
2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #ifndef __PINCTRL_UNIPHIER_H__
16 #define __PINCTRL_UNIPHIER_H__
17
18 #include <linux/bitops.h>
19 #include <linux/bug.h>
20 #include <linux/kernel.h>
21 #include <linux/types.h>
22
23 struct platform_device;
24
25 #define UNIPHIER_PINCTRL_PINMUX_BASE 0x0
26 #define UNIPHIER_PINCTRL_LOAD_PINMUX 0x700
27 #define UNIPHIER_PINCTRL_DRVCTRL_BASE 0x800
28 #define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x900
29 #define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x980
30 #define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0xa00
31 #define UNIPHIER_PINCTRL_IECTRL 0xd00
32
33 /* input enable control register bit */
34 #define UNIPHIER_PIN_IECTRL_SHIFT 0
35 #define UNIPHIER_PIN_IECTRL_BITS 8
36 #define UNIPHIER_PIN_IECTRL_MASK ((1UL << (UNIPHIER_PIN_IECTRL_BITS)) \
37 - 1)
38
39 /* drive strength control register number */
40 #define UNIPHIER_PIN_DRVCTRL_SHIFT ((UNIPHIER_PIN_IECTRL_SHIFT) + \
41 (UNIPHIER_PIN_IECTRL_BITS))
42 #define UNIPHIER_PIN_DRVCTRL_BITS 9
43 #define UNIPHIER_PIN_DRVCTRL_MASK ((1UL << (UNIPHIER_PIN_DRVCTRL_BITS)) \
44 - 1)
45
46 /* drive control type */
47 #define UNIPHIER_PIN_DRV_TYPE_SHIFT ((UNIPHIER_PIN_DRVCTRL_SHIFT) + \
48 (UNIPHIER_PIN_DRVCTRL_BITS))
49 #define UNIPHIER_PIN_DRV_TYPE_BITS 3
50 #define UNIPHIER_PIN_DRV_TYPE_MASK ((1UL << (UNIPHIER_PIN_DRV_TYPE_BITS)) \
51 - 1)
52
53 /* pull-up / pull-down register number */
54 #define UNIPHIER_PIN_PUPDCTRL_SHIFT ((UNIPHIER_PIN_DRV_TYPE_SHIFT) + \
55 (UNIPHIER_PIN_DRV_TYPE_BITS))
56 #define UNIPHIER_PIN_PUPDCTRL_BITS 9
57 #define UNIPHIER_PIN_PUPDCTRL_MASK ((1UL << (UNIPHIER_PIN_PUPDCTRL_BITS))\
58 - 1)
59
60 /* direction of pull register */
61 #define UNIPHIER_PIN_PULL_DIR_SHIFT ((UNIPHIER_PIN_PUPDCTRL_SHIFT) + \
62 (UNIPHIER_PIN_PUPDCTRL_BITS))
63 #define UNIPHIER_PIN_PULL_DIR_BITS 3
64 #define UNIPHIER_PIN_PULL_DIR_MASK ((1UL << (UNIPHIER_PIN_PULL_DIR_BITS))\
65 - 1)
66
67 #if UNIPHIER_PIN_PULL_DIR_SHIFT + UNIPHIER_PIN_PULL_DIR_BITS > BITS_PER_LONG
68 #error "unable to pack pin attributes."
69 #endif
70
71 #define UNIPHIER_PIN_IECTRL_NONE (UNIPHIER_PIN_IECTRL_MASK)
72
73 /* drive control type */
74 enum uniphier_pin_drv_type {
75 UNIPHIER_PIN_DRV_1BIT, /* 2 level control: 4/8 mA */
76 UNIPHIER_PIN_DRV_2BIT, /* 4 level control: 8/12/16/20 mA */
77 UNIPHIER_PIN_DRV_3BIT, /* 8 level control: 4/5/7/9/11/12/14/16 mA */
78 UNIPHIER_PIN_DRV_FIXED4, /* fixed to 4mA */
79 UNIPHIER_PIN_DRV_FIXED5, /* fixed to 5mA */
80 UNIPHIER_PIN_DRV_FIXED8, /* fixed to 8mA */
81 UNIPHIER_PIN_DRV_NONE, /* no support (input only pin) */
82 };
83
84 /* direction of pull register (no pin supports bi-directional pull biasing) */
85 enum uniphier_pin_pull_dir {
86 UNIPHIER_PIN_PULL_UP, /* pull-up or disabled */
87 UNIPHIER_PIN_PULL_DOWN, /* pull-down or disabled */
88 UNIPHIER_PIN_PULL_UP_FIXED, /* always pull-up */
89 UNIPHIER_PIN_PULL_DOWN_FIXED, /* always pull-down */
90 UNIPHIER_PIN_PULL_NONE, /* no pull register */
91 };
92
93 #define UNIPHIER_PIN_IECTRL(x) \
94 (((x) & (UNIPHIER_PIN_IECTRL_MASK)) << (UNIPHIER_PIN_IECTRL_SHIFT))
95 #define UNIPHIER_PIN_DRVCTRL(x) \
96 (((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT))
97 #define UNIPHIER_PIN_DRV_TYPE(x) \
98 (((x) & (UNIPHIER_PIN_DRV_TYPE_MASK)) << (UNIPHIER_PIN_DRV_TYPE_SHIFT))
99 #define UNIPHIER_PIN_PUPDCTRL(x) \
100 (((x) & (UNIPHIER_PIN_PUPDCTRL_MASK)) << (UNIPHIER_PIN_PUPDCTRL_SHIFT))
101 #define UNIPHIER_PIN_PULL_DIR(x) \
102 (((x) & (UNIPHIER_PIN_PULL_DIR_MASK)) << (UNIPHIER_PIN_PULL_DIR_SHIFT))
103
104 #define UNIPHIER_PIN_ATTR_PACKED(iectrl, drvctrl, drv_type, pupdctrl, pull_dir)\
105 (UNIPHIER_PIN_IECTRL(iectrl) | \
106 UNIPHIER_PIN_DRVCTRL(drvctrl) | \
107 UNIPHIER_PIN_DRV_TYPE(drv_type) | \
108 UNIPHIER_PIN_PUPDCTRL(pupdctrl) | \
109 UNIPHIER_PIN_PULL_DIR(pull_dir))
110
111 static inline unsigned int uniphier_pin_get_iectrl(void *drv_data)
112 {
113 return ((unsigned long)drv_data >> UNIPHIER_PIN_IECTRL_SHIFT) &
114 UNIPHIER_PIN_IECTRL_MASK;
115 }
116
117 static inline unsigned int uniphier_pin_get_drvctrl(void *drv_data)
118 {
119 return ((unsigned long)drv_data >> UNIPHIER_PIN_DRVCTRL_SHIFT) &
120 UNIPHIER_PIN_DRVCTRL_MASK;
121 }
122
123 static inline unsigned int uniphier_pin_get_drv_type(void *drv_data)
124 {
125 return ((unsigned long)drv_data >> UNIPHIER_PIN_DRV_TYPE_SHIFT) &
126 UNIPHIER_PIN_DRV_TYPE_MASK;
127 }
128
129 static inline unsigned int uniphier_pin_get_pupdctrl(void *drv_data)
130 {
131 return ((unsigned long)drv_data >> UNIPHIER_PIN_PUPDCTRL_SHIFT) &
132 UNIPHIER_PIN_PUPDCTRL_MASK;
133 }
134
135 static inline unsigned int uniphier_pin_get_pull_dir(void *drv_data)
136 {
137 return ((unsigned long)drv_data >> UNIPHIER_PIN_PULL_DIR_SHIFT) &
138 UNIPHIER_PIN_PULL_DIR_MASK;
139 }
140
141 enum uniphier_pinmux_gpio_range_type {
142 UNIPHIER_PINMUX_GPIO_RANGE_PORT,
143 UNIPHIER_PINMUX_GPIO_RANGE_IRQ,
144 UNIPHIER_PINMUX_GPIO_RANGE_NONE,
145 };
146
147 struct uniphier_pinctrl_group {
148 const char *name;
149 const unsigned *pins;
150 unsigned num_pins;
151 const int *muxvals;
152 enum uniphier_pinmux_gpio_range_type range_type;
153 };
154
155 struct uniphier_pinmux_function {
156 const char *name;
157 const char * const *groups;
158 unsigned num_groups;
159 };
160
161 struct uniphier_pinctrl_socdata {
162 const struct pinctrl_pin_desc *pins;
163 unsigned int npins;
164 const struct uniphier_pinctrl_group *groups;
165 int groups_count;
166 const struct uniphier_pinmux_function *functions;
167 int functions_count;
168 unsigned int caps;
169 #define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(1)
170 #define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0)
171 };
172
173 #define UNIPHIER_PINCTRL_PIN(a, b, c, d, e, f, g) \
174 { \
175 .number = a, \
176 .name = b, \
177 .drv_data = (void *)UNIPHIER_PIN_ATTR_PACKED(c, d, e, f, g), \
178 }
179
180 #define __UNIPHIER_PINCTRL_GROUP(grp, type) \
181 { \
182 .name = #grp, \
183 .pins = grp##_pins, \
184 .num_pins = ARRAY_SIZE(grp##_pins), \
185 .muxvals = grp##_muxvals + \
186 BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \
187 ARRAY_SIZE(grp##_muxvals)), \
188 .range_type = type, \
189 }
190
191 #define UNIPHIER_PINCTRL_GROUP(grp) \
192 __UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_NONE)
193
194 #define UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(grp) \
195 __UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_PORT)
196
197 #define UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(grp) \
198 __UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_IRQ)
199
200 #define UNIPHIER_PINCTRL_GROUP_SINGLE(grp, array, ofst) \
201 { \
202 .name = #grp, \
203 .pins = array##_pins + ofst, \
204 .num_pins = 1, \
205 .muxvals = array##_muxvals + ofst, \
206 }
207
208 #define UNIPHIER_PINMUX_FUNCTION(func) \
209 { \
210 .name = #func, \
211 .groups = func##_groups, \
212 .num_groups = ARRAY_SIZE(func##_groups), \
213 }
214
215 int uniphier_pinctrl_probe(struct platform_device *pdev,
216 struct uniphier_pinctrl_socdata *socdata);
217
218 #endif /* __PINCTRL_UNIPHIER_H__ */
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