2 * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
4 * (C) Copyright 2008-2010 Intel Corporation
5 * Author: Sreedhara DS (sreedhara.ds@intel.com)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
12 * SCU runing in ARC processor communicates with other entity running in IA
13 * core through IPC mechanism which in turn messaging between IA core ad SCU.
14 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
15 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
16 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
17 * along with other APIs.
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/sysdev.h>
24 #include <linux/pci.h>
25 #include <linux/interrupt.h>
27 #include <asm/intel_scu_ipc.h>
29 /* IPC defines the following message types */
30 #define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
31 #define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */
32 #define IPCMSG_FW_UPDATE 0xFE /* Firmware update */
33 #define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */
34 #define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */
36 /* Command id associated with message IPCMSG_PCNTRL */
37 #define IPC_CMD_PCNTRL_W 0 /* Register write */
38 #define IPC_CMD_PCNTRL_R 1 /* Register read */
39 #define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
42 * IPC register summary
44 * IPC register blocks are memory mapped at fixed address of 0xFF11C000
45 * To read or write information to the SCU, driver writes to IPC-1 memory
46 * mapped registers (base address 0xFF11C000). The following is the IPC
49 * 1. IA core cDMI interface claims this transaction and converts it to a
50 * Transaction Layer Packet (TLP) message which is sent across the cDMI.
52 * 2. South Complex cDMI block receives this message and writes it to
53 * the IPC-1 register block, causing an interrupt to the SCU
55 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
56 * message handler is called within firmware.
59 #define IPC_BASE_ADDR 0xFF11C000 /* IPC1 base register address */
60 #define IPC_MAX_ADDR 0x100 /* Maximum IPC regisers */
61 #define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
62 #define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
63 #define IPC_I2C_BASE 0xFF12B000 /* I2C control register base address */
64 #define IPC_I2C_MAX_ADDR 0x10 /* Maximum I2C regisers */
66 static int ipc_probe(struct pci_dev
*dev
, const struct pci_device_id
*id
);
67 static void ipc_remove(struct pci_dev
*pdev
);
69 struct intel_scu_ipc_dev
{
71 void __iomem
*ipc_base
;
72 void __iomem
*i2c_base
;
75 static struct intel_scu_ipc_dev ipcdev
; /* Only one for now */
77 static int platform
; /* Platform type */
80 * IPC Read Buffer (Read Only):
81 * 16 byte buffer for receiving data from SCU, if IPC command
82 * processing results in response data
84 #define IPC_READ_BUFFER 0x90
86 #define IPC_I2C_CNTRL_ADDR 0
87 #define I2C_DATA_ADDR 0x04
89 static DEFINE_MUTEX(ipclock
); /* lock used to prevent multiple call to SCU */
92 * Command Register (Write Only):
93 * A write to this register results in an interrupt to the SCU core processor
95 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
97 static inline void ipc_command(u32 cmd
) /* Send ipc command */
99 writel(cmd
, ipcdev
.ipc_base
);
103 * IPC Write Buffer (Write Only):
104 * 16-byte buffer for sending data associated with IPC command to
105 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
107 static inline void ipc_data_writel(u32 data
, u32 offset
) /* Write ipc data */
109 writel(data
, ipcdev
.ipc_base
+ 0x80 + offset
);
113 * Status Register (Read Only):
114 * Driver will read this register to get the ready/busy status of the IPC
115 * block and error status of the IPC command that was just processed by SCU
117 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
120 static inline u8
ipc_read_status(void)
122 return __raw_readl(ipcdev
.ipc_base
+ 0x04);
125 static inline u8
ipc_data_readb(u32 offset
) /* Read ipc byte data */
127 return readb(ipcdev
.ipc_base
+ IPC_READ_BUFFER
+ offset
);
130 static inline u32
ipc_data_readl(u32 offset
) /* Read ipc u32 data */
132 return readl(ipcdev
.ipc_base
+ IPC_READ_BUFFER
+ offset
);
135 static inline int busy_loop(void) /* Wait till scu status is busy */
140 status
= ipc_read_status();
142 udelay(1); /* scu processing time is in few u secods */
143 status
= ipc_read_status();
145 /* break if scu doesn't reset busy bit after huge retry */
146 if (loop_count
> 100000) {
147 dev_err(&ipcdev
.pdev
->dev
, "IPC timed out");
151 return (status
>> 1) & 1;
154 /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
155 static int pwr_reg_rdwr(u16
*addr
, u8
*data
, u32 count
, u32 op
, u32 id
)
160 u8 cbuf
[IPC_WWBUF_SIZE
] = { };
161 u32
*wbuf
= (u32
*)&cbuf
;
163 mutex_lock(&ipclock
);
165 memset(cbuf
, 0, sizeof(cbuf
));
167 if (ipcdev
.pdev
== NULL
) {
168 mutex_unlock(&ipclock
);
172 if (platform
!= MRST_CPU_CHIP_PENWELL
) {
175 for (i
= 0; i
< count
; i
++) {
176 cbuf
[bytes
++] = addr
[i
];
177 cbuf
[bytes
++] = addr
[i
] >> 8;
178 if (id
!= IPC_CMD_PCNTRL_R
)
179 cbuf
[bytes
++] = data
[d
++];
180 if (id
== IPC_CMD_PCNTRL_M
)
181 cbuf
[bytes
++] = data
[d
++];
183 for (i
= 0; i
< bytes
; i
+= 4)
184 ipc_data_writel(wbuf
[i
/4], i
);
185 ipc_command(bytes
<< 16 | id
<< 12 | 0 << 8 | op
);
187 for (nc
= 0; nc
< count
; nc
++, offset
+= 2) {
188 cbuf
[offset
] = addr
[nc
];
189 cbuf
[offset
+ 1] = addr
[nc
] >> 8;
192 if (id
== IPC_CMD_PCNTRL_R
) {
193 for (nc
= 0, offset
= 0; nc
< count
; nc
++, offset
+= 4)
194 ipc_data_writel(wbuf
[nc
], offset
);
195 ipc_command((count
*2) << 16 | id
<< 12 | 0 << 8 | op
);
196 } else if (id
== IPC_CMD_PCNTRL_W
) {
197 for (nc
= 0; nc
< count
; nc
++, offset
+= 1)
198 cbuf
[offset
] = data
[nc
];
199 for (nc
= 0, offset
= 0; nc
< count
; nc
++, offset
+= 4)
200 ipc_data_writel(wbuf
[nc
], offset
);
201 ipc_command((count
*3) << 16 | id
<< 12 | 0 << 8 | op
);
202 } else if (id
== IPC_CMD_PCNTRL_M
) {
203 cbuf
[offset
] = data
[0];
204 cbuf
[offset
+ 1] = data
[1];
205 ipc_data_writel(wbuf
[0], 0); /* Write wbuff */
206 ipc_command(4 << 16 | id
<< 12 | 0 << 8 | op
);
211 if (id
== IPC_CMD_PCNTRL_R
) { /* Read rbuf */
212 /* Workaround: values are read as 0 without memcpy_fromio */
213 memcpy_fromio(cbuf
, ipcdev
.ipc_base
+ 0x90, 16);
214 if (platform
!= MRST_CPU_CHIP_PENWELL
) {
215 for (nc
= 0, offset
= 2; nc
< count
; nc
++, offset
+= 3)
216 data
[nc
] = ipc_data_readb(offset
);
218 for (nc
= 0; nc
< count
; nc
++)
219 data
[nc
] = ipc_data_readb(nc
);
222 mutex_unlock(&ipclock
);
227 * intel_scu_ipc_ioread8 - read a word via the SCU
228 * @addr: register on SCU
229 * @data: return pointer for read byte
231 * Read a single register. Returns 0 on success or an error code. All
232 * locking between SCU accesses is handled for the caller.
234 * This function may sleep.
236 int intel_scu_ipc_ioread8(u16 addr
, u8
*data
)
238 return pwr_reg_rdwr(&addr
, data
, 1, IPCMSG_PCNTRL
, IPC_CMD_PCNTRL_R
);
240 EXPORT_SYMBOL(intel_scu_ipc_ioread8
);
243 * intel_scu_ipc_ioread16 - read a word via the SCU
244 * @addr: register on SCU
245 * @data: return pointer for read word
247 * Read a register pair. Returns 0 on success or an error code. All
248 * locking between SCU accesses is handled for the caller.
250 * This function may sleep.
252 int intel_scu_ipc_ioread16(u16 addr
, u16
*data
)
254 u16 x
[2] = {addr
, addr
+ 1 };
255 return pwr_reg_rdwr(x
, (u8
*)data
, 2, IPCMSG_PCNTRL
, IPC_CMD_PCNTRL_R
);
257 EXPORT_SYMBOL(intel_scu_ipc_ioread16
);
260 * intel_scu_ipc_ioread32 - read a dword via the SCU
261 * @addr: register on SCU
262 * @data: return pointer for read dword
264 * Read four registers. Returns 0 on success or an error code. All
265 * locking between SCU accesses is handled for the caller.
267 * This function may sleep.
269 int intel_scu_ipc_ioread32(u16 addr
, u32
*data
)
271 u16 x
[4] = {addr
, addr
+ 1, addr
+ 2, addr
+ 3};
272 return pwr_reg_rdwr(x
, (u8
*)data
, 4, IPCMSG_PCNTRL
, IPC_CMD_PCNTRL_R
);
274 EXPORT_SYMBOL(intel_scu_ipc_ioread32
);
277 * intel_scu_ipc_iowrite8 - write a byte via the SCU
278 * @addr: register on SCU
279 * @data: byte to write
281 * Write a single register. Returns 0 on success or an error code. All
282 * locking between SCU accesses is handled for the caller.
284 * This function may sleep.
286 int intel_scu_ipc_iowrite8(u16 addr
, u8 data
)
288 return pwr_reg_rdwr(&addr
, &data
, 1, IPCMSG_PCNTRL
, IPC_CMD_PCNTRL_W
);
290 EXPORT_SYMBOL(intel_scu_ipc_iowrite8
);
293 * intel_scu_ipc_iowrite16 - write a word via the SCU
294 * @addr: register on SCU
295 * @data: word to write
297 * Write two registers. Returns 0 on success or an error code. All
298 * locking between SCU accesses is handled for the caller.
300 * This function may sleep.
302 int intel_scu_ipc_iowrite16(u16 addr
, u16 data
)
304 u16 x
[2] = {addr
, addr
+ 1 };
305 return pwr_reg_rdwr(x
, (u8
*)&data
, 2, IPCMSG_PCNTRL
, IPC_CMD_PCNTRL_W
);
307 EXPORT_SYMBOL(intel_scu_ipc_iowrite16
);
310 * intel_scu_ipc_iowrite32 - write a dword via the SCU
311 * @addr: register on SCU
312 * @data: dword to write
314 * Write four registers. Returns 0 on success or an error code. All
315 * locking between SCU accesses is handled for the caller.
317 * This function may sleep.
319 int intel_scu_ipc_iowrite32(u16 addr
, u32 data
)
321 u16 x
[4] = {addr
, addr
+ 1, addr
+ 2, addr
+ 3};
322 return pwr_reg_rdwr(x
, (u8
*)&data
, 4, IPCMSG_PCNTRL
, IPC_CMD_PCNTRL_W
);
324 EXPORT_SYMBOL(intel_scu_ipc_iowrite32
);
327 * intel_scu_ipc_readvv - read a set of registers
328 * @addr: register list
329 * @data: bytes to return
330 * @len: length of array
332 * Read registers. Returns 0 on success or an error code. All
333 * locking between SCU accesses is handled for the caller.
335 * The largest array length permitted by the hardware is 5 items.
337 * This function may sleep.
339 int intel_scu_ipc_readv(u16
*addr
, u8
*data
, int len
)
341 return pwr_reg_rdwr(addr
, data
, len
, IPCMSG_PCNTRL
, IPC_CMD_PCNTRL_R
);
343 EXPORT_SYMBOL(intel_scu_ipc_readv
);
346 * intel_scu_ipc_writev - write a set of registers
347 * @addr: register list
348 * @data: bytes to write
349 * @len: length of array
351 * Write registers. Returns 0 on success or an error code. All
352 * locking between SCU accesses is handled for the caller.
354 * The largest array length permitted by the hardware is 5 items.
356 * This function may sleep.
359 int intel_scu_ipc_writev(u16
*addr
, u8
*data
, int len
)
361 return pwr_reg_rdwr(addr
, data
, len
, IPCMSG_PCNTRL
, IPC_CMD_PCNTRL_W
);
363 EXPORT_SYMBOL(intel_scu_ipc_writev
);
367 * intel_scu_ipc_update_register - r/m/w a register
368 * @addr: register address
369 * @bits: bits to update
370 * @mask: mask of bits to update
372 * Read-modify-write power control unit register. The first data argument
373 * must be register value and second is mask value
374 * mask is a bitmap that indicates which bits to update.
375 * 0 = masked. Don't modify this bit, 1 = modify this bit.
376 * returns 0 on success or an error code.
378 * This function may sleep. Locking between SCU accesses is handled
381 int intel_scu_ipc_update_register(u16 addr
, u8 bits
, u8 mask
)
383 u8 data
[2] = { bits
, mask
};
384 return pwr_reg_rdwr(&addr
, data
, 1, IPCMSG_PCNTRL
, IPC_CMD_PCNTRL_M
);
386 EXPORT_SYMBOL(intel_scu_ipc_update_register
);
389 * intel_scu_ipc_simple_command - send a simple command
393 * Issue a simple command to the SCU. Do not use this interface if
394 * you must then access data as any data values may be overwritten
395 * by another SCU access by the time this function returns.
397 * This function may sleep. Locking for SCU accesses is handled for
400 int intel_scu_ipc_simple_command(int cmd
, int sub
)
404 mutex_lock(&ipclock
);
405 if (ipcdev
.pdev
== NULL
) {
406 mutex_unlock(&ipclock
);
409 ipc_command(sub
<< 12 | cmd
);
411 mutex_unlock(&ipclock
);
414 EXPORT_SYMBOL(intel_scu_ipc_simple_command
);
417 * intel_scu_ipc_command - command with data
421 * @inlen: input length in dwords
423 * @outlein: output length in dwords
425 * Issue a command to the SCU which involves data transfers. Do the
426 * data copies under the lock but leave it for the caller to interpret
429 int intel_scu_ipc_command(int cmd
, int sub
, u32
*in
, int inlen
,
430 u32
*out
, int outlen
)
435 mutex_lock(&ipclock
);
436 if (ipcdev
.pdev
== NULL
) {
437 mutex_unlock(&ipclock
);
441 for (i
= 0; i
< inlen
; i
++)
442 ipc_data_writel(*in
++, 4 * i
);
444 ipc_command((sub
<< 12) | cmd
| (inlen
<< 18));
447 for (i
= 0; i
< outlen
; i
++)
448 *out
++ = ipc_data_readl(4 * i
);
450 mutex_unlock(&ipclock
);
453 EXPORT_SYMBOL(intel_scu_ipc_command
);
456 #define IPC_I2C_WRITE 1 /* I2C Write command */
457 #define IPC_I2C_READ 2 /* I2C Read command */
460 * intel_scu_ipc_i2c_cntrl - I2C read/write operations
461 * @addr: I2C address + command bits
462 * @data: data to read/write
464 * Perform an an I2C read/write operation via the SCU. All locking is
465 * handled for the caller. This function may sleep.
467 * Returns an error code or 0 on success.
469 * This has to be in the IPC driver for the locking.
471 int intel_scu_ipc_i2c_cntrl(u32 addr
, u32
*data
)
475 mutex_lock(&ipclock
);
476 if (ipcdev
.pdev
== NULL
) {
477 mutex_unlock(&ipclock
);
480 cmd
= (addr
>> 24) & 0xFF;
481 if (cmd
== IPC_I2C_READ
) {
482 writel(addr
, ipcdev
.i2c_base
+ IPC_I2C_CNTRL_ADDR
);
483 /* Write not getting updated without delay */
485 *data
= readl(ipcdev
.i2c_base
+ I2C_DATA_ADDR
);
486 } else if (cmd
== IPC_I2C_WRITE
) {
487 writel(addr
, ipcdev
.i2c_base
+ I2C_DATA_ADDR
);
489 writel(addr
, ipcdev
.i2c_base
+ IPC_I2C_CNTRL_ADDR
);
491 dev_err(&ipcdev
.pdev
->dev
,
492 "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd
);
494 mutex_unlock(&ipclock
);
497 mutex_unlock(&ipclock
);
500 EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl
);
502 #define IPC_FW_LOAD_ADDR 0xFFFC0000 /* Storage location for FW image */
503 #define IPC_FW_UPDATE_MBOX_ADDR 0xFFFFDFF4 /* Mailbox between ipc and scu */
504 #define IPC_MAX_FW_SIZE 262144 /* 256K storage size for loading the FW image */
505 #define IPC_FW_MIP_HEADER_SIZE 2048 /* Firmware MIP header size */
506 /* IPC inform SCU to get ready for update process */
507 #define IPC_CMD_FW_UPDATE_READY 0x10FE
508 /* IPC inform SCU to go for update process */
509 #define IPC_CMD_FW_UPDATE_GO 0x20FE
510 /* Status code for fw update */
511 #define IPC_FW_UPDATE_SUCCESS 0x444f4e45 /* Status code 'DONE' */
512 #define IPC_FW_UPDATE_BADN 0x4241444E /* Status code 'BADN' */
513 #define IPC_FW_TXHIGH 0x54784849 /* Status code 'IPC_FW_TXHIGH' */
514 #define IPC_FW_TXLOW 0x54784c4f /* Status code 'IPC_FW_TXLOW' */
516 struct fw_update_mailbox
{
524 * intel_scu_ipc_fw_update - Firmware update utility
525 * @buffer: firmware buffer
526 * @length: size of firmware buffer
528 * This function provides an interface to load the firmware into
529 * the SCU. Returns 0 on success or -1 on failure
531 int intel_scu_ipc_fw_update(u8
*buffer
, u32 length
)
533 void __iomem
*fw_update_base
;
534 struct fw_update_mailbox __iomem
*mailbox
= NULL
;
538 mutex_lock(&ipclock
);
539 fw_update_base
= ioremap_nocache(IPC_FW_LOAD_ADDR
, (128*1024));
540 if (fw_update_base
== NULL
) {
541 mutex_unlock(&ipclock
);
544 mailbox
= ioremap_nocache(IPC_FW_UPDATE_MBOX_ADDR
,
545 sizeof(struct fw_update_mailbox
));
546 if (mailbox
== NULL
) {
547 iounmap(fw_update_base
);
548 mutex_unlock(&ipclock
);
552 ipc_command(IPC_CMD_FW_UPDATE_READY
);
554 /* Intitialize mailbox */
555 writel(0, &mailbox
->status
);
556 writel(0, &mailbox
->scu_flag
);
557 writel(0, &mailbox
->driver_flag
);
559 /* Driver copies the 2KB MIP header to SRAM at 0xFFFC0000*/
560 memcpy_toio(fw_update_base
, buffer
, 0x800);
562 /* Driver sends "FW Update" IPC command (CMD_ID 0xFE; MSG_ID 0x02).
563 * Upon receiving this command, SCU will write the 2K MIP header
564 * from 0xFFFC0000 into NAND.
565 * SCU will write a status code into the Mailbox, and then set scu_flag.
568 ipc_command(IPC_CMD_FW_UPDATE_GO
);
570 /*Driver stalls until scu_flag is set */
571 while (readl(&mailbox
->scu_flag
) != 1) {
576 /* Driver checks Mailbox status.
577 * If the status is 'BADN', then abort (bad NAND).
578 * If the status is 'IPC_FW_TXLOW', then continue.
580 while (readl(&mailbox
->status
) != IPC_FW_TXLOW
) {
590 if (readl(&mailbox
->status
) != IPC_FW_TXLOW
)
592 buffer
= buffer
+ 0x800;
593 memcpy_toio(fw_update_base
, buffer
, 0x20000);
594 writel(1, &mailbox
->driver_flag
);
595 while (readl(&mailbox
->scu_flag
) == 1) {
600 /* check for 'BADN' */
601 if (readl(&mailbox
->status
) == IPC_FW_UPDATE_BADN
)
604 while (readl(&mailbox
->status
) != IPC_FW_TXHIGH
) {
610 if (readl(&mailbox
->status
) != IPC_FW_TXHIGH
)
613 buffer
= buffer
+ 0x20000;
614 memcpy_toio(fw_update_base
, buffer
, 0x20000);
615 writel(0, &mailbox
->driver_flag
);
617 while (mailbox
->scu_flag
== 0) {
622 /* check for 'BADN' */
623 if (readl(&mailbox
->status
) == IPC_FW_UPDATE_BADN
)
626 if (readl(&mailbox
->status
) == IPC_FW_TXLOW
) {
632 status
= readl(&mailbox
->status
);
634 iounmap(fw_update_base
);
636 mutex_unlock(&ipclock
);
638 if (status
== IPC_FW_UPDATE_SUCCESS
)
642 EXPORT_SYMBOL(intel_scu_ipc_fw_update
);
645 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
646 * When ioc bit is set to 1, caller api must wait for interrupt handler called
647 * which in turn unlocks the caller api. Currently this is not used
649 * This is edge triggered so we need take no action to clear anything
651 static irqreturn_t
ioc(int irq
, void *dev_id
)
657 * ipc_probe - probe an Intel SCU IPC
658 * @dev: the PCI device matching
659 * @id: entry in the match table
661 * Enable and install an intel SCU IPC. This appears in the PCI space
662 * but uses some hard coded addresses as well.
664 static int ipc_probe(struct pci_dev
*dev
, const struct pci_device_id
*id
)
667 resource_size_t pci_resource
;
669 if (ipcdev
.pdev
) /* We support only one SCU */
672 ipcdev
.pdev
= pci_dev_get(dev
);
674 err
= pci_enable_device(dev
);
678 err
= pci_request_regions(dev
, "intel_scu_ipc");
682 pci_resource
= pci_resource_start(dev
, 0);
686 if (request_irq(dev
->irq
, ioc
, 0, "intel_scu_ipc", &ipcdev
))
689 ipcdev
.ipc_base
= ioremap_nocache(IPC_BASE_ADDR
, IPC_MAX_ADDR
);
690 if (!ipcdev
.ipc_base
)
693 ipcdev
.i2c_base
= ioremap_nocache(IPC_I2C_BASE
, IPC_I2C_MAX_ADDR
);
694 if (!ipcdev
.i2c_base
) {
695 iounmap(ipcdev
.ipc_base
);
702 * ipc_remove - remove a bound IPC device
705 * In practice the SCU is not removable but this function is also
706 * called for each device on a module unload or cleanup which is the
707 * path that will get used.
709 * Free up the mappings and release the PCI resources
711 static void ipc_remove(struct pci_dev
*pdev
)
713 free_irq(pdev
->irq
, &ipcdev
);
714 pci_release_regions(pdev
);
715 pci_dev_put(ipcdev
.pdev
);
716 iounmap(ipcdev
.ipc_base
);
717 iounmap(ipcdev
.i2c_base
);
721 static const struct pci_device_id pci_ids
[] = {
722 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x080e)},
723 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x082a)},
726 MODULE_DEVICE_TABLE(pci
, pci_ids
);
728 static struct pci_driver ipc_driver
= {
729 .name
= "intel_scu_ipc",
732 .remove
= ipc_remove
,
736 static int __init
intel_scu_ipc_init(void)
738 platform
= mrst_identify_cpu();
741 return pci_register_driver(&ipc_driver
);
744 static void __exit
intel_scu_ipc_exit(void)
746 pci_unregister_driver(&ipc_driver
);
749 MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>");
750 MODULE_DESCRIPTION("Intel SCU IPC driver");
751 MODULE_LICENSE("GPL");
753 module_init(intel_scu_ipc_init
);
754 module_exit(intel_scu_ipc_exit
);