2 * PTP 1588 clock using the EG20T PCH
4 * Copyright (C) 2010 OMICRON electronics GmbH
5 * Copyright (C) 2011-2012 LAPIS SEMICONDUCTOR Co., LTD.
7 * This code was derived from the IXP46X driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
23 #include <linux/device.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/irq.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/ptp_clock_kernel.h>
34 #define STATION_ADDR_LEN 20
35 #define PCI_DEVICE_ID_PCH_1588 0x8819
38 #define DEFAULT_ADDEND 0xA0000000
39 #define TICKS_NS_SHIFT 5
46 PCH_INTERRUPTMODEINUSE
,
51 * struct pch_ts_regs - IEEE 1588 registers
90 #define PCH_TSC_RESET (1 << 0)
91 #define PCH_TSC_TTM_MASK (1 << 1)
92 #define PCH_TSC_ASMS_MASK (1 << 2)
93 #define PCH_TSC_AMMS_MASK (1 << 3)
94 #define PCH_TSC_PPSM_MASK (1 << 4)
95 #define PCH_TSE_TTIPEND (1 << 1)
96 #define PCH_TSE_SNS (1 << 2)
97 #define PCH_TSE_SNM (1 << 3)
98 #define PCH_TSE_PPS (1 << 4)
99 #define PCH_CC_MM (1 << 0)
100 #define PCH_CC_TA (1 << 1)
102 #define PCH_CC_MODE_SHIFT 16
103 #define PCH_CC_MODE_MASK 0x001F0000
104 #define PCH_CC_VERSION (1 << 31)
105 #define PCH_CE_TXS (1 << 0)
106 #define PCH_CE_RXS (1 << 1)
107 #define PCH_CE_OVR (1 << 0)
108 #define PCH_CE_VAL (1 << 1)
109 #define PCH_ECS_ETH (1 << 0)
111 #define PCH_ECS_CAN (1 << 1)
112 #define PCH_STATION_BYTES 6
114 #define PCH_IEEE1588_ETH (1 << 0)
115 #define PCH_IEEE1588_CAN (1 << 1)
117 * struct pch_dev - Driver private data
120 struct pch_ts_regs
*regs
;
121 struct ptp_clock
*ptp_clock
;
122 struct ptp_clock_info caps
;
129 struct pci_dev
*pdev
;
130 spinlock_t register_lock
;
134 * struct pch_params - 1588 module parameter
137 u8 station
[STATION_ADDR_LEN
];
140 /* structure to hold the module parameters */
141 static struct pch_params pch_param
= {
146 * Register access functions
148 static inline void pch_eth_enable_set(struct pch_dev
*chip
)
151 /* SET the eth_enable bit */
152 val
= ioread32(&chip
->regs
->ts_sel
) | (PCH_ECS_ETH
);
153 iowrite32(val
, (&chip
->regs
->ts_sel
));
156 static u64
pch_systime_read(struct pch_ts_regs
*regs
)
161 lo
= ioread32(®s
->systime_lo
);
162 hi
= ioread32(®s
->systime_hi
);
164 ns
= ((u64
) hi
) << 32;
166 ns
<<= TICKS_NS_SHIFT
;
171 static void pch_systime_write(struct pch_ts_regs
*regs
, u64 ns
)
175 ns
>>= TICKS_NS_SHIFT
;
177 lo
= ns
& 0xffffffff;
179 iowrite32(lo
, ®s
->systime_lo
);
180 iowrite32(hi
, ®s
->systime_hi
);
183 static inline void pch_block_reset(struct pch_dev
*chip
)
186 /* Reset Hardware Assist block */
187 val
= ioread32(&chip
->regs
->control
) | PCH_TSC_RESET
;
188 iowrite32(val
, (&chip
->regs
->control
));
189 val
= val
& ~PCH_TSC_RESET
;
190 iowrite32(val
, (&chip
->regs
->control
));
193 u32
pch_ch_control_read(struct pci_dev
*pdev
)
195 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
198 val
= ioread32(&chip
->regs
->ch_control
);
202 EXPORT_SYMBOL(pch_ch_control_read
);
204 void pch_ch_control_write(struct pci_dev
*pdev
, u32 val
)
206 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
208 iowrite32(val
, (&chip
->regs
->ch_control
));
210 EXPORT_SYMBOL(pch_ch_control_write
);
212 u32
pch_ch_event_read(struct pci_dev
*pdev
)
214 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
217 val
= ioread32(&chip
->regs
->ch_event
);
221 EXPORT_SYMBOL(pch_ch_event_read
);
223 void pch_ch_event_write(struct pci_dev
*pdev
, u32 val
)
225 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
227 iowrite32(val
, (&chip
->regs
->ch_event
));
229 EXPORT_SYMBOL(pch_ch_event_write
);
231 u32
pch_src_uuid_lo_read(struct pci_dev
*pdev
)
233 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
236 val
= ioread32(&chip
->regs
->src_uuid_lo
);
240 EXPORT_SYMBOL(pch_src_uuid_lo_read
);
242 u32
pch_src_uuid_hi_read(struct pci_dev
*pdev
)
244 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
247 val
= ioread32(&chip
->regs
->src_uuid_hi
);
251 EXPORT_SYMBOL(pch_src_uuid_hi_read
);
253 u64
pch_rx_snap_read(struct pci_dev
*pdev
)
255 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
259 lo
= ioread32(&chip
->regs
->rx_snap_lo
);
260 hi
= ioread32(&chip
->regs
->rx_snap_hi
);
262 ns
= ((u64
) hi
) << 32;
267 EXPORT_SYMBOL(pch_rx_snap_read
);
269 u64
pch_tx_snap_read(struct pci_dev
*pdev
)
271 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
275 lo
= ioread32(&chip
->regs
->tx_snap_lo
);
276 hi
= ioread32(&chip
->regs
->tx_snap_hi
);
278 ns
= ((u64
) hi
) << 32;
283 EXPORT_SYMBOL(pch_tx_snap_read
);
285 /* This function enables all 64 bits in system time registers [high & low].
286 This is a work-around for non continuous value in the SystemTime Register*/
287 static void pch_set_system_time_count(struct pch_dev
*chip
)
289 iowrite32(0x01, &chip
->regs
->stl_max_set_en
);
290 iowrite32(0xFFFFFFFF, &chip
->regs
->stl_max_set
);
291 iowrite32(0x00, &chip
->regs
->stl_max_set_en
);
294 static void pch_reset(struct pch_dev
*chip
)
296 /* Reset Hardware Assist */
297 pch_block_reset(chip
);
299 /* enable all 32 bits in system time registers */
300 pch_set_system_time_count(chip
);
304 * pch_set_station_address() - This API sets the station address used by
305 * IEEE 1588 hardware when looking at PTP
306 * traffic on the ethernet interface
307 * @addr: dress which contain the column separated address to be used.
309 static int pch_set_station_address(u8
*addr
, struct pci_dev
*pdev
)
312 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
314 /* Verify the parameter */
315 if ((chip
->regs
== 0) || addr
== (u8
*)NULL
) {
317 "invalid params returning PCH_INVALIDPARAM\n");
318 return PCH_INVALIDPARAM
;
320 /* For all station address bytes */
321 for (i
= 0; i
< PCH_STATION_BYTES
; i
++) {
325 tmp
= hex_to_bin(addr
[i
* 3]);
328 "invalid params returning PCH_INVALIDPARAM\n");
329 return PCH_INVALIDPARAM
;
332 tmp
= hex_to_bin(addr
[(i
* 3) + 1]);
335 "invalid params returning PCH_INVALIDPARAM\n");
336 return PCH_INVALIDPARAM
;
339 /* Expects ':' separated addresses */
340 if ((i
< 5) && (addr
[(i
* 3) + 2] != ':')) {
342 "invalid params returning PCH_INVALIDPARAM\n");
343 return PCH_INVALIDPARAM
;
346 /* Ideally we should set the address only after validating
348 dev_dbg(&pdev
->dev
, "invoking pch_station_set\n");
349 iowrite32(val
, &chip
->regs
->ts_st
[i
]);
355 * Interrupt service routine
357 static irqreturn_t
isr(int irq
, void *priv
)
359 struct pch_dev
*pch_dev
= priv
;
360 struct pch_ts_regs
*regs
= pch_dev
->regs
;
361 struct ptp_clock_event event
;
362 u32 ack
= 0, lo
, hi
, val
;
364 val
= ioread32(®s
->event
);
366 if (val
& PCH_TSE_SNS
) {
368 if (pch_dev
->exts0_enabled
) {
369 hi
= ioread32(®s
->asms_hi
);
370 lo
= ioread32(®s
->asms_lo
);
371 event
.type
= PTP_CLOCK_EXTTS
;
373 event
.timestamp
= ((u64
) hi
) << 32;
374 event
.timestamp
|= lo
;
375 event
.timestamp
<<= TICKS_NS_SHIFT
;
376 ptp_clock_event(pch_dev
->ptp_clock
, &event
);
380 if (val
& PCH_TSE_SNM
) {
382 if (pch_dev
->exts1_enabled
) {
383 hi
= ioread32(®s
->amms_hi
);
384 lo
= ioread32(®s
->amms_lo
);
385 event
.type
= PTP_CLOCK_EXTTS
;
387 event
.timestamp
= ((u64
) hi
) << 32;
388 event
.timestamp
|= lo
;
389 event
.timestamp
<<= TICKS_NS_SHIFT
;
390 ptp_clock_event(pch_dev
->ptp_clock
, &event
);
394 if (val
& PCH_TSE_TTIPEND
)
395 ack
|= PCH_TSE_TTIPEND
; /* this bit seems to be always set */
398 iowrite32(ack
, ®s
->event
);
405 * PTP clock operations
408 static int ptp_pch_adjfreq(struct ptp_clock_info
*ptp
, s32 ppb
)
413 struct pch_dev
*pch_dev
= container_of(ptp
, struct pch_dev
, caps
);
414 struct pch_ts_regs
*regs
= pch_dev
->regs
;
420 addend
= DEFAULT_ADDEND
;
423 diff
= div_u64(adj
, 1000000000ULL);
425 addend
= neg_adj
? addend
- diff
: addend
+ diff
;
427 iowrite32(addend
, ®s
->addend
);
432 static int ptp_pch_adjtime(struct ptp_clock_info
*ptp
, s64 delta
)
436 struct pch_dev
*pch_dev
= container_of(ptp
, struct pch_dev
, caps
);
437 struct pch_ts_regs
*regs
= pch_dev
->regs
;
439 spin_lock_irqsave(&pch_dev
->register_lock
, flags
);
440 now
= pch_systime_read(regs
);
442 pch_systime_write(regs
, now
);
443 spin_unlock_irqrestore(&pch_dev
->register_lock
, flags
);
448 static int ptp_pch_gettime(struct ptp_clock_info
*ptp
, struct timespec
*ts
)
453 struct pch_dev
*pch_dev
= container_of(ptp
, struct pch_dev
, caps
);
454 struct pch_ts_regs
*regs
= pch_dev
->regs
;
456 spin_lock_irqsave(&pch_dev
->register_lock
, flags
);
457 ns
= pch_systime_read(regs
);
458 spin_unlock_irqrestore(&pch_dev
->register_lock
, flags
);
460 ts
->tv_sec
= div_u64_rem(ns
, 1000000000, &remainder
);
461 ts
->tv_nsec
= remainder
;
465 static int ptp_pch_settime(struct ptp_clock_info
*ptp
,
466 const struct timespec
*ts
)
470 struct pch_dev
*pch_dev
= container_of(ptp
, struct pch_dev
, caps
);
471 struct pch_ts_regs
*regs
= pch_dev
->regs
;
473 ns
= ts
->tv_sec
* 1000000000ULL;
476 spin_lock_irqsave(&pch_dev
->register_lock
, flags
);
477 pch_systime_write(regs
, ns
);
478 spin_unlock_irqrestore(&pch_dev
->register_lock
, flags
);
483 static int ptp_pch_enable(struct ptp_clock_info
*ptp
,
484 struct ptp_clock_request
*rq
, int on
)
486 struct pch_dev
*pch_dev
= container_of(ptp
, struct pch_dev
, caps
);
489 case PTP_CLK_REQ_EXTTS
:
490 switch (rq
->extts
.index
) {
492 pch_dev
->exts0_enabled
= on
? 1 : 0;
495 pch_dev
->exts1_enabled
= on
? 1 : 0;
508 static struct ptp_clock_info ptp_pch_caps
= {
509 .owner
= THIS_MODULE
,
512 .n_ext_ts
= N_EXT_TS
,
514 .adjfreq
= ptp_pch_adjfreq
,
515 .adjtime
= ptp_pch_adjtime
,
516 .gettime
= ptp_pch_gettime
,
517 .settime
= ptp_pch_settime
,
518 .enable
= ptp_pch_enable
,
523 static s32
pch_suspend(struct pci_dev
*pdev
, pm_message_t state
)
525 pci_disable_device(pdev
);
526 pci_enable_wake(pdev
, PCI_D3hot
, 0);
528 if (pci_save_state(pdev
) != 0) {
529 dev_err(&pdev
->dev
, "could not save PCI config state\n");
532 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
537 static s32
pch_resume(struct pci_dev
*pdev
)
541 pci_set_power_state(pdev
, PCI_D0
);
542 pci_restore_state(pdev
);
543 ret
= pci_enable_device(pdev
);
545 dev_err(&pdev
->dev
, "pci_enable_device failed\n");
548 pci_enable_wake(pdev
, PCI_D3hot
, 0);
552 #define pch_suspend NULL
553 #define pch_resume NULL
556 static void __devexit
pch_remove(struct pci_dev
*pdev
)
558 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
560 ptp_clock_unregister(chip
->ptp_clock
);
561 /* free the interrupt */
563 free_irq(pdev
->irq
, chip
);
565 /* unmap the virtual IO memory space */
566 if (chip
->regs
!= 0) {
570 /* release the reserved IO memory space */
571 if (chip
->mem_base
!= 0) {
572 release_mem_region(chip
->mem_base
, chip
->mem_size
);
575 pci_disable_device(pdev
);
577 dev_info(&pdev
->dev
, "complete\n");
581 pch_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
585 struct pch_dev
*chip
;
587 chip
= kzalloc(sizeof(struct pch_dev
), GFP_KERNEL
);
591 /* enable the 1588 pci device */
592 ret
= pci_enable_device(pdev
);
594 dev_err(&pdev
->dev
, "could not enable the pci device\n");
598 chip
->mem_base
= pci_resource_start(pdev
, IO_MEM_BAR
);
599 if (!chip
->mem_base
) {
600 dev_err(&pdev
->dev
, "could not locate IO memory address\n");
605 /* retrieve the available length of the IO memory space */
606 chip
->mem_size
= pci_resource_len(pdev
, IO_MEM_BAR
);
608 /* allocate the memory for the device registers */
609 if (!request_mem_region(chip
->mem_base
, chip
->mem_size
, "1588_regs")) {
611 "could not allocate register memory space\n");
613 goto err_req_mem_region
;
616 /* get the virtual address to the 1588 registers */
617 chip
->regs
= ioremap(chip
->mem_base
, chip
->mem_size
);
620 dev_err(&pdev
->dev
, "Could not get virtual address\n");
625 chip
->caps
= ptp_pch_caps
;
626 chip
->ptp_clock
= ptp_clock_register(&chip
->caps
);
628 if (IS_ERR(chip
->ptp_clock
))
629 return PTR_ERR(chip
->ptp_clock
);
631 spin_lock_init(&chip
->register_lock
);
633 ret
= request_irq(pdev
->irq
, &isr
, IRQF_SHARED
, KBUILD_MODNAME
, chip
);
635 dev_err(&pdev
->dev
, "failed to get irq %d\n", pdev
->irq
);
639 /* indicate success */
640 chip
->irq
= pdev
->irq
;
642 pci_set_drvdata(pdev
, chip
);
644 spin_lock_irqsave(&chip
->register_lock
, flags
);
645 /* reset the ieee1588 h/w */
648 iowrite32(DEFAULT_ADDEND
, &chip
->regs
->addend
);
649 iowrite32(1, &chip
->regs
->trgt_lo
);
650 iowrite32(0, &chip
->regs
->trgt_hi
);
651 iowrite32(PCH_TSE_TTIPEND
, &chip
->regs
->event
);
652 /* Version: IEEE1588 v1 and IEEE1588-2008, Mode: All Evwnt, Locked */
653 iowrite32(0x80020000, &chip
->regs
->ch_control
);
655 pch_eth_enable_set(chip
);
657 if (strcmp(pch_param
.station
, "00:00:00:00:00:00") != 0) {
658 if (pch_set_station_address(pch_param
.station
, pdev
) != 0) {
660 "Invalid station address parameter\n"
661 "Module loaded but station address not set correctly\n"
665 spin_unlock_irqrestore(&chip
->register_lock
, flags
);
669 ptp_clock_unregister(chip
->ptp_clock
);
674 release_mem_region(chip
->mem_base
, chip
->mem_size
);
680 pci_disable_device(pdev
);
684 dev_err(&pdev
->dev
, "probe failed(ret=0x%x)\n", ret
);
689 static DEFINE_PCI_DEVICE_TABLE(pch_ieee1588_pcidev_id
) = {
691 .vendor
= PCI_VENDOR_ID_INTEL
,
692 .device
= PCI_DEVICE_ID_PCH_1588
697 static struct pci_driver pch_driver
= {
698 .name
= KBUILD_MODNAME
,
699 .id_table
= pch_ieee1588_pcidev_id
,
701 .remove
= pch_remove
,
702 .suspend
= pch_suspend
,
703 .resume
= pch_resume
,
706 static void __exit
ptp_pch_exit(void)
708 pci_unregister_driver(&pch_driver
);
711 static s32 __init
ptp_pch_init(void)
715 /* register the driver with the pci core */
716 ret
= pci_register_driver(&pch_driver
);
721 module_init(ptp_pch_init
);
722 module_exit(ptp_pch_exit
);
724 module_param_string(station
, pch_param
.station
, sizeof pch_param
.station
, 0444);
725 MODULE_PARM_DESC(station
,
726 "IEEE 1588 station address to use - column separated hex values");
728 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
729 MODULE_DESCRIPTION("PTP clock using the EG20T timer");
730 MODULE_LICENSE("GPL");