drivers/pwm/pwm-omap-dmtimer.c

   1 /*
   2  * Copyright (c) 2015 Neil Armstrong <narmstrong@baylibre.com>
   3  * Copyright (c) 2014 Joachim Eastwood <manabian@gmail.com>
   4  * Copyright (c) 2012 NeilBrown <neilb@suse.de>
   5  * Heavily based on earlier code which is:
   6  * Copyright (c) 2010 Grant Erickson <marathon96@gmail.com>
   7  *
   8  * Also based on pwm-samsung.c
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * version 2 as published by the Free Software Foundation.
  13  *
  14  * Description:
  15  *   This file is the core OMAP support for the generic, Linux
  16  *   PWM driver / controller, using the OMAP's dual-mode timers.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/err.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/mutex.h>
  24 #include <linux/of.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/platform_data/pwm_omap_dmtimer.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/pwm.h>
  30 #include <linux/slab.h>
  31 #include <linux/time.h>
  32
  33 #define DM_TIMER_LOAD_MIN 0xfffffffe
  34 #define DM_TIMER_MAX      0xffffffff
  35
  36 struct pwm_omap_dmtimer_chip {
  37         struct pwm_chip chip;
  38         struct mutex mutex;
  39         pwm_omap_dmtimer *dm_timer;
  40         struct pwm_omap_dmtimer_pdata *pdata;
  41         struct platform_device *dm_timer_pdev;
  42 };
  43
  44 static inline struct pwm_omap_dmtimer_chip *
  45 to_pwm_omap_dmtimer_chip(struct pwm_chip *chip)
  46 {
  47         return container_of(chip, struct pwm_omap_dmtimer_chip, chip);
  48 }
  49
  50 static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns)
  51 {
  52         u64 c = (u64)clk_rate * ns;
  53
  54         do_div(c, NSEC_PER_SEC);
  55
  56         return c;
  57 }
  58
  59 static void pwm_omap_dmtimer_start(struct pwm_omap_dmtimer_chip *omap)
  60 {
  61         /*
  62          * According to OMAP 4 TRM section 22.2.4.10 the counter should be
  63          * started at 0xFFFFFFFE when overflow and match is used to ensure
  64          * that the PWM line is toggled on the first event.
  65          *
  66          * Note that omap_dm_timer_enable/disable is for register access and
  67          * not the timer counter itself.
  68          */
  69         omap->pdata->enable(omap->dm_timer);
  70         omap->pdata->write_counter(omap->dm_timer, DM_TIMER_LOAD_MIN);
  71         omap->pdata->disable(omap->dm_timer);
  72
  73         omap->pdata->start(omap->dm_timer);
  74 }
  75
  76 static int pwm_omap_dmtimer_enable(struct pwm_chip *chip,
  77                                    struct pwm_device *pwm)
  78 {
  79         struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
  80
  81         mutex_lock(&omap->mutex);
  82         pwm_omap_dmtimer_start(omap);
  83         mutex_unlock(&omap->mutex);
  84
  85         return 0;
  86 }
  87
  88 static void pwm_omap_dmtimer_disable(struct pwm_chip *chip,
  89                                      struct pwm_device *pwm)
  90 {
  91         struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
  92
  93         mutex_lock(&omap->mutex);
  94         omap->pdata->stop(omap->dm_timer);
  95         mutex_unlock(&omap->mutex);
  96 }
  97
  98 static int pwm_omap_dmtimer_config(struct pwm_chip *chip,
  99                                    struct pwm_device *pwm,
 100                                    int duty_ns, int period_ns)
 101 {
 102         struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
 103         u32 period_cycles, duty_cycles;
 104         u32 load_value, match_value;
 105         struct clk *fclk;
 106         unsigned long clk_rate;
 107         bool timer_active;
 108
 109         dev_dbg(chip->dev, "duty cycle: %d, period %d\n", duty_ns, period_ns);
 110
 111         mutex_lock(&omap->mutex);
 112         if (duty_ns == pwm_get_duty_cycle(pwm) &&
 113             period_ns == pwm_get_period(pwm)) {
 114                 /* No change - don't cause any transients. */
 115                 mutex_unlock(&omap->mutex);
 116                 return 0;
 117         }
 118
 119         fclk = omap->pdata->get_fclk(omap->dm_timer);
 120         if (!fclk) {
 121                 dev_err(chip->dev, "invalid pmtimer fclk\n");
 122                 mutex_unlock(&omap->mutex);
 123                 return -EINVAL;
 124         }
 125
 126         clk_rate = clk_get_rate(fclk);
 127         if (!clk_rate) {
 128                 dev_err(chip->dev, "invalid pmtimer fclk rate\n");
 129                 mutex_unlock(&omap->mutex);
 130                 return -EINVAL;
 131         }
 132
 133         dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate);
 134
 135         /*
 136          * Calculate the appropriate load and match values based on the
 137          * specified period and duty cycle. The load value determines the
 138          * period time and the match value determines the duty time.
 139          *
 140          * The period lasts for (DM_TIMER_MAX-load_value+1) clock cycles.
 141          * Similarly, the active time lasts (match_value-load_value+1) cycles.
 142          * The non-active time is the remainder: (DM_TIMER_MAX-match_value)
 143          * clock cycles.
 144          *
 145          * References:
 146          *   OMAP4430/60/70 TRM sections 22.2.4.10 and 22.2.4.11
 147          *   AM335x Sitara TRM sections 20.1.3.5 and 20.1.3.6
 148          */
 149         period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
 150         duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);
 151
 152         load_value = (DM_TIMER_MAX - period_cycles) + 1;
 153         match_value = load_value + duty_cycles - 1;
 154
 155         /*
 156          * We MUST stop the associated dual-mode timer before attempting to
 157          * write its registers, but calls to omap_dm_timer_start/stop must
 158          * be balanced so check if timer is active before calling timer_stop.
 159          */
 160         timer_active = pm_runtime_active(&omap->dm_timer_pdev->dev);
 161         if (timer_active)
 162                 omap->pdata->stop(omap->dm_timer);
 163
 164         omap->pdata->set_load(omap->dm_timer, true, load_value);
 165         omap->pdata->set_match(omap->dm_timer, true, match_value);
 166
 167         dev_dbg(chip->dev, "load value: %#08x (%d), match value: %#08x (%d)\n",
 168                 load_value, load_value, match_value, match_value);
 169
 170         omap->pdata->set_pwm(omap->dm_timer,
 171                               pwm->polarity == PWM_POLARITY_INVERSED,
 172                               true,
 173                               PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
 174
 175         /* If config was called while timer was running it must be reenabled. */
 176         if (timer_active)
 177                 pwm_omap_dmtimer_start(omap);
 178
 179         mutex_unlock(&omap->mutex);
 180
 181         return 0;
 182 }
 183
 184 static int pwm_omap_dmtimer_set_polarity(struct pwm_chip *chip,
 185                                          struct pwm_device *pwm,
 186                                          enum pwm_polarity polarity)
 187 {
 188         struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
 189
 190         /*
 191          * PWM core will not call set_polarity while PWM is enabled so it's
 192          * safe to reconfigure the timer here without stopping it first.
 193          */
 194         mutex_lock(&omap->mutex);
 195         omap->pdata->set_pwm(omap->dm_timer,
 196                               polarity == PWM_POLARITY_INVERSED,
 197                               true,
 198                               PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
 199         mutex_unlock(&omap->mutex);
 200
 201         return 0;
 202 }
 203
 204 static const struct pwm_ops pwm_omap_dmtimer_ops = {
 205         .enable = pwm_omap_dmtimer_enable,
 206         .disable = pwm_omap_dmtimer_disable,
 207         .config = pwm_omap_dmtimer_config,
 208         .set_polarity = pwm_omap_dmtimer_set_polarity,
 209         .owner = THIS_MODULE,
 210 };
 211
 212 static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
 213 {
 214         struct device_node *np = pdev->dev.of_node;
 215         struct device_node *timer;
 216         struct pwm_omap_dmtimer_chip *omap;
 217         struct pwm_omap_dmtimer_pdata *pdata;
 218         pwm_omap_dmtimer *dm_timer;
 219         u32 prescaler;
 220         int status;
 221
 222         pdata = dev_get_platdata(&pdev->dev);
 223         if (!pdata) {
 224                 dev_err(&pdev->dev, "Missing dmtimer platform data\n");
 225                 return -EINVAL;
 226         }
 227
 228         if (!pdata->request_by_node ||
 229             !pdata->free ||
 230             !pdata->enable ||
 231             !pdata->disable ||
 232             !pdata->get_fclk ||
 233             !pdata->start ||
 234             !pdata->stop ||
 235             !pdata->set_load ||
 236             !pdata->set_match ||
 237             !pdata->set_pwm ||
 238             !pdata->set_prescaler ||
 239             !pdata->write_counter) {
 240                 dev_err(&pdev->dev, "Incomplete dmtimer pdata structure\n");
 241                 return -EINVAL;
 242         }
 243
 244         timer = of_parse_phandle(np, "ti,timers", 0);
 245         if (!timer)
 246                 return -ENODEV;
 247
 248         if (!of_get_property(timer, "ti,timer-pwm", NULL)) {
 249                 dev_err(&pdev->dev, "Missing ti,timer-pwm capability\n");
 250                 return -ENODEV;
 251         }
 252
 253         dm_timer = pdata->request_by_node(timer);
 254         if (!dm_timer)
 255                 return -EPROBE_DEFER;
 256
 257         omap = devm_kzalloc(&pdev->dev, sizeof(*omap), GFP_KERNEL);
 258         if (!omap) {
 259                 pdata->free(dm_timer);
 260                 return -ENOMEM;
 261         }
 262
 263         omap->pdata = pdata;
 264         omap->dm_timer = dm_timer;
 265
 266         omap->dm_timer_pdev = of_find_device_by_node(timer);
 267         if (!omap->dm_timer_pdev) {
 268                 dev_err(&pdev->dev, "Unable to find timer pdev\n");
 269                 omap->pdata->free(dm_timer);
 270                 return -EINVAL;
 271         }
 272
 273         /*
 274          * Ensure that the timer is stopped before we allow PWM core to call
 275          * pwm_enable.
 276          */
 277         if (pm_runtime_active(&omap->dm_timer_pdev->dev))
 278                 omap->pdata->stop(omap->dm_timer);
 279
 280         /* setup dmtimer prescaler */
 281         if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler",
 282                                 &prescaler))
 283                 omap->pdata->set_prescaler(omap->dm_timer, prescaler);
 284
 285         omap->chip.dev = &pdev->dev;
 286         omap->chip.ops = &pwm_omap_dmtimer_ops;
 287         omap->chip.base = -1;
 288         omap->chip.npwm = 1;
 289         omap->chip.of_xlate = of_pwm_xlate_with_flags;
 290         omap->chip.of_pwm_n_cells = 3;
 291
 292         mutex_init(&omap->mutex);
 293
 294         status = pwmchip_add(&omap->chip);
 295         if (status < 0) {
 296                 dev_err(&pdev->dev, "failed to register PWM\n");
 297                 omap->pdata->free(omap->dm_timer);
 298                 return status;
 299         }
 300
 301         platform_set_drvdata(pdev, omap);
 302
 303         return 0;
 304 }
 305
 306 static int pwm_omap_dmtimer_remove(struct platform_device *pdev)
 307 {
 308         struct pwm_omap_dmtimer_chip *omap = platform_get_drvdata(pdev);
 309
 310         if (pm_runtime_active(&omap->dm_timer_pdev->dev))
 311                 omap->pdata->stop(omap->dm_timer);
 312
 313         omap->pdata->free(omap->dm_timer);
 314
 315         mutex_destroy(&omap->mutex);
 316
 317         return pwmchip_remove(&omap->chip);
 318 }
 319
 320 static const struct of_device_id pwm_omap_dmtimer_of_match[] = {
 321         {.compatible = "ti,omap-dmtimer-pwm"},
 322         {}
 323 };
 324 MODULE_DEVICE_TABLE(of, pwm_omap_dmtimer_of_match);
 325
 326 static struct platform_driver pwm_omap_dmtimer_driver = {
 327         .driver = {
 328                 .name = "omap-dmtimer-pwm",
 329                 .of_match_table = of_match_ptr(pwm_omap_dmtimer_of_match),
 330         },
 331         .probe = pwm_omap_dmtimer_probe,
 332         .remove = pwm_omap_dmtimer_remove,
 333 };
 334 module_platform_driver(pwm_omap_dmtimer_driver);
 335
 336 MODULE_AUTHOR("Grant Erickson <marathon96@gmail.com>");
 337 MODULE_AUTHOR("NeilBrown <neilb@suse.de>");
 338 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
 339 MODULE_LICENSE("GPL v2");
 340 MODULE_DESCRIPTION("OMAP PWM Driver using Dual-mode Timers");