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ac89439a4f9a41c27c5755546a547c79f9176802
[deliverable/linux.git] / drivers / regulator / ab8500.c
1 /*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
8 * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
9 *
10 * AB8500 peripheral regulators
11 *
12 * AB8500 supports the following regulators:
13 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
14 *
15 * AB8505 supports the following regulators:
16 * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
17 */
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/mfd/abx500.h>
24 #include <linux/mfd/abx500/ab8500.h>
25 #include <linux/of.h>
26 #include <linux/regulator/of_regulator.h>
27 #include <linux/regulator/driver.h>
28 #include <linux/regulator/machine.h>
29 #include <linux/regulator/ab8500.h>
30 #include <linux/slab.h>
31
32 /**
33 * struct ab8500_shared_mode - is used when mode is shared between
34 * two regulators.
35 * @shared_regulator: pointer to the other sharing regulator
36 * @lp_mode_req: low power mode requested by this regulator
37 */
38 struct ab8500_shared_mode {
39 struct ab8500_regulator_info *shared_regulator;
40 bool lp_mode_req;
41 };
42
43 /**
44 * struct ab8500_regulator_info - ab8500 regulator information
45 * @dev: device pointer
46 * @desc: regulator description
47 * @regulator_dev: regulator device
48 * @shared_mode: used when mode is shared between two regulators
49 * @is_enabled: status of regulator (on/off)
50 * @load_lp_uA: maximum load in idle (low power) mode
51 * @update_bank: bank to control on/off
52 * @update_reg: register to control on/off
53 * @update_mask: mask to enable/disable and set mode of regulator
54 * @update_val: bits holding the regulator current mode
55 * @update_val_idle: bits to enable the regulator in idle (low power) mode
56 * @update_val_normal: bits to enable the regulator in normal (high power) mode
57 * @mode_bank: bank with location of mode register
58 * @mode_reg: mode register
59 * @mode_mask: mask for setting mode
60 * @mode_val_idle: mode setting for low power
61 * @mode_val_normal: mode setting for normal power
62 * @voltage_bank: bank to control regulator voltage
63 * @voltage_reg: register to control regulator voltage
64 * @voltage_mask: mask to control regulator voltage
65 * @voltage_shift: shift to control regulator voltage
66 */
67 struct ab8500_regulator_info {
68 struct device *dev;
69 struct regulator_desc desc;
70 struct regulator_dev *regulator;
71 struct ab8500_shared_mode *shared_mode;
72 bool is_enabled;
73 int load_lp_uA;
74 u8 update_bank;
75 u8 update_reg;
76 u8 update_mask;
77 u8 update_val;
78 u8 update_val_idle;
79 u8 update_val_normal;
80 u8 mode_bank;
81 u8 mode_reg;
82 u8 mode_mask;
83 u8 mode_val_idle;
84 u8 mode_val_normal;
85 u8 voltage_bank;
86 u8 voltage_reg;
87 u8 voltage_mask;
88 u8 voltage_shift;
89 struct {
90 u8 voltage_limit;
91 u8 voltage_bank;
92 u8 voltage_reg;
93 u8 voltage_mask;
94 u8 voltage_shift;
95 } expand_register;
96 };
97
98 /* voltage tables for the vauxn/vintcore supplies */
99 static const unsigned int ldo_vauxn_voltages[] = {
100 1100000,
101 1200000,
102 1300000,
103 1400000,
104 1500000,
105 1800000,
106 1850000,
107 1900000,
108 2500000,
109 2650000,
110 2700000,
111 2750000,
112 2800000,
113 2900000,
114 3000000,
115 3300000,
116 };
117
118 static const unsigned int ldo_vaux3_voltages[] = {
119 1200000,
120 1500000,
121 1800000,
122 2100000,
123 2500000,
124 2750000,
125 2790000,
126 2910000,
127 };
128
129 static const unsigned int ldo_vaux56_voltages[] = {
130 1800000,
131 1050000,
132 1100000,
133 1200000,
134 1500000,
135 2200000,
136 2500000,
137 2790000,
138 };
139
140 static const unsigned int ldo_vaux3_ab8540_voltages[] = {
141 1200000,
142 1500000,
143 1800000,
144 2100000,
145 2500000,
146 2750000,
147 2790000,
148 2910000,
149 3050000,
150 };
151
152 static const unsigned int ldo_vintcore_voltages[] = {
153 1200000,
154 1225000,
155 1250000,
156 1275000,
157 1300000,
158 1325000,
159 1350000,
160 };
161
162 static const unsigned int ldo_sdio_voltages[] = {
163 1160000,
164 1050000,
165 1100000,
166 1500000,
167 1800000,
168 2200000,
169 2910000,
170 3050000,
171 };
172
173 static const unsigned int fixed_1200000_voltage[] = {
174 1200000,
175 };
176
177 static const unsigned int fixed_1800000_voltage[] = {
178 1800000,
179 };
180
181 static const unsigned int fixed_2000000_voltage[] = {
182 2000000,
183 };
184
185 static const unsigned int fixed_2050000_voltage[] = {
186 2050000,
187 };
188
189 static const unsigned int fixed_3300000_voltage[] = {
190 3300000,
191 };
192
193 static const unsigned int ldo_vana_voltages[] = {
194 1050000,
195 1075000,
196 1100000,
197 1125000,
198 1150000,
199 1175000,
200 1200000,
201 1225000,
202 };
203
204 static const unsigned int ldo_vaudio_voltages[] = {
205 2000000,
206 2100000,
207 2200000,
208 2300000,
209 2400000,
210 2500000,
211 2600000,
212 2600000, /* Duplicated in Vaudio and IsoUicc Control register. */
213 };
214
215 static DEFINE_MUTEX(shared_mode_mutex);
216 static struct ab8500_shared_mode ldo_anamic1_shared;
217 static struct ab8500_shared_mode ldo_anamic2_shared;
218
219 static int ab8500_regulator_enable(struct regulator_dev *rdev)
220 {
221 int ret;
222 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
223
224 if (info == NULL) {
225 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
226 return -EINVAL;
227 }
228
229 ret = abx500_mask_and_set_register_interruptible(info->dev,
230 info->update_bank, info->update_reg,
231 info->update_mask, info->update_val);
232 if (ret < 0) {
233 dev_err(rdev_get_dev(rdev),
234 "couldn't set enable bits for regulator\n");
235 return ret;
236 }
237
238 info->is_enabled = true;
239
240 dev_vdbg(rdev_get_dev(rdev),
241 "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
242 info->desc.name, info->update_bank, info->update_reg,
243 info->update_mask, info->update_val);
244
245 return ret;
246 }
247
248 static int ab8500_regulator_disable(struct regulator_dev *rdev)
249 {
250 int ret;
251 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
252
253 if (info == NULL) {
254 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
255 return -EINVAL;
256 }
257
258 ret = abx500_mask_and_set_register_interruptible(info->dev,
259 info->update_bank, info->update_reg,
260 info->update_mask, 0x0);
261 if (ret < 0) {
262 dev_err(rdev_get_dev(rdev),
263 "couldn't set disable bits for regulator\n");
264 return ret;
265 }
266
267 info->is_enabled = false;
268
269 dev_vdbg(rdev_get_dev(rdev),
270 "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
271 info->desc.name, info->update_bank, info->update_reg,
272 info->update_mask, 0x0);
273
274 return ret;
275 }
276
277 static unsigned int ab8500_regulator_get_optimum_mode(
278 struct regulator_dev *rdev, int input_uV,
279 int output_uV, int load_uA)
280 {
281 unsigned int mode;
282
283 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
284
285 if (info == NULL) {
286 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
287 return -EINVAL;
288 }
289
290 if (load_uA <= info->load_lp_uA)
291 mode = REGULATOR_MODE_IDLE;
292 else
293 mode = REGULATOR_MODE_NORMAL;
294
295 return mode;
296 }
297
298 static int ab8500_regulator_set_mode(struct regulator_dev *rdev,
299 unsigned int mode)
300 {
301 int ret = 0;
302 u8 bank;
303 u8 reg;
304 u8 mask;
305 u8 val;
306 bool dmr = false; /* Dedicated mode register */
307 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
308
309 if (info == NULL) {
310 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
311 return -EINVAL;
312 }
313
314 if (info->shared_mode) {
315 /*
316 * Special case where mode is shared between two regulators.
317 */
318 struct ab8500_shared_mode *sm = info->shared_mode;
319 mutex_lock(&shared_mode_mutex);
320
321 if (mode == REGULATOR_MODE_IDLE) {
322 sm->lp_mode_req = true; /* Low power mode requested */
323 if (!((sm->shared_regulator)->
324 shared_mode->lp_mode_req)) {
325 mutex_unlock(&shared_mode_mutex);
326 return 0; /* Other regulator prevent LP mode */
327 }
328 } else {
329 sm->lp_mode_req = false;
330 }
331 }
332
333 if (info->mode_mask) {
334 /* Dedicated register for handling mode */
335
336 dmr = true;
337
338 switch (mode) {
339 case REGULATOR_MODE_NORMAL:
340 val = info->mode_val_normal;
341 break;
342 case REGULATOR_MODE_IDLE:
343 val = info->mode_val_idle;
344 break;
345 default:
346 if (info->shared_mode)
347 mutex_unlock(&shared_mode_mutex);
348 return -EINVAL;
349 }
350
351 bank = info->mode_bank;
352 reg = info->mode_reg;
353 mask = info->mode_mask;
354 } else {
355 /* Mode register same as enable register */
356
357 switch (mode) {
358 case REGULATOR_MODE_NORMAL:
359 info->update_val = info->update_val_normal;
360 val = info->update_val_normal;
361 break;
362 case REGULATOR_MODE_IDLE:
363 info->update_val = info->update_val_idle;
364 val = info->update_val_idle;
365 break;
366 default:
367 if (info->shared_mode)
368 mutex_unlock(&shared_mode_mutex);
369 return -EINVAL;
370 }
371
372 bank = info->update_bank;
373 reg = info->update_reg;
374 mask = info->update_mask;
375 }
376
377 if (info->is_enabled || dmr) {
378 ret = abx500_mask_and_set_register_interruptible(info->dev,
379 bank, reg, mask, val);
380 if (ret < 0)
381 dev_err(rdev_get_dev(rdev),
382 "couldn't set regulator mode\n");
383
384 dev_vdbg(rdev_get_dev(rdev),
385 "%s-set_mode (bank, reg, mask, value): "
386 "0x%x, 0x%x, 0x%x, 0x%x\n",
387 info->desc.name, bank, reg,
388 mask, val);
389 }
390
391 if (info->shared_mode)
392 mutex_unlock(&shared_mode_mutex);
393
394 return ret;
395 }
396
397 static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev)
398 {
399 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
400 int ret;
401 u8 val;
402 u8 val_normal;
403 u8 val_idle;
404
405 if (info == NULL) {
406 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
407 return -EINVAL;
408 }
409
410 /* Need special handling for shared mode */
411 if (info->shared_mode) {
412 if (info->shared_mode->lp_mode_req)
413 return REGULATOR_MODE_IDLE;
414 else
415 return REGULATOR_MODE_NORMAL;
416 }
417
418 if (info->mode_mask) {
419 /* Dedicated register for handling mode */
420 ret = abx500_get_register_interruptible(info->dev,
421 info->mode_bank, info->mode_reg, &val);
422 val = val & info->mode_mask;
423
424 val_normal = info->mode_val_normal;
425 val_idle = info->mode_val_idle;
426 } else {
427 /* Mode register same as enable register */
428 val = info->update_val;
429 val_normal = info->update_val_normal;
430 val_idle = info->update_val_idle;
431 }
432
433 if (val == val_normal)
434 ret = REGULATOR_MODE_NORMAL;
435 else if (val == val_idle)
436 ret = REGULATOR_MODE_IDLE;
437 else
438 ret = -EINVAL;
439
440 return ret;
441 }
442
443 static int ab8500_regulator_is_enabled(struct regulator_dev *rdev)
444 {
445 int ret;
446 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
447 u8 regval;
448
449 if (info == NULL) {
450 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
451 return -EINVAL;
452 }
453
454 ret = abx500_get_register_interruptible(info->dev,
455 info->update_bank, info->update_reg, &regval);
456 if (ret < 0) {
457 dev_err(rdev_get_dev(rdev),
458 "couldn't read 0x%x register\n", info->update_reg);
459 return ret;
460 }
461
462 dev_vdbg(rdev_get_dev(rdev),
463 "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
464 " 0x%x\n",
465 info->desc.name, info->update_bank, info->update_reg,
466 info->update_mask, regval);
467
468 if (regval & info->update_mask)
469 info->is_enabled = true;
470 else
471 info->is_enabled = false;
472
473 return info->is_enabled;
474 }
475
476 static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev)
477 {
478 int ret, val;
479 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
480 u8 regval;
481
482 if (info == NULL) {
483 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
484 return -EINVAL;
485 }
486
487 ret = abx500_get_register_interruptible(info->dev,
488 info->voltage_bank, info->voltage_reg, &regval);
489 if (ret < 0) {
490 dev_err(rdev_get_dev(rdev),
491 "couldn't read voltage reg for regulator\n");
492 return ret;
493 }
494
495 dev_vdbg(rdev_get_dev(rdev),
496 "%s-get_voltage (bank, reg, mask, shift, value): "
497 "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
498 info->desc.name, info->voltage_bank,
499 info->voltage_reg, info->voltage_mask,
500 info->voltage_shift, regval);
501
502 val = regval & info->voltage_mask;
503 return val >> info->voltage_shift;
504 }
505
506 static int ab8540_aux3_regulator_get_voltage_sel(struct regulator_dev *rdev)
507 {
508 int ret, val;
509 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
510 u8 regval, regval_expand;
511
512 if (info == NULL) {
513 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
514 return -EINVAL;
515 }
516
517 ret = abx500_get_register_interruptible(info->dev,
518 info->voltage_bank, info->voltage_reg, &regval);
519
520 if (ret < 0) {
521 dev_err(rdev_get_dev(rdev),
522 "couldn't read voltage reg for regulator\n");
523 return ret;
524 }
525
526 ret = abx500_get_register_interruptible(info->dev,
527 info->expand_register.voltage_bank,
528 info->expand_register.voltage_reg, &regval_expand);
529
530 if (ret < 0) {
531 dev_err(rdev_get_dev(rdev),
532 "couldn't read voltage reg for regulator\n");
533 return ret;
534 }
535
536 dev_vdbg(rdev_get_dev(rdev),
537 "%s-get_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
538 " 0x%x\n",
539 info->desc.name, info->voltage_bank, info->voltage_reg,
540 info->voltage_mask, regval);
541 dev_vdbg(rdev_get_dev(rdev),
542 "%s-get_voltage expand (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
543 " 0x%x\n",
544 info->desc.name, info->expand_register.voltage_bank,
545 info->expand_register.voltage_reg,
546 info->expand_register.voltage_mask, regval_expand);
547
548 if (regval_expand&(info->expand_register.voltage_mask))
549 /* Vaux3 has a different layout */
550 val = info->expand_register.voltage_limit;
551 else
552 val = (regval & info->voltage_mask) >> info->voltage_shift;
553
554 return val;
555 }
556
557 static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev,
558 unsigned selector)
559 {
560 int ret;
561 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
562 u8 regval;
563
564 if (info == NULL) {
565 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
566 return -EINVAL;
567 }
568
569 /* set the registers for the request */
570 regval = (u8)selector << info->voltage_shift;
571 ret = abx500_mask_and_set_register_interruptible(info->dev,
572 info->voltage_bank, info->voltage_reg,
573 info->voltage_mask, regval);
574 if (ret < 0)
575 dev_err(rdev_get_dev(rdev),
576 "couldn't set voltage reg for regulator\n");
577
578 dev_vdbg(rdev_get_dev(rdev),
579 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
580 " 0x%x\n",
581 info->desc.name, info->voltage_bank, info->voltage_reg,
582 info->voltage_mask, regval);
583
584 return ret;
585 }
586
587 static int ab8540_aux3_regulator_set_voltage_sel(struct regulator_dev *rdev,
588 unsigned selector)
589 {
590 int ret;
591 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
592 u8 regval;
593
594 if (info == NULL) {
595 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
596 return -EINVAL;
597 }
598
599 if (selector >= info->expand_register.voltage_limit) {
600 /* Vaux3 bit4 has different layout */
601 regval = (u8)selector << info->expand_register.voltage_shift;
602 ret = abx500_mask_and_set_register_interruptible(info->dev,
603 info->expand_register.voltage_bank,
604 info->expand_register.voltage_reg,
605 info->expand_register.voltage_mask,
606 regval);
607 } else {
608 /* set the registers for the request */
609 regval = (u8)selector << info->voltage_shift;
610 ret = abx500_mask_and_set_register_interruptible(info->dev,
611 info->voltage_bank, info->voltage_reg,
612 info->voltage_mask, regval);
613 }
614 if (ret < 0)
615 dev_err(rdev_get_dev(rdev),
616 "couldn't set voltage reg for regulator\n");
617
618 dev_vdbg(rdev_get_dev(rdev),
619 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
620 " 0x%x\n",
621 info->desc.name, info->voltage_bank, info->voltage_reg,
622 info->voltage_mask, regval);
623
624 return ret;
625 }
626
627 static int ab8500_regulator_set_voltage_time_sel(struct regulator_dev *rdev,
628 unsigned int old_sel,
629 unsigned int new_sel)
630 {
631 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
632
633 return info->delay;
634 }
635
636 static struct regulator_ops ab8500_regulator_volt_mode_ops = {
637 .enable = ab8500_regulator_enable,
638 .disable = ab8500_regulator_disable,
639 .is_enabled = ab8500_regulator_is_enabled,
640 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
641 .set_mode = ab8500_regulator_set_mode,
642 .get_mode = ab8500_regulator_get_mode,
643 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
644 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
645 .list_voltage = regulator_list_voltage_table,
646 };
647
648 static struct regulator_ops ab8540_aux3_regulator_volt_mode_ops = {
649 .enable = ab8500_regulator_enable,
650 .disable = ab8500_regulator_disable,
651 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
652 .set_mode = ab8500_regulator_set_mode,
653 .get_mode = ab8500_regulator_get_mode,
654 .is_enabled = ab8500_regulator_is_enabled,
655 .get_voltage_sel = ab8540_aux3_regulator_get_voltage_sel,
656 .set_voltage_sel = ab8540_aux3_regulator_set_voltage_sel,
657 .list_voltage = regulator_list_voltage_table,
658 .set_voltage_time_sel = ab8500_regulator_set_voltage_time_sel,
659 };
660
661 static struct regulator_ops ab8500_regulator_volt_ops = {
662 .enable = ab8500_regulator_enable,
663 .disable = ab8500_regulator_disable,
664 .is_enabled = ab8500_regulator_is_enabled,
665 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
666 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
667 .list_voltage = regulator_list_voltage_table,
668 .set_voltage_time_sel = ab8500_regulator_set_voltage_time_sel,
669 };
670
671 static struct regulator_ops ab8500_regulator_mode_ops = {
672 .enable = ab8500_regulator_enable,
673 .disable = ab8500_regulator_disable,
674 .is_enabled = ab8500_regulator_is_enabled,
675 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
676 .set_mode = ab8500_regulator_set_mode,
677 .get_mode = ab8500_regulator_get_mode,
678 .list_voltage = regulator_list_voltage_linear,
679 };
680
681 static struct regulator_ops ab8500_regulator_ops = {
682 .enable = ab8500_regulator_enable,
683 .disable = ab8500_regulator_disable,
684 .is_enabled = ab8500_regulator_is_enabled,
685 .list_voltage = regulator_list_voltage_linear,
686 };
687
688 static struct regulator_ops ab8500_regulator_anamic_mode_ops = {
689 .enable = ab8500_regulator_enable,
690 .disable = ab8500_regulator_disable,
691 .is_enabled = ab8500_regulator_is_enabled,
692 .set_mode = ab8500_regulator_set_mode,
693 .get_mode = ab8500_regulator_get_mode,
694 .list_voltage = regulator_list_voltage_table,
695 };
696
697 /* AB8500 regulator information */
698 static struct ab8500_regulator_info
699 ab8500_regulator_info[AB8500_NUM_REGULATORS] = {
700 /*
701 * Variable Voltage Regulators
702 * name, min mV, max mV,
703 * update bank, reg, mask, enable val
704 * volt bank, reg, mask
705 */
706 [AB8500_LDO_AUX1] = {
707 .desc = {
708 .name = "LDO-AUX1",
709 .ops = &ab8500_regulator_volt_mode_ops,
710 .type = REGULATOR_VOLTAGE,
711 .id = AB8500_LDO_AUX1,
712 .owner = THIS_MODULE,
713 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
714 .volt_table = ldo_vauxn_voltages,
715 .enable_time = 200,
716 },
717 .load_lp_uA = 5000,
718 .update_bank = 0x04,
719 .update_reg = 0x09,
720 .update_mask = 0x03,
721 .update_val = 0x01,
722 .update_val_idle = 0x03,
723 .update_val_normal = 0x01,
724 .voltage_bank = 0x04,
725 .voltage_reg = 0x1f,
726 .voltage_mask = 0x0f,
727 },
728 [AB8500_LDO_AUX2] = {
729 .desc = {
730 .name = "LDO-AUX2",
731 .ops = &ab8500_regulator_volt_mode_ops,
732 .type = REGULATOR_VOLTAGE,
733 .id = AB8500_LDO_AUX2,
734 .owner = THIS_MODULE,
735 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
736 .volt_table = ldo_vauxn_voltages,
737 .enable_time = 200,
738 },
739 .load_lp_uA = 5000,
740 .update_bank = 0x04,
741 .update_reg = 0x09,
742 .update_mask = 0x0c,
743 .update_val = 0x04,
744 .update_val_idle = 0x0c,
745 .update_val_normal = 0x04,
746 .voltage_bank = 0x04,
747 .voltage_reg = 0x20,
748 .voltage_mask = 0x0f,
749 },
750 [AB8500_LDO_AUX3] = {
751 .desc = {
752 .name = "LDO-AUX3",
753 .ops = &ab8500_regulator_volt_mode_ops,
754 .type = REGULATOR_VOLTAGE,
755 .id = AB8500_LDO_AUX3,
756 .owner = THIS_MODULE,
757 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
758 .volt_table = ldo_vaux3_voltages,
759 .enable_time = 450,
760 },
761 .load_lp_uA = 5000,
762 .update_bank = 0x04,
763 .update_reg = 0x0a,
764 .update_mask = 0x03,
765 .update_val = 0x01,
766 .update_val_idle = 0x03,
767 .update_val_normal = 0x01,
768 .voltage_bank = 0x04,
769 .voltage_reg = 0x21,
770 .voltage_mask = 0x07,
771 },
772 [AB8500_LDO_INTCORE] = {
773 .desc = {
774 .name = "LDO-INTCORE",
775 .ops = &ab8500_regulator_volt_mode_ops,
776 .type = REGULATOR_VOLTAGE,
777 .id = AB8500_LDO_INTCORE,
778 .owner = THIS_MODULE,
779 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
780 .volt_table = ldo_vintcore_voltages,
781 .enable_time = 750,
782 },
783 .load_lp_uA = 5000,
784 .update_bank = 0x03,
785 .update_reg = 0x80,
786 .update_mask = 0x44,
787 .update_val = 0x44,
788 .update_val_idle = 0x44,
789 .update_val_normal = 0x04,
790 .voltage_bank = 0x03,
791 .voltage_reg = 0x80,
792 .voltage_mask = 0x38,
793 .voltage_shift = 3,
794 },
795
796 /*
797 * Fixed Voltage Regulators
798 * name, fixed mV,
799 * update bank, reg, mask, enable val
800 */
801 [AB8500_LDO_TVOUT] = {
802 .desc = {
803 .name = "LDO-TVOUT",
804 .ops = &ab8500_regulator_mode_ops,
805 .type = REGULATOR_VOLTAGE,
806 .id = AB8500_LDO_TVOUT,
807 .owner = THIS_MODULE,
808 .n_voltages = 1,
809 .volt_table = fixed_2000000_voltage,
810 .enable_time = 500,
811 },
812 .load_lp_uA = 1000,
813 .update_bank = 0x03,
814 .update_reg = 0x80,
815 .update_mask = 0x82,
816 .update_val = 0x02,
817 .update_val_idle = 0x82,
818 .update_val_normal = 0x02,
819 },
820 [AB8500_LDO_AUDIO] = {
821 .desc = {
822 .name = "LDO-AUDIO",
823 .ops = &ab8500_regulator_ops,
824 .type = REGULATOR_VOLTAGE,
825 .id = AB8500_LDO_AUDIO,
826 .owner = THIS_MODULE,
827 .n_voltages = 1,
828 .enable_time = 140,
829 .volt_table = fixed_2000000_voltage,
830 },
831 .update_bank = 0x03,
832 .update_reg = 0x83,
833 .update_mask = 0x02,
834 .update_val = 0x02,
835 },
836 [AB8500_LDO_ANAMIC1] = {
837 .desc = {
838 .name = "LDO-ANAMIC1",
839 .ops = &ab8500_regulator_ops,
840 .type = REGULATOR_VOLTAGE,
841 .id = AB8500_LDO_ANAMIC1,
842 .owner = THIS_MODULE,
843 .n_voltages = 1,
844 .enable_time = 500,
845 .volt_table = fixed_2050000_voltage,
846 },
847 .update_bank = 0x03,
848 .update_reg = 0x83,
849 .update_mask = 0x08,
850 .update_val = 0x08,
851 },
852 [AB8500_LDO_ANAMIC2] = {
853 .desc = {
854 .name = "LDO-ANAMIC2",
855 .ops = &ab8500_regulator_ops,
856 .type = REGULATOR_VOLTAGE,
857 .id = AB8500_LDO_ANAMIC2,
858 .owner = THIS_MODULE,
859 .n_voltages = 1,
860 .enable_time = 500,
861 .volt_table = fixed_2050000_voltage,
862 },
863 .update_bank = 0x03,
864 .update_reg = 0x83,
865 .update_mask = 0x10,
866 .update_val = 0x10,
867 },
868 [AB8500_LDO_DMIC] = {
869 .desc = {
870 .name = "LDO-DMIC",
871 .ops = &ab8500_regulator_ops,
872 .type = REGULATOR_VOLTAGE,
873 .id = AB8500_LDO_DMIC,
874 .owner = THIS_MODULE,
875 .n_voltages = 1,
876 .enable_time = 420,
877 .volt_table = fixed_1800000_voltage,
878 },
879 .update_bank = 0x03,
880 .update_reg = 0x83,
881 .update_mask = 0x04,
882 .update_val = 0x04,
883 },
884
885 /*
886 * Regulators with fixed voltage and normal/idle modes
887 */
888 [AB8500_LDO_ANA] = {
889 .desc = {
890 .name = "LDO-ANA",
891 .ops = &ab8500_regulator_mode_ops,
892 .type = REGULATOR_VOLTAGE,
893 .id = AB8500_LDO_ANA,
894 .owner = THIS_MODULE,
895 .n_voltages = 1,
896 .enable_time = 140,
897 .volt_table = fixed_1200000_voltage,
898 },
899 .load_lp_uA = 1000,
900 .update_bank = 0x04,
901 .update_reg = 0x06,
902 .update_mask = 0x0c,
903 .update_val = 0x04,
904 .update_val_idle = 0x0c,
905 .update_val_normal = 0x04,
906 },
907 };
908
909 /* AB8505 regulator information */
910 static struct ab8500_regulator_info
911 ab8505_regulator_info[AB8505_NUM_REGULATORS] = {
912 /*
913 * Variable Voltage Regulators
914 * name, min mV, max mV,
915 * update bank, reg, mask, enable val
916 * volt bank, reg, mask, table, table length
917 */
918 [AB8505_LDO_AUX1] = {
919 .desc = {
920 .name = "LDO-AUX1",
921 .ops = &ab8500_regulator_volt_mode_ops,
922 .type = REGULATOR_VOLTAGE,
923 .id = AB8505_LDO_AUX1,
924 .owner = THIS_MODULE,
925 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
926 .volt_table = ldo_vauxn_voltages,
927 },
928 .load_lp_uA = 5000,
929 .update_bank = 0x04,
930 .update_reg = 0x09,
931 .update_mask = 0x03,
932 .update_val = 0x01,
933 .update_val_idle = 0x03,
934 .update_val_normal = 0x01,
935 .voltage_bank = 0x04,
936 .voltage_reg = 0x1f,
937 .voltage_mask = 0x0f,
938 },
939 [AB8505_LDO_AUX2] = {
940 .desc = {
941 .name = "LDO-AUX2",
942 .ops = &ab8500_regulator_volt_mode_ops,
943 .type = REGULATOR_VOLTAGE,
944 .id = AB8505_LDO_AUX2,
945 .owner = THIS_MODULE,
946 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
947 .volt_table = ldo_vauxn_voltages,
948 },
949 .load_lp_uA = 5000,
950 .update_bank = 0x04,
951 .update_reg = 0x09,
952 .update_mask = 0x0c,
953 .update_val = 0x04,
954 .update_val_idle = 0x0c,
955 .update_val_normal = 0x04,
956 .voltage_bank = 0x04,
957 .voltage_reg = 0x20,
958 .voltage_mask = 0x0f,
959 },
960 [AB8505_LDO_AUX3] = {
961 .desc = {
962 .name = "LDO-AUX3",
963 .ops = &ab8500_regulator_volt_mode_ops,
964 .type = REGULATOR_VOLTAGE,
965 .id = AB8505_LDO_AUX3,
966 .owner = THIS_MODULE,
967 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
968 .volt_table = ldo_vaux3_voltages,
969 },
970 .load_lp_uA = 5000,
971 .update_bank = 0x04,
972 .update_reg = 0x0a,
973 .update_mask = 0x03,
974 .update_val = 0x01,
975 .update_val_idle = 0x03,
976 .update_val_normal = 0x01,
977 .voltage_bank = 0x04,
978 .voltage_reg = 0x21,
979 .voltage_mask = 0x07,
980 },
981 [AB8505_LDO_AUX4] = {
982 .desc = {
983 .name = "LDO-AUX4",
984 .ops = &ab8500_regulator_volt_mode_ops,
985 .type = REGULATOR_VOLTAGE,
986 .id = AB8505_LDO_AUX4,
987 .owner = THIS_MODULE,
988 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
989 .volt_table = ldo_vauxn_voltages,
990 },
991 .load_lp_uA = 5000,
992 /* values for Vaux4Regu register */
993 .update_bank = 0x04,
994 .update_reg = 0x2e,
995 .update_mask = 0x03,
996 .update_val = 0x01,
997 .update_val_idle = 0x03,
998 .update_val_normal = 0x01,
999 /* values for Vaux4SEL register */
1000 .voltage_bank = 0x04,
1001 .voltage_reg = 0x2f,
1002 .voltage_mask = 0x0f,
1003 },
1004 [AB8505_LDO_AUX5] = {
1005 .desc = {
1006 .name = "LDO-AUX5",
1007 .ops = &ab8500_regulator_volt_mode_ops,
1008 .type = REGULATOR_VOLTAGE,
1009 .id = AB8505_LDO_AUX5,
1010 .owner = THIS_MODULE,
1011 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
1012 .volt_table = ldo_vaux56_voltages,
1013 },
1014 .load_lp_uA = 2000,
1015 /* values for CtrlVaux5 register */
1016 .update_bank = 0x01,
1017 .update_reg = 0x55,
1018 .update_mask = 0x18,
1019 .update_val = 0x10,
1020 .update_val_idle = 0x18,
1021 .update_val_normal = 0x10,
1022 .voltage_bank = 0x01,
1023 .voltage_reg = 0x55,
1024 .voltage_mask = 0x07,
1025 },
1026 [AB8505_LDO_AUX6] = {
1027 .desc = {
1028 .name = "LDO-AUX6",
1029 .ops = &ab8500_regulator_volt_mode_ops,
1030 .type = REGULATOR_VOLTAGE,
1031 .id = AB8505_LDO_AUX6,
1032 .owner = THIS_MODULE,
1033 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
1034 .volt_table = ldo_vaux56_voltages,
1035 },
1036 .load_lp_uA = 2000,
1037 /* values for CtrlVaux6 register */
1038 .update_bank = 0x01,
1039 .update_reg = 0x56,
1040 .update_mask = 0x18,
1041 .update_val = 0x10,
1042 .update_val_idle = 0x18,
1043 .update_val_normal = 0x10,
1044 .voltage_bank = 0x01,
1045 .voltage_reg = 0x56,
1046 .voltage_mask = 0x07,
1047 },
1048 [AB8505_LDO_INTCORE] = {
1049 .desc = {
1050 .name = "LDO-INTCORE",
1051 .ops = &ab8500_regulator_volt_mode_ops,
1052 .type = REGULATOR_VOLTAGE,
1053 .id = AB8505_LDO_INTCORE,
1054 .owner = THIS_MODULE,
1055 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
1056 .volt_table = ldo_vintcore_voltages,
1057 },
1058 .load_lp_uA = 5000,
1059 .update_bank = 0x03,
1060 .update_reg = 0x80,
1061 .update_mask = 0x44,
1062 .update_val = 0x04,
1063 .update_val_idle = 0x44,
1064 .update_val_normal = 0x04,
1065 .voltage_bank = 0x03,
1066 .voltage_reg = 0x80,
1067 .voltage_mask = 0x38,
1068 .voltage_shift = 3,
1069 },
1070
1071 /*
1072 * Fixed Voltage Regulators
1073 * name, fixed mV,
1074 * update bank, reg, mask, enable val
1075 */
1076 [AB8505_LDO_ADC] = {
1077 .desc = {
1078 .name = "LDO-ADC",
1079 .ops = &ab8500_regulator_mode_ops,
1080 .type = REGULATOR_VOLTAGE,
1081 .id = AB8505_LDO_ADC,
1082 .owner = THIS_MODULE,
1083 .n_voltages = 1,
1084 .volt_table = fixed_2000000_voltage,
1085 },
1086 .delay = 10000,
1087 .load_lp_uA = 1000,
1088 .update_bank = 0x03,
1089 .update_reg = 0x80,
1090 .update_mask = 0x82,
1091 .update_val = 0x02,
1092 .update_val_idle = 0x82,
1093 .update_val_normal = 0x02,
1094 },
1095 [AB8505_LDO_USB] = {
1096 .desc = {
1097 .name = "LDO-USB",
1098 .ops = &ab8500_regulator_mode_ops,
1099 .type = REGULATOR_VOLTAGE,
1100 .id = AB8505_LDO_USB,
1101 .owner = THIS_MODULE,
1102 .n_voltages = 1,
1103 .volt_table = fixed_3300000_voltage,
1104 },
1105 .update_bank = 0x03,
1106 .update_reg = 0x82,
1107 .update_mask = 0x03,
1108 .update_val = 0x01,
1109 .update_val_idle = 0x03,
1110 .update_val_normal = 0x01,
1111 },
1112 [AB8505_LDO_AUDIO] = {
1113 .desc = {
1114 .name = "LDO-AUDIO",
1115 .ops = &ab8500_regulator_volt_ops,
1116 .type = REGULATOR_VOLTAGE,
1117 .id = AB8505_LDO_AUDIO,
1118 .owner = THIS_MODULE,
1119 .n_voltages = ARRAY_SIZE(ldo_vaudio_voltages),
1120 .volt_table = ldo_vaudio_voltages,
1121 },
1122 .update_bank = 0x03,
1123 .update_reg = 0x83,
1124 .update_mask = 0x02,
1125 .update_val = 0x02,
1126 .voltage_bank = 0x01,
1127 .voltage_reg = 0x57,
1128 .voltage_mask = 0x7,
1129 .voltage_shift = 4,
1130 .voltages = ldo_vaudio_voltages,
1131 .voltages_len = ARRAY_SIZE(ldo_vaudio_voltages),
1132 },
1133 [AB8505_LDO_ANAMIC1] = {
1134 .desc = {
1135 .name = "LDO-ANAMIC1",
1136 .ops = &ab8500_regulator_anamic_mode_ops,
1137 .type = REGULATOR_VOLTAGE,
1138 .id = AB8505_LDO_ANAMIC1,
1139 .owner = THIS_MODULE,
1140 .n_voltages = 1,
1141 .volt_table = fixed_2050000_voltage,
1142 },
1143 .shared_mode = &ldo_anamic1_shared,
1144 .update_bank = 0x03,
1145 .update_reg = 0x83,
1146 .update_mask = 0x08,
1147 .update_val = 0x08,
1148 .mode_bank = 0x01,
1149 .mode_reg = 0x54,
1150 .mode_mask = 0x04,
1151 .mode_val_idle = 0x04,
1152 .mode_val_normal = 0x00,
1153 },
1154 [AB8505_LDO_ANAMIC2] = {
1155 .desc = {
1156 .name = "LDO-ANAMIC2",
1157 .ops = &ab8500_regulator_anamic_mode_ops,
1158 .type = REGULATOR_VOLTAGE,
1159 .id = AB8505_LDO_ANAMIC2,
1160 .owner = THIS_MODULE,
1161 .n_voltages = 1,
1162 .volt_table = fixed_2050000_voltage,
1163 },
1164 .shared_mode = &ldo_anamic2_shared,
1165 .update_bank = 0x03,
1166 .update_reg = 0x83,
1167 .update_mask = 0x10,
1168 .update_val = 0x10,
1169 .mode_bank = 0x01,
1170 .mode_reg = 0x54,
1171 .mode_mask = 0x04,
1172 .mode_val_idle = 0x04,
1173 .mode_val_normal = 0x00,
1174 },
1175 [AB8505_LDO_AUX8] = {
1176 .desc = {
1177 .name = "LDO-AUX8",
1178 .ops = &ab8500_regulator_ops,
1179 .type = REGULATOR_VOLTAGE,
1180 .id = AB8505_LDO_AUX8,
1181 .owner = THIS_MODULE,
1182 .n_voltages = 1,
1183 .volt_table = fixed_1800000_voltage,
1184 },
1185 .update_bank = 0x03,
1186 .update_reg = 0x83,
1187 .update_mask = 0x04,
1188 .update_val = 0x04,
1189 },
1190 /*
1191 * Regulators with fixed voltage and normal/idle modes
1192 */
1193 [AB8505_LDO_ANA] = {
1194 .desc = {
1195 .name = "LDO-ANA",
1196 .ops = &ab8500_regulator_volt_mode_ops,
1197 .type = REGULATOR_VOLTAGE,
1198 .id = AB8505_LDO_ANA,
1199 .owner = THIS_MODULE,
1200 .n_voltages = ARRAY_SIZE(ldo_vana_voltages),
1201 .volt_table = ldo_vana_voltages,
1202 },
1203 .load_lp_uA = 1000,
1204 .update_bank = 0x04,
1205 .update_reg = 0x06,
1206 .update_mask = 0x0c,
1207 .update_val = 0x04,
1208 .update_val_idle = 0x0c,
1209 .update_val_normal = 0x04,
1210 .voltage_bank = 0x04,
1211 .voltage_reg = 0x29,
1212 .voltage_mask = 0x7,
1213 .voltages = ldo_vana_voltages,
1214 .voltages_len = ARRAY_SIZE(ldo_vana_voltages),
1215 },
1216 };
1217
1218 /* AB9540 regulator information */
1219 static struct ab8500_regulator_info
1220 ab9540_regulator_info[AB9540_NUM_REGULATORS] = {
1221 /*
1222 * Variable Voltage Regulators
1223 * name, min mV, max mV,
1224 * update bank, reg, mask, enable val
1225 * volt bank, reg, mask, table, table length
1226 */
1227 [AB9540_LDO_AUX1] = {
1228 .desc = {
1229 .name = "LDO-AUX1",
1230 .ops = &ab8500_regulator_volt_mode_ops,
1231 .type = REGULATOR_VOLTAGE,
1232 .id = AB9540_LDO_AUX1,
1233 .owner = THIS_MODULE,
1234 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1235 .volt_table = ldo_vauxn_voltages,
1236 },
1237 .load_lp_uA = 5000,
1238 .update_bank = 0x04,
1239 .update_reg = 0x09,
1240 .update_mask = 0x03,
1241 .update_val = 0x01,
1242 .update_val_idle = 0x03,
1243 .update_val_normal = 0x01,
1244 .voltage_bank = 0x04,
1245 .voltage_reg = 0x1f,
1246 .voltage_mask = 0x0f,
1247 },
1248 [AB9540_LDO_AUX2] = {
1249 .desc = {
1250 .name = "LDO-AUX2",
1251 .ops = &ab8500_regulator_volt_mode_ops,
1252 .type = REGULATOR_VOLTAGE,
1253 .id = AB9540_LDO_AUX2,
1254 .owner = THIS_MODULE,
1255 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1256 .volt_table = ldo_vauxn_voltages,
1257 },
1258 .load_lp_uA = 5000,
1259 .update_bank = 0x04,
1260 .update_reg = 0x09,
1261 .update_mask = 0x0c,
1262 .update_val = 0x04,
1263 .update_val_idle = 0x0c,
1264 .update_val_normal = 0x04,
1265 .voltage_bank = 0x04,
1266 .voltage_reg = 0x20,
1267 .voltage_mask = 0x0f,
1268 },
1269 [AB9540_LDO_AUX3] = {
1270 .desc = {
1271 .name = "LDO-AUX3",
1272 .ops = &ab8500_regulator_volt_mode_ops,
1273 .type = REGULATOR_VOLTAGE,
1274 .id = AB9540_LDO_AUX3,
1275 .owner = THIS_MODULE,
1276 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
1277 .volt_table = ldo_vaux3_voltages,
1278 },
1279 .load_lp_uA = 5000,
1280 .update_bank = 0x04,
1281 .update_reg = 0x0a,
1282 .update_mask = 0x03,
1283 .update_val = 0x01,
1284 .update_val_idle = 0x03,
1285 .update_val_normal = 0x01,
1286 .voltage_bank = 0x04,
1287 .voltage_reg = 0x21,
1288 .voltage_mask = 0x07,
1289 },
1290 [AB9540_LDO_AUX4] = {
1291 .desc = {
1292 .name = "LDO-AUX4",
1293 .ops = &ab8500_regulator_volt_mode_ops,
1294 .type = REGULATOR_VOLTAGE,
1295 .id = AB9540_LDO_AUX4,
1296 .owner = THIS_MODULE,
1297 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1298 .volt_table = ldo_vauxn_voltages,
1299 },
1300 .load_lp_uA = 5000,
1301 /* values for Vaux4Regu register */
1302 .update_bank = 0x04,
1303 .update_reg = 0x2e,
1304 .update_mask = 0x03,
1305 .update_val = 0x01,
1306 .update_val_idle = 0x03,
1307 .update_val_normal = 0x01,
1308 /* values for Vaux4SEL register */
1309 .voltage_bank = 0x04,
1310 .voltage_reg = 0x2f,
1311 .voltage_mask = 0x0f,
1312 },
1313 [AB9540_LDO_INTCORE] = {
1314 .desc = {
1315 .name = "LDO-INTCORE",
1316 .ops = &ab8500_regulator_volt_mode_ops,
1317 .type = REGULATOR_VOLTAGE,
1318 .id = AB9540_LDO_INTCORE,
1319 .owner = THIS_MODULE,
1320 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
1321 .volt_table = ldo_vintcore_voltages,
1322 },
1323 .load_lp_uA = 5000,
1324 .update_bank = 0x03,
1325 .update_reg = 0x80,
1326 .update_mask = 0x44,
1327 .update_val = 0x44,
1328 .update_val_idle = 0x44,
1329 .update_val_normal = 0x04,
1330 .voltage_bank = 0x03,
1331 .voltage_reg = 0x80,
1332 .voltage_mask = 0x38,
1333 .voltage_shift = 3,
1334 },
1335
1336 /*
1337 * Fixed Voltage Regulators
1338 * name, fixed mV,
1339 * update bank, reg, mask, enable val
1340 */
1341 [AB9540_LDO_TVOUT] = {
1342 .desc = {
1343 .name = "LDO-TVOUT",
1344 .ops = &ab8500_regulator_mode_ops,
1345 .type = REGULATOR_VOLTAGE,
1346 .id = AB9540_LDO_TVOUT,
1347 .owner = THIS_MODULE,
1348 .n_voltages = 1,
1349 .volt_table = fixed_2000000_voltage,
1350 },
1351 .delay = 10000,
1352 .load_lp_uA = 1000,
1353 .update_bank = 0x03,
1354 .update_reg = 0x80,
1355 .update_mask = 0x82,
1356 .update_val = 0x02,
1357 .update_val_idle = 0x82,
1358 .update_val_normal = 0x02,
1359 },
1360 [AB9540_LDO_USB] = {
1361 .desc = {
1362 .name = "LDO-USB",
1363 .ops = &ab8500_regulator_ops,
1364 .type = REGULATOR_VOLTAGE,
1365 .id = AB9540_LDO_USB,
1366 .owner = THIS_MODULE,
1367 .n_voltages = 1,
1368 .volt_table = fixed_3300000_voltage,
1369 },
1370 .update_bank = 0x03,
1371 .update_reg = 0x82,
1372 .update_mask = 0x03,
1373 .update_val = 0x01,
1374 .update_val_idle = 0x03,
1375 .update_val_normal = 0x01,
1376 },
1377 [AB9540_LDO_AUDIO] = {
1378 .desc = {
1379 .name = "LDO-AUDIO",
1380 .ops = &ab8500_regulator_ops,
1381 .type = REGULATOR_VOLTAGE,
1382 .id = AB9540_LDO_AUDIO,
1383 .owner = THIS_MODULE,
1384 .n_voltages = 1,
1385 .volt_table = fixed_2000000_voltage,
1386 },
1387 .update_bank = 0x03,
1388 .update_reg = 0x83,
1389 .update_mask = 0x02,
1390 .update_val = 0x02,
1391 },
1392 [AB9540_LDO_ANAMIC1] = {
1393 .desc = {
1394 .name = "LDO-ANAMIC1",
1395 .ops = &ab8500_regulator_ops,
1396 .type = REGULATOR_VOLTAGE,
1397 .id = AB9540_LDO_ANAMIC1,
1398 .owner = THIS_MODULE,
1399 .n_voltages = 1,
1400 .volt_table = fixed_2050000_voltage,
1401 },
1402 .update_bank = 0x03,
1403 .update_reg = 0x83,
1404 .update_mask = 0x08,
1405 .update_val = 0x08,
1406 },
1407 [AB9540_LDO_ANAMIC2] = {
1408 .desc = {
1409 .name = "LDO-ANAMIC2",
1410 .ops = &ab8500_regulator_ops,
1411 .type = REGULATOR_VOLTAGE,
1412 .id = AB9540_LDO_ANAMIC2,
1413 .owner = THIS_MODULE,
1414 .n_voltages = 1,
1415 .volt_table = fixed_2050000_voltage,
1416 },
1417 .update_bank = 0x03,
1418 .update_reg = 0x83,
1419 .update_mask = 0x10,
1420 .update_val = 0x10,
1421 },
1422 [AB9540_LDO_DMIC] = {
1423 .desc = {
1424 .name = "LDO-DMIC",
1425 .ops = &ab8500_regulator_ops,
1426 .type = REGULATOR_VOLTAGE,
1427 .id = AB9540_LDO_DMIC,
1428 .owner = THIS_MODULE,
1429 .n_voltages = 1,
1430 .volt_table = fixed_1800000_voltage,
1431 },
1432 .update_bank = 0x03,
1433 .update_reg = 0x83,
1434 .update_mask = 0x04,
1435 .update_val = 0x04,
1436 },
1437
1438 /*
1439 * Regulators with fixed voltage and normal/idle modes
1440 */
1441 [AB9540_LDO_ANA] = {
1442 .desc = {
1443 .name = "LDO-ANA",
1444 .ops = &ab8500_regulator_mode_ops,
1445 .type = REGULATOR_VOLTAGE,
1446 .id = AB9540_LDO_ANA,
1447 .owner = THIS_MODULE,
1448 .n_voltages = 1,
1449 .volt_table = fixed_1200000_voltage,
1450 },
1451 .load_lp_uA = 1000,
1452 .update_bank = 0x04,
1453 .update_reg = 0x06,
1454 .update_mask = 0x0c,
1455 .update_val = 0x08,
1456 .update_val_idle = 0x0c,
1457 .update_val_normal = 0x08,
1458 },
1459 };
1460
1461 /* AB8540 regulator information */
1462 static struct ab8500_regulator_info
1463 ab8540_regulator_info[AB8540_NUM_REGULATORS] = {
1464 /*
1465 * Variable Voltage Regulators
1466 * name, min mV, max mV,
1467 * update bank, reg, mask, enable val
1468 * volt bank, reg, mask, table, table length
1469 */
1470 [AB8540_LDO_AUX1] = {
1471 .desc = {
1472 .name = "LDO-AUX1",
1473 .ops = &ab8500_regulator_volt_mode_ops,
1474 .type = REGULATOR_VOLTAGE,
1475 .id = AB8540_LDO_AUX1,
1476 .owner = THIS_MODULE,
1477 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1478 .volt_table = ldo_vauxn_voltages,
1479 },
1480 .load_lp_uA = 5000,
1481 .update_bank = 0x04,
1482 .update_reg = 0x09,
1483 .update_mask = 0x03,
1484 .update_val = 0x01,
1485 .update_val_idle = 0x03,
1486 .update_val_normal = 0x01,
1487 .voltage_bank = 0x04,
1488 .voltage_reg = 0x1f,
1489 .voltage_mask = 0x0f,
1490 },
1491 [AB8540_LDO_AUX2] = {
1492 .desc = {
1493 .name = "LDO-AUX2",
1494 .ops = &ab8500_regulator_volt_mode_ops,
1495 .type = REGULATOR_VOLTAGE,
1496 .id = AB8540_LDO_AUX2,
1497 .owner = THIS_MODULE,
1498 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1499 .volt_table = ldo_vauxn_voltages,
1500 },
1501 .load_lp_uA = 5000,
1502 .update_bank = 0x04,
1503 .update_reg = 0x09,
1504 .update_mask = 0x0c,
1505 .update_val = 0x04,
1506 .update_val_idle = 0x0c,
1507 .update_val_normal = 0x04,
1508 .voltage_bank = 0x04,
1509 .voltage_reg = 0x20,
1510 .voltage_mask = 0x0f,
1511 },
1512 [AB8540_LDO_AUX3] = {
1513 .desc = {
1514 .name = "LDO-AUX3",
1515 .ops = &ab8540_aux3_regulator_volt_mode_ops,
1516 .type = REGULATOR_VOLTAGE,
1517 .id = AB8540_LDO_AUX3,
1518 .owner = THIS_MODULE,
1519 .n_voltages = ARRAY_SIZE(ldo_vaux3_ab8540_voltages),
1520 .volt_table = ldo_vaux3_ab8540_voltages,
1521 },
1522 .load_lp_uA = 5000,
1523 .update_bank = 0x04,
1524 .update_reg = 0x0a,
1525 .update_mask = 0x03,
1526 .update_val = 0x01,
1527 .update_val_idle = 0x03,
1528 .update_val_normal = 0x01,
1529 .voltage_bank = 0x04,
1530 .voltage_reg = 0x21,
1531 .voltage_mask = 0x07,
1532 .expand_register = {
1533 .voltage_limit = 8,
1534 .voltage_bank = 0x04,
1535 .voltage_reg = 0x01,
1536 .voltage_mask = 0x10,
1537 .voltage_shift = 1,
1538 }
1539 },
1540 [AB8540_LDO_AUX4] = {
1541 .desc = {
1542 .name = "LDO-AUX4",
1543 .ops = &ab8500_regulator_volt_mode_ops,
1544 .type = REGULATOR_VOLTAGE,
1545 .id = AB8540_LDO_AUX4,
1546 .owner = THIS_MODULE,
1547 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1548 .volt_table = ldo_vauxn_voltages,
1549 },
1550 .load_lp_uA = 5000,
1551 /* values for Vaux4Regu register */
1552 .update_bank = 0x04,
1553 .update_reg = 0x2e,
1554 .update_mask = 0x03,
1555 .update_val = 0x01,
1556 .update_val_idle = 0x03,
1557 .update_val_normal = 0x01,
1558 /* values for Vaux4SEL register */
1559 .voltage_bank = 0x04,
1560 .voltage_reg = 0x2f,
1561 .voltage_mask = 0x0f,
1562 },
1563 [AB8540_LDO_INTCORE] = {
1564 .desc = {
1565 .name = "LDO-INTCORE",
1566 .ops = &ab8500_regulator_volt_mode_ops,
1567 .type = REGULATOR_VOLTAGE,
1568 .id = AB8540_LDO_INTCORE,
1569 .owner = THIS_MODULE,
1570 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
1571 .volt_table = ldo_vintcore_voltages,
1572 },
1573 .load_lp_uA = 5000,
1574 .update_bank = 0x03,
1575 .update_reg = 0x80,
1576 .update_mask = 0x44,
1577 .update_val = 0x44,
1578 .update_val_idle = 0x44,
1579 .update_val_normal = 0x04,
1580 .voltage_bank = 0x03,
1581 .voltage_reg = 0x80,
1582 .voltage_mask = 0x38,
1583 .voltage_shift = 3,
1584 },
1585
1586 /*
1587 * Fixed Voltage Regulators
1588 * name, fixed mV,
1589 * update bank, reg, mask, enable val
1590 */
1591 [AB8540_LDO_TVOUT] = {
1592 .desc = {
1593 .name = "LDO-TVOUT",
1594 .ops = &ab8500_regulator_mode_ops,
1595 .type = REGULATOR_VOLTAGE,
1596 .id = AB8540_LDO_TVOUT,
1597 .owner = THIS_MODULE,
1598 .n_voltages = 1,
1599 },
1600 .delay = 10000,
1601 .load_lp_uA = 1000,
1602 .update_bank = 0x03,
1603 .update_reg = 0x80,
1604 .update_mask = 0x82,
1605 .update_val = 0x02,
1606 .update_val_idle = 0x82,
1607 .update_val_normal = 0x02,
1608 },
1609 [AB8540_LDO_AUDIO] = {
1610 .desc = {
1611 .name = "LDO-AUDIO",
1612 .ops = &ab8500_regulator_ops,
1613 .type = REGULATOR_VOLTAGE,
1614 .id = AB8540_LDO_AUDIO,
1615 .owner = THIS_MODULE,
1616 .n_voltages = 1,
1617 .volt_table = fixed_2000000_voltage,
1618 },
1619 .update_bank = 0x03,
1620 .update_reg = 0x83,
1621 .update_mask = 0x02,
1622 .update_val = 0x02,
1623 },
1624 [AB8540_LDO_ANAMIC1] = {
1625 .desc = {
1626 .name = "LDO-ANAMIC1",
1627 .ops = &ab8500_regulator_ops,
1628 .type = REGULATOR_VOLTAGE,
1629 .id = AB8540_LDO_ANAMIC1,
1630 .owner = THIS_MODULE,
1631 .n_voltages = 1,
1632 .volt_table = fixed_2050000_voltage,
1633 },
1634 .update_bank = 0x03,
1635 .update_reg = 0x83,
1636 .update_mask = 0x08,
1637 .update_val = 0x08,
1638 },
1639 [AB8540_LDO_ANAMIC2] = {
1640 .desc = {
1641 .name = "LDO-ANAMIC2",
1642 .ops = &ab8500_regulator_ops,
1643 .type = REGULATOR_VOLTAGE,
1644 .id = AB8540_LDO_ANAMIC2,
1645 .owner = THIS_MODULE,
1646 .n_voltages = 1,
1647 .volt_table = fixed_2050000_voltage,
1648 },
1649 .update_bank = 0x03,
1650 .update_reg = 0x83,
1651 .update_mask = 0x10,
1652 .update_val = 0x10,
1653 },
1654 [AB8540_LDO_DMIC] = {
1655 .desc = {
1656 .name = "LDO-DMIC",
1657 .ops = &ab8500_regulator_ops,
1658 .type = REGULATOR_VOLTAGE,
1659 .id = AB8540_LDO_DMIC,
1660 .owner = THIS_MODULE,
1661 .n_voltages = 1,
1662 },
1663 .update_bank = 0x03,
1664 .update_reg = 0x83,
1665 .update_mask = 0x04,
1666 .update_val = 0x04,
1667 },
1668
1669 /*
1670 * Regulators with fixed voltage and normal/idle modes
1671 */
1672 [AB8540_LDO_ANA] = {
1673 .desc = {
1674 .name = "LDO-ANA",
1675 .ops = &ab8500_regulator_mode_ops,
1676 .type = REGULATOR_VOLTAGE,
1677 .id = AB8540_LDO_ANA,
1678 .owner = THIS_MODULE,
1679 .n_voltages = 1,
1680 .volt_table = fixed_1200000_voltage,
1681 },
1682 .load_lp_uA = 1000,
1683 .update_bank = 0x04,
1684 .update_reg = 0x06,
1685 .update_mask = 0x0c,
1686 .update_val = 0x04,
1687 .update_val_idle = 0x0c,
1688 .update_val_normal = 0x04,
1689 },
1690 [AB8540_LDO_SDIO] = {
1691 .desc = {
1692 .name = "LDO-SDIO",
1693 .ops = &ab8500_regulator_volt_mode_ops,
1694 .type = REGULATOR_VOLTAGE,
1695 .id = AB8540_LDO_SDIO,
1696 .owner = THIS_MODULE,
1697 .n_voltages = ARRAY_SIZE(ldo_sdio_voltages),
1698 .volt_table = ldo_sdio_voltages,
1699 },
1700 .load_lp_uA = 5000,
1701 .update_bank = 0x03,
1702 .update_reg = 0x88,
1703 .update_mask = 0x30,
1704 .update_val = 0x10,
1705 .update_val_idle = 0x30,
1706 .update_val_normal = 0x10,
1707 .voltage_bank = 0x03,
1708 .voltage_reg = 0x88,
1709 .voltage_mask = 0x07,
1710 },
1711 };
1712
1713 static struct ab8500_shared_mode ldo_anamic1_shared = {
1714 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC2],
1715 };
1716
1717 static struct ab8500_shared_mode ldo_anamic2_shared = {
1718 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC1],
1719 };
1720
1721 struct ab8500_reg_init {
1722 u8 bank;
1723 u8 addr;
1724 u8 mask;
1725 };
1726
1727 #define REG_INIT(_id, _bank, _addr, _mask) \
1728 [_id] = { \
1729 .bank = _bank, \
1730 .addr = _addr, \
1731 .mask = _mask, \
1732 }
1733
1734 /* AB8500 register init */
1735 static struct ab8500_reg_init ab8500_reg_init[] = {
1736 /*
1737 * 0x30, VanaRequestCtrl
1738 * 0xc0, VextSupply1RequestCtrl
1739 */
1740 REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0),
1741 /*
1742 * 0x03, VextSupply2RequestCtrl
1743 * 0x0c, VextSupply3RequestCtrl
1744 * 0x30, Vaux1RequestCtrl
1745 * 0xc0, Vaux2RequestCtrl
1746 */
1747 REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
1748 /*
1749 * 0x03, Vaux3RequestCtrl
1750 * 0x04, SwHPReq
1751 */
1752 REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1753 /*
1754 * 0x08, VanaSysClkReq1HPValid
1755 * 0x20, Vaux1SysClkReq1HPValid
1756 * 0x40, Vaux2SysClkReq1HPValid
1757 * 0x80, Vaux3SysClkReq1HPValid
1758 */
1759 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
1760 /*
1761 * 0x10, VextSupply1SysClkReq1HPValid
1762 * 0x20, VextSupply2SysClkReq1HPValid
1763 * 0x40, VextSupply3SysClkReq1HPValid
1764 */
1765 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
1766 /*
1767 * 0x08, VanaHwHPReq1Valid
1768 * 0x20, Vaux1HwHPReq1Valid
1769 * 0x40, Vaux2HwHPReq1Valid
1770 * 0x80, Vaux3HwHPReq1Valid
1771 */
1772 REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8),
1773 /*
1774 * 0x01, VextSupply1HwHPReq1Valid
1775 * 0x02, VextSupply2HwHPReq1Valid
1776 * 0x04, VextSupply3HwHPReq1Valid
1777 */
1778 REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
1779 /*
1780 * 0x08, VanaHwHPReq2Valid
1781 * 0x20, Vaux1HwHPReq2Valid
1782 * 0x40, Vaux2HwHPReq2Valid
1783 * 0x80, Vaux3HwHPReq2Valid
1784 */
1785 REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8),
1786 /*
1787 * 0x01, VextSupply1HwHPReq2Valid
1788 * 0x02, VextSupply2HwHPReq2Valid
1789 * 0x04, VextSupply3HwHPReq2Valid
1790 */
1791 REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
1792 /*
1793 * 0x20, VanaSwHPReqValid
1794 * 0x80, Vaux1SwHPReqValid
1795 */
1796 REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0),
1797 /*
1798 * 0x01, Vaux2SwHPReqValid
1799 * 0x02, Vaux3SwHPReqValid
1800 * 0x04, VextSupply1SwHPReqValid
1801 * 0x08, VextSupply2SwHPReqValid
1802 * 0x10, VextSupply3SwHPReqValid
1803 */
1804 REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
1805 /*
1806 * 0x02, SysClkReq2Valid1
1807 * 0x04, SysClkReq3Valid1
1808 * 0x08, SysClkReq4Valid1
1809 * 0x10, SysClkReq5Valid1
1810 * 0x20, SysClkReq6Valid1
1811 * 0x40, SysClkReq7Valid1
1812 * 0x80, SysClkReq8Valid1
1813 */
1814 REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
1815 /*
1816 * 0x02, SysClkReq2Valid2
1817 * 0x04, SysClkReq3Valid2
1818 * 0x08, SysClkReq4Valid2
1819 * 0x10, SysClkReq5Valid2
1820 * 0x20, SysClkReq6Valid2
1821 * 0x40, SysClkReq7Valid2
1822 * 0x80, SysClkReq8Valid2
1823 */
1824 REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
1825 /*
1826 * 0x02, VTVoutEna
1827 * 0x04, Vintcore12Ena
1828 * 0x38, Vintcore12Sel
1829 * 0x40, Vintcore12LP
1830 * 0x80, VTVoutLP
1831 */
1832 REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
1833 /*
1834 * 0x02, VaudioEna
1835 * 0x04, VdmicEna
1836 * 0x08, Vamic1Ena
1837 * 0x10, Vamic2Ena
1838 */
1839 REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
1840 /*
1841 * 0x01, Vamic1_dzout
1842 * 0x02, Vamic2_dzout
1843 */
1844 REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
1845 /*
1846 * 0x03, VpllRegu (NOTE! PRCMU register bits)
1847 * 0x0c, VanaRegu
1848 */
1849 REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
1850 /*
1851 * 0x01, VrefDDREna
1852 * 0x02, VrefDDRSleepMode
1853 */
1854 REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
1855 /*
1856 * 0x03, VextSupply1Regu
1857 * 0x0c, VextSupply2Regu
1858 * 0x30, VextSupply3Regu
1859 * 0x40, ExtSupply2Bypass
1860 * 0x80, ExtSupply3Bypass
1861 */
1862 REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
1863 /*
1864 * 0x03, Vaux1Regu
1865 * 0x0c, Vaux2Regu
1866 */
1867 REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
1868 /*
1869 * 0x03, Vaux3Regu
1870 */
1871 REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03),
1872 /*
1873 * 0x0f, Vaux1Sel
1874 */
1875 REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
1876 /*
1877 * 0x0f, Vaux2Sel
1878 */
1879 REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
1880 /*
1881 * 0x07, Vaux3Sel
1882 */
1883 REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07),
1884 /*
1885 * 0x01, VextSupply12LP
1886 */
1887 REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
1888 /*
1889 * 0x04, Vaux1Disch
1890 * 0x08, Vaux2Disch
1891 * 0x10, Vaux3Disch
1892 * 0x20, Vintcore12Disch
1893 * 0x40, VTVoutDisch
1894 * 0x80, VaudioDisch
1895 */
1896 REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
1897 /*
1898 * 0x02, VanaDisch
1899 * 0x04, VdmicPullDownEna
1900 * 0x10, VdmicDisch
1901 */
1902 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
1903 };
1904
1905 /* AB8505 register init */
1906 static struct ab8500_reg_init ab8505_reg_init[] = {
1907 /*
1908 * 0x03, VarmRequestCtrl
1909 * 0x0c, VsmpsCRequestCtrl
1910 * 0x30, VsmpsARequestCtrl
1911 * 0xc0, VsmpsBRequestCtrl
1912 */
1913 REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
1914 /*
1915 * 0x03, VsafeRequestCtrl
1916 * 0x0c, VpllRequestCtrl
1917 * 0x30, VanaRequestCtrl
1918 */
1919 REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f),
1920 /*
1921 * 0x30, Vaux1RequestCtrl
1922 * 0xc0, Vaux2RequestCtrl
1923 */
1924 REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0),
1925 /*
1926 * 0x03, Vaux3RequestCtrl
1927 * 0x04, SwHPReq
1928 */
1929 REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1930 /*
1931 * 0x01, VsmpsASysClkReq1HPValid
1932 * 0x02, VsmpsBSysClkReq1HPValid
1933 * 0x04, VsafeSysClkReq1HPValid
1934 * 0x08, VanaSysClkReq1HPValid
1935 * 0x10, VpllSysClkReq1HPValid
1936 * 0x20, Vaux1SysClkReq1HPValid
1937 * 0x40, Vaux2SysClkReq1HPValid
1938 * 0x80, Vaux3SysClkReq1HPValid
1939 */
1940 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
1941 /*
1942 * 0x01, VsmpsCSysClkReq1HPValid
1943 * 0x02, VarmSysClkReq1HPValid
1944 * 0x04, VbbSysClkReq1HPValid
1945 * 0x08, VsmpsMSysClkReq1HPValid
1946 */
1947 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f),
1948 /*
1949 * 0x01, VsmpsAHwHPReq1Valid
1950 * 0x02, VsmpsBHwHPReq1Valid
1951 * 0x04, VsafeHwHPReq1Valid
1952 * 0x08, VanaHwHPReq1Valid
1953 * 0x10, VpllHwHPReq1Valid
1954 * 0x20, Vaux1HwHPReq1Valid
1955 * 0x40, Vaux2HwHPReq1Valid
1956 * 0x80, Vaux3HwHPReq1Valid
1957 */
1958 REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
1959 /*
1960 * 0x08, VsmpsMHwHPReq1Valid
1961 */
1962 REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08),
1963 /*
1964 * 0x01, VsmpsAHwHPReq2Valid
1965 * 0x02, VsmpsBHwHPReq2Valid
1966 * 0x04, VsafeHwHPReq2Valid
1967 * 0x08, VanaHwHPReq2Valid
1968 * 0x10, VpllHwHPReq2Valid
1969 * 0x20, Vaux1HwHPReq2Valid
1970 * 0x40, Vaux2HwHPReq2Valid
1971 * 0x80, Vaux3HwHPReq2Valid
1972 */
1973 REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
1974 /*
1975 * 0x08, VsmpsMHwHPReq2Valid
1976 */
1977 REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08),
1978 /*
1979 * 0x01, VsmpsCSwHPReqValid
1980 * 0x02, VarmSwHPReqValid
1981 * 0x04, VsmpsASwHPReqValid
1982 * 0x08, VsmpsBSwHPReqValid
1983 * 0x10, VsafeSwHPReqValid
1984 * 0x20, VanaSwHPReqValid
1985 * 0x40, VpllSwHPReqValid
1986 * 0x80, Vaux1SwHPReqValid
1987 */
1988 REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
1989 /*
1990 * 0x01, Vaux2SwHPReqValid
1991 * 0x02, Vaux3SwHPReqValid
1992 * 0x20, VsmpsMSwHPReqValid
1993 */
1994 REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23),
1995 /*
1996 * 0x02, SysClkReq2Valid1
1997 * 0x04, SysClkReq3Valid1
1998 * 0x08, SysClkReq4Valid1
1999 */
2000 REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e),
2001 /*
2002 * 0x02, SysClkReq2Valid2
2003 * 0x04, SysClkReq3Valid2
2004 * 0x08, SysClkReq4Valid2
2005 */
2006 REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e),
2007 /*
2008 * 0x01, Vaux4SwHPReqValid
2009 * 0x02, Vaux4HwHPReq2Valid
2010 * 0x04, Vaux4HwHPReq1Valid
2011 * 0x08, Vaux4SysClkReq1HPValid
2012 */
2013 REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2014 /*
2015 * 0x02, VadcEna
2016 * 0x04, VintCore12Ena
2017 * 0x38, VintCore12Sel
2018 * 0x40, VintCore12LP
2019 * 0x80, VadcLP
2020 */
2021 REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe),
2022 /*
2023 * 0x02, VaudioEna
2024 * 0x04, VdmicEna
2025 * 0x08, Vamic1Ena
2026 * 0x10, Vamic2Ena
2027 */
2028 REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2029 /*
2030 * 0x01, Vamic1_dzout
2031 * 0x02, Vamic2_dzout
2032 */
2033 REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2034 /*
2035 * 0x03, VsmpsARegu
2036 * 0x0c, VsmpsASelCtrl
2037 * 0x10, VsmpsAAutoMode
2038 * 0x20, VsmpsAPWMMode
2039 */
2040 REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f),
2041 /*
2042 * 0x03, VsmpsBRegu
2043 * 0x0c, VsmpsBSelCtrl
2044 * 0x10, VsmpsBAutoMode
2045 * 0x20, VsmpsBPWMMode
2046 */
2047 REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f),
2048 /*
2049 * 0x03, VsafeRegu
2050 * 0x0c, VsafeSelCtrl
2051 * 0x10, VsafeAutoMode
2052 * 0x20, VsafePWMMode
2053 */
2054 REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f),
2055 /*
2056 * 0x03, VpllRegu (NOTE! PRCMU register bits)
2057 * 0x0c, VanaRegu
2058 */
2059 REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2060 /*
2061 * 0x03, VextSupply1Regu
2062 * 0x0c, VextSupply2Regu
2063 * 0x30, VextSupply3Regu
2064 * 0x40, ExtSupply2Bypass
2065 * 0x80, ExtSupply3Bypass
2066 */
2067 REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2068 /*
2069 * 0x03, Vaux1Regu
2070 * 0x0c, Vaux2Regu
2071 */
2072 REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f),
2073 /*
2074 * 0x0f, Vaux3Regu
2075 */
2076 REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2077 /*
2078 * 0x3f, VsmpsASel1
2079 */
2080 REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f),
2081 /*
2082 * 0x3f, VsmpsASel2
2083 */
2084 REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f),
2085 /*
2086 * 0x3f, VsmpsASel3
2087 */
2088 REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f),
2089 /*
2090 * 0x3f, VsmpsBSel1
2091 */
2092 REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f),
2093 /*
2094 * 0x3f, VsmpsBSel2
2095 */
2096 REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f),
2097 /*
2098 * 0x3f, VsmpsBSel3
2099 */
2100 REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f),
2101 /*
2102 * 0x7f, VsafeSel1
2103 */
2104 REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f),
2105 /*
2106 * 0x3f, VsafeSel2
2107 */
2108 REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f),
2109 /*
2110 * 0x3f, VsafeSel3
2111 */
2112 REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f),
2113 /*
2114 * 0x0f, Vaux1Sel
2115 */
2116 REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f),
2117 /*
2118 * 0x0f, Vaux2Sel
2119 */
2120 REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f),
2121 /*
2122 * 0x07, Vaux3Sel
2123 * 0x30, VRF1Sel
2124 */
2125 REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2126 /*
2127 * 0x03, Vaux4RequestCtrl
2128 */
2129 REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2130 /*
2131 * 0x03, Vaux4Regu
2132 */
2133 REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03),
2134 /*
2135 * 0x0f, Vaux4Sel
2136 */
2137 REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f),
2138 /*
2139 * 0x04, Vaux1Disch
2140 * 0x08, Vaux2Disch
2141 * 0x10, Vaux3Disch
2142 * 0x20, Vintcore12Disch
2143 * 0x40, VTVoutDisch
2144 * 0x80, VaudioDisch
2145 */
2146 REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
2147 /*
2148 * 0x02, VanaDisch
2149 * 0x04, VdmicPullDownEna
2150 * 0x10, VdmicDisch
2151 */
2152 REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
2153 /*
2154 * 0x01, Vaux4Disch
2155 */
2156 REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2157 /*
2158 * 0x07, Vaux5Sel
2159 * 0x08, Vaux5LP
2160 * 0x10, Vaux5Ena
2161 * 0x20, Vaux5Disch
2162 * 0x40, Vaux5DisSfst
2163 * 0x80, Vaux5DisPulld
2164 */
2165 REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff),
2166 /*
2167 * 0x07, Vaux6Sel
2168 * 0x08, Vaux6LP
2169 * 0x10, Vaux6Ena
2170 * 0x80, Vaux6DisPulld
2171 */
2172 REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f),
2173 };
2174
2175 /* AB9540 register init */
2176 static struct ab8500_reg_init ab9540_reg_init[] = {
2177 /*
2178 * 0x03, VarmRequestCtrl
2179 * 0x0c, VapeRequestCtrl
2180 * 0x30, Vsmps1RequestCtrl
2181 * 0xc0, Vsmps2RequestCtrl
2182 */
2183 REG_INIT(AB9540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2184 /*
2185 * 0x03, Vsmps3RequestCtrl
2186 * 0x0c, VpllRequestCtrl
2187 * 0x30, VanaRequestCtrl
2188 * 0xc0, VextSupply1RequestCtrl
2189 */
2190 REG_INIT(AB9540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2191 /*
2192 * 0x03, VextSupply2RequestCtrl
2193 * 0x0c, VextSupply3RequestCtrl
2194 * 0x30, Vaux1RequestCtrl
2195 * 0xc0, Vaux2RequestCtrl
2196 */
2197 REG_INIT(AB9540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2198 /*
2199 * 0x03, Vaux3RequestCtrl
2200 * 0x04, SwHPReq
2201 */
2202 REG_INIT(AB9540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2203 /*
2204 * 0x01, Vsmps1SysClkReq1HPValid
2205 * 0x02, Vsmps2SysClkReq1HPValid
2206 * 0x04, Vsmps3SysClkReq1HPValid
2207 * 0x08, VanaSysClkReq1HPValid
2208 * 0x10, VpllSysClkReq1HPValid
2209 * 0x20, Vaux1SysClkReq1HPValid
2210 * 0x40, Vaux2SysClkReq1HPValid
2211 * 0x80, Vaux3SysClkReq1HPValid
2212 */
2213 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2214 /*
2215 * 0x01, VapeSysClkReq1HPValid
2216 * 0x02, VarmSysClkReq1HPValid
2217 * 0x04, VbbSysClkReq1HPValid
2218 * 0x08, VmodSysClkReq1HPValid
2219 * 0x10, VextSupply1SysClkReq1HPValid
2220 * 0x20, VextSupply2SysClkReq1HPValid
2221 * 0x40, VextSupply3SysClkReq1HPValid
2222 */
2223 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x7f),
2224 /*
2225 * 0x01, Vsmps1HwHPReq1Valid
2226 * 0x02, Vsmps2HwHPReq1Valid
2227 * 0x04, Vsmps3HwHPReq1Valid
2228 * 0x08, VanaHwHPReq1Valid
2229 * 0x10, VpllHwHPReq1Valid
2230 * 0x20, Vaux1HwHPReq1Valid
2231 * 0x40, Vaux2HwHPReq1Valid
2232 * 0x80, Vaux3HwHPReq1Valid
2233 */
2234 REG_INIT(AB9540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2235 /*
2236 * 0x01, VextSupply1HwHPReq1Valid
2237 * 0x02, VextSupply2HwHPReq1Valid
2238 * 0x04, VextSupply3HwHPReq1Valid
2239 * 0x08, VmodHwHPReq1Valid
2240 */
2241 REG_INIT(AB9540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x0f),
2242 /*
2243 * 0x01, Vsmps1HwHPReq2Valid
2244 * 0x02, Vsmps2HwHPReq2Valid
2245 * 0x03, Vsmps3HwHPReq2Valid
2246 * 0x08, VanaHwHPReq2Valid
2247 * 0x10, VpllHwHPReq2Valid
2248 * 0x20, Vaux1HwHPReq2Valid
2249 * 0x40, Vaux2HwHPReq2Valid
2250 * 0x80, Vaux3HwHPReq2Valid
2251 */
2252 REG_INIT(AB9540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2253 /*
2254 * 0x01, VextSupply1HwHPReq2Valid
2255 * 0x02, VextSupply2HwHPReq2Valid
2256 * 0x04, VextSupply3HwHPReq2Valid
2257 * 0x08, VmodHwHPReq2Valid
2258 */
2259 REG_INIT(AB9540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x0f),
2260 /*
2261 * 0x01, VapeSwHPReqValid
2262 * 0x02, VarmSwHPReqValid
2263 * 0x04, Vsmps1SwHPReqValid
2264 * 0x08, Vsmps2SwHPReqValid
2265 * 0x10, Vsmps3SwHPReqValid
2266 * 0x20, VanaSwHPReqValid
2267 * 0x40, VpllSwHPReqValid
2268 * 0x80, Vaux1SwHPReqValid
2269 */
2270 REG_INIT(AB9540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2271 /*
2272 * 0x01, Vaux2SwHPReqValid
2273 * 0x02, Vaux3SwHPReqValid
2274 * 0x04, VextSupply1SwHPReqValid
2275 * 0x08, VextSupply2SwHPReqValid
2276 * 0x10, VextSupply3SwHPReqValid
2277 * 0x20, VmodSwHPReqValid
2278 */
2279 REG_INIT(AB9540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x3f),
2280 /*
2281 * 0x02, SysClkReq2Valid1
2282 * ...
2283 * 0x80, SysClkReq8Valid1
2284 */
2285 REG_INIT(AB9540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
2286 /*
2287 * 0x02, SysClkReq2Valid2
2288 * ...
2289 * 0x80, SysClkReq8Valid2
2290 */
2291 REG_INIT(AB9540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
2292 /*
2293 * 0x01, Vaux4SwHPReqValid
2294 * 0x02, Vaux4HwHPReq2Valid
2295 * 0x04, Vaux4HwHPReq1Valid
2296 * 0x08, Vaux4SysClkReq1HPValid
2297 */
2298 REG_INIT(AB9540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2299 /*
2300 * 0x02, VTVoutEna
2301 * 0x04, Vintcore12Ena
2302 * 0x38, Vintcore12Sel
2303 * 0x40, Vintcore12LP
2304 * 0x80, VTVoutLP
2305 */
2306 REG_INIT(AB9540_REGUMISC1, 0x03, 0x80, 0xfe),
2307 /*
2308 * 0x02, VaudioEna
2309 * 0x04, VdmicEna
2310 * 0x08, Vamic1Ena
2311 * 0x10, Vamic2Ena
2312 */
2313 REG_INIT(AB9540_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2314 /*
2315 * 0x01, Vamic1_dzout
2316 * 0x02, Vamic2_dzout
2317 */
2318 REG_INIT(AB9540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2319 /*
2320 * 0x03, Vsmps1Regu
2321 * 0x0c, Vsmps1SelCtrl
2322 * 0x10, Vsmps1AutoMode
2323 * 0x20, Vsmps1PWMMode
2324 */
2325 REG_INIT(AB9540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2326 /*
2327 * 0x03, Vsmps2Regu
2328 * 0x0c, Vsmps2SelCtrl
2329 * 0x10, Vsmps2AutoMode
2330 * 0x20, Vsmps2PWMMode
2331 */
2332 REG_INIT(AB9540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2333 /*
2334 * 0x03, Vsmps3Regu
2335 * 0x0c, Vsmps3SelCtrl
2336 * NOTE! PRCMU register
2337 */
2338 REG_INIT(AB9540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2339 /*
2340 * 0x03, VpllRegu
2341 * 0x0c, VanaRegu
2342 */
2343 REG_INIT(AB9540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2344 /*
2345 * 0x03, VextSupply1Regu
2346 * 0x0c, VextSupply2Regu
2347 * 0x30, VextSupply3Regu
2348 * 0x40, ExtSupply2Bypass
2349 * 0x80, ExtSupply3Bypass
2350 */
2351 REG_INIT(AB9540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2352 /*
2353 * 0x03, Vaux1Regu
2354 * 0x0c, Vaux2Regu
2355 */
2356 REG_INIT(AB9540_VAUX12REGU, 0x04, 0x09, 0x0f),
2357 /*
2358 * 0x0c, Vrf1Regu
2359 * 0x03, Vaux3Regu
2360 */
2361 REG_INIT(AB9540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2362 /*
2363 * 0x3f, Vsmps1Sel1
2364 */
2365 REG_INIT(AB9540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2366 /*
2367 * 0x3f, Vsmps1Sel2
2368 */
2369 REG_INIT(AB9540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2370 /*
2371 * 0x3f, Vsmps1Sel3
2372 */
2373 REG_INIT(AB9540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2374 /*
2375 * 0x3f, Vsmps2Sel1
2376 */
2377 REG_INIT(AB9540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2378 /*
2379 * 0x3f, Vsmps2Sel2
2380 */
2381 REG_INIT(AB9540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2382 /*
2383 * 0x3f, Vsmps2Sel3
2384 */
2385 REG_INIT(AB9540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2386 /*
2387 * 0x7f, Vsmps3Sel1
2388 * NOTE! PRCMU register
2389 */
2390 REG_INIT(AB9540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2391 /*
2392 * 0x7f, Vsmps3Sel2
2393 * NOTE! PRCMU register
2394 */
2395 REG_INIT(AB9540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2396 /*
2397 * 0x0f, Vaux1Sel
2398 */
2399 REG_INIT(AB9540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2400 /*
2401 * 0x0f, Vaux2Sel
2402 */
2403 REG_INIT(AB9540_VAUX2SEL, 0x04, 0x20, 0x0f),
2404 /*
2405 * 0x07, Vaux3Sel
2406 * 0x30, Vrf1Sel
2407 */
2408 REG_INIT(AB9540_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2409 /*
2410 * 0x01, VextSupply12LP
2411 */
2412 REG_INIT(AB9540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2413 /*
2414 * 0x03, Vaux4RequestCtrl
2415 */
2416 REG_INIT(AB9540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2417 /*
2418 * 0x03, Vaux4Regu
2419 */
2420 REG_INIT(AB9540_VAUX4REGU, 0x04, 0x2e, 0x03),
2421 /*
2422 * 0x08, Vaux4Sel
2423 */
2424 REG_INIT(AB9540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2425 /*
2426 * 0x01, VpllDisch
2427 * 0x02, Vrf1Disch
2428 * 0x04, Vaux1Disch
2429 * 0x08, Vaux2Disch
2430 * 0x10, Vaux3Disch
2431 * 0x20, Vintcore12Disch
2432 * 0x40, VTVoutDisch
2433 * 0x80, VaudioDisch
2434 */
2435 REG_INIT(AB9540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2436 /*
2437 * 0x01, VsimDisch
2438 * 0x02, VanaDisch
2439 * 0x04, VdmicPullDownEna
2440 * 0x08, VpllPullDownEna
2441 * 0x10, VdmicDisch
2442 */
2443 REG_INIT(AB9540_REGUCTRLDISCH2, 0x04, 0x44, 0x1f),
2444 /*
2445 * 0x01, Vaux4Disch
2446 */
2447 REG_INIT(AB9540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2448 };
2449
2450 /* AB8540 register init */
2451 static struct ab8500_reg_init ab8540_reg_init[] = {
2452 /*
2453 * 0x01, VSimSycClkReq1Valid
2454 * 0x02, VSimSycClkReq2Valid
2455 * 0x04, VSimSycClkReq3Valid
2456 * 0x08, VSimSycClkReq4Valid
2457 * 0x10, VSimSycClkReq5Valid
2458 * 0x20, VSimSycClkReq6Valid
2459 * 0x40, VSimSycClkReq7Valid
2460 * 0x80, VSimSycClkReq8Valid
2461 */
2462 REG_INIT(AB8540_VSIMSYSCLKCTRL, 0x02, 0x33, 0xff),
2463 /*
2464 * 0x03, VarmRequestCtrl
2465 * 0x0c, VapeRequestCtrl
2466 * 0x30, Vsmps1RequestCtrl
2467 * 0xc0, Vsmps2RequestCtrl
2468 */
2469 REG_INIT(AB8540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2470 /*
2471 * 0x03, Vsmps3RequestCtrl
2472 * 0x0c, VpllRequestCtrl
2473 * 0x30, VanaRequestCtrl
2474 * 0xc0, VextSupply1RequestCtrl
2475 */
2476 REG_INIT(AB8540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2477 /*
2478 * 0x03, VextSupply2RequestCtrl
2479 * 0x0c, VextSupply3RequestCtrl
2480 * 0x30, Vaux1RequestCtrl
2481 * 0xc0, Vaux2RequestCtrl
2482 */
2483 REG_INIT(AB8540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2484 /*
2485 * 0x03, Vaux3RequestCtrl
2486 * 0x04, SwHPReq
2487 */
2488 REG_INIT(AB8540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2489 /*
2490 * 0x01, Vsmps1SysClkReq1HPValid
2491 * 0x02, Vsmps2SysClkReq1HPValid
2492 * 0x04, Vsmps3SysClkReq1HPValid
2493 * 0x08, VanaSysClkReq1HPValid
2494 * 0x10, VpllSysClkReq1HPValid
2495 * 0x20, Vaux1SysClkReq1HPValid
2496 * 0x40, Vaux2SysClkReq1HPValid
2497 * 0x80, Vaux3SysClkReq1HPValid
2498 */
2499 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2500 /*
2501 * 0x01, VapeSysClkReq1HPValid
2502 * 0x02, VarmSysClkReq1HPValid
2503 * 0x04, VbbSysClkReq1HPValid
2504 * 0x10, VextSupply1SysClkReq1HPValid
2505 * 0x20, VextSupply2SysClkReq1HPValid
2506 * 0x40, VextSupply3SysClkReq1HPValid
2507 */
2508 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x77),
2509 /*
2510 * 0x01, Vsmps1HwHPReq1Valid
2511 * 0x02, Vsmps2HwHPReq1Valid
2512 * 0x04, Vsmps3HwHPReq1Valid
2513 * 0x08, VanaHwHPReq1Valid
2514 * 0x10, VpllHwHPReq1Valid
2515 * 0x20, Vaux1HwHPReq1Valid
2516 * 0x40, Vaux2HwHPReq1Valid
2517 * 0x80, Vaux3HwHPReq1Valid
2518 */
2519 REG_INIT(AB8540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2520 /*
2521 * 0x01, VextSupply1HwHPReq1Valid
2522 * 0x02, VextSupply2HwHPReq1Valid
2523 * 0x04, VextSupply3HwHPReq1Valid
2524 */
2525 REG_INIT(AB8540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
2526 /*
2527 * 0x01, Vsmps1HwHPReq2Valid
2528 * 0x02, Vsmps2HwHPReq2Valid
2529 * 0x03, Vsmps3HwHPReq2Valid
2530 * 0x08, VanaHwHPReq2Valid
2531 * 0x10, VpllHwHPReq2Valid
2532 * 0x20, Vaux1HwHPReq2Valid
2533 * 0x40, Vaux2HwHPReq2Valid
2534 * 0x80, Vaux3HwHPReq2Valid
2535 */
2536 REG_INIT(AB8540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2537 /*
2538 * 0x01, VextSupply1HwHPReq2Valid
2539 * 0x02, VextSupply2HwHPReq2Valid
2540 * 0x04, VextSupply3HwHPReq2Valid
2541 */
2542 REG_INIT(AB8540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
2543 /*
2544 * 0x01, VapeSwHPReqValid
2545 * 0x02, VarmSwHPReqValid
2546 * 0x04, Vsmps1SwHPReqValid
2547 * 0x08, Vsmps2SwHPReqValid
2548 * 0x10, Vsmps3SwHPReqValid
2549 * 0x20, VanaSwHPReqValid
2550 * 0x40, VpllSwHPReqValid
2551 * 0x80, Vaux1SwHPReqValid
2552 */
2553 REG_INIT(AB8540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2554 /*
2555 * 0x01, Vaux2SwHPReqValid
2556 * 0x02, Vaux3SwHPReqValid
2557 * 0x04, VextSupply1SwHPReqValid
2558 * 0x08, VextSupply2SwHPReqValid
2559 * 0x10, VextSupply3SwHPReqValid
2560 */
2561 REG_INIT(AB8540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
2562 /*
2563 * 0x02, SysClkReq2Valid1
2564 * ...
2565 * 0x80, SysClkReq8Valid1
2566 */
2567 REG_INIT(AB8540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xff),
2568 /*
2569 * 0x02, SysClkReq2Valid2
2570 * ...
2571 * 0x80, SysClkReq8Valid2
2572 */
2573 REG_INIT(AB8540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xff),
2574 /*
2575 * 0x01, Vaux4SwHPReqValid
2576 * 0x02, Vaux4HwHPReq2Valid
2577 * 0x04, Vaux4HwHPReq1Valid
2578 * 0x08, Vaux4SysClkReq1HPValid
2579 */
2580 REG_INIT(AB8540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2581 /*
2582 * 0x01, Vaux5SwHPReqValid
2583 * 0x02, Vaux5HwHPReq2Valid
2584 * 0x04, Vaux5HwHPReq1Valid
2585 * 0x08, Vaux5SysClkReq1HPValid
2586 */
2587 REG_INIT(AB8540_REGUVAUX5REQVALID, 0x03, 0x12, 0x0f),
2588 /*
2589 * 0x01, Vaux6SwHPReqValid
2590 * 0x02, Vaux6HwHPReq2Valid
2591 * 0x04, Vaux6HwHPReq1Valid
2592 * 0x08, Vaux6SysClkReq1HPValid
2593 */
2594 REG_INIT(AB8540_REGUVAUX6REQVALID, 0x03, 0x13, 0x0f),
2595 /*
2596 * 0x01, VclkbSwHPReqValid
2597 * 0x02, VclkbHwHPReq2Valid
2598 * 0x04, VclkbHwHPReq1Valid
2599 * 0x08, VclkbSysClkReq1HPValid
2600 */
2601 REG_INIT(AB8540_REGUVCLKBREQVALID, 0x03, 0x14, 0x0f),
2602 /*
2603 * 0x01, Vrf1SwHPReqValid
2604 * 0x02, Vrf1HwHPReq2Valid
2605 * 0x04, Vrf1HwHPReq1Valid
2606 * 0x08, Vrf1SysClkReq1HPValid
2607 */
2608 REG_INIT(AB8540_REGUVRF1REQVALID, 0x03, 0x15, 0x0f),
2609 /*
2610 * 0x02, VTVoutEna
2611 * 0x04, Vintcore12Ena
2612 * 0x38, Vintcore12Sel
2613 * 0x40, Vintcore12LP
2614 * 0x80, VTVoutLP
2615 */
2616 REG_INIT(AB8540_REGUMISC1, 0x03, 0x80, 0xfe),
2617 /*
2618 * 0x02, VaudioEna
2619 * 0x04, VdmicEna
2620 * 0x08, Vamic1Ena
2621 * 0x10, Vamic2Ena
2622 * 0x20, Vamic12LP
2623 * 0xC0, VdmicSel
2624 */
2625 REG_INIT(AB8540_VAUDIOSUPPLY, 0x03, 0x83, 0xfe),
2626 /*
2627 * 0x01, Vamic1_dzout
2628 * 0x02, Vamic2_dzout
2629 */
2630 REG_INIT(AB8540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2631 /*
2632 * 0x07, VHSICSel
2633 * 0x08, VHSICOffState
2634 * 0x10, VHSIEna
2635 * 0x20, VHSICLP
2636 */
2637 REG_INIT(AB8540_VHSIC, 0x03, 0x87, 0x3f),
2638 /*
2639 * 0x07, VSDIOSel
2640 * 0x08, VSDIOOffState
2641 * 0x10, VSDIOEna
2642 * 0x20, VSDIOLP
2643 */
2644 REG_INIT(AB8540_VSDIO, 0x03, 0x88, 0x3f),
2645 /*
2646 * 0x03, Vsmps1Regu
2647 * 0x0c, Vsmps1SelCtrl
2648 * 0x10, Vsmps1AutoMode
2649 * 0x20, Vsmps1PWMMode
2650 */
2651 REG_INIT(AB8540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2652 /*
2653 * 0x03, Vsmps2Regu
2654 * 0x0c, Vsmps2SelCtrl
2655 * 0x10, Vsmps2AutoMode
2656 * 0x20, Vsmps2PWMMode
2657 */
2658 REG_INIT(AB8540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2659 /*
2660 * 0x03, Vsmps3Regu
2661 * 0x0c, Vsmps3SelCtrl
2662 * 0x10, Vsmps3AutoMode
2663 * 0x20, Vsmps3PWMMode
2664 * NOTE! PRCMU register
2665 */
2666 REG_INIT(AB8540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2667 /*
2668 * 0x03, VpllRegu
2669 * 0x0c, VanaRegu
2670 */
2671 REG_INIT(AB8540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2672 /*
2673 * 0x03, VextSupply1Regu
2674 * 0x0c, VextSupply2Regu
2675 * 0x30, VextSupply3Regu
2676 * 0x40, ExtSupply2Bypass
2677 * 0x80, ExtSupply3Bypass
2678 */
2679 REG_INIT(AB8540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2680 /*
2681 * 0x03, Vaux1Regu
2682 * 0x0c, Vaux2Regu
2683 */
2684 REG_INIT(AB8540_VAUX12REGU, 0x04, 0x09, 0x0f),
2685 /*
2686 * 0x0c, VRF1Regu
2687 * 0x03, Vaux3Regu
2688 */
2689 REG_INIT(AB8540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2690 /*
2691 * 0x3f, Vsmps1Sel1
2692 */
2693 REG_INIT(AB8540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2694 /*
2695 * 0x3f, Vsmps1Sel2
2696 */
2697 REG_INIT(AB8540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2698 /*
2699 * 0x3f, Vsmps1Sel3
2700 */
2701 REG_INIT(AB8540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2702 /*
2703 * 0x3f, Vsmps2Sel1
2704 */
2705 REG_INIT(AB8540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2706 /*
2707 * 0x3f, Vsmps2Sel2
2708 */
2709 REG_INIT(AB8540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2710 /*
2711 * 0x3f, Vsmps2Sel3
2712 */
2713 REG_INIT(AB8540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2714 /*
2715 * 0x7f, Vsmps3Sel1
2716 * NOTE! PRCMU register
2717 */
2718 REG_INIT(AB8540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2719 /*
2720 * 0x7f, Vsmps3Sel2
2721 * NOTE! PRCMU register
2722 */
2723 REG_INIT(AB8540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2724 /*
2725 * 0x0f, Vaux1Sel
2726 */
2727 REG_INIT(AB8540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2728 /*
2729 * 0x0f, Vaux2Sel
2730 */
2731 REG_INIT(AB8540_VAUX2SEL, 0x04, 0x20, 0x0f),
2732 /*
2733 * 0x07, Vaux3Sel
2734 * 0x70, Vrf1Sel
2735 */
2736 REG_INIT(AB8540_VRF1VAUX3SEL, 0x04, 0x21, 0x77),
2737 /*
2738 * 0x01, VextSupply12LP
2739 */
2740 REG_INIT(AB8540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2741 /*
2742 * 0x07, Vanasel
2743 * 0x30, Vpllsel
2744 */
2745 REG_INIT(AB8540_VANAVPLLSEL, 0x04, 0x29, 0x37),
2746 /*
2747 * 0x03, Vaux4RequestCtrl
2748 */
2749 REG_INIT(AB8540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2750 /*
2751 * 0x03, Vaux4Regu
2752 */
2753 REG_INIT(AB8540_VAUX4REGU, 0x04, 0x2e, 0x03),
2754 /*
2755 * 0x0f, Vaux4Sel
2756 */
2757 REG_INIT(AB8540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2758 /*
2759 * 0x03, Vaux5RequestCtrl
2760 */
2761 REG_INIT(AB8540_VAUX5REQCTRL, 0x04, 0x31, 0x03),
2762 /*
2763 * 0x03, Vaux5Regu
2764 */
2765 REG_INIT(AB8540_VAUX5REGU, 0x04, 0x32, 0x03),
2766 /*
2767 * 0x3f, Vaux5Sel
2768 */
2769 REG_INIT(AB8540_VAUX5SEL, 0x04, 0x33, 0x3f),
2770 /*
2771 * 0x03, Vaux6RequestCtrl
2772 */
2773 REG_INIT(AB8540_VAUX6REQCTRL, 0x04, 0x34, 0x03),
2774 /*
2775 * 0x03, Vaux6Regu
2776 */
2777 REG_INIT(AB8540_VAUX6REGU, 0x04, 0x35, 0x03),
2778 /*
2779 * 0x3f, Vaux6Sel
2780 */
2781 REG_INIT(AB8540_VAUX6SEL, 0x04, 0x36, 0x3f),
2782 /*
2783 * 0x03, VCLKBRequestCtrl
2784 */
2785 REG_INIT(AB8540_VCLKBREQCTRL, 0x04, 0x37, 0x03),
2786 /*
2787 * 0x03, VCLKBRegu
2788 */
2789 REG_INIT(AB8540_VCLKBREGU, 0x04, 0x38, 0x03),
2790 /*
2791 * 0x07, VCLKBSel
2792 */
2793 REG_INIT(AB8540_VCLKBSEL, 0x04, 0x39, 0x07),
2794 /*
2795 * 0x03, Vrf1RequestCtrl
2796 */
2797 REG_INIT(AB8540_VRF1REQCTRL, 0x04, 0x3a, 0x03),
2798 /*
2799 * 0x01, VpllDisch
2800 * 0x02, Vrf1Disch
2801 * 0x04, Vaux1Disch
2802 * 0x08, Vaux2Disch
2803 * 0x10, Vaux3Disch
2804 * 0x20, Vintcore12Disch
2805 * 0x40, VTVoutDisch
2806 * 0x80, VaudioDisch
2807 */
2808 REG_INIT(AB8540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2809 /*
2810 * 0x02, VanaDisch
2811 * 0x04, VdmicPullDownEna
2812 * 0x08, VpllPullDownEna
2813 * 0x10, VdmicDisch
2814 */
2815 REG_INIT(AB8540_REGUCTRLDISCH2, 0x04, 0x44, 0x1e),
2816 /*
2817 * 0x01, Vaux4Disch
2818 */
2819 REG_INIT(AB8540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2820 /*
2821 * 0x01, Vaux5Disch
2822 * 0x02, Vaux6Disch
2823 * 0x04, VCLKBDisch
2824 */
2825 REG_INIT(AB8540_REGUCTRLDISCH4, 0x04, 0x49, 0x07),
2826 };
2827
2828 static int ab8500_regulator_init_registers(struct platform_device *pdev,
2829 struct ab8500_reg_init *reg_init,
2830 int id, int mask, int value)
2831 {
2832 int err;
2833
2834 BUG_ON(value & ~mask);
2835 BUG_ON(mask & ~reg_init[id].mask);
2836
2837 /* initialize register */
2838 err = abx500_mask_and_set_register_interruptible(
2839 &pdev->dev,
2840 reg_init[id].bank,
2841 reg_init[id].addr,
2842 mask, value);
2843 if (err < 0) {
2844 dev_err(&pdev->dev,
2845 "Failed to initialize 0x%02x, 0x%02x.\n",
2846 reg_init[id].bank,
2847 reg_init[id].addr);
2848 return err;
2849 }
2850 dev_vdbg(&pdev->dev,
2851 " init: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
2852 reg_init[id].bank,
2853 reg_init[id].addr,
2854 mask, value);
2855
2856 return 0;
2857 }
2858
2859 static int ab8500_regulator_register(struct platform_device *pdev,
2860 struct regulator_init_data *init_data,
2861 struct ab8500_regulator_info *regulator_info,
2862 int id, struct device_node *np)
2863 {
2864 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
2865 struct ab8500_regulator_info *info = NULL;
2866 struct regulator_config config = { };
2867 int err;
2868
2869 /* assign per-regulator data */
2870 info = &regulator_info[id];
2871 info->dev = &pdev->dev;
2872
2873 config.dev = &pdev->dev;
2874 config.init_data = init_data;
2875 config.driver_data = info;
2876 config.of_node = np;
2877
2878 /* fix for hardware before ab8500v2.0 */
2879 if (is_ab8500_1p1_or_earlier(ab8500)) {
2880 if (info->desc.id == AB8500_LDO_AUX3) {
2881 info->desc.n_voltages =
2882 ARRAY_SIZE(ldo_vauxn_voltages);
2883 info->desc.volt_table = ldo_vauxn_voltages;
2884 info->voltage_mask = 0xf;
2885 }
2886 }
2887
2888 /* register regulator with framework */
2889 info->regulator = regulator_register(&info->desc, &config);
2890 if (IS_ERR(info->regulator)) {
2891 err = PTR_ERR(info->regulator);
2892 dev_err(&pdev->dev, "failed to register regulator %s\n",
2893 info->desc.name);
2894 /* when we fail, un-register all earlier regulators */
2895 while (--id >= 0) {
2896 info = &regulator_info[id];
2897 regulator_unregister(info->regulator);
2898 }
2899 return err;
2900 }
2901
2902 return 0;
2903 }
2904
2905 static struct of_regulator_match ab8500_regulator_match[] = {
2906 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, },
2907 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, },
2908 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, },
2909 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, },
2910 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, },
2911 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, },
2912 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
2913 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
2914 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, },
2915 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, },
2916 };
2917
2918 static struct of_regulator_match ab8505_regulator_match[] = {
2919 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, },
2920 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, },
2921 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, },
2922 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, },
2923 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, },
2924 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, },
2925 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, },
2926 { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, },
2927 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, },
2928 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, },
2929 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
2930 { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, },
2931 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, },
2932 };
2933
2934 static struct of_regulator_match ab8540_regulator_match[] = {
2935 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8540_LDO_AUX1, },
2936 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8540_LDO_AUX2, },
2937 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8540_LDO_AUX3, },
2938 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8540_LDO_AUX4, },
2939 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8540_LDO_INTCORE, },
2940 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8540_LDO_TVOUT, },
2941 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8540_LDO_AUDIO, },
2942 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, },
2943 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, },
2944 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8540_LDO_DMIC, },
2945 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8540_LDO_ANA, },
2946 { .name = "ab8500_ldo_sdio", .driver_data = (void *) AB8540_LDO_SDIO, },
2947 };
2948
2949 static struct of_regulator_match ab9540_regulator_match[] = {
2950 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB9540_LDO_AUX1, },
2951 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB9540_LDO_AUX2, },
2952 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB9540_LDO_AUX3, },
2953 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB9540_LDO_AUX4, },
2954 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB9540_LDO_INTCORE, },
2955 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB9540_LDO_TVOUT, },
2956 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB9540_LDO_AUDIO, },
2957 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, },
2958 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, },
2959 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB9540_LDO_DMIC, },
2960 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB9540_LDO_ANA, },
2961 };
2962
2963 static int
2964 ab8500_regulator_of_probe(struct platform_device *pdev,
2965 struct ab8500_regulator_info *regulator_info,
2966 int regulator_info_size,
2967 struct of_regulator_match *match,
2968 struct device_node *np)
2969 {
2970 int err, i;
2971
2972 for (i = 0; i < regulator_info_size; i++) {
2973 err = ab8500_regulator_register(
2974 pdev, match[i].init_data, regulator_info,
2975 i, match[i].of_node);
2976 if (err)
2977 return err;
2978 }
2979
2980 return 0;
2981 }
2982
2983 static int ab8500_regulator_probe(struct platform_device *pdev)
2984 {
2985 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
2986 struct device_node *np = pdev->dev.of_node;
2987 struct of_regulator_match *match;
2988 struct ab8500_platform_data *ppdata;
2989 struct ab8500_regulator_platform_data *pdata;
2990 int i, err;
2991 struct ab8500_regulator_info *regulator_info;
2992 int regulator_info_size;
2993 struct ab8500_reg_init *reg_init;
2994 int reg_init_size;
2995
2996 if (is_ab9540(ab8500)) {
2997 regulator_info = ab9540_regulator_info;
2998 regulator_info_size = ARRAY_SIZE(ab9540_regulator_info);
2999 reg_init = ab9540_reg_init;
3000 reg_init_size = AB9540_NUM_REGULATOR_REGISTERS;
3001 match = ab9540_regulator_match;
3002 match_size = ARRAY_SIZE(ab9540_regulator_match)
3003 } else if (is_ab8505(ab8500)) {
3004 regulator_info = ab8505_regulator_info;
3005 regulator_info_size = ARRAY_SIZE(ab8505_regulator_info);
3006 reg_init = ab8505_reg_init;
3007 reg_init_size = AB8505_NUM_REGULATOR_REGISTERS;
3008 } else if (is_ab8540(ab8500)) {
3009 regulator_info = ab8540_regulator_info;
3010 regulator_info_size = ARRAY_SIZE(ab8540_regulator_info);
3011 reg_init = ab8540_reg_init;
3012 reg_init_size = AB8540_NUM_REGULATOR_REGISTERS;
3013 } else {
3014 regulator_info = ab8500_regulator_info;
3015 regulator_info_size = ARRAY_SIZE(ab8500_regulator_info);
3016 reg_init = ab8500_reg_init;
3017 reg_init_size = AB8500_NUM_REGULATOR_REGISTERS;
3018 match = ab8500_regulator_match;
3019 match_size = ARRAY_SIZE(ab8500_regulator_match)
3020 }
3021
3022 if (np) {
3023 err = of_regulator_match(&pdev->dev, np, match, match_size);
3024 if (err < 0) {
3025 dev_err(&pdev->dev,
3026 "Error parsing regulator init data: %d\n", err);
3027 return err;
3028 }
3029
3030 err = ab8500_regulator_of_probe(pdev, regulator_info,
3031 regulator_info_size, match, np);
3032 return err;
3033 }
3034
3035 if (!ab8500) {
3036 dev_err(&pdev->dev, "null mfd parent\n");
3037 return -EINVAL;
3038 }
3039
3040 ppdata = dev_get_platdata(ab8500->dev);
3041 if (!ppdata) {
3042 dev_err(&pdev->dev, "null parent pdata\n");
3043 return -EINVAL;
3044 }
3045
3046 pdata = ppdata->regulator;
3047 if (!pdata) {
3048 dev_err(&pdev->dev, "null pdata\n");
3049 return -EINVAL;
3050 }
3051
3052 /* make sure the platform data has the correct size */
3053 if (pdata->num_regulator != regulator_info_size) {
3054 dev_err(&pdev->dev, "Configuration error: size mismatch.\n");
3055 return -EINVAL;
3056 }
3057
3058 /* initialize debug (initial state is recorded with this call) */
3059 err = ab8500_regulator_debug_init(pdev);
3060 if (err)
3061 return err;
3062
3063 /* initialize registers */
3064 for (i = 0; i < pdata->num_reg_init; i++) {
3065 int id, mask, value;
3066
3067 id = pdata->reg_init[i].id;
3068 mask = pdata->reg_init[i].mask;
3069 value = pdata->reg_init[i].value;
3070
3071 /* check for configuration errors */
3072 BUG_ON(id >= AB8500_NUM_REGULATOR_REGISTERS);
3073
3074 err = ab8500_regulator_init_registers(pdev, reg_init, id, mask, value);
3075 if (err < 0)
3076 return err;
3077 }
3078
3079 if (!is_ab8505(ab8500)) {
3080 /* register external regulators (before Vaux1, 2 and 3) */
3081 err = ab8500_ext_regulator_init(pdev);
3082 if (err)
3083 return err;
3084 }
3085
3086 /* register all regulators */
3087 for (i = 0; i < regulator_info_size; i++) {
3088 err = ab8500_regulator_register(pdev, &pdata->regulator[i],
3089 regulator_info, i, NULL);
3090 if (err < 0)
3091 return err;
3092 }
3093
3094 return 0;
3095 }
3096
3097 static int ab8500_regulator_remove(struct platform_device *pdev)
3098 {
3099 int i, err;
3100 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3101 struct ab8500_regulator_info *regulator_info;
3102 int regulator_info_size;
3103
3104
3105 if (is_ab9540(ab8500)) {
3106 regulator_info = ab9540_regulator_info;
3107 regulator_info_size = ARRAY_SIZE(ab9540_regulator_info);
3108 } else if (is_ab8505(ab8500)) {
3109 regulator_info = ab8505_regulator_info;
3110 regulator_info_size = ARRAY_SIZE(ab8505_regulator_info);
3111 } else if (is_ab8540(ab8500)) {
3112 regulator_info = ab8540_regulator_info;
3113 regulator_info_size = ARRAY_SIZE(ab8540_regulator_info);
3114 } else {
3115 regulator_info = ab8500_regulator_info;
3116 regulator_info_size = ARRAY_SIZE(ab8500_regulator_info);
3117 }
3118
3119 for (i = 0; i < regulator_info_size; i++) {
3120 struct ab8500_regulator_info *info = NULL;
3121 info = &regulator_info[i];
3122
3123 dev_vdbg(rdev_get_dev(info->regulator),
3124 "%s-remove\n", info->desc.name);
3125
3126 regulator_unregister(info->regulator);
3127 }
3128
3129 if (!is_ab8505(ab8500)) {
3130 /* remove external regulators (after Vaux1, 2 and 3) */
3131 err = ab8500_ext_regulator_exit(pdev);
3132 if (err)
3133 return err;
3134 }
3135
3136 /* remove regulator debug */
3137 err = ab8500_regulator_debug_exit(pdev);
3138 if (err)
3139 return err;
3140
3141 return 0;
3142 }
3143
3144 static struct platform_driver ab8500_regulator_driver = {
3145 .probe = ab8500_regulator_probe,
3146 .remove = ab8500_regulator_remove,
3147 .driver = {
3148 .name = "ab8500-regulator",
3149 .owner = THIS_MODULE,
3150 },
3151 };
3152
3153 static int __init ab8500_regulator_init(void)
3154 {
3155 int ret;
3156
3157 ret = platform_driver_register(&ab8500_regulator_driver);
3158 if (ret != 0)
3159 pr_err("Failed to register ab8500 regulator: %d\n", ret);
3160
3161 return ret;
3162 }
3163 subsys_initcall(ab8500_regulator_init);
3164
3165 static void __exit ab8500_regulator_exit(void)
3166 {
3167 platform_driver_unregister(&ab8500_regulator_driver);
3168 }
3169 module_exit(ab8500_regulator_exit);
3170
3171 MODULE_LICENSE("GPL v2");
3172 MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
3173 MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>");
3174 MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>");
3175 MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
3176 MODULE_ALIAS("platform:ab8500-regulator");
Linux kernel - Deliverables
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