2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
7 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/bcd.h>
15 #include <linux/i2c.h>
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/rtc/ds1307.h>
19 #include <linux/rtc.h>
20 #include <linux/slab.h>
21 #include <linux/string.h>
22 #include <linux/hwmon.h>
23 #include <linux/hwmon-sysfs.h>
24 #include <linux/clk-provider.h>
27 * We can't determine type by probing, but if we expect pre-Linux code
28 * to have set the chip up as a clock (turning on the oscillator and
29 * setting the date and time), Linux can ignore the non-clock features.
30 * That's a natural job for a factory or repair bench.
43 last_ds_type
/* always last */
44 /* rs5c372 too? different address... */
48 /* RTC registers don't differ much, except for the century flag */
49 #define DS1307_REG_SECS 0x00 /* 00-59 */
50 # define DS1307_BIT_CH 0x80
51 # define DS1340_BIT_nEOSC 0x80
52 # define MCP794XX_BIT_ST 0x80
53 #define DS1307_REG_MIN 0x01 /* 00-59 */
54 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
55 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
56 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
57 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
58 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
59 #define DS1307_REG_WDAY 0x03 /* 01-07 */
60 # define MCP794XX_BIT_VBATEN 0x08
61 #define DS1307_REG_MDAY 0x04 /* 01-31 */
62 #define DS1307_REG_MONTH 0x05 /* 01-12 */
63 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
64 #define DS1307_REG_YEAR 0x06 /* 00-99 */
67 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
68 * start at 7, and they differ a LOT. Only control and status matter for
69 * basic RTC date and time functionality; be careful using them.
71 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
72 # define DS1307_BIT_OUT 0x80
73 # define DS1338_BIT_OSF 0x20
74 # define DS1307_BIT_SQWE 0x10
75 # define DS1307_BIT_RS1 0x02
76 # define DS1307_BIT_RS0 0x01
77 #define DS1337_REG_CONTROL 0x0e
78 # define DS1337_BIT_nEOSC 0x80
79 # define DS1339_BIT_BBSQI 0x20
80 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
81 # define DS1337_BIT_RS2 0x10
82 # define DS1337_BIT_RS1 0x08
83 # define DS1337_BIT_INTCN 0x04
84 # define DS1337_BIT_A2IE 0x02
85 # define DS1337_BIT_A1IE 0x01
86 #define DS1340_REG_CONTROL 0x07
87 # define DS1340_BIT_OUT 0x80
88 # define DS1340_BIT_FT 0x40
89 # define DS1340_BIT_CALIB_SIGN 0x20
90 # define DS1340_M_CALIBRATION 0x1f
91 #define DS1340_REG_FLAG 0x09
92 # define DS1340_BIT_OSF 0x80
93 #define DS1337_REG_STATUS 0x0f
94 # define DS1337_BIT_OSF 0x80
95 # define DS3231_BIT_EN32KHZ 0x08
96 # define DS1337_BIT_A2I 0x02
97 # define DS1337_BIT_A1I 0x01
98 #define DS1339_REG_ALARM1_SECS 0x07
100 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
102 #define RX8025_REG_CTRL1 0x0e
103 # define RX8025_BIT_2412 0x20
104 #define RX8025_REG_CTRL2 0x0f
105 # define RX8025_BIT_PON 0x10
106 # define RX8025_BIT_VDET 0x40
107 # define RX8025_BIT_XST 0x20
111 u8 offset
; /* register's offset */
114 struct bin_attribute
*nvram
;
117 #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
118 #define HAS_ALARM 1 /* bit 1 == irq claimed */
119 struct i2c_client
*client
;
120 struct rtc_device
*rtc
;
121 s32 (*read_block_data
)(const struct i2c_client
*client
, u8 command
,
122 u8 length
, u8
*values
);
123 s32 (*write_block_data
)(const struct i2c_client
*client
, u8 command
,
124 u8 length
, const u8
*values
);
125 #ifdef CONFIG_COMMON_CLK
126 struct clk_hw clks
[2];
134 u16 trickle_charger_reg
;
135 u8 trickle_charger_setup
;
136 u8 (*do_trickle_setup
)(struct i2c_client
*, uint32_t, bool);
139 static u8
do_trickle_setup_ds1339(struct i2c_client
*,
140 uint32_t ohms
, bool diode
);
142 static struct chip_desc chips
[last_ds_type
] = {
156 .trickle_charger_reg
= 0x10,
157 .do_trickle_setup
= &do_trickle_setup_ds1339
,
160 .trickle_charger_reg
= 0x08,
163 .trickle_charger_reg
= 0x0a,
170 /* this is battery backed SRAM */
171 .nvram_offset
= 0x20,
176 static const struct i2c_device_id ds1307_id
[] = {
177 { "ds1307", ds_1307
},
178 { "ds1337", ds_1337
},
179 { "ds1338", ds_1338
},
180 { "ds1339", ds_1339
},
181 { "ds1388", ds_1388
},
182 { "ds1340", ds_1340
},
183 { "ds3231", ds_3231
},
184 { "m41t00", m41t00
},
185 { "mcp7940x", mcp794xx
},
186 { "mcp7941x", mcp794xx
},
187 { "pt7c4338", ds_1307
},
188 { "rx8025", rx_8025
},
191 MODULE_DEVICE_TABLE(i2c
, ds1307_id
);
193 /*----------------------------------------------------------------------*/
195 #define BLOCK_DATA_MAX_TRIES 10
197 static s32
ds1307_read_block_data_once(const struct i2c_client
*client
,
198 u8 command
, u8 length
, u8
*values
)
202 for (i
= 0; i
< length
; i
++) {
203 data
= i2c_smbus_read_byte_data(client
, command
+ i
);
211 static s32
ds1307_read_block_data(const struct i2c_client
*client
, u8 command
,
212 u8 length
, u8
*values
)
218 dev_dbg(&client
->dev
, "ds1307_read_block_data (length=%d)\n", length
);
219 ret
= ds1307_read_block_data_once(client
, command
, length
, values
);
223 if (++tries
> BLOCK_DATA_MAX_TRIES
) {
224 dev_err(&client
->dev
,
225 "ds1307_read_block_data failed\n");
228 memcpy(oldvalues
, values
, length
);
229 ret
= ds1307_read_block_data_once(client
, command
, length
,
233 } while (memcmp(oldvalues
, values
, length
));
237 static s32
ds1307_write_block_data(const struct i2c_client
*client
, u8 command
,
238 u8 length
, const u8
*values
)
243 dev_dbg(&client
->dev
, "ds1307_write_block_data (length=%d)\n", length
);
247 if (++tries
> BLOCK_DATA_MAX_TRIES
) {
248 dev_err(&client
->dev
,
249 "ds1307_write_block_data failed\n");
252 for (i
= 0; i
< length
; i
++) {
253 ret
= i2c_smbus_write_byte_data(client
, command
+ i
,
258 ret
= ds1307_read_block_data_once(client
, command
, length
,
262 } while (memcmp(currvalues
, values
, length
));
266 /*----------------------------------------------------------------------*/
268 /* These RTC devices are not designed to be connected to a SMbus adapter.
269 SMbus limits block operations length to 32 bytes, whereas it's not
270 limited on I2C buses. As a result, accesses may exceed 32 bytes;
271 in that case, split them into smaller blocks */
273 static s32
ds1307_native_smbus_write_block_data(const struct i2c_client
*client
,
274 u8 command
, u8 length
, const u8
*values
)
278 if (length
<= I2C_SMBUS_BLOCK_MAX
) {
279 s32 retval
= i2c_smbus_write_i2c_block_data(client
,
280 command
, length
, values
);
286 while (suboffset
< length
) {
287 s32 retval
= i2c_smbus_write_i2c_block_data(client
,
289 min(I2C_SMBUS_BLOCK_MAX
, length
- suboffset
),
294 suboffset
+= I2C_SMBUS_BLOCK_MAX
;
299 static s32
ds1307_native_smbus_read_block_data(const struct i2c_client
*client
,
300 u8 command
, u8 length
, u8
*values
)
304 if (length
<= I2C_SMBUS_BLOCK_MAX
)
305 return i2c_smbus_read_i2c_block_data(client
,
306 command
, length
, values
);
308 while (suboffset
< length
) {
309 s32 retval
= i2c_smbus_read_i2c_block_data(client
,
311 min(I2C_SMBUS_BLOCK_MAX
, length
- suboffset
),
316 suboffset
+= I2C_SMBUS_BLOCK_MAX
;
321 /*----------------------------------------------------------------------*/
324 * The ds1337 and ds1339 both have two alarms, but we only use the first
325 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
326 * signal; ds1339 chips have only one alarm signal.
328 static irqreturn_t
ds1307_irq(int irq
, void *dev_id
)
330 struct i2c_client
*client
= dev_id
;
331 struct ds1307
*ds1307
= i2c_get_clientdata(client
);
332 struct mutex
*lock
= &ds1307
->rtc
->ops_lock
;
336 stat
= i2c_smbus_read_byte_data(client
, DS1337_REG_STATUS
);
340 if (stat
& DS1337_BIT_A1I
) {
341 stat
&= ~DS1337_BIT_A1I
;
342 i2c_smbus_write_byte_data(client
, DS1337_REG_STATUS
, stat
);
344 control
= i2c_smbus_read_byte_data(client
, DS1337_REG_CONTROL
);
348 control
&= ~DS1337_BIT_A1IE
;
349 i2c_smbus_write_byte_data(client
, DS1337_REG_CONTROL
, control
);
351 rtc_update_irq(ds1307
->rtc
, 1, RTC_AF
| RTC_IRQF
);
360 /*----------------------------------------------------------------------*/
362 static int ds1307_get_time(struct device
*dev
, struct rtc_time
*t
)
364 struct ds1307
*ds1307
= dev_get_drvdata(dev
);
367 /* read the RTC date and time registers all at once */
368 tmp
= ds1307
->read_block_data(ds1307
->client
,
369 ds1307
->offset
, 7, ds1307
->regs
);
371 dev_err(dev
, "%s error %d\n", "read", tmp
);
375 dev_dbg(dev
, "%s: %7ph\n", "read", ds1307
->regs
);
377 t
->tm_sec
= bcd2bin(ds1307
->regs
[DS1307_REG_SECS
] & 0x7f);
378 t
->tm_min
= bcd2bin(ds1307
->regs
[DS1307_REG_MIN
] & 0x7f);
379 tmp
= ds1307
->regs
[DS1307_REG_HOUR
] & 0x3f;
380 t
->tm_hour
= bcd2bin(tmp
);
381 t
->tm_wday
= bcd2bin(ds1307
->regs
[DS1307_REG_WDAY
] & 0x07) - 1;
382 t
->tm_mday
= bcd2bin(ds1307
->regs
[DS1307_REG_MDAY
] & 0x3f);
383 tmp
= ds1307
->regs
[DS1307_REG_MONTH
] & 0x1f;
384 t
->tm_mon
= bcd2bin(tmp
) - 1;
386 /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
387 t
->tm_year
= bcd2bin(ds1307
->regs
[DS1307_REG_YEAR
]) + 100;
389 dev_dbg(dev
, "%s secs=%d, mins=%d, "
390 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
391 "read", t
->tm_sec
, t
->tm_min
,
392 t
->tm_hour
, t
->tm_mday
,
393 t
->tm_mon
, t
->tm_year
, t
->tm_wday
);
395 /* initial clock setting can be undefined */
396 return rtc_valid_tm(t
);
399 static int ds1307_set_time(struct device
*dev
, struct rtc_time
*t
)
401 struct ds1307
*ds1307
= dev_get_drvdata(dev
);
404 u8
*buf
= ds1307
->regs
;
406 dev_dbg(dev
, "%s secs=%d, mins=%d, "
407 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
408 "write", t
->tm_sec
, t
->tm_min
,
409 t
->tm_hour
, t
->tm_mday
,
410 t
->tm_mon
, t
->tm_year
, t
->tm_wday
);
412 buf
[DS1307_REG_SECS
] = bin2bcd(t
->tm_sec
);
413 buf
[DS1307_REG_MIN
] = bin2bcd(t
->tm_min
);
414 buf
[DS1307_REG_HOUR
] = bin2bcd(t
->tm_hour
);
415 buf
[DS1307_REG_WDAY
] = bin2bcd(t
->tm_wday
+ 1);
416 buf
[DS1307_REG_MDAY
] = bin2bcd(t
->tm_mday
);
417 buf
[DS1307_REG_MONTH
] = bin2bcd(t
->tm_mon
+ 1);
419 /* assume 20YY not 19YY */
420 tmp
= t
->tm_year
- 100;
421 buf
[DS1307_REG_YEAR
] = bin2bcd(tmp
);
423 switch (ds1307
->type
) {
427 buf
[DS1307_REG_MONTH
] |= DS1337_BIT_CENTURY
;
430 buf
[DS1307_REG_HOUR
] |= DS1340_BIT_CENTURY_EN
431 | DS1340_BIT_CENTURY
;
435 * these bits were cleared when preparing the date/time
436 * values and need to be set again before writing the
437 * buffer out to the device.
439 buf
[DS1307_REG_SECS
] |= MCP794XX_BIT_ST
;
440 buf
[DS1307_REG_WDAY
] |= MCP794XX_BIT_VBATEN
;
446 dev_dbg(dev
, "%s: %7ph\n", "write", buf
);
448 result
= ds1307
->write_block_data(ds1307
->client
,
449 ds1307
->offset
, 7, buf
);
451 dev_err(dev
, "%s error %d\n", "write", result
);
457 static int ds1337_read_alarm(struct device
*dev
, struct rtc_wkalrm
*t
)
459 struct i2c_client
*client
= to_i2c_client(dev
);
460 struct ds1307
*ds1307
= i2c_get_clientdata(client
);
463 if (!test_bit(HAS_ALARM
, &ds1307
->flags
))
466 /* read all ALARM1, ALARM2, and status registers at once */
467 ret
= ds1307
->read_block_data(client
,
468 DS1339_REG_ALARM1_SECS
, 9, ds1307
->regs
);
470 dev_err(dev
, "%s error %d\n", "alarm read", ret
);
474 dev_dbg(dev
, "%s: %4ph, %3ph, %2ph\n", "alarm read",
475 &ds1307
->regs
[0], &ds1307
->regs
[4], &ds1307
->regs
[7]);
478 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
479 * and that all four fields are checked matches
481 t
->time
.tm_sec
= bcd2bin(ds1307
->regs
[0] & 0x7f);
482 t
->time
.tm_min
= bcd2bin(ds1307
->regs
[1] & 0x7f);
483 t
->time
.tm_hour
= bcd2bin(ds1307
->regs
[2] & 0x3f);
484 t
->time
.tm_mday
= bcd2bin(ds1307
->regs
[3] & 0x3f);
486 t
->time
.tm_year
= -1;
487 t
->time
.tm_wday
= -1;
488 t
->time
.tm_yday
= -1;
489 t
->time
.tm_isdst
= -1;
492 t
->enabled
= !!(ds1307
->regs
[7] & DS1337_BIT_A1IE
);
493 t
->pending
= !!(ds1307
->regs
[8] & DS1337_BIT_A1I
);
495 dev_dbg(dev
, "%s secs=%d, mins=%d, "
496 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
497 "alarm read", t
->time
.tm_sec
, t
->time
.tm_min
,
498 t
->time
.tm_hour
, t
->time
.tm_mday
,
499 t
->enabled
, t
->pending
);
504 static int ds1337_set_alarm(struct device
*dev
, struct rtc_wkalrm
*t
)
506 struct i2c_client
*client
= to_i2c_client(dev
);
507 struct ds1307
*ds1307
= i2c_get_clientdata(client
);
508 unsigned char *buf
= ds1307
->regs
;
512 if (!test_bit(HAS_ALARM
, &ds1307
->flags
))
515 dev_dbg(dev
, "%s secs=%d, mins=%d, "
516 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
517 "alarm set", t
->time
.tm_sec
, t
->time
.tm_min
,
518 t
->time
.tm_hour
, t
->time
.tm_mday
,
519 t
->enabled
, t
->pending
);
521 /* read current status of both alarms and the chip */
522 ret
= ds1307
->read_block_data(client
,
523 DS1339_REG_ALARM1_SECS
, 9, buf
);
525 dev_err(dev
, "%s error %d\n", "alarm write", ret
);
528 control
= ds1307
->regs
[7];
529 status
= ds1307
->regs
[8];
531 dev_dbg(dev
, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
532 &ds1307
->regs
[0], &ds1307
->regs
[4], control
, status
);
534 /* set ALARM1, using 24 hour and day-of-month modes */
535 buf
[0] = bin2bcd(t
->time
.tm_sec
);
536 buf
[1] = bin2bcd(t
->time
.tm_min
);
537 buf
[2] = bin2bcd(t
->time
.tm_hour
);
538 buf
[3] = bin2bcd(t
->time
.tm_mday
);
540 /* set ALARM2 to non-garbage */
545 /* optionally enable ALARM1 */
546 buf
[7] = control
& ~(DS1337_BIT_A1IE
| DS1337_BIT_A2IE
);
548 dev_dbg(dev
, "alarm IRQ armed\n");
549 buf
[7] |= DS1337_BIT_A1IE
; /* only ALARM1 is used */
551 buf
[8] = status
& ~(DS1337_BIT_A1I
| DS1337_BIT_A2I
);
553 ret
= ds1307
->write_block_data(client
,
554 DS1339_REG_ALARM1_SECS
, 9, buf
);
556 dev_err(dev
, "can't set alarm time\n");
563 static int ds1307_alarm_irq_enable(struct device
*dev
, unsigned int enabled
)
565 struct i2c_client
*client
= to_i2c_client(dev
);
566 struct ds1307
*ds1307
= i2c_get_clientdata(client
);
569 if (!test_bit(HAS_ALARM
, &ds1307
->flags
))
572 ret
= i2c_smbus_read_byte_data(client
, DS1337_REG_CONTROL
);
577 ret
|= DS1337_BIT_A1IE
;
579 ret
&= ~DS1337_BIT_A1IE
;
581 ret
= i2c_smbus_write_byte_data(client
, DS1337_REG_CONTROL
, ret
);
588 static const struct rtc_class_ops ds13xx_rtc_ops
= {
589 .read_time
= ds1307_get_time
,
590 .set_time
= ds1307_set_time
,
591 .read_alarm
= ds1337_read_alarm
,
592 .set_alarm
= ds1337_set_alarm
,
593 .alarm_irq_enable
= ds1307_alarm_irq_enable
,
596 /*----------------------------------------------------------------------*/
599 * Alarm support for mcp794xx devices.
602 #define MCP794XX_REG_CONTROL 0x07
603 # define MCP794XX_BIT_ALM0_EN 0x10
604 # define MCP794XX_BIT_ALM1_EN 0x20
605 #define MCP794XX_REG_ALARM0_BASE 0x0a
606 #define MCP794XX_REG_ALARM0_CTRL 0x0d
607 #define MCP794XX_REG_ALARM1_BASE 0x11
608 #define MCP794XX_REG_ALARM1_CTRL 0x14
609 # define MCP794XX_BIT_ALMX_IF (1 << 3)
610 # define MCP794XX_BIT_ALMX_C0 (1 << 4)
611 # define MCP794XX_BIT_ALMX_C1 (1 << 5)
612 # define MCP794XX_BIT_ALMX_C2 (1 << 6)
613 # define MCP794XX_BIT_ALMX_POL (1 << 7)
614 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
615 MCP794XX_BIT_ALMX_C1 | \
616 MCP794XX_BIT_ALMX_C2)
618 static irqreturn_t
mcp794xx_irq(int irq
, void *dev_id
)
620 struct i2c_client
*client
= dev_id
;
621 struct ds1307
*ds1307
= i2c_get_clientdata(client
);
622 struct mutex
*lock
= &ds1307
->rtc
->ops_lock
;
627 /* Check and clear alarm 0 interrupt flag. */
628 reg
= i2c_smbus_read_byte_data(client
, MCP794XX_REG_ALARM0_CTRL
);
631 if (!(reg
& MCP794XX_BIT_ALMX_IF
))
633 reg
&= ~MCP794XX_BIT_ALMX_IF
;
634 ret
= i2c_smbus_write_byte_data(client
, MCP794XX_REG_ALARM0_CTRL
, reg
);
638 /* Disable alarm 0. */
639 reg
= i2c_smbus_read_byte_data(client
, MCP794XX_REG_CONTROL
);
642 reg
&= ~MCP794XX_BIT_ALM0_EN
;
643 ret
= i2c_smbus_write_byte_data(client
, MCP794XX_REG_CONTROL
, reg
);
647 rtc_update_irq(ds1307
->rtc
, 1, RTC_AF
| RTC_IRQF
);
655 static int mcp794xx_read_alarm(struct device
*dev
, struct rtc_wkalrm
*t
)
657 struct i2c_client
*client
= to_i2c_client(dev
);
658 struct ds1307
*ds1307
= i2c_get_clientdata(client
);
659 u8
*regs
= ds1307
->regs
;
662 if (!test_bit(HAS_ALARM
, &ds1307
->flags
))
665 /* Read control and alarm 0 registers. */
666 ret
= ds1307
->read_block_data(client
, MCP794XX_REG_CONTROL
, 10, regs
);
670 t
->enabled
= !!(regs
[0] & MCP794XX_BIT_ALM0_EN
);
672 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
673 t
->time
.tm_sec
= bcd2bin(ds1307
->regs
[3] & 0x7f);
674 t
->time
.tm_min
= bcd2bin(ds1307
->regs
[4] & 0x7f);
675 t
->time
.tm_hour
= bcd2bin(ds1307
->regs
[5] & 0x3f);
676 t
->time
.tm_wday
= bcd2bin(ds1307
->regs
[6] & 0x7) - 1;
677 t
->time
.tm_mday
= bcd2bin(ds1307
->regs
[7] & 0x3f);
678 t
->time
.tm_mon
= bcd2bin(ds1307
->regs
[8] & 0x1f) - 1;
679 t
->time
.tm_year
= -1;
680 t
->time
.tm_yday
= -1;
681 t
->time
.tm_isdst
= -1;
683 dev_dbg(dev
, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
684 "enabled=%d polarity=%d irq=%d match=%d\n", __func__
,
685 t
->time
.tm_sec
, t
->time
.tm_min
, t
->time
.tm_hour
,
686 t
->time
.tm_wday
, t
->time
.tm_mday
, t
->time
.tm_mon
, t
->enabled
,
687 !!(ds1307
->regs
[6] & MCP794XX_BIT_ALMX_POL
),
688 !!(ds1307
->regs
[6] & MCP794XX_BIT_ALMX_IF
),
689 (ds1307
->regs
[6] & MCP794XX_MSK_ALMX_MATCH
) >> 4);
694 static int mcp794xx_set_alarm(struct device
*dev
, struct rtc_wkalrm
*t
)
696 struct i2c_client
*client
= to_i2c_client(dev
);
697 struct ds1307
*ds1307
= i2c_get_clientdata(client
);
698 unsigned char *regs
= ds1307
->regs
;
701 if (!test_bit(HAS_ALARM
, &ds1307
->flags
))
704 dev_dbg(dev
, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
705 "enabled=%d pending=%d\n", __func__
,
706 t
->time
.tm_sec
, t
->time
.tm_min
, t
->time
.tm_hour
,
707 t
->time
.tm_wday
, t
->time
.tm_mday
, t
->time
.tm_mon
,
708 t
->enabled
, t
->pending
);
710 /* Read control and alarm 0 registers. */
711 ret
= ds1307
->read_block_data(client
, MCP794XX_REG_CONTROL
, 10, regs
);
715 /* Set alarm 0, using 24-hour and day-of-month modes. */
716 regs
[3] = bin2bcd(t
->time
.tm_sec
);
717 regs
[4] = bin2bcd(t
->time
.tm_min
);
718 regs
[5] = bin2bcd(t
->time
.tm_hour
);
719 regs
[6] = bin2bcd(t
->time
.tm_wday
+ 1);
720 regs
[7] = bin2bcd(t
->time
.tm_mday
);
721 regs
[8] = bin2bcd(t
->time
.tm_mon
+ 1);
723 /* Clear the alarm 0 interrupt flag. */
724 regs
[6] &= ~MCP794XX_BIT_ALMX_IF
;
725 /* Set alarm match: second, minute, hour, day, date, month. */
726 regs
[6] |= MCP794XX_MSK_ALMX_MATCH
;
727 /* Disable interrupt. We will not enable until completely programmed */
728 regs
[0] &= ~MCP794XX_BIT_ALM0_EN
;
730 ret
= ds1307
->write_block_data(client
, MCP794XX_REG_CONTROL
, 10, regs
);
736 regs
[0] |= MCP794XX_BIT_ALM0_EN
;
737 return i2c_smbus_write_byte_data(client
, MCP794XX_REG_CONTROL
, regs
[0]);
740 static int mcp794xx_alarm_irq_enable(struct device
*dev
, unsigned int enabled
)
742 struct i2c_client
*client
= to_i2c_client(dev
);
743 struct ds1307
*ds1307
= i2c_get_clientdata(client
);
746 if (!test_bit(HAS_ALARM
, &ds1307
->flags
))
749 reg
= i2c_smbus_read_byte_data(client
, MCP794XX_REG_CONTROL
);
754 reg
|= MCP794XX_BIT_ALM0_EN
;
756 reg
&= ~MCP794XX_BIT_ALM0_EN
;
758 return i2c_smbus_write_byte_data(client
, MCP794XX_REG_CONTROL
, reg
);
761 static const struct rtc_class_ops mcp794xx_rtc_ops
= {
762 .read_time
= ds1307_get_time
,
763 .set_time
= ds1307_set_time
,
764 .read_alarm
= mcp794xx_read_alarm
,
765 .set_alarm
= mcp794xx_set_alarm
,
766 .alarm_irq_enable
= mcp794xx_alarm_irq_enable
,
769 /*----------------------------------------------------------------------*/
772 ds1307_nvram_read(struct file
*filp
, struct kobject
*kobj
,
773 struct bin_attribute
*attr
,
774 char *buf
, loff_t off
, size_t count
)
776 struct i2c_client
*client
;
777 struct ds1307
*ds1307
;
780 client
= kobj_to_i2c_client(kobj
);
781 ds1307
= i2c_get_clientdata(client
);
783 result
= ds1307
->read_block_data(client
, ds1307
->nvram_offset
+ off
,
786 dev_err(&client
->dev
, "%s error %d\n", "nvram read", result
);
791 ds1307_nvram_write(struct file
*filp
, struct kobject
*kobj
,
792 struct bin_attribute
*attr
,
793 char *buf
, loff_t off
, size_t count
)
795 struct i2c_client
*client
;
796 struct ds1307
*ds1307
;
799 client
= kobj_to_i2c_client(kobj
);
800 ds1307
= i2c_get_clientdata(client
);
802 result
= ds1307
->write_block_data(client
, ds1307
->nvram_offset
+ off
,
805 dev_err(&client
->dev
, "%s error %d\n", "nvram write", result
);
812 /*----------------------------------------------------------------------*/
814 static u8
do_trickle_setup_ds1339(struct i2c_client
*client
,
815 uint32_t ohms
, bool diode
)
817 u8 setup
= (diode
) ? DS1307_TRICKLE_CHARGER_DIODE
:
818 DS1307_TRICKLE_CHARGER_NO_DIODE
;
822 setup
|= DS1307_TRICKLE_CHARGER_250_OHM
;
825 setup
|= DS1307_TRICKLE_CHARGER_2K_OHM
;
828 setup
|= DS1307_TRICKLE_CHARGER_4K_OHM
;
831 dev_warn(&client
->dev
,
832 "Unsupported ohm value %u in dt\n", ohms
);
838 static void ds1307_trickle_of_init(struct i2c_client
*client
,
839 struct chip_desc
*chip
)
844 if (!chip
->do_trickle_setup
)
846 if (of_property_read_u32(client
->dev
.of_node
, "trickle-resistor-ohms" , &ohms
))
848 if (of_property_read_bool(client
->dev
.of_node
, "trickle-diode-disable"))
850 chip
->trickle_charger_setup
= chip
->do_trickle_setup(client
,
856 /*----------------------------------------------------------------------*/
858 #ifdef CONFIG_RTC_DRV_DS1307_HWMON
861 * Temperature sensor support for ds3231 devices.
864 #define DS3231_REG_TEMPERATURE 0x11
867 * A user-initiated temperature conversion is not started by this function,
868 * so the temperature is updated once every 64 seconds.
870 static int ds3231_hwmon_read_temp(struct device
*dev
, s32
*mC
)
872 struct ds1307
*ds1307
= dev_get_drvdata(dev
);
877 ret
= ds1307
->read_block_data(ds1307
->client
, DS3231_REG_TEMPERATURE
,
878 sizeof(temp_buf
), temp_buf
);
881 if (ret
!= sizeof(temp_buf
))
885 * Temperature is represented as a 10-bit code with a resolution of
886 * 0.25 degree celsius and encoded in two's complement format.
888 temp
= (temp_buf
[0] << 8) | temp_buf
[1];
895 static ssize_t
ds3231_hwmon_show_temp(struct device
*dev
,
896 struct device_attribute
*attr
, char *buf
)
901 ret
= ds3231_hwmon_read_temp(dev
, &temp
);
905 return sprintf(buf
, "%d\n", temp
);
907 static SENSOR_DEVICE_ATTR(temp1_input
, S_IRUGO
, ds3231_hwmon_show_temp
,
910 static struct attribute
*ds3231_hwmon_attrs
[] = {
911 &sensor_dev_attr_temp1_input
.dev_attr
.attr
,
914 ATTRIBUTE_GROUPS(ds3231_hwmon
);
916 static void ds1307_hwmon_register(struct ds1307
*ds1307
)
920 if (ds1307
->type
!= ds_3231
)
923 dev
= devm_hwmon_device_register_with_groups(&ds1307
->client
->dev
,
924 ds1307
->client
->name
,
925 ds1307
, ds3231_hwmon_groups
);
927 dev_warn(&ds1307
->client
->dev
,
928 "unable to register hwmon device %ld\n", PTR_ERR(dev
));
934 static void ds1307_hwmon_register(struct ds1307
*ds1307
)
938 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
940 /*----------------------------------------------------------------------*/
943 * Square-wave output support for DS3231
944 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
946 #ifdef CONFIG_COMMON_CLK
953 #define clk_sqw_to_ds1307(clk) \
954 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
955 #define clk_32khz_to_ds1307(clk) \
956 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
958 static int ds3231_clk_sqw_rates
[] = {
965 static int ds1337_write_control(struct ds1307
*ds1307
, u8 mask
, u8 value
)
967 struct i2c_client
*client
= ds1307
->client
;
968 struct mutex
*lock
= &ds1307
->rtc
->ops_lock
;
974 control
= i2c_smbus_read_byte_data(client
, DS1337_REG_CONTROL
);
983 ret
= i2c_smbus_write_byte_data(client
, DS1337_REG_CONTROL
, control
);
990 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw
*hw
,
991 unsigned long parent_rate
)
993 struct ds1307
*ds1307
= clk_sqw_to_ds1307(hw
);
997 control
= i2c_smbus_read_byte_data(ds1307
->client
, DS1337_REG_CONTROL
);
1000 if (control
& DS1337_BIT_RS1
)
1002 if (control
& DS1337_BIT_RS2
)
1005 return ds3231_clk_sqw_rates
[rate_sel
];
1008 static long ds3231_clk_sqw_round_rate(struct clk_hw
*hw
, unsigned long rate
,
1009 unsigned long *prate
)
1013 for (i
= ARRAY_SIZE(ds3231_clk_sqw_rates
) - 1; i
>= 0; i
--) {
1014 if (ds3231_clk_sqw_rates
[i
] <= rate
)
1015 return ds3231_clk_sqw_rates
[i
];
1021 static int ds3231_clk_sqw_set_rate(struct clk_hw
*hw
, unsigned long rate
,
1022 unsigned long parent_rate
)
1024 struct ds1307
*ds1307
= clk_sqw_to_ds1307(hw
);
1028 for (rate_sel
= 0; rate_sel
< ARRAY_SIZE(ds3231_clk_sqw_rates
);
1030 if (ds3231_clk_sqw_rates
[rate_sel
] == rate
)
1034 if (rate_sel
== ARRAY_SIZE(ds3231_clk_sqw_rates
))
1038 control
|= DS1337_BIT_RS1
;
1040 control
|= DS1337_BIT_RS2
;
1042 return ds1337_write_control(ds1307
, DS1337_BIT_RS1
| DS1337_BIT_RS2
,
1046 static int ds3231_clk_sqw_prepare(struct clk_hw
*hw
)
1048 struct ds1307
*ds1307
= clk_sqw_to_ds1307(hw
);
1050 return ds1337_write_control(ds1307
, DS1337_BIT_INTCN
, 0);
1053 static void ds3231_clk_sqw_unprepare(struct clk_hw
*hw
)
1055 struct ds1307
*ds1307
= clk_sqw_to_ds1307(hw
);
1057 ds1337_write_control(ds1307
, DS1337_BIT_INTCN
, DS1337_BIT_INTCN
);
1060 static int ds3231_clk_sqw_is_prepared(struct clk_hw
*hw
)
1062 struct ds1307
*ds1307
= clk_sqw_to_ds1307(hw
);
1065 control
= i2c_smbus_read_byte_data(ds1307
->client
, DS1337_REG_CONTROL
);
1069 return !(control
& DS1337_BIT_INTCN
);
1072 static const struct clk_ops ds3231_clk_sqw_ops
= {
1073 .prepare
= ds3231_clk_sqw_prepare
,
1074 .unprepare
= ds3231_clk_sqw_unprepare
,
1075 .is_prepared
= ds3231_clk_sqw_is_prepared
,
1076 .recalc_rate
= ds3231_clk_sqw_recalc_rate
,
1077 .round_rate
= ds3231_clk_sqw_round_rate
,
1078 .set_rate
= ds3231_clk_sqw_set_rate
,
1081 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw
*hw
,
1082 unsigned long parent_rate
)
1087 static int ds3231_clk_32khz_control(struct ds1307
*ds1307
, bool enable
)
1089 struct i2c_client
*client
= ds1307
->client
;
1090 struct mutex
*lock
= &ds1307
->rtc
->ops_lock
;
1096 status
= i2c_smbus_read_byte_data(client
, DS1337_REG_STATUS
);
1103 status
|= DS3231_BIT_EN32KHZ
;
1105 status
&= ~DS3231_BIT_EN32KHZ
;
1107 ret
= i2c_smbus_write_byte_data(client
, DS1337_REG_STATUS
, status
);
1114 static int ds3231_clk_32khz_prepare(struct clk_hw
*hw
)
1116 struct ds1307
*ds1307
= clk_32khz_to_ds1307(hw
);
1118 return ds3231_clk_32khz_control(ds1307
, true);
1121 static void ds3231_clk_32khz_unprepare(struct clk_hw
*hw
)
1123 struct ds1307
*ds1307
= clk_32khz_to_ds1307(hw
);
1125 ds3231_clk_32khz_control(ds1307
, false);
1128 static int ds3231_clk_32khz_is_prepared(struct clk_hw
*hw
)
1130 struct ds1307
*ds1307
= clk_32khz_to_ds1307(hw
);
1133 status
= i2c_smbus_read_byte_data(ds1307
->client
, DS1337_REG_STATUS
);
1137 return !!(status
& DS3231_BIT_EN32KHZ
);
1140 static const struct clk_ops ds3231_clk_32khz_ops
= {
1141 .prepare
= ds3231_clk_32khz_prepare
,
1142 .unprepare
= ds3231_clk_32khz_unprepare
,
1143 .is_prepared
= ds3231_clk_32khz_is_prepared
,
1144 .recalc_rate
= ds3231_clk_32khz_recalc_rate
,
1147 static struct clk_init_data ds3231_clks_init
[] = {
1148 [DS3231_CLK_SQW
] = {
1149 .name
= "ds3231_clk_sqw",
1150 .ops
= &ds3231_clk_sqw_ops
,
1151 .flags
= CLK_IS_ROOT
,
1153 [DS3231_CLK_32KHZ
] = {
1154 .name
= "ds3231_clk_32khz",
1155 .ops
= &ds3231_clk_32khz_ops
,
1156 .flags
= CLK_IS_ROOT
,
1160 static int ds3231_clks_register(struct ds1307
*ds1307
)
1162 struct i2c_client
*client
= ds1307
->client
;
1163 struct device_node
*node
= client
->dev
.of_node
;
1164 struct clk_onecell_data
*onecell
;
1167 onecell
= devm_kzalloc(&client
->dev
, sizeof(*onecell
), GFP_KERNEL
);
1171 onecell
->clk_num
= ARRAY_SIZE(ds3231_clks_init
);
1172 onecell
->clks
= devm_kcalloc(&client
->dev
, onecell
->clk_num
,
1173 sizeof(onecell
->clks
[0]), GFP_KERNEL
);
1177 for (i
= 0; i
< ARRAY_SIZE(ds3231_clks_init
); i
++) {
1178 struct clk_init_data init
= ds3231_clks_init
[i
];
1181 * Interrupt signal due to alarm conditions and square-wave
1182 * output share same pin, so don't initialize both.
1184 if (i
== DS3231_CLK_SQW
&& test_bit(HAS_ALARM
, &ds1307
->flags
))
1187 /* optional override of the clockname */
1188 of_property_read_string_index(node
, "clock-output-names", i
,
1190 ds1307
->clks
[i
].init
= &init
;
1192 onecell
->clks
[i
] = devm_clk_register(&client
->dev
,
1194 if (IS_ERR(onecell
->clks
[i
]))
1195 return PTR_ERR(onecell
->clks
[i
]);
1201 of_clk_add_provider(node
, of_clk_src_onecell_get
, onecell
);
1206 static void ds1307_clks_register(struct ds1307
*ds1307
)
1210 if (ds1307
->type
!= ds_3231
)
1213 ret
= ds3231_clks_register(ds1307
);
1215 dev_warn(&ds1307
->client
->dev
,
1216 "unable to register clock device %d\n", ret
);
1222 static void ds1307_clks_register(struct ds1307
*ds1307
)
1226 #endif /* CONFIG_COMMON_CLK */
1228 static int ds1307_probe(struct i2c_client
*client
,
1229 const struct i2c_device_id
*id
)
1231 struct ds1307
*ds1307
;
1234 struct chip_desc
*chip
= &chips
[id
->driver_data
];
1235 struct i2c_adapter
*adapter
= to_i2c_adapter(client
->dev
.parent
);
1236 bool want_irq
= false;
1237 bool ds1307_can_wakeup_device
= false;
1239 struct ds1307_platform_data
*pdata
= dev_get_platdata(&client
->dev
);
1240 irq_handler_t irq_handler
= ds1307_irq
;
1242 static const int bbsqi_bitpos
[] = {
1244 [ds_1339
] = DS1339_BIT_BBSQI
,
1245 [ds_3231
] = DS3231_BIT_BBSQW
,
1247 const struct rtc_class_ops
*rtc_ops
= &ds13xx_rtc_ops
;
1249 if (!i2c_check_functionality(adapter
, I2C_FUNC_SMBUS_BYTE_DATA
)
1250 && !i2c_check_functionality(adapter
, I2C_FUNC_SMBUS_I2C_BLOCK
))
1253 ds1307
= devm_kzalloc(&client
->dev
, sizeof(struct ds1307
), GFP_KERNEL
);
1257 i2c_set_clientdata(client
, ds1307
);
1259 ds1307
->client
= client
;
1260 ds1307
->type
= id
->driver_data
;
1262 if (!pdata
&& client
->dev
.of_node
)
1263 ds1307_trickle_of_init(client
, chip
);
1264 else if (pdata
&& pdata
->trickle_charger_setup
)
1265 chip
->trickle_charger_setup
= pdata
->trickle_charger_setup
;
1267 if (chip
->trickle_charger_setup
&& chip
->trickle_charger_reg
) {
1268 dev_dbg(&client
->dev
, "writing trickle charger info 0x%x to 0x%x\n",
1269 DS13XX_TRICKLE_CHARGER_MAGIC
| chip
->trickle_charger_setup
,
1270 chip
->trickle_charger_reg
);
1271 i2c_smbus_write_byte_data(client
, chip
->trickle_charger_reg
,
1272 DS13XX_TRICKLE_CHARGER_MAGIC
|
1273 chip
->trickle_charger_setup
);
1277 if (i2c_check_functionality(adapter
, I2C_FUNC_SMBUS_I2C_BLOCK
)) {
1278 ds1307
->read_block_data
= ds1307_native_smbus_read_block_data
;
1279 ds1307
->write_block_data
= ds1307_native_smbus_write_block_data
;
1281 ds1307
->read_block_data
= ds1307_read_block_data
;
1282 ds1307
->write_block_data
= ds1307_write_block_data
;
1287 * For devices with no IRQ directly connected to the SoC, the RTC chip
1288 * can be forced as a wakeup source by stating that explicitly in
1289 * the device's .dts file using the "wakeup-source" boolean property.
1290 * If the "wakeup-source" property is set, don't request an IRQ.
1291 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1292 * if supported by the RTC.
1294 if (of_property_read_bool(client
->dev
.of_node
, "wakeup-source")) {
1295 ds1307_can_wakeup_device
= true;
1299 switch (ds1307
->type
) {
1303 /* get registers that the "rtc" read below won't read... */
1304 tmp
= ds1307
->read_block_data(ds1307
->client
,
1305 DS1337_REG_CONTROL
, 2, buf
);
1307 dev_dbg(&client
->dev
, "read error %d\n", tmp
);
1312 /* oscillator off? turn it on, so clock can tick. */
1313 if (ds1307
->regs
[0] & DS1337_BIT_nEOSC
)
1314 ds1307
->regs
[0] &= ~DS1337_BIT_nEOSC
;
1317 * Using IRQ or defined as wakeup-source?
1318 * Disable the square wave and both alarms.
1319 * For some variants, be sure alarms can trigger when we're
1320 * running on Vbackup (BBSQI/BBSQW)
1322 if (chip
->alarm
&& (ds1307
->client
->irq
> 0 ||
1323 ds1307_can_wakeup_device
)) {
1324 ds1307
->regs
[0] |= DS1337_BIT_INTCN
1325 | bbsqi_bitpos
[ds1307
->type
];
1326 ds1307
->regs
[0] &= ~(DS1337_BIT_A2IE
| DS1337_BIT_A1IE
);
1331 i2c_smbus_write_byte_data(client
, DS1337_REG_CONTROL
,
1334 /* oscillator fault? clear flag, and warn */
1335 if (ds1307
->regs
[1] & DS1337_BIT_OSF
) {
1336 i2c_smbus_write_byte_data(client
, DS1337_REG_STATUS
,
1337 ds1307
->regs
[1] & ~DS1337_BIT_OSF
);
1338 dev_warn(&client
->dev
, "SET TIME!\n");
1343 tmp
= i2c_smbus_read_i2c_block_data(ds1307
->client
,
1344 RX8025_REG_CTRL1
<< 4 | 0x08, 2, buf
);
1346 dev_dbg(&client
->dev
, "read error %d\n", tmp
);
1351 /* oscillator off? turn it on, so clock can tick. */
1352 if (!(ds1307
->regs
[1] & RX8025_BIT_XST
)) {
1353 ds1307
->regs
[1] |= RX8025_BIT_XST
;
1354 i2c_smbus_write_byte_data(client
,
1355 RX8025_REG_CTRL2
<< 4 | 0x08,
1357 dev_warn(&client
->dev
,
1358 "oscillator stop detected - SET TIME!\n");
1361 if (ds1307
->regs
[1] & RX8025_BIT_PON
) {
1362 ds1307
->regs
[1] &= ~RX8025_BIT_PON
;
1363 i2c_smbus_write_byte_data(client
,
1364 RX8025_REG_CTRL2
<< 4 | 0x08,
1366 dev_warn(&client
->dev
, "power-on detected\n");
1369 if (ds1307
->regs
[1] & RX8025_BIT_VDET
) {
1370 ds1307
->regs
[1] &= ~RX8025_BIT_VDET
;
1371 i2c_smbus_write_byte_data(client
,
1372 RX8025_REG_CTRL2
<< 4 | 0x08,
1374 dev_warn(&client
->dev
, "voltage drop detected\n");
1377 /* make sure we are running in 24hour mode */
1378 if (!(ds1307
->regs
[0] & RX8025_BIT_2412
)) {
1381 /* switch to 24 hour mode */
1382 i2c_smbus_write_byte_data(client
,
1383 RX8025_REG_CTRL1
<< 4 | 0x08,
1387 tmp
= i2c_smbus_read_i2c_block_data(ds1307
->client
,
1388 RX8025_REG_CTRL1
<< 4 | 0x08, 2, buf
);
1390 dev_dbg(&client
->dev
, "read error %d\n", tmp
);
1396 hour
= bcd2bin(ds1307
->regs
[DS1307_REG_HOUR
]);
1399 if (ds1307
->regs
[DS1307_REG_HOUR
] & DS1307_BIT_PM
)
1402 i2c_smbus_write_byte_data(client
,
1403 DS1307_REG_HOUR
<< 4 | 0x08,
1408 ds1307
->offset
= 1; /* Seconds starts at 1 */
1411 rtc_ops
= &mcp794xx_rtc_ops
;
1412 if (ds1307
->client
->irq
> 0 && chip
->alarm
) {
1413 irq_handler
= mcp794xx_irq
;
1422 /* read RTC registers */
1423 tmp
= ds1307
->read_block_data(ds1307
->client
, ds1307
->offset
, 8, buf
);
1425 dev_dbg(&client
->dev
, "read error %d\n", tmp
);
1431 * minimal sanity checking; some chips (like DS1340) don't
1432 * specify the extra bits as must-be-zero, but there are
1433 * still a few values that are clearly out-of-range.
1435 tmp
= ds1307
->regs
[DS1307_REG_SECS
];
1436 switch (ds1307
->type
) {
1439 /* clock halted? turn it on, so clock can tick. */
1440 if (tmp
& DS1307_BIT_CH
) {
1441 i2c_smbus_write_byte_data(client
, DS1307_REG_SECS
, 0);
1442 dev_warn(&client
->dev
, "SET TIME!\n");
1447 /* clock halted? turn it on, so clock can tick. */
1448 if (tmp
& DS1307_BIT_CH
)
1449 i2c_smbus_write_byte_data(client
, DS1307_REG_SECS
, 0);
1451 /* oscillator fault? clear flag, and warn */
1452 if (ds1307
->regs
[DS1307_REG_CONTROL
] & DS1338_BIT_OSF
) {
1453 i2c_smbus_write_byte_data(client
, DS1307_REG_CONTROL
,
1454 ds1307
->regs
[DS1307_REG_CONTROL
]
1456 dev_warn(&client
->dev
, "SET TIME!\n");
1461 /* clock halted? turn it on, so clock can tick. */
1462 if (tmp
& DS1340_BIT_nEOSC
)
1463 i2c_smbus_write_byte_data(client
, DS1307_REG_SECS
, 0);
1465 tmp
= i2c_smbus_read_byte_data(client
, DS1340_REG_FLAG
);
1467 dev_dbg(&client
->dev
, "read error %d\n", tmp
);
1472 /* oscillator fault? clear flag, and warn */
1473 if (tmp
& DS1340_BIT_OSF
) {
1474 i2c_smbus_write_byte_data(client
, DS1340_REG_FLAG
, 0);
1475 dev_warn(&client
->dev
, "SET TIME!\n");
1479 /* make sure that the backup battery is enabled */
1480 if (!(ds1307
->regs
[DS1307_REG_WDAY
] & MCP794XX_BIT_VBATEN
)) {
1481 i2c_smbus_write_byte_data(client
, DS1307_REG_WDAY
,
1482 ds1307
->regs
[DS1307_REG_WDAY
]
1483 | MCP794XX_BIT_VBATEN
);
1486 /* clock halted? turn it on, so clock can tick. */
1487 if (!(tmp
& MCP794XX_BIT_ST
)) {
1488 i2c_smbus_write_byte_data(client
, DS1307_REG_SECS
,
1490 dev_warn(&client
->dev
, "SET TIME!\n");
1499 tmp
= ds1307
->regs
[DS1307_REG_HOUR
];
1500 switch (ds1307
->type
) {
1504 * NOTE: ignores century bits; fix before deploying
1505 * systems that will run through year 2100.
1511 if (!(tmp
& DS1307_BIT_12HR
))
1515 * Be sure we're in 24 hour mode. Multi-master systems
1518 tmp
= bcd2bin(tmp
& 0x1f);
1521 if (ds1307
->regs
[DS1307_REG_HOUR
] & DS1307_BIT_PM
)
1523 i2c_smbus_write_byte_data(client
,
1524 ds1307
->offset
+ DS1307_REG_HOUR
,
1529 device_set_wakeup_capable(&client
->dev
, true);
1530 set_bit(HAS_ALARM
, &ds1307
->flags
);
1532 ds1307
->rtc
= devm_rtc_device_register(&client
->dev
, client
->name
,
1533 rtc_ops
, THIS_MODULE
);
1534 if (IS_ERR(ds1307
->rtc
)) {
1535 return PTR_ERR(ds1307
->rtc
);
1538 if (ds1307_can_wakeup_device
&& ds1307
->client
->irq
<= 0) {
1539 /* Disable request for an IRQ */
1541 dev_info(&client
->dev
, "'wakeup-source' is set, request for an IRQ is disabled!\n");
1542 /* We cannot support UIE mode if we do not have an IRQ line */
1543 ds1307
->rtc
->uie_unsupported
= 1;
1547 err
= devm_request_threaded_irq(&client
->dev
,
1548 client
->irq
, NULL
, irq_handler
,
1549 IRQF_SHARED
| IRQF_ONESHOT
,
1550 ds1307
->rtc
->name
, client
);
1553 device_set_wakeup_capable(&client
->dev
, false);
1554 clear_bit(HAS_ALARM
, &ds1307
->flags
);
1555 dev_err(&client
->dev
, "unable to request IRQ!\n");
1557 dev_dbg(&client
->dev
, "got IRQ %d\n", client
->irq
);
1560 if (chip
->nvram_size
) {
1562 ds1307
->nvram
= devm_kzalloc(&client
->dev
,
1563 sizeof(struct bin_attribute
),
1565 if (!ds1307
->nvram
) {
1566 dev_err(&client
->dev
, "cannot allocate memory for nvram sysfs\n");
1569 ds1307
->nvram
->attr
.name
= "nvram";
1570 ds1307
->nvram
->attr
.mode
= S_IRUGO
| S_IWUSR
;
1572 sysfs_bin_attr_init(ds1307
->nvram
);
1574 ds1307
->nvram
->read
= ds1307_nvram_read
;
1575 ds1307
->nvram
->write
= ds1307_nvram_write
;
1576 ds1307
->nvram
->size
= chip
->nvram_size
;
1577 ds1307
->nvram_offset
= chip
->nvram_offset
;
1579 err
= sysfs_create_bin_file(&client
->dev
.kobj
,
1582 dev_err(&client
->dev
,
1583 "unable to create sysfs file: %s\n",
1584 ds1307
->nvram
->attr
.name
);
1586 set_bit(HAS_NVRAM
, &ds1307
->flags
);
1587 dev_info(&client
->dev
, "%zu bytes nvram\n",
1588 ds1307
->nvram
->size
);
1593 ds1307_hwmon_register(ds1307
);
1594 ds1307_clks_register(ds1307
);
1602 static int ds1307_remove(struct i2c_client
*client
)
1604 struct ds1307
*ds1307
= i2c_get_clientdata(client
);
1606 if (test_and_clear_bit(HAS_NVRAM
, &ds1307
->flags
))
1607 sysfs_remove_bin_file(&client
->dev
.kobj
, ds1307
->nvram
);
1612 static struct i2c_driver ds1307_driver
= {
1614 .name
= "rtc-ds1307",
1616 .probe
= ds1307_probe
,
1617 .remove
= ds1307_remove
,
1618 .id_table
= ds1307_id
,
1621 module_i2c_driver(ds1307_driver
);
1623 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1624 MODULE_LICENSE("GPL");