drivers/rtc/rtc-imxdi.c

   1 /*
   2  * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2010 Orex Computed Radiography
   4  */
   5
   6 /*
   7  * The code contained herein is licensed under the GNU General Public
   8  * License. You may obtain a copy of the GNU General Public License
   9  * Version 2 or later at the following locations:
  10  *
  11  * http://www.opensource.org/licenses/gpl-license.html
  12  * http://www.gnu.org/copyleft/gpl.html
  13  */
  14
  15 /* based on rtc-mc13892.c */
  16
  17 /*
  18  * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
  19  * to implement a Linux RTC. Times and alarms are truncated to seconds.
  20  * Since the RTC framework performs API locking via rtc->ops_lock the
  21  * only simultaneous accesses we need to deal with is updating DryIce
  22  * registers while servicing an alarm.
  23  *
  24  * Note that reading the DSR (DryIce Status Register) automatically clears
  25  * the WCF (Write Complete Flag). All DryIce writes are synchronized to the
  26  * LP (Low Power) domain and set the WCF upon completion. Writes to the
  27  * DIER (DryIce Interrupt Enable Register) are the only exception. These
  28  * occur at normal bus speeds and do not set WCF.  Periodic interrupts are
  29  * not supported by the hardware.
  30  */
  31
  32 #include <linux/io.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <linux/module.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/rtc.h>
  38 #include <linux/sched.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/of.h>
  42
  43 /* DryIce Register Definitions */
  44
  45 #define DTCMR     0x00           /* Time Counter MSB Reg */
  46 #define DTCLR     0x04           /* Time Counter LSB Reg */
  47
  48 #define DCAMR     0x08           /* Clock Alarm MSB Reg */
  49 #define DCALR     0x0c           /* Clock Alarm LSB Reg */
  50 #define DCAMR_UNSET  0xFFFFFFFF  /* doomsday - 1 sec */
  51
  52 #define DCR       0x10           /* Control Reg */
  53 #define DCR_TDCHL (1 << 30)      /* Tamper-detect configuration hard lock */
  54 #define DCR_TDCSL (1 << 29)      /* Tamper-detect configuration soft lock */
  55 #define DCR_KSSL  (1 << 27)      /* Key-select soft lock */
  56 #define DCR_MCHL  (1 << 20)      /* Monotonic-counter hard lock */
  57 #define DCR_MCSL  (1 << 19)      /* Monotonic-counter soft lock */
  58 #define DCR_TCHL  (1 << 18)      /* Timer-counter hard lock */
  59 #define DCR_TCSL  (1 << 17)      /* Timer-counter soft lock */
  60 #define DCR_FSHL  (1 << 16)      /* Failure state hard lock */
  61 #define DCR_TCE   (1 << 3)       /* Time Counter Enable */
  62 #define DCR_MCE   (1 << 2)       /* Monotonic Counter Enable */
  63
  64 #define DSR       0x14           /* Status Reg */
  65 #define DSR_WTD   (1 << 23)      /* Wire-mesh tamper detected */
  66 #define DSR_ETBD  (1 << 22)      /* External tamper B detected */
  67 #define DSR_ETAD  (1 << 21)      /* External tamper A detected */
  68 #define DSR_EBD   (1 << 20)      /* External boot detected */
  69 #define DSR_SAD   (1 << 19)      /* SCC alarm detected */
  70 #define DSR_TTD   (1 << 18)      /* Temperatur tamper detected */
  71 #define DSR_CTD   (1 << 17)      /* Clock tamper detected */
  72 #define DSR_VTD   (1 << 16)      /* Voltage tamper detected */
  73 #define DSR_WBF   (1 << 10)      /* Write Busy Flag (synchronous) */
  74 #define DSR_WNF   (1 << 9)       /* Write Next Flag (synchronous) */
  75 #define DSR_WCF   (1 << 8)       /* Write Complete Flag (synchronous)*/
  76 #define DSR_WEF   (1 << 7)       /* Write Error Flag */
  77 #define DSR_CAF   (1 << 4)       /* Clock Alarm Flag */
  78 #define DSR_MCO   (1 << 3)       /* monotonic counter overflow */
  79 #define DSR_TCO   (1 << 2)       /* time counter overflow */
  80 #define DSR_NVF   (1 << 1)       /* Non-Valid Flag */
  81 #define DSR_SVF   (1 << 0)       /* Security Violation Flag */
  82
  83 #define DIER      0x18           /* Interrupt Enable Reg (synchronous) */
  84 #define DIER_WNIE (1 << 9)       /* Write Next Interrupt Enable */
  85 #define DIER_WCIE (1 << 8)       /* Write Complete Interrupt Enable */
  86 #define DIER_WEIE (1 << 7)       /* Write Error Interrupt Enable */
  87 #define DIER_CAIE (1 << 4)       /* Clock Alarm Interrupt Enable */
  88 #define DIER_SVIE (1 << 0)       /* Security-violation Interrupt Enable */
  89
  90 #define DMCR      0x1c           /* DryIce Monotonic Counter Reg */
  91
  92 #define DTCR      0x28           /* DryIce Tamper Configuration Reg */
  93 #define DTCR_MOE  (1 << 9)       /* monotonic overflow enabled */
  94 #define DTCR_TOE  (1 << 8)       /* time overflow enabled */
  95 #define DTCR_WTE  (1 << 7)       /* wire-mesh tamper enabled */
  96 #define DTCR_ETBE (1 << 6)       /* external B tamper enabled */
  97 #define DTCR_ETAE (1 << 5)       /* external A tamper enabled */
  98 #define DTCR_EBE  (1 << 4)       /* external boot tamper enabled */
  99 #define DTCR_SAIE (1 << 3)       /* SCC enabled */
 100 #define DTCR_TTE  (1 << 2)       /* temperature tamper enabled */
 101 #define DTCR_CTE  (1 << 1)       /* clock tamper enabled */
 102 #define DTCR_VTE  (1 << 0)       /* voltage tamper enabled */
 103
 104 #define DGPR      0x3c           /* DryIce General Purpose Reg */
 105
 106 /**
 107  * struct imxdi_dev - private imxdi rtc data
 108  * @pdev: pionter to platform dev
 109  * @rtc: pointer to rtc struct
 110  * @ioaddr: IO registers pointer
 111  * @irq: dryice normal interrupt
 112  * @clk: input reference clock
 113  * @dsr: copy of the DSR register
 114  * @irq_lock: interrupt enable register (DIER) lock
 115  * @write_wait: registers write complete queue
 116  * @write_mutex: serialize registers write
 117  * @work: schedule alarm work
 118  */
 119 struct imxdi_dev {
 120         struct platform_device *pdev;
 121         struct rtc_device *rtc;
 122         void __iomem *ioaddr;
 123         int irq;
 124         struct clk *clk;
 125         u32 dsr;
 126         spinlock_t irq_lock;
 127         wait_queue_head_t write_wait;
 128         struct mutex write_mutex;
 129         struct work_struct work;
 130 };
 131
 132 /*
 133  * enable a dryice interrupt
 134  */
 135 static void di_int_enable(struct imxdi_dev *imxdi, u32 intr)
 136 {
 137         unsigned long flags;
 138
 139         spin_lock_irqsave(&imxdi->irq_lock, flags);
 140         __raw_writel(__raw_readl(imxdi->ioaddr + DIER) | intr,
 141                         imxdi->ioaddr + DIER);
 142         spin_unlock_irqrestore(&imxdi->irq_lock, flags);
 143 }
 144
 145 /*
 146  * disable a dryice interrupt
 147  */
 148 static void di_int_disable(struct imxdi_dev *imxdi, u32 intr)
 149 {
 150         unsigned long flags;
 151
 152         spin_lock_irqsave(&imxdi->irq_lock, flags);
 153         __raw_writel(__raw_readl(imxdi->ioaddr + DIER) & ~intr,
 154                         imxdi->ioaddr + DIER);
 155         spin_unlock_irqrestore(&imxdi->irq_lock, flags);
 156 }
 157
 158 /*
 159  * This function attempts to clear the dryice write-error flag.
 160  *
 161  * A dryice write error is similar to a bus fault and should not occur in
 162  * normal operation.  Clearing the flag requires another write, so the root
 163  * cause of the problem may need to be fixed before the flag can be cleared.
 164  */
 165 static void clear_write_error(struct imxdi_dev *imxdi)
 166 {
 167         int cnt;
 168
 169         dev_warn(&imxdi->pdev->dev, "WARNING: Register write error!\n");
 170
 171         /* clear the write error flag */
 172         __raw_writel(DSR_WEF, imxdi->ioaddr + DSR);
 173
 174         /* wait for it to take effect */
 175         for (cnt = 0; cnt < 1000; cnt++) {
 176                 if ((__raw_readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0)
 177                         return;
 178                 udelay(10);
 179         }
 180         dev_err(&imxdi->pdev->dev,
 181                         "ERROR: Cannot clear write-error flag!\n");
 182 }
 183
 184 /*
 185  * Write a dryice register and wait until it completes.
 186  *
 187  * This function uses interrupts to determine when the
 188  * write has completed.
 189  */
 190 static int di_write_wait(struct imxdi_dev *imxdi, u32 val, int reg)
 191 {
 192         int ret;
 193         int rc = 0;
 194
 195         /* serialize register writes */
 196         mutex_lock(&imxdi->write_mutex);
 197
 198         /* enable the write-complete interrupt */
 199         di_int_enable(imxdi, DIER_WCIE);
 200
 201         imxdi->dsr = 0;
 202
 203         /* do the register write */
 204         __raw_writel(val, imxdi->ioaddr + reg);
 205
 206         /* wait for the write to finish */
 207         ret = wait_event_interruptible_timeout(imxdi->write_wait,
 208                         imxdi->dsr & (DSR_WCF | DSR_WEF), msecs_to_jiffies(1));
 209         if (ret < 0) {
 210                 rc = ret;
 211                 goto out;
 212         } else if (ret == 0) {
 213                 dev_warn(&imxdi->pdev->dev,
 214                                 "Write-wait timeout "
 215                                 "val = 0x%08x reg = 0x%08x\n", val, reg);
 216         }
 217
 218         /* check for write error */
 219         if (imxdi->dsr & DSR_WEF) {
 220                 clear_write_error(imxdi);
 221                 rc = -EIO;
 222         }
 223
 224 out:
 225         mutex_unlock(&imxdi->write_mutex);
 226
 227         return rc;
 228 }
 229
 230 /*
 231  * read the seconds portion of the current time from the dryice time counter
 232  */
 233 static int dryice_rtc_read_time(struct device *dev, struct rtc_time *tm)
 234 {
 235         struct imxdi_dev *imxdi = dev_get_drvdata(dev);
 236         unsigned long now;
 237
 238         now = __raw_readl(imxdi->ioaddr + DTCMR);
 239         rtc_time_to_tm(now, tm);
 240
 241         return 0;
 242 }
 243
 244 /*
 245  * set the seconds portion of dryice time counter and clear the
 246  * fractional part.
 247  */
 248 static int dryice_rtc_set_mmss(struct device *dev, unsigned long secs)
 249 {
 250         struct imxdi_dev *imxdi = dev_get_drvdata(dev);
 251         int rc;
 252
 253         /* zero the fractional part first */
 254         rc = di_write_wait(imxdi, 0, DTCLR);
 255         if (rc == 0)
 256                 rc = di_write_wait(imxdi, secs, DTCMR);
 257
 258         return rc;
 259 }
 260
 261 static int dryice_rtc_alarm_irq_enable(struct device *dev,
 262                 unsigned int enabled)
 263 {
 264         struct imxdi_dev *imxdi = dev_get_drvdata(dev);
 265
 266         if (enabled)
 267                 di_int_enable(imxdi, DIER_CAIE);
 268         else
 269                 di_int_disable(imxdi, DIER_CAIE);
 270
 271         return 0;
 272 }
 273
 274 /*
 275  * read the seconds portion of the alarm register.
 276  * the fractional part of the alarm register is always zero.
 277  */
 278 static int dryice_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 279 {
 280         struct imxdi_dev *imxdi = dev_get_drvdata(dev);
 281         u32 dcamr;
 282
 283         dcamr = __raw_readl(imxdi->ioaddr + DCAMR);
 284         rtc_time_to_tm(dcamr, &alarm->time);
 285
 286         /* alarm is enabled if the interrupt is enabled */
 287         alarm->enabled = (__raw_readl(imxdi->ioaddr + DIER) & DIER_CAIE) != 0;
 288
 289         /* don't allow the DSR read to mess up DSR_WCF */
 290         mutex_lock(&imxdi->write_mutex);
 291
 292         /* alarm is pending if the alarm flag is set */
 293         alarm->pending = (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0;
 294
 295         mutex_unlock(&imxdi->write_mutex);
 296
 297         return 0;
 298 }
 299
 300 /*
 301  * set the seconds portion of dryice alarm register
 302  */
 303 static int dryice_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 304 {
 305         struct imxdi_dev *imxdi = dev_get_drvdata(dev);
 306         unsigned long now;
 307         unsigned long alarm_time;
 308         int rc;
 309
 310         rc = rtc_tm_to_time(&alarm->time, &alarm_time);
 311         if (rc)
 312                 return rc;
 313
 314         /* don't allow setting alarm in the past */
 315         now = __raw_readl(imxdi->ioaddr + DTCMR);
 316         if (alarm_time < now)
 317                 return -EINVAL;
 318
 319         /* write the new alarm time */
 320         rc = di_write_wait(imxdi, (u32)alarm_time, DCAMR);
 321         if (rc)
 322                 return rc;
 323
 324         if (alarm->enabled)
 325                 di_int_enable(imxdi, DIER_CAIE);  /* enable alarm intr */
 326         else
 327                 di_int_disable(imxdi, DIER_CAIE); /* disable alarm intr */
 328
 329         return 0;
 330 }
 331
 332 static struct rtc_class_ops dryice_rtc_ops = {
 333         .read_time              = dryice_rtc_read_time,
 334         .set_mmss               = dryice_rtc_set_mmss,
 335         .alarm_irq_enable       = dryice_rtc_alarm_irq_enable,
 336         .read_alarm             = dryice_rtc_read_alarm,
 337         .set_alarm              = dryice_rtc_set_alarm,
 338 };
 339
 340 /*
 341  * dryice "normal" interrupt handler
 342  */
 343 static irqreturn_t dryice_norm_irq(int irq, void *dev_id)
 344 {
 345         struct imxdi_dev *imxdi = dev_id;
 346         u32 dsr, dier;
 347         irqreturn_t rc = IRQ_NONE;
 348
 349         dier = __raw_readl(imxdi->ioaddr + DIER);
 350
 351         /* handle write complete and write error cases */
 352         if (dier & DIER_WCIE) {
 353                 /*If the write wait queue is empty then there is no pending
 354                   operations. It means the interrupt is for DryIce -Security.
 355                   IRQ must be returned as none.*/
 356                 if (list_empty_careful(&imxdi->write_wait.task_list))
 357                         return rc;
 358
 359                 /* DSR_WCF clears itself on DSR read */
 360                 dsr = __raw_readl(imxdi->ioaddr + DSR);
 361                 if (dsr & (DSR_WCF | DSR_WEF)) {
 362                         /* mask the interrupt */
 363                         di_int_disable(imxdi, DIER_WCIE);
 364
 365                         /* save the dsr value for the wait queue */
 366                         imxdi->dsr |= dsr;
 367
 368                         wake_up_interruptible(&imxdi->write_wait);
 369                         rc = IRQ_HANDLED;
 370                 }
 371         }
 372
 373         /* handle the alarm case */
 374         if (dier & DIER_CAIE) {
 375                 /* DSR_WCF clears itself on DSR read */
 376                 dsr = __raw_readl(imxdi->ioaddr + DSR);
 377                 if (dsr & DSR_CAF) {
 378                         /* mask the interrupt */
 379                         di_int_disable(imxdi, DIER_CAIE);
 380
 381                         /* finish alarm in user context */
 382                         schedule_work(&imxdi->work);
 383                         rc = IRQ_HANDLED;
 384                 }
 385         }
 386         return rc;
 387 }
 388
 389 /*
 390  * post the alarm event from user context so it can sleep
 391  * on the write completion.
 392  */
 393 static void dryice_work(struct work_struct *work)
 394 {
 395         struct imxdi_dev *imxdi = container_of(work,
 396                         struct imxdi_dev, work);
 397
 398         /* dismiss the interrupt (ignore error) */
 399         di_write_wait(imxdi, DSR_CAF, DSR);
 400
 401         /* pass the alarm event to the rtc framework. */
 402         rtc_update_irq(imxdi->rtc, 1, RTC_AF | RTC_IRQF);
 403 }
 404
 405 /*
 406  * probe for dryice rtc device
 407  */
 408 static int __init dryice_rtc_probe(struct platform_device *pdev)
 409 {
 410         struct resource *res;
 411         struct imxdi_dev *imxdi;
 412         int rc;
 413
 414         imxdi = devm_kzalloc(&pdev->dev, sizeof(*imxdi), GFP_KERNEL);
 415         if (!imxdi)
 416                 return -ENOMEM;
 417
 418         imxdi->pdev = pdev;
 419
 420         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 421         imxdi->ioaddr = devm_ioremap_resource(&pdev->dev, res);
 422         if (IS_ERR(imxdi->ioaddr))
 423                 return PTR_ERR(imxdi->ioaddr);
 424
 425         spin_lock_init(&imxdi->irq_lock);
 426
 427         imxdi->irq = platform_get_irq(pdev, 0);
 428         if (imxdi->irq < 0)
 429                 return imxdi->irq;
 430
 431         init_waitqueue_head(&imxdi->write_wait);
 432
 433         INIT_WORK(&imxdi->work, dryice_work);
 434
 435         mutex_init(&imxdi->write_mutex);
 436
 437         imxdi->clk = devm_clk_get(&pdev->dev, NULL);
 438         if (IS_ERR(imxdi->clk))
 439                 return PTR_ERR(imxdi->clk);
 440         rc = clk_prepare_enable(imxdi->clk);
 441         if (rc)
 442                 return rc;
 443
 444         /*
 445          * Initialize dryice hardware
 446          */
 447
 448         /* mask all interrupts */
 449         __raw_writel(0, imxdi->ioaddr + DIER);
 450
 451         rc = devm_request_irq(&pdev->dev, imxdi->irq, dryice_norm_irq,
 452                         IRQF_SHARED, pdev->name, imxdi);
 453         if (rc) {
 454                 dev_warn(&pdev->dev, "interrupt not available.\n");
 455                 goto err;
 456         }
 457
 458         /* put dryice into valid state */
 459         if (__raw_readl(imxdi->ioaddr + DSR) & DSR_NVF) {
 460                 rc = di_write_wait(imxdi, DSR_NVF | DSR_SVF, DSR);
 461                 if (rc)
 462                         goto err;
 463         }
 464
 465         /* initialize alarm */
 466         rc = di_write_wait(imxdi, DCAMR_UNSET, DCAMR);
 467         if (rc)
 468                 goto err;
 469         rc = di_write_wait(imxdi, 0, DCALR);
 470         if (rc)
 471                 goto err;
 472
 473         /* clear alarm flag */
 474         if (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) {
 475                 rc = di_write_wait(imxdi, DSR_CAF, DSR);
 476                 if (rc)
 477                         goto err;
 478         }
 479
 480         /* the timer won't count if it has never been written to */
 481         if (__raw_readl(imxdi->ioaddr + DTCMR) == 0) {
 482                 rc = di_write_wait(imxdi, 0, DTCMR);
 483                 if (rc)
 484                         goto err;
 485         }
 486
 487         /* start keeping time */
 488         if (!(__raw_readl(imxdi->ioaddr + DCR) & DCR_TCE)) {
 489                 rc = di_write_wait(imxdi,
 490                                 __raw_readl(imxdi->ioaddr + DCR) | DCR_TCE,
 491                                 DCR);
 492                 if (rc)
 493                         goto err;
 494         }
 495
 496         platform_set_drvdata(pdev, imxdi);
 497         imxdi->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
 498                                   &dryice_rtc_ops, THIS_MODULE);
 499         if (IS_ERR(imxdi->rtc)) {
 500                 rc = PTR_ERR(imxdi->rtc);
 501                 goto err;
 502         }
 503
 504         return 0;
 505
 506 err:
 507         clk_disable_unprepare(imxdi->clk);
 508
 509         return rc;
 510 }
 511
 512 static int __exit dryice_rtc_remove(struct platform_device *pdev)
 513 {
 514         struct imxdi_dev *imxdi = platform_get_drvdata(pdev);
 515
 516         flush_work(&imxdi->work);
 517
 518         /* mask all interrupts */
 519         __raw_writel(0, imxdi->ioaddr + DIER);
 520
 521         clk_disable_unprepare(imxdi->clk);
 522
 523         return 0;
 524 }
 525
 526 #ifdef CONFIG_OF
 527 static const struct of_device_id dryice_dt_ids[] = {
 528         { .compatible = "fsl,imx25-rtc" },
 529         { /* sentinel */ }
 530 };
 531
 532 MODULE_DEVICE_TABLE(of, dryice_dt_ids);
 533 #endif
 534
 535 static struct platform_driver dryice_rtc_driver = {
 536         .driver = {
 537                    .name = "imxdi_rtc",
 538                    .of_match_table = of_match_ptr(dryice_dt_ids),
 539                    },
 540         .remove = __exit_p(dryice_rtc_remove),
 541 };
 542
 543 module_platform_driver_probe(dryice_rtc_driver, dryice_rtc_probe);
 544
 545 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
 546 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
 547 MODULE_DESCRIPTION("IMX DryIce Realtime Clock Driver (RTC)");
 548 MODULE_LICENSE("GPL");