2 * An SPI driver for the Philips PCF2123 RTC
3 * Copyright 2009 Cyber Switching, Inc.
5 * Author: Chris Verges <chrisv@cyberswitching.com>
6 * Maintainers: http://www.cyberswitching.com
8 * based on the RS5C348 driver in this same directory.
10 * Thanks to Christian Pellegrin <chripell@fsfe.org> for
11 * the sysfs contributions to this driver.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
17 * Please note that the CS is active high, so platform data
18 * should look something like:
20 * static struct spi_board_info ek_spi_devices[] = {
23 * .modalias = "rtc-pcf2123",
25 * .controller_data = (void *)AT91_PIN_PA10,
26 * .max_speed_hz = 1000 * 1000,
27 * .mode = SPI_CS_HIGH,
35 #include <linux/bcd.h>
36 #include <linux/delay.h>
37 #include <linux/device.h>
38 #include <linux/errno.h>
39 #include <linux/init.h>
40 #include <linux/kernel.h>
42 #include <linux/string.h>
43 #include <linux/slab.h>
44 #include <linux/rtc.h>
45 #include <linux/spi/spi.h>
46 #include <linux/module.h>
47 #include <linux/sysfs.h>
49 #define DRV_VERSION "0.6"
52 #define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */
53 #define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */
54 #define PCF2123_REG_SC (0x02) /* datetime */
55 #define PCF2123_REG_MN (0x03)
56 #define PCF2123_REG_HR (0x04)
57 #define PCF2123_REG_DM (0x05)
58 #define PCF2123_REG_DW (0x06)
59 #define PCF2123_REG_MO (0x07)
60 #define PCF2123_REG_YR (0x08)
61 #define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */
62 #define PCF2123_REG_ALRM_HR (0x0a)
63 #define PCF2123_REG_ALRM_DM (0x0b)
64 #define PCF2123_REG_ALRM_DW (0x0c)
65 #define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */
66 #define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */
67 #define PCF2123_REG_CTDWN_TMR (0x0f)
69 /* PCF2123_REG_CTRL1 BITS */
70 #define CTRL1_CLEAR (0) /* Clear */
71 #define CTRL1_CORR_INT BIT(1) /* Correction irq enable */
72 #define CTRL1_12_HOUR BIT(2) /* 12 hour time */
73 #define CTRL1_SW_RESET (BIT(3) | BIT(4) | BIT(6)) /* Software reset */
74 #define CTRL1_STOP BIT(5) /* Stop the clock */
75 #define CTRL1_EXT_TEST BIT(7) /* External clock test mode */
77 /* PCF2123_REG_CTRL2 BITS */
78 #define CTRL2_TIE BIT(0) /* Countdown timer irq enable */
79 #define CTRL2_AIE BIT(1) /* Alarm irq enable */
80 #define CTRL2_TF BIT(2) /* Countdown timer flag */
81 #define CTRL2_AF BIT(3) /* Alarm flag */
82 #define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */
83 #define CTRL2_MSF BIT(5) /* Minute or second irq flag */
84 #define CTRL2_SI BIT(6) /* Second irq enable */
85 #define CTRL2_MI BIT(7) /* Minute irq enable */
87 /* PCF2123_REG_SC BITS */
88 #define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */
90 /* PCF2123_REG_ALRM_XX BITS */
91 #define ALRM_ENABLE BIT(7) /* MN, HR, DM, or DW alarm enable */
93 /* PCF2123_REG_TMR_CLKOUT BITS */
94 #define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */
95 #define CD_TMR_64HZ (1) /* 64 Hz countdown timer */
96 #define CD_TMR_1HZ (2) /* 1 Hz countdown timer */
97 #define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */
98 #define CD_TMR_TE BIT(3) /* Countdown timer enable */
100 /* PCF2123_REG_OFFSET BITS */
101 #define OFFSET_SIGN_BIT BIT(6) /* 2's complement sign bit */
102 #define OFFSET_COARSE BIT(7) /* Coarse mode offset */
104 /* READ/WRITE ADDRESS BITS */
105 #define PCF2123_WRITE BIT(4)
106 #define PCF2123_READ (BIT(4) | BIT(7))
109 static struct spi_driver pcf2123_driver
;
111 struct pcf2123_sysfs_reg
{
112 struct device_attribute attr
;
116 struct pcf2123_plat_data
{
117 struct rtc_device
*rtc
;
118 struct pcf2123_sysfs_reg regs
[16];
122 * Causes a 30 nanosecond delay to ensure that the PCF2123 chip select
123 * is released properly after an SPI write. This function should be
124 * called after EVERY read/write call over SPI.
126 static inline void pcf2123_delay_trec(void)
131 static ssize_t
pcf2123_show(struct device
*dev
, struct device_attribute
*attr
,
134 struct spi_device
*spi
= to_spi_device(dev
);
135 struct pcf2123_sysfs_reg
*r
;
136 u8 txbuf
[1], rxbuf
[1];
140 r
= container_of(attr
, struct pcf2123_sysfs_reg
, attr
);
142 ret
= kstrtoul(r
->name
, 16, ®
);
146 txbuf
[0] = PCF2123_READ
| reg
;
147 ret
= spi_write_then_read(spi
, txbuf
, 1, rxbuf
, 1);
150 pcf2123_delay_trec();
151 return sprintf(buffer
, "0x%x\n", rxbuf
[0]);
154 static ssize_t
pcf2123_store(struct device
*dev
, struct device_attribute
*attr
,
155 const char *buffer
, size_t count
) {
156 struct spi_device
*spi
= to_spi_device(dev
);
157 struct pcf2123_sysfs_reg
*r
;
164 r
= container_of(attr
, struct pcf2123_sysfs_reg
, attr
);
166 ret
= kstrtoul(r
->name
, 16, ®
);
170 ret
= kstrtoul(buffer
, 10, &val
);
174 txbuf
[0] = PCF2123_WRITE
| reg
;
176 ret
= spi_write(spi
, txbuf
, sizeof(txbuf
));
179 pcf2123_delay_trec();
183 static int pcf2123_rtc_read_time(struct device
*dev
, struct rtc_time
*tm
)
185 struct spi_device
*spi
= to_spi_device(dev
);
186 u8 txbuf
[1], rxbuf
[7];
189 txbuf
[0] = PCF2123_READ
| PCF2123_REG_SC
;
190 ret
= spi_write_then_read(spi
, txbuf
, sizeof(txbuf
),
191 rxbuf
, sizeof(rxbuf
));
194 pcf2123_delay_trec();
196 tm
->tm_sec
= bcd2bin(rxbuf
[0] & 0x7F);
197 tm
->tm_min
= bcd2bin(rxbuf
[1] & 0x7F);
198 tm
->tm_hour
= bcd2bin(rxbuf
[2] & 0x3F); /* rtc hr 0-23 */
199 tm
->tm_mday
= bcd2bin(rxbuf
[3] & 0x3F);
200 tm
->tm_wday
= rxbuf
[4] & 0x07;
201 tm
->tm_mon
= bcd2bin(rxbuf
[5] & 0x1F) - 1; /* rtc mn 1-12 */
202 tm
->tm_year
= bcd2bin(rxbuf
[6]);
203 if (tm
->tm_year
< 70)
204 tm
->tm_year
+= 100; /* assume we are in 1970...2069 */
206 dev_dbg(dev
, "%s: tm is secs=%d, mins=%d, hours=%d, "
207 "mday=%d, mon=%d, year=%d, wday=%d\n",
209 tm
->tm_sec
, tm
->tm_min
, tm
->tm_hour
,
210 tm
->tm_mday
, tm
->tm_mon
, tm
->tm_year
, tm
->tm_wday
);
212 return rtc_valid_tm(tm
);
215 static int pcf2123_rtc_set_time(struct device
*dev
, struct rtc_time
*tm
)
217 struct spi_device
*spi
= to_spi_device(dev
);
221 dev_dbg(dev
, "%s: tm is secs=%d, mins=%d, hours=%d, "
222 "mday=%d, mon=%d, year=%d, wday=%d\n",
224 tm
->tm_sec
, tm
->tm_min
, tm
->tm_hour
,
225 tm
->tm_mday
, tm
->tm_mon
, tm
->tm_year
, tm
->tm_wday
);
227 /* Stop the counter first */
228 txbuf
[0] = PCF2123_WRITE
| PCF2123_REG_CTRL1
;
230 ret
= spi_write(spi
, txbuf
, 2);
233 pcf2123_delay_trec();
235 /* Set the new time */
236 txbuf
[0] = PCF2123_WRITE
| PCF2123_REG_SC
;
237 txbuf
[1] = bin2bcd(tm
->tm_sec
& 0x7F);
238 txbuf
[2] = bin2bcd(tm
->tm_min
& 0x7F);
239 txbuf
[3] = bin2bcd(tm
->tm_hour
& 0x3F);
240 txbuf
[4] = bin2bcd(tm
->tm_mday
& 0x3F);
241 txbuf
[5] = tm
->tm_wday
& 0x07;
242 txbuf
[6] = bin2bcd((tm
->tm_mon
+ 1) & 0x1F); /* rtc mn 1-12 */
243 txbuf
[7] = bin2bcd(tm
->tm_year
< 100 ? tm
->tm_year
: tm
->tm_year
- 100);
245 ret
= spi_write(spi
, txbuf
, sizeof(txbuf
));
248 pcf2123_delay_trec();
250 /* Start the counter */
251 txbuf
[0] = PCF2123_WRITE
| PCF2123_REG_CTRL1
;
253 ret
= spi_write(spi
, txbuf
, 2);
256 pcf2123_delay_trec();
261 static const struct rtc_class_ops pcf2123_rtc_ops
= {
262 .read_time
= pcf2123_rtc_read_time
,
263 .set_time
= pcf2123_rtc_set_time
,
266 static int pcf2123_probe(struct spi_device
*spi
)
268 struct rtc_device
*rtc
;
269 struct pcf2123_plat_data
*pdata
;
270 u8 txbuf
[2], rxbuf
[2];
273 pdata
= devm_kzalloc(&spi
->dev
, sizeof(struct pcf2123_plat_data
),
277 spi
->dev
.platform_data
= pdata
;
279 /* Send a software reset command */
280 txbuf
[0] = PCF2123_WRITE
| PCF2123_REG_CTRL1
;
282 dev_dbg(&spi
->dev
, "resetting RTC (0x%02X 0x%02X)\n",
284 ret
= spi_write(spi
, txbuf
, 2 * sizeof(u8
));
287 pcf2123_delay_trec();
289 /* Stop the counter */
290 txbuf
[0] = PCF2123_WRITE
| PCF2123_REG_CTRL1
;
292 dev_dbg(&spi
->dev
, "stopping RTC (0x%02X 0x%02X)\n",
294 ret
= spi_write(spi
, txbuf
, 2 * sizeof(u8
));
297 pcf2123_delay_trec();
299 /* See if the counter was actually stopped */
300 txbuf
[0] = PCF2123_READ
| PCF2123_REG_CTRL1
;
301 dev_dbg(&spi
->dev
, "checking for presence of RTC (0x%02X)\n",
303 ret
= spi_write_then_read(spi
, txbuf
, 1 * sizeof(u8
),
304 rxbuf
, 2 * sizeof(u8
));
305 dev_dbg(&spi
->dev
, "received data from RTC (0x%02X 0x%02X)\n",
309 pcf2123_delay_trec();
311 if (!(rxbuf
[0] & 0x20)) {
312 dev_err(&spi
->dev
, "chip not found\n");
317 dev_info(&spi
->dev
, "chip found, driver version " DRV_VERSION
"\n");
318 dev_info(&spi
->dev
, "spiclk %u KHz.\n",
319 (spi
->max_speed_hz
+ 500) / 1000);
321 /* Start the counter */
322 txbuf
[0] = PCF2123_WRITE
| PCF2123_REG_CTRL1
;
324 ret
= spi_write(spi
, txbuf
, sizeof(txbuf
));
327 pcf2123_delay_trec();
329 /* Finalize the initialization */
330 rtc
= devm_rtc_device_register(&spi
->dev
, pcf2123_driver
.driver
.name
,
331 &pcf2123_rtc_ops
, THIS_MODULE
);
334 dev_err(&spi
->dev
, "failed to register.\n");
341 for (i
= 0; i
< 16; i
++) {
342 sysfs_attr_init(&pdata
->regs
[i
].attr
.attr
);
343 sprintf(pdata
->regs
[i
].name
, "%1x", i
);
344 pdata
->regs
[i
].attr
.attr
.mode
= S_IRUGO
| S_IWUSR
;
345 pdata
->regs
[i
].attr
.attr
.name
= pdata
->regs
[i
].name
;
346 pdata
->regs
[i
].attr
.show
= pcf2123_show
;
347 pdata
->regs
[i
].attr
.store
= pcf2123_store
;
348 ret
= device_create_file(&spi
->dev
, &pdata
->regs
[i
].attr
);
350 dev_err(&spi
->dev
, "Unable to create sysfs %s\n",
351 pdata
->regs
[i
].name
);
359 for (i
--; i
>= 0; i
--)
360 device_remove_file(&spi
->dev
, &pdata
->regs
[i
].attr
);
363 spi
->dev
.platform_data
= NULL
;
367 static int pcf2123_remove(struct spi_device
*spi
)
369 struct pcf2123_plat_data
*pdata
= dev_get_platdata(&spi
->dev
);
373 for (i
= 0; i
< 16; i
++)
374 if (pdata
->regs
[i
].name
[0])
375 device_remove_file(&spi
->dev
,
376 &pdata
->regs
[i
].attr
);
383 static const struct of_device_id pcf2123_dt_ids
[] = {
384 { .compatible
= "nxp,rtc-pcf2123", },
387 MODULE_DEVICE_TABLE(of
, pcf2123_dt_ids
);
390 static struct spi_driver pcf2123_driver
= {
392 .name
= "rtc-pcf2123",
393 .of_match_table
= of_match_ptr(pcf2123_dt_ids
),
395 .probe
= pcf2123_probe
,
396 .remove
= pcf2123_remove
,
399 module_spi_driver(pcf2123_driver
);
401 MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
402 MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
403 MODULE_LICENSE("GPL");
404 MODULE_VERSION(DRV_VERSION
);