drivers/scsi/NCR5380.h

   1 /*
   2  * NCR 5380 defines
   3  *
   4  * Copyright 1993, Drew Eckhardt
   5  *      Visionary Computing
   6  *      (Unix consulting and custom programming)
   7  *      drew@colorado.edu
   8  *      +1 (303) 666-5836
   9  *
  10  * For more information, please consult
  11  *
  12  * NCR 5380 Family
  13  * SCSI Protocol Controller
  14  * Databook
  15  * NCR Microelectronics
  16  * 1635 Aeroplaza Drive
  17  * Colorado Springs, CO 80916
  18  * 1+ (719) 578-3400
  19  * 1+ (800) 334-5454
  20  */
  21
  22 #ifndef NCR5380_H
  23 #define NCR5380_H
  24
  25 #include <linux/delay.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/workqueue.h>
  28 #include <scsi/scsi_dbg.h>
  29 #include <scsi/scsi_eh.h>
  30 #include <scsi/scsi_transport_spi.h>
  31
  32 #define NDEBUG_ARBITRATION      0x1
  33 #define NDEBUG_AUTOSENSE        0x2
  34 #define NDEBUG_DMA              0x4
  35 #define NDEBUG_HANDSHAKE        0x8
  36 #define NDEBUG_INFORMATION      0x10
  37 #define NDEBUG_INIT             0x20
  38 #define NDEBUG_INTR             0x40
  39 #define NDEBUG_LINKED           0x80
  40 #define NDEBUG_MAIN             0x100
  41 #define NDEBUG_NO_DATAOUT       0x200
  42 #define NDEBUG_NO_WRITE         0x400
  43 #define NDEBUG_PIO              0x800
  44 #define NDEBUG_PSEUDO_DMA       0x1000
  45 #define NDEBUG_QUEUES           0x2000
  46 #define NDEBUG_RESELECTION      0x4000
  47 #define NDEBUG_SELECTION        0x8000
  48 #define NDEBUG_USLEEP           0x10000
  49 #define NDEBUG_LAST_BYTE_SENT   0x20000
  50 #define NDEBUG_RESTART_SELECT   0x40000
  51 #define NDEBUG_EXTENDED         0x80000
  52 #define NDEBUG_C400_PREAD       0x100000
  53 #define NDEBUG_C400_PWRITE      0x200000
  54 #define NDEBUG_LISTS            0x400000
  55 #define NDEBUG_ABORT            0x800000
  56 #define NDEBUG_TAGS             0x1000000
  57 #define NDEBUG_MERGING          0x2000000
  58
  59 #define NDEBUG_ANY              0xFFFFFFFFUL
  60
  61 /*
  62  * The contents of the OUTPUT DATA register are asserted on the bus when
  63  * either arbitration is occurring or the phase-indicating signals (
  64  * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
  65  * bit in the INITIATOR COMMAND register is set.
  66  */
  67
  68 #define OUTPUT_DATA_REG         0       /* wo DATA lines on SCSI bus */
  69 #define CURRENT_SCSI_DATA_REG   0       /* ro same */
  70
  71 #define INITIATOR_COMMAND_REG   1       /* rw */
  72 #define ICR_ASSERT_RST          0x80    /* rw Set to assert RST  */
  73 #define ICR_ARBITRATION_PROGRESS 0x40   /* ro Indicates arbitration complete */
  74 #define ICR_TRI_STATE           0x40    /* wo Set to tri-state drivers */
  75 #define ICR_ARBITRATION_LOST    0x20    /* ro Indicates arbitration lost */
  76 #define ICR_DIFF_ENABLE         0x20    /* wo Set to enable diff. drivers */
  77 #define ICR_ASSERT_ACK          0x10    /* rw ini Set to assert ACK */
  78 #define ICR_ASSERT_BSY          0x08    /* rw Set to assert BSY */
  79 #define ICR_ASSERT_SEL          0x04    /* rw Set to assert SEL */
  80 #define ICR_ASSERT_ATN          0x02    /* rw Set to assert ATN */
  81 #define ICR_ASSERT_DATA         0x01    /* rw SCSI_DATA_REG is asserted */
  82
  83 #ifdef DIFFERENTIAL
  84 #define ICR_BASE                ICR_DIFF_ENABLE
  85 #else
  86 #define ICR_BASE                0
  87 #endif
  88
  89 #define MODE_REG                2
  90 /*
  91  * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
  92  * transfer, causing the chip to hog the bus.  You probably don't want
  93  * this.
  94  */
  95 #define MR_BLOCK_DMA_MODE       0x80    /* rw block mode DMA */
  96 #define MR_TARGET               0x40    /* rw target mode */
  97 #define MR_ENABLE_PAR_CHECK     0x20    /* rw enable parity checking */
  98 #define MR_ENABLE_PAR_INTR      0x10    /* rw enable bad parity interrupt */
  99 #define MR_ENABLE_EOP_INTR      0x08    /* rw enable eop interrupt */
 100 #define MR_MONITOR_BSY          0x04    /* rw enable int on unexpected bsy fail */
 101 #define MR_DMA_MODE             0x02    /* rw DMA / pseudo DMA mode */
 102 #define MR_ARBITRATE            0x01    /* rw start arbitration */
 103
 104 #ifdef PARITY
 105 #define MR_BASE                 MR_ENABLE_PAR_CHECK
 106 #else
 107 #define MR_BASE                 0
 108 #endif
 109
 110 #define TARGET_COMMAND_REG      3
 111 #define TCR_LAST_BYTE_SENT      0x80    /* ro DMA done */
 112 #define TCR_ASSERT_REQ          0x08    /* tgt rw assert REQ */
 113 #define TCR_ASSERT_MSG          0x04    /* tgt rw assert MSG */
 114 #define TCR_ASSERT_CD           0x02    /* tgt rw assert CD */
 115 #define TCR_ASSERT_IO           0x01    /* tgt rw assert IO */
 116
 117 #define STATUS_REG              4       /* ro */
 118 /*
 119  * Note : a set bit indicates an active signal, driven by us or another
 120  * device.
 121  */
 122 #define SR_RST                  0x80
 123 #define SR_BSY                  0x40
 124 #define SR_REQ                  0x20
 125 #define SR_MSG                  0x10
 126 #define SR_CD                   0x08
 127 #define SR_IO                   0x04
 128 #define SR_SEL                  0x02
 129 #define SR_DBP                  0x01
 130
 131 /*
 132  * Setting a bit in this register will cause an interrupt to be generated when
 133  * BSY is false and SEL true and this bit is asserted  on the bus.
 134  */
 135 #define SELECT_ENABLE_REG       4       /* wo */
 136
 137 #define BUS_AND_STATUS_REG      5       /* ro */
 138 #define BASR_END_DMA_TRANSFER   0x80    /* ro set on end of transfer */
 139 #define BASR_DRQ                0x40    /* ro mirror of DRQ pin */
 140 #define BASR_PARITY_ERROR       0x20    /* ro parity error detected */
 141 #define BASR_IRQ                0x10    /* ro mirror of IRQ pin */
 142 #define BASR_PHASE_MATCH        0x08    /* ro Set when MSG CD IO match TCR */
 143 #define BASR_BUSY_ERROR         0x04    /* ro Unexpected change to inactive state */
 144 #define BASR_ATN                0x02    /* ro BUS status */
 145 #define BASR_ACK                0x01    /* ro BUS status */
 146
 147 /* Write any value to this register to start a DMA send */
 148 #define START_DMA_SEND_REG      5       /* wo */
 149
 150 /*
 151  * Used in DMA transfer mode, data is latched from the SCSI bus on
 152  * the falling edge of REQ (ini) or ACK (tgt)
 153  */
 154 #define INPUT_DATA_REG                  6       /* ro */
 155
 156 /* Write any value to this register to start a DMA receive */
 157 #define START_DMA_TARGET_RECEIVE_REG    6       /* wo */
 158
 159 /* Read this register to clear interrupt conditions */
 160 #define RESET_PARITY_INTERRUPT_REG      7       /* ro */
 161
 162 /* Write any value to this register to start an ini mode DMA receive */
 163 #define START_DMA_INITIATOR_RECEIVE_REG 7       /* wo */
 164
 165 #define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8     /* rw */
 166
 167 #define CSR_RESET              0x80     /* wo  Resets 53c400 */
 168 #define CSR_53C80_REG          0x80     /* ro  5380 registers busy */
 169 #define CSR_TRANS_DIR          0x40     /* rw  Data transfer direction */
 170 #define CSR_SCSI_BUFF_INTR     0x20     /* rw  Enable int on transfer ready */
 171 #define CSR_53C80_INTR         0x10     /* rw  Enable 53c80 interrupts */
 172 #define CSR_SHARED_INTR        0x08     /* rw  Interrupt sharing */
 173 #define CSR_HOST_BUF_NOT_RDY   0x04     /* ro  Is Host buffer ready */
 174 #define CSR_SCSI_BUF_RDY       0x02     /* ro  SCSI buffer read */
 175 #define CSR_GATED_53C80_IRQ    0x01     /* ro  Last block xferred */
 176
 177 #if 0
 178 #define CSR_BASE CSR_SCSI_BUFF_INTR | CSR_53C80_INTR
 179 #else
 180 #define CSR_BASE CSR_53C80_INTR
 181 #endif
 182
 183 /* Number of 128-byte blocks to be transferred */
 184 #define C400_BLOCK_COUNTER_REG   NCR53C400_register_offset-7    /* rw */
 185
 186 /* Resume transfer after disconnect */
 187 #define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6    /* wo */
 188
 189 /* Access to host buffer stack */
 190 #define C400_HOST_BUFFER         NCR53C400_register_offset-4    /* rw */
 191
 192
 193 /* Note : PHASE_* macros are based on the values of the STATUS register */
 194 #define PHASE_MASK      (SR_MSG | SR_CD | SR_IO)
 195
 196 #define PHASE_DATAOUT           0
 197 #define PHASE_DATAIN            SR_IO
 198 #define PHASE_CMDOUT            SR_CD
 199 #define PHASE_STATIN            (SR_CD | SR_IO)
 200 #define PHASE_MSGOUT            (SR_MSG | SR_CD)
 201 #define PHASE_MSGIN             (SR_MSG | SR_CD | SR_IO)
 202 #define PHASE_UNKNOWN           0xff
 203
 204 /*
 205  * Convert status register phase to something we can use to set phase in
 206  * the target register so we can get phase mismatch interrupts on DMA
 207  * transfers.
 208  */
 209
 210 #define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
 211
 212 /*
 213  * "Special" value for the (unsigned char) command tag, to indicate
 214  * I_T_L nexus instead of I_T_L_Q.
 215  */
 216
 217 #define TAG_NONE        0xff
 218
 219 /*
 220  * These are "special" values for the irq and dma_channel fields of the
 221  * Scsi_Host structure
 222  */
 223
 224 #define DMA_NONE        255
 225 #define IRQ_AUTO        254
 226 #define DMA_AUTO        254
 227 #define PORT_AUTO       0xffff  /* autoprobe io port for 53c400a */
 228
 229 #ifndef NO_IRQ
 230 #define NO_IRQ          0
 231 #endif
 232
 233 #define FLAG_NO_DMA_FIXUP               1       /* No DMA errata workarounds */
 234 #define FLAG_NO_PSEUDO_DMA              8       /* Inhibit DMA */
 235 #define FLAG_LATE_DMA_SETUP             32      /* Setup NCR before DMA H/W */
 236 #define FLAG_TAGGED_QUEUING             64      /* as X3T9.2 spelled it */
 237 #define FLAG_TOSHIBA_DELAY              128     /* Allow for borken CD-ROMs */
 238
 239 #ifdef SUPPORT_TAGS
 240 struct tag_alloc {
 241         DECLARE_BITMAP(allocated, MAX_TAGS);
 242         int nr_allocated;
 243         int queue_size;
 244 };
 245 #endif
 246
 247 struct NCR5380_hostdata {
 248         NCR5380_implementation_fields;          /* implementation specific */
 249         struct Scsi_Host *host;                 /* Host backpointer */
 250         unsigned char id_mask, id_higher_mask;  /* 1 << id, all bits greater */
 251         volatile unsigned char busy[8];         /* index = target, bit = lun */
 252 #if defined(REAL_DMA) || defined(REAL_DMA_POLL)
 253         volatile int dma_len;                   /* requested length of DMA */
 254 #endif
 255         volatile unsigned char last_message;    /* last message OUT */
 256         volatile struct scsi_cmnd *connected;   /* currently connected command */
 257         volatile struct scsi_cmnd *issue_queue; /* waiting to be issued */
 258         volatile struct scsi_cmnd *disconnected_queue;  /* waiting for reconnect */
 259         spinlock_t lock;                        /* protects this struct */
 260         int flags;
 261         struct scsi_eh_save ses;
 262         char info[256];
 263         int read_overruns;                /* number of bytes to cut from a
 264                                            * transfer to handle chip overruns */
 265         int retain_dma_intr;
 266         struct work_struct main_task;
 267 #ifdef SUPPORT_TAGS
 268         struct tag_alloc TagAlloc[8][8];        /* 8 targets and 8 LUNs */
 269 #endif
 270 #ifdef PSEUDO_DMA
 271         unsigned spin_max_r;
 272         unsigned spin_max_w;
 273 #endif
 274         struct workqueue_struct *work_q;
 275         unsigned long accesses_per_ms;  /* chip register accesses per ms */
 276 };
 277
 278 #ifdef __KERNEL__
 279
 280 #ifndef NDEBUG
 281 #define NDEBUG (0)
 282 #endif
 283
 284 #define dprintk(flg, fmt, ...) \
 285         do { if ((NDEBUG) & (flg)) \
 286                 printk(KERN_DEBUG fmt, ## __VA_ARGS__); } while (0)
 287
 288 #define dsprintk(flg, host, fmt, ...) \
 289         do { if ((NDEBUG) & (flg)) \
 290                 shost_printk(KERN_DEBUG, host, fmt, ## __VA_ARGS__); \
 291         } while (0)
 292
 293 #if NDEBUG
 294 #define NCR5380_dprint(flg, arg) \
 295         do { if ((NDEBUG) & (flg)) NCR5380_print(arg); } while (0)
 296 #define NCR5380_dprint_phase(flg, arg) \
 297         do { if ((NDEBUG) & (flg)) NCR5380_print_phase(arg); } while (0)
 298 static void NCR5380_print_phase(struct Scsi_Host *instance);
 299 static void NCR5380_print(struct Scsi_Host *instance);
 300 #else
 301 #define NCR5380_dprint(flg, arg)       do {} while (0)
 302 #define NCR5380_dprint_phase(flg, arg) do {} while (0)
 303 #endif
 304
 305 #if defined(AUTOPROBE_IRQ)
 306 static int NCR5380_probe_irq(struct Scsi_Host *instance, int possible);
 307 #endif
 308 static int NCR5380_init(struct Scsi_Host *instance, int flags);
 309 static int NCR5380_maybe_reset_bus(struct Scsi_Host *);
 310 static void NCR5380_exit(struct Scsi_Host *instance);
 311 static void NCR5380_information_transfer(struct Scsi_Host *instance);
 312 #ifndef DONT_USE_INTR
 313 static irqreturn_t NCR5380_intr(int irq, void *dev_id);
 314 #endif
 315 static void NCR5380_main(struct work_struct *work);
 316 static const char *NCR5380_info(struct Scsi_Host *instance);
 317 static void NCR5380_reselect(struct Scsi_Host *instance);
 318 static int NCR5380_select(struct Scsi_Host *instance, struct scsi_cmnd *cmd);
 319 #if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
 320 static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
 321 #endif
 322 static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
 323
 324 #if (defined(REAL_DMA) || defined(REAL_DMA_POLL))
 325
 326 #if defined(i386) || defined(__alpha__)
 327
 328 /**
 329  *      NCR5380_pc_dma_setup            -       setup ISA DMA
 330  *      @instance: adapter to set up
 331  *      @ptr: block to transfer (virtual address)
 332  *      @count: number of bytes to transfer
 333  *      @mode: DMA controller mode to use
 334  *
 335  *      Program the DMA controller ready to perform an ISA DMA transfer
 336  *      on this chip.
 337  *
 338  *      Locks: takes and releases the ISA DMA lock.
 339  */
 340
 341 static __inline__ int NCR5380_pc_dma_setup(struct Scsi_Host *instance, unsigned char *ptr, unsigned int count, unsigned char mode)
 342 {
 343         unsigned limit;
 344         unsigned long bus_addr = virt_to_bus(ptr);
 345         unsigned long flags;
 346
 347         if (instance->dma_channel <= 3) {
 348                 if (count > 65536)
 349                         count = 65536;
 350                 limit = 65536 - (bus_addr & 0xFFFF);
 351         } else {
 352                 if (count > 65536 * 2)
 353                         count = 65536 * 2;
 354                 limit = 65536 * 2 - (bus_addr & 0x1FFFF);
 355         }
 356
 357         if (count > limit)
 358                 count = limit;
 359
 360         if ((count & 1) || (bus_addr & 1))
 361                 panic("scsi%d : attempted unaligned DMA transfer\n", instance->host_no);
 362
 363         flags=claim_dma_lock();
 364         disable_dma(instance->dma_channel);
 365         clear_dma_ff(instance->dma_channel);
 366         set_dma_addr(instance->dma_channel, bus_addr);
 367         set_dma_count(instance->dma_channel, count);
 368         set_dma_mode(instance->dma_channel, mode);
 369         enable_dma(instance->dma_channel);
 370         release_dma_lock(flags);
 371
 372         return count;
 373 }
 374
 375 /**
 376  *      NCR5380_pc_dma_write_setup              -       setup ISA DMA write
 377  *      @instance: adapter to set up
 378  *      @ptr: block to transfer (virtual address)
 379  *      @count: number of bytes to transfer
 380  *
 381  *      Program the DMA controller ready to perform an ISA DMA write to the
 382  *      SCSI controller.
 383  *
 384  *      Locks: called routines take and release the ISA DMA lock.
 385  */
 386
 387 static __inline__ int NCR5380_pc_dma_write_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
 388 {
 389         return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_WRITE);
 390 }
 391
 392 /**
 393  *      NCR5380_pc_dma_read_setup               -       setup ISA DMA read
 394  *      @instance: adapter to set up
 395  *      @ptr: block to transfer (virtual address)
 396  *      @count: number of bytes to transfer
 397  *
 398  *      Program the DMA controller ready to perform an ISA DMA read from the
 399  *      SCSI controller.
 400  *
 401  *      Locks: called routines take and release the ISA DMA lock.
 402  */
 403
 404 static __inline__ int NCR5380_pc_dma_read_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
 405 {
 406         return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_READ);
 407 }
 408
 409 /**
 410  *      NCR5380_pc_dma_residual         -       return bytes left
 411  *      @instance: adapter
 412  *
 413  *      Reports the number of bytes left over after the DMA was terminated.
 414  *
 415  *      Locks: takes and releases the ISA DMA lock.
 416  */
 417
 418 static __inline__ int NCR5380_pc_dma_residual(struct Scsi_Host *instance)
 419 {
 420         unsigned long flags;
 421         int tmp;
 422
 423         flags = claim_dma_lock();
 424         clear_dma_ff(instance->dma_channel);
 425         tmp = get_dma_residue(instance->dma_channel);
 426         release_dma_lock(flags);
 427
 428         return tmp;
 429 }
 430 #endif                          /* defined(i386) || defined(__alpha__) */
 431 #endif                          /* defined(REAL_DMA)  */
 432 #endif                          /* __KERNEL__ */
 433 #endif                          /* NCR5380_H */