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[deliverable/linux.git] / drivers / scsi / advansys.c
1 #define DRV_NAME "advansys"
2 #define ASC_VERSION "3.4" /* AdvanSys Driver Version */
3
4 /*
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
6 *
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
10 * All Rights Reserved.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18 /*
19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
22 */
23
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/ioport.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/slab.h>
32 #include <linux/mm.h>
33 #include <linux/proc_fs.h>
34 #include <linux/init.h>
35 #include <linux/blkdev.h>
36 #include <linux/isa.h>
37 #include <linux/eisa.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/firmware.h>
42
43 #include <asm/io.h>
44 #include <asm/dma.h>
45
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <scsi/scsi_tcq.h>
49 #include <scsi/scsi.h>
50 #include <scsi/scsi_host.h>
51
52 /* FIXME:
53 *
54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
61 * safely?
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
69 * 8. Add module_param to override ISA/VLB ioport array
70 */
71 #warning this driver is still not properly converted to the DMA API
72
73 /* Enable driver /proc statistics. */
74 #define ADVANSYS_STATS
75
76 /* Enable driver tracing. */
77 #undef ADVANSYS_DEBUG
78
79 typedef unsigned char uchar;
80
81 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
82
83 #define PCI_VENDOR_ID_ASP 0x10cd
84 #define PCI_DEVICE_ID_ASP_1200A 0x1100
85 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
86 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
87 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
88 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
89 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
90
91 #define PortAddr unsigned int /* port address size */
92 #define inp(port) inb(port)
93 #define outp(port, byte) outb((byte), (port))
94
95 #define inpw(port) inw(port)
96 #define outpw(port, word) outw((word), (port))
97
98 #define ASC_MAX_SG_QUEUE 7
99 #define ASC_MAX_SG_LIST 255
100
101 #define ASC_CS_TYPE unsigned short
102
103 #define ASC_IS_ISA (0x0001)
104 #define ASC_IS_ISAPNP (0x0081)
105 #define ASC_IS_EISA (0x0002)
106 #define ASC_IS_PCI (0x0004)
107 #define ASC_IS_PCI_ULTRA (0x0104)
108 #define ASC_IS_PCMCIA (0x0008)
109 #define ASC_IS_MCA (0x0020)
110 #define ASC_IS_VL (0x0040)
111 #define ASC_IS_WIDESCSI_16 (0x0100)
112 #define ASC_IS_WIDESCSI_32 (0x0200)
113 #define ASC_IS_BIG_ENDIAN (0x8000)
114
115 #define ASC_CHIP_MIN_VER_VL (0x01)
116 #define ASC_CHIP_MAX_VER_VL (0x07)
117 #define ASC_CHIP_MIN_VER_PCI (0x09)
118 #define ASC_CHIP_MAX_VER_PCI (0x0F)
119 #define ASC_CHIP_VER_PCI_BIT (0x08)
120 #define ASC_CHIP_MIN_VER_ISA (0x11)
121 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
122 #define ASC_CHIP_MAX_VER_ISA (0x27)
123 #define ASC_CHIP_VER_ISA_BIT (0x30)
124 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
125 #define ASC_CHIP_VER_ASYN_BUG (0x21)
126 #define ASC_CHIP_VER_PCI 0x08
127 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
128 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
129 #define ASC_CHIP_MIN_VER_EISA (0x41)
130 #define ASC_CHIP_MAX_VER_EISA (0x47)
131 #define ASC_CHIP_VER_EISA_BIT (0x40)
132 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
133 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
134 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
135 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
136
137 #define ASC_SCSI_ID_BITS 3
138 #define ASC_SCSI_TIX_TYPE uchar
139 #define ASC_ALL_DEVICE_BIT_SET 0xFF
140 #define ASC_SCSI_BIT_ID_TYPE uchar
141 #define ASC_MAX_TID 7
142 #define ASC_MAX_LUN 7
143 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
144 #define ASC_MAX_SENSE_LEN 32
145 #define ASC_MIN_SENSE_LEN 14
146 #define ASC_SCSI_RESET_HOLD_TIME_US 60
147
148 /*
149 * Narrow boards only support 12-byte commands, while wide boards
150 * extend to 16-byte commands.
151 */
152 #define ASC_MAX_CDB_LEN 12
153 #define ADV_MAX_CDB_LEN 16
154
155 #define MS_SDTR_LEN 0x03
156 #define MS_WDTR_LEN 0x02
157
158 #define ASC_SG_LIST_PER_Q 7
159 #define QS_FREE 0x00
160 #define QS_READY 0x01
161 #define QS_DISC1 0x02
162 #define QS_DISC2 0x04
163 #define QS_BUSY 0x08
164 #define QS_ABORTED 0x40
165 #define QS_DONE 0x80
166 #define QC_NO_CALLBACK 0x01
167 #define QC_SG_SWAP_QUEUE 0x02
168 #define QC_SG_HEAD 0x04
169 #define QC_DATA_IN 0x08
170 #define QC_DATA_OUT 0x10
171 #define QC_URGENT 0x20
172 #define QC_MSG_OUT 0x40
173 #define QC_REQ_SENSE 0x80
174 #define QCSG_SG_XFER_LIST 0x02
175 #define QCSG_SG_XFER_MORE 0x04
176 #define QCSG_SG_XFER_END 0x08
177 #define QD_IN_PROGRESS 0x00
178 #define QD_NO_ERROR 0x01
179 #define QD_ABORTED_BY_HOST 0x02
180 #define QD_WITH_ERROR 0x04
181 #define QD_INVALID_REQUEST 0x80
182 #define QD_INVALID_HOST_NUM 0x81
183 #define QD_INVALID_DEVICE 0x82
184 #define QD_ERR_INTERNAL 0xFF
185 #define QHSTA_NO_ERROR 0x00
186 #define QHSTA_M_SEL_TIMEOUT 0x11
187 #define QHSTA_M_DATA_OVER_RUN 0x12
188 #define QHSTA_M_DATA_UNDER_RUN 0x12
189 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
190 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
191 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
192 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
193 #define QHSTA_D_HOST_ABORT_FAILED 0x23
194 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
195 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
196 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
197 #define QHSTA_M_WTM_TIMEOUT 0x41
198 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
199 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
200 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
201 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
202 #define QHSTA_M_BAD_TAG_CODE 0x46
203 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
204 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
205 #define QHSTA_D_LRAM_CMP_ERROR 0x81
206 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
207 #define ASC_FLAG_SCSIQ_REQ 0x01
208 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
209 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
210 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
211 #define ASC_FLAG_WIN16 0x10
212 #define ASC_FLAG_WIN32 0x20
213 #define ASC_FLAG_ISA_OVER_16MB 0x40
214 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
215 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
216 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
217 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
218 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
219 #define ASC_SCSIQ_CPY_BEG 4
220 #define ASC_SCSIQ_SGHD_CPY_BEG 2
221 #define ASC_SCSIQ_B_FWD 0
222 #define ASC_SCSIQ_B_BWD 1
223 #define ASC_SCSIQ_B_STATUS 2
224 #define ASC_SCSIQ_B_QNO 3
225 #define ASC_SCSIQ_B_CNTL 4
226 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
227 #define ASC_SCSIQ_D_DATA_ADDR 8
228 #define ASC_SCSIQ_D_DATA_CNT 12
229 #define ASC_SCSIQ_B_SENSE_LEN 20
230 #define ASC_SCSIQ_DONE_INFO_BEG 22
231 #define ASC_SCSIQ_D_SRBPTR 22
232 #define ASC_SCSIQ_B_TARGET_IX 26
233 #define ASC_SCSIQ_B_CDB_LEN 28
234 #define ASC_SCSIQ_B_TAG_CODE 29
235 #define ASC_SCSIQ_W_VM_ID 30
236 #define ASC_SCSIQ_DONE_STATUS 32
237 #define ASC_SCSIQ_HOST_STATUS 33
238 #define ASC_SCSIQ_SCSI_STATUS 34
239 #define ASC_SCSIQ_CDB_BEG 36
240 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
241 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
242 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
243 #define ASC_SCSIQ_B_SG_WK_QP 49
244 #define ASC_SCSIQ_B_SG_WK_IX 50
245 #define ASC_SCSIQ_W_ALT_DC1 52
246 #define ASC_SCSIQ_B_LIST_CNT 6
247 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
248 #define ASC_SGQ_B_SG_CNTL 4
249 #define ASC_SGQ_B_SG_HEAD_QP 5
250 #define ASC_SGQ_B_SG_LIST_CNT 6
251 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
252 #define ASC_SGQ_LIST_BEG 8
253 #define ASC_DEF_SCSI1_QNG 4
254 #define ASC_MAX_SCSI1_QNG 4
255 #define ASC_DEF_SCSI2_QNG 16
256 #define ASC_MAX_SCSI2_QNG 32
257 #define ASC_TAG_CODE_MASK 0x23
258 #define ASC_STOP_REQ_RISC_STOP 0x01
259 #define ASC_STOP_ACK_RISC_STOP 0x03
260 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
261 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
262 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
263 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
264 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
265 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
266 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
267 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
268 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
269 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
270
271 typedef struct asc_scsiq_1 {
272 uchar status;
273 uchar q_no;
274 uchar cntl;
275 uchar sg_queue_cnt;
276 uchar target_id;
277 uchar target_lun;
278 __le32 data_addr;
279 __le32 data_cnt;
280 __le32 sense_addr;
281 uchar sense_len;
282 uchar extra_bytes;
283 } ASC_SCSIQ_1;
284
285 typedef struct asc_scsiq_2 {
286 u32 srb_tag;
287 uchar target_ix;
288 uchar flag;
289 uchar cdb_len;
290 uchar tag_code;
291 ushort vm_id;
292 } ASC_SCSIQ_2;
293
294 typedef struct asc_scsiq_3 {
295 uchar done_stat;
296 uchar host_stat;
297 uchar scsi_stat;
298 uchar scsi_msg;
299 } ASC_SCSIQ_3;
300
301 typedef struct asc_scsiq_4 {
302 uchar cdb[ASC_MAX_CDB_LEN];
303 uchar y_first_sg_list_qp;
304 uchar y_working_sg_qp;
305 uchar y_working_sg_ix;
306 uchar y_res;
307 ushort x_req_count;
308 ushort x_reconnect_rtn;
309 __le32 x_saved_data_addr;
310 __le32 x_saved_data_cnt;
311 } ASC_SCSIQ_4;
312
313 typedef struct asc_q_done_info {
314 ASC_SCSIQ_2 d2;
315 ASC_SCSIQ_3 d3;
316 uchar q_status;
317 uchar q_no;
318 uchar cntl;
319 uchar sense_len;
320 uchar extra_bytes;
321 uchar res;
322 u32 remain_bytes;
323 } ASC_QDONE_INFO;
324
325 typedef struct asc_sg_list {
326 __le32 addr;
327 __le32 bytes;
328 } ASC_SG_LIST;
329
330 typedef struct asc_sg_head {
331 ushort entry_cnt;
332 ushort queue_cnt;
333 ushort entry_to_copy;
334 ushort res;
335 ASC_SG_LIST sg_list[0];
336 } ASC_SG_HEAD;
337
338 typedef struct asc_scsi_q {
339 ASC_SCSIQ_1 q1;
340 ASC_SCSIQ_2 q2;
341 uchar *cdbptr;
342 ASC_SG_HEAD *sg_head;
343 ushort remain_sg_entry_cnt;
344 ushort next_sg_index;
345 } ASC_SCSI_Q;
346
347 typedef struct asc_scsi_bios_req_q {
348 ASC_SCSIQ_1 r1;
349 ASC_SCSIQ_2 r2;
350 uchar *cdbptr;
351 ASC_SG_HEAD *sg_head;
352 uchar *sense_ptr;
353 ASC_SCSIQ_3 r3;
354 uchar cdb[ASC_MAX_CDB_LEN];
355 uchar sense[ASC_MIN_SENSE_LEN];
356 } ASC_SCSI_BIOS_REQ_Q;
357
358 typedef struct asc_risc_q {
359 uchar fwd;
360 uchar bwd;
361 ASC_SCSIQ_1 i1;
362 ASC_SCSIQ_2 i2;
363 ASC_SCSIQ_3 i3;
364 ASC_SCSIQ_4 i4;
365 } ASC_RISC_Q;
366
367 typedef struct asc_sg_list_q {
368 uchar seq_no;
369 uchar q_no;
370 uchar cntl;
371 uchar sg_head_qp;
372 uchar sg_list_cnt;
373 uchar sg_cur_list_cnt;
374 } ASC_SG_LIST_Q;
375
376 typedef struct asc_risc_sg_list_q {
377 uchar fwd;
378 uchar bwd;
379 ASC_SG_LIST_Q sg;
380 ASC_SG_LIST sg_list[7];
381 } ASC_RISC_SG_LIST_Q;
382
383 #define ASCQ_ERR_Q_STATUS 0x0D
384 #define ASCQ_ERR_CUR_QNG 0x17
385 #define ASCQ_ERR_SG_Q_LINKS 0x18
386 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
387 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
388 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
389
390 /*
391 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
392 */
393 #define ASC_WARN_NO_ERROR 0x0000
394 #define ASC_WARN_IO_PORT_ROTATE 0x0001
395 #define ASC_WARN_EEPROM_CHKSUM 0x0002
396 #define ASC_WARN_IRQ_MODIFIED 0x0004
397 #define ASC_WARN_AUTO_CONFIG 0x0008
398 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
399 #define ASC_WARN_EEPROM_RECOVER 0x0020
400 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
401
402 /*
403 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
404 */
405 #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
406 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
407 #define ASC_IERR_SET_PC_ADDR 0x0004
408 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
409 #define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
410 #define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
411 #define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
412 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
413 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
414 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
415 #define ASC_IERR_NO_BUS_TYPE 0x0400
416 #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
417 #define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
418 #define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
419
420 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
421 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
422 #define ASC_MIN_FREE_Q (0x02)
423 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
424 #define ASC_MAX_TOTAL_QNG 240
425 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
426 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
427 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
428 #define ASC_MAX_INRAM_TAG_QNG 16
429 #define ASC_IOADR_GAP 0x10
430 #define ASC_SYN_MAX_OFFSET 0x0F
431 #define ASC_DEF_SDTR_OFFSET 0x0F
432 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
433 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
434
435 /* The narrow chip only supports a limited selection of transfer rates.
436 * These are encoded in the range 0..7 or 0..15 depending whether the chip
437 * is Ultra-capable or not. These tables let us convert from one to the other.
438 */
439 static const unsigned char asc_syn_xfer_period[8] = {
440 25, 30, 35, 40, 50, 60, 70, 85
441 };
442
443 static const unsigned char asc_syn_ultra_xfer_period[16] = {
444 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
445 };
446
447 typedef struct ext_msg {
448 uchar msg_type;
449 uchar msg_len;
450 uchar msg_req;
451 union {
452 struct {
453 uchar sdtr_xfer_period;
454 uchar sdtr_req_ack_offset;
455 } sdtr;
456 struct {
457 uchar wdtr_width;
458 } wdtr;
459 struct {
460 uchar mdp_b3;
461 uchar mdp_b2;
462 uchar mdp_b1;
463 uchar mdp_b0;
464 } mdp;
465 } u_ext_msg;
466 uchar res;
467 } EXT_MSG;
468
469 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
470 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
471 #define wdtr_width u_ext_msg.wdtr.wdtr_width
472 #define mdp_b3 u_ext_msg.mdp_b3
473 #define mdp_b2 u_ext_msg.mdp_b2
474 #define mdp_b1 u_ext_msg.mdp_b1
475 #define mdp_b0 u_ext_msg.mdp_b0
476
477 typedef struct asc_dvc_cfg {
478 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
479 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
480 ASC_SCSI_BIT_ID_TYPE disc_enable;
481 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
482 uchar chip_scsi_id;
483 uchar isa_dma_speed;
484 uchar isa_dma_channel;
485 uchar chip_version;
486 ushort mcode_date;
487 ushort mcode_version;
488 uchar max_tag_qng[ASC_MAX_TID + 1];
489 uchar sdtr_period_offset[ASC_MAX_TID + 1];
490 uchar adapter_info[6];
491 } ASC_DVC_CFG;
492
493 #define ASC_DEF_DVC_CNTL 0xFFFF
494 #define ASC_DEF_CHIP_SCSI_ID 7
495 #define ASC_DEF_ISA_DMA_SPEED 4
496 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
497 #define ASC_INIT_STATE_END_GET_CFG 0x0002
498 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
499 #define ASC_INIT_STATE_END_SET_CFG 0x0008
500 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
501 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
502 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
503 #define ASC_INIT_STATE_END_INQUIRY 0x0080
504 #define ASC_INIT_RESET_SCSI_DONE 0x0100
505 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
506 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
507 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
508 #define ASC_MIN_TAGGED_CMD 7
509 #define ASC_MAX_SCSI_RESET_WAIT 30
510 #define ASC_OVERRUN_BSIZE 64
511
512 struct asc_dvc_var; /* Forward Declaration. */
513
514 typedef struct asc_dvc_var {
515 PortAddr iop_base;
516 ushort err_code;
517 ushort dvc_cntl;
518 ushort bug_fix_cntl;
519 ushort bus_type;
520 ASC_SCSI_BIT_ID_TYPE init_sdtr;
521 ASC_SCSI_BIT_ID_TYPE sdtr_done;
522 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
523 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
524 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
525 ASC_SCSI_BIT_ID_TYPE start_motor;
526 uchar *overrun_buf;
527 dma_addr_t overrun_dma;
528 uchar scsi_reset_wait;
529 uchar chip_no;
530 bool is_in_int;
531 uchar max_total_qng;
532 uchar cur_total_qng;
533 uchar in_critical_cnt;
534 uchar last_q_shortage;
535 ushort init_state;
536 uchar cur_dvc_qng[ASC_MAX_TID + 1];
537 uchar max_dvc_qng[ASC_MAX_TID + 1];
538 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
539 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
540 const uchar *sdtr_period_tbl;
541 ASC_DVC_CFG *cfg;
542 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
543 char redo_scam;
544 ushort res2;
545 uchar dos_int13_table[ASC_MAX_TID + 1];
546 unsigned int max_dma_count;
547 ASC_SCSI_BIT_ID_TYPE no_scam;
548 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
549 uchar min_sdtr_index;
550 uchar max_sdtr_index;
551 struct asc_board *drv_ptr;
552 unsigned int uc_break;
553 } ASC_DVC_VAR;
554
555 typedef struct asc_dvc_inq_info {
556 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
557 } ASC_DVC_INQ_INFO;
558
559 typedef struct asc_cap_info {
560 u32 lba;
561 u32 blk_size;
562 } ASC_CAP_INFO;
563
564 typedef struct asc_cap_info_array {
565 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
566 } ASC_CAP_INFO_ARRAY;
567
568 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
569 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
570 #define ASC_CNTL_INITIATOR (ushort)0x0001
571 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
572 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
573 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
574 #define ASC_CNTL_NO_SCAM (ushort)0x0010
575 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
576 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
577 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
578 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
579 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
580 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
581 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
582 #define ASC_CNTL_BURST_MODE (ushort)0x2000
583 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
584 #define ASC_EEP_DVC_CFG_BEG_VL 2
585 #define ASC_EEP_MAX_DVC_ADDR_VL 15
586 #define ASC_EEP_DVC_CFG_BEG 32
587 #define ASC_EEP_MAX_DVC_ADDR 45
588 #define ASC_EEP_MAX_RETRY 20
589
590 /*
591 * These macros keep the chip SCSI id and ISA DMA speed
592 * bitfields in board order. C bitfields aren't portable
593 * between big and little-endian platforms so they are
594 * not used.
595 */
596
597 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
598 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
599 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
600 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
601 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
602 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
603
604 typedef struct asceep_config {
605 ushort cfg_lsw;
606 ushort cfg_msw;
607 uchar init_sdtr;
608 uchar disc_enable;
609 uchar use_cmd_qng;
610 uchar start_motor;
611 uchar max_total_qng;
612 uchar max_tag_qng;
613 uchar bios_scan;
614 uchar power_up_wait;
615 uchar no_scam;
616 uchar id_speed; /* low order 4 bits is chip scsi id */
617 /* high order 4 bits is isa dma speed */
618 uchar dos_int13_table[ASC_MAX_TID + 1];
619 uchar adapter_info[6];
620 ushort cntl;
621 ushort chksum;
622 } ASCEEP_CONFIG;
623
624 #define ASC_EEP_CMD_READ 0x80
625 #define ASC_EEP_CMD_WRITE 0x40
626 #define ASC_EEP_CMD_WRITE_ABLE 0x30
627 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
628 #define ASCV_MSGOUT_BEG 0x0000
629 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
630 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
631 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
632 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
633 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
634 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
635 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
636 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
637 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
638 #define ASCV_BREAK_ADDR (ushort)0x0028
639 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
640 #define ASCV_BREAK_CONTROL (ushort)0x002C
641 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
642
643 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
644 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
645 #define ASCV_MCODE_SIZE_W (ushort)0x0034
646 #define ASCV_STOP_CODE_B (ushort)0x0036
647 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
648 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
649 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
650 #define ASCV_HALTCODE_W (ushort)0x0040
651 #define ASCV_CHKSUM_W (ushort)0x0042
652 #define ASCV_MC_DATE_W (ushort)0x0044
653 #define ASCV_MC_VER_W (ushort)0x0046
654 #define ASCV_NEXTRDY_B (ushort)0x0048
655 #define ASCV_DONENEXT_B (ushort)0x0049
656 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
657 #define ASCV_SCSIBUSY_B (ushort)0x004B
658 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
659 #define ASCV_CURCDB_B (ushort)0x004D
660 #define ASCV_RCLUN_B (ushort)0x004E
661 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
662 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
663 #define ASCV_DISC_ENABLE_B (ushort)0x0052
664 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
665 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
666 #define ASCV_MCODE_CNTL_B (ushort)0x0056
667 #define ASCV_NULL_TARGET_B (ushort)0x0057
668 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
669 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
670 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
671 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
672 #define ASCV_HOST_FLAG_B (ushort)0x005D
673 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
674 #define ASCV_VER_SERIAL_B (ushort)0x0065
675 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
676 #define ASCV_WTM_FLAG_B (ushort)0x0068
677 #define ASCV_RISC_FLAG_B (ushort)0x006A
678 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
679 #define ASC_HOST_FLAG_IN_ISR 0x01
680 #define ASC_HOST_FLAG_ACK_INT 0x02
681 #define ASC_RISC_FLAG_GEN_INT 0x01
682 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
683 #define IOP_CTRL (0x0F)
684 #define IOP_STATUS (0x0E)
685 #define IOP_INT_ACK IOP_STATUS
686 #define IOP_REG_IFC (0x0D)
687 #define IOP_SYN_OFFSET (0x0B)
688 #define IOP_EXTRA_CONTROL (0x0D)
689 #define IOP_REG_PC (0x0C)
690 #define IOP_RAM_ADDR (0x0A)
691 #define IOP_RAM_DATA (0x08)
692 #define IOP_EEP_DATA (0x06)
693 #define IOP_EEP_CMD (0x07)
694 #define IOP_VERSION (0x03)
695 #define IOP_CONFIG_HIGH (0x04)
696 #define IOP_CONFIG_LOW (0x02)
697 #define IOP_SIG_BYTE (0x01)
698 #define IOP_SIG_WORD (0x00)
699 #define IOP_REG_DC1 (0x0E)
700 #define IOP_REG_DC0 (0x0C)
701 #define IOP_REG_SB (0x0B)
702 #define IOP_REG_DA1 (0x0A)
703 #define IOP_REG_DA0 (0x08)
704 #define IOP_REG_SC (0x09)
705 #define IOP_DMA_SPEED (0x07)
706 #define IOP_REG_FLAG (0x07)
707 #define IOP_FIFO_H (0x06)
708 #define IOP_FIFO_L (0x04)
709 #define IOP_REG_ID (0x05)
710 #define IOP_REG_QP (0x03)
711 #define IOP_REG_IH (0x02)
712 #define IOP_REG_IX (0x01)
713 #define IOP_REG_AX (0x00)
714 #define IFC_REG_LOCK (0x00)
715 #define IFC_REG_UNLOCK (0x09)
716 #define IFC_WR_EN_FILTER (0x10)
717 #define IFC_RD_NO_EEPROM (0x10)
718 #define IFC_SLEW_RATE (0x20)
719 #define IFC_ACT_NEG (0x40)
720 #define IFC_INP_FILTER (0x80)
721 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
722 #define SC_SEL (uchar)(0x80)
723 #define SC_BSY (uchar)(0x40)
724 #define SC_ACK (uchar)(0x20)
725 #define SC_REQ (uchar)(0x10)
726 #define SC_ATN (uchar)(0x08)
727 #define SC_IO (uchar)(0x04)
728 #define SC_CD (uchar)(0x02)
729 #define SC_MSG (uchar)(0x01)
730 #define SEC_SCSI_CTL (uchar)(0x80)
731 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
732 #define SEC_SLEW_RATE (uchar)(0x20)
733 #define SEC_ENABLE_FILTER (uchar)(0x10)
734 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
735 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
736 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
737 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
738 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
739 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
740 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
741 #define ASC_MAX_QNO 0xF8
742 #define ASC_DATA_SEC_BEG (ushort)0x0080
743 #define ASC_DATA_SEC_END (ushort)0x0080
744 #define ASC_CODE_SEC_BEG (ushort)0x0080
745 #define ASC_CODE_SEC_END (ushort)0x0080
746 #define ASC_QADR_BEG (0x4000)
747 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
748 #define ASC_QADR_END (ushort)0x7FFF
749 #define ASC_QLAST_ADR (ushort)0x7FC0
750 #define ASC_QBLK_SIZE 0x40
751 #define ASC_BIOS_DATA_QBEG 0xF8
752 #define ASC_MIN_ACTIVE_QNO 0x01
753 #define ASC_QLINK_END 0xFF
754 #define ASC_EEPROM_WORDS 0x10
755 #define ASC_MAX_MGS_LEN 0x10
756 #define ASC_BIOS_ADDR_DEF 0xDC00
757 #define ASC_BIOS_SIZE 0x3800
758 #define ASC_BIOS_RAM_OFF 0x3800
759 #define ASC_BIOS_RAM_SIZE 0x800
760 #define ASC_BIOS_MIN_ADDR 0xC000
761 #define ASC_BIOS_MAX_ADDR 0xEC00
762 #define ASC_BIOS_BANK_SIZE 0x0400
763 #define ASC_MCODE_START_ADDR 0x0080
764 #define ASC_CFG0_HOST_INT_ON 0x0020
765 #define ASC_CFG0_BIOS_ON 0x0040
766 #define ASC_CFG0_VERA_BURST_ON 0x0080
767 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
768 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
769 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
770 #define ASC_CFG_MSW_CLR_MASK 0x3080
771 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
772 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
773 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
774 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
775 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
776 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
777 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
778 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
779 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
780 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
781 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
782 #define CSW_HALTED (ASC_CS_TYPE)0x0010
783 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
784 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
785 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
786 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
787 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
788 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
789 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
790 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
791 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
792 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
793 #define CC_CHIP_RESET (uchar)0x80
794 #define CC_SCSI_RESET (uchar)0x40
795 #define CC_HALT (uchar)0x20
796 #define CC_SINGLE_STEP (uchar)0x10
797 #define CC_DMA_ABLE (uchar)0x08
798 #define CC_TEST (uchar)0x04
799 #define CC_BANK_ONE (uchar)0x02
800 #define CC_DIAG (uchar)0x01
801 #define ASC_1000_ID0W 0x04C1
802 #define ASC_1000_ID0W_FIX 0x00C1
803 #define ASC_1000_ID1B 0x25
804 #define ASC_EISA_REV_IOP_MASK (0x0C83)
805 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
806 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
807 #define INS_HALTINT (ushort)0x6281
808 #define INS_HALT (ushort)0x6280
809 #define INS_SINT (ushort)0x6200
810 #define INS_RFLAG_WTM (ushort)0x7380
811 #define ASC_MC_SAVE_CODE_WSIZE 0x500
812 #define ASC_MC_SAVE_DATA_WSIZE 0x40
813
814 typedef struct asc_mc_saved {
815 ushort data[ASC_MC_SAVE_DATA_WSIZE];
816 ushort code[ASC_MC_SAVE_CODE_WSIZE];
817 } ASC_MC_SAVED;
818
819 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
820 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
821 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
822 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
823 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
824 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
825 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
826 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
827 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
828 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
829 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
830 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
831 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
832 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
833 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
834 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
835 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
836 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
837 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
838 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
839 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
840 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
841 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
842 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
843 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
844 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
845 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
846 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
847 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
848 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
849 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
850 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
851 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
852 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
853 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
854 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
855 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
856 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
857 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
858 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
859 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
860 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
861 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
862 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
863 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
864 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
865 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
866 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
867 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
868 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
869 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
870 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
871 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
872 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
873 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
874 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
875 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
876 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
877 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
878 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
879 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
880 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
881 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
882 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
883 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
884 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
885 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
886
887 #define AdvPortAddr void __iomem * /* Virtual memory address size */
888
889 /*
890 * Define Adv Library required memory access macros.
891 */
892 #define ADV_MEM_READB(addr) readb(addr)
893 #define ADV_MEM_READW(addr) readw(addr)
894 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
895 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
896 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
897
898 /*
899 * Define total number of simultaneous maximum element scatter-gather
900 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
901 * maximum number of outstanding commands per wide host adapter. Each
902 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
903 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
904 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
905 * structures or 255 scatter-gather elements.
906 */
907 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
908
909 /*
910 * Define maximum number of scatter-gather elements per request.
911 */
912 #define ADV_MAX_SG_LIST 255
913 #define NO_OF_SG_PER_BLOCK 15
914
915 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
916 #define ADV_EEP_DVC_CFG_END (0x15)
917 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
918 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
919
920 #define ADV_EEP_DELAY_MS 100
921
922 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
923 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
924 /*
925 * For the ASC3550 Bit 13 is Termination Polarity control bit.
926 * For later ICs Bit 13 controls whether the CIS (Card Information
927 * Service Section) is loaded from EEPROM.
928 */
929 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
930 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
931 /*
932 * ASC38C1600 Bit 11
933 *
934 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
935 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
936 * Function 0 will specify INT B.
937 *
938 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
939 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
940 * Function 1 will specify INT A.
941 */
942 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
943
944 typedef struct adveep_3550_config {
945 /* Word Offset, Description */
946
947 ushort cfg_lsw; /* 00 power up initialization */
948 /* bit 13 set - Term Polarity Control */
949 /* bit 14 set - BIOS Enable */
950 /* bit 15 set - Big Endian Mode */
951 ushort cfg_msw; /* 01 unused */
952 ushort disc_enable; /* 02 disconnect enable */
953 ushort wdtr_able; /* 03 Wide DTR able */
954 ushort sdtr_able; /* 04 Synchronous DTR able */
955 ushort start_motor; /* 05 send start up motor */
956 ushort tagqng_able; /* 06 tag queuing able */
957 ushort bios_scan; /* 07 BIOS device control */
958 ushort scam_tolerant; /* 08 no scam */
959
960 uchar adapter_scsi_id; /* 09 Host Adapter ID */
961 uchar bios_boot_delay; /* power up wait */
962
963 uchar scsi_reset_delay; /* 10 reset delay */
964 uchar bios_id_lun; /* first boot device scsi id & lun */
965 /* high nibble is lun */
966 /* low nibble is scsi id */
967
968 uchar termination; /* 11 0 - automatic */
969 /* 1 - low off / high off */
970 /* 2 - low off / high on */
971 /* 3 - low on / high on */
972 /* There is no low on / high off */
973
974 uchar reserved1; /* reserved byte (not used) */
975
976 ushort bios_ctrl; /* 12 BIOS control bits */
977 /* bit 0 BIOS don't act as initiator. */
978 /* bit 1 BIOS > 1 GB support */
979 /* bit 2 BIOS > 2 Disk Support */
980 /* bit 3 BIOS don't support removables */
981 /* bit 4 BIOS support bootable CD */
982 /* bit 5 BIOS scan enabled */
983 /* bit 6 BIOS support multiple LUNs */
984 /* bit 7 BIOS display of message */
985 /* bit 8 SCAM disabled */
986 /* bit 9 Reset SCSI bus during init. */
987 /* bit 10 */
988 /* bit 11 No verbose initialization. */
989 /* bit 12 SCSI parity enabled */
990 /* bit 13 */
991 /* bit 14 */
992 /* bit 15 */
993 ushort ultra_able; /* 13 ULTRA speed able */
994 ushort reserved2; /* 14 reserved */
995 uchar max_host_qng; /* 15 maximum host queuing */
996 uchar max_dvc_qng; /* maximum per device queuing */
997 ushort dvc_cntl; /* 16 control bit for driver */
998 ushort bug_fix; /* 17 control bit for bug fix */
999 ushort serial_number_word1; /* 18 Board serial number word 1 */
1000 ushort serial_number_word2; /* 19 Board serial number word 2 */
1001 ushort serial_number_word3; /* 20 Board serial number word 3 */
1002 ushort check_sum; /* 21 EEP check sum */
1003 uchar oem_name[16]; /* 22 OEM name */
1004 ushort dvc_err_code; /* 30 last device driver error code */
1005 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1006 ushort adv_err_addr; /* 32 last uc error address */
1007 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1008 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1009 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1010 ushort num_of_err; /* 36 number of error */
1011 } ADVEEP_3550_CONFIG;
1012
1013 typedef struct adveep_38C0800_config {
1014 /* Word Offset, Description */
1015
1016 ushort cfg_lsw; /* 00 power up initialization */
1017 /* bit 13 set - Load CIS */
1018 /* bit 14 set - BIOS Enable */
1019 /* bit 15 set - Big Endian Mode */
1020 ushort cfg_msw; /* 01 unused */
1021 ushort disc_enable; /* 02 disconnect enable */
1022 ushort wdtr_able; /* 03 Wide DTR able */
1023 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1024 ushort start_motor; /* 05 send start up motor */
1025 ushort tagqng_able; /* 06 tag queuing able */
1026 ushort bios_scan; /* 07 BIOS device control */
1027 ushort scam_tolerant; /* 08 no scam */
1028
1029 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1030 uchar bios_boot_delay; /* power up wait */
1031
1032 uchar scsi_reset_delay; /* 10 reset delay */
1033 uchar bios_id_lun; /* first boot device scsi id & lun */
1034 /* high nibble is lun */
1035 /* low nibble is scsi id */
1036
1037 uchar termination_se; /* 11 0 - automatic */
1038 /* 1 - low off / high off */
1039 /* 2 - low off / high on */
1040 /* 3 - low on / high on */
1041 /* There is no low on / high off */
1042
1043 uchar termination_lvd; /* 11 0 - automatic */
1044 /* 1 - low off / high off */
1045 /* 2 - low off / high on */
1046 /* 3 - low on / high on */
1047 /* There is no low on / high off */
1048
1049 ushort bios_ctrl; /* 12 BIOS control bits */
1050 /* bit 0 BIOS don't act as initiator. */
1051 /* bit 1 BIOS > 1 GB support */
1052 /* bit 2 BIOS > 2 Disk Support */
1053 /* bit 3 BIOS don't support removables */
1054 /* bit 4 BIOS support bootable CD */
1055 /* bit 5 BIOS scan enabled */
1056 /* bit 6 BIOS support multiple LUNs */
1057 /* bit 7 BIOS display of message */
1058 /* bit 8 SCAM disabled */
1059 /* bit 9 Reset SCSI bus during init. */
1060 /* bit 10 */
1061 /* bit 11 No verbose initialization. */
1062 /* bit 12 SCSI parity enabled */
1063 /* bit 13 */
1064 /* bit 14 */
1065 /* bit 15 */
1066 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1067 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1068 uchar max_host_qng; /* 15 maximum host queueing */
1069 uchar max_dvc_qng; /* maximum per device queuing */
1070 ushort dvc_cntl; /* 16 control bit for driver */
1071 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1072 ushort serial_number_word1; /* 18 Board serial number word 1 */
1073 ushort serial_number_word2; /* 19 Board serial number word 2 */
1074 ushort serial_number_word3; /* 20 Board serial number word 3 */
1075 ushort check_sum; /* 21 EEP check sum */
1076 uchar oem_name[16]; /* 22 OEM name */
1077 ushort dvc_err_code; /* 30 last device driver error code */
1078 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1079 ushort adv_err_addr; /* 32 last uc error address */
1080 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1081 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1082 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1083 ushort reserved36; /* 36 reserved */
1084 ushort reserved37; /* 37 reserved */
1085 ushort reserved38; /* 38 reserved */
1086 ushort reserved39; /* 39 reserved */
1087 ushort reserved40; /* 40 reserved */
1088 ushort reserved41; /* 41 reserved */
1089 ushort reserved42; /* 42 reserved */
1090 ushort reserved43; /* 43 reserved */
1091 ushort reserved44; /* 44 reserved */
1092 ushort reserved45; /* 45 reserved */
1093 ushort reserved46; /* 46 reserved */
1094 ushort reserved47; /* 47 reserved */
1095 ushort reserved48; /* 48 reserved */
1096 ushort reserved49; /* 49 reserved */
1097 ushort reserved50; /* 50 reserved */
1098 ushort reserved51; /* 51 reserved */
1099 ushort reserved52; /* 52 reserved */
1100 ushort reserved53; /* 53 reserved */
1101 ushort reserved54; /* 54 reserved */
1102 ushort reserved55; /* 55 reserved */
1103 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1104 ushort cisprt_msw; /* 57 CIS PTR MSW */
1105 ushort subsysvid; /* 58 SubSystem Vendor ID */
1106 ushort subsysid; /* 59 SubSystem ID */
1107 ushort reserved60; /* 60 reserved */
1108 ushort reserved61; /* 61 reserved */
1109 ushort reserved62; /* 62 reserved */
1110 ushort reserved63; /* 63 reserved */
1111 } ADVEEP_38C0800_CONFIG;
1112
1113 typedef struct adveep_38C1600_config {
1114 /* Word Offset, Description */
1115
1116 ushort cfg_lsw; /* 00 power up initialization */
1117 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1118 /* clear - Func. 0 INTA, Func. 1 INTB */
1119 /* bit 13 set - Load CIS */
1120 /* bit 14 set - BIOS Enable */
1121 /* bit 15 set - Big Endian Mode */
1122 ushort cfg_msw; /* 01 unused */
1123 ushort disc_enable; /* 02 disconnect enable */
1124 ushort wdtr_able; /* 03 Wide DTR able */
1125 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1126 ushort start_motor; /* 05 send start up motor */
1127 ushort tagqng_able; /* 06 tag queuing able */
1128 ushort bios_scan; /* 07 BIOS device control */
1129 ushort scam_tolerant; /* 08 no scam */
1130
1131 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1132 uchar bios_boot_delay; /* power up wait */
1133
1134 uchar scsi_reset_delay; /* 10 reset delay */
1135 uchar bios_id_lun; /* first boot device scsi id & lun */
1136 /* high nibble is lun */
1137 /* low nibble is scsi id */
1138
1139 uchar termination_se; /* 11 0 - automatic */
1140 /* 1 - low off / high off */
1141 /* 2 - low off / high on */
1142 /* 3 - low on / high on */
1143 /* There is no low on / high off */
1144
1145 uchar termination_lvd; /* 11 0 - automatic */
1146 /* 1 - low off / high off */
1147 /* 2 - low off / high on */
1148 /* 3 - low on / high on */
1149 /* There is no low on / high off */
1150
1151 ushort bios_ctrl; /* 12 BIOS control bits */
1152 /* bit 0 BIOS don't act as initiator. */
1153 /* bit 1 BIOS > 1 GB support */
1154 /* bit 2 BIOS > 2 Disk Support */
1155 /* bit 3 BIOS don't support removables */
1156 /* bit 4 BIOS support bootable CD */
1157 /* bit 5 BIOS scan enabled */
1158 /* bit 6 BIOS support multiple LUNs */
1159 /* bit 7 BIOS display of message */
1160 /* bit 8 SCAM disabled */
1161 /* bit 9 Reset SCSI bus during init. */
1162 /* bit 10 Basic Integrity Checking disabled */
1163 /* bit 11 No verbose initialization. */
1164 /* bit 12 SCSI parity enabled */
1165 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1166 /* bit 14 */
1167 /* bit 15 */
1168 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1169 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1170 uchar max_host_qng; /* 15 maximum host queueing */
1171 uchar max_dvc_qng; /* maximum per device queuing */
1172 ushort dvc_cntl; /* 16 control bit for driver */
1173 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1174 ushort serial_number_word1; /* 18 Board serial number word 1 */
1175 ushort serial_number_word2; /* 19 Board serial number word 2 */
1176 ushort serial_number_word3; /* 20 Board serial number word 3 */
1177 ushort check_sum; /* 21 EEP check sum */
1178 uchar oem_name[16]; /* 22 OEM name */
1179 ushort dvc_err_code; /* 30 last device driver error code */
1180 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1181 ushort adv_err_addr; /* 32 last uc error address */
1182 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1183 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1184 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1185 ushort reserved36; /* 36 reserved */
1186 ushort reserved37; /* 37 reserved */
1187 ushort reserved38; /* 38 reserved */
1188 ushort reserved39; /* 39 reserved */
1189 ushort reserved40; /* 40 reserved */
1190 ushort reserved41; /* 41 reserved */
1191 ushort reserved42; /* 42 reserved */
1192 ushort reserved43; /* 43 reserved */
1193 ushort reserved44; /* 44 reserved */
1194 ushort reserved45; /* 45 reserved */
1195 ushort reserved46; /* 46 reserved */
1196 ushort reserved47; /* 47 reserved */
1197 ushort reserved48; /* 48 reserved */
1198 ushort reserved49; /* 49 reserved */
1199 ushort reserved50; /* 50 reserved */
1200 ushort reserved51; /* 51 reserved */
1201 ushort reserved52; /* 52 reserved */
1202 ushort reserved53; /* 53 reserved */
1203 ushort reserved54; /* 54 reserved */
1204 ushort reserved55; /* 55 reserved */
1205 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1206 ushort cisprt_msw; /* 57 CIS PTR MSW */
1207 ushort subsysvid; /* 58 SubSystem Vendor ID */
1208 ushort subsysid; /* 59 SubSystem ID */
1209 ushort reserved60; /* 60 reserved */
1210 ushort reserved61; /* 61 reserved */
1211 ushort reserved62; /* 62 reserved */
1212 ushort reserved63; /* 63 reserved */
1213 } ADVEEP_38C1600_CONFIG;
1214
1215 /*
1216 * EEPROM Commands
1217 */
1218 #define ASC_EEP_CMD_DONE 0x0200
1219
1220 /* bios_ctrl */
1221 #define BIOS_CTRL_BIOS 0x0001
1222 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
1223 #define BIOS_CTRL_GT_2_DISK 0x0004
1224 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1225 #define BIOS_CTRL_BOOTABLE_CD 0x0010
1226 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
1227 #define BIOS_CTRL_DISPLAY_MSG 0x0080
1228 #define BIOS_CTRL_NO_SCAM 0x0100
1229 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1230 #define BIOS_CTRL_INIT_VERBOSE 0x0800
1231 #define BIOS_CTRL_SCSI_PARITY 0x1000
1232 #define BIOS_CTRL_AIPP_DIS 0x2000
1233
1234 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1235
1236 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1237
1238 /*
1239 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1240 * a special 16K Adv Library and Microcode version. After the issue is
1241 * resolved, should restore 32K support.
1242 *
1243 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1244 */
1245 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1246
1247 /*
1248 * Byte I/O register address from base of 'iop_base'.
1249 */
1250 #define IOPB_INTR_STATUS_REG 0x00
1251 #define IOPB_CHIP_ID_1 0x01
1252 #define IOPB_INTR_ENABLES 0x02
1253 #define IOPB_CHIP_TYPE_REV 0x03
1254 #define IOPB_RES_ADDR_4 0x04
1255 #define IOPB_RES_ADDR_5 0x05
1256 #define IOPB_RAM_DATA 0x06
1257 #define IOPB_RES_ADDR_7 0x07
1258 #define IOPB_FLAG_REG 0x08
1259 #define IOPB_RES_ADDR_9 0x09
1260 #define IOPB_RISC_CSR 0x0A
1261 #define IOPB_RES_ADDR_B 0x0B
1262 #define IOPB_RES_ADDR_C 0x0C
1263 #define IOPB_RES_ADDR_D 0x0D
1264 #define IOPB_SOFT_OVER_WR 0x0E
1265 #define IOPB_RES_ADDR_F 0x0F
1266 #define IOPB_MEM_CFG 0x10
1267 #define IOPB_RES_ADDR_11 0x11
1268 #define IOPB_GPIO_DATA 0x12
1269 #define IOPB_RES_ADDR_13 0x13
1270 #define IOPB_FLASH_PAGE 0x14
1271 #define IOPB_RES_ADDR_15 0x15
1272 #define IOPB_GPIO_CNTL 0x16
1273 #define IOPB_RES_ADDR_17 0x17
1274 #define IOPB_FLASH_DATA 0x18
1275 #define IOPB_RES_ADDR_19 0x19
1276 #define IOPB_RES_ADDR_1A 0x1A
1277 #define IOPB_RES_ADDR_1B 0x1B
1278 #define IOPB_RES_ADDR_1C 0x1C
1279 #define IOPB_RES_ADDR_1D 0x1D
1280 #define IOPB_RES_ADDR_1E 0x1E
1281 #define IOPB_RES_ADDR_1F 0x1F
1282 #define IOPB_DMA_CFG0 0x20
1283 #define IOPB_DMA_CFG1 0x21
1284 #define IOPB_TICKLE 0x22
1285 #define IOPB_DMA_REG_WR 0x23
1286 #define IOPB_SDMA_STATUS 0x24
1287 #define IOPB_SCSI_BYTE_CNT 0x25
1288 #define IOPB_HOST_BYTE_CNT 0x26
1289 #define IOPB_BYTE_LEFT_TO_XFER 0x27
1290 #define IOPB_BYTE_TO_XFER_0 0x28
1291 #define IOPB_BYTE_TO_XFER_1 0x29
1292 #define IOPB_BYTE_TO_XFER_2 0x2A
1293 #define IOPB_BYTE_TO_XFER_3 0x2B
1294 #define IOPB_ACC_GRP 0x2C
1295 #define IOPB_RES_ADDR_2D 0x2D
1296 #define IOPB_DEV_ID 0x2E
1297 #define IOPB_RES_ADDR_2F 0x2F
1298 #define IOPB_SCSI_DATA 0x30
1299 #define IOPB_RES_ADDR_31 0x31
1300 #define IOPB_RES_ADDR_32 0x32
1301 #define IOPB_SCSI_DATA_HSHK 0x33
1302 #define IOPB_SCSI_CTRL 0x34
1303 #define IOPB_RES_ADDR_35 0x35
1304 #define IOPB_RES_ADDR_36 0x36
1305 #define IOPB_RES_ADDR_37 0x37
1306 #define IOPB_RAM_BIST 0x38
1307 #define IOPB_PLL_TEST 0x39
1308 #define IOPB_PCI_INT_CFG 0x3A
1309 #define IOPB_RES_ADDR_3B 0x3B
1310 #define IOPB_RFIFO_CNT 0x3C
1311 #define IOPB_RES_ADDR_3D 0x3D
1312 #define IOPB_RES_ADDR_3E 0x3E
1313 #define IOPB_RES_ADDR_3F 0x3F
1314
1315 /*
1316 * Word I/O register address from base of 'iop_base'.
1317 */
1318 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
1319 #define IOPW_CTRL_REG 0x02 /* CC */
1320 #define IOPW_RAM_ADDR 0x04 /* LA */
1321 #define IOPW_RAM_DATA 0x06 /* LD */
1322 #define IOPW_RES_ADDR_08 0x08
1323 #define IOPW_RISC_CSR 0x0A /* CSR */
1324 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1325 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1326 #define IOPW_RES_ADDR_10 0x10
1327 #define IOPW_SEL_MASK 0x12 /* SM */
1328 #define IOPW_RES_ADDR_14 0x14
1329 #define IOPW_FLASH_ADDR 0x16 /* FA */
1330 #define IOPW_RES_ADDR_18 0x18
1331 #define IOPW_EE_CMD 0x1A /* EC */
1332 #define IOPW_EE_DATA 0x1C /* ED */
1333 #define IOPW_SFIFO_CNT 0x1E /* SFC */
1334 #define IOPW_RES_ADDR_20 0x20
1335 #define IOPW_Q_BASE 0x22 /* QB */
1336 #define IOPW_QP 0x24 /* QP */
1337 #define IOPW_IX 0x26 /* IX */
1338 #define IOPW_SP 0x28 /* SP */
1339 #define IOPW_PC 0x2A /* PC */
1340 #define IOPW_RES_ADDR_2C 0x2C
1341 #define IOPW_RES_ADDR_2E 0x2E
1342 #define IOPW_SCSI_DATA 0x30 /* SD */
1343 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1344 #define IOPW_SCSI_CTRL 0x34 /* SC */
1345 #define IOPW_HSHK_CFG 0x36 /* HCFG */
1346 #define IOPW_SXFR_STATUS 0x36 /* SXS */
1347 #define IOPW_SXFR_CNTL 0x38 /* SXL */
1348 #define IOPW_SXFR_CNTH 0x3A /* SXH */
1349 #define IOPW_RES_ADDR_3C 0x3C
1350 #define IOPW_RFIFO_DATA 0x3E /* RFD */
1351
1352 /*
1353 * Doubleword I/O register address from base of 'iop_base'.
1354 */
1355 #define IOPDW_RES_ADDR_0 0x00
1356 #define IOPDW_RAM_DATA 0x04
1357 #define IOPDW_RES_ADDR_8 0x08
1358 #define IOPDW_RES_ADDR_C 0x0C
1359 #define IOPDW_RES_ADDR_10 0x10
1360 #define IOPDW_COMMA 0x14
1361 #define IOPDW_COMMB 0x18
1362 #define IOPDW_RES_ADDR_1C 0x1C
1363 #define IOPDW_SDMA_ADDR0 0x20
1364 #define IOPDW_SDMA_ADDR1 0x24
1365 #define IOPDW_SDMA_COUNT 0x28
1366 #define IOPDW_SDMA_ERROR 0x2C
1367 #define IOPDW_RDMA_ADDR0 0x30
1368 #define IOPDW_RDMA_ADDR1 0x34
1369 #define IOPDW_RDMA_COUNT 0x38
1370 #define IOPDW_RDMA_ERROR 0x3C
1371
1372 #define ADV_CHIP_ID_BYTE 0x25
1373 #define ADV_CHIP_ID_WORD 0x04C1
1374
1375 #define ADV_INTR_ENABLE_HOST_INTR 0x01
1376 #define ADV_INTR_ENABLE_SEL_INTR 0x02
1377 #define ADV_INTR_ENABLE_DPR_INTR 0x04
1378 #define ADV_INTR_ENABLE_RTA_INTR 0x08
1379 #define ADV_INTR_ENABLE_RMA_INTR 0x10
1380 #define ADV_INTR_ENABLE_RST_INTR 0x20
1381 #define ADV_INTR_ENABLE_DPE_INTR 0x40
1382 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1383
1384 #define ADV_INTR_STATUS_INTRA 0x01
1385 #define ADV_INTR_STATUS_INTRB 0x02
1386 #define ADV_INTR_STATUS_INTRC 0x04
1387
1388 #define ADV_RISC_CSR_STOP (0x0000)
1389 #define ADV_RISC_TEST_COND (0x2000)
1390 #define ADV_RISC_CSR_RUN (0x4000)
1391 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1392
1393 #define ADV_CTRL_REG_HOST_INTR 0x0100
1394 #define ADV_CTRL_REG_SEL_INTR 0x0200
1395 #define ADV_CTRL_REG_DPR_INTR 0x0400
1396 #define ADV_CTRL_REG_RTA_INTR 0x0800
1397 #define ADV_CTRL_REG_RMA_INTR 0x1000
1398 #define ADV_CTRL_REG_RES_BIT14 0x2000
1399 #define ADV_CTRL_REG_DPE_INTR 0x4000
1400 #define ADV_CTRL_REG_POWER_DONE 0x8000
1401 #define ADV_CTRL_REG_ANY_INTR 0xFF00
1402
1403 #define ADV_CTRL_REG_CMD_RESET 0x00C6
1404 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1405 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1406 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1407 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1408
1409 #define ADV_TICKLE_NOP 0x00
1410 #define ADV_TICKLE_A 0x01
1411 #define ADV_TICKLE_B 0x02
1412 #define ADV_TICKLE_C 0x03
1413
1414 #define AdvIsIntPending(port) \
1415 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1416
1417 /*
1418 * SCSI_CFG0 Register bit definitions
1419 */
1420 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1421 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1422 #define EVEN_PARITY 0x1000 /* Select Even Parity */
1423 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1424 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1425 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1426 #define SCAM_EN 0x0080 /* Enable SCAM selection */
1427 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1428 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1429 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1430 #define OUR_ID 0x000F /* SCSI ID */
1431
1432 /*
1433 * SCSI_CFG1 Register bit definitions
1434 */
1435 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1436 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1437 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1438 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
1439 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1440 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1441 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1442 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1443 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1444 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1445 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1446 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1447 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1448 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1449 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1450
1451 /*
1452 * Addendum for ASC-38C0800 Chip
1453 *
1454 * The ASC-38C1600 Chip uses the same definitions except that the
1455 * bus mode override bits [12:10] have been moved to byte register
1456 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1457 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1458 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1459 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1460 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1461 */
1462 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1463 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1464 #define HVD 0x1000 /* HVD Device Detect */
1465 #define LVD 0x0800 /* LVD Device Detect */
1466 #define SE 0x0400 /* SE Device Detect */
1467 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
1468 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1469 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1470 #define TERM_SE 0x0030 /* SE Termination Bits */
1471 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1472 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1473 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1474 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1475 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1476 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1477 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1478 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1479
1480 #define CABLE_ILLEGAL_A 0x7
1481 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1482
1483 #define CABLE_ILLEGAL_B 0xB
1484 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1485
1486 /*
1487 * MEM_CFG Register bit definitions
1488 */
1489 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1490 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1491 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1492 #define RAM_SZ_2KB 0x00 /* 2 KB */
1493 #define RAM_SZ_4KB 0x04 /* 4 KB */
1494 #define RAM_SZ_8KB 0x08 /* 8 KB */
1495 #define RAM_SZ_16KB 0x0C /* 16 KB */
1496 #define RAM_SZ_32KB 0x10 /* 32 KB */
1497 #define RAM_SZ_64KB 0x14 /* 64 KB */
1498
1499 /*
1500 * DMA_CFG0 Register bit definitions
1501 *
1502 * This register is only accessible to the host.
1503 */
1504 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1505 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1506 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
1507 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
1508 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
1509 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
1510 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1511 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
1512 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
1513 #define START_CTL 0x0C /* DMA start conditions */
1514 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
1515 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1516 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1517 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1518 #define READ_CMD 0x03 /* Memory Read Method */
1519 #define READ_CMD_MR 0x00 /* Memory Read */
1520 #define READ_CMD_MRL 0x02 /* Memory Read Long */
1521 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1522
1523 /*
1524 * ASC-38C0800 RAM BIST Register bit definitions
1525 */
1526 #define RAM_TEST_MODE 0x80
1527 #define PRE_TEST_MODE 0x40
1528 #define NORMAL_MODE 0x00
1529 #define RAM_TEST_DONE 0x10
1530 #define RAM_TEST_STATUS 0x0F
1531 #define RAM_TEST_HOST_ERROR 0x08
1532 #define RAM_TEST_INTRAM_ERROR 0x04
1533 #define RAM_TEST_RISC_ERROR 0x02
1534 #define RAM_TEST_SCSI_ERROR 0x01
1535 #define RAM_TEST_SUCCESS 0x00
1536 #define PRE_TEST_VALUE 0x05
1537 #define NORMAL_VALUE 0x00
1538
1539 /*
1540 * ASC38C1600 Definitions
1541 *
1542 * IOPB_PCI_INT_CFG Bit Field Definitions
1543 */
1544
1545 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1546
1547 /*
1548 * Bit 1 can be set to change the interrupt for the Function to operate in
1549 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1550 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1551 * mode, otherwise the operating mode is undefined.
1552 */
1553 #define TOTEMPOLE 0x02
1554
1555 /*
1556 * Bit 0 can be used to change the Int Pin for the Function. The value is
1557 * 0 by default for both Functions with Function 0 using INT A and Function
1558 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1559 * INT A is used.
1560 *
1561 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1562 * value specified in the PCI Configuration Space.
1563 */
1564 #define INTAB 0x01
1565
1566 /*
1567 * Adv Library Status Definitions
1568 */
1569 #define ADV_TRUE 1
1570 #define ADV_FALSE 0
1571 #define ADV_SUCCESS 1
1572 #define ADV_BUSY 0
1573 #define ADV_ERROR (-1)
1574
1575 /*
1576 * ADV_DVC_VAR 'warn_code' values
1577 */
1578 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1579 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1580 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
1581 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1582
1583 #define ADV_MAX_TID 15 /* max. target identifier */
1584 #define ADV_MAX_LUN 7 /* max. logical unit number */
1585
1586 /*
1587 * Fixed locations of microcode operating variables.
1588 */
1589 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1590 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1591 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1592 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1593 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1594 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1595 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1596 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1597 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1598 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1599 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1600 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1601 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1602 #define ASC_MC_CHIP_TYPE 0x009A
1603 #define ASC_MC_INTRB_CODE 0x009B
1604 #define ASC_MC_WDTR_ABLE 0x009C
1605 #define ASC_MC_SDTR_ABLE 0x009E
1606 #define ASC_MC_TAGQNG_ABLE 0x00A0
1607 #define ASC_MC_DISC_ENABLE 0x00A2
1608 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
1609 #define ASC_MC_IDLE_CMD 0x00A6
1610 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1611 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1612 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1613 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1614 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1615 #define ASC_MC_SDTR_DONE 0x00B6
1616 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1617 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1618 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
1619 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1620 #define ASC_MC_WDTR_DONE 0x0124
1621 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1622 #define ASC_MC_ICQ 0x0160
1623 #define ASC_MC_IRQ 0x0164
1624 #define ASC_MC_PPR_ABLE 0x017A
1625
1626 /*
1627 * BIOS LRAM variable absolute offsets.
1628 */
1629 #define BIOS_CODESEG 0x54
1630 #define BIOS_CODELEN 0x56
1631 #define BIOS_SIGNATURE 0x58
1632 #define BIOS_VERSION 0x5A
1633
1634 /*
1635 * Microcode Control Flags
1636 *
1637 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1638 * and handled by the microcode.
1639 */
1640 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1641 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1642
1643 /*
1644 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1645 */
1646 #define HSHK_CFG_WIDE_XFR 0x8000
1647 #define HSHK_CFG_RATE 0x0F00
1648 #define HSHK_CFG_OFFSET 0x001F
1649
1650 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1651 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1652 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1653 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1654
1655 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1656 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1657 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1658 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1659 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1660
1661 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1662 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1663 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1664 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1665 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1666 /*
1667 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1668 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1669 */
1670 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1671 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1672
1673 /*
1674 * All fields here are accessed by the board microcode and need to be
1675 * little-endian.
1676 */
1677 typedef struct adv_carr_t {
1678 __le32 carr_va; /* Carrier Virtual Address */
1679 __le32 carr_pa; /* Carrier Physical Address */
1680 __le32 areq_vpa; /* ADV_SCSI_REQ_Q Virtual or Physical Address */
1681 /*
1682 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1683 *
1684 * next_vpa [3:1] Reserved Bits
1685 * next_vpa [0] Done Flag set in Response Queue.
1686 */
1687 __le32 next_vpa;
1688 } ADV_CARR_T;
1689
1690 /*
1691 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1692 */
1693 #define ADV_NEXT_VPA_MASK 0xFFFFFFF0
1694
1695 #define ADV_RQ_DONE 0x00000001
1696 #define ADV_RQ_GOOD 0x00000002
1697 #define ADV_CQ_STOPPER 0x00000000
1698
1699 #define ADV_GET_CARRP(carrp) ((carrp) & ADV_NEXT_VPA_MASK)
1700
1701 /*
1702 * Each carrier is 64 bytes, and we need three additional
1703 * carrier for icq, irq, and the termination carrier.
1704 */
1705 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 3)
1706
1707 #define ADV_CARRIER_BUFSIZE \
1708 (ADV_CARRIER_COUNT * sizeof(ADV_CARR_T))
1709
1710 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1711 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1712 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1713
1714 /*
1715 * Adapter temporary configuration structure
1716 *
1717 * This structure can be discarded after initialization. Don't add
1718 * fields here needed after initialization.
1719 *
1720 * Field naming convention:
1721 *
1722 * *_enable indicates the field enables or disables a feature. The
1723 * value of the field is never reset.
1724 */
1725 typedef struct adv_dvc_cfg {
1726 ushort disc_enable; /* enable disconnection */
1727 uchar chip_version; /* chip version */
1728 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1729 ushort control_flag; /* Microcode Control Flag */
1730 ushort mcode_date; /* Microcode date */
1731 ushort mcode_version; /* Microcode version */
1732 ushort serial1; /* EEPROM serial number word 1 */
1733 ushort serial2; /* EEPROM serial number word 2 */
1734 ushort serial3; /* EEPROM serial number word 3 */
1735 } ADV_DVC_CFG;
1736
1737 struct adv_dvc_var;
1738 struct adv_scsi_req_q;
1739
1740 typedef struct adv_sg_block {
1741 uchar reserved1;
1742 uchar reserved2;
1743 uchar reserved3;
1744 uchar sg_cnt; /* Valid entries in block. */
1745 __le32 sg_ptr; /* Pointer to next sg block. */
1746 struct {
1747 __le32 sg_addr; /* SG element address. */
1748 __le32 sg_count; /* SG element count. */
1749 } sg_list[NO_OF_SG_PER_BLOCK];
1750 } ADV_SG_BLOCK;
1751
1752 /*
1753 * ADV_SCSI_REQ_Q - microcode request structure
1754 *
1755 * All fields in this structure up to byte 60 are used by the microcode.
1756 * The microcode makes assumptions about the size and ordering of fields
1757 * in this structure. Do not change the structure definition here without
1758 * coordinating the change with the microcode.
1759 *
1760 * All fields accessed by microcode must be maintained in little_endian
1761 * order.
1762 */
1763 typedef struct adv_scsi_req_q {
1764 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1765 uchar target_cmd;
1766 uchar target_id; /* Device target identifier. */
1767 uchar target_lun; /* Device target logical unit number. */
1768 __le32 data_addr; /* Data buffer physical address. */
1769 __le32 data_cnt; /* Data count. Ucode sets to residual. */
1770 __le32 sense_addr;
1771 __le32 carr_pa;
1772 uchar mflag;
1773 uchar sense_len;
1774 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1775 uchar scsi_cntl;
1776 uchar done_status; /* Completion status. */
1777 uchar scsi_status; /* SCSI status byte. */
1778 uchar host_status; /* Ucode host status. */
1779 uchar sg_working_ix;
1780 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
1781 __le32 sg_real_addr; /* SG list physical address. */
1782 __le32 scsiq_rptr;
1783 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
1784 __le32 scsiq_ptr;
1785 __le32 carr_va;
1786 /*
1787 * End of microcode structure - 60 bytes. The rest of the structure
1788 * is used by the Adv Library and ignored by the microcode.
1789 */
1790 u32 srb_tag;
1791 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1792 } ADV_SCSI_REQ_Q;
1793
1794 /*
1795 * The following two structures are used to process Wide Board requests.
1796 *
1797 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1798 * and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the
1799 * SCSI request tag. The adv_req_t structure 'cmndp' field in turn points
1800 * to the Mid-Level SCSI request structure.
1801 *
1802 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1803 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1804 * up to 255 scatter-gather elements may be used per request or
1805 * ADV_SCSI_REQ_Q.
1806 *
1807 * Both structures must be 32 byte aligned.
1808 */
1809 typedef struct adv_sgblk {
1810 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
1811 dma_addr_t sg_addr; /* Physical address */
1812 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
1813 } adv_sgblk_t;
1814
1815 typedef struct adv_req {
1816 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
1817 uchar align[24]; /* Request structure padding. */
1818 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
1819 dma_addr_t req_addr;
1820 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
1821 } adv_req_t __aligned(32);
1822
1823 /*
1824 * Adapter operation variable structure.
1825 *
1826 * One structure is required per host adapter.
1827 *
1828 * Field naming convention:
1829 *
1830 * *_able indicates both whether a feature should be enabled or disabled
1831 * and whether a device isi capable of the feature. At initialization
1832 * this field may be set, but later if a device is found to be incapable
1833 * of the feature, the field is cleared.
1834 */
1835 typedef struct adv_dvc_var {
1836 AdvPortAddr iop_base; /* I/O port address */
1837 ushort err_code; /* fatal error code */
1838 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1839 ushort wdtr_able; /* try WDTR for a device */
1840 ushort sdtr_able; /* try SDTR for a device */
1841 ushort ultra_able; /* try SDTR Ultra speed for a device */
1842 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1843 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1844 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1845 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1846 ushort tagqng_able; /* try tagged queuing with a device */
1847 ushort ppr_able; /* PPR message capable per TID bitmask. */
1848 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1849 ushort start_motor; /* start motor command allowed */
1850 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1851 uchar chip_no; /* should be assigned by caller */
1852 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1853 ushort no_scam; /* scam_tolerant of EEPROM */
1854 struct asc_board *drv_ptr; /* driver pointer to private structure */
1855 uchar chip_scsi_id; /* chip SCSI target ID */
1856 uchar chip_type;
1857 uchar bist_err_code;
1858 ADV_CARR_T *carrier;
1859 ADV_CARR_T *carr_freelist; /* Carrier free list. */
1860 dma_addr_t carrier_addr;
1861 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1862 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1863 ushort carr_pending_cnt; /* Count of pending carriers. */
1864 /*
1865 * Note: The following fields will not be used after initialization. The
1866 * driver may discard the buffer after initialization is done.
1867 */
1868 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1869 } ADV_DVC_VAR;
1870
1871 /*
1872 * Microcode idle loop commands
1873 */
1874 #define IDLE_CMD_COMPLETED 0
1875 #define IDLE_CMD_STOP_CHIP 0x0001
1876 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
1877 #define IDLE_CMD_SEND_INT 0x0004
1878 #define IDLE_CMD_ABORT 0x0008
1879 #define IDLE_CMD_DEVICE_RESET 0x0010
1880 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
1881 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
1882 #define IDLE_CMD_SCSIREQ 0x0080
1883
1884 #define IDLE_CMD_STATUS_SUCCESS 0x0001
1885 #define IDLE_CMD_STATUS_FAILURE 0x0002
1886
1887 /*
1888 * AdvSendIdleCmd() flag definitions.
1889 */
1890 #define ADV_NOWAIT 0x01
1891
1892 /*
1893 * Wait loop time out values.
1894 */
1895 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
1896 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
1897 #define SCSI_MAX_RETRY 10 /* retry count */
1898
1899 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
1900 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
1901 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
1902 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
1903
1904 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
1905
1906 /* Read byte from a register. */
1907 #define AdvReadByteRegister(iop_base, reg_off) \
1908 (ADV_MEM_READB((iop_base) + (reg_off)))
1909
1910 /* Write byte to a register. */
1911 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
1912 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1913
1914 /* Read word (2 bytes) from a register. */
1915 #define AdvReadWordRegister(iop_base, reg_off) \
1916 (ADV_MEM_READW((iop_base) + (reg_off)))
1917
1918 /* Write word (2 bytes) to a register. */
1919 #define AdvWriteWordRegister(iop_base, reg_off, word) \
1920 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
1921
1922 /* Write dword (4 bytes) to a register. */
1923 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
1924 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
1925
1926 /* Read byte from LRAM. */
1927 #define AdvReadByteLram(iop_base, addr, byte) \
1928 do { \
1929 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1930 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
1931 } while (0)
1932
1933 /* Write byte to LRAM. */
1934 #define AdvWriteByteLram(iop_base, addr, byte) \
1935 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1936 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
1937
1938 /* Read word (2 bytes) from LRAM. */
1939 #define AdvReadWordLram(iop_base, addr, word) \
1940 do { \
1941 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1942 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
1943 } while (0)
1944
1945 /* Write word (2 bytes) to LRAM. */
1946 #define AdvWriteWordLram(iop_base, addr, word) \
1947 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1948 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
1949
1950 /* Write little-endian double word (4 bytes) to LRAM */
1951 /* Because of unspecified C language ordering don't use auto-increment. */
1952 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
1953 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1954 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
1955 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
1956 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
1957 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
1958 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
1959
1960 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
1961 #define AdvReadWordAutoIncLram(iop_base) \
1962 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
1963
1964 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
1965 #define AdvWriteWordAutoIncLram(iop_base, word) \
1966 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
1967
1968 /*
1969 * Define macro to check for Condor signature.
1970 *
1971 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
1972 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
1973 */
1974 #define AdvFindSignature(iop_base) \
1975 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
1976 ADV_CHIP_ID_BYTE) && \
1977 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
1978 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
1979
1980 /*
1981 * Define macro to Return the version number of the chip at 'iop_base'.
1982 *
1983 * The second parameter 'bus_type' is currently unused.
1984 */
1985 #define AdvGetChipVersion(iop_base, bus_type) \
1986 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
1987
1988 /*
1989 * Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must
1990 * match the ADV_SCSI_REQ_Q 'srb_tag' field.
1991 *
1992 * If the request has not yet been sent to the device it will simply be
1993 * aborted from RISC memory. If the request is disconnected it will be
1994 * aborted on reselection by sending an Abort Message to the target ID.
1995 *
1996 * Return value:
1997 * ADV_TRUE(1) - Queue was successfully aborted.
1998 * ADV_FALSE(0) - Queue was not found on the active queue list.
1999 */
2000 #define AdvAbortQueue(asc_dvc, srb_tag) \
2001 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2002 (ADV_DCNT) (srb_tag))
2003
2004 /*
2005 * Send a Bus Device Reset Message to the specified target ID.
2006 *
2007 * All outstanding commands will be purged if sending the
2008 * Bus Device Reset Message is successful.
2009 *
2010 * Return Value:
2011 * ADV_TRUE(1) - All requests on the target are purged.
2012 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2013 * are not purged.
2014 */
2015 #define AdvResetDevice(asc_dvc, target_id) \
2016 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2017 (ADV_DCNT) (target_id))
2018
2019 /*
2020 * SCSI Wide Type definition.
2021 */
2022 #define ADV_SCSI_BIT_ID_TYPE ushort
2023
2024 /*
2025 * AdvInitScsiTarget() 'cntl_flag' options.
2026 */
2027 #define ADV_SCAN_LUN 0x01
2028 #define ADV_CAPINFO_NOLUN 0x02
2029
2030 /*
2031 * Convert target id to target id bit mask.
2032 */
2033 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2034
2035 /*
2036 * ADV_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2037 */
2038
2039 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
2040 #define QD_NO_ERROR 0x01
2041 #define QD_ABORTED_BY_HOST 0x02
2042 #define QD_WITH_ERROR 0x04
2043
2044 #define QHSTA_NO_ERROR 0x00
2045 #define QHSTA_M_SEL_TIMEOUT 0x11
2046 #define QHSTA_M_DATA_OVER_RUN 0x12
2047 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2048 #define QHSTA_M_QUEUE_ABORTED 0x15
2049 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2050 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2051 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2052 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2053 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2054 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2055 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
2056 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2057 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2058 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2059 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2060 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2061 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2062 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2063 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2064 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
2065 #define QHSTA_M_WTM_TIMEOUT 0x41
2066 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2067 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2068 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2069 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2070 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2071 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
2072
2073 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2074 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2075
2076 /*
2077 * Total contiguous memory needed for driver SG blocks.
2078 *
2079 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2080 * number of scatter-gather elements the driver supports in a
2081 * single request.
2082 */
2083
2084 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2085 (sizeof(ADV_SG_BLOCK) * \
2086 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2087
2088 /* struct asc_board flags */
2089 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
2090
2091 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2092
2093 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
2094
2095 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
2096
2097 /* Asc Library return codes */
2098 #define ASC_TRUE 1
2099 #define ASC_FALSE 0
2100 #define ASC_NOERROR 1
2101 #define ASC_BUSY 0
2102 #define ASC_ERROR (-1)
2103
2104 /* struct scsi_cmnd function return codes */
2105 #define STATUS_BYTE(byte) (byte)
2106 #define MSG_BYTE(byte) ((byte) << 8)
2107 #define HOST_BYTE(byte) ((byte) << 16)
2108 #define DRIVER_BYTE(byte) ((byte) << 24)
2109
2110 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2111 #ifndef ADVANSYS_STATS
2112 #define ASC_STATS_ADD(shost, counter, count)
2113 #else /* ADVANSYS_STATS */
2114 #define ASC_STATS_ADD(shost, counter, count) \
2115 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2116 #endif /* ADVANSYS_STATS */
2117
2118 /* If the result wraps when calculating tenths, return 0. */
2119 #define ASC_TENTHS(num, den) \
2120 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2121 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2122
2123 /*
2124 * Display a message to the console.
2125 */
2126 #define ASC_PRINT(s) \
2127 { \
2128 printk("advansys: "); \
2129 printk(s); \
2130 }
2131
2132 #define ASC_PRINT1(s, a1) \
2133 { \
2134 printk("advansys: "); \
2135 printk((s), (a1)); \
2136 }
2137
2138 #define ASC_PRINT2(s, a1, a2) \
2139 { \
2140 printk("advansys: "); \
2141 printk((s), (a1), (a2)); \
2142 }
2143
2144 #define ASC_PRINT3(s, a1, a2, a3) \
2145 { \
2146 printk("advansys: "); \
2147 printk((s), (a1), (a2), (a3)); \
2148 }
2149
2150 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2151 { \
2152 printk("advansys: "); \
2153 printk((s), (a1), (a2), (a3), (a4)); \
2154 }
2155
2156 #ifndef ADVANSYS_DEBUG
2157
2158 #define ASC_DBG(lvl, s...)
2159 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2160 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2161 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2162 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2163 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2164 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2165 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2166 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2167 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2168
2169 #else /* ADVANSYS_DEBUG */
2170
2171 /*
2172 * Debugging Message Levels:
2173 * 0: Errors Only
2174 * 1: High-Level Tracing
2175 * 2-N: Verbose Tracing
2176 */
2177
2178 #define ASC_DBG(lvl, format, arg...) { \
2179 if (asc_dbglvl >= (lvl)) \
2180 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
2181 __func__ , ## arg); \
2182 }
2183
2184 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2185 { \
2186 if (asc_dbglvl >= (lvl)) { \
2187 asc_prt_scsi_host(s); \
2188 } \
2189 }
2190
2191 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2192 { \
2193 if (asc_dbglvl >= (lvl)) { \
2194 asc_prt_asc_scsi_q(scsiqp); \
2195 } \
2196 }
2197
2198 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2199 { \
2200 if (asc_dbglvl >= (lvl)) { \
2201 asc_prt_asc_qdone_info(qdone); \
2202 } \
2203 }
2204
2205 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2206 { \
2207 if (asc_dbglvl >= (lvl)) { \
2208 asc_prt_adv_scsi_req_q(scsiqp); \
2209 } \
2210 }
2211
2212 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2213 { \
2214 if (asc_dbglvl >= (lvl)) { \
2215 asc_prt_hex((name), (start), (length)); \
2216 } \
2217 }
2218
2219 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2220 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2221
2222 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2223 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2224
2225 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2226 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2227 #endif /* ADVANSYS_DEBUG */
2228
2229 #ifdef ADVANSYS_STATS
2230
2231 /* Per board statistics structure */
2232 struct asc_stats {
2233 /* Driver Entrypoint Statistics */
2234 unsigned int queuecommand; /* # calls to advansys_queuecommand() */
2235 unsigned int reset; /* # calls to advansys_eh_bus_reset() */
2236 unsigned int biosparam; /* # calls to advansys_biosparam() */
2237 unsigned int interrupt; /* # advansys_interrupt() calls */
2238 unsigned int callback; /* # calls to asc/adv_isr_callback() */
2239 unsigned int done; /* # calls to request's scsi_done function */
2240 unsigned int build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2241 unsigned int adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2242 unsigned int adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2243 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2244 unsigned int exe_noerror; /* # ASC_NOERROR returns. */
2245 unsigned int exe_busy; /* # ASC_BUSY returns. */
2246 unsigned int exe_error; /* # ASC_ERROR returns. */
2247 unsigned int exe_unknown; /* # unknown returns. */
2248 /* Data Transfer Statistics */
2249 unsigned int xfer_cnt; /* # I/O requests received */
2250 unsigned int xfer_elem; /* # scatter-gather elements */
2251 unsigned int xfer_sect; /* # 512-byte blocks */
2252 };
2253 #endif /* ADVANSYS_STATS */
2254
2255 /*
2256 * Structure allocated for each board.
2257 *
2258 * This structure is allocated by scsi_host_alloc() at the end
2259 * of the 'Scsi_Host' structure starting at the 'hostdata'
2260 * field. It is guaranteed to be allocated from DMA-able memory.
2261 */
2262 struct asc_board {
2263 struct device *dev;
2264 struct Scsi_Host *shost;
2265 uint flags; /* Board flags */
2266 unsigned int irq;
2267 union {
2268 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2269 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2270 } dvc_var;
2271 union {
2272 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2273 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2274 } dvc_cfg;
2275 ushort asc_n_io_port; /* Number I/O ports. */
2276 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
2277 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2278 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2279 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2280 union {
2281 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2282 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2283 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2284 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2285 } eep_config;
2286 /* /proc/scsi/advansys/[0...] */
2287 #ifdef ADVANSYS_STATS
2288 struct asc_stats asc_stats; /* Board statistics */
2289 #endif /* ADVANSYS_STATS */
2290 /*
2291 * The following fields are used only for Narrow Boards.
2292 */
2293 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2294 /*
2295 * The following fields are used only for Wide Boards.
2296 */
2297 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2298 ushort ioport; /* I/O Port address. */
2299 adv_req_t *adv_reqp; /* Request structures. */
2300 dma_addr_t adv_reqp_addr;
2301 size_t adv_reqp_size;
2302 struct dma_pool *adv_sgblk_pool; /* Scatter-gather structures. */
2303 ushort bios_signature; /* BIOS Signature. */
2304 ushort bios_version; /* BIOS Version. */
2305 ushort bios_codeseg; /* BIOS Code Segment. */
2306 ushort bios_codelen; /* BIOS Code Segment Length. */
2307 };
2308
2309 #define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2310 dvc_var.asc_dvc_var)
2311 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2312 dvc_var.adv_dvc_var)
2313 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2314
2315 #ifdef ADVANSYS_DEBUG
2316 static int asc_dbglvl = 3;
2317
2318 /*
2319 * asc_prt_asc_dvc_var()
2320 */
2321 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2322 {
2323 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2324
2325 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2326 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2327
2328 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2329 (unsigned)h->init_sdtr);
2330
2331 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2332 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2333 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2334 (unsigned)h->chip_no);
2335
2336 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2337 "%u,\n", (unsigned)h->queue_full_or_busy,
2338 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2339
2340 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2341 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2342 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2343 (unsigned)h->in_critical_cnt);
2344
2345 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2346 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2347 (unsigned)h->init_state, (unsigned)h->no_scam,
2348 (unsigned)h->pci_fix_asyn_xfer);
2349
2350 printk(" cfg 0x%lx\n", (ulong)h->cfg);
2351 }
2352
2353 /*
2354 * asc_prt_asc_dvc_cfg()
2355 */
2356 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2357 {
2358 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2359
2360 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2361 h->can_tagged_qng, h->cmd_qng_enabled);
2362 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2363 h->disc_enable, h->sdtr_enable);
2364
2365 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2366 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2367 h->isa_dma_channel, h->chip_version);
2368
2369 printk(" mcode_date 0x%x, mcode_version %d\n",
2370 h->mcode_date, h->mcode_version);
2371 }
2372
2373 /*
2374 * asc_prt_adv_dvc_var()
2375 *
2376 * Display an ADV_DVC_VAR structure.
2377 */
2378 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2379 {
2380 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2381
2382 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2383 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2384
2385 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
2386 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2387
2388 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
2389 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2390
2391 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%p\n",
2392 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2393 h->carr_freelist);
2394
2395 printk(" icq_sp 0x%p, irq_sp 0x%p\n", h->icq_sp, h->irq_sp);
2396
2397 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2398 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2399
2400 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2401 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2402 }
2403
2404 /*
2405 * asc_prt_adv_dvc_cfg()
2406 *
2407 * Display an ADV_DVC_CFG structure.
2408 */
2409 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2410 {
2411 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2412
2413 printk(" disc_enable 0x%x, termination 0x%x\n",
2414 h->disc_enable, h->termination);
2415
2416 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2417 h->chip_version, h->mcode_date);
2418
2419 printk(" mcode_version 0x%x, control_flag 0x%x\n",
2420 h->mcode_version, h->control_flag);
2421 }
2422
2423 /*
2424 * asc_prt_scsi_host()
2425 */
2426 static void asc_prt_scsi_host(struct Scsi_Host *s)
2427 {
2428 struct asc_board *boardp = shost_priv(s);
2429
2430 printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
2431 printk(" host_busy %u, host_no %d,\n",
2432 atomic_read(&s->host_busy), s->host_no);
2433
2434 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2435 (ulong)s->base, (ulong)s->io_port, boardp->irq);
2436
2437 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2438 s->dma_channel, s->this_id, s->can_queue);
2439
2440 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2441 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2442
2443 if (ASC_NARROW_BOARD(boardp)) {
2444 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2445 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2446 } else {
2447 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2448 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2449 }
2450 }
2451
2452 /*
2453 * asc_prt_hex()
2454 *
2455 * Print hexadecimal output in 4 byte groupings 32 bytes
2456 * or 8 double-words per line.
2457 */
2458 static void asc_prt_hex(char *f, uchar *s, int l)
2459 {
2460 int i;
2461 int j;
2462 int k;
2463 int m;
2464
2465 printk("%s: (%d bytes)\n", f, l);
2466
2467 for (i = 0; i < l; i += 32) {
2468
2469 /* Display a maximum of 8 double-words per line. */
2470 if ((k = (l - i) / 4) >= 8) {
2471 k = 8;
2472 m = 0;
2473 } else {
2474 m = (l - i) % 4;
2475 }
2476
2477 for (j = 0; j < k; j++) {
2478 printk(" %2.2X%2.2X%2.2X%2.2X",
2479 (unsigned)s[i + (j * 4)],
2480 (unsigned)s[i + (j * 4) + 1],
2481 (unsigned)s[i + (j * 4) + 2],
2482 (unsigned)s[i + (j * 4) + 3]);
2483 }
2484
2485 switch (m) {
2486 case 0:
2487 default:
2488 break;
2489 case 1:
2490 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2491 break;
2492 case 2:
2493 printk(" %2.2X%2.2X",
2494 (unsigned)s[i + (j * 4)],
2495 (unsigned)s[i + (j * 4) + 1]);
2496 break;
2497 case 3:
2498 printk(" %2.2X%2.2X%2.2X",
2499 (unsigned)s[i + (j * 4) + 1],
2500 (unsigned)s[i + (j * 4) + 2],
2501 (unsigned)s[i + (j * 4) + 3]);
2502 break;
2503 }
2504
2505 printk("\n");
2506 }
2507 }
2508
2509 /*
2510 * asc_prt_asc_scsi_q()
2511 */
2512 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2513 {
2514 ASC_SG_HEAD *sgp;
2515 int i;
2516
2517 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2518
2519 printk
2520 (" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n",
2521 q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag,
2522 q->q2.tag_code);
2523
2524 printk
2525 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2526 (ulong)le32_to_cpu(q->q1.data_addr),
2527 (ulong)le32_to_cpu(q->q1.data_cnt),
2528 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2529
2530 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2531 (ulong)q->cdbptr, q->q2.cdb_len,
2532 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2533
2534 if (q->sg_head) {
2535 sgp = q->sg_head;
2536 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2537 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2538 sgp->queue_cnt);
2539 for (i = 0; i < sgp->entry_cnt; i++) {
2540 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2541 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2542 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2543 }
2544
2545 }
2546 }
2547
2548 /*
2549 * asc_prt_asc_qdone_info()
2550 */
2551 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2552 {
2553 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2554 printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n",
2555 q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len,
2556 q->d2.tag_code);
2557 printk
2558 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2559 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2560 }
2561
2562 /*
2563 * asc_prt_adv_sgblock()
2564 *
2565 * Display an ADV_SG_BLOCK structure.
2566 */
2567 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2568 {
2569 int i;
2570
2571 printk(" ADV_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2572 (ulong)b, sgblockno);
2573 printk(" sg_cnt %u, sg_ptr 0x%x\n",
2574 b->sg_cnt, (u32)le32_to_cpu(b->sg_ptr));
2575 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2576 if (b->sg_ptr != 0)
2577 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2578 for (i = 0; i < b->sg_cnt; i++) {
2579 printk(" [%u]: sg_addr 0x%x, sg_count 0x%x\n",
2580 i, (u32)le32_to_cpu(b->sg_list[i].sg_addr),
2581 (u32)le32_to_cpu(b->sg_list[i].sg_count));
2582 }
2583 }
2584
2585 /*
2586 * asc_prt_adv_scsi_req_q()
2587 *
2588 * Display an ADV_SCSI_REQ_Q structure.
2589 */
2590 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2591 {
2592 int sg_blk_cnt;
2593 struct adv_sg_block *sg_ptr;
2594 adv_sgblk_t *sgblkp;
2595
2596 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2597
2598 printk(" target_id %u, target_lun %u, srb_tag 0x%x\n",
2599 q->target_id, q->target_lun, q->srb_tag);
2600
2601 printk(" cntl 0x%x, data_addr 0x%lx\n",
2602 q->cntl, (ulong)le32_to_cpu(q->data_addr));
2603
2604 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2605 (ulong)le32_to_cpu(q->data_cnt),
2606 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2607
2608 printk
2609 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2610 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2611
2612 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2613 q->sg_working_ix, q->target_cmd);
2614
2615 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2616 (ulong)le32_to_cpu(q->scsiq_rptr),
2617 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2618
2619 /* Display the request's ADV_SG_BLOCK structures. */
2620 if (q->sg_list_ptr != NULL) {
2621 sgblkp = container_of(q->sg_list_ptr, adv_sgblk_t, sg_block);
2622 sg_blk_cnt = 0;
2623 while (sgblkp) {
2624 sg_ptr = &sgblkp->sg_block;
2625 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2626 if (sg_ptr->sg_ptr == 0) {
2627 break;
2628 }
2629 sgblkp = sgblkp->next_sgblkp;
2630 sg_blk_cnt++;
2631 }
2632 }
2633 }
2634 #endif /* ADVANSYS_DEBUG */
2635
2636 /*
2637 * advansys_info()
2638 *
2639 * Return suitable for printing on the console with the argument
2640 * adapter's configuration information.
2641 *
2642 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2643 * otherwise the static 'info' array will be overrun.
2644 */
2645 static const char *advansys_info(struct Scsi_Host *shost)
2646 {
2647 static char info[ASC_INFO_SIZE];
2648 struct asc_board *boardp = shost_priv(shost);
2649 ASC_DVC_VAR *asc_dvc_varp;
2650 ADV_DVC_VAR *adv_dvc_varp;
2651 char *busname;
2652 char *widename = NULL;
2653
2654 if (ASC_NARROW_BOARD(boardp)) {
2655 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2656 ASC_DBG(1, "begin\n");
2657 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2658 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2659 ASC_IS_ISAPNP) {
2660 busname = "ISA PnP";
2661 } else {
2662 busname = "ISA";
2663 }
2664 sprintf(info,
2665 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2666 ASC_VERSION, busname,
2667 (ulong)shost->io_port,
2668 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2669 boardp->irq, shost->dma_channel);
2670 } else {
2671 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2672 busname = "VL";
2673 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2674 busname = "EISA";
2675 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2676 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2677 == ASC_IS_PCI_ULTRA) {
2678 busname = "PCI Ultra";
2679 } else {
2680 busname = "PCI";
2681 }
2682 } else {
2683 busname = "?";
2684 shost_printk(KERN_ERR, shost, "unknown bus "
2685 "type %d\n", asc_dvc_varp->bus_type);
2686 }
2687 sprintf(info,
2688 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2689 ASC_VERSION, busname, (ulong)shost->io_port,
2690 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2691 boardp->irq);
2692 }
2693 } else {
2694 /*
2695 * Wide Adapter Information
2696 *
2697 * Memory-mapped I/O is used instead of I/O space to access
2698 * the adapter, but display the I/O Port range. The Memory
2699 * I/O address is displayed through the driver /proc file.
2700 */
2701 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2702 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2703 widename = "Ultra-Wide";
2704 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2705 widename = "Ultra2-Wide";
2706 } else {
2707 widename = "Ultra3-Wide";
2708 }
2709 sprintf(info,
2710 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2711 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2712 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2713 }
2714 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2715 ASC_DBG(1, "end\n");
2716 return info;
2717 }
2718
2719 #ifdef CONFIG_PROC_FS
2720
2721 /*
2722 * asc_prt_board_devices()
2723 *
2724 * Print driver information for devices attached to the board.
2725 */
2726 static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
2727 {
2728 struct asc_board *boardp = shost_priv(shost);
2729 int chip_scsi_id;
2730 int i;
2731
2732 seq_printf(m,
2733 "\nDevice Information for AdvanSys SCSI Host %d:\n",
2734 shost->host_no);
2735
2736 if (ASC_NARROW_BOARD(boardp)) {
2737 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2738 } else {
2739 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2740 }
2741
2742 seq_puts(m, "Target IDs Detected:");
2743 for (i = 0; i <= ADV_MAX_TID; i++) {
2744 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2745 seq_printf(m, " %X,", i);
2746 }
2747 seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
2748 }
2749
2750 /*
2751 * Display Wide Board BIOS Information.
2752 */
2753 static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
2754 {
2755 struct asc_board *boardp = shost_priv(shost);
2756 ushort major, minor, letter;
2757
2758 seq_puts(m, "\nROM BIOS Version: ");
2759
2760 /*
2761 * If the BIOS saved a valid signature, then fill in
2762 * the BIOS code segment base address.
2763 */
2764 if (boardp->bios_signature != 0x55AA) {
2765 seq_puts(m, "Disabled or Pre-3.1\n"
2766 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"
2767 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2768 } else {
2769 major = (boardp->bios_version >> 12) & 0xF;
2770 minor = (boardp->bios_version >> 8) & 0xF;
2771 letter = (boardp->bios_version & 0xFF);
2772
2773 seq_printf(m, "%d.%d%c\n",
2774 major, minor,
2775 letter >= 26 ? '?' : letter + 'A');
2776 /*
2777 * Current available ROM BIOS release is 3.1I for UW
2778 * and 3.2I for U2W. This code doesn't differentiate
2779 * UW and U2W boards.
2780 */
2781 if (major < 3 || (major <= 3 && minor < 1) ||
2782 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
2783 seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"
2784 "ftp://ftp.connectcom.net/pub\n");
2785 }
2786 }
2787 }
2788
2789 /*
2790 * Add serial number to information bar if signature AAh
2791 * is found in at bit 15-9 (7 bits) of word 1.
2792 *
2793 * Serial Number consists fo 12 alpha-numeric digits.
2794 *
2795 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
2796 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
2797 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
2798 * 5 - Product revision (A-J) Word0: " "
2799 *
2800 * Signature Word1: 15-9 (7 bits)
2801 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2802 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
2803 *
2804 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
2805 *
2806 * Note 1: Only production cards will have a serial number.
2807 *
2808 * Note 2: Signature is most significant 7 bits (0xFE).
2809 *
2810 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
2811 */
2812 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
2813 {
2814 ushort w, num;
2815
2816 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2817 return ASC_FALSE;
2818 } else {
2819 /*
2820 * First word - 6 digits.
2821 */
2822 w = serialnum[0];
2823
2824 /* Product type - 1st digit. */
2825 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2826 /* Product type is P=Prototype */
2827 *cp += 0x8;
2828 }
2829 cp++;
2830
2831 /* Manufacturing location - 2nd digit. */
2832 *cp++ = 'A' + ((w & 0x1C00) >> 10);
2833
2834 /* Product ID - 3rd, 4th digits. */
2835 num = w & 0x3FF;
2836 *cp++ = '0' + (num / 100);
2837 num %= 100;
2838 *cp++ = '0' + (num / 10);
2839
2840 /* Product revision - 5th digit. */
2841 *cp++ = 'A' + (num % 10);
2842
2843 /*
2844 * Second word
2845 */
2846 w = serialnum[1];
2847
2848 /*
2849 * Year - 6th digit.
2850 *
2851 * If bit 15 of third word is set, then the
2852 * last digit of the year is greater than 7.
2853 */
2854 if (serialnum[2] & 0x8000) {
2855 *cp++ = '8' + ((w & 0x1C0) >> 6);
2856 } else {
2857 *cp++ = '0' + ((w & 0x1C0) >> 6);
2858 }
2859
2860 /* Week of year - 7th, 8th digits. */
2861 num = w & 0x003F;
2862 *cp++ = '0' + num / 10;
2863 num %= 10;
2864 *cp++ = '0' + num;
2865
2866 /*
2867 * Third word
2868 */
2869 w = serialnum[2] & 0x7FFF;
2870
2871 /* Serial number - 9th digit. */
2872 *cp++ = 'A' + (w / 1000);
2873
2874 /* 10th, 11th, 12th digits. */
2875 num = w % 1000;
2876 *cp++ = '0' + num / 100;
2877 num %= 100;
2878 *cp++ = '0' + num / 10;
2879 num %= 10;
2880 *cp++ = '0' + num;
2881
2882 *cp = '\0'; /* Null Terminate the string. */
2883 return ASC_TRUE;
2884 }
2885 }
2886
2887 /*
2888 * asc_prt_asc_board_eeprom()
2889 *
2890 * Print board EEPROM configuration.
2891 */
2892 static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
2893 {
2894 struct asc_board *boardp = shost_priv(shost);
2895 ASC_DVC_VAR *asc_dvc_varp;
2896 ASCEEP_CONFIG *ep;
2897 int i;
2898 #ifdef CONFIG_ISA
2899 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
2900 #endif /* CONFIG_ISA */
2901 uchar serialstr[13];
2902
2903 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2904 ep = &boardp->eep_config.asc_eep;
2905
2906 seq_printf(m,
2907 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
2908 shost->host_no);
2909
2910 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
2911 == ASC_TRUE)
2912 seq_printf(m, " Serial Number: %s\n", serialstr);
2913 else if (ep->adapter_info[5] == 0xBB)
2914 seq_puts(m,
2915 " Default Settings Used for EEPROM-less Adapter.\n");
2916 else
2917 seq_puts(m, " Serial Number Signature Not Present.\n");
2918
2919 seq_printf(m,
2920 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2921 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
2922 ep->max_tag_qng);
2923
2924 seq_printf(m,
2925 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
2926
2927 seq_puts(m, " Target ID: ");
2928 for (i = 0; i <= ASC_MAX_TID; i++)
2929 seq_printf(m, " %d", i);
2930
2931 seq_puts(m, "\n Disconnects: ");
2932 for (i = 0; i <= ASC_MAX_TID; i++)
2933 seq_printf(m, " %c",
2934 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2935
2936 seq_puts(m, "\n Command Queuing: ");
2937 for (i = 0; i <= ASC_MAX_TID; i++)
2938 seq_printf(m, " %c",
2939 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2940
2941 seq_puts(m, "\n Start Motor: ");
2942 for (i = 0; i <= ASC_MAX_TID; i++)
2943 seq_printf(m, " %c",
2944 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2945
2946 seq_puts(m, "\n Synchronous Transfer:");
2947 for (i = 0; i <= ASC_MAX_TID; i++)
2948 seq_printf(m, " %c",
2949 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2950 seq_putc(m, '\n');
2951
2952 #ifdef CONFIG_ISA
2953 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2954 seq_printf(m,
2955 " Host ISA DMA speed: %d MB/S\n",
2956 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
2957 }
2958 #endif /* CONFIG_ISA */
2959 }
2960
2961 /*
2962 * asc_prt_adv_board_eeprom()
2963 *
2964 * Print board EEPROM configuration.
2965 */
2966 static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
2967 {
2968 struct asc_board *boardp = shost_priv(shost);
2969 ADV_DVC_VAR *adv_dvc_varp;
2970 int i;
2971 char *termstr;
2972 uchar serialstr[13];
2973 ADVEEP_3550_CONFIG *ep_3550 = NULL;
2974 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
2975 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
2976 ushort word;
2977 ushort *wordp;
2978 ushort sdtr_speed = 0;
2979
2980 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2981 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2982 ep_3550 = &boardp->eep_config.adv_3550_eep;
2983 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2984 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
2985 } else {
2986 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
2987 }
2988
2989 seq_printf(m,
2990 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
2991 shost->host_no);
2992
2993 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2994 wordp = &ep_3550->serial_number_word1;
2995 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2996 wordp = &ep_38C0800->serial_number_word1;
2997 } else {
2998 wordp = &ep_38C1600->serial_number_word1;
2999 }
3000
3001 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
3002 seq_printf(m, " Serial Number: %s\n", serialstr);
3003 else
3004 seq_puts(m, " Serial Number Signature Not Present.\n");
3005
3006 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3007 seq_printf(m,
3008 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3009 ep_3550->adapter_scsi_id,
3010 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3011 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3012 seq_printf(m,
3013 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3014 ep_38C0800->adapter_scsi_id,
3015 ep_38C0800->max_host_qng,
3016 ep_38C0800->max_dvc_qng);
3017 else
3018 seq_printf(m,
3019 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3020 ep_38C1600->adapter_scsi_id,
3021 ep_38C1600->max_host_qng,
3022 ep_38C1600->max_dvc_qng);
3023 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3024 word = ep_3550->termination;
3025 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3026 word = ep_38C0800->termination_lvd;
3027 } else {
3028 word = ep_38C1600->termination_lvd;
3029 }
3030 switch (word) {
3031 case 1:
3032 termstr = "Low Off/High Off";
3033 break;
3034 case 2:
3035 termstr = "Low Off/High On";
3036 break;
3037 case 3:
3038 termstr = "Low On/High On";
3039 break;
3040 default:
3041 case 0:
3042 termstr = "Automatic";
3043 break;
3044 }
3045
3046 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3047 seq_printf(m,
3048 " termination: %u (%s), bios_ctrl: 0x%x\n",
3049 ep_3550->termination, termstr,
3050 ep_3550->bios_ctrl);
3051 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3052 seq_printf(m,
3053 " termination: %u (%s), bios_ctrl: 0x%x\n",
3054 ep_38C0800->termination_lvd, termstr,
3055 ep_38C0800->bios_ctrl);
3056 else
3057 seq_printf(m,
3058 " termination: %u (%s), bios_ctrl: 0x%x\n",
3059 ep_38C1600->termination_lvd, termstr,
3060 ep_38C1600->bios_ctrl);
3061
3062 seq_puts(m, " Target ID: ");
3063 for (i = 0; i <= ADV_MAX_TID; i++)
3064 seq_printf(m, " %X", i);
3065 seq_putc(m, '\n');
3066
3067 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3068 word = ep_3550->disc_enable;
3069 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3070 word = ep_38C0800->disc_enable;
3071 } else {
3072 word = ep_38C1600->disc_enable;
3073 }
3074 seq_puts(m, " Disconnects: ");
3075 for (i = 0; i <= ADV_MAX_TID; i++)
3076 seq_printf(m, " %c",
3077 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3078 seq_putc(m, '\n');
3079
3080 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3081 word = ep_3550->tagqng_able;
3082 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3083 word = ep_38C0800->tagqng_able;
3084 } else {
3085 word = ep_38C1600->tagqng_able;
3086 }
3087 seq_puts(m, " Command Queuing: ");
3088 for (i = 0; i <= ADV_MAX_TID; i++)
3089 seq_printf(m, " %c",
3090 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3091 seq_putc(m, '\n');
3092
3093 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3094 word = ep_3550->start_motor;
3095 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3096 word = ep_38C0800->start_motor;
3097 } else {
3098 word = ep_38C1600->start_motor;
3099 }
3100 seq_puts(m, " Start Motor: ");
3101 for (i = 0; i <= ADV_MAX_TID; i++)
3102 seq_printf(m, " %c",
3103 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3104 seq_putc(m, '\n');
3105
3106 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3107 seq_puts(m, " Synchronous Transfer:");
3108 for (i = 0; i <= ADV_MAX_TID; i++)
3109 seq_printf(m, " %c",
3110 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3111 'Y' : 'N');
3112 seq_putc(m, '\n');
3113 }
3114
3115 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3116 seq_puts(m, " Ultra Transfer: ");
3117 for (i = 0; i <= ADV_MAX_TID; i++)
3118 seq_printf(m, " %c",
3119 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3120 ? 'Y' : 'N');
3121 seq_putc(m, '\n');
3122 }
3123
3124 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3125 word = ep_3550->wdtr_able;
3126 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3127 word = ep_38C0800->wdtr_able;
3128 } else {
3129 word = ep_38C1600->wdtr_able;
3130 }
3131 seq_puts(m, " Wide Transfer: ");
3132 for (i = 0; i <= ADV_MAX_TID; i++)
3133 seq_printf(m, " %c",
3134 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3135 seq_putc(m, '\n');
3136
3137 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3138 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3139 seq_puts(m, " Synchronous Transfer Speed (Mhz):\n ");
3140 for (i = 0; i <= ADV_MAX_TID; i++) {
3141 char *speed_str;
3142
3143 if (i == 0) {
3144 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3145 } else if (i == 4) {
3146 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3147 } else if (i == 8) {
3148 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3149 } else if (i == 12) {
3150 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3151 }
3152 switch (sdtr_speed & ADV_MAX_TID) {
3153 case 0:
3154 speed_str = "Off";
3155 break;
3156 case 1:
3157 speed_str = " 5";
3158 break;
3159 case 2:
3160 speed_str = " 10";
3161 break;
3162 case 3:
3163 speed_str = " 20";
3164 break;
3165 case 4:
3166 speed_str = " 40";
3167 break;
3168 case 5:
3169 speed_str = " 80";
3170 break;
3171 default:
3172 speed_str = "Unk";
3173 break;
3174 }
3175 seq_printf(m, "%X:%s ", i, speed_str);
3176 if (i == 7)
3177 seq_puts(m, "\n ");
3178 sdtr_speed >>= 4;
3179 }
3180 seq_putc(m, '\n');
3181 }
3182 }
3183
3184 /*
3185 * asc_prt_driver_conf()
3186 */
3187 static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
3188 {
3189 struct asc_board *boardp = shost_priv(shost);
3190 int chip_scsi_id;
3191
3192 seq_printf(m,
3193 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3194 shost->host_no);
3195
3196 seq_printf(m,
3197 " host_busy %u, max_id %u, max_lun %llu, max_channel %u\n",
3198 atomic_read(&shost->host_busy), shost->max_id,
3199 shost->max_lun, shost->max_channel);
3200
3201 seq_printf(m,
3202 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3203 shost->unique_id, shost->can_queue, shost->this_id,
3204 shost->sg_tablesize, shost->cmd_per_lun);
3205
3206 seq_printf(m,
3207 " unchecked_isa_dma %d, use_clustering %d\n",
3208 shost->unchecked_isa_dma, shost->use_clustering);
3209
3210 seq_printf(m,
3211 " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
3212 boardp->flags, shost->last_reset, jiffies,
3213 boardp->asc_n_io_port);
3214
3215 seq_printf(m, " io_port 0x%lx\n", shost->io_port);
3216
3217 if (ASC_NARROW_BOARD(boardp)) {
3218 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3219 } else {
3220 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3221 }
3222 }
3223
3224 /*
3225 * asc_prt_asc_board_info()
3226 *
3227 * Print dynamic board configuration information.
3228 */
3229 static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
3230 {
3231 struct asc_board *boardp = shost_priv(shost);
3232 int chip_scsi_id;
3233 ASC_DVC_VAR *v;
3234 ASC_DVC_CFG *c;
3235 int i;
3236 int renegotiate = 0;
3237
3238 v = &boardp->dvc_var.asc_dvc_var;
3239 c = &boardp->dvc_cfg.asc_dvc_cfg;
3240 chip_scsi_id = c->chip_scsi_id;
3241
3242 seq_printf(m,
3243 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3244 shost->host_no);
3245
3246 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3247 "mcode_version 0x%x, err_code %u\n",
3248 c->chip_version, c->mcode_date, c->mcode_version,
3249 v->err_code);
3250
3251 /* Current number of commands waiting for the host. */
3252 seq_printf(m,
3253 " Total Command Pending: %d\n", v->cur_total_qng);
3254
3255 seq_puts(m, " Command Queuing:");
3256 for (i = 0; i <= ASC_MAX_TID; i++) {
3257 if ((chip_scsi_id == i) ||
3258 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3259 continue;
3260 }
3261 seq_printf(m, " %X:%c",
3262 i,
3263 (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3264 }
3265
3266 /* Current number of commands waiting for a device. */
3267 seq_puts(m, "\n Command Queue Pending:");
3268 for (i = 0; i <= ASC_MAX_TID; i++) {
3269 if ((chip_scsi_id == i) ||
3270 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3271 continue;
3272 }
3273 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
3274 }
3275
3276 /* Current limit on number of commands that can be sent to a device. */
3277 seq_puts(m, "\n Command Queue Limit:");
3278 for (i = 0; i <= ASC_MAX_TID; i++) {
3279 if ((chip_scsi_id == i) ||
3280 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3281 continue;
3282 }
3283 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
3284 }
3285
3286 /* Indicate whether the device has returned queue full status. */
3287 seq_puts(m, "\n Command Queue Full:");
3288 for (i = 0; i <= ASC_MAX_TID; i++) {
3289 if ((chip_scsi_id == i) ||
3290 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3291 continue;
3292 }
3293 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3294 seq_printf(m, " %X:Y-%d",
3295 i, boardp->queue_full_cnt[i]);
3296 else
3297 seq_printf(m, " %X:N", i);
3298 }
3299
3300 seq_puts(m, "\n Synchronous Transfer:");
3301 for (i = 0; i <= ASC_MAX_TID; i++) {
3302 if ((chip_scsi_id == i) ||
3303 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3304 continue;
3305 }
3306 seq_printf(m, " %X:%c",
3307 i,
3308 (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3309 }
3310 seq_putc(m, '\n');
3311
3312 for (i = 0; i <= ASC_MAX_TID; i++) {
3313 uchar syn_period_ix;
3314
3315 if ((chip_scsi_id == i) ||
3316 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3317 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3318 continue;
3319 }
3320
3321 seq_printf(m, " %X:", i);
3322
3323 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3324 seq_puts(m, " Asynchronous");
3325 } else {
3326 syn_period_ix =
3327 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3328 1);
3329
3330 seq_printf(m,
3331 " Transfer Period Factor: %d (%d.%d Mhz),",
3332 v->sdtr_period_tbl[syn_period_ix],
3333 250 / v->sdtr_period_tbl[syn_period_ix],
3334 ASC_TENTHS(250,
3335 v->sdtr_period_tbl[syn_period_ix]));
3336
3337 seq_printf(m, " REQ/ACK Offset: %d",
3338 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3339 }
3340
3341 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3342 seq_puts(m, "*\n");
3343 renegotiate = 1;
3344 } else {
3345 seq_putc(m, '\n');
3346 }
3347 }
3348
3349 if (renegotiate) {
3350 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3351 }
3352 }
3353
3354 /*
3355 * asc_prt_adv_board_info()
3356 *
3357 * Print dynamic board configuration information.
3358 */
3359 static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
3360 {
3361 struct asc_board *boardp = shost_priv(shost);
3362 int i;
3363 ADV_DVC_VAR *v;
3364 ADV_DVC_CFG *c;
3365 AdvPortAddr iop_base;
3366 ushort chip_scsi_id;
3367 ushort lramword;
3368 uchar lrambyte;
3369 ushort tagqng_able;
3370 ushort sdtr_able, wdtr_able;
3371 ushort wdtr_done, sdtr_done;
3372 ushort period = 0;
3373 int renegotiate = 0;
3374
3375 v = &boardp->dvc_var.adv_dvc_var;
3376 c = &boardp->dvc_cfg.adv_dvc_cfg;
3377 iop_base = v->iop_base;
3378 chip_scsi_id = v->chip_scsi_id;
3379
3380 seq_printf(m,
3381 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3382 shost->host_no);
3383
3384 seq_printf(m,
3385 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3386 (unsigned long)v->iop_base,
3387 AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3388 v->err_code);
3389
3390 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3391 "mcode_version 0x%x\n", c->chip_version,
3392 c->mcode_date, c->mcode_version);
3393
3394 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3395 seq_puts(m, " Queuing Enabled:");
3396 for (i = 0; i <= ADV_MAX_TID; i++) {
3397 if ((chip_scsi_id == i) ||
3398 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3399 continue;
3400 }
3401
3402 seq_printf(m, " %X:%c",
3403 i,
3404 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3405 }
3406
3407 seq_puts(m, "\n Queue Limit:");
3408 for (i = 0; i <= ADV_MAX_TID; i++) {
3409 if ((chip_scsi_id == i) ||
3410 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3411 continue;
3412 }
3413
3414 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3415 lrambyte);
3416
3417 seq_printf(m, " %X:%d", i, lrambyte);
3418 }
3419
3420 seq_puts(m, "\n Command Pending:");
3421 for (i = 0; i <= ADV_MAX_TID; i++) {
3422 if ((chip_scsi_id == i) ||
3423 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3424 continue;
3425 }
3426
3427 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3428 lrambyte);
3429
3430 seq_printf(m, " %X:%d", i, lrambyte);
3431 }
3432 seq_putc(m, '\n');
3433
3434 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3435 seq_puts(m, " Wide Enabled:");
3436 for (i = 0; i <= ADV_MAX_TID; i++) {
3437 if ((chip_scsi_id == i) ||
3438 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3439 continue;
3440 }
3441
3442 seq_printf(m, " %X:%c",
3443 i,
3444 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3445 }
3446 seq_putc(m, '\n');
3447
3448 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3449 seq_puts(m, " Transfer Bit Width:");
3450 for (i = 0; i <= ADV_MAX_TID; i++) {
3451 if ((chip_scsi_id == i) ||
3452 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3453 continue;
3454 }
3455
3456 AdvReadWordLram(iop_base,
3457 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3458 lramword);
3459
3460 seq_printf(m, " %X:%d",
3461 i, (lramword & 0x8000) ? 16 : 8);
3462
3463 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3464 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3465 seq_putc(m, '*');
3466 renegotiate = 1;
3467 }
3468 }
3469 seq_putc(m, '\n');
3470
3471 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3472 seq_puts(m, " Synchronous Enabled:");
3473 for (i = 0; i <= ADV_MAX_TID; i++) {
3474 if ((chip_scsi_id == i) ||
3475 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3476 continue;
3477 }
3478
3479 seq_printf(m, " %X:%c",
3480 i,
3481 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3482 }
3483 seq_putc(m, '\n');
3484
3485 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3486 for (i = 0; i <= ADV_MAX_TID; i++) {
3487
3488 AdvReadWordLram(iop_base,
3489 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3490 lramword);
3491 lramword &= ~0x8000;
3492
3493 if ((chip_scsi_id == i) ||
3494 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3495 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3496 continue;
3497 }
3498
3499 seq_printf(m, " %X:", i);
3500
3501 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
3502 seq_puts(m, " Asynchronous");
3503 } else {
3504 seq_puts(m, " Transfer Period Factor: ");
3505
3506 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
3507 seq_puts(m, "9 (80.0 Mhz),");
3508 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
3509 seq_puts(m, "10 (40.0 Mhz),");
3510 } else { /* 20 Mhz or below. */
3511
3512 period = (((lramword >> 8) * 25) + 50) / 4;
3513
3514 if (period == 0) { /* Should never happen. */
3515 seq_printf(m, "%d (? Mhz), ", period);
3516 } else {
3517 seq_printf(m,
3518 "%d (%d.%d Mhz),",
3519 period, 250 / period,
3520 ASC_TENTHS(250, period));
3521 }
3522 }
3523
3524 seq_printf(m, " REQ/ACK Offset: %d",
3525 lramword & 0x1F);
3526 }
3527
3528 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3529 seq_puts(m, "*\n");
3530 renegotiate = 1;
3531 } else {
3532 seq_putc(m, '\n');
3533 }
3534 }
3535
3536 if (renegotiate) {
3537 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3538 }
3539 }
3540
3541 #ifdef ADVANSYS_STATS
3542 /*
3543 * asc_prt_board_stats()
3544 */
3545 static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
3546 {
3547 struct asc_board *boardp = shost_priv(shost);
3548 struct asc_stats *s = &boardp->asc_stats;
3549
3550 seq_printf(m,
3551 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3552 shost->host_no);
3553
3554 seq_printf(m,
3555 " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
3556 s->queuecommand, s->reset, s->biosparam,
3557 s->interrupt);
3558
3559 seq_printf(m,
3560 " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
3561 s->callback, s->done, s->build_error,
3562 s->adv_build_noreq, s->adv_build_nosg);
3563
3564 seq_printf(m,
3565 " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
3566 s->exe_noerror, s->exe_busy, s->exe_error,
3567 s->exe_unknown);
3568
3569 /*
3570 * Display data transfer statistics.
3571 */
3572 if (s->xfer_cnt > 0) {
3573 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
3574 s->xfer_cnt, s->xfer_elem);
3575
3576 seq_printf(m, "xfer_bytes %u.%01u kb\n",
3577 s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
3578
3579 /* Scatter gather transfer statistics */
3580 seq_printf(m, " avg_num_elem %u.%01u, ",
3581 s->xfer_elem / s->xfer_cnt,
3582 ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
3583
3584 seq_printf(m, "avg_elem_size %u.%01u kb, ",
3585 (s->xfer_sect / 2) / s->xfer_elem,
3586 ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
3587
3588 seq_printf(m, "avg_xfer_size %u.%01u kb\n",
3589 (s->xfer_sect / 2) / s->xfer_cnt,
3590 ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
3591 }
3592 }
3593 #endif /* ADVANSYS_STATS */
3594
3595 /*
3596 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
3597 *
3598 * m: seq_file to print into
3599 * shost: Scsi_Host
3600 *
3601 * Return the number of bytes read from or written to a
3602 * /proc/scsi/advansys/[0...] file.
3603 */
3604 static int
3605 advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
3606 {
3607 struct asc_board *boardp = shost_priv(shost);
3608
3609 ASC_DBG(1, "begin\n");
3610
3611 /*
3612 * User read of /proc/scsi/advansys/[0...] file.
3613 */
3614
3615 /*
3616 * Get board configuration information.
3617 *
3618 * advansys_info() returns the board string from its own static buffer.
3619 */
3620 /* Copy board information. */
3621 seq_printf(m, "%s\n", (char *)advansys_info(shost));
3622 /*
3623 * Display Wide Board BIOS Information.
3624 */
3625 if (!ASC_NARROW_BOARD(boardp))
3626 asc_prt_adv_bios(m, shost);
3627
3628 /*
3629 * Display driver information for each device attached to the board.
3630 */
3631 asc_prt_board_devices(m, shost);
3632
3633 /*
3634 * Display EEPROM configuration for the board.
3635 */
3636 if (ASC_NARROW_BOARD(boardp))
3637 asc_prt_asc_board_eeprom(m, shost);
3638 else
3639 asc_prt_adv_board_eeprom(m, shost);
3640
3641 /*
3642 * Display driver configuration and information for the board.
3643 */
3644 asc_prt_driver_conf(m, shost);
3645
3646 #ifdef ADVANSYS_STATS
3647 /*
3648 * Display driver statistics for the board.
3649 */
3650 asc_prt_board_stats(m, shost);
3651 #endif /* ADVANSYS_STATS */
3652
3653 /*
3654 * Display Asc Library dynamic configuration information
3655 * for the board.
3656 */
3657 if (ASC_NARROW_BOARD(boardp))
3658 asc_prt_asc_board_info(m, shost);
3659 else
3660 asc_prt_adv_board_info(m, shost);
3661 return 0;
3662 }
3663 #endif /* CONFIG_PROC_FS */
3664
3665 static void asc_scsi_done(struct scsi_cmnd *scp)
3666 {
3667 scsi_dma_unmap(scp);
3668 ASC_STATS(scp->device->host, done);
3669 scp->scsi_done(scp);
3670 }
3671
3672 static void AscSetBank(PortAddr iop_base, uchar bank)
3673 {
3674 uchar val;
3675
3676 val = AscGetChipControl(iop_base) &
3677 (~
3678 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3679 CC_CHIP_RESET));
3680 if (bank == 1) {
3681 val |= CC_BANK_ONE;
3682 } else if (bank == 2) {
3683 val |= CC_DIAG | CC_BANK_ONE;
3684 } else {
3685 val &= ~CC_BANK_ONE;
3686 }
3687 AscSetChipControl(iop_base, val);
3688 }
3689
3690 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3691 {
3692 AscSetBank(iop_base, 1);
3693 AscWriteChipIH(iop_base, ins_code);
3694 AscSetBank(iop_base, 0);
3695 }
3696
3697 static int AscStartChip(PortAddr iop_base)
3698 {
3699 AscSetChipControl(iop_base, 0);
3700 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3701 return (0);
3702 }
3703 return (1);
3704 }
3705
3706 static bool AscStopChip(PortAddr iop_base)
3707 {
3708 uchar cc_val;
3709
3710 cc_val =
3711 AscGetChipControl(iop_base) &
3712 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3713 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3714 AscSetChipIH(iop_base, INS_HALT);
3715 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3716 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
3717 return false;
3718 }
3719 return true;
3720 }
3721
3722 static bool AscIsChipHalted(PortAddr iop_base)
3723 {
3724 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3725 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
3726 return true;
3727 }
3728 }
3729 return false;
3730 }
3731
3732 static bool AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
3733 {
3734 PortAddr iop_base;
3735 int i = 10;
3736
3737 iop_base = asc_dvc->iop_base;
3738 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3739 && (i-- > 0)) {
3740 mdelay(100);
3741 }
3742 AscStopChip(iop_base);
3743 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3744 udelay(60);
3745 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3746 AscSetChipIH(iop_base, INS_HALT);
3747 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3748 AscSetChipControl(iop_base, CC_HALT);
3749 mdelay(200);
3750 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3751 AscSetChipStatus(iop_base, 0);
3752 return (AscIsChipHalted(iop_base));
3753 }
3754
3755 static int AscFindSignature(PortAddr iop_base)
3756 {
3757 ushort sig_word;
3758
3759 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
3760 iop_base, AscGetChipSignatureByte(iop_base));
3761 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
3762 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
3763 iop_base, AscGetChipSignatureWord(iop_base));
3764 sig_word = AscGetChipSignatureWord(iop_base);
3765 if ((sig_word == (ushort)ASC_1000_ID0W) ||
3766 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3767 return (1);
3768 }
3769 }
3770 return (0);
3771 }
3772
3773 static void AscEnableInterrupt(PortAddr iop_base)
3774 {
3775 ushort cfg;
3776
3777 cfg = AscGetChipCfgLsw(iop_base);
3778 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
3779 }
3780
3781 static void AscDisableInterrupt(PortAddr iop_base)
3782 {
3783 ushort cfg;
3784
3785 cfg = AscGetChipCfgLsw(iop_base);
3786 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
3787 }
3788
3789 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3790 {
3791 unsigned char byte_data;
3792 unsigned short word_data;
3793
3794 if (isodd_word(addr)) {
3795 AscSetChipLramAddr(iop_base, addr - 1);
3796 word_data = AscGetChipLramData(iop_base);
3797 byte_data = (word_data >> 8) & 0xFF;
3798 } else {
3799 AscSetChipLramAddr(iop_base, addr);
3800 word_data = AscGetChipLramData(iop_base);
3801 byte_data = word_data & 0xFF;
3802 }
3803 return byte_data;
3804 }
3805
3806 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3807 {
3808 ushort word_data;
3809
3810 AscSetChipLramAddr(iop_base, addr);
3811 word_data = AscGetChipLramData(iop_base);
3812 return (word_data);
3813 }
3814
3815 static void
3816 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3817 {
3818 int i;
3819
3820 AscSetChipLramAddr(iop_base, s_addr);
3821 for (i = 0; i < words; i++) {
3822 AscSetChipLramData(iop_base, set_wval);
3823 }
3824 }
3825
3826 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
3827 {
3828 AscSetChipLramAddr(iop_base, addr);
3829 AscSetChipLramData(iop_base, word_val);
3830 }
3831
3832 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
3833 {
3834 ushort word_data;
3835
3836 if (isodd_word(addr)) {
3837 addr--;
3838 word_data = AscReadLramWord(iop_base, addr);
3839 word_data &= 0x00FF;
3840 word_data |= (((ushort)byte_val << 8) & 0xFF00);
3841 } else {
3842 word_data = AscReadLramWord(iop_base, addr);
3843 word_data &= 0xFF00;
3844 word_data |= ((ushort)byte_val & 0x00FF);
3845 }
3846 AscWriteLramWord(iop_base, addr, word_data);
3847 }
3848
3849 /*
3850 * Copy 2 bytes to LRAM.
3851 *
3852 * The source data is assumed to be in little-endian order in memory
3853 * and is maintained in little-endian order when written to LRAM.
3854 */
3855 static void
3856 AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
3857 const uchar *s_buffer, int words)
3858 {
3859 int i;
3860
3861 AscSetChipLramAddr(iop_base, s_addr);
3862 for (i = 0; i < 2 * words; i += 2) {
3863 /*
3864 * On a little-endian system the second argument below
3865 * produces a little-endian ushort which is written to
3866 * LRAM in little-endian order. On a big-endian system
3867 * the second argument produces a big-endian ushort which
3868 * is "transparently" byte-swapped by outpw() and written
3869 * in little-endian order to LRAM.
3870 */
3871 outpw(iop_base + IOP_RAM_DATA,
3872 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
3873 }
3874 }
3875
3876 /*
3877 * Copy 4 bytes to LRAM.
3878 *
3879 * The source data is assumed to be in little-endian order in memory
3880 * and is maintained in little-endian order when written to LRAM.
3881 */
3882 static void
3883 AscMemDWordCopyPtrToLram(PortAddr iop_base,
3884 ushort s_addr, uchar *s_buffer, int dwords)
3885 {
3886 int i;
3887
3888 AscSetChipLramAddr(iop_base, s_addr);
3889 for (i = 0; i < 4 * dwords; i += 4) {
3890 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
3891 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
3892 }
3893 }
3894
3895 /*
3896 * Copy 2 bytes from LRAM.
3897 *
3898 * The source data is assumed to be in little-endian order in LRAM
3899 * and is maintained in little-endian order when written to memory.
3900 */
3901 static void
3902 AscMemWordCopyPtrFromLram(PortAddr iop_base,
3903 ushort s_addr, uchar *d_buffer, int words)
3904 {
3905 int i;
3906 ushort word;
3907
3908 AscSetChipLramAddr(iop_base, s_addr);
3909 for (i = 0; i < 2 * words; i += 2) {
3910 word = inpw(iop_base + IOP_RAM_DATA);
3911 d_buffer[i] = word & 0xff;
3912 d_buffer[i + 1] = (word >> 8) & 0xff;
3913 }
3914 }
3915
3916 static u32 AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
3917 {
3918 u32 sum = 0;
3919 int i;
3920
3921 for (i = 0; i < words; i++, s_addr += 2) {
3922 sum += AscReadLramWord(iop_base, s_addr);
3923 }
3924 return (sum);
3925 }
3926
3927 static void AscInitLram(ASC_DVC_VAR *asc_dvc)
3928 {
3929 uchar i;
3930 ushort s_addr;
3931 PortAddr iop_base;
3932
3933 iop_base = asc_dvc->iop_base;
3934 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
3935 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
3936 64) >> 1));
3937 i = ASC_MIN_ACTIVE_QNO;
3938 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
3939 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3940 (uchar)(i + 1));
3941 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3942 (uchar)(asc_dvc->max_total_qng));
3943 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3944 (uchar)i);
3945 i++;
3946 s_addr += ASC_QBLK_SIZE;
3947 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
3948 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3949 (uchar)(i + 1));
3950 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3951 (uchar)(i - 1));
3952 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3953 (uchar)i);
3954 }
3955 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3956 (uchar)ASC_QLINK_END);
3957 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3958 (uchar)(asc_dvc->max_total_qng - 1));
3959 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3960 (uchar)asc_dvc->max_total_qng);
3961 i++;
3962 s_addr += ASC_QBLK_SIZE;
3963 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
3964 i++, s_addr += ASC_QBLK_SIZE) {
3965 AscWriteLramByte(iop_base,
3966 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
3967 AscWriteLramByte(iop_base,
3968 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
3969 AscWriteLramByte(iop_base,
3970 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
3971 }
3972 }
3973
3974 static u32
3975 AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
3976 const uchar *mcode_buf, ushort mcode_size)
3977 {
3978 u32 chksum;
3979 ushort mcode_word_size;
3980 ushort mcode_chksum;
3981
3982 /* Write the microcode buffer starting at LRAM address 0. */
3983 mcode_word_size = (ushort)(mcode_size >> 1);
3984 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
3985 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
3986
3987 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
3988 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
3989 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
3990 (ushort)ASC_CODE_SEC_BEG,
3991 (ushort)((mcode_size -
3992 s_addr - (ushort)
3993 ASC_CODE_SEC_BEG) /
3994 2));
3995 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
3996 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
3997 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
3998 return chksum;
3999 }
4000
4001 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
4002 {
4003 PortAddr iop_base;
4004 int i;
4005 ushort lram_addr;
4006
4007 iop_base = asc_dvc->iop_base;
4008 AscPutRiscVarFreeQHead(iop_base, 1);
4009 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4010 AscPutVarFreeQHead(iop_base, 1);
4011 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4012 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4013 (uchar)((int)asc_dvc->max_total_qng + 1));
4014 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4015 (uchar)((int)asc_dvc->max_total_qng + 2));
4016 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4017 asc_dvc->max_total_qng);
4018 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4019 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4020 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4021 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4022 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4023 AscPutQDoneInProgress(iop_base, 0);
4024 lram_addr = ASC_QADR_BEG;
4025 for (i = 0; i < 32; i++, lram_addr += 2) {
4026 AscWriteLramWord(iop_base, lram_addr, 0);
4027 }
4028 }
4029
4030 static int AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
4031 {
4032 int i;
4033 int warn_code;
4034 PortAddr iop_base;
4035 __le32 phy_addr;
4036 __le32 phy_size;
4037 struct asc_board *board = asc_dvc_to_board(asc_dvc);
4038
4039 iop_base = asc_dvc->iop_base;
4040 warn_code = 0;
4041 for (i = 0; i <= ASC_MAX_TID; i++) {
4042 AscPutMCodeInitSDTRAtID(iop_base, i,
4043 asc_dvc->cfg->sdtr_period_offset[i]);
4044 }
4045
4046 AscInitQLinkVar(asc_dvc);
4047 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4048 asc_dvc->cfg->disc_enable);
4049 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4050 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4051
4052 /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4053 BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4054 asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4055 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4056 if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4057 warn_code = -ENOMEM;
4058 goto err_dma_map;
4059 }
4060 phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
4061 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4062 (uchar *)&phy_addr, 1);
4063 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
4064 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4065 (uchar *)&phy_size, 1);
4066
4067 asc_dvc->cfg->mcode_date =
4068 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4069 asc_dvc->cfg->mcode_version =
4070 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4071
4072 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4073 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4074 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
4075 warn_code = -EINVAL;
4076 goto err_mcode_start;
4077 }
4078 if (AscStartChip(iop_base) != 1) {
4079 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
4080 warn_code = -EIO;
4081 goto err_mcode_start;
4082 }
4083
4084 return warn_code;
4085
4086 err_mcode_start:
4087 dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4088 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4089 err_dma_map:
4090 asc_dvc->overrun_dma = 0;
4091 return warn_code;
4092 }
4093
4094 static int AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4095 {
4096 const struct firmware *fw;
4097 const char fwname[] = "advansys/mcode.bin";
4098 int err;
4099 unsigned long chksum;
4100 int warn_code;
4101 PortAddr iop_base;
4102
4103 iop_base = asc_dvc->iop_base;
4104 warn_code = 0;
4105 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4106 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4107 AscResetChipAndScsiBus(asc_dvc);
4108 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4109 }
4110 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4111 if (asc_dvc->err_code != 0)
4112 return ASC_ERROR;
4113 if (!AscFindSignature(asc_dvc->iop_base)) {
4114 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4115 return warn_code;
4116 }
4117 AscDisableInterrupt(iop_base);
4118 AscInitLram(asc_dvc);
4119
4120 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4121 if (err) {
4122 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4123 fwname, err);
4124 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4125 return err;
4126 }
4127 if (fw->size < 4) {
4128 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4129 fw->size, fwname);
4130 release_firmware(fw);
4131 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4132 return -EINVAL;
4133 }
4134 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4135 (fw->data[1] << 8) | fw->data[0];
4136 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4137 if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4138 fw->size - 4) != chksum) {
4139 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4140 release_firmware(fw);
4141 return warn_code;
4142 }
4143 release_firmware(fw);
4144 warn_code |= AscInitMicroCodeVar(asc_dvc);
4145 if (!asc_dvc->overrun_dma)
4146 return warn_code;
4147 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4148 AscEnableInterrupt(iop_base);
4149 return warn_code;
4150 }
4151
4152 /*
4153 * Load the Microcode
4154 *
4155 * Write the microcode image to RISC memory starting at address 0.
4156 *
4157 * The microcode is stored compressed in the following format:
4158 *
4159 * 254 word (508 byte) table indexed by byte code followed
4160 * by the following byte codes:
4161 *
4162 * 1-Byte Code:
4163 * 00: Emit word 0 in table.
4164 * 01: Emit word 1 in table.
4165 * .
4166 * FD: Emit word 253 in table.
4167 *
4168 * Multi-Byte Code:
4169 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4170 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4171 *
4172 * Returns 0 or an error if the checksum doesn't match
4173 */
4174 static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4175 int size, int memsize, int chksum)
4176 {
4177 int i, j, end, len = 0;
4178 u32 sum;
4179
4180 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4181
4182 for (i = 253 * 2; i < size; i++) {
4183 if (buf[i] == 0xff) {
4184 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4185 for (j = 0; j < buf[i + 1]; j++) {
4186 AdvWriteWordAutoIncLram(iop_base, word);
4187 len += 2;
4188 }
4189 i += 3;
4190 } else if (buf[i] == 0xfe) {
4191 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4192 AdvWriteWordAutoIncLram(iop_base, word);
4193 i += 2;
4194 len += 2;
4195 } else {
4196 unsigned int off = buf[i] * 2;
4197 unsigned short word = (buf[off + 1] << 8) | buf[off];
4198 AdvWriteWordAutoIncLram(iop_base, word);
4199 len += 2;
4200 }
4201 }
4202
4203 end = len;
4204
4205 while (len < memsize) {
4206 AdvWriteWordAutoIncLram(iop_base, 0);
4207 len += 2;
4208 }
4209
4210 /* Verify the microcode checksum. */
4211 sum = 0;
4212 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4213
4214 for (len = 0; len < end; len += 2) {
4215 sum += AdvReadWordAutoIncLram(iop_base);
4216 }
4217
4218 if (sum != chksum)
4219 return ASC_IERR_MCODE_CHKSUM;
4220
4221 return 0;
4222 }
4223
4224 static void AdvBuildCarrierFreelist(struct adv_dvc_var *adv_dvc)
4225 {
4226 off_t carr_offset = 0, next_offset;
4227 dma_addr_t carr_paddr;
4228 int carr_num = ADV_CARRIER_BUFSIZE / sizeof(ADV_CARR_T), i;
4229
4230 for (i = 0; i < carr_num; i++) {
4231 carr_offset = i * sizeof(ADV_CARR_T);
4232 /* Get physical address of the carrier 'carrp'. */
4233 carr_paddr = adv_dvc->carrier_addr + carr_offset;
4234
4235 adv_dvc->carrier[i].carr_pa = cpu_to_le32(carr_paddr);
4236 adv_dvc->carrier[i].carr_va = cpu_to_le32(carr_offset);
4237 adv_dvc->carrier[i].areq_vpa = 0;
4238 next_offset = carr_offset + sizeof(ADV_CARR_T);
4239 if (i == carr_num)
4240 next_offset = ~0;
4241 adv_dvc->carrier[i].next_vpa = cpu_to_le32(next_offset);
4242 }
4243 /*
4244 * We cannot have a carrier with 'carr_va' of '0', as
4245 * a reference to this carrier would be interpreted as
4246 * list termination.
4247 * So start at carrier 1 with the freelist.
4248 */
4249 adv_dvc->carr_freelist = &adv_dvc->carrier[1];
4250 }
4251
4252 static ADV_CARR_T *adv_get_carrier(struct adv_dvc_var *adv_dvc, u32 offset)
4253 {
4254 int index;
4255
4256 BUG_ON(offset > ADV_CARRIER_BUFSIZE);
4257
4258 index = offset / sizeof(ADV_CARR_T);
4259 return &adv_dvc->carrier[index];
4260 }
4261
4262 static ADV_CARR_T *adv_get_next_carrier(struct adv_dvc_var *adv_dvc)
4263 {
4264 ADV_CARR_T *carrp = adv_dvc->carr_freelist;
4265 u32 next_vpa = le32_to_cpu(carrp->next_vpa);
4266
4267 if (next_vpa == 0 || next_vpa == ~0) {
4268 ASC_DBG(1, "invalid vpa offset 0x%x\n", next_vpa);
4269 return NULL;
4270 }
4271
4272 adv_dvc->carr_freelist = adv_get_carrier(adv_dvc, next_vpa);
4273 /*
4274 * insert stopper carrier to terminate list
4275 */
4276 carrp->next_vpa = cpu_to_le32(ADV_CQ_STOPPER);
4277
4278 return carrp;
4279 }
4280
4281 /*
4282 * 'offset' is the index in the request pointer array
4283 */
4284 static adv_req_t * adv_get_reqp(struct adv_dvc_var *adv_dvc, u32 offset)
4285 {
4286 struct asc_board *boardp = adv_dvc->drv_ptr;
4287
4288 BUG_ON(offset > adv_dvc->max_host_qng);
4289 return &boardp->adv_reqp[offset];
4290 }
4291
4292 /*
4293 * Send an idle command to the chip and wait for completion.
4294 *
4295 * Command completion is polled for once per microsecond.
4296 *
4297 * The function can be called from anywhere including an interrupt handler.
4298 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4299 * functions to prevent reentrancy.
4300 *
4301 * Return Values:
4302 * ADV_TRUE - command completed successfully
4303 * ADV_FALSE - command failed
4304 * ADV_ERROR - command timed out
4305 */
4306 static int
4307 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4308 ushort idle_cmd, u32 idle_cmd_parameter)
4309 {
4310 int result, i, j;
4311 AdvPortAddr iop_base;
4312
4313 iop_base = asc_dvc->iop_base;
4314
4315 /*
4316 * Clear the idle command status which is set by the microcode
4317 * to a non-zero value to indicate when the command is completed.
4318 * The non-zero result is one of the IDLE_CMD_STATUS_* values
4319 */
4320 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4321
4322 /*
4323 * Write the idle command value after the idle command parameter
4324 * has been written to avoid a race condition. If the order is not
4325 * followed, the microcode may process the idle command before the
4326 * parameters have been written to LRAM.
4327 */
4328 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4329 cpu_to_le32(idle_cmd_parameter));
4330 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4331
4332 /*
4333 * Tickle the RISC to tell it to process the idle command.
4334 */
4335 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4336 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4337 /*
4338 * Clear the tickle value. In the ASC-3550 the RISC flag
4339 * command 'clr_tickle_b' does not work unless the host
4340 * value is cleared.
4341 */
4342 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4343 }
4344
4345 /* Wait for up to 100 millisecond for the idle command to timeout. */
4346 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4347 /* Poll once each microsecond for command completion. */
4348 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4349 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4350 result);
4351 if (result != 0)
4352 return result;
4353 udelay(1);
4354 }
4355 }
4356
4357 BUG(); /* The idle command should never timeout. */
4358 return ADV_ERROR;
4359 }
4360
4361 /*
4362 * Reset SCSI Bus and purge all outstanding requests.
4363 *
4364 * Return Value:
4365 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
4366 * ADV_FALSE(0) - Microcode command failed.
4367 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4368 * may be hung which requires driver recovery.
4369 */
4370 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4371 {
4372 int status;
4373
4374 /*
4375 * Send the SCSI Bus Reset idle start idle command which asserts
4376 * the SCSI Bus Reset signal.
4377 */
4378 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4379 if (status != ADV_TRUE) {
4380 return status;
4381 }
4382
4383 /*
4384 * Delay for the specified SCSI Bus Reset hold time.
4385 *
4386 * The hold time delay is done on the host because the RISC has no
4387 * microsecond accurate timer.
4388 */
4389 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4390
4391 /*
4392 * Send the SCSI Bus Reset end idle command which de-asserts
4393 * the SCSI Bus Reset signal and purges any pending requests.
4394 */
4395 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4396 if (status != ADV_TRUE) {
4397 return status;
4398 }
4399
4400 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4401
4402 return status;
4403 }
4404
4405 /*
4406 * Initialize the ASC-3550.
4407 *
4408 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4409 *
4410 * For a non-fatal error return a warning code. If there are no warnings
4411 * then 0 is returned.
4412 *
4413 * Needed after initialization for error recovery.
4414 */
4415 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4416 {
4417 const struct firmware *fw;
4418 const char fwname[] = "advansys/3550.bin";
4419 AdvPortAddr iop_base;
4420 ushort warn_code;
4421 int begin_addr;
4422 int end_addr;
4423 ushort code_sum;
4424 int word;
4425 int i;
4426 int err;
4427 unsigned long chksum;
4428 ushort scsi_cfg1;
4429 uchar tid;
4430 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4431 ushort wdtr_able = 0, sdtr_able, tagqng_able;
4432 uchar max_cmd[ADV_MAX_TID + 1];
4433
4434 /* If there is already an error, don't continue. */
4435 if (asc_dvc->err_code != 0)
4436 return ADV_ERROR;
4437
4438 /*
4439 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4440 */
4441 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4442 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4443 return ADV_ERROR;
4444 }
4445
4446 warn_code = 0;
4447 iop_base = asc_dvc->iop_base;
4448
4449 /*
4450 * Save the RISC memory BIOS region before writing the microcode.
4451 * The BIOS may already be loaded and using its RISC LRAM region
4452 * so its region must be saved and restored.
4453 *
4454 * Note: This code makes the assumption, which is currently true,
4455 * that a chip reset does not clear RISC LRAM.
4456 */
4457 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4458 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4459 bios_mem[i]);
4460 }
4461
4462 /*
4463 * Save current per TID negotiated values.
4464 */
4465 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
4466 ushort bios_version, major, minor;
4467
4468 bios_version =
4469 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
4470 major = (bios_version >> 12) & 0xF;
4471 minor = (bios_version >> 8) & 0xF;
4472 if (major < 3 || (major == 3 && minor == 1)) {
4473 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
4474 AdvReadWordLram(iop_base, 0x120, wdtr_able);
4475 } else {
4476 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4477 }
4478 }
4479 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4480 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4481 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4482 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4483 max_cmd[tid]);
4484 }
4485
4486 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4487 if (err) {
4488 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4489 fwname, err);
4490 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4491 return err;
4492 }
4493 if (fw->size < 4) {
4494 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4495 fw->size, fwname);
4496 release_firmware(fw);
4497 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4498 return -EINVAL;
4499 }
4500 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4501 (fw->data[1] << 8) | fw->data[0];
4502 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4503 fw->size - 4, ADV_3550_MEMSIZE,
4504 chksum);
4505 release_firmware(fw);
4506 if (asc_dvc->err_code)
4507 return ADV_ERROR;
4508
4509 /*
4510 * Restore the RISC memory BIOS region.
4511 */
4512 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4513 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4514 bios_mem[i]);
4515 }
4516
4517 /*
4518 * Calculate and write the microcode code checksum to the microcode
4519 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4520 */
4521 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4522 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4523 code_sum = 0;
4524 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4525 for (word = begin_addr; word < end_addr; word += 2) {
4526 code_sum += AdvReadWordAutoIncLram(iop_base);
4527 }
4528 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4529
4530 /*
4531 * Read and save microcode version and date.
4532 */
4533 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4534 asc_dvc->cfg->mcode_date);
4535 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4536 asc_dvc->cfg->mcode_version);
4537
4538 /*
4539 * Set the chip type to indicate the ASC3550.
4540 */
4541 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
4542
4543 /*
4544 * If the PCI Configuration Command Register "Parity Error Response
4545 * Control" Bit was clear (0), then set the microcode variable
4546 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4547 * to ignore DMA parity errors.
4548 */
4549 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4550 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4551 word |= CONTROL_FLAG_IGNORE_PERR;
4552 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4553 }
4554
4555 /*
4556 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
4557 * threshold of 128 bytes. This register is only accessible to the host.
4558 */
4559 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
4560 START_CTL_EMFU | READ_CMD_MRM);
4561
4562 /*
4563 * Microcode operating variables for WDTR, SDTR, and command tag
4564 * queuing will be set in slave_configure() based on what a
4565 * device reports it is capable of in Inquiry byte 7.
4566 *
4567 * If SCSI Bus Resets have been disabled, then directly set
4568 * SDTR and WDTR from the EEPROM configuration. This will allow
4569 * the BIOS and warm boot to work without a SCSI bus hang on
4570 * the Inquiry caused by host and target mismatched DTR values.
4571 * Without the SCSI Bus Reset, before an Inquiry a device can't
4572 * be assumed to be in Asynchronous, Narrow mode.
4573 */
4574 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
4575 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
4576 asc_dvc->wdtr_able);
4577 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
4578 asc_dvc->sdtr_able);
4579 }
4580
4581 /*
4582 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
4583 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
4584 * bitmask. These values determine the maximum SDTR speed negotiated
4585 * with a device.
4586 *
4587 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
4588 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
4589 * without determining here whether the device supports SDTR.
4590 *
4591 * 4-bit speed SDTR speed name
4592 * =========== ===============
4593 * 0000b (0x0) SDTR disabled
4594 * 0001b (0x1) 5 Mhz
4595 * 0010b (0x2) 10 Mhz
4596 * 0011b (0x3) 20 Mhz (Ultra)
4597 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
4598 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
4599 * 0110b (0x6) Undefined
4600 * .
4601 * 1111b (0xF) Undefined
4602 */
4603 word = 0;
4604 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4605 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
4606 /* Set Ultra speed for TID 'tid'. */
4607 word |= (0x3 << (4 * (tid % 4)));
4608 } else {
4609 /* Set Fast speed for TID 'tid'. */
4610 word |= (0x2 << (4 * (tid % 4)));
4611 }
4612 if (tid == 3) { /* Check if done with sdtr_speed1. */
4613 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
4614 word = 0;
4615 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
4616 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
4617 word = 0;
4618 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
4619 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
4620 word = 0;
4621 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
4622 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
4623 /* End of loop. */
4624 }
4625 }
4626
4627 /*
4628 * Set microcode operating variable for the disconnect per TID bitmask.
4629 */
4630 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
4631 asc_dvc->cfg->disc_enable);
4632
4633 /*
4634 * Set SCSI_CFG0 Microcode Default Value.
4635 *
4636 * The microcode will set the SCSI_CFG0 register using this value
4637 * after it is started below.
4638 */
4639 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
4640 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
4641 asc_dvc->chip_scsi_id);
4642
4643 /*
4644 * Determine SCSI_CFG1 Microcode Default Value.
4645 *
4646 * The microcode will set the SCSI_CFG1 register using this value
4647 * after it is started below.
4648 */
4649
4650 /* Read current SCSI_CFG1 Register value. */
4651 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4652
4653 /*
4654 * If all three connectors are in use, return an error.
4655 */
4656 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
4657 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
4658 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
4659 return ADV_ERROR;
4660 }
4661
4662 /*
4663 * If the internal narrow cable is reversed all of the SCSI_CTRL
4664 * register signals will be set. Check for and return an error if
4665 * this condition is found.
4666 */
4667 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
4668 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
4669 return ADV_ERROR;
4670 }
4671
4672 /*
4673 * If this is a differential board and a single-ended device
4674 * is attached to one of the connectors, return an error.
4675 */
4676 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
4677 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
4678 return ADV_ERROR;
4679 }
4680
4681 /*
4682 * If automatic termination control is enabled, then set the
4683 * termination value based on a table listed in a_condor.h.
4684 *
4685 * If manual termination was specified with an EEPROM setting
4686 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
4687 * is ready to be 'ored' into SCSI_CFG1.
4688 */
4689 if (asc_dvc->cfg->termination == 0) {
4690 /*
4691 * The software always controls termination by setting TERM_CTL_SEL.
4692 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
4693 */
4694 asc_dvc->cfg->termination |= TERM_CTL_SEL;
4695
4696 switch (scsi_cfg1 & CABLE_DETECT) {
4697 /* TERM_CTL_H: on, TERM_CTL_L: on */
4698 case 0x3:
4699 case 0x7:
4700 case 0xB:
4701 case 0xD:
4702 case 0xE:
4703 case 0xF:
4704 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
4705 break;
4706
4707 /* TERM_CTL_H: on, TERM_CTL_L: off */
4708 case 0x1:
4709 case 0x5:
4710 case 0x9:
4711 case 0xA:
4712 case 0xC:
4713 asc_dvc->cfg->termination |= TERM_CTL_H;
4714 break;
4715
4716 /* TERM_CTL_H: off, TERM_CTL_L: off */
4717 case 0x2:
4718 case 0x6:
4719 break;
4720 }
4721 }
4722
4723 /*
4724 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
4725 */
4726 scsi_cfg1 &= ~TERM_CTL;
4727
4728 /*
4729 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
4730 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
4731 * referenced, because the hardware internally inverts
4732 * the Termination High and Low bits if TERM_POL is set.
4733 */
4734 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
4735
4736 /*
4737 * Set SCSI_CFG1 Microcode Default Value
4738 *
4739 * Set filter value and possibly modified termination control
4740 * bits in the Microcode SCSI_CFG1 Register Value.
4741 *
4742 * The microcode will set the SCSI_CFG1 register using this value
4743 * after it is started below.
4744 */
4745 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
4746 FLTR_DISABLE | scsi_cfg1);
4747
4748 /*
4749 * Set MEM_CFG Microcode Default Value
4750 *
4751 * The microcode will set the MEM_CFG register using this value
4752 * after it is started below.
4753 *
4754 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4755 * are defined.
4756 *
4757 * ASC-3550 has 8KB internal memory.
4758 */
4759 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
4760 BIOS_EN | RAM_SZ_8KB);
4761
4762 /*
4763 * Set SEL_MASK Microcode Default Value
4764 *
4765 * The microcode will set the SEL_MASK register using this value
4766 * after it is started below.
4767 */
4768 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
4769 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
4770
4771 AdvBuildCarrierFreelist(asc_dvc);
4772
4773 /*
4774 * Set-up the Host->RISC Initiator Command Queue (ICQ).
4775 */
4776
4777 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
4778 if (!asc_dvc->icq_sp) {
4779 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4780 return ADV_ERROR;
4781 }
4782
4783 /*
4784 * Set RISC ICQ physical address start value.
4785 */
4786 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
4787
4788 /*
4789 * Set-up the RISC->Host Initiator Response Queue (IRQ).
4790 */
4791 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
4792 if (!asc_dvc->irq_sp) {
4793 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4794 return ADV_ERROR;
4795 }
4796
4797 /*
4798 * Set RISC IRQ physical address start value.
4799 */
4800 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
4801 asc_dvc->carr_pending_cnt = 0;
4802
4803 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
4804 (ADV_INTR_ENABLE_HOST_INTR |
4805 ADV_INTR_ENABLE_GLOBAL_INTR));
4806
4807 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
4808 AdvWriteWordRegister(iop_base, IOPW_PC, word);
4809
4810 /* finally, finally, gentlemen, start your engine */
4811 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
4812
4813 /*
4814 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
4815 * Resets should be performed. The RISC has to be running
4816 * to issue a SCSI Bus Reset.
4817 */
4818 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
4819 /*
4820 * If the BIOS Signature is present in memory, restore the
4821 * BIOS Handshake Configuration Table and do not perform
4822 * a SCSI Bus Reset.
4823 */
4824 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
4825 0x55AA) {
4826 /*
4827 * Restore per TID negotiated values.
4828 */
4829 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4830 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4831 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
4832 tagqng_able);
4833 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4834 AdvWriteByteLram(iop_base,
4835 ASC_MC_NUMBER_OF_MAX_CMD + tid,
4836 max_cmd[tid]);
4837 }
4838 } else {
4839 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
4840 warn_code = ASC_WARN_BUSRESET_ERROR;
4841 }
4842 }
4843 }
4844
4845 return warn_code;
4846 }
4847
4848 /*
4849 * Initialize the ASC-38C0800.
4850 *
4851 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4852 *
4853 * For a non-fatal error return a warning code. If there are no warnings
4854 * then 0 is returned.
4855 *
4856 * Needed after initialization for error recovery.
4857 */
4858 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
4859 {
4860 const struct firmware *fw;
4861 const char fwname[] = "advansys/38C0800.bin";
4862 AdvPortAddr iop_base;
4863 ushort warn_code;
4864 int begin_addr;
4865 int end_addr;
4866 ushort code_sum;
4867 int word;
4868 int i;
4869 int err;
4870 unsigned long chksum;
4871 ushort scsi_cfg1;
4872 uchar byte;
4873 uchar tid;
4874 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4875 ushort wdtr_able, sdtr_able, tagqng_able;
4876 uchar max_cmd[ADV_MAX_TID + 1];
4877
4878 /* If there is already an error, don't continue. */
4879 if (asc_dvc->err_code != 0)
4880 return ADV_ERROR;
4881
4882 /*
4883 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
4884 */
4885 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
4886 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4887 return ADV_ERROR;
4888 }
4889
4890 warn_code = 0;
4891 iop_base = asc_dvc->iop_base;
4892
4893 /*
4894 * Save the RISC memory BIOS region before writing the microcode.
4895 * The BIOS may already be loaded and using its RISC LRAM region
4896 * so its region must be saved and restored.
4897 *
4898 * Note: This code makes the assumption, which is currently true,
4899 * that a chip reset does not clear RISC LRAM.
4900 */
4901 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4902 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4903 bios_mem[i]);
4904 }
4905
4906 /*
4907 * Save current per TID negotiated values.
4908 */
4909 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4910 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4911 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4912 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4913 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4914 max_cmd[tid]);
4915 }
4916
4917 /*
4918 * RAM BIST (RAM Built-In Self Test)
4919 *
4920 * Address : I/O base + offset 0x38h register (byte).
4921 * Function: Bit 7-6(RW) : RAM mode
4922 * Normal Mode : 0x00
4923 * Pre-test Mode : 0x40
4924 * RAM Test Mode : 0x80
4925 * Bit 5 : unused
4926 * Bit 4(RO) : Done bit
4927 * Bit 3-0(RO) : Status
4928 * Host Error : 0x08
4929 * Int_RAM Error : 0x04
4930 * RISC Error : 0x02
4931 * SCSI Error : 0x01
4932 * No Error : 0x00
4933 *
4934 * Note: RAM BIST code should be put right here, before loading the
4935 * microcode and after saving the RISC memory BIOS region.
4936 */
4937
4938 /*
4939 * LRAM Pre-test
4940 *
4941 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
4942 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
4943 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
4944 * to NORMAL_MODE, return an error too.
4945 */
4946 for (i = 0; i < 2; i++) {
4947 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
4948 mdelay(10); /* Wait for 10ms before reading back. */
4949 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
4950 if ((byte & RAM_TEST_DONE) == 0
4951 || (byte & 0x0F) != PRE_TEST_VALUE) {
4952 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
4953 return ADV_ERROR;
4954 }
4955
4956 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
4957 mdelay(10); /* Wait for 10ms before reading back. */
4958 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
4959 != NORMAL_VALUE) {
4960 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
4961 return ADV_ERROR;
4962 }
4963 }
4964
4965 /*
4966 * LRAM Test - It takes about 1.5 ms to run through the test.
4967 *
4968 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
4969 * If Done bit not set or Status not 0, save register byte, set the
4970 * err_code, and return an error.
4971 */
4972 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
4973 mdelay(10); /* Wait for 10ms before checking status. */
4974
4975 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
4976 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
4977 /* Get here if Done bit not set or Status not 0. */
4978 asc_dvc->bist_err_code = byte; /* for BIOS display message */
4979 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
4980 return ADV_ERROR;
4981 }
4982
4983 /* We need to reset back to normal mode after LRAM test passes. */
4984 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
4985
4986 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4987 if (err) {
4988 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4989 fwname, err);
4990 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4991 return err;
4992 }
4993 if (fw->size < 4) {
4994 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4995 fw->size, fwname);
4996 release_firmware(fw);
4997 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4998 return -EINVAL;
4999 }
5000 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5001 (fw->data[1] << 8) | fw->data[0];
5002 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5003 fw->size - 4, ADV_38C0800_MEMSIZE,
5004 chksum);
5005 release_firmware(fw);
5006 if (asc_dvc->err_code)
5007 return ADV_ERROR;
5008
5009 /*
5010 * Restore the RISC memory BIOS region.
5011 */
5012 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5013 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5014 bios_mem[i]);
5015 }
5016
5017 /*
5018 * Calculate and write the microcode code checksum to the microcode
5019 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5020 */
5021 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5022 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5023 code_sum = 0;
5024 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5025 for (word = begin_addr; word < end_addr; word += 2) {
5026 code_sum += AdvReadWordAutoIncLram(iop_base);
5027 }
5028 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5029
5030 /*
5031 * Read microcode version and date.
5032 */
5033 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5034 asc_dvc->cfg->mcode_date);
5035 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5036 asc_dvc->cfg->mcode_version);
5037
5038 /*
5039 * Set the chip type to indicate the ASC38C0800.
5040 */
5041 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
5042
5043 /*
5044 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5045 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5046 * cable detection and then we are able to read C_DET[3:0].
5047 *
5048 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5049 * Microcode Default Value' section below.
5050 */
5051 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5052 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5053 scsi_cfg1 | DIS_TERM_DRV);
5054
5055 /*
5056 * If the PCI Configuration Command Register "Parity Error Response
5057 * Control" Bit was clear (0), then set the microcode variable
5058 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5059 * to ignore DMA parity errors.
5060 */
5061 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5062 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5063 word |= CONTROL_FLAG_IGNORE_PERR;
5064 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5065 }
5066
5067 /*
5068 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
5069 * bits for the default FIFO threshold.
5070 *
5071 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
5072 *
5073 * For DMA Errata #4 set the BC_THRESH_ENB bit.
5074 */
5075 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5076 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
5077 READ_CMD_MRM);
5078
5079 /*
5080 * Microcode operating variables for WDTR, SDTR, and command tag
5081 * queuing will be set in slave_configure() based on what a
5082 * device reports it is capable of in Inquiry byte 7.
5083 *
5084 * If SCSI Bus Resets have been disabled, then directly set
5085 * SDTR and WDTR from the EEPROM configuration. This will allow
5086 * the BIOS and warm boot to work without a SCSI bus hang on
5087 * the Inquiry caused by host and target mismatched DTR values.
5088 * Without the SCSI Bus Reset, before an Inquiry a device can't
5089 * be assumed to be in Asynchronous, Narrow mode.
5090 */
5091 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5092 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5093 asc_dvc->wdtr_able);
5094 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5095 asc_dvc->sdtr_able);
5096 }
5097
5098 /*
5099 * Set microcode operating variables for DISC and SDTR_SPEED1,
5100 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5101 * configuration values.
5102 *
5103 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5104 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5105 * without determining here whether the device supports SDTR.
5106 */
5107 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5108 asc_dvc->cfg->disc_enable);
5109 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5110 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5111 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5112 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5113
5114 /*
5115 * Set SCSI_CFG0 Microcode Default Value.
5116 *
5117 * The microcode will set the SCSI_CFG0 register using this value
5118 * after it is started below.
5119 */
5120 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5121 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5122 asc_dvc->chip_scsi_id);
5123
5124 /*
5125 * Determine SCSI_CFG1 Microcode Default Value.
5126 *
5127 * The microcode will set the SCSI_CFG1 register using this value
5128 * after it is started below.
5129 */
5130
5131 /* Read current SCSI_CFG1 Register value. */
5132 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5133
5134 /*
5135 * If the internal narrow cable is reversed all of the SCSI_CTRL
5136 * register signals will be set. Check for and return an error if
5137 * this condition is found.
5138 */
5139 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5140 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5141 return ADV_ERROR;
5142 }
5143
5144 /*
5145 * All kind of combinations of devices attached to one of four
5146 * connectors are acceptable except HVD device attached. For example,
5147 * LVD device can be attached to SE connector while SE device attached
5148 * to LVD connector. If LVD device attached to SE connector, it only
5149 * runs up to Ultra speed.
5150 *
5151 * If an HVD device is attached to one of LVD connectors, return an
5152 * error. However, there is no way to detect HVD device attached to
5153 * SE connectors.
5154 */
5155 if (scsi_cfg1 & HVD) {
5156 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
5157 return ADV_ERROR;
5158 }
5159
5160 /*
5161 * If either SE or LVD automatic termination control is enabled, then
5162 * set the termination value based on a table listed in a_condor.h.
5163 *
5164 * If manual termination was specified with an EEPROM setting then
5165 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
5166 * to be 'ored' into SCSI_CFG1.
5167 */
5168 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5169 /* SE automatic termination control is enabled. */
5170 switch (scsi_cfg1 & C_DET_SE) {
5171 /* TERM_SE_HI: on, TERM_SE_LO: on */
5172 case 0x1:
5173 case 0x2:
5174 case 0x3:
5175 asc_dvc->cfg->termination |= TERM_SE;
5176 break;
5177
5178 /* TERM_SE_HI: on, TERM_SE_LO: off */
5179 case 0x0:
5180 asc_dvc->cfg->termination |= TERM_SE_HI;
5181 break;
5182 }
5183 }
5184
5185 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
5186 /* LVD automatic termination control is enabled. */
5187 switch (scsi_cfg1 & C_DET_LVD) {
5188 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
5189 case 0x4:
5190 case 0x8:
5191 case 0xC:
5192 asc_dvc->cfg->termination |= TERM_LVD;
5193 break;
5194
5195 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
5196 case 0x0:
5197 break;
5198 }
5199 }
5200
5201 /*
5202 * Clear any set TERM_SE and TERM_LVD bits.
5203 */
5204 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
5205
5206 /*
5207 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
5208 */
5209 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
5210
5211 /*
5212 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
5213 * bits and set possibly modified termination control bits in the
5214 * Microcode SCSI_CFG1 Register Value.
5215 */
5216 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
5217
5218 /*
5219 * Set SCSI_CFG1 Microcode Default Value
5220 *
5221 * Set possibly modified termination control and reset DIS_TERM_DRV
5222 * bits in the Microcode SCSI_CFG1 Register Value.
5223 *
5224 * The microcode will set the SCSI_CFG1 register using this value
5225 * after it is started below.
5226 */
5227 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5228
5229 /*
5230 * Set MEM_CFG Microcode Default Value
5231 *
5232 * The microcode will set the MEM_CFG register using this value
5233 * after it is started below.
5234 *
5235 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5236 * are defined.
5237 *
5238 * ASC-38C0800 has 16KB internal memory.
5239 */
5240 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5241 BIOS_EN | RAM_SZ_16KB);
5242
5243 /*
5244 * Set SEL_MASK Microcode Default Value
5245 *
5246 * The microcode will set the SEL_MASK register using this value
5247 * after it is started below.
5248 */
5249 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5250 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5251
5252 AdvBuildCarrierFreelist(asc_dvc);
5253
5254 /*
5255 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5256 */
5257
5258 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5259 if (!asc_dvc->icq_sp) {
5260 ASC_DBG(0, "Failed to get ICQ carrier\n");
5261 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5262 return ADV_ERROR;
5263 }
5264
5265 /*
5266 * Set RISC ICQ physical address start value.
5267 * carr_pa is LE, must be native before write
5268 */
5269 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5270
5271 /*
5272 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5273 */
5274 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5275 if (!asc_dvc->irq_sp) {
5276 ASC_DBG(0, "Failed to get IRQ carrier\n");
5277 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5278 return ADV_ERROR;
5279 }
5280
5281 /*
5282 * Set RISC IRQ physical address start value.
5283 *
5284 * carr_pa is LE, must be native before write *
5285 */
5286 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5287 asc_dvc->carr_pending_cnt = 0;
5288
5289 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5290 (ADV_INTR_ENABLE_HOST_INTR |
5291 ADV_INTR_ENABLE_GLOBAL_INTR));
5292
5293 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5294 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5295
5296 /* finally, finally, gentlemen, start your engine */
5297 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5298
5299 /*
5300 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5301 * Resets should be performed. The RISC has to be running
5302 * to issue a SCSI Bus Reset.
5303 */
5304 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5305 /*
5306 * If the BIOS Signature is present in memory, restore the
5307 * BIOS Handshake Configuration Table and do not perform
5308 * a SCSI Bus Reset.
5309 */
5310 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5311 0x55AA) {
5312 /*
5313 * Restore per TID negotiated values.
5314 */
5315 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5316 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5317 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5318 tagqng_able);
5319 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5320 AdvWriteByteLram(iop_base,
5321 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5322 max_cmd[tid]);
5323 }
5324 } else {
5325 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5326 warn_code = ASC_WARN_BUSRESET_ERROR;
5327 }
5328 }
5329 }
5330
5331 return warn_code;
5332 }
5333
5334 /*
5335 * Initialize the ASC-38C1600.
5336 *
5337 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
5338 *
5339 * For a non-fatal error return a warning code. If there are no warnings
5340 * then 0 is returned.
5341 *
5342 * Needed after initialization for error recovery.
5343 */
5344 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
5345 {
5346 const struct firmware *fw;
5347 const char fwname[] = "advansys/38C1600.bin";
5348 AdvPortAddr iop_base;
5349 ushort warn_code;
5350 int begin_addr;
5351 int end_addr;
5352 ushort code_sum;
5353 long word;
5354 int i;
5355 int err;
5356 unsigned long chksum;
5357 ushort scsi_cfg1;
5358 uchar byte;
5359 uchar tid;
5360 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
5361 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
5362 uchar max_cmd[ASC_MAX_TID + 1];
5363
5364 /* If there is already an error, don't continue. */
5365 if (asc_dvc->err_code != 0) {
5366 return ADV_ERROR;
5367 }
5368
5369 /*
5370 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
5371 */
5372 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
5373 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5374 return ADV_ERROR;
5375 }
5376
5377 warn_code = 0;
5378 iop_base = asc_dvc->iop_base;
5379
5380 /*
5381 * Save the RISC memory BIOS region before writing the microcode.
5382 * The BIOS may already be loaded and using its RISC LRAM region
5383 * so its region must be saved and restored.
5384 *
5385 * Note: This code makes the assumption, which is currently true,
5386 * that a chip reset does not clear RISC LRAM.
5387 */
5388 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5389 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5390 bios_mem[i]);
5391 }
5392
5393 /*
5394 * Save current per TID negotiated values.
5395 */
5396 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5397 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5398 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5399 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5400 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5401 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5402 max_cmd[tid]);
5403 }
5404
5405 /*
5406 * RAM BIST (Built-In Self Test)
5407 *
5408 * Address : I/O base + offset 0x38h register (byte).
5409 * Function: Bit 7-6(RW) : RAM mode
5410 * Normal Mode : 0x00
5411 * Pre-test Mode : 0x40
5412 * RAM Test Mode : 0x80
5413 * Bit 5 : unused
5414 * Bit 4(RO) : Done bit
5415 * Bit 3-0(RO) : Status
5416 * Host Error : 0x08
5417 * Int_RAM Error : 0x04
5418 * RISC Error : 0x02
5419 * SCSI Error : 0x01
5420 * No Error : 0x00
5421 *
5422 * Note: RAM BIST code should be put right here, before loading the
5423 * microcode and after saving the RISC memory BIOS region.
5424 */
5425
5426 /*
5427 * LRAM Pre-test
5428 *
5429 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5430 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5431 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5432 * to NORMAL_MODE, return an error too.
5433 */
5434 for (i = 0; i < 2; i++) {
5435 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5436 mdelay(10); /* Wait for 10ms before reading back. */
5437 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5438 if ((byte & RAM_TEST_DONE) == 0
5439 || (byte & 0x0F) != PRE_TEST_VALUE) {
5440 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5441 return ADV_ERROR;
5442 }
5443
5444 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5445 mdelay(10); /* Wait for 10ms before reading back. */
5446 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5447 != NORMAL_VALUE) {
5448 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5449 return ADV_ERROR;
5450 }
5451 }
5452
5453 /*
5454 * LRAM Test - It takes about 1.5 ms to run through the test.
5455 *
5456 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5457 * If Done bit not set or Status not 0, save register byte, set the
5458 * err_code, and return an error.
5459 */
5460 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5461 mdelay(10); /* Wait for 10ms before checking status. */
5462
5463 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5464 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5465 /* Get here if Done bit not set or Status not 0. */
5466 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5467 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5468 return ADV_ERROR;
5469 }
5470
5471 /* We need to reset back to normal mode after LRAM test passes. */
5472 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5473
5474 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5475 if (err) {
5476 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5477 fwname, err);
5478 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5479 return err;
5480 }
5481 if (fw->size < 4) {
5482 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5483 fw->size, fwname);
5484 release_firmware(fw);
5485 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5486 return -EINVAL;
5487 }
5488 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5489 (fw->data[1] << 8) | fw->data[0];
5490 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5491 fw->size - 4, ADV_38C1600_MEMSIZE,
5492 chksum);
5493 release_firmware(fw);
5494 if (asc_dvc->err_code)
5495 return ADV_ERROR;
5496
5497 /*
5498 * Restore the RISC memory BIOS region.
5499 */
5500 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5501 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5502 bios_mem[i]);
5503 }
5504
5505 /*
5506 * Calculate and write the microcode code checksum to the microcode
5507 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5508 */
5509 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5510 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5511 code_sum = 0;
5512 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5513 for (word = begin_addr; word < end_addr; word += 2) {
5514 code_sum += AdvReadWordAutoIncLram(iop_base);
5515 }
5516 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5517
5518 /*
5519 * Read microcode version and date.
5520 */
5521 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5522 asc_dvc->cfg->mcode_date);
5523 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5524 asc_dvc->cfg->mcode_version);
5525
5526 /*
5527 * Set the chip type to indicate the ASC38C1600.
5528 */
5529 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
5530
5531 /*
5532 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5533 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5534 * cable detection and then we are able to read C_DET[3:0].
5535 *
5536 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5537 * Microcode Default Value' section below.
5538 */
5539 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5540 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5541 scsi_cfg1 | DIS_TERM_DRV);
5542
5543 /*
5544 * If the PCI Configuration Command Register "Parity Error Response
5545 * Control" Bit was clear (0), then set the microcode variable
5546 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5547 * to ignore DMA parity errors.
5548 */
5549 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5550 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5551 word |= CONTROL_FLAG_IGNORE_PERR;
5552 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5553 }
5554
5555 /*
5556 * If the BIOS control flag AIPP (Asynchronous Information
5557 * Phase Protection) disable bit is not set, then set the firmware
5558 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
5559 * AIPP checking and encoding.
5560 */
5561 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
5562 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5563 word |= CONTROL_FLAG_ENABLE_AIPP;
5564 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5565 }
5566
5567 /*
5568 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
5569 * and START_CTL_TH [3:2].
5570 */
5571 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5572 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
5573
5574 /*
5575 * Microcode operating variables for WDTR, SDTR, and command tag
5576 * queuing will be set in slave_configure() based on what a
5577 * device reports it is capable of in Inquiry byte 7.
5578 *
5579 * If SCSI Bus Resets have been disabled, then directly set
5580 * SDTR and WDTR from the EEPROM configuration. This will allow
5581 * the BIOS and warm boot to work without a SCSI bus hang on
5582 * the Inquiry caused by host and target mismatched DTR values.
5583 * Without the SCSI Bus Reset, before an Inquiry a device can't
5584 * be assumed to be in Asynchronous, Narrow mode.
5585 */
5586 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5587 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5588 asc_dvc->wdtr_able);
5589 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5590 asc_dvc->sdtr_able);
5591 }
5592
5593 /*
5594 * Set microcode operating variables for DISC and SDTR_SPEED1,
5595 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5596 * configuration values.
5597 *
5598 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5599 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5600 * without determining here whether the device supports SDTR.
5601 */
5602 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5603 asc_dvc->cfg->disc_enable);
5604 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5605 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5606 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5607 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5608
5609 /*
5610 * Set SCSI_CFG0 Microcode Default Value.
5611 *
5612 * The microcode will set the SCSI_CFG0 register using this value
5613 * after it is started below.
5614 */
5615 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5616 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5617 asc_dvc->chip_scsi_id);
5618
5619 /*
5620 * Calculate SCSI_CFG1 Microcode Default Value.
5621 *
5622 * The microcode will set the SCSI_CFG1 register using this value
5623 * after it is started below.
5624 *
5625 * Each ASC-38C1600 function has only two cable detect bits.
5626 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
5627 */
5628 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5629
5630 /*
5631 * If the cable is reversed all of the SCSI_CTRL register signals
5632 * will be set. Check for and return an error if this condition is
5633 * found.
5634 */
5635 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5636 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5637 return ADV_ERROR;
5638 }
5639
5640 /*
5641 * Each ASC-38C1600 function has two connectors. Only an HVD device
5642 * can not be connected to either connector. An LVD device or SE device
5643 * may be connected to either connecor. If an SE device is connected,
5644 * then at most Ultra speed (20 Mhz) can be used on both connectors.
5645 *
5646 * If an HVD device is attached, return an error.
5647 */
5648 if (scsi_cfg1 & HVD) {
5649 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
5650 return ADV_ERROR;
5651 }
5652
5653 /*
5654 * Each function in the ASC-38C1600 uses only the SE cable detect and
5655 * termination because there are two connectors for each function. Each
5656 * function may use either LVD or SE mode. Corresponding the SE automatic
5657 * termination control EEPROM bits are used for each function. Each
5658 * function has its own EEPROM. If SE automatic control is enabled for
5659 * the function, then set the termination value based on a table listed
5660 * in a_condor.h.
5661 *
5662 * If manual termination is specified in the EEPROM for the function,
5663 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
5664 * ready to be 'ored' into SCSI_CFG1.
5665 */
5666 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5667 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
5668 /* SE automatic termination control is enabled. */
5669 switch (scsi_cfg1 & C_DET_SE) {
5670 /* TERM_SE_HI: on, TERM_SE_LO: on */
5671 case 0x1:
5672 case 0x2:
5673 case 0x3:
5674 asc_dvc->cfg->termination |= TERM_SE;
5675 break;
5676
5677 case 0x0:
5678 if (PCI_FUNC(pdev->devfn) == 0) {
5679 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
5680 } else {
5681 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
5682 asc_dvc->cfg->termination |= TERM_SE_HI;
5683 }
5684 break;
5685 }
5686 }
5687
5688 /*
5689 * Clear any set TERM_SE bits.
5690 */
5691 scsi_cfg1 &= ~TERM_SE;
5692
5693 /*
5694 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
5695 */
5696 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
5697
5698 /*
5699 * Clear Big Endian and Terminator Polarity bits and set possibly
5700 * modified termination control bits in the Microcode SCSI_CFG1
5701 * Register Value.
5702 *
5703 * Big Endian bit is not used even on big endian machines.
5704 */
5705 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
5706
5707 /*
5708 * Set SCSI_CFG1 Microcode Default Value
5709 *
5710 * Set possibly modified termination control bits in the Microcode
5711 * SCSI_CFG1 Register Value.
5712 *
5713 * The microcode will set the SCSI_CFG1 register using this value
5714 * after it is started below.
5715 */
5716 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5717
5718 /*
5719 * Set MEM_CFG Microcode Default Value
5720 *
5721 * The microcode will set the MEM_CFG register using this value
5722 * after it is started below.
5723 *
5724 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5725 * are defined.
5726 *
5727 * ASC-38C1600 has 32KB internal memory.
5728 *
5729 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
5730 * out a special 16K Adv Library and Microcode version. After the issue
5731 * resolved, we should turn back to the 32K support. Both a_condor.h and
5732 * mcode.sas files also need to be updated.
5733 *
5734 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5735 * BIOS_EN | RAM_SZ_32KB);
5736 */
5737 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5738 BIOS_EN | RAM_SZ_16KB);
5739
5740 /*
5741 * Set SEL_MASK Microcode Default Value
5742 *
5743 * The microcode will set the SEL_MASK register using this value
5744 * after it is started below.
5745 */
5746 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5747 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5748
5749 AdvBuildCarrierFreelist(asc_dvc);
5750
5751 /*
5752 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5753 */
5754 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5755 if (!asc_dvc->icq_sp) {
5756 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5757 return ADV_ERROR;
5758 }
5759
5760 /*
5761 * Set RISC ICQ physical address start value. Initialize the
5762 * COMMA register to the same value otherwise the RISC will
5763 * prematurely detect a command is available.
5764 */
5765 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5766 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
5767 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
5768
5769 /*
5770 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5771 */
5772 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5773 if (!asc_dvc->irq_sp) {
5774 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5775 return ADV_ERROR;
5776 }
5777
5778 /*
5779 * Set RISC IRQ physical address start value.
5780 */
5781 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5782 asc_dvc->carr_pending_cnt = 0;
5783
5784 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5785 (ADV_INTR_ENABLE_HOST_INTR |
5786 ADV_INTR_ENABLE_GLOBAL_INTR));
5787 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5788 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5789
5790 /* finally, finally, gentlemen, start your engine */
5791 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5792
5793 /*
5794 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5795 * Resets should be performed. The RISC has to be running
5796 * to issue a SCSI Bus Reset.
5797 */
5798 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5799 /*
5800 * If the BIOS Signature is present in memory, restore the
5801 * per TID microcode operating variables.
5802 */
5803 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5804 0x55AA) {
5805 /*
5806 * Restore per TID negotiated values.
5807 */
5808 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5809 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5810 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5811 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5812 tagqng_able);
5813 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5814 AdvWriteByteLram(iop_base,
5815 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5816 max_cmd[tid]);
5817 }
5818 } else {
5819 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5820 warn_code = ASC_WARN_BUSRESET_ERROR;
5821 }
5822 }
5823 }
5824
5825 return warn_code;
5826 }
5827
5828 /*
5829 * Reset chip and SCSI Bus.
5830 *
5831 * Return Value:
5832 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
5833 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
5834 */
5835 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
5836 {
5837 int status;
5838 ushort wdtr_able, sdtr_able, tagqng_able;
5839 ushort ppr_able = 0;
5840 uchar tid, max_cmd[ADV_MAX_TID + 1];
5841 AdvPortAddr iop_base;
5842 ushort bios_sig;
5843
5844 iop_base = asc_dvc->iop_base;
5845
5846 /*
5847 * Save current per TID negotiated values.
5848 */
5849 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5850 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5851 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5852 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5853 }
5854 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5855 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5856 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5857 max_cmd[tid]);
5858 }
5859
5860 /*
5861 * Force the AdvInitAsc3550/38C0800Driver() function to
5862 * perform a SCSI Bus Reset by clearing the BIOS signature word.
5863 * The initialization functions assumes a SCSI Bus Reset is not
5864 * needed if the BIOS signature word is present.
5865 */
5866 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5867 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
5868
5869 /*
5870 * Stop chip and reset it.
5871 */
5872 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
5873 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
5874 mdelay(100);
5875 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
5876 ADV_CTRL_REG_CMD_WR_IO_REG);
5877
5878 /*
5879 * Reset Adv Library error code, if any, and try
5880 * re-initializing the chip.
5881 */
5882 asc_dvc->err_code = 0;
5883 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5884 status = AdvInitAsc38C1600Driver(asc_dvc);
5885 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
5886 status = AdvInitAsc38C0800Driver(asc_dvc);
5887 } else {
5888 status = AdvInitAsc3550Driver(asc_dvc);
5889 }
5890
5891 /* Translate initialization return value to status value. */
5892 if (status == 0) {
5893 status = ADV_TRUE;
5894 } else {
5895 status = ADV_FALSE;
5896 }
5897
5898 /*
5899 * Restore the BIOS signature word.
5900 */
5901 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5902
5903 /*
5904 * Restore per TID negotiated values.
5905 */
5906 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5907 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5908 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5909 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5910 }
5911 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5912 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5913 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5914 max_cmd[tid]);
5915 }
5916
5917 return status;
5918 }
5919
5920 /*
5921 * adv_async_callback() - Adv Library asynchronous event callback function.
5922 */
5923 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
5924 {
5925 switch (code) {
5926 case ADV_ASYNC_SCSI_BUS_RESET_DET:
5927 /*
5928 * The firmware detected a SCSI Bus reset.
5929 */
5930 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
5931 break;
5932
5933 case ADV_ASYNC_RDMA_FAILURE:
5934 /*
5935 * Handle RDMA failure by resetting the SCSI Bus and
5936 * possibly the chip if it is unresponsive. Log the error
5937 * with a unique code.
5938 */
5939 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
5940 AdvResetChipAndSB(adv_dvc_varp);
5941 break;
5942
5943 case ADV_HOST_SCSI_BUS_RESET:
5944 /*
5945 * Host generated SCSI bus reset occurred.
5946 */
5947 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
5948 break;
5949
5950 default:
5951 ASC_DBG(0, "unknown code 0x%x\n", code);
5952 break;
5953 }
5954 }
5955
5956 /*
5957 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
5958 *
5959 * Callback function for the Wide SCSI Adv Library.
5960 */
5961 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
5962 {
5963 struct asc_board *boardp = adv_dvc_varp->drv_ptr;
5964 u32 srb_tag;
5965 adv_req_t *reqp;
5966 adv_sgblk_t *sgblkp;
5967 struct scsi_cmnd *scp;
5968 u32 resid_cnt;
5969 dma_addr_t sense_addr;
5970
5971 ASC_DBG(1, "adv_dvc_varp 0x%p, scsiqp 0x%p\n",
5972 adv_dvc_varp, scsiqp);
5973 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
5974
5975 /*
5976 * Get the adv_req_t structure for the command that has been
5977 * completed. The adv_req_t structure actually contains the
5978 * completed ADV_SCSI_REQ_Q structure.
5979 */
5980 srb_tag = le32_to_cpu(scsiqp->srb_tag);
5981 scp = scsi_host_find_tag(boardp->shost, scsiqp->srb_tag);
5982
5983 ASC_DBG(1, "scp 0x%p\n", scp);
5984 if (scp == NULL) {
5985 ASC_PRINT
5986 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
5987 return;
5988 }
5989 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
5990
5991 reqp = (adv_req_t *)scp->host_scribble;
5992 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
5993 if (reqp == NULL) {
5994 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
5995 return;
5996 }
5997 /*
5998 * Remove backreferences to avoid duplicate
5999 * command completions.
6000 */
6001 scp->host_scribble = NULL;
6002 reqp->cmndp = NULL;
6003
6004 ASC_STATS(boardp->shost, callback);
6005 ASC_DBG(1, "shost 0x%p\n", boardp->shost);
6006
6007 sense_addr = le32_to_cpu(scsiqp->sense_addr);
6008 dma_unmap_single(boardp->dev, sense_addr,
6009 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
6010
6011 /*
6012 * 'done_status' contains the command's ending status.
6013 */
6014 switch (scsiqp->done_status) {
6015 case QD_NO_ERROR:
6016 ASC_DBG(2, "QD_NO_ERROR\n");
6017 scp->result = 0;
6018
6019 /*
6020 * Check for an underrun condition.
6021 *
6022 * If there was no error and an underrun condition, then
6023 * then return the number of underrun bytes.
6024 */
6025 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
6026 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
6027 resid_cnt <= scsi_bufflen(scp)) {
6028 ASC_DBG(1, "underrun condition %lu bytes\n",
6029 (ulong)resid_cnt);
6030 scsi_set_resid(scp, resid_cnt);
6031 }
6032 break;
6033
6034 case QD_WITH_ERROR:
6035 ASC_DBG(2, "QD_WITH_ERROR\n");
6036 switch (scsiqp->host_status) {
6037 case QHSTA_NO_ERROR:
6038 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
6039 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
6040 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6041 SCSI_SENSE_BUFFERSIZE);
6042 /*
6043 * Note: The 'status_byte()' macro used by
6044 * target drivers defined in scsi.h shifts the
6045 * status byte returned by host drivers right
6046 * by 1 bit. This is why target drivers also
6047 * use right shifted status byte definitions.
6048 * For instance target drivers use
6049 * CHECK_CONDITION, defined to 0x1, instead of
6050 * the SCSI defined check condition value of
6051 * 0x2. Host drivers are supposed to return
6052 * the status byte as it is defined by SCSI.
6053 */
6054 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6055 STATUS_BYTE(scsiqp->scsi_status);
6056 } else {
6057 scp->result = STATUS_BYTE(scsiqp->scsi_status);
6058 }
6059 break;
6060
6061 default:
6062 /* Some other QHSTA error occurred. */
6063 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
6064 scp->result = HOST_BYTE(DID_BAD_TARGET);
6065 break;
6066 }
6067 break;
6068
6069 case QD_ABORTED_BY_HOST:
6070 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
6071 scp->result =
6072 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
6073 break;
6074
6075 default:
6076 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
6077 scp->result =
6078 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
6079 break;
6080 }
6081
6082 /*
6083 * If the 'init_tidmask' bit isn't already set for the target and the
6084 * current request finished normally, then set the bit for the target
6085 * to indicate that a device is present.
6086 */
6087 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6088 scsiqp->done_status == QD_NO_ERROR &&
6089 scsiqp->host_status == QHSTA_NO_ERROR) {
6090 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6091 }
6092
6093 asc_scsi_done(scp);
6094
6095 /*
6096 * Free all 'adv_sgblk_t' structures allocated for the request.
6097 */
6098 while ((sgblkp = reqp->sgblkp) != NULL) {
6099 /* Remove 'sgblkp' from the request list. */
6100 reqp->sgblkp = sgblkp->next_sgblkp;
6101
6102 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
6103 sgblkp->sg_addr);
6104 }
6105
6106 ASC_DBG(1, "done\n");
6107 }
6108
6109 /*
6110 * Adv Library Interrupt Service Routine
6111 *
6112 * This function is called by a driver's interrupt service routine.
6113 * The function disables and re-enables interrupts.
6114 *
6115 * When a microcode idle command is completed, the ADV_DVC_VAR
6116 * 'idle_cmd_done' field is set to ADV_TRUE.
6117 *
6118 * Note: AdvISR() can be called when interrupts are disabled or even
6119 * when there is no hardware interrupt condition present. It will
6120 * always check for completed idle commands and microcode requests.
6121 * This is an important feature that shouldn't be changed because it
6122 * allows commands to be completed from polling mode loops.
6123 *
6124 * Return:
6125 * ADV_TRUE(1) - interrupt was pending
6126 * ADV_FALSE(0) - no interrupt was pending
6127 */
6128 static int AdvISR(ADV_DVC_VAR *asc_dvc)
6129 {
6130 AdvPortAddr iop_base;
6131 uchar int_stat;
6132 ushort target_bit;
6133 ADV_CARR_T *free_carrp;
6134 __le32 irq_next_vpa;
6135 ADV_SCSI_REQ_Q *scsiq;
6136 adv_req_t *reqp;
6137
6138 iop_base = asc_dvc->iop_base;
6139
6140 /* Reading the register clears the interrupt. */
6141 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
6142
6143 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
6144 ADV_INTR_STATUS_INTRC)) == 0) {
6145 return ADV_FALSE;
6146 }
6147
6148 /*
6149 * Notify the driver of an asynchronous microcode condition by
6150 * calling the adv_async_callback function. The function
6151 * is passed the microcode ASC_MC_INTRB_CODE byte value.
6152 */
6153 if (int_stat & ADV_INTR_STATUS_INTRB) {
6154 uchar intrb_code;
6155
6156 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
6157
6158 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
6159 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6160 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
6161 asc_dvc->carr_pending_cnt != 0) {
6162 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
6163 ADV_TICKLE_A);
6164 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6165 AdvWriteByteRegister(iop_base,
6166 IOPB_TICKLE,
6167 ADV_TICKLE_NOP);
6168 }
6169 }
6170 }
6171
6172 adv_async_callback(asc_dvc, intrb_code);
6173 }
6174
6175 /*
6176 * Check if the IRQ stopper carrier contains a completed request.
6177 */
6178 while (((irq_next_vpa =
6179 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ADV_RQ_DONE) != 0) {
6180 /*
6181 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
6182 * The RISC will have set 'areq_vpa' to a virtual address.
6183 *
6184 * The firmware will have copied the ADV_SCSI_REQ_Q.scsiq_ptr
6185 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
6186 * below complements the conversion of ADV_SCSI_REQ_Q.scsiq_ptr'
6187 * in AdvExeScsiQueue().
6188 */
6189 u32 pa_offset = le32_to_cpu(asc_dvc->irq_sp->areq_vpa);
6190 ASC_DBG(1, "irq_sp %p areq_vpa %u\n",
6191 asc_dvc->irq_sp, pa_offset);
6192 reqp = adv_get_reqp(asc_dvc, pa_offset);
6193 scsiq = &reqp->scsi_req_q;
6194
6195 /*
6196 * Request finished with good status and the queue was not
6197 * DMAed to host memory by the firmware. Set all status fields
6198 * to indicate good status.
6199 */
6200 if ((irq_next_vpa & ADV_RQ_GOOD) != 0) {
6201 scsiq->done_status = QD_NO_ERROR;
6202 scsiq->host_status = scsiq->scsi_status = 0;
6203 scsiq->data_cnt = 0L;
6204 }
6205
6206 /*
6207 * Advance the stopper pointer to the next carrier
6208 * ignoring the lower four bits. Free the previous
6209 * stopper carrier.
6210 */
6211 free_carrp = asc_dvc->irq_sp;
6212 asc_dvc->irq_sp = adv_get_carrier(asc_dvc,
6213 ADV_GET_CARRP(irq_next_vpa));
6214
6215 free_carrp->next_vpa = asc_dvc->carr_freelist->carr_va;
6216 asc_dvc->carr_freelist = free_carrp;
6217 asc_dvc->carr_pending_cnt--;
6218
6219 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
6220
6221 /*
6222 * Clear request microcode control flag.
6223 */
6224 scsiq->cntl = 0;
6225
6226 /*
6227 * Notify the driver of the completed request by passing
6228 * the ADV_SCSI_REQ_Q pointer to its callback function.
6229 */
6230 adv_isr_callback(asc_dvc, scsiq);
6231 /*
6232 * Note: After the driver callback function is called, 'scsiq'
6233 * can no longer be referenced.
6234 *
6235 * Fall through and continue processing other completed
6236 * requests...
6237 */
6238 }
6239 return ADV_TRUE;
6240 }
6241
6242 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
6243 {
6244 if (asc_dvc->err_code == 0) {
6245 asc_dvc->err_code = err_code;
6246 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
6247 err_code);
6248 }
6249 return err_code;
6250 }
6251
6252 static void AscAckInterrupt(PortAddr iop_base)
6253 {
6254 uchar host_flag;
6255 uchar risc_flag;
6256 ushort loop;
6257
6258 loop = 0;
6259 do {
6260 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
6261 if (loop++ > 0x7FFF) {
6262 break;
6263 }
6264 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
6265 host_flag =
6266 AscReadLramByte(iop_base,
6267 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
6268 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6269 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
6270 AscSetChipStatus(iop_base, CIW_INT_ACK);
6271 loop = 0;
6272 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
6273 AscSetChipStatus(iop_base, CIW_INT_ACK);
6274 if (loop++ > 3) {
6275 break;
6276 }
6277 }
6278 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
6279 }
6280
6281 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
6282 {
6283 const uchar *period_table;
6284 int max_index;
6285 int min_index;
6286 int i;
6287
6288 period_table = asc_dvc->sdtr_period_tbl;
6289 max_index = (int)asc_dvc->max_sdtr_index;
6290 min_index = (int)asc_dvc->min_sdtr_index;
6291 if ((syn_time <= period_table[max_index])) {
6292 for (i = min_index; i < (max_index - 1); i++) {
6293 if (syn_time <= period_table[i]) {
6294 return (uchar)i;
6295 }
6296 }
6297 return (uchar)max_index;
6298 } else {
6299 return (uchar)(max_index + 1);
6300 }
6301 }
6302
6303 static uchar
6304 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
6305 {
6306 EXT_MSG sdtr_buf;
6307 uchar sdtr_period_index;
6308 PortAddr iop_base;
6309
6310 iop_base = asc_dvc->iop_base;
6311 sdtr_buf.msg_type = EXTENDED_MESSAGE;
6312 sdtr_buf.msg_len = MS_SDTR_LEN;
6313 sdtr_buf.msg_req = EXTENDED_SDTR;
6314 sdtr_buf.xfer_period = sdtr_period;
6315 sdtr_offset &= ASC_SYN_MAX_OFFSET;
6316 sdtr_buf.req_ack_offset = sdtr_offset;
6317 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6318 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
6319 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6320 (uchar *)&sdtr_buf,
6321 sizeof(EXT_MSG) >> 1);
6322 return ((sdtr_period_index << 4) | sdtr_offset);
6323 } else {
6324 sdtr_buf.req_ack_offset = 0;
6325 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6326 (uchar *)&sdtr_buf,
6327 sizeof(EXT_MSG) >> 1);
6328 return 0;
6329 }
6330 }
6331
6332 static uchar
6333 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
6334 {
6335 uchar byte;
6336 uchar sdtr_period_ix;
6337
6338 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6339 if (sdtr_period_ix > asc_dvc->max_sdtr_index)
6340 return 0xFF;
6341 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
6342 return byte;
6343 }
6344
6345 static bool AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
6346 {
6347 ASC_SCSI_BIT_ID_TYPE org_id;
6348 int i;
6349 bool sta = true;
6350
6351 AscSetBank(iop_base, 1);
6352 org_id = AscReadChipDvcID(iop_base);
6353 for (i = 0; i <= ASC_MAX_TID; i++) {
6354 if (org_id == (0x01 << i))
6355 break;
6356 }
6357 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
6358 AscWriteChipDvcID(iop_base, id);
6359 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
6360 AscSetBank(iop_base, 0);
6361 AscSetChipSyn(iop_base, sdtr_data);
6362 if (AscGetChipSyn(iop_base) != sdtr_data) {
6363 sta = false;
6364 }
6365 } else {
6366 sta = false;
6367 }
6368 AscSetBank(iop_base, 1);
6369 AscWriteChipDvcID(iop_base, org_id);
6370 AscSetBank(iop_base, 0);
6371 return (sta);
6372 }
6373
6374 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
6375 {
6376 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
6377 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
6378 }
6379
6380 static void AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
6381 {
6382 EXT_MSG ext_msg;
6383 EXT_MSG out_msg;
6384 ushort halt_q_addr;
6385 bool sdtr_accept;
6386 ushort int_halt_code;
6387 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6388 ASC_SCSI_BIT_ID_TYPE target_id;
6389 PortAddr iop_base;
6390 uchar tag_code;
6391 uchar q_status;
6392 uchar halt_qp;
6393 uchar sdtr_data;
6394 uchar target_ix;
6395 uchar q_cntl, tid_no;
6396 uchar cur_dvc_qng;
6397 uchar asyn_sdtr;
6398 uchar scsi_status;
6399 struct asc_board *boardp;
6400
6401 BUG_ON(!asc_dvc->drv_ptr);
6402 boardp = asc_dvc->drv_ptr;
6403
6404 iop_base = asc_dvc->iop_base;
6405 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
6406
6407 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
6408 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
6409 target_ix = AscReadLramByte(iop_base,
6410 (ushort)(halt_q_addr +
6411 (ushort)ASC_SCSIQ_B_TARGET_IX));
6412 q_cntl = AscReadLramByte(iop_base,
6413 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6414 tid_no = ASC_TIX_TO_TID(target_ix);
6415 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
6416 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6417 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
6418 } else {
6419 asyn_sdtr = 0;
6420 }
6421 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
6422 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6423 AscSetChipSDTR(iop_base, 0, tid_no);
6424 boardp->sdtr_data[tid_no] = 0;
6425 }
6426 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6427 return;
6428 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
6429 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6430 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6431 boardp->sdtr_data[tid_no] = asyn_sdtr;
6432 }
6433 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6434 return;
6435 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
6436 AscMemWordCopyPtrFromLram(iop_base,
6437 ASCV_MSGIN_BEG,
6438 (uchar *)&ext_msg,
6439 sizeof(EXT_MSG) >> 1);
6440
6441 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6442 ext_msg.msg_req == EXTENDED_SDTR &&
6443 ext_msg.msg_len == MS_SDTR_LEN) {
6444 sdtr_accept = true;
6445 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
6446
6447 sdtr_accept = false;
6448 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
6449 }
6450 if ((ext_msg.xfer_period <
6451 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
6452 || (ext_msg.xfer_period >
6453 asc_dvc->sdtr_period_tbl[asc_dvc->
6454 max_sdtr_index])) {
6455 sdtr_accept = false;
6456 ext_msg.xfer_period =
6457 asc_dvc->sdtr_period_tbl[asc_dvc->
6458 min_sdtr_index];
6459 }
6460 if (sdtr_accept) {
6461 sdtr_data =
6462 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
6463 ext_msg.req_ack_offset);
6464 if ((sdtr_data == 0xFF)) {
6465
6466 q_cntl |= QC_MSG_OUT;
6467 asc_dvc->init_sdtr &= ~target_id;
6468 asc_dvc->sdtr_done &= ~target_id;
6469 AscSetChipSDTR(iop_base, asyn_sdtr,
6470 tid_no);
6471 boardp->sdtr_data[tid_no] = asyn_sdtr;
6472 }
6473 }
6474 if (ext_msg.req_ack_offset == 0) {
6475
6476 q_cntl &= ~QC_MSG_OUT;
6477 asc_dvc->init_sdtr &= ~target_id;
6478 asc_dvc->sdtr_done &= ~target_id;
6479 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6480 } else {
6481 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
6482 q_cntl &= ~QC_MSG_OUT;
6483 asc_dvc->sdtr_done |= target_id;
6484 asc_dvc->init_sdtr |= target_id;
6485 asc_dvc->pci_fix_asyn_xfer &=
6486 ~target_id;
6487 sdtr_data =
6488 AscCalSDTRData(asc_dvc,
6489 ext_msg.xfer_period,
6490 ext_msg.
6491 req_ack_offset);
6492 AscSetChipSDTR(iop_base, sdtr_data,
6493 tid_no);
6494 boardp->sdtr_data[tid_no] = sdtr_data;
6495 } else {
6496 q_cntl |= QC_MSG_OUT;
6497 AscMsgOutSDTR(asc_dvc,
6498 ext_msg.xfer_period,
6499 ext_msg.req_ack_offset);
6500 asc_dvc->pci_fix_asyn_xfer &=
6501 ~target_id;
6502 sdtr_data =
6503 AscCalSDTRData(asc_dvc,
6504 ext_msg.xfer_period,
6505 ext_msg.
6506 req_ack_offset);
6507 AscSetChipSDTR(iop_base, sdtr_data,
6508 tid_no);
6509 boardp->sdtr_data[tid_no] = sdtr_data;
6510 asc_dvc->sdtr_done |= target_id;
6511 asc_dvc->init_sdtr |= target_id;
6512 }
6513 }
6514
6515 AscWriteLramByte(iop_base,
6516 (ushort)(halt_q_addr +
6517 (ushort)ASC_SCSIQ_B_CNTL),
6518 q_cntl);
6519 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6520 return;
6521 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6522 ext_msg.msg_req == EXTENDED_WDTR &&
6523 ext_msg.msg_len == MS_WDTR_LEN) {
6524
6525 ext_msg.wdtr_width = 0;
6526 AscMemWordCopyPtrToLram(iop_base,
6527 ASCV_MSGOUT_BEG,
6528 (uchar *)&ext_msg,
6529 sizeof(EXT_MSG) >> 1);
6530 q_cntl |= QC_MSG_OUT;
6531 AscWriteLramByte(iop_base,
6532 (ushort)(halt_q_addr +
6533 (ushort)ASC_SCSIQ_B_CNTL),
6534 q_cntl);
6535 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6536 return;
6537 } else {
6538
6539 ext_msg.msg_type = MESSAGE_REJECT;
6540 AscMemWordCopyPtrToLram(iop_base,
6541 ASCV_MSGOUT_BEG,
6542 (uchar *)&ext_msg,
6543 sizeof(EXT_MSG) >> 1);
6544 q_cntl |= QC_MSG_OUT;
6545 AscWriteLramByte(iop_base,
6546 (ushort)(halt_q_addr +
6547 (ushort)ASC_SCSIQ_B_CNTL),
6548 q_cntl);
6549 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6550 return;
6551 }
6552 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
6553
6554 q_cntl |= QC_REQ_SENSE;
6555
6556 if ((asc_dvc->init_sdtr & target_id) != 0) {
6557
6558 asc_dvc->sdtr_done &= ~target_id;
6559
6560 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
6561 q_cntl |= QC_MSG_OUT;
6562 AscMsgOutSDTR(asc_dvc,
6563 asc_dvc->
6564 sdtr_period_tbl[(sdtr_data >> 4) &
6565 (uchar)(asc_dvc->
6566 max_sdtr_index -
6567 1)],
6568 (uchar)(sdtr_data & (uchar)
6569 ASC_SYN_MAX_OFFSET));
6570 }
6571
6572 AscWriteLramByte(iop_base,
6573 (ushort)(halt_q_addr +
6574 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6575
6576 tag_code = AscReadLramByte(iop_base,
6577 (ushort)(halt_q_addr + (ushort)
6578 ASC_SCSIQ_B_TAG_CODE));
6579 tag_code &= 0xDC;
6580 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
6581 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
6582 ) {
6583
6584 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
6585 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
6586
6587 }
6588 AscWriteLramByte(iop_base,
6589 (ushort)(halt_q_addr +
6590 (ushort)ASC_SCSIQ_B_TAG_CODE),
6591 tag_code);
6592
6593 q_status = AscReadLramByte(iop_base,
6594 (ushort)(halt_q_addr + (ushort)
6595 ASC_SCSIQ_B_STATUS));
6596 q_status |= (QS_READY | QS_BUSY);
6597 AscWriteLramByte(iop_base,
6598 (ushort)(halt_q_addr +
6599 (ushort)ASC_SCSIQ_B_STATUS),
6600 q_status);
6601
6602 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
6603 scsi_busy &= ~target_id;
6604 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6605
6606 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6607 return;
6608 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
6609
6610 AscMemWordCopyPtrFromLram(iop_base,
6611 ASCV_MSGOUT_BEG,
6612 (uchar *)&out_msg,
6613 sizeof(EXT_MSG) >> 1);
6614
6615 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
6616 (out_msg.msg_len == MS_SDTR_LEN) &&
6617 (out_msg.msg_req == EXTENDED_SDTR)) {
6618
6619 asc_dvc->init_sdtr &= ~target_id;
6620 asc_dvc->sdtr_done &= ~target_id;
6621 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6622 boardp->sdtr_data[tid_no] = asyn_sdtr;
6623 }
6624 q_cntl &= ~QC_MSG_OUT;
6625 AscWriteLramByte(iop_base,
6626 (ushort)(halt_q_addr +
6627 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6628 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6629 return;
6630 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
6631
6632 scsi_status = AscReadLramByte(iop_base,
6633 (ushort)((ushort)halt_q_addr +
6634 (ushort)
6635 ASC_SCSIQ_SCSI_STATUS));
6636 cur_dvc_qng =
6637 AscReadLramByte(iop_base,
6638 (ushort)((ushort)ASC_QADR_BEG +
6639 (ushort)target_ix));
6640 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
6641
6642 scsi_busy = AscReadLramByte(iop_base,
6643 (ushort)ASCV_SCSIBUSY_B);
6644 scsi_busy |= target_id;
6645 AscWriteLramByte(iop_base,
6646 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6647 asc_dvc->queue_full_or_busy |= target_id;
6648
6649 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
6650 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
6651 cur_dvc_qng -= 1;
6652 asc_dvc->max_dvc_qng[tid_no] =
6653 cur_dvc_qng;
6654
6655 AscWriteLramByte(iop_base,
6656 (ushort)((ushort)
6657 ASCV_MAX_DVC_QNG_BEG
6658 + (ushort)
6659 tid_no),
6660 cur_dvc_qng);
6661
6662 /*
6663 * Set the device queue depth to the
6664 * number of active requests when the
6665 * QUEUE FULL condition was encountered.
6666 */
6667 boardp->queue_full |= target_id;
6668 boardp->queue_full_cnt[tid_no] =
6669 cur_dvc_qng;
6670 }
6671 }
6672 }
6673 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6674 return;
6675 }
6676 return;
6677 }
6678
6679 /*
6680 * void
6681 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6682 *
6683 * Calling/Exit State:
6684 * none
6685 *
6686 * Description:
6687 * Input an ASC_QDONE_INFO structure from the chip
6688 */
6689 static void
6690 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6691 {
6692 int i;
6693 ushort word;
6694
6695 AscSetChipLramAddr(iop_base, s_addr);
6696 for (i = 0; i < 2 * words; i += 2) {
6697 if (i == 10) {
6698 continue;
6699 }
6700 word = inpw(iop_base + IOP_RAM_DATA);
6701 inbuf[i] = word & 0xff;
6702 inbuf[i + 1] = (word >> 8) & 0xff;
6703 }
6704 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
6705 }
6706
6707 static uchar
6708 _AscCopyLramScsiDoneQ(PortAddr iop_base,
6709 ushort q_addr,
6710 ASC_QDONE_INFO *scsiq, unsigned int max_dma_count)
6711 {
6712 ushort _val;
6713 uchar sg_queue_cnt;
6714
6715 DvcGetQinfo(iop_base,
6716 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
6717 (uchar *)scsiq,
6718 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
6719
6720 _val = AscReadLramWord(iop_base,
6721 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
6722 scsiq->q_status = (uchar)_val;
6723 scsiq->q_no = (uchar)(_val >> 8);
6724 _val = AscReadLramWord(iop_base,
6725 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6726 scsiq->cntl = (uchar)_val;
6727 sg_queue_cnt = (uchar)(_val >> 8);
6728 _val = AscReadLramWord(iop_base,
6729 (ushort)(q_addr +
6730 (ushort)ASC_SCSIQ_B_SENSE_LEN));
6731 scsiq->sense_len = (uchar)_val;
6732 scsiq->extra_bytes = (uchar)(_val >> 8);
6733
6734 /*
6735 * Read high word of remain bytes from alternate location.
6736 */
6737 scsiq->remain_bytes = (((u32)AscReadLramWord(iop_base,
6738 (ushort)(q_addr +
6739 (ushort)
6740 ASC_SCSIQ_W_ALT_DC1)))
6741 << 16);
6742 /*
6743 * Read low word of remain bytes from original location.
6744 */
6745 scsiq->remain_bytes += AscReadLramWord(iop_base,
6746 (ushort)(q_addr + (ushort)
6747 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
6748
6749 scsiq->remain_bytes &= max_dma_count;
6750 return sg_queue_cnt;
6751 }
6752
6753 /*
6754 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
6755 *
6756 * Interrupt callback function for the Narrow SCSI Asc Library.
6757 */
6758 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
6759 {
6760 struct asc_board *boardp = asc_dvc_varp->drv_ptr;
6761 u32 srb_tag;
6762 struct scsi_cmnd *scp;
6763
6764 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
6765 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
6766
6767 /*
6768 * Decrease the srb_tag by 1 to find the SCSI command
6769 */
6770 srb_tag = qdonep->d2.srb_tag - 1;
6771 scp = scsi_host_find_tag(boardp->shost, srb_tag);
6772 if (!scp)
6773 return;
6774
6775 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6776
6777 ASC_STATS(boardp->shost, callback);
6778
6779 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
6780 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
6781 /*
6782 * 'qdonep' contains the command's ending status.
6783 */
6784 switch (qdonep->d3.done_stat) {
6785 case QD_NO_ERROR:
6786 ASC_DBG(2, "QD_NO_ERROR\n");
6787 scp->result = 0;
6788
6789 /*
6790 * Check for an underrun condition.
6791 *
6792 * If there was no error and an underrun condition, then
6793 * return the number of underrun bytes.
6794 */
6795 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
6796 qdonep->remain_bytes <= scsi_bufflen(scp)) {
6797 ASC_DBG(1, "underrun condition %u bytes\n",
6798 (unsigned)qdonep->remain_bytes);
6799 scsi_set_resid(scp, qdonep->remain_bytes);
6800 }
6801 break;
6802
6803 case QD_WITH_ERROR:
6804 ASC_DBG(2, "QD_WITH_ERROR\n");
6805 switch (qdonep->d3.host_stat) {
6806 case QHSTA_NO_ERROR:
6807 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
6808 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
6809 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6810 SCSI_SENSE_BUFFERSIZE);
6811 /*
6812 * Note: The 'status_byte()' macro used by
6813 * target drivers defined in scsi.h shifts the
6814 * status byte returned by host drivers right
6815 * by 1 bit. This is why target drivers also
6816 * use right shifted status byte definitions.
6817 * For instance target drivers use
6818 * CHECK_CONDITION, defined to 0x1, instead of
6819 * the SCSI defined check condition value of
6820 * 0x2. Host drivers are supposed to return
6821 * the status byte as it is defined by SCSI.
6822 */
6823 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6824 STATUS_BYTE(qdonep->d3.scsi_stat);
6825 } else {
6826 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
6827 }
6828 break;
6829
6830 default:
6831 /* QHSTA error occurred */
6832 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
6833 scp->result = HOST_BYTE(DID_BAD_TARGET);
6834 break;
6835 }
6836 break;
6837
6838 case QD_ABORTED_BY_HOST:
6839 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
6840 scp->result =
6841 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
6842 scsi_msg) |
6843 STATUS_BYTE(qdonep->d3.scsi_stat);
6844 break;
6845
6846 default:
6847 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
6848 scp->result =
6849 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
6850 scsi_msg) |
6851 STATUS_BYTE(qdonep->d3.scsi_stat);
6852 break;
6853 }
6854
6855 /*
6856 * If the 'init_tidmask' bit isn't already set for the target and the
6857 * current request finished normally, then set the bit for the target
6858 * to indicate that a device is present.
6859 */
6860 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6861 qdonep->d3.done_stat == QD_NO_ERROR &&
6862 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
6863 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6864 }
6865
6866 asc_scsi_done(scp);
6867 }
6868
6869 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
6870 {
6871 uchar next_qp;
6872 uchar n_q_used;
6873 uchar sg_list_qp;
6874 uchar sg_queue_cnt;
6875 uchar q_cnt;
6876 uchar done_q_tail;
6877 uchar tid_no;
6878 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6879 ASC_SCSI_BIT_ID_TYPE target_id;
6880 PortAddr iop_base;
6881 ushort q_addr;
6882 ushort sg_q_addr;
6883 uchar cur_target_qng;
6884 ASC_QDONE_INFO scsiq_buf;
6885 ASC_QDONE_INFO *scsiq;
6886 bool false_overrun;
6887
6888 iop_base = asc_dvc->iop_base;
6889 n_q_used = 1;
6890 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
6891 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
6892 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
6893 next_qp = AscReadLramByte(iop_base,
6894 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
6895 if (next_qp != ASC_QLINK_END) {
6896 AscPutVarDoneQTail(iop_base, next_qp);
6897 q_addr = ASC_QNO_TO_QADDR(next_qp);
6898 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
6899 asc_dvc->max_dma_count);
6900 AscWriteLramByte(iop_base,
6901 (ushort)(q_addr +
6902 (ushort)ASC_SCSIQ_B_STATUS),
6903 (uchar)(scsiq->
6904 q_status & (uchar)~(QS_READY |
6905 QS_ABORTED)));
6906 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
6907 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
6908 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
6909 sg_q_addr = q_addr;
6910 sg_list_qp = next_qp;
6911 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
6912 sg_list_qp = AscReadLramByte(iop_base,
6913 (ushort)(sg_q_addr
6914 + (ushort)
6915 ASC_SCSIQ_B_FWD));
6916 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
6917 if (sg_list_qp == ASC_QLINK_END) {
6918 AscSetLibErrorCode(asc_dvc,
6919 ASCQ_ERR_SG_Q_LINKS);
6920 scsiq->d3.done_stat = QD_WITH_ERROR;
6921 scsiq->d3.host_stat =
6922 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
6923 goto FATAL_ERR_QDONE;
6924 }
6925 AscWriteLramByte(iop_base,
6926 (ushort)(sg_q_addr + (ushort)
6927 ASC_SCSIQ_B_STATUS),
6928 QS_FREE);
6929 }
6930 n_q_used = sg_queue_cnt + 1;
6931 AscPutVarDoneQTail(iop_base, sg_list_qp);
6932 }
6933 if (asc_dvc->queue_full_or_busy & target_id) {
6934 cur_target_qng = AscReadLramByte(iop_base,
6935 (ushort)((ushort)
6936 ASC_QADR_BEG
6937 + (ushort)
6938 scsiq->d2.
6939 target_ix));
6940 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
6941 scsi_busy = AscReadLramByte(iop_base, (ushort)
6942 ASCV_SCSIBUSY_B);
6943 scsi_busy &= ~target_id;
6944 AscWriteLramByte(iop_base,
6945 (ushort)ASCV_SCSIBUSY_B,
6946 scsi_busy);
6947 asc_dvc->queue_full_or_busy &= ~target_id;
6948 }
6949 }
6950 if (asc_dvc->cur_total_qng >= n_q_used) {
6951 asc_dvc->cur_total_qng -= n_q_used;
6952 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
6953 asc_dvc->cur_dvc_qng[tid_no]--;
6954 }
6955 } else {
6956 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
6957 scsiq->d3.done_stat = QD_WITH_ERROR;
6958 goto FATAL_ERR_QDONE;
6959 }
6960 if ((scsiq->d2.srb_tag == 0UL) ||
6961 ((scsiq->q_status & QS_ABORTED) != 0)) {
6962 return (0x11);
6963 } else if (scsiq->q_status == QS_DONE) {
6964 /*
6965 * This is also curious.
6966 * false_overrun will _always_ be set to 'false'
6967 */
6968 false_overrun = false;
6969 if (scsiq->extra_bytes != 0) {
6970 scsiq->remain_bytes += scsiq->extra_bytes;
6971 }
6972 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
6973 if (scsiq->d3.host_stat ==
6974 QHSTA_M_DATA_OVER_RUN) {
6975 if ((scsiq->
6976 cntl & (QC_DATA_IN | QC_DATA_OUT))
6977 == 0) {
6978 scsiq->d3.done_stat =
6979 QD_NO_ERROR;
6980 scsiq->d3.host_stat =
6981 QHSTA_NO_ERROR;
6982 } else if (false_overrun) {
6983 scsiq->d3.done_stat =
6984 QD_NO_ERROR;
6985 scsiq->d3.host_stat =
6986 QHSTA_NO_ERROR;
6987 }
6988 } else if (scsiq->d3.host_stat ==
6989 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
6990 AscStopChip(iop_base);
6991 AscSetChipControl(iop_base,
6992 (uchar)(CC_SCSI_RESET
6993 | CC_HALT));
6994 udelay(60);
6995 AscSetChipControl(iop_base, CC_HALT);
6996 AscSetChipStatus(iop_base,
6997 CIW_CLR_SCSI_RESET_INT);
6998 AscSetChipStatus(iop_base, 0);
6999 AscSetChipControl(iop_base, 0);
7000 }
7001 }
7002 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7003 asc_isr_callback(asc_dvc, scsiq);
7004 } else {
7005 if ((AscReadLramByte(iop_base,
7006 (ushort)(q_addr + (ushort)
7007 ASC_SCSIQ_CDB_BEG))
7008 == START_STOP)) {
7009 asc_dvc->unit_not_ready &= ~target_id;
7010 if (scsiq->d3.done_stat != QD_NO_ERROR) {
7011 asc_dvc->start_motor &=
7012 ~target_id;
7013 }
7014 }
7015 }
7016 return (1);
7017 } else {
7018 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
7019 FATAL_ERR_QDONE:
7020 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7021 asc_isr_callback(asc_dvc, scsiq);
7022 }
7023 return (0x80);
7024 }
7025 }
7026 return (0);
7027 }
7028
7029 static int AscISR(ASC_DVC_VAR *asc_dvc)
7030 {
7031 ASC_CS_TYPE chipstat;
7032 PortAddr iop_base;
7033 ushort saved_ram_addr;
7034 uchar ctrl_reg;
7035 uchar saved_ctrl_reg;
7036 int int_pending;
7037 int status;
7038 uchar host_flag;
7039
7040 iop_base = asc_dvc->iop_base;
7041 int_pending = ASC_FALSE;
7042
7043 if (AscIsIntPending(iop_base) == 0)
7044 return int_pending;
7045
7046 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
7047 return ASC_ERROR;
7048 }
7049 if (asc_dvc->in_critical_cnt != 0) {
7050 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
7051 return ASC_ERROR;
7052 }
7053 if (asc_dvc->is_in_int) {
7054 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
7055 return ASC_ERROR;
7056 }
7057 asc_dvc->is_in_int = true;
7058 ctrl_reg = AscGetChipControl(iop_base);
7059 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
7060 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
7061 chipstat = AscGetChipStatus(iop_base);
7062 if (chipstat & CSW_SCSI_RESET_LATCH) {
7063 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
7064 int i = 10;
7065 int_pending = ASC_TRUE;
7066 asc_dvc->sdtr_done = 0;
7067 saved_ctrl_reg &= (uchar)(~CC_HALT);
7068 while ((AscGetChipStatus(iop_base) &
7069 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
7070 mdelay(100);
7071 }
7072 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
7073 AscSetChipControl(iop_base, CC_HALT);
7074 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
7075 AscSetChipStatus(iop_base, 0);
7076 chipstat = AscGetChipStatus(iop_base);
7077 }
7078 }
7079 saved_ram_addr = AscGetChipLramAddr(iop_base);
7080 host_flag = AscReadLramByte(iop_base,
7081 ASCV_HOST_FLAG_B) &
7082 (uchar)(~ASC_HOST_FLAG_IN_ISR);
7083 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
7084 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
7085 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
7086 AscAckInterrupt(iop_base);
7087 int_pending = ASC_TRUE;
7088 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
7089 AscIsrChipHalted(asc_dvc);
7090 saved_ctrl_reg &= (uchar)(~CC_HALT);
7091 } else {
7092 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
7093 while (((status =
7094 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
7095 }
7096 } else {
7097 do {
7098 if ((status =
7099 AscIsrQDone(asc_dvc)) == 1) {
7100 break;
7101 }
7102 } while (status == 0x11);
7103 }
7104 if ((status & 0x80) != 0)
7105 int_pending = ASC_ERROR;
7106 }
7107 }
7108 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
7109 AscSetChipLramAddr(iop_base, saved_ram_addr);
7110 AscSetChipControl(iop_base, saved_ctrl_reg);
7111 asc_dvc->is_in_int = false;
7112 return int_pending;
7113 }
7114
7115 /*
7116 * advansys_reset()
7117 *
7118 * Reset the host associated with the command 'scp'.
7119 *
7120 * This function runs its own thread. Interrupts must be blocked but
7121 * sleeping is allowed and no locking other than for host structures is
7122 * required. Returns SUCCESS or FAILED.
7123 */
7124 static int advansys_reset(struct scsi_cmnd *scp)
7125 {
7126 struct Scsi_Host *shost = scp->device->host;
7127 struct asc_board *boardp = shost_priv(shost);
7128 unsigned long flags;
7129 int status;
7130 int ret = SUCCESS;
7131
7132 ASC_DBG(1, "0x%p\n", scp);
7133
7134 ASC_STATS(shost, reset);
7135
7136 scmd_printk(KERN_INFO, scp, "SCSI host reset started...\n");
7137
7138 if (ASC_NARROW_BOARD(boardp)) {
7139 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7140
7141 /* Reset the chip and SCSI bus. */
7142 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
7143 status = AscInitAsc1000Driver(asc_dvc);
7144
7145 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */
7146 if (asc_dvc->err_code || !asc_dvc->overrun_dma) {
7147 scmd_printk(KERN_INFO, scp, "SCSI host reset error: "
7148 "0x%x, status: 0x%x\n", asc_dvc->err_code,
7149 status);
7150 ret = FAILED;
7151 } else if (status) {
7152 scmd_printk(KERN_INFO, scp, "SCSI host reset warning: "
7153 "0x%x\n", status);
7154 } else {
7155 scmd_printk(KERN_INFO, scp, "SCSI host reset "
7156 "successful\n");
7157 }
7158
7159 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
7160 } else {
7161 /*
7162 * If the suggest reset bus flags are set, then reset the bus.
7163 * Otherwise only reset the device.
7164 */
7165 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
7166
7167 /*
7168 * Reset the chip and SCSI bus.
7169 */
7170 ASC_DBG(1, "before AdvResetChipAndSB()\n");
7171 switch (AdvResetChipAndSB(adv_dvc)) {
7172 case ASC_TRUE:
7173 scmd_printk(KERN_INFO, scp, "SCSI host reset "
7174 "successful\n");
7175 break;
7176 case ASC_FALSE:
7177 default:
7178 scmd_printk(KERN_INFO, scp, "SCSI host reset error\n");
7179 ret = FAILED;
7180 break;
7181 }
7182 spin_lock_irqsave(shost->host_lock, flags);
7183 AdvISR(adv_dvc);
7184 spin_unlock_irqrestore(shost->host_lock, flags);
7185 }
7186
7187 ASC_DBG(1, "ret %d\n", ret);
7188
7189 return ret;
7190 }
7191
7192 /*
7193 * advansys_biosparam()
7194 *
7195 * Translate disk drive geometry if the "BIOS greater than 1 GB"
7196 * support is enabled for a drive.
7197 *
7198 * ip (information pointer) is an int array with the following definition:
7199 * ip[0]: heads
7200 * ip[1]: sectors
7201 * ip[2]: cylinders
7202 */
7203 static int
7204 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
7205 sector_t capacity, int ip[])
7206 {
7207 struct asc_board *boardp = shost_priv(sdev->host);
7208
7209 ASC_DBG(1, "begin\n");
7210 ASC_STATS(sdev->host, biosparam);
7211 if (ASC_NARROW_BOARD(boardp)) {
7212 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
7213 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
7214 ip[0] = 255;
7215 ip[1] = 63;
7216 } else {
7217 ip[0] = 64;
7218 ip[1] = 32;
7219 }
7220 } else {
7221 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
7222 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
7223 ip[0] = 255;
7224 ip[1] = 63;
7225 } else {
7226 ip[0] = 64;
7227 ip[1] = 32;
7228 }
7229 }
7230 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
7231 ASC_DBG(1, "end\n");
7232 return 0;
7233 }
7234
7235 /*
7236 * First-level interrupt handler.
7237 *
7238 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
7239 */
7240 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
7241 {
7242 struct Scsi_Host *shost = dev_id;
7243 struct asc_board *boardp = shost_priv(shost);
7244 irqreturn_t result = IRQ_NONE;
7245
7246 ASC_DBG(2, "boardp 0x%p\n", boardp);
7247 spin_lock(shost->host_lock);
7248 if (ASC_NARROW_BOARD(boardp)) {
7249 if (AscIsIntPending(shost->io_port)) {
7250 result = IRQ_HANDLED;
7251 ASC_STATS(shost, interrupt);
7252 ASC_DBG(1, "before AscISR()\n");
7253 AscISR(&boardp->dvc_var.asc_dvc_var);
7254 }
7255 } else {
7256 ASC_DBG(1, "before AdvISR()\n");
7257 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
7258 result = IRQ_HANDLED;
7259 ASC_STATS(shost, interrupt);
7260 }
7261 }
7262 spin_unlock(shost->host_lock);
7263
7264 ASC_DBG(1, "end\n");
7265 return result;
7266 }
7267
7268 static bool AscHostReqRiscHalt(PortAddr iop_base)
7269 {
7270 int count = 0;
7271 bool sta = false;
7272 uchar saved_stop_code;
7273
7274 if (AscIsChipHalted(iop_base))
7275 return true;
7276 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
7277 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
7278 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
7279 do {
7280 if (AscIsChipHalted(iop_base)) {
7281 sta = true;
7282 break;
7283 }
7284 mdelay(100);
7285 } while (count++ < 20);
7286 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
7287 return sta;
7288 }
7289
7290 static bool
7291 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
7292 {
7293 bool sta = false;
7294
7295 if (AscHostReqRiscHalt(iop_base)) {
7296 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
7297 AscStartChip(iop_base);
7298 }
7299 return sta;
7300 }
7301
7302 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
7303 {
7304 char type = sdev->type;
7305 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
7306
7307 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
7308 return;
7309 if (asc_dvc->init_sdtr & tid_bits)
7310 return;
7311
7312 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
7313 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
7314
7315 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
7316 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
7317 (type == TYPE_ROM) || (type == TYPE_TAPE))
7318 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
7319
7320 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
7321 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
7322 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
7323 }
7324
7325 static void
7326 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
7327 {
7328 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
7329 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
7330
7331 if (sdev->lun == 0) {
7332 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
7333 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
7334 asc_dvc->init_sdtr |= tid_bit;
7335 } else {
7336 asc_dvc->init_sdtr &= ~tid_bit;
7337 }
7338
7339 if (orig_init_sdtr != asc_dvc->init_sdtr)
7340 AscAsyncFix(asc_dvc, sdev);
7341 }
7342
7343 if (sdev->tagged_supported) {
7344 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
7345 if (sdev->lun == 0) {
7346 asc_dvc->cfg->can_tagged_qng |= tid_bit;
7347 asc_dvc->use_tagged_qng |= tid_bit;
7348 }
7349 scsi_change_queue_depth(sdev,
7350 asc_dvc->max_dvc_qng[sdev->id]);
7351 }
7352 } else {
7353 if (sdev->lun == 0) {
7354 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
7355 asc_dvc->use_tagged_qng &= ~tid_bit;
7356 }
7357 }
7358
7359 if ((sdev->lun == 0) &&
7360 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
7361 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
7362 asc_dvc->cfg->disc_enable);
7363 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
7364 asc_dvc->use_tagged_qng);
7365 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
7366 asc_dvc->cfg->can_tagged_qng);
7367
7368 asc_dvc->max_dvc_qng[sdev->id] =
7369 asc_dvc->cfg->max_tag_qng[sdev->id];
7370 AscWriteLramByte(asc_dvc->iop_base,
7371 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
7372 asc_dvc->max_dvc_qng[sdev->id]);
7373 }
7374 }
7375
7376 /*
7377 * Wide Transfers
7378 *
7379 * If the EEPROM enabled WDTR for the device and the device supports wide
7380 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
7381 * write the new value to the microcode.
7382 */
7383 static void
7384 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
7385 {
7386 unsigned short cfg_word;
7387 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7388 if ((cfg_word & tidmask) != 0)
7389 return;
7390
7391 cfg_word |= tidmask;
7392 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7393
7394 /*
7395 * Clear the microcode SDTR and WDTR negotiation done indicators for
7396 * the target to cause it to negotiate with the new setting set above.
7397 * WDTR when accepted causes the target to enter asynchronous mode, so
7398 * SDTR must be negotiated.
7399 */
7400 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7401 cfg_word &= ~tidmask;
7402 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7403 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7404 cfg_word &= ~tidmask;
7405 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7406 }
7407
7408 /*
7409 * Synchronous Transfers
7410 *
7411 * If the EEPROM enabled SDTR for the device and the device
7412 * supports synchronous transfers, then turn on the device's
7413 * 'sdtr_able' bit. Write the new value to the microcode.
7414 */
7415 static void
7416 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
7417 {
7418 unsigned short cfg_word;
7419 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7420 if ((cfg_word & tidmask) != 0)
7421 return;
7422
7423 cfg_word |= tidmask;
7424 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7425
7426 /*
7427 * Clear the microcode "SDTR negotiation" done indicator for the
7428 * target to cause it to negotiate with the new setting set above.
7429 */
7430 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7431 cfg_word &= ~tidmask;
7432 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7433 }
7434
7435 /*
7436 * PPR (Parallel Protocol Request) Capable
7437 *
7438 * If the device supports DT mode, then it must be PPR capable.
7439 * The PPR message will be used in place of the SDTR and WDTR
7440 * messages to negotiate synchronous speed and offset, transfer
7441 * width, and protocol options.
7442 */
7443 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
7444 AdvPortAddr iop_base, unsigned short tidmask)
7445 {
7446 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7447 adv_dvc->ppr_able |= tidmask;
7448 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7449 }
7450
7451 static void
7452 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
7453 {
7454 AdvPortAddr iop_base = adv_dvc->iop_base;
7455 unsigned short tidmask = 1 << sdev->id;
7456
7457 if (sdev->lun == 0) {
7458 /*
7459 * Handle WDTR, SDTR, and Tag Queuing. If the feature
7460 * is enabled in the EEPROM and the device supports the
7461 * feature, then enable it in the microcode.
7462 */
7463
7464 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
7465 advansys_wide_enable_wdtr(iop_base, tidmask);
7466 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
7467 advansys_wide_enable_sdtr(iop_base, tidmask);
7468 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
7469 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
7470
7471 /*
7472 * Tag Queuing is disabled for the BIOS which runs in polled
7473 * mode and would see no benefit from Tag Queuing. Also by
7474 * disabling Tag Queuing in the BIOS devices with Tag Queuing
7475 * bugs will at least work with the BIOS.
7476 */
7477 if ((adv_dvc->tagqng_able & tidmask) &&
7478 sdev->tagged_supported) {
7479 unsigned short cfg_word;
7480 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
7481 cfg_word |= tidmask;
7482 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7483 cfg_word);
7484 AdvWriteByteLram(iop_base,
7485 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
7486 adv_dvc->max_dvc_qng);
7487 }
7488 }
7489
7490 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported)
7491 scsi_change_queue_depth(sdev, adv_dvc->max_dvc_qng);
7492 }
7493
7494 /*
7495 * Set the number of commands to queue per device for the
7496 * specified host adapter.
7497 */
7498 static int advansys_slave_configure(struct scsi_device *sdev)
7499 {
7500 struct asc_board *boardp = shost_priv(sdev->host);
7501
7502 if (ASC_NARROW_BOARD(boardp))
7503 advansys_narrow_slave_configure(sdev,
7504 &boardp->dvc_var.asc_dvc_var);
7505 else
7506 advansys_wide_slave_configure(sdev,
7507 &boardp->dvc_var.adv_dvc_var);
7508
7509 return 0;
7510 }
7511
7512 static __le32 advansys_get_sense_buffer_dma(struct scsi_cmnd *scp)
7513 {
7514 struct asc_board *board = shost_priv(scp->device->host);
7515 scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer,
7516 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7517 if (dma_mapping_error(board->dev, scp->SCp.dma_handle)) {
7518 ASC_DBG(1, "failed to map sense buffer\n");
7519 return 0;
7520 }
7521 dma_cache_sync(board->dev, scp->sense_buffer,
7522 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7523 return cpu_to_le32(scp->SCp.dma_handle);
7524 }
7525
7526 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
7527 struct asc_scsi_q *asc_scsi_q)
7528 {
7529 struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7530 int use_sg;
7531 u32 srb_tag;
7532
7533 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
7534
7535 /*
7536 * Set the srb_tag to the command tag + 1, as
7537 * srb_tag '0' is used internally by the chip.
7538 */
7539 srb_tag = scp->request->tag + 1;
7540 asc_scsi_q->q2.srb_tag = srb_tag;
7541
7542 /*
7543 * Build the ASC_SCSI_Q request.
7544 */
7545 asc_scsi_q->cdbptr = &scp->cmnd[0];
7546 asc_scsi_q->q2.cdb_len = scp->cmd_len;
7547 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
7548 asc_scsi_q->q1.target_lun = scp->device->lun;
7549 asc_scsi_q->q2.target_ix =
7550 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
7551 asc_scsi_q->q1.sense_addr = advansys_get_sense_buffer_dma(scp);
7552 asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE;
7553 if (!asc_scsi_q->q1.sense_addr)
7554 return ASC_BUSY;
7555
7556 /*
7557 * If there are any outstanding requests for the current target,
7558 * then every 255th request send an ORDERED request. This heuristic
7559 * tries to retain the benefit of request sorting while preventing
7560 * request starvation. 255 is the max number of tags or pending commands
7561 * a device may have outstanding.
7562 *
7563 * The request count is incremented below for every successfully
7564 * started request.
7565 *
7566 */
7567 if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
7568 (boardp->reqcnt[scp->device->id] % 255) == 0) {
7569 asc_scsi_q->q2.tag_code = ORDERED_QUEUE_TAG;
7570 } else {
7571 asc_scsi_q->q2.tag_code = SIMPLE_QUEUE_TAG;
7572 }
7573
7574 /* Build ASC_SCSI_Q */
7575 use_sg = scsi_dma_map(scp);
7576 if (use_sg < 0) {
7577 ASC_DBG(1, "failed to map sglist\n");
7578 return ASC_BUSY;
7579 } else if (use_sg > 0) {
7580 int sgcnt;
7581 struct scatterlist *slp;
7582 struct asc_sg_head *asc_sg_head;
7583
7584 if (use_sg > scp->device->host->sg_tablesize) {
7585 scmd_printk(KERN_ERR, scp, "use_sg %d > "
7586 "sg_tablesize %d\n", use_sg,
7587 scp->device->host->sg_tablesize);
7588 scsi_dma_unmap(scp);
7589 scp->result = HOST_BYTE(DID_ERROR);
7590 return ASC_ERROR;
7591 }
7592
7593 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
7594 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
7595 if (!asc_sg_head) {
7596 scsi_dma_unmap(scp);
7597 scp->result = HOST_BYTE(DID_SOFT_ERROR);
7598 return ASC_ERROR;
7599 }
7600
7601 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
7602 asc_scsi_q->sg_head = asc_sg_head;
7603 asc_scsi_q->q1.data_cnt = 0;
7604 asc_scsi_q->q1.data_addr = 0;
7605 /* This is a byte value, otherwise it would need to be swapped. */
7606 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
7607 ASC_STATS_ADD(scp->device->host, xfer_elem,
7608 asc_sg_head->entry_cnt);
7609
7610 /*
7611 * Convert scatter-gather list into ASC_SG_HEAD list.
7612 */
7613 scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
7614 asc_sg_head->sg_list[sgcnt].addr =
7615 cpu_to_le32(sg_dma_address(slp));
7616 asc_sg_head->sg_list[sgcnt].bytes =
7617 cpu_to_le32(sg_dma_len(slp));
7618 ASC_STATS_ADD(scp->device->host, xfer_sect,
7619 DIV_ROUND_UP(sg_dma_len(slp), 512));
7620 }
7621 }
7622
7623 ASC_STATS(scp->device->host, xfer_cnt);
7624
7625 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
7626 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
7627
7628 return ASC_NOERROR;
7629 }
7630
7631 /*
7632 * Build scatter-gather list for Adv Library (Wide Board).
7633 *
7634 * Additional ADV_SG_BLOCK structures will need to be allocated
7635 * if the total number of scatter-gather elements exceeds
7636 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
7637 * assumed to be physically contiguous.
7638 *
7639 * Return:
7640 * ADV_SUCCESS(1) - SG List successfully created
7641 * ADV_ERROR(-1) - SG List creation failed
7642 */
7643 static int
7644 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp,
7645 ADV_SCSI_REQ_Q *scsiqp, struct scsi_cmnd *scp, int use_sg)
7646 {
7647 adv_sgblk_t *sgblkp, *prev_sgblkp;
7648 struct scatterlist *slp;
7649 int sg_elem_cnt;
7650 ADV_SG_BLOCK *sg_block, *prev_sg_block;
7651 dma_addr_t sgblk_paddr;
7652 int i;
7653
7654 slp = scsi_sglist(scp);
7655 sg_elem_cnt = use_sg;
7656 prev_sgblkp = NULL;
7657 prev_sg_block = NULL;
7658 reqp->sgblkp = NULL;
7659
7660 for (;;) {
7661 /*
7662 * Allocate a 'adv_sgblk_t' structure from the board free
7663 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
7664 * (15) scatter-gather elements.
7665 */
7666 sgblkp = dma_pool_alloc(boardp->adv_sgblk_pool, GFP_ATOMIC,
7667 &sgblk_paddr);
7668 if (!sgblkp) {
7669 ASC_DBG(1, "no free adv_sgblk_t\n");
7670 ASC_STATS(scp->device->host, adv_build_nosg);
7671
7672 /*
7673 * Allocation failed. Free 'adv_sgblk_t' structures
7674 * already allocated for the request.
7675 */
7676 while ((sgblkp = reqp->sgblkp) != NULL) {
7677 /* Remove 'sgblkp' from the request list. */
7678 reqp->sgblkp = sgblkp->next_sgblkp;
7679 sgblkp->next_sgblkp = NULL;
7680 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
7681 sgblkp->sg_addr);
7682 }
7683 return ASC_BUSY;
7684 }
7685 /* Complete 'adv_sgblk_t' board allocation. */
7686 sgblkp->sg_addr = sgblk_paddr;
7687 sgblkp->next_sgblkp = NULL;
7688 sg_block = &sgblkp->sg_block;
7689
7690 /*
7691 * Check if this is the first 'adv_sgblk_t' for the
7692 * request.
7693 */
7694 if (reqp->sgblkp == NULL) {
7695 /* Request's first scatter-gather block. */
7696 reqp->sgblkp = sgblkp;
7697
7698 /*
7699 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
7700 * address pointers.
7701 */
7702 scsiqp->sg_list_ptr = sg_block;
7703 scsiqp->sg_real_addr = cpu_to_le32(sgblk_paddr);
7704 } else {
7705 /* Request's second or later scatter-gather block. */
7706 prev_sgblkp->next_sgblkp = sgblkp;
7707
7708 /*
7709 * Point the previous ADV_SG_BLOCK structure to
7710 * the newly allocated ADV_SG_BLOCK structure.
7711 */
7712 prev_sg_block->sg_ptr = cpu_to_le32(sgblk_paddr);
7713 }
7714
7715 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
7716 sg_block->sg_list[i].sg_addr =
7717 cpu_to_le32(sg_dma_address(slp));
7718 sg_block->sg_list[i].sg_count =
7719 cpu_to_le32(sg_dma_len(slp));
7720 ASC_STATS_ADD(scp->device->host, xfer_sect,
7721 DIV_ROUND_UP(sg_dma_len(slp), 512));
7722
7723 if (--sg_elem_cnt == 0) {
7724 /*
7725 * Last ADV_SG_BLOCK and scatter-gather entry.
7726 */
7727 sg_block->sg_cnt = i + 1;
7728 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
7729 return ADV_SUCCESS;
7730 }
7731 slp++;
7732 }
7733 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
7734 prev_sg_block = sg_block;
7735 prev_sgblkp = sgblkp;
7736 }
7737 }
7738
7739 /*
7740 * Build a request structure for the Adv Library (Wide Board).
7741 *
7742 * If an adv_req_t can not be allocated to issue the request,
7743 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
7744 *
7745 * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the
7746 * microcode for DMA addresses or math operations are byte swapped
7747 * to little-endian order.
7748 */
7749 static int
7750 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
7751 adv_req_t **adv_reqpp)
7752 {
7753 u32 srb_tag = scp->request->tag;
7754 adv_req_t *reqp;
7755 ADV_SCSI_REQ_Q *scsiqp;
7756 int ret;
7757 int use_sg;
7758 dma_addr_t sense_addr;
7759
7760 /*
7761 * Allocate an adv_req_t structure from the board to execute
7762 * the command.
7763 */
7764 reqp = &boardp->adv_reqp[srb_tag];
7765 if (reqp->cmndp && reqp->cmndp != scp ) {
7766 ASC_DBG(1, "no free adv_req_t\n");
7767 ASC_STATS(scp->device->host, adv_build_noreq);
7768 return ASC_BUSY;
7769 }
7770
7771 reqp->req_addr = boardp->adv_reqp_addr + (srb_tag * sizeof(adv_req_t));
7772
7773 scsiqp = &reqp->scsi_req_q;
7774
7775 /*
7776 * Initialize the structure.
7777 */
7778 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
7779
7780 /*
7781 * Set the srb_tag to the command tag.
7782 */
7783 scsiqp->srb_tag = srb_tag;
7784
7785 /*
7786 * Set 'host_scribble' to point to the adv_req_t structure.
7787 */
7788 reqp->cmndp = scp;
7789 scp->host_scribble = (void *)reqp;
7790
7791 /*
7792 * Build the ADV_SCSI_REQ_Q request.
7793 */
7794
7795 /* Set CDB length and copy it to the request structure. */
7796 scsiqp->cdb_len = scp->cmd_len;
7797 /* Copy first 12 CDB bytes to cdb[]. */
7798 memcpy(scsiqp->cdb, scp->cmnd, scp->cmd_len < 12 ? scp->cmd_len : 12);
7799 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
7800 if (scp->cmd_len > 12) {
7801 int cdb16_len = scp->cmd_len - 12;
7802
7803 memcpy(scsiqp->cdb16, &scp->cmnd[12], cdb16_len);
7804 }
7805
7806 scsiqp->target_id = scp->device->id;
7807 scsiqp->target_lun = scp->device->lun;
7808
7809 sense_addr = dma_map_single(boardp->dev, scp->sense_buffer,
7810 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7811 if (dma_mapping_error(boardp->dev, sense_addr)) {
7812 ASC_DBG(1, "failed to map sense buffer\n");
7813 ASC_STATS(scp->device->host, adv_build_noreq);
7814 return ASC_BUSY;
7815 }
7816 scsiqp->sense_addr = cpu_to_le32(sense_addr);
7817 scsiqp->sense_len = cpu_to_le32(SCSI_SENSE_BUFFERSIZE);
7818
7819 /* Build ADV_SCSI_REQ_Q */
7820
7821 use_sg = scsi_dma_map(scp);
7822 if (use_sg < 0) {
7823 ASC_DBG(1, "failed to map SG list\n");
7824 ASC_STATS(scp->device->host, adv_build_noreq);
7825 return ASC_BUSY;
7826 } else if (use_sg == 0) {
7827 /* Zero-length transfer */
7828 reqp->sgblkp = NULL;
7829 scsiqp->data_cnt = 0;
7830
7831 scsiqp->data_addr = 0;
7832 scsiqp->sg_list_ptr = NULL;
7833 scsiqp->sg_real_addr = 0;
7834 } else {
7835 if (use_sg > ADV_MAX_SG_LIST) {
7836 scmd_printk(KERN_ERR, scp, "use_sg %d > "
7837 "ADV_MAX_SG_LIST %d\n", use_sg,
7838 scp->device->host->sg_tablesize);
7839 scsi_dma_unmap(scp);
7840 scp->result = HOST_BYTE(DID_ERROR);
7841 reqp->cmndp = NULL;
7842 scp->host_scribble = NULL;
7843
7844 return ASC_ERROR;
7845 }
7846
7847 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
7848
7849 ret = adv_get_sglist(boardp, reqp, scsiqp, scp, use_sg);
7850 if (ret != ADV_SUCCESS) {
7851 scsi_dma_unmap(scp);
7852 scp->result = HOST_BYTE(DID_ERROR);
7853 reqp->cmndp = NULL;
7854 scp->host_scribble = NULL;
7855
7856 return ret;
7857 }
7858
7859 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
7860 }
7861
7862 ASC_STATS(scp->device->host, xfer_cnt);
7863
7864 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
7865 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
7866
7867 *adv_reqpp = reqp;
7868
7869 return ASC_NOERROR;
7870 }
7871
7872 static int AscSgListToQueue(int sg_list)
7873 {
7874 int n_sg_list_qs;
7875
7876 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
7877 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
7878 n_sg_list_qs++;
7879 return n_sg_list_qs + 1;
7880 }
7881
7882 static uint
7883 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
7884 {
7885 uint cur_used_qs;
7886 uint cur_free_qs;
7887 ASC_SCSI_BIT_ID_TYPE target_id;
7888 uchar tid_no;
7889
7890 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
7891 tid_no = ASC_TIX_TO_TID(target_ix);
7892 if ((asc_dvc->unit_not_ready & target_id) ||
7893 (asc_dvc->queue_full_or_busy & target_id)) {
7894 return 0;
7895 }
7896 if (n_qs == 1) {
7897 cur_used_qs = (uint) asc_dvc->cur_total_qng +
7898 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
7899 } else {
7900 cur_used_qs = (uint) asc_dvc->cur_total_qng +
7901 (uint) ASC_MIN_FREE_Q;
7902 }
7903 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
7904 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
7905 if (asc_dvc->cur_dvc_qng[tid_no] >=
7906 asc_dvc->max_dvc_qng[tid_no]) {
7907 return 0;
7908 }
7909 return cur_free_qs;
7910 }
7911 if (n_qs > 1) {
7912 if ((n_qs > asc_dvc->last_q_shortage)
7913 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
7914 asc_dvc->last_q_shortage = n_qs;
7915 }
7916 }
7917 return 0;
7918 }
7919
7920 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
7921 {
7922 ushort q_addr;
7923 uchar next_qp;
7924 uchar q_status;
7925
7926 q_addr = ASC_QNO_TO_QADDR(free_q_head);
7927 q_status = (uchar)AscReadLramByte(iop_base,
7928 (ushort)(q_addr +
7929 ASC_SCSIQ_B_STATUS));
7930 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
7931 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
7932 return next_qp;
7933 return ASC_QLINK_END;
7934 }
7935
7936 static uchar
7937 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
7938 {
7939 uchar i;
7940
7941 for (i = 0; i < n_free_q; i++) {
7942 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
7943 if (free_q_head == ASC_QLINK_END)
7944 break;
7945 }
7946 return free_q_head;
7947 }
7948
7949 /*
7950 * void
7951 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
7952 *
7953 * Calling/Exit State:
7954 * none
7955 *
7956 * Description:
7957 * Output an ASC_SCSI_Q structure to the chip
7958 */
7959 static void
7960 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
7961 {
7962 int i;
7963
7964 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
7965 AscSetChipLramAddr(iop_base, s_addr);
7966 for (i = 0; i < 2 * words; i += 2) {
7967 if (i == 4 || i == 20) {
7968 continue;
7969 }
7970 outpw(iop_base + IOP_RAM_DATA,
7971 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
7972 }
7973 }
7974
7975 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
7976 {
7977 ushort q_addr;
7978 uchar tid_no;
7979 uchar sdtr_data;
7980 uchar syn_period_ix;
7981 uchar syn_offset;
7982 PortAddr iop_base;
7983
7984 iop_base = asc_dvc->iop_base;
7985 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
7986 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
7987 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
7988 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
7989 syn_period_ix =
7990 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
7991 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
7992 AscMsgOutSDTR(asc_dvc,
7993 asc_dvc->sdtr_period_tbl[syn_period_ix],
7994 syn_offset);
7995 scsiq->q1.cntl |= QC_MSG_OUT;
7996 }
7997 q_addr = ASC_QNO_TO_QADDR(q_no);
7998 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
7999 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
8000 }
8001 scsiq->q1.status = QS_FREE;
8002 AscMemWordCopyPtrToLram(iop_base,
8003 q_addr + ASC_SCSIQ_CDB_BEG,
8004 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
8005
8006 DvcPutScsiQ(iop_base,
8007 q_addr + ASC_SCSIQ_CPY_BEG,
8008 (uchar *)&scsiq->q1.cntl,
8009 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
8010 AscWriteLramWord(iop_base,
8011 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
8012 (ushort)(((ushort)scsiq->q1.
8013 q_no << 8) | (ushort)QS_READY));
8014 return 1;
8015 }
8016
8017 static int
8018 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8019 {
8020 int sta;
8021 int i;
8022 ASC_SG_HEAD *sg_head;
8023 ASC_SG_LIST_Q scsi_sg_q;
8024 __le32 saved_data_addr;
8025 __le32 saved_data_cnt;
8026 PortAddr iop_base;
8027 ushort sg_list_dwords;
8028 ushort sg_index;
8029 ushort sg_entry_cnt;
8030 ushort q_addr;
8031 uchar next_qp;
8032
8033 iop_base = asc_dvc->iop_base;
8034 sg_head = scsiq->sg_head;
8035 saved_data_addr = scsiq->q1.data_addr;
8036 saved_data_cnt = scsiq->q1.data_cnt;
8037 scsiq->q1.data_addr = cpu_to_le32(sg_head->sg_list[0].addr);
8038 scsiq->q1.data_cnt = cpu_to_le32(sg_head->sg_list[0].bytes);
8039 /*
8040 * Set sg_entry_cnt to be the number of SG elements that
8041 * will fit in the allocated SG queues. It is minus 1, because
8042 * the first SG element is handled above.
8043 */
8044 sg_entry_cnt = sg_head->entry_cnt - 1;
8045
8046 if (sg_entry_cnt != 0) {
8047 scsiq->q1.cntl |= QC_SG_HEAD;
8048 q_addr = ASC_QNO_TO_QADDR(q_no);
8049 sg_index = 1;
8050 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
8051 scsi_sg_q.sg_head_qp = q_no;
8052 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
8053 for (i = 0; i < sg_head->queue_cnt; i++) {
8054 scsi_sg_q.seq_no = i + 1;
8055 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
8056 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
8057 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
8058 if (i == 0) {
8059 scsi_sg_q.sg_list_cnt =
8060 ASC_SG_LIST_PER_Q;
8061 scsi_sg_q.sg_cur_list_cnt =
8062 ASC_SG_LIST_PER_Q;
8063 } else {
8064 scsi_sg_q.sg_list_cnt =
8065 ASC_SG_LIST_PER_Q - 1;
8066 scsi_sg_q.sg_cur_list_cnt =
8067 ASC_SG_LIST_PER_Q - 1;
8068 }
8069 } else {
8070 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
8071 sg_list_dwords = sg_entry_cnt << 1;
8072 if (i == 0) {
8073 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
8074 scsi_sg_q.sg_cur_list_cnt =
8075 sg_entry_cnt;
8076 } else {
8077 scsi_sg_q.sg_list_cnt =
8078 sg_entry_cnt - 1;
8079 scsi_sg_q.sg_cur_list_cnt =
8080 sg_entry_cnt - 1;
8081 }
8082 sg_entry_cnt = 0;
8083 }
8084 next_qp = AscReadLramByte(iop_base,
8085 (ushort)(q_addr +
8086 ASC_SCSIQ_B_FWD));
8087 scsi_sg_q.q_no = next_qp;
8088 q_addr = ASC_QNO_TO_QADDR(next_qp);
8089 AscMemWordCopyPtrToLram(iop_base,
8090 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
8091 (uchar *)&scsi_sg_q,
8092 sizeof(ASC_SG_LIST_Q) >> 1);
8093 AscMemDWordCopyPtrToLram(iop_base,
8094 q_addr + ASC_SGQ_LIST_BEG,
8095 (uchar *)&sg_head->
8096 sg_list[sg_index],
8097 sg_list_dwords);
8098 sg_index += ASC_SG_LIST_PER_Q;
8099 scsiq->next_sg_index = sg_index;
8100 }
8101 } else {
8102 scsiq->q1.cntl &= ~QC_SG_HEAD;
8103 }
8104 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
8105 scsiq->q1.data_addr = saved_data_addr;
8106 scsiq->q1.data_cnt = saved_data_cnt;
8107 return (sta);
8108 }
8109
8110 static int
8111 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
8112 {
8113 PortAddr iop_base;
8114 uchar free_q_head;
8115 uchar next_qp;
8116 uchar tid_no;
8117 uchar target_ix;
8118 int sta;
8119
8120 iop_base = asc_dvc->iop_base;
8121 target_ix = scsiq->q2.target_ix;
8122 tid_no = ASC_TIX_TO_TID(target_ix);
8123 sta = 0;
8124 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
8125 if (n_q_required > 1) {
8126 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
8127 (uchar)n_q_required);
8128 if (next_qp != ASC_QLINK_END) {
8129 asc_dvc->last_q_shortage = 0;
8130 scsiq->sg_head->queue_cnt = n_q_required - 1;
8131 scsiq->q1.q_no = free_q_head;
8132 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
8133 free_q_head);
8134 }
8135 } else if (n_q_required == 1) {
8136 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
8137 if (next_qp != ASC_QLINK_END) {
8138 scsiq->q1.q_no = free_q_head;
8139 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
8140 }
8141 }
8142 if (sta == 1) {
8143 AscPutVarFreeQHead(iop_base, next_qp);
8144 asc_dvc->cur_total_qng += n_q_required;
8145 asc_dvc->cur_dvc_qng[tid_no]++;
8146 }
8147 return sta;
8148 }
8149
8150 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
8151 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
8152 INQUIRY,
8153 REQUEST_SENSE,
8154 READ_CAPACITY,
8155 READ_TOC,
8156 MODE_SELECT,
8157 MODE_SENSE,
8158 MODE_SELECT_10,
8159 MODE_SENSE_10,
8160 0xFF,
8161 0xFF,
8162 0xFF,
8163 0xFF,
8164 0xFF,
8165 0xFF,
8166 0xFF,
8167 0xFF
8168 };
8169
8170 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
8171 {
8172 PortAddr iop_base;
8173 int sta;
8174 int n_q_required;
8175 bool disable_syn_offset_one_fix;
8176 int i;
8177 u32 addr;
8178 ushort sg_entry_cnt = 0;
8179 ushort sg_entry_cnt_minus_one = 0;
8180 uchar target_ix;
8181 uchar tid_no;
8182 uchar sdtr_data;
8183 uchar extra_bytes;
8184 uchar scsi_cmd;
8185 uchar disable_cmd;
8186 ASC_SG_HEAD *sg_head;
8187 unsigned long data_cnt;
8188
8189 iop_base = asc_dvc->iop_base;
8190 sg_head = scsiq->sg_head;
8191 if (asc_dvc->err_code != 0)
8192 return ASC_ERROR;
8193 scsiq->q1.q_no = 0;
8194 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
8195 scsiq->q1.extra_bytes = 0;
8196 }
8197 sta = 0;
8198 target_ix = scsiq->q2.target_ix;
8199 tid_no = ASC_TIX_TO_TID(target_ix);
8200 n_q_required = 1;
8201 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
8202 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
8203 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
8204 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8205 AscMsgOutSDTR(asc_dvc,
8206 asc_dvc->
8207 sdtr_period_tbl[(sdtr_data >> 4) &
8208 (uchar)(asc_dvc->
8209 max_sdtr_index -
8210 1)],
8211 (uchar)(sdtr_data & (uchar)
8212 ASC_SYN_MAX_OFFSET));
8213 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
8214 }
8215 }
8216 if (asc_dvc->in_critical_cnt != 0) {
8217 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
8218 return ASC_ERROR;
8219 }
8220 asc_dvc->in_critical_cnt++;
8221 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8222 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
8223 asc_dvc->in_critical_cnt--;
8224 return ASC_ERROR;
8225 }
8226 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8227 asc_dvc->in_critical_cnt--;
8228 return ASC_ERROR;
8229 }
8230 if (sg_entry_cnt == 1) {
8231 scsiq->q1.data_addr = cpu_to_le32(sg_head->sg_list[0].addr);
8232 scsiq->q1.data_cnt = cpu_to_le32(sg_head->sg_list[0].bytes);
8233 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
8234 }
8235 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
8236 }
8237 scsi_cmd = scsiq->cdbptr[0];
8238 disable_syn_offset_one_fix = false;
8239 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
8240 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
8241 if (scsiq->q1.cntl & QC_SG_HEAD) {
8242 data_cnt = 0;
8243 for (i = 0; i < sg_entry_cnt; i++) {
8244 data_cnt += le32_to_cpu(sg_head->sg_list[i].
8245 bytes);
8246 }
8247 } else {
8248 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
8249 }
8250 if (data_cnt != 0UL) {
8251 if (data_cnt < 512UL) {
8252 disable_syn_offset_one_fix = true;
8253 } else {
8254 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
8255 i++) {
8256 disable_cmd =
8257 _syn_offset_one_disable_cmd[i];
8258 if (disable_cmd == 0xFF) {
8259 break;
8260 }
8261 if (scsi_cmd == disable_cmd) {
8262 disable_syn_offset_one_fix =
8263 true;
8264 break;
8265 }
8266 }
8267 }
8268 }
8269 }
8270 if (disable_syn_offset_one_fix) {
8271 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
8272 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
8273 ASC_TAG_FLAG_DISABLE_DISCONNECT);
8274 } else {
8275 scsiq->q2.tag_code &= 0x27;
8276 }
8277 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8278 if (asc_dvc->bug_fix_cntl) {
8279 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8280 if ((scsi_cmd == READ_6) ||
8281 (scsi_cmd == READ_10)) {
8282 addr = le32_to_cpu(sg_head->
8283 sg_list
8284 [sg_entry_cnt_minus_one].
8285 addr) +
8286 le32_to_cpu(sg_head->
8287 sg_list
8288 [sg_entry_cnt_minus_one].
8289 bytes);
8290 extra_bytes =
8291 (uchar)((ushort)addr & 0x0003);
8292 if ((extra_bytes != 0)
8293 &&
8294 ((scsiq->q2.
8295 tag_code &
8296 ASC_TAG_FLAG_EXTRA_BYTES)
8297 == 0)) {
8298 scsiq->q2.tag_code |=
8299 ASC_TAG_FLAG_EXTRA_BYTES;
8300 scsiq->q1.extra_bytes =
8301 extra_bytes;
8302 data_cnt =
8303 le32_to_cpu(sg_head->
8304 sg_list
8305 [sg_entry_cnt_minus_one].
8306 bytes);
8307 data_cnt -= extra_bytes;
8308 sg_head->
8309 sg_list
8310 [sg_entry_cnt_minus_one].
8311 bytes =
8312 cpu_to_le32(data_cnt);
8313 }
8314 }
8315 }
8316 }
8317 sg_head->entry_to_copy = sg_head->entry_cnt;
8318 n_q_required = AscSgListToQueue(sg_entry_cnt);
8319 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
8320 (uint) n_q_required)
8321 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8322 if ((sta =
8323 AscSendScsiQueue(asc_dvc, scsiq,
8324 n_q_required)) == 1) {
8325 asc_dvc->in_critical_cnt--;
8326 return (sta);
8327 }
8328 }
8329 } else {
8330 if (asc_dvc->bug_fix_cntl) {
8331 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8332 if ((scsi_cmd == READ_6) ||
8333 (scsi_cmd == READ_10)) {
8334 addr =
8335 le32_to_cpu(scsiq->q1.data_addr) +
8336 le32_to_cpu(scsiq->q1.data_cnt);
8337 extra_bytes =
8338 (uchar)((ushort)addr & 0x0003);
8339 if ((extra_bytes != 0)
8340 &&
8341 ((scsiq->q2.
8342 tag_code &
8343 ASC_TAG_FLAG_EXTRA_BYTES)
8344 == 0)) {
8345 data_cnt =
8346 le32_to_cpu(scsiq->q1.
8347 data_cnt);
8348 if (((ushort)data_cnt & 0x01FF)
8349 == 0) {
8350 scsiq->q2.tag_code |=
8351 ASC_TAG_FLAG_EXTRA_BYTES;
8352 data_cnt -= extra_bytes;
8353 scsiq->q1.data_cnt =
8354 cpu_to_le32
8355 (data_cnt);
8356 scsiq->q1.extra_bytes =
8357 extra_bytes;
8358 }
8359 }
8360 }
8361 }
8362 }
8363 n_q_required = 1;
8364 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
8365 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8366 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
8367 n_q_required)) == 1) {
8368 asc_dvc->in_critical_cnt--;
8369 return (sta);
8370 }
8371 }
8372 }
8373 asc_dvc->in_critical_cnt--;
8374 return (sta);
8375 }
8376
8377 /*
8378 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
8379 *
8380 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
8381 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
8382 * RISC to notify it a new command is ready to be executed.
8383 *
8384 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
8385 * set to SCSI_MAX_RETRY.
8386 *
8387 * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the microcode
8388 * for DMA addresses or math operations are byte swapped to little-endian
8389 * order.
8390 *
8391 * Return:
8392 * ADV_SUCCESS(1) - The request was successfully queued.
8393 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
8394 * request completes.
8395 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
8396 * host IC error.
8397 */
8398 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, adv_req_t *reqp)
8399 {
8400 AdvPortAddr iop_base;
8401 ADV_CARR_T *new_carrp;
8402 ADV_SCSI_REQ_Q *scsiq = &reqp->scsi_req_q;
8403
8404 /*
8405 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
8406 */
8407 if (scsiq->target_id > ADV_MAX_TID) {
8408 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
8409 scsiq->done_status = QD_WITH_ERROR;
8410 return ADV_ERROR;
8411 }
8412
8413 iop_base = asc_dvc->iop_base;
8414
8415 /*
8416 * Allocate a carrier ensuring at least one carrier always
8417 * remains on the freelist and initialize fields.
8418 */
8419 new_carrp = adv_get_next_carrier(asc_dvc);
8420 if (!new_carrp) {
8421 ASC_DBG(1, "No free carriers\n");
8422 return ADV_BUSY;
8423 }
8424
8425 asc_dvc->carr_pending_cnt++;
8426
8427 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
8428 scsiq->scsiq_ptr = cpu_to_le32(scsiq->srb_tag);
8429 scsiq->scsiq_rptr = cpu_to_le32(reqp->req_addr);
8430
8431 scsiq->carr_va = asc_dvc->icq_sp->carr_va;
8432 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
8433
8434 /*
8435 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
8436 * the microcode. The newly allocated stopper will become the new
8437 * stopper.
8438 */
8439 asc_dvc->icq_sp->areq_vpa = scsiq->scsiq_rptr;
8440
8441 /*
8442 * Set the 'next_vpa' pointer for the old stopper to be the
8443 * physical address of the new stopper. The RISC can only
8444 * follow physical addresses.
8445 */
8446 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
8447
8448 /*
8449 * Set the host adapter stopper pointer to point to the new carrier.
8450 */
8451 asc_dvc->icq_sp = new_carrp;
8452
8453 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8454 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8455 /*
8456 * Tickle the RISC to tell it to read its Command Queue Head pointer.
8457 */
8458 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
8459 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8460 /*
8461 * Clear the tickle value. In the ASC-3550 the RISC flag
8462 * command 'clr_tickle_a' does not work unless the host
8463 * value is cleared.
8464 */
8465 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8466 ADV_TICKLE_NOP);
8467 }
8468 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8469 /*
8470 * Notify the RISC a carrier is ready by writing the physical
8471 * address of the new carrier stopper to the COMMA register.
8472 */
8473 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8474 le32_to_cpu(new_carrp->carr_pa));
8475 }
8476
8477 return ADV_SUCCESS;
8478 }
8479
8480 /*
8481 * Execute a single 'Scsi_Cmnd'.
8482 */
8483 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
8484 {
8485 int ret, err_code;
8486 struct asc_board *boardp = shost_priv(scp->device->host);
8487
8488 ASC_DBG(1, "scp 0x%p\n", scp);
8489
8490 if (ASC_NARROW_BOARD(boardp)) {
8491 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
8492 struct asc_scsi_q asc_scsi_q;
8493
8494 ret = asc_build_req(boardp, scp, &asc_scsi_q);
8495 if (ret != ASC_NOERROR) {
8496 ASC_STATS(scp->device->host, build_error);
8497 return ret;
8498 }
8499
8500 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
8501 kfree(asc_scsi_q.sg_head);
8502 err_code = asc_dvc->err_code;
8503 } else {
8504 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
8505 adv_req_t *adv_reqp;
8506
8507 switch (adv_build_req(boardp, scp, &adv_reqp)) {
8508 case ASC_NOERROR:
8509 ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
8510 break;
8511 case ASC_BUSY:
8512 ASC_DBG(1, "adv_build_req ASC_BUSY\n");
8513 /*
8514 * The asc_stats fields 'adv_build_noreq' and
8515 * 'adv_build_nosg' count wide board busy conditions.
8516 * They are updated in adv_build_req and
8517 * adv_get_sglist, respectively.
8518 */
8519 return ASC_BUSY;
8520 case ASC_ERROR:
8521 default:
8522 ASC_DBG(1, "adv_build_req ASC_ERROR\n");
8523 ASC_STATS(scp->device->host, build_error);
8524 return ASC_ERROR;
8525 }
8526
8527 ret = AdvExeScsiQueue(adv_dvc, adv_reqp);
8528 err_code = adv_dvc->err_code;
8529 }
8530
8531 switch (ret) {
8532 case ASC_NOERROR:
8533 ASC_STATS(scp->device->host, exe_noerror);
8534 /*
8535 * Increment monotonically increasing per device
8536 * successful request counter. Wrapping doesn't matter.
8537 */
8538 boardp->reqcnt[scp->device->id]++;
8539 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
8540 break;
8541 case ASC_BUSY:
8542 ASC_DBG(1, "ExeScsiQueue() ASC_BUSY\n");
8543 ASC_STATS(scp->device->host, exe_busy);
8544 break;
8545 case ASC_ERROR:
8546 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
8547 "err_code 0x%x\n", err_code);
8548 ASC_STATS(scp->device->host, exe_error);
8549 scp->result = HOST_BYTE(DID_ERROR);
8550 break;
8551 default:
8552 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
8553 "err_code 0x%x\n", err_code);
8554 ASC_STATS(scp->device->host, exe_unknown);
8555 scp->result = HOST_BYTE(DID_ERROR);
8556 break;
8557 }
8558
8559 ASC_DBG(1, "end\n");
8560 return ret;
8561 }
8562
8563 /*
8564 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
8565 *
8566 * This function always returns 0. Command return status is saved
8567 * in the 'scp' result field.
8568 */
8569 static int
8570 advansys_queuecommand_lck(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
8571 {
8572 struct Scsi_Host *shost = scp->device->host;
8573 int asc_res, result = 0;
8574
8575 ASC_STATS(shost, queuecommand);
8576 scp->scsi_done = done;
8577
8578 asc_res = asc_execute_scsi_cmnd(scp);
8579
8580 switch (asc_res) {
8581 case ASC_NOERROR:
8582 break;
8583 case ASC_BUSY:
8584 result = SCSI_MLQUEUE_HOST_BUSY;
8585 break;
8586 case ASC_ERROR:
8587 default:
8588 asc_scsi_done(scp);
8589 break;
8590 }
8591
8592 return result;
8593 }
8594
8595 static DEF_SCSI_QCMD(advansys_queuecommand)
8596
8597 static ushort AscGetEisaChipCfg(PortAddr iop_base)
8598 {
8599 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8600 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
8601 return inpw(eisa_cfg_iop);
8602 }
8603
8604 /*
8605 * Return the BIOS address of the adapter at the specified
8606 * I/O port and with the specified bus type.
8607 */
8608 static unsigned short AscGetChipBiosAddress(PortAddr iop_base,
8609 unsigned short bus_type)
8610 {
8611 unsigned short cfg_lsw;
8612 unsigned short bios_addr;
8613
8614 /*
8615 * The PCI BIOS is re-located by the motherboard BIOS. Because
8616 * of this the driver can not determine where a PCI BIOS is
8617 * loaded and executes.
8618 */
8619 if (bus_type & ASC_IS_PCI)
8620 return 0;
8621
8622 if ((bus_type & ASC_IS_EISA) != 0) {
8623 cfg_lsw = AscGetEisaChipCfg(iop_base);
8624 cfg_lsw &= 0x000F;
8625 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
8626 return bios_addr;
8627 }
8628
8629 cfg_lsw = AscGetChipCfgLsw(iop_base);
8630
8631 /*
8632 * ISA PnP uses the top bit as the 32K BIOS flag
8633 */
8634 if (bus_type == ASC_IS_ISAPNP)
8635 cfg_lsw &= 0x7FFF;
8636 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
8637 return bios_addr;
8638 }
8639
8640 static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
8641 {
8642 ushort cfg_lsw;
8643
8644 if (AscGetChipScsiID(iop_base) == new_host_id) {
8645 return (new_host_id);
8646 }
8647 cfg_lsw = AscGetChipCfgLsw(iop_base);
8648 cfg_lsw &= 0xF8FF;
8649 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
8650 AscSetChipCfgLsw(iop_base, cfg_lsw);
8651 return (AscGetChipScsiID(iop_base));
8652 }
8653
8654 static unsigned char AscGetChipScsiCtrl(PortAddr iop_base)
8655 {
8656 unsigned char sc;
8657
8658 AscSetBank(iop_base, 1);
8659 sc = inp(iop_base + IOP_REG_SC);
8660 AscSetBank(iop_base, 0);
8661 return sc;
8662 }
8663
8664 static unsigned char AscGetChipVersion(PortAddr iop_base,
8665 unsigned short bus_type)
8666 {
8667 if (bus_type & ASC_IS_EISA) {
8668 PortAddr eisa_iop;
8669 unsigned char revision;
8670 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8671 (PortAddr) ASC_EISA_REV_IOP_MASK;
8672 revision = inp(eisa_iop);
8673 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
8674 }
8675 return AscGetChipVerNo(iop_base);
8676 }
8677
8678 #ifdef CONFIG_ISA
8679 static void AscEnableIsaDma(uchar dma_channel)
8680 {
8681 if (dma_channel < 4) {
8682 outp(0x000B, (ushort)(0xC0 | dma_channel));
8683 outp(0x000A, dma_channel);
8684 } else if (dma_channel < 8) {
8685 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
8686 outp(0x00D4, (ushort)(dma_channel - 4));
8687 }
8688 }
8689 #endif /* CONFIG_ISA */
8690
8691 static int AscStopQueueExe(PortAddr iop_base)
8692 {
8693 int count = 0;
8694
8695 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
8696 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
8697 ASC_STOP_REQ_RISC_STOP);
8698 do {
8699 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
8700 ASC_STOP_ACK_RISC_STOP) {
8701 return (1);
8702 }
8703 mdelay(100);
8704 } while (count++ < 20);
8705 }
8706 return (0);
8707 }
8708
8709 static unsigned int AscGetMaxDmaCount(ushort bus_type)
8710 {
8711 if (bus_type & ASC_IS_ISA)
8712 return ASC_MAX_ISA_DMA_COUNT;
8713 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
8714 return ASC_MAX_VL_DMA_COUNT;
8715 return ASC_MAX_PCI_DMA_COUNT;
8716 }
8717
8718 #ifdef CONFIG_ISA
8719 static ushort AscGetIsaDmaChannel(PortAddr iop_base)
8720 {
8721 ushort channel;
8722
8723 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
8724 if (channel == 0x03)
8725 return (0);
8726 else if (channel == 0x00)
8727 return (7);
8728 return (channel + 4);
8729 }
8730
8731 static ushort AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
8732 {
8733 ushort cfg_lsw;
8734 uchar value;
8735
8736 if ((dma_channel >= 5) && (dma_channel <= 7)) {
8737 if (dma_channel == 7)
8738 value = 0x00;
8739 else
8740 value = dma_channel - 4;
8741 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
8742 cfg_lsw |= value;
8743 AscSetChipCfgLsw(iop_base, cfg_lsw);
8744 return (AscGetIsaDmaChannel(iop_base));
8745 }
8746 return 0;
8747 }
8748
8749 static uchar AscGetIsaDmaSpeed(PortAddr iop_base)
8750 {
8751 uchar speed_value;
8752
8753 AscSetBank(iop_base, 1);
8754 speed_value = AscReadChipDmaSpeed(iop_base);
8755 speed_value &= 0x07;
8756 AscSetBank(iop_base, 0);
8757 return speed_value;
8758 }
8759
8760 static uchar AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
8761 {
8762 speed_value &= 0x07;
8763 AscSetBank(iop_base, 1);
8764 AscWriteChipDmaSpeed(iop_base, speed_value);
8765 AscSetBank(iop_base, 0);
8766 return AscGetIsaDmaSpeed(iop_base);
8767 }
8768 #endif /* CONFIG_ISA */
8769
8770 static void AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
8771 {
8772 int i;
8773 PortAddr iop_base;
8774 uchar chip_version;
8775
8776 iop_base = asc_dvc->iop_base;
8777 asc_dvc->err_code = 0;
8778 if ((asc_dvc->bus_type &
8779 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
8780 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
8781 }
8782 AscSetChipControl(iop_base, CC_HALT);
8783 AscSetChipStatus(iop_base, 0);
8784 asc_dvc->bug_fix_cntl = 0;
8785 asc_dvc->pci_fix_asyn_xfer = 0;
8786 asc_dvc->pci_fix_asyn_xfer_always = 0;
8787 /* asc_dvc->init_state initialized in AscInitGetConfig(). */
8788 asc_dvc->sdtr_done = 0;
8789 asc_dvc->cur_total_qng = 0;
8790 asc_dvc->is_in_int = false;
8791 asc_dvc->in_critical_cnt = 0;
8792 asc_dvc->last_q_shortage = 0;
8793 asc_dvc->use_tagged_qng = 0;
8794 asc_dvc->no_scam = 0;
8795 asc_dvc->unit_not_ready = 0;
8796 asc_dvc->queue_full_or_busy = 0;
8797 asc_dvc->redo_scam = 0;
8798 asc_dvc->res2 = 0;
8799 asc_dvc->min_sdtr_index = 0;
8800 asc_dvc->cfg->can_tagged_qng = 0;
8801 asc_dvc->cfg->cmd_qng_enabled = 0;
8802 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
8803 asc_dvc->init_sdtr = 0;
8804 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
8805 asc_dvc->scsi_reset_wait = 3;
8806 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
8807 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
8808 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
8809 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
8810 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
8811 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
8812 asc_dvc->cfg->chip_version = chip_version;
8813 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
8814 asc_dvc->max_sdtr_index = 7;
8815 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
8816 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
8817 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
8818 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
8819 asc_dvc->max_sdtr_index = 15;
8820 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
8821 AscSetExtraControl(iop_base,
8822 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
8823 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
8824 AscSetExtraControl(iop_base,
8825 (SEC_ACTIVE_NEGATE |
8826 SEC_ENABLE_FILTER));
8827 }
8828 }
8829 if (asc_dvc->bus_type == ASC_IS_PCI) {
8830 AscSetExtraControl(iop_base,
8831 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
8832 }
8833
8834 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
8835 #ifdef CONFIG_ISA
8836 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
8837 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
8838 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
8839 asc_dvc->bus_type = ASC_IS_ISAPNP;
8840 }
8841 asc_dvc->cfg->isa_dma_channel =
8842 (uchar)AscGetIsaDmaChannel(iop_base);
8843 }
8844 #endif /* CONFIG_ISA */
8845 for (i = 0; i <= ASC_MAX_TID; i++) {
8846 asc_dvc->cur_dvc_qng[i] = 0;
8847 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
8848 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
8849 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
8850 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
8851 }
8852 }
8853
8854 static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
8855 {
8856 int retry;
8857
8858 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
8859 unsigned char read_back;
8860 AscSetChipEEPCmd(iop_base, cmd_reg);
8861 mdelay(1);
8862 read_back = AscGetChipEEPCmd(iop_base);
8863 if (read_back == cmd_reg)
8864 return 1;
8865 }
8866 return 0;
8867 }
8868
8869 static void AscWaitEEPRead(void)
8870 {
8871 mdelay(1);
8872 }
8873
8874 static ushort AscReadEEPWord(PortAddr iop_base, uchar addr)
8875 {
8876 ushort read_wval;
8877 uchar cmd_reg;
8878
8879 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
8880 AscWaitEEPRead();
8881 cmd_reg = addr | ASC_EEP_CMD_READ;
8882 AscWriteEEPCmdReg(iop_base, cmd_reg);
8883 AscWaitEEPRead();
8884 read_wval = AscGetChipEEPData(iop_base);
8885 AscWaitEEPRead();
8886 return read_wval;
8887 }
8888
8889 static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
8890 ushort bus_type)
8891 {
8892 ushort wval;
8893 ushort sum;
8894 ushort *wbuf;
8895 int cfg_beg;
8896 int cfg_end;
8897 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
8898 int s_addr;
8899
8900 wbuf = (ushort *)cfg_buf;
8901 sum = 0;
8902 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
8903 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
8904 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
8905 sum += *wbuf;
8906 }
8907 if (bus_type & ASC_IS_VL) {
8908 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
8909 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
8910 } else {
8911 cfg_beg = ASC_EEP_DVC_CFG_BEG;
8912 cfg_end = ASC_EEP_MAX_DVC_ADDR;
8913 }
8914 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
8915 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
8916 if (s_addr <= uchar_end_in_config) {
8917 /*
8918 * Swap all char fields - must unswap bytes already swapped
8919 * by AscReadEEPWord().
8920 */
8921 *wbuf = le16_to_cpu(wval);
8922 } else {
8923 /* Don't swap word field at the end - cntl field. */
8924 *wbuf = wval;
8925 }
8926 sum += wval; /* Checksum treats all EEPROM data as words. */
8927 }
8928 /*
8929 * Read the checksum word which will be compared against 'sum'
8930 * by the caller. Word field already swapped.
8931 */
8932 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
8933 return sum;
8934 }
8935
8936 static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
8937 {
8938 PortAddr iop_base;
8939 ushort q_addr;
8940 ushort saved_word;
8941 int sta;
8942
8943 iop_base = asc_dvc->iop_base;
8944 sta = 0;
8945 q_addr = ASC_QNO_TO_QADDR(241);
8946 saved_word = AscReadLramWord(iop_base, q_addr);
8947 AscSetChipLramAddr(iop_base, q_addr);
8948 AscSetChipLramData(iop_base, 0x55AA);
8949 mdelay(10);
8950 AscSetChipLramAddr(iop_base, q_addr);
8951 if (AscGetChipLramData(iop_base) == 0x55AA) {
8952 sta = 1;
8953 AscWriteLramWord(iop_base, q_addr, saved_word);
8954 }
8955 return (sta);
8956 }
8957
8958 static void AscWaitEEPWrite(void)
8959 {
8960 mdelay(20);
8961 }
8962
8963 static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
8964 {
8965 ushort read_back;
8966 int retry;
8967
8968 retry = 0;
8969 while (true) {
8970 AscSetChipEEPData(iop_base, data_reg);
8971 mdelay(1);
8972 read_back = AscGetChipEEPData(iop_base);
8973 if (read_back == data_reg) {
8974 return (1);
8975 }
8976 if (retry++ > ASC_EEP_MAX_RETRY) {
8977 return (0);
8978 }
8979 }
8980 }
8981
8982 static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
8983 {
8984 ushort read_wval;
8985
8986 read_wval = AscReadEEPWord(iop_base, addr);
8987 if (read_wval != word_val) {
8988 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
8989 AscWaitEEPRead();
8990 AscWriteEEPDataReg(iop_base, word_val);
8991 AscWaitEEPRead();
8992 AscWriteEEPCmdReg(iop_base,
8993 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
8994 AscWaitEEPWrite();
8995 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
8996 AscWaitEEPRead();
8997 return (AscReadEEPWord(iop_base, addr));
8998 }
8999 return (read_wval);
9000 }
9001
9002 static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9003 ushort bus_type)
9004 {
9005 int n_error;
9006 ushort *wbuf;
9007 ushort word;
9008 ushort sum;
9009 int s_addr;
9010 int cfg_beg;
9011 int cfg_end;
9012 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9013
9014 wbuf = (ushort *)cfg_buf;
9015 n_error = 0;
9016 sum = 0;
9017 /* Write two config words; AscWriteEEPWord() will swap bytes. */
9018 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9019 sum += *wbuf;
9020 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9021 n_error++;
9022 }
9023 }
9024 if (bus_type & ASC_IS_VL) {
9025 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9026 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9027 } else {
9028 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9029 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9030 }
9031 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9032 if (s_addr <= uchar_end_in_config) {
9033 /*
9034 * This is a char field. Swap char fields before they are
9035 * swapped again by AscWriteEEPWord().
9036 */
9037 word = cpu_to_le16(*wbuf);
9038 if (word !=
9039 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
9040 n_error++;
9041 }
9042 } else {
9043 /* Don't swap word field at the end - cntl field. */
9044 if (*wbuf !=
9045 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9046 n_error++;
9047 }
9048 }
9049 sum += *wbuf; /* Checksum calculated from word values. */
9050 }
9051 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
9052 *wbuf = sum;
9053 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
9054 n_error++;
9055 }
9056
9057 /* Read EEPROM back again. */
9058 wbuf = (ushort *)cfg_buf;
9059 /*
9060 * Read two config words; Byte-swapping done by AscReadEEPWord().
9061 */
9062 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9063 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
9064 n_error++;
9065 }
9066 }
9067 if (bus_type & ASC_IS_VL) {
9068 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9069 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9070 } else {
9071 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9072 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9073 }
9074 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9075 if (s_addr <= uchar_end_in_config) {
9076 /*
9077 * Swap all char fields. Must unswap bytes already swapped
9078 * by AscReadEEPWord().
9079 */
9080 word =
9081 le16_to_cpu(AscReadEEPWord
9082 (iop_base, (uchar)s_addr));
9083 } else {
9084 /* Don't swap word field at the end - cntl field. */
9085 word = AscReadEEPWord(iop_base, (uchar)s_addr);
9086 }
9087 if (*wbuf != word) {
9088 n_error++;
9089 }
9090 }
9091 /* Read checksum; Byte swapping not needed. */
9092 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
9093 n_error++;
9094 }
9095 return n_error;
9096 }
9097
9098 static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9099 ushort bus_type)
9100 {
9101 int retry;
9102 int n_error;
9103
9104 retry = 0;
9105 while (true) {
9106 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
9107 bus_type)) == 0) {
9108 break;
9109 }
9110 if (++retry > ASC_EEP_MAX_RETRY) {
9111 break;
9112 }
9113 }
9114 return n_error;
9115 }
9116
9117 static int AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
9118 {
9119 ASCEEP_CONFIG eep_config_buf;
9120 ASCEEP_CONFIG *eep_config;
9121 PortAddr iop_base;
9122 ushort chksum;
9123 ushort warn_code;
9124 ushort cfg_msw, cfg_lsw;
9125 int i;
9126 int write_eep = 0;
9127
9128 iop_base = asc_dvc->iop_base;
9129 warn_code = 0;
9130 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
9131 AscStopQueueExe(iop_base);
9132 if ((AscStopChip(iop_base)) ||
9133 (AscGetChipScsiCtrl(iop_base) != 0)) {
9134 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
9135 AscResetChipAndScsiBus(asc_dvc);
9136 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
9137 }
9138 if (!AscIsChipHalted(iop_base)) {
9139 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
9140 return (warn_code);
9141 }
9142 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
9143 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
9144 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
9145 return (warn_code);
9146 }
9147 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
9148 cfg_msw = AscGetChipCfgMsw(iop_base);
9149 cfg_lsw = AscGetChipCfgLsw(iop_base);
9150 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9151 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9152 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9153 AscSetChipCfgMsw(iop_base, cfg_msw);
9154 }
9155 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
9156 ASC_DBG(1, "chksum 0x%x\n", chksum);
9157 if (chksum == 0) {
9158 chksum = 0xaa55;
9159 }
9160 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9161 warn_code |= ASC_WARN_AUTO_CONFIG;
9162 if (asc_dvc->cfg->chip_version == 3) {
9163 if (eep_config->cfg_lsw != cfg_lsw) {
9164 warn_code |= ASC_WARN_EEPROM_RECOVER;
9165 eep_config->cfg_lsw =
9166 AscGetChipCfgLsw(iop_base);
9167 }
9168 if (eep_config->cfg_msw != cfg_msw) {
9169 warn_code |= ASC_WARN_EEPROM_RECOVER;
9170 eep_config->cfg_msw =
9171 AscGetChipCfgMsw(iop_base);
9172 }
9173 }
9174 }
9175 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9176 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
9177 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
9178 if (chksum != eep_config->chksum) {
9179 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
9180 ASC_CHIP_VER_PCI_ULTRA_3050) {
9181 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
9182 eep_config->init_sdtr = 0xFF;
9183 eep_config->disc_enable = 0xFF;
9184 eep_config->start_motor = 0xFF;
9185 eep_config->use_cmd_qng = 0;
9186 eep_config->max_total_qng = 0xF0;
9187 eep_config->max_tag_qng = 0x20;
9188 eep_config->cntl = 0xBFFF;
9189 ASC_EEP_SET_CHIP_ID(eep_config, 7);
9190 eep_config->no_scam = 0;
9191 eep_config->adapter_info[0] = 0;
9192 eep_config->adapter_info[1] = 0;
9193 eep_config->adapter_info[2] = 0;
9194 eep_config->adapter_info[3] = 0;
9195 eep_config->adapter_info[4] = 0;
9196 /* Indicate EEPROM-less board. */
9197 eep_config->adapter_info[5] = 0xBB;
9198 } else {
9199 ASC_PRINT
9200 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
9201 write_eep = 1;
9202 warn_code |= ASC_WARN_EEPROM_CHKSUM;
9203 }
9204 }
9205 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
9206 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
9207 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
9208 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
9209 asc_dvc->start_motor = eep_config->start_motor;
9210 asc_dvc->dvc_cntl = eep_config->cntl;
9211 asc_dvc->no_scam = eep_config->no_scam;
9212 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
9213 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
9214 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
9215 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
9216 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
9217 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
9218 if (!AscTestExternalLram(asc_dvc)) {
9219 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
9220 ASC_IS_PCI_ULTRA)) {
9221 eep_config->max_total_qng =
9222 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
9223 eep_config->max_tag_qng =
9224 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
9225 } else {
9226 eep_config->cfg_msw |= 0x0800;
9227 cfg_msw |= 0x0800;
9228 AscSetChipCfgMsw(iop_base, cfg_msw);
9229 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
9230 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
9231 }
9232 } else {
9233 }
9234 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
9235 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
9236 }
9237 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
9238 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
9239 }
9240 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
9241 eep_config->max_tag_qng = eep_config->max_total_qng;
9242 }
9243 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
9244 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
9245 }
9246 asc_dvc->max_total_qng = eep_config->max_total_qng;
9247 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
9248 eep_config->use_cmd_qng) {
9249 eep_config->disc_enable = eep_config->use_cmd_qng;
9250 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9251 }
9252 ASC_EEP_SET_CHIP_ID(eep_config,
9253 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
9254 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
9255 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
9256 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
9257 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
9258 }
9259
9260 for (i = 0; i <= ASC_MAX_TID; i++) {
9261 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
9262 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
9263 asc_dvc->cfg->sdtr_period_offset[i] =
9264 (uchar)(ASC_DEF_SDTR_OFFSET |
9265 (asc_dvc->min_sdtr_index << 4));
9266 }
9267 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
9268 if (write_eep) {
9269 if ((i = AscSetEEPConfig(iop_base, eep_config,
9270 asc_dvc->bus_type)) != 0) {
9271 ASC_PRINT1
9272 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
9273 i);
9274 } else {
9275 ASC_PRINT
9276 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
9277 }
9278 }
9279 return (warn_code);
9280 }
9281
9282 static int AscInitGetConfig(struct Scsi_Host *shost)
9283 {
9284 struct asc_board *board = shost_priv(shost);
9285 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9286 unsigned short warn_code = 0;
9287
9288 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
9289 if (asc_dvc->err_code != 0)
9290 return asc_dvc->err_code;
9291
9292 if (AscFindSignature(asc_dvc->iop_base)) {
9293 AscInitAscDvcVar(asc_dvc);
9294 warn_code = AscInitFromEEP(asc_dvc);
9295 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
9296 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
9297 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
9298 } else {
9299 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9300 }
9301
9302 switch (warn_code) {
9303 case 0: /* No error */
9304 break;
9305 case ASC_WARN_IO_PORT_ROTATE:
9306 shost_printk(KERN_WARNING, shost, "I/O port address "
9307 "modified\n");
9308 break;
9309 case ASC_WARN_AUTO_CONFIG:
9310 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9311 "enabled\n");
9312 break;
9313 case ASC_WARN_EEPROM_CHKSUM:
9314 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9315 break;
9316 case ASC_WARN_IRQ_MODIFIED:
9317 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9318 break;
9319 case ASC_WARN_CMD_QNG_CONFLICT:
9320 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
9321 "disconnects\n");
9322 break;
9323 default:
9324 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9325 warn_code);
9326 break;
9327 }
9328
9329 if (asc_dvc->err_code != 0)
9330 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9331 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9332
9333 return asc_dvc->err_code;
9334 }
9335
9336 static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
9337 {
9338 struct asc_board *board = shost_priv(shost);
9339 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9340 PortAddr iop_base = asc_dvc->iop_base;
9341 unsigned short cfg_msw;
9342 unsigned short warn_code = 0;
9343
9344 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
9345 if (asc_dvc->err_code != 0)
9346 return asc_dvc->err_code;
9347 if (!AscFindSignature(asc_dvc->iop_base)) {
9348 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9349 return asc_dvc->err_code;
9350 }
9351
9352 cfg_msw = AscGetChipCfgMsw(iop_base);
9353 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9354 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9355 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9356 AscSetChipCfgMsw(iop_base, cfg_msw);
9357 }
9358 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
9359 asc_dvc->cfg->cmd_qng_enabled) {
9360 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
9361 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9362 }
9363 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9364 warn_code |= ASC_WARN_AUTO_CONFIG;
9365 }
9366 #ifdef CONFIG_PCI
9367 if (asc_dvc->bus_type & ASC_IS_PCI) {
9368 cfg_msw &= 0xFFC0;
9369 AscSetChipCfgMsw(iop_base, cfg_msw);
9370 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
9371 } else {
9372 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
9373 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
9374 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
9375 asc_dvc->bug_fix_cntl |=
9376 ASC_BUG_FIX_ASYN_USE_SYN;
9377 }
9378 }
9379 } else
9380 #endif /* CONFIG_PCI */
9381 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
9382 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
9383 == ASC_CHIP_VER_ASYN_BUG) {
9384 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
9385 }
9386 }
9387 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
9388 asc_dvc->cfg->chip_scsi_id) {
9389 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
9390 }
9391 #ifdef CONFIG_ISA
9392 if (asc_dvc->bus_type & ASC_IS_ISA) {
9393 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
9394 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
9395 }
9396 #endif /* CONFIG_ISA */
9397
9398 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
9399
9400 switch (warn_code) {
9401 case 0: /* No error. */
9402 break;
9403 case ASC_WARN_IO_PORT_ROTATE:
9404 shost_printk(KERN_WARNING, shost, "I/O port address "
9405 "modified\n");
9406 break;
9407 case ASC_WARN_AUTO_CONFIG:
9408 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9409 "enabled\n");
9410 break;
9411 case ASC_WARN_EEPROM_CHKSUM:
9412 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9413 break;
9414 case ASC_WARN_IRQ_MODIFIED:
9415 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9416 break;
9417 case ASC_WARN_CMD_QNG_CONFLICT:
9418 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
9419 "disconnects\n");
9420 break;
9421 default:
9422 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9423 warn_code);
9424 break;
9425 }
9426
9427 if (asc_dvc->err_code != 0)
9428 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9429 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9430
9431 return asc_dvc->err_code;
9432 }
9433
9434 /*
9435 * EEPROM Configuration.
9436 *
9437 * All drivers should use this structure to set the default EEPROM
9438 * configuration. The BIOS now uses this structure when it is built.
9439 * Additional structure information can be found in a_condor.h where
9440 * the structure is defined.
9441 *
9442 * The *_Field_IsChar structs are needed to correct for endianness.
9443 * These values are read from the board 16 bits at a time directly
9444 * into the structs. Because some fields are char, the values will be
9445 * in the wrong order. The *_Field_IsChar tells when to flip the
9446 * bytes. Data read and written to PCI memory is automatically swapped
9447 * on big-endian platforms so char fields read as words are actually being
9448 * unswapped on big-endian platforms.
9449 */
9450 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = {
9451 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
9452 0x0000, /* cfg_msw */
9453 0xFFFF, /* disc_enable */
9454 0xFFFF, /* wdtr_able */
9455 0xFFFF, /* sdtr_able */
9456 0xFFFF, /* start_motor */
9457 0xFFFF, /* tagqng_able */
9458 0xFFFF, /* bios_scan */
9459 0, /* scam_tolerant */
9460 7, /* adapter_scsi_id */
9461 0, /* bios_boot_delay */
9462 3, /* scsi_reset_delay */
9463 0, /* bios_id_lun */
9464 0, /* termination */
9465 0, /* reserved1 */
9466 0xFFE7, /* bios_ctrl */
9467 0xFFFF, /* ultra_able */
9468 0, /* reserved2 */
9469 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
9470 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9471 0, /* dvc_cntl */
9472 0, /* bug_fix */
9473 0, /* serial_number_word1 */
9474 0, /* serial_number_word2 */
9475 0, /* serial_number_word3 */
9476 0, /* check_sum */
9477 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9478 , /* oem_name[16] */
9479 0, /* dvc_err_code */
9480 0, /* adv_err_code */
9481 0, /* adv_err_addr */
9482 0, /* saved_dvc_err_code */
9483 0, /* saved_adv_err_code */
9484 0, /* saved_adv_err_addr */
9485 0 /* num_of_err */
9486 };
9487
9488 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = {
9489 0, /* cfg_lsw */
9490 0, /* cfg_msw */
9491 0, /* -disc_enable */
9492 0, /* wdtr_able */
9493 0, /* sdtr_able */
9494 0, /* start_motor */
9495 0, /* tagqng_able */
9496 0, /* bios_scan */
9497 0, /* scam_tolerant */
9498 1, /* adapter_scsi_id */
9499 1, /* bios_boot_delay */
9500 1, /* scsi_reset_delay */
9501 1, /* bios_id_lun */
9502 1, /* termination */
9503 1, /* reserved1 */
9504 0, /* bios_ctrl */
9505 0, /* ultra_able */
9506 0, /* reserved2 */
9507 1, /* max_host_qng */
9508 1, /* max_dvc_qng */
9509 0, /* dvc_cntl */
9510 0, /* bug_fix */
9511 0, /* serial_number_word1 */
9512 0, /* serial_number_word2 */
9513 0, /* serial_number_word3 */
9514 0, /* check_sum */
9515 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9516 , /* oem_name[16] */
9517 0, /* dvc_err_code */
9518 0, /* adv_err_code */
9519 0, /* adv_err_addr */
9520 0, /* saved_dvc_err_code */
9521 0, /* saved_adv_err_code */
9522 0, /* saved_adv_err_addr */
9523 0 /* num_of_err */
9524 };
9525
9526 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = {
9527 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9528 0x0000, /* 01 cfg_msw */
9529 0xFFFF, /* 02 disc_enable */
9530 0xFFFF, /* 03 wdtr_able */
9531 0x4444, /* 04 sdtr_speed1 */
9532 0xFFFF, /* 05 start_motor */
9533 0xFFFF, /* 06 tagqng_able */
9534 0xFFFF, /* 07 bios_scan */
9535 0, /* 08 scam_tolerant */
9536 7, /* 09 adapter_scsi_id */
9537 0, /* bios_boot_delay */
9538 3, /* 10 scsi_reset_delay */
9539 0, /* bios_id_lun */
9540 0, /* 11 termination_se */
9541 0, /* termination_lvd */
9542 0xFFE7, /* 12 bios_ctrl */
9543 0x4444, /* 13 sdtr_speed2 */
9544 0x4444, /* 14 sdtr_speed3 */
9545 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9546 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9547 0, /* 16 dvc_cntl */
9548 0x4444, /* 17 sdtr_speed4 */
9549 0, /* 18 serial_number_word1 */
9550 0, /* 19 serial_number_word2 */
9551 0, /* 20 serial_number_word3 */
9552 0, /* 21 check_sum */
9553 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9554 , /* 22-29 oem_name[16] */
9555 0, /* 30 dvc_err_code */
9556 0, /* 31 adv_err_code */
9557 0, /* 32 adv_err_addr */
9558 0, /* 33 saved_dvc_err_code */
9559 0, /* 34 saved_adv_err_code */
9560 0, /* 35 saved_adv_err_addr */
9561 0, /* 36 reserved */
9562 0, /* 37 reserved */
9563 0, /* 38 reserved */
9564 0, /* 39 reserved */
9565 0, /* 40 reserved */
9566 0, /* 41 reserved */
9567 0, /* 42 reserved */
9568 0, /* 43 reserved */
9569 0, /* 44 reserved */
9570 0, /* 45 reserved */
9571 0, /* 46 reserved */
9572 0, /* 47 reserved */
9573 0, /* 48 reserved */
9574 0, /* 49 reserved */
9575 0, /* 50 reserved */
9576 0, /* 51 reserved */
9577 0, /* 52 reserved */
9578 0, /* 53 reserved */
9579 0, /* 54 reserved */
9580 0, /* 55 reserved */
9581 0, /* 56 cisptr_lsw */
9582 0, /* 57 cisprt_msw */
9583 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9584 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
9585 0, /* 60 reserved */
9586 0, /* 61 reserved */
9587 0, /* 62 reserved */
9588 0 /* 63 reserved */
9589 };
9590
9591 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = {
9592 0, /* 00 cfg_lsw */
9593 0, /* 01 cfg_msw */
9594 0, /* 02 disc_enable */
9595 0, /* 03 wdtr_able */
9596 0, /* 04 sdtr_speed1 */
9597 0, /* 05 start_motor */
9598 0, /* 06 tagqng_able */
9599 0, /* 07 bios_scan */
9600 0, /* 08 scam_tolerant */
9601 1, /* 09 adapter_scsi_id */
9602 1, /* bios_boot_delay */
9603 1, /* 10 scsi_reset_delay */
9604 1, /* bios_id_lun */
9605 1, /* 11 termination_se */
9606 1, /* termination_lvd */
9607 0, /* 12 bios_ctrl */
9608 0, /* 13 sdtr_speed2 */
9609 0, /* 14 sdtr_speed3 */
9610 1, /* 15 max_host_qng */
9611 1, /* max_dvc_qng */
9612 0, /* 16 dvc_cntl */
9613 0, /* 17 sdtr_speed4 */
9614 0, /* 18 serial_number_word1 */
9615 0, /* 19 serial_number_word2 */
9616 0, /* 20 serial_number_word3 */
9617 0, /* 21 check_sum */
9618 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9619 , /* 22-29 oem_name[16] */
9620 0, /* 30 dvc_err_code */
9621 0, /* 31 adv_err_code */
9622 0, /* 32 adv_err_addr */
9623 0, /* 33 saved_dvc_err_code */
9624 0, /* 34 saved_adv_err_code */
9625 0, /* 35 saved_adv_err_addr */
9626 0, /* 36 reserved */
9627 0, /* 37 reserved */
9628 0, /* 38 reserved */
9629 0, /* 39 reserved */
9630 0, /* 40 reserved */
9631 0, /* 41 reserved */
9632 0, /* 42 reserved */
9633 0, /* 43 reserved */
9634 0, /* 44 reserved */
9635 0, /* 45 reserved */
9636 0, /* 46 reserved */
9637 0, /* 47 reserved */
9638 0, /* 48 reserved */
9639 0, /* 49 reserved */
9640 0, /* 50 reserved */
9641 0, /* 51 reserved */
9642 0, /* 52 reserved */
9643 0, /* 53 reserved */
9644 0, /* 54 reserved */
9645 0, /* 55 reserved */
9646 0, /* 56 cisptr_lsw */
9647 0, /* 57 cisprt_msw */
9648 0, /* 58 subsysvid */
9649 0, /* 59 subsysid */
9650 0, /* 60 reserved */
9651 0, /* 61 reserved */
9652 0, /* 62 reserved */
9653 0 /* 63 reserved */
9654 };
9655
9656 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = {
9657 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9658 0x0000, /* 01 cfg_msw */
9659 0xFFFF, /* 02 disc_enable */
9660 0xFFFF, /* 03 wdtr_able */
9661 0x5555, /* 04 sdtr_speed1 */
9662 0xFFFF, /* 05 start_motor */
9663 0xFFFF, /* 06 tagqng_able */
9664 0xFFFF, /* 07 bios_scan */
9665 0, /* 08 scam_tolerant */
9666 7, /* 09 adapter_scsi_id */
9667 0, /* bios_boot_delay */
9668 3, /* 10 scsi_reset_delay */
9669 0, /* bios_id_lun */
9670 0, /* 11 termination_se */
9671 0, /* termination_lvd */
9672 0xFFE7, /* 12 bios_ctrl */
9673 0x5555, /* 13 sdtr_speed2 */
9674 0x5555, /* 14 sdtr_speed3 */
9675 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9676 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9677 0, /* 16 dvc_cntl */
9678 0x5555, /* 17 sdtr_speed4 */
9679 0, /* 18 serial_number_word1 */
9680 0, /* 19 serial_number_word2 */
9681 0, /* 20 serial_number_word3 */
9682 0, /* 21 check_sum */
9683 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9684 , /* 22-29 oem_name[16] */
9685 0, /* 30 dvc_err_code */
9686 0, /* 31 adv_err_code */
9687 0, /* 32 adv_err_addr */
9688 0, /* 33 saved_dvc_err_code */
9689 0, /* 34 saved_adv_err_code */
9690 0, /* 35 saved_adv_err_addr */
9691 0, /* 36 reserved */
9692 0, /* 37 reserved */
9693 0, /* 38 reserved */
9694 0, /* 39 reserved */
9695 0, /* 40 reserved */
9696 0, /* 41 reserved */
9697 0, /* 42 reserved */
9698 0, /* 43 reserved */
9699 0, /* 44 reserved */
9700 0, /* 45 reserved */
9701 0, /* 46 reserved */
9702 0, /* 47 reserved */
9703 0, /* 48 reserved */
9704 0, /* 49 reserved */
9705 0, /* 50 reserved */
9706 0, /* 51 reserved */
9707 0, /* 52 reserved */
9708 0, /* 53 reserved */
9709 0, /* 54 reserved */
9710 0, /* 55 reserved */
9711 0, /* 56 cisptr_lsw */
9712 0, /* 57 cisprt_msw */
9713 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9714 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
9715 0, /* 60 reserved */
9716 0, /* 61 reserved */
9717 0, /* 62 reserved */
9718 0 /* 63 reserved */
9719 };
9720
9721 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = {
9722 0, /* 00 cfg_lsw */
9723 0, /* 01 cfg_msw */
9724 0, /* 02 disc_enable */
9725 0, /* 03 wdtr_able */
9726 0, /* 04 sdtr_speed1 */
9727 0, /* 05 start_motor */
9728 0, /* 06 tagqng_able */
9729 0, /* 07 bios_scan */
9730 0, /* 08 scam_tolerant */
9731 1, /* 09 adapter_scsi_id */
9732 1, /* bios_boot_delay */
9733 1, /* 10 scsi_reset_delay */
9734 1, /* bios_id_lun */
9735 1, /* 11 termination_se */
9736 1, /* termination_lvd */
9737 0, /* 12 bios_ctrl */
9738 0, /* 13 sdtr_speed2 */
9739 0, /* 14 sdtr_speed3 */
9740 1, /* 15 max_host_qng */
9741 1, /* max_dvc_qng */
9742 0, /* 16 dvc_cntl */
9743 0, /* 17 sdtr_speed4 */
9744 0, /* 18 serial_number_word1 */
9745 0, /* 19 serial_number_word2 */
9746 0, /* 20 serial_number_word3 */
9747 0, /* 21 check_sum */
9748 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9749 , /* 22-29 oem_name[16] */
9750 0, /* 30 dvc_err_code */
9751 0, /* 31 adv_err_code */
9752 0, /* 32 adv_err_addr */
9753 0, /* 33 saved_dvc_err_code */
9754 0, /* 34 saved_adv_err_code */
9755 0, /* 35 saved_adv_err_addr */
9756 0, /* 36 reserved */
9757 0, /* 37 reserved */
9758 0, /* 38 reserved */
9759 0, /* 39 reserved */
9760 0, /* 40 reserved */
9761 0, /* 41 reserved */
9762 0, /* 42 reserved */
9763 0, /* 43 reserved */
9764 0, /* 44 reserved */
9765 0, /* 45 reserved */
9766 0, /* 46 reserved */
9767 0, /* 47 reserved */
9768 0, /* 48 reserved */
9769 0, /* 49 reserved */
9770 0, /* 50 reserved */
9771 0, /* 51 reserved */
9772 0, /* 52 reserved */
9773 0, /* 53 reserved */
9774 0, /* 54 reserved */
9775 0, /* 55 reserved */
9776 0, /* 56 cisptr_lsw */
9777 0, /* 57 cisprt_msw */
9778 0, /* 58 subsysvid */
9779 0, /* 59 subsysid */
9780 0, /* 60 reserved */
9781 0, /* 61 reserved */
9782 0, /* 62 reserved */
9783 0 /* 63 reserved */
9784 };
9785
9786 #ifdef CONFIG_PCI
9787 /*
9788 * Wait for EEPROM command to complete
9789 */
9790 static void AdvWaitEEPCmd(AdvPortAddr iop_base)
9791 {
9792 int eep_delay_ms;
9793
9794 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
9795 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
9796 ASC_EEP_CMD_DONE) {
9797 break;
9798 }
9799 mdelay(1);
9800 }
9801 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
9802 0)
9803 BUG();
9804 }
9805
9806 /*
9807 * Read the EEPROM from specified location
9808 */
9809 static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
9810 {
9811 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9812 ASC_EEP_CMD_READ | eep_word_addr);
9813 AdvWaitEEPCmd(iop_base);
9814 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
9815 }
9816
9817 /*
9818 * Write the EEPROM from 'cfg_buf'.
9819 */
9820 static void AdvSet3550EEPConfig(AdvPortAddr iop_base,
9821 ADVEEP_3550_CONFIG *cfg_buf)
9822 {
9823 ushort *wbuf;
9824 ushort addr, chksum;
9825 ushort *charfields;
9826
9827 wbuf = (ushort *)cfg_buf;
9828 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
9829 chksum = 0;
9830
9831 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
9832 AdvWaitEEPCmd(iop_base);
9833
9834 /*
9835 * Write EEPROM from word 0 to word 20.
9836 */
9837 for (addr = ADV_EEP_DVC_CFG_BEGIN;
9838 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
9839 ushort word;
9840
9841 if (*charfields++) {
9842 word = cpu_to_le16(*wbuf);
9843 } else {
9844 word = *wbuf;
9845 }
9846 chksum += *wbuf; /* Checksum is calculated from word values. */
9847 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9848 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9849 ASC_EEP_CMD_WRITE | addr);
9850 AdvWaitEEPCmd(iop_base);
9851 mdelay(ADV_EEP_DELAY_MS);
9852 }
9853
9854 /*
9855 * Write EEPROM checksum at word 21.
9856 */
9857 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
9858 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
9859 AdvWaitEEPCmd(iop_base);
9860 wbuf++;
9861 charfields++;
9862
9863 /*
9864 * Write EEPROM OEM name at words 22 to 29.
9865 */
9866 for (addr = ADV_EEP_DVC_CTL_BEGIN;
9867 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
9868 ushort word;
9869
9870 if (*charfields++) {
9871 word = cpu_to_le16(*wbuf);
9872 } else {
9873 word = *wbuf;
9874 }
9875 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9876 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9877 ASC_EEP_CMD_WRITE | addr);
9878 AdvWaitEEPCmd(iop_base);
9879 }
9880 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
9881 AdvWaitEEPCmd(iop_base);
9882 }
9883
9884 /*
9885 * Write the EEPROM from 'cfg_buf'.
9886 */
9887 static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
9888 ADVEEP_38C0800_CONFIG *cfg_buf)
9889 {
9890 ushort *wbuf;
9891 ushort *charfields;
9892 ushort addr, chksum;
9893
9894 wbuf = (ushort *)cfg_buf;
9895 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
9896 chksum = 0;
9897
9898 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
9899 AdvWaitEEPCmd(iop_base);
9900
9901 /*
9902 * Write EEPROM from word 0 to word 20.
9903 */
9904 for (addr = ADV_EEP_DVC_CFG_BEGIN;
9905 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
9906 ushort word;
9907
9908 if (*charfields++) {
9909 word = cpu_to_le16(*wbuf);
9910 } else {
9911 word = *wbuf;
9912 }
9913 chksum += *wbuf; /* Checksum is calculated from word values. */
9914 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9915 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9916 ASC_EEP_CMD_WRITE | addr);
9917 AdvWaitEEPCmd(iop_base);
9918 mdelay(ADV_EEP_DELAY_MS);
9919 }
9920
9921 /*
9922 * Write EEPROM checksum at word 21.
9923 */
9924 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
9925 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
9926 AdvWaitEEPCmd(iop_base);
9927 wbuf++;
9928 charfields++;
9929
9930 /*
9931 * Write EEPROM OEM name at words 22 to 29.
9932 */
9933 for (addr = ADV_EEP_DVC_CTL_BEGIN;
9934 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
9935 ushort word;
9936
9937 if (*charfields++) {
9938 word = cpu_to_le16(*wbuf);
9939 } else {
9940 word = *wbuf;
9941 }
9942 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9943 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9944 ASC_EEP_CMD_WRITE | addr);
9945 AdvWaitEEPCmd(iop_base);
9946 }
9947 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
9948 AdvWaitEEPCmd(iop_base);
9949 }
9950
9951 /*
9952 * Write the EEPROM from 'cfg_buf'.
9953 */
9954 static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
9955 ADVEEP_38C1600_CONFIG *cfg_buf)
9956 {
9957 ushort *wbuf;
9958 ushort *charfields;
9959 ushort addr, chksum;
9960
9961 wbuf = (ushort *)cfg_buf;
9962 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
9963 chksum = 0;
9964
9965 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
9966 AdvWaitEEPCmd(iop_base);
9967
9968 /*
9969 * Write EEPROM from word 0 to word 20.
9970 */
9971 for (addr = ADV_EEP_DVC_CFG_BEGIN;
9972 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
9973 ushort word;
9974
9975 if (*charfields++) {
9976 word = cpu_to_le16(*wbuf);
9977 } else {
9978 word = *wbuf;
9979 }
9980 chksum += *wbuf; /* Checksum is calculated from word values. */
9981 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9982 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9983 ASC_EEP_CMD_WRITE | addr);
9984 AdvWaitEEPCmd(iop_base);
9985 mdelay(ADV_EEP_DELAY_MS);
9986 }
9987
9988 /*
9989 * Write EEPROM checksum at word 21.
9990 */
9991 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
9992 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
9993 AdvWaitEEPCmd(iop_base);
9994 wbuf++;
9995 charfields++;
9996
9997 /*
9998 * Write EEPROM OEM name at words 22 to 29.
9999 */
10000 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10001 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10002 ushort word;
10003
10004 if (*charfields++) {
10005 word = cpu_to_le16(*wbuf);
10006 } else {
10007 word = *wbuf;
10008 }
10009 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10010 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10011 ASC_EEP_CMD_WRITE | addr);
10012 AdvWaitEEPCmd(iop_base);
10013 }
10014 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10015 AdvWaitEEPCmd(iop_base);
10016 }
10017
10018 /*
10019 * Read EEPROM configuration into the specified buffer.
10020 *
10021 * Return a checksum based on the EEPROM configuration read.
10022 */
10023 static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base,
10024 ADVEEP_3550_CONFIG *cfg_buf)
10025 {
10026 ushort wval, chksum;
10027 ushort *wbuf;
10028 int eep_addr;
10029 ushort *charfields;
10030
10031 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
10032 wbuf = (ushort *)cfg_buf;
10033 chksum = 0;
10034
10035 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10036 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10037 wval = AdvReadEEPWord(iop_base, eep_addr);
10038 chksum += wval; /* Checksum is calculated from word values. */
10039 if (*charfields++) {
10040 *wbuf = le16_to_cpu(wval);
10041 } else {
10042 *wbuf = wval;
10043 }
10044 }
10045 /* Read checksum word. */
10046 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10047 wbuf++;
10048 charfields++;
10049
10050 /* Read rest of EEPROM not covered by the checksum. */
10051 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10052 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10053 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10054 if (*charfields++) {
10055 *wbuf = le16_to_cpu(*wbuf);
10056 }
10057 }
10058 return chksum;
10059 }
10060
10061 /*
10062 * Read EEPROM configuration into the specified buffer.
10063 *
10064 * Return a checksum based on the EEPROM configuration read.
10065 */
10066 static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
10067 ADVEEP_38C0800_CONFIG *cfg_buf)
10068 {
10069 ushort wval, chksum;
10070 ushort *wbuf;
10071 int eep_addr;
10072 ushort *charfields;
10073
10074 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10075 wbuf = (ushort *)cfg_buf;
10076 chksum = 0;
10077
10078 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10079 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10080 wval = AdvReadEEPWord(iop_base, eep_addr);
10081 chksum += wval; /* Checksum is calculated from word values. */
10082 if (*charfields++) {
10083 *wbuf = le16_to_cpu(wval);
10084 } else {
10085 *wbuf = wval;
10086 }
10087 }
10088 /* Read checksum word. */
10089 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10090 wbuf++;
10091 charfields++;
10092
10093 /* Read rest of EEPROM not covered by the checksum. */
10094 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10095 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10096 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10097 if (*charfields++) {
10098 *wbuf = le16_to_cpu(*wbuf);
10099 }
10100 }
10101 return chksum;
10102 }
10103
10104 /*
10105 * Read EEPROM configuration into the specified buffer.
10106 *
10107 * Return a checksum based on the EEPROM configuration read.
10108 */
10109 static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
10110 ADVEEP_38C1600_CONFIG *cfg_buf)
10111 {
10112 ushort wval, chksum;
10113 ushort *wbuf;
10114 int eep_addr;
10115 ushort *charfields;
10116
10117 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
10118 wbuf = (ushort *)cfg_buf;
10119 chksum = 0;
10120
10121 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10122 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10123 wval = AdvReadEEPWord(iop_base, eep_addr);
10124 chksum += wval; /* Checksum is calculated from word values. */
10125 if (*charfields++) {
10126 *wbuf = le16_to_cpu(wval);
10127 } else {
10128 *wbuf = wval;
10129 }
10130 }
10131 /* Read checksum word. */
10132 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10133 wbuf++;
10134 charfields++;
10135
10136 /* Read rest of EEPROM not covered by the checksum. */
10137 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10138 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10139 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10140 if (*charfields++) {
10141 *wbuf = le16_to_cpu(*wbuf);
10142 }
10143 }
10144 return chksum;
10145 }
10146
10147 /*
10148 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10149 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10150 * all of this is done.
10151 *
10152 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10153 *
10154 * For a non-fatal error return a warning code. If there are no warnings
10155 * then 0 is returned.
10156 *
10157 * Note: Chip is stopped on entry.
10158 */
10159 static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
10160 {
10161 AdvPortAddr iop_base;
10162 ushort warn_code;
10163 ADVEEP_3550_CONFIG eep_config;
10164
10165 iop_base = asc_dvc->iop_base;
10166
10167 warn_code = 0;
10168
10169 /*
10170 * Read the board's EEPROM configuration.
10171 *
10172 * Set default values if a bad checksum is found.
10173 */
10174 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
10175 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10176
10177 /*
10178 * Set EEPROM default values.
10179 */
10180 memcpy(&eep_config, &Default_3550_EEPROM_Config,
10181 sizeof(ADVEEP_3550_CONFIG));
10182
10183 /*
10184 * Assume the 6 byte board serial number that was read from
10185 * EEPROM is correct even if the EEPROM checksum failed.
10186 */
10187 eep_config.serial_number_word3 =
10188 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10189
10190 eep_config.serial_number_word2 =
10191 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10192
10193 eep_config.serial_number_word1 =
10194 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10195
10196 AdvSet3550EEPConfig(iop_base, &eep_config);
10197 }
10198 /*
10199 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10200 * EEPROM configuration that was read.
10201 *
10202 * This is the mapping of EEPROM fields to Adv Library fields.
10203 */
10204 asc_dvc->wdtr_able = eep_config.wdtr_able;
10205 asc_dvc->sdtr_able = eep_config.sdtr_able;
10206 asc_dvc->ultra_able = eep_config.ultra_able;
10207 asc_dvc->tagqng_able = eep_config.tagqng_able;
10208 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10209 asc_dvc->max_host_qng = eep_config.max_host_qng;
10210 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10211 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10212 asc_dvc->start_motor = eep_config.start_motor;
10213 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10214 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10215 asc_dvc->no_scam = eep_config.scam_tolerant;
10216 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10217 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10218 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10219
10220 /*
10221 * Set the host maximum queuing (max. 253, min. 16) and the per device
10222 * maximum queuing (max. 63, min. 4).
10223 */
10224 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10225 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10226 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10227 /* If the value is zero, assume it is uninitialized. */
10228 if (eep_config.max_host_qng == 0) {
10229 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10230 } else {
10231 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10232 }
10233 }
10234
10235 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10236 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10237 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10238 /* If the value is zero, assume it is uninitialized. */
10239 if (eep_config.max_dvc_qng == 0) {
10240 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10241 } else {
10242 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10243 }
10244 }
10245
10246 /*
10247 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10248 * set 'max_dvc_qng' to 'max_host_qng'.
10249 */
10250 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10251 eep_config.max_dvc_qng = eep_config.max_host_qng;
10252 }
10253
10254 /*
10255 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10256 * values based on possibly adjusted EEPROM values.
10257 */
10258 asc_dvc->max_host_qng = eep_config.max_host_qng;
10259 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10260
10261 /*
10262 * If the EEPROM 'termination' field is set to automatic (0), then set
10263 * the ADV_DVC_CFG 'termination' field to automatic also.
10264 *
10265 * If the termination is specified with a non-zero 'termination'
10266 * value check that a legal value is set and set the ADV_DVC_CFG
10267 * 'termination' field appropriately.
10268 */
10269 if (eep_config.termination == 0) {
10270 asc_dvc->cfg->termination = 0; /* auto termination */
10271 } else {
10272 /* Enable manual control with low off / high off. */
10273 if (eep_config.termination == 1) {
10274 asc_dvc->cfg->termination = TERM_CTL_SEL;
10275
10276 /* Enable manual control with low off / high on. */
10277 } else if (eep_config.termination == 2) {
10278 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
10279
10280 /* Enable manual control with low on / high on. */
10281 } else if (eep_config.termination == 3) {
10282 asc_dvc->cfg->termination =
10283 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
10284 } else {
10285 /*
10286 * The EEPROM 'termination' field contains a bad value. Use
10287 * automatic termination instead.
10288 */
10289 asc_dvc->cfg->termination = 0;
10290 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10291 }
10292 }
10293
10294 return warn_code;
10295 }
10296
10297 /*
10298 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10299 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10300 * all of this is done.
10301 *
10302 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10303 *
10304 * For a non-fatal error return a warning code. If there are no warnings
10305 * then 0 is returned.
10306 *
10307 * Note: Chip is stopped on entry.
10308 */
10309 static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
10310 {
10311 AdvPortAddr iop_base;
10312 ushort warn_code;
10313 ADVEEP_38C0800_CONFIG eep_config;
10314 uchar tid, termination;
10315 ushort sdtr_speed = 0;
10316
10317 iop_base = asc_dvc->iop_base;
10318
10319 warn_code = 0;
10320
10321 /*
10322 * Read the board's EEPROM configuration.
10323 *
10324 * Set default values if a bad checksum is found.
10325 */
10326 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
10327 eep_config.check_sum) {
10328 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10329
10330 /*
10331 * Set EEPROM default values.
10332 */
10333 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
10334 sizeof(ADVEEP_38C0800_CONFIG));
10335
10336 /*
10337 * Assume the 6 byte board serial number that was read from
10338 * EEPROM is correct even if the EEPROM checksum failed.
10339 */
10340 eep_config.serial_number_word3 =
10341 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10342
10343 eep_config.serial_number_word2 =
10344 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10345
10346 eep_config.serial_number_word1 =
10347 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10348
10349 AdvSet38C0800EEPConfig(iop_base, &eep_config);
10350 }
10351 /*
10352 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
10353 * EEPROM configuration that was read.
10354 *
10355 * This is the mapping of EEPROM fields to Adv Library fields.
10356 */
10357 asc_dvc->wdtr_able = eep_config.wdtr_able;
10358 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10359 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10360 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10361 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10362 asc_dvc->tagqng_able = eep_config.tagqng_able;
10363 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10364 asc_dvc->max_host_qng = eep_config.max_host_qng;
10365 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10366 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10367 asc_dvc->start_motor = eep_config.start_motor;
10368 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10369 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10370 asc_dvc->no_scam = eep_config.scam_tolerant;
10371 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10372 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10373 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10374
10375 /*
10376 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10377 * are set, then set an 'sdtr_able' bit for it.
10378 */
10379 asc_dvc->sdtr_able = 0;
10380 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
10381 if (tid == 0) {
10382 sdtr_speed = asc_dvc->sdtr_speed1;
10383 } else if (tid == 4) {
10384 sdtr_speed = asc_dvc->sdtr_speed2;
10385 } else if (tid == 8) {
10386 sdtr_speed = asc_dvc->sdtr_speed3;
10387 } else if (tid == 12) {
10388 sdtr_speed = asc_dvc->sdtr_speed4;
10389 }
10390 if (sdtr_speed & ADV_MAX_TID) {
10391 asc_dvc->sdtr_able |= (1 << tid);
10392 }
10393 sdtr_speed >>= 4;
10394 }
10395
10396 /*
10397 * Set the host maximum queuing (max. 253, min. 16) and the per device
10398 * maximum queuing (max. 63, min. 4).
10399 */
10400 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10401 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10402 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10403 /* If the value is zero, assume it is uninitialized. */
10404 if (eep_config.max_host_qng == 0) {
10405 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10406 } else {
10407 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10408 }
10409 }
10410
10411 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10412 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10413 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10414 /* If the value is zero, assume it is uninitialized. */
10415 if (eep_config.max_dvc_qng == 0) {
10416 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10417 } else {
10418 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10419 }
10420 }
10421
10422 /*
10423 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10424 * set 'max_dvc_qng' to 'max_host_qng'.
10425 */
10426 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10427 eep_config.max_dvc_qng = eep_config.max_host_qng;
10428 }
10429
10430 /*
10431 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10432 * values based on possibly adjusted EEPROM values.
10433 */
10434 asc_dvc->max_host_qng = eep_config.max_host_qng;
10435 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10436
10437 /*
10438 * If the EEPROM 'termination' field is set to automatic (0), then set
10439 * the ADV_DVC_CFG 'termination' field to automatic also.
10440 *
10441 * If the termination is specified with a non-zero 'termination'
10442 * value check that a legal value is set and set the ADV_DVC_CFG
10443 * 'termination' field appropriately.
10444 */
10445 if (eep_config.termination_se == 0) {
10446 termination = 0; /* auto termination for SE */
10447 } else {
10448 /* Enable manual control with low off / high off. */
10449 if (eep_config.termination_se == 1) {
10450 termination = 0;
10451
10452 /* Enable manual control with low off / high on. */
10453 } else if (eep_config.termination_se == 2) {
10454 termination = TERM_SE_HI;
10455
10456 /* Enable manual control with low on / high on. */
10457 } else if (eep_config.termination_se == 3) {
10458 termination = TERM_SE;
10459 } else {
10460 /*
10461 * The EEPROM 'termination_se' field contains a bad value.
10462 * Use automatic termination instead.
10463 */
10464 termination = 0;
10465 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10466 }
10467 }
10468
10469 if (eep_config.termination_lvd == 0) {
10470 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10471 } else {
10472 /* Enable manual control with low off / high off. */
10473 if (eep_config.termination_lvd == 1) {
10474 asc_dvc->cfg->termination = termination;
10475
10476 /* Enable manual control with low off / high on. */
10477 } else if (eep_config.termination_lvd == 2) {
10478 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10479
10480 /* Enable manual control with low on / high on. */
10481 } else if (eep_config.termination_lvd == 3) {
10482 asc_dvc->cfg->termination = termination | TERM_LVD;
10483 } else {
10484 /*
10485 * The EEPROM 'termination_lvd' field contains a bad value.
10486 * Use automatic termination instead.
10487 */
10488 asc_dvc->cfg->termination = termination;
10489 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10490 }
10491 }
10492
10493 return warn_code;
10494 }
10495
10496 /*
10497 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
10498 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
10499 * all of this is done.
10500 *
10501 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
10502 *
10503 * For a non-fatal error return a warning code. If there are no warnings
10504 * then 0 is returned.
10505 *
10506 * Note: Chip is stopped on entry.
10507 */
10508 static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
10509 {
10510 AdvPortAddr iop_base;
10511 ushort warn_code;
10512 ADVEEP_38C1600_CONFIG eep_config;
10513 uchar tid, termination;
10514 ushort sdtr_speed = 0;
10515
10516 iop_base = asc_dvc->iop_base;
10517
10518 warn_code = 0;
10519
10520 /*
10521 * Read the board's EEPROM configuration.
10522 *
10523 * Set default values if a bad checksum is found.
10524 */
10525 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
10526 eep_config.check_sum) {
10527 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
10528 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10529
10530 /*
10531 * Set EEPROM default values.
10532 */
10533 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
10534 sizeof(ADVEEP_38C1600_CONFIG));
10535
10536 if (PCI_FUNC(pdev->devfn) != 0) {
10537 u8 ints;
10538 /*
10539 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
10540 * and old Mac system booting problem. The Expansion
10541 * ROM must be disabled in Function 1 for these systems
10542 */
10543 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
10544 /*
10545 * Clear the INTAB (bit 11) if the GPIO 0 input
10546 * indicates the Function 1 interrupt line is wired
10547 * to INTB.
10548 *
10549 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
10550 * 1 - Function 1 interrupt line wired to INT A.
10551 * 0 - Function 1 interrupt line wired to INT B.
10552 *
10553 * Note: Function 0 is always wired to INTA.
10554 * Put all 5 GPIO bits in input mode and then read
10555 * their input values.
10556 */
10557 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
10558 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
10559 if ((ints & 0x01) == 0)
10560 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
10561 }
10562
10563 /*
10564 * Assume the 6 byte board serial number that was read from
10565 * EEPROM is correct even if the EEPROM checksum failed.
10566 */
10567 eep_config.serial_number_word3 =
10568 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10569 eep_config.serial_number_word2 =
10570 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10571 eep_config.serial_number_word1 =
10572 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10573
10574 AdvSet38C1600EEPConfig(iop_base, &eep_config);
10575 }
10576
10577 /*
10578 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10579 * EEPROM configuration that was read.
10580 *
10581 * This is the mapping of EEPROM fields to Adv Library fields.
10582 */
10583 asc_dvc->wdtr_able = eep_config.wdtr_able;
10584 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10585 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10586 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10587 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10588 asc_dvc->ppr_able = 0;
10589 asc_dvc->tagqng_able = eep_config.tagqng_able;
10590 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10591 asc_dvc->max_host_qng = eep_config.max_host_qng;
10592 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10593 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
10594 asc_dvc->start_motor = eep_config.start_motor;
10595 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10596 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10597 asc_dvc->no_scam = eep_config.scam_tolerant;
10598
10599 /*
10600 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10601 * are set, then set an 'sdtr_able' bit for it.
10602 */
10603 asc_dvc->sdtr_able = 0;
10604 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
10605 if (tid == 0) {
10606 sdtr_speed = asc_dvc->sdtr_speed1;
10607 } else if (tid == 4) {
10608 sdtr_speed = asc_dvc->sdtr_speed2;
10609 } else if (tid == 8) {
10610 sdtr_speed = asc_dvc->sdtr_speed3;
10611 } else if (tid == 12) {
10612 sdtr_speed = asc_dvc->sdtr_speed4;
10613 }
10614 if (sdtr_speed & ASC_MAX_TID) {
10615 asc_dvc->sdtr_able |= (1 << tid);
10616 }
10617 sdtr_speed >>= 4;
10618 }
10619
10620 /*
10621 * Set the host maximum queuing (max. 253, min. 16) and the per device
10622 * maximum queuing (max. 63, min. 4).
10623 */
10624 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10625 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10626 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10627 /* If the value is zero, assume it is uninitialized. */
10628 if (eep_config.max_host_qng == 0) {
10629 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10630 } else {
10631 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10632 }
10633 }
10634
10635 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10636 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10637 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10638 /* If the value is zero, assume it is uninitialized. */
10639 if (eep_config.max_dvc_qng == 0) {
10640 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10641 } else {
10642 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10643 }
10644 }
10645
10646 /*
10647 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10648 * set 'max_dvc_qng' to 'max_host_qng'.
10649 */
10650 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10651 eep_config.max_dvc_qng = eep_config.max_host_qng;
10652 }
10653
10654 /*
10655 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
10656 * values based on possibly adjusted EEPROM values.
10657 */
10658 asc_dvc->max_host_qng = eep_config.max_host_qng;
10659 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10660
10661 /*
10662 * If the EEPROM 'termination' field is set to automatic (0), then set
10663 * the ASC_DVC_CFG 'termination' field to automatic also.
10664 *
10665 * If the termination is specified with a non-zero 'termination'
10666 * value check that a legal value is set and set the ASC_DVC_CFG
10667 * 'termination' field appropriately.
10668 */
10669 if (eep_config.termination_se == 0) {
10670 termination = 0; /* auto termination for SE */
10671 } else {
10672 /* Enable manual control with low off / high off. */
10673 if (eep_config.termination_se == 1) {
10674 termination = 0;
10675
10676 /* Enable manual control with low off / high on. */
10677 } else if (eep_config.termination_se == 2) {
10678 termination = TERM_SE_HI;
10679
10680 /* Enable manual control with low on / high on. */
10681 } else if (eep_config.termination_se == 3) {
10682 termination = TERM_SE;
10683 } else {
10684 /*
10685 * The EEPROM 'termination_se' field contains a bad value.
10686 * Use automatic termination instead.
10687 */
10688 termination = 0;
10689 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10690 }
10691 }
10692
10693 if (eep_config.termination_lvd == 0) {
10694 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10695 } else {
10696 /* Enable manual control with low off / high off. */
10697 if (eep_config.termination_lvd == 1) {
10698 asc_dvc->cfg->termination = termination;
10699
10700 /* Enable manual control with low off / high on. */
10701 } else if (eep_config.termination_lvd == 2) {
10702 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10703
10704 /* Enable manual control with low on / high on. */
10705 } else if (eep_config.termination_lvd == 3) {
10706 asc_dvc->cfg->termination = termination | TERM_LVD;
10707 } else {
10708 /*
10709 * The EEPROM 'termination_lvd' field contains a bad value.
10710 * Use automatic termination instead.
10711 */
10712 asc_dvc->cfg->termination = termination;
10713 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10714 }
10715 }
10716
10717 return warn_code;
10718 }
10719
10720 /*
10721 * Initialize the ADV_DVC_VAR structure.
10722 *
10723 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10724 *
10725 * For a non-fatal error return a warning code. If there are no warnings
10726 * then 0 is returned.
10727 */
10728 static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
10729 {
10730 struct asc_board *board = shost_priv(shost);
10731 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
10732 unsigned short warn_code = 0;
10733 AdvPortAddr iop_base = asc_dvc->iop_base;
10734 u16 cmd;
10735 int status;
10736
10737 asc_dvc->err_code = 0;
10738
10739 /*
10740 * Save the state of the PCI Configuration Command Register
10741 * "Parity Error Response Control" Bit. If the bit is clear (0),
10742 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
10743 * DMA parity errors.
10744 */
10745 asc_dvc->cfg->control_flag = 0;
10746 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
10747 if ((cmd & PCI_COMMAND_PARITY) == 0)
10748 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
10749
10750 asc_dvc->cfg->chip_version =
10751 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
10752
10753 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
10754 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
10755 (ushort)ADV_CHIP_ID_BYTE);
10756
10757 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
10758 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
10759 (ushort)ADV_CHIP_ID_WORD);
10760
10761 /*
10762 * Reset the chip to start and allow register writes.
10763 */
10764 if (AdvFindSignature(iop_base) == 0) {
10765 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
10766 return ADV_ERROR;
10767 } else {
10768 /*
10769 * The caller must set 'chip_type' to a valid setting.
10770 */
10771 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
10772 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
10773 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
10774 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
10775 return ADV_ERROR;
10776 }
10777
10778 /*
10779 * Reset Chip.
10780 */
10781 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
10782 ADV_CTRL_REG_CMD_RESET);
10783 mdelay(100);
10784 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
10785 ADV_CTRL_REG_CMD_WR_IO_REG);
10786
10787 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
10788 status = AdvInitFrom38C1600EEP(asc_dvc);
10789 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
10790 status = AdvInitFrom38C0800EEP(asc_dvc);
10791 } else {
10792 status = AdvInitFrom3550EEP(asc_dvc);
10793 }
10794 warn_code |= status;
10795 }
10796
10797 if (warn_code != 0)
10798 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
10799
10800 if (asc_dvc->err_code)
10801 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
10802 asc_dvc->err_code);
10803
10804 return asc_dvc->err_code;
10805 }
10806 #endif
10807
10808 static struct scsi_host_template advansys_template = {
10809 .proc_name = DRV_NAME,
10810 #ifdef CONFIG_PROC_FS
10811 .show_info = advansys_show_info,
10812 #endif
10813 .name = DRV_NAME,
10814 .info = advansys_info,
10815 .queuecommand = advansys_queuecommand,
10816 .eh_host_reset_handler = advansys_reset,
10817 .bios_param = advansys_biosparam,
10818 .slave_configure = advansys_slave_configure,
10819 /*
10820 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
10821 * must be set. The flag will be cleared in advansys_board_found
10822 * for non-ISA adapters.
10823 */
10824 .unchecked_isa_dma = true,
10825 /*
10826 * All adapters controlled by this driver are capable of large
10827 * scatter-gather lists. According to the mid-level SCSI documentation
10828 * this obviates any performance gain provided by setting
10829 * 'use_clustering'. But empirically while CPU utilization is increased
10830 * by enabling clustering, I/O throughput increases as well.
10831 */
10832 .use_clustering = ENABLE_CLUSTERING,
10833 .use_blk_tags = 1,
10834 };
10835
10836 static int advansys_wide_init_chip(struct Scsi_Host *shost)
10837 {
10838 struct asc_board *board = shost_priv(shost);
10839 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
10840 size_t sgblk_pool_size;
10841 int warn_code, err_code;
10842
10843 /*
10844 * Allocate buffer carrier structures. The total size
10845 * is about 8 KB, so allocate all at once.
10846 */
10847 adv_dvc->carrier = dma_alloc_coherent(board->dev,
10848 ADV_CARRIER_BUFSIZE, &adv_dvc->carrier_addr, GFP_KERNEL);
10849 ASC_DBG(1, "carrier 0x%p\n", adv_dvc->carrier);
10850
10851 if (!adv_dvc->carrier)
10852 goto kmalloc_failed;
10853
10854 /*
10855 * Allocate up to 'max_host_qng' request structures for the Wide
10856 * board. The total size is about 16 KB, so allocate all at once.
10857 * If the allocation fails decrement and try again.
10858 */
10859 board->adv_reqp_size = adv_dvc->max_host_qng * sizeof(adv_req_t);
10860 if (board->adv_reqp_size & 0x1f) {
10861 ASC_DBG(1, "unaligned reqp %lu bytes\n", sizeof(adv_req_t));
10862 board->adv_reqp_size = ADV_32BALIGN(board->adv_reqp_size);
10863 }
10864 board->adv_reqp = dma_alloc_coherent(board->dev, board->adv_reqp_size,
10865 &board->adv_reqp_addr, GFP_KERNEL);
10866
10867 if (!board->adv_reqp)
10868 goto kmalloc_failed;
10869
10870 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", board->adv_reqp,
10871 adv_dvc->max_host_qng, board->adv_reqp_size);
10872
10873 /*
10874 * Allocate up to ADV_TOT_SG_BLOCK request structures for
10875 * the Wide board. Each structure is about 136 bytes.
10876 */
10877 sgblk_pool_size = sizeof(adv_sgblk_t) * ADV_TOT_SG_BLOCK;
10878 board->adv_sgblk_pool = dma_pool_create("adv_sgblk", board->dev,
10879 sgblk_pool_size, 32, 0);
10880
10881 ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", ADV_TOT_SG_BLOCK,
10882 sizeof(adv_sgblk_t), sgblk_pool_size);
10883
10884 if (!board->adv_sgblk_pool)
10885 goto kmalloc_failed;
10886
10887 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
10888 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
10889 warn_code = AdvInitAsc3550Driver(adv_dvc);
10890 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
10891 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
10892 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
10893 } else {
10894 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
10895 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
10896 }
10897 err_code = adv_dvc->err_code;
10898
10899 if (warn_code || err_code) {
10900 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
10901 "0x%x\n", warn_code, err_code);
10902 }
10903
10904 goto exit;
10905
10906 kmalloc_failed:
10907 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
10908 err_code = ADV_ERROR;
10909 exit:
10910 return err_code;
10911 }
10912
10913 static void advansys_wide_free_mem(struct asc_board *board)
10914 {
10915 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
10916
10917 if (adv_dvc->carrier) {
10918 dma_free_coherent(board->dev, ADV_CARRIER_BUFSIZE,
10919 adv_dvc->carrier, adv_dvc->carrier_addr);
10920 adv_dvc->carrier = NULL;
10921 }
10922 if (board->adv_reqp) {
10923 dma_free_coherent(board->dev, board->adv_reqp_size,
10924 board->adv_reqp, board->adv_reqp_addr);
10925 board->adv_reqp = NULL;
10926 }
10927 if (board->adv_sgblk_pool) {
10928 dma_pool_destroy(board->adv_sgblk_pool);
10929 board->adv_sgblk_pool = NULL;
10930 }
10931 }
10932
10933 static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop,
10934 int bus_type)
10935 {
10936 struct pci_dev *pdev;
10937 struct asc_board *boardp = shost_priv(shost);
10938 ASC_DVC_VAR *asc_dvc_varp = NULL;
10939 ADV_DVC_VAR *adv_dvc_varp = NULL;
10940 int share_irq, warn_code, ret;
10941
10942 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
10943
10944 if (ASC_NARROW_BOARD(boardp)) {
10945 ASC_DBG(1, "narrow board\n");
10946 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
10947 asc_dvc_varp->bus_type = bus_type;
10948 asc_dvc_varp->drv_ptr = boardp;
10949 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
10950 asc_dvc_varp->iop_base = iop;
10951 } else {
10952 #ifdef CONFIG_PCI
10953 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
10954 adv_dvc_varp->drv_ptr = boardp;
10955 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
10956 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
10957 ASC_DBG(1, "wide board ASC-3550\n");
10958 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
10959 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
10960 ASC_DBG(1, "wide board ASC-38C0800\n");
10961 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
10962 } else {
10963 ASC_DBG(1, "wide board ASC-38C1600\n");
10964 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
10965 }
10966
10967 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
10968 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1);
10969 if (!boardp->ioremap_addr) {
10970 shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) "
10971 "returned NULL\n",
10972 (long)pci_resource_start(pdev, 1),
10973 boardp->asc_n_io_port);
10974 ret = -ENODEV;
10975 goto err_shost;
10976 }
10977 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
10978 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
10979
10980 /*
10981 * Even though it isn't used to access wide boards, other
10982 * than for the debug line below, save I/O Port address so
10983 * that it can be reported.
10984 */
10985 boardp->ioport = iop;
10986
10987 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
10988 (ushort)inp(iop + 1), (ushort)inpw(iop));
10989 #endif /* CONFIG_PCI */
10990 }
10991
10992 if (ASC_NARROW_BOARD(boardp)) {
10993 /*
10994 * Set the board bus type and PCI IRQ before
10995 * calling AscInitGetConfig().
10996 */
10997 switch (asc_dvc_varp->bus_type) {
10998 #ifdef CONFIG_ISA
10999 case ASC_IS_ISA:
11000 shost->unchecked_isa_dma = true;
11001 share_irq = 0;
11002 break;
11003 case ASC_IS_VL:
11004 shost->unchecked_isa_dma = false;
11005 share_irq = 0;
11006 break;
11007 case ASC_IS_EISA:
11008 shost->unchecked_isa_dma = false;
11009 share_irq = IRQF_SHARED;
11010 break;
11011 #endif /* CONFIG_ISA */
11012 #ifdef CONFIG_PCI
11013 case ASC_IS_PCI:
11014 shost->unchecked_isa_dma = false;
11015 share_irq = IRQF_SHARED;
11016 break;
11017 #endif /* CONFIG_PCI */
11018 default:
11019 shost_printk(KERN_ERR, shost, "unknown adapter type: "
11020 "%d\n", asc_dvc_varp->bus_type);
11021 shost->unchecked_isa_dma = false;
11022 share_irq = 0;
11023 break;
11024 }
11025
11026 /*
11027 * NOTE: AscInitGetConfig() may change the board's
11028 * bus_type value. The bus_type value should no
11029 * longer be used. If the bus_type field must be
11030 * referenced only use the bit-wise AND operator "&".
11031 */
11032 ASC_DBG(2, "AscInitGetConfig()\n");
11033 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
11034 } else {
11035 #ifdef CONFIG_PCI
11036 /*
11037 * For Wide boards set PCI information before calling
11038 * AdvInitGetConfig().
11039 */
11040 shost->unchecked_isa_dma = false;
11041 share_irq = IRQF_SHARED;
11042 ASC_DBG(2, "AdvInitGetConfig()\n");
11043
11044 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
11045 #endif /* CONFIG_PCI */
11046 }
11047
11048 if (ret)
11049 goto err_unmap;
11050
11051 /*
11052 * Save the EEPROM configuration so that it can be displayed
11053 * from /proc/scsi/advansys/[0...].
11054 */
11055 if (ASC_NARROW_BOARD(boardp)) {
11056
11057 ASCEEP_CONFIG *ep;
11058
11059 /*
11060 * Set the adapter's target id bit in the 'init_tidmask' field.
11061 */
11062 boardp->init_tidmask |=
11063 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
11064
11065 /*
11066 * Save EEPROM settings for the board.
11067 */
11068 ep = &boardp->eep_config.asc_eep;
11069
11070 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
11071 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
11072 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
11073 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
11074 ep->start_motor = asc_dvc_varp->start_motor;
11075 ep->cntl = asc_dvc_varp->dvc_cntl;
11076 ep->no_scam = asc_dvc_varp->no_scam;
11077 ep->max_total_qng = asc_dvc_varp->max_total_qng;
11078 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
11079 /* 'max_tag_qng' is set to the same value for every device. */
11080 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
11081 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
11082 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
11083 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
11084 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
11085 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
11086 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
11087
11088 /*
11089 * Modify board configuration.
11090 */
11091 ASC_DBG(2, "AscInitSetConfig()\n");
11092 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
11093 if (ret)
11094 goto err_unmap;
11095 } else {
11096 ADVEEP_3550_CONFIG *ep_3550;
11097 ADVEEP_38C0800_CONFIG *ep_38C0800;
11098 ADVEEP_38C1600_CONFIG *ep_38C1600;
11099
11100 /*
11101 * Save Wide EEP Configuration Information.
11102 */
11103 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
11104 ep_3550 = &boardp->eep_config.adv_3550_eep;
11105
11106 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
11107 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
11108 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11109 ep_3550->termination = adv_dvc_varp->cfg->termination;
11110 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
11111 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
11112 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
11113 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
11114 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
11115 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
11116 ep_3550->start_motor = adv_dvc_varp->start_motor;
11117 ep_3550->scsi_reset_delay =
11118 adv_dvc_varp->scsi_reset_wait;
11119 ep_3550->serial_number_word1 =
11120 adv_dvc_varp->cfg->serial1;
11121 ep_3550->serial_number_word2 =
11122 adv_dvc_varp->cfg->serial2;
11123 ep_3550->serial_number_word3 =
11124 adv_dvc_varp->cfg->serial3;
11125 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
11126 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
11127
11128 ep_38C0800->adapter_scsi_id =
11129 adv_dvc_varp->chip_scsi_id;
11130 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
11131 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11132 ep_38C0800->termination_lvd =
11133 adv_dvc_varp->cfg->termination;
11134 ep_38C0800->disc_enable =
11135 adv_dvc_varp->cfg->disc_enable;
11136 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
11137 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
11138 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11139 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11140 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11141 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11142 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11143 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11144 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
11145 ep_38C0800->scsi_reset_delay =
11146 adv_dvc_varp->scsi_reset_wait;
11147 ep_38C0800->serial_number_word1 =
11148 adv_dvc_varp->cfg->serial1;
11149 ep_38C0800->serial_number_word2 =
11150 adv_dvc_varp->cfg->serial2;
11151 ep_38C0800->serial_number_word3 =
11152 adv_dvc_varp->cfg->serial3;
11153 } else {
11154 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
11155
11156 ep_38C1600->adapter_scsi_id =
11157 adv_dvc_varp->chip_scsi_id;
11158 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
11159 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11160 ep_38C1600->termination_lvd =
11161 adv_dvc_varp->cfg->termination;
11162 ep_38C1600->disc_enable =
11163 adv_dvc_varp->cfg->disc_enable;
11164 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
11165 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
11166 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11167 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11168 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11169 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11170 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11171 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11172 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
11173 ep_38C1600->scsi_reset_delay =
11174 adv_dvc_varp->scsi_reset_wait;
11175 ep_38C1600->serial_number_word1 =
11176 adv_dvc_varp->cfg->serial1;
11177 ep_38C1600->serial_number_word2 =
11178 adv_dvc_varp->cfg->serial2;
11179 ep_38C1600->serial_number_word3 =
11180 adv_dvc_varp->cfg->serial3;
11181 }
11182
11183 /*
11184 * Set the adapter's target id bit in the 'init_tidmask' field.
11185 */
11186 boardp->init_tidmask |=
11187 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
11188 }
11189
11190 /*
11191 * Channels are numbered beginning with 0. For AdvanSys one host
11192 * structure supports one channel. Multi-channel boards have a
11193 * separate host structure for each channel.
11194 */
11195 shost->max_channel = 0;
11196 if (ASC_NARROW_BOARD(boardp)) {
11197 shost->max_id = ASC_MAX_TID + 1;
11198 shost->max_lun = ASC_MAX_LUN + 1;
11199 shost->max_cmd_len = ASC_MAX_CDB_LEN;
11200
11201 shost->io_port = asc_dvc_varp->iop_base;
11202 boardp->asc_n_io_port = ASC_IOADR_GAP;
11203 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
11204
11205 /* Set maximum number of queues the adapter can handle. */
11206 shost->can_queue = asc_dvc_varp->max_total_qng;
11207 } else {
11208 shost->max_id = ADV_MAX_TID + 1;
11209 shost->max_lun = ADV_MAX_LUN + 1;
11210 shost->max_cmd_len = ADV_MAX_CDB_LEN;
11211
11212 /*
11213 * Save the I/O Port address and length even though
11214 * I/O ports are not used to access Wide boards.
11215 * Instead the Wide boards are accessed with
11216 * PCI Memory Mapped I/O.
11217 */
11218 shost->io_port = iop;
11219
11220 shost->this_id = adv_dvc_varp->chip_scsi_id;
11221
11222 /* Set maximum number of queues the adapter can handle. */
11223 shost->can_queue = adv_dvc_varp->max_host_qng;
11224 }
11225 ret = scsi_init_shared_tag_map(shost, shost->can_queue);
11226 if (ret) {
11227 shost_printk(KERN_ERR, shost, "init tag map failed\n");
11228 goto err_free_dma;
11229 }
11230
11231 /*
11232 * Set the maximum number of scatter-gather elements the
11233 * adapter can handle.
11234 */
11235 if (ASC_NARROW_BOARD(boardp)) {
11236 /*
11237 * Allow two commands with 'sg_tablesize' scatter-gather
11238 * elements to be executed simultaneously. This value is
11239 * the theoretical hardware limit. It may be decreased
11240 * below.
11241 */
11242 shost->sg_tablesize =
11243 (((asc_dvc_varp->max_total_qng - 2) / 2) *
11244 ASC_SG_LIST_PER_Q) + 1;
11245 } else {
11246 shost->sg_tablesize = ADV_MAX_SG_LIST;
11247 }
11248
11249 /*
11250 * The value of 'sg_tablesize' can not exceed the SCSI
11251 * mid-level driver definition of SG_ALL. SG_ALL also
11252 * must not be exceeded, because it is used to define the
11253 * size of the scatter-gather table in 'struct asc_sg_head'.
11254 */
11255 if (shost->sg_tablesize > SG_ALL) {
11256 shost->sg_tablesize = SG_ALL;
11257 }
11258
11259 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
11260
11261 /* BIOS start address. */
11262 if (ASC_NARROW_BOARD(boardp)) {
11263 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
11264 asc_dvc_varp->bus_type);
11265 } else {
11266 /*
11267 * Fill-in BIOS board variables. The Wide BIOS saves
11268 * information in LRAM that is used by the driver.
11269 */
11270 AdvReadWordLram(adv_dvc_varp->iop_base,
11271 BIOS_SIGNATURE, boardp->bios_signature);
11272 AdvReadWordLram(adv_dvc_varp->iop_base,
11273 BIOS_VERSION, boardp->bios_version);
11274 AdvReadWordLram(adv_dvc_varp->iop_base,
11275 BIOS_CODESEG, boardp->bios_codeseg);
11276 AdvReadWordLram(adv_dvc_varp->iop_base,
11277 BIOS_CODELEN, boardp->bios_codelen);
11278
11279 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
11280 boardp->bios_signature, boardp->bios_version);
11281
11282 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
11283 boardp->bios_codeseg, boardp->bios_codelen);
11284
11285 /*
11286 * If the BIOS saved a valid signature, then fill in
11287 * the BIOS code segment base address.
11288 */
11289 if (boardp->bios_signature == 0x55AA) {
11290 /*
11291 * Convert x86 realmode code segment to a linear
11292 * address by shifting left 4.
11293 */
11294 shost->base = ((ulong)boardp->bios_codeseg << 4);
11295 } else {
11296 shost->base = 0;
11297 }
11298 }
11299
11300 /*
11301 * Register Board Resources - I/O Port, DMA, IRQ
11302 */
11303
11304 /* Register DMA Channel for Narrow boards. */
11305 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
11306 #ifdef CONFIG_ISA
11307 if (ASC_NARROW_BOARD(boardp)) {
11308 /* Register DMA channel for ISA bus. */
11309 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
11310 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
11311 ret = request_dma(shost->dma_channel, DRV_NAME);
11312 if (ret) {
11313 shost_printk(KERN_ERR, shost, "request_dma() "
11314 "%d failed %d\n",
11315 shost->dma_channel, ret);
11316 goto err_unmap;
11317 }
11318 AscEnableIsaDma(shost->dma_channel);
11319 }
11320 }
11321 #endif /* CONFIG_ISA */
11322
11323 /* Register IRQ Number. */
11324 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
11325
11326 ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
11327 DRV_NAME, shost);
11328
11329 if (ret) {
11330 if (ret == -EBUSY) {
11331 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11332 "already in use\n", boardp->irq);
11333 } else if (ret == -EINVAL) {
11334 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11335 "not valid\n", boardp->irq);
11336 } else {
11337 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11338 "failed with %d\n", boardp->irq, ret);
11339 }
11340 goto err_free_dma;
11341 }
11342
11343 /*
11344 * Initialize board RISC chip and enable interrupts.
11345 */
11346 if (ASC_NARROW_BOARD(boardp)) {
11347 ASC_DBG(2, "AscInitAsc1000Driver()\n");
11348
11349 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL);
11350 if (!asc_dvc_varp->overrun_buf) {
11351 ret = -ENOMEM;
11352 goto err_free_irq;
11353 }
11354 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
11355
11356 if (warn_code || asc_dvc_varp->err_code) {
11357 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
11358 "warn 0x%x, error 0x%x\n",
11359 asc_dvc_varp->init_state, warn_code,
11360 asc_dvc_varp->err_code);
11361 if (!asc_dvc_varp->overrun_dma) {
11362 ret = -ENODEV;
11363 goto err_free_mem;
11364 }
11365 }
11366 } else {
11367 if (advansys_wide_init_chip(shost)) {
11368 ret = -ENODEV;
11369 goto err_free_mem;
11370 }
11371 }
11372
11373 ASC_DBG_PRT_SCSI_HOST(2, shost);
11374
11375 ret = scsi_add_host(shost, boardp->dev);
11376 if (ret)
11377 goto err_free_mem;
11378
11379 scsi_scan_host(shost);
11380 return 0;
11381
11382 err_free_mem:
11383 if (ASC_NARROW_BOARD(boardp)) {
11384 if (asc_dvc_varp->overrun_dma)
11385 dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma,
11386 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11387 kfree(asc_dvc_varp->overrun_buf);
11388 } else
11389 advansys_wide_free_mem(boardp);
11390 err_free_irq:
11391 free_irq(boardp->irq, shost);
11392 err_free_dma:
11393 #ifdef CONFIG_ISA
11394 if (shost->dma_channel != NO_ISA_DMA)
11395 free_dma(shost->dma_channel);
11396 #endif
11397 err_unmap:
11398 if (boardp->ioremap_addr)
11399 iounmap(boardp->ioremap_addr);
11400 err_shost:
11401 return ret;
11402 }
11403
11404 /*
11405 * advansys_release()
11406 *
11407 * Release resources allocated for a single AdvanSys adapter.
11408 */
11409 static int advansys_release(struct Scsi_Host *shost)
11410 {
11411 struct asc_board *board = shost_priv(shost);
11412 ASC_DBG(1, "begin\n");
11413 scsi_remove_host(shost);
11414 free_irq(board->irq, shost);
11415 #ifdef CONFIG_ISA
11416 if (shost->dma_channel != NO_ISA_DMA) {
11417 ASC_DBG(1, "free_dma()\n");
11418 free_dma(shost->dma_channel);
11419 }
11420 #endif
11421 if (ASC_NARROW_BOARD(board)) {
11422 dma_unmap_single(board->dev,
11423 board->dvc_var.asc_dvc_var.overrun_dma,
11424 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11425 kfree(board->dvc_var.asc_dvc_var.overrun_buf);
11426 } else {
11427 iounmap(board->ioremap_addr);
11428 advansys_wide_free_mem(board);
11429 }
11430 scsi_host_put(shost);
11431 ASC_DBG(1, "end\n");
11432 return 0;
11433 }
11434
11435 #define ASC_IOADR_TABLE_MAX_IX 11
11436
11437 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = {
11438 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
11439 0x0210, 0x0230, 0x0250, 0x0330
11440 };
11441
11442 /*
11443 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
11444 * 00: 10
11445 * 01: 11
11446 * 10: 12
11447 * 11: 15
11448 */
11449 static unsigned int advansys_isa_irq_no(PortAddr iop_base)
11450 {
11451 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11452 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
11453 if (chip_irq == 13)
11454 chip_irq = 15;
11455 return chip_irq;
11456 }
11457
11458 static int advansys_isa_probe(struct device *dev, unsigned int id)
11459 {
11460 int err = -ENODEV;
11461 PortAddr iop_base = _asc_def_iop_base[id];
11462 struct Scsi_Host *shost;
11463 struct asc_board *board;
11464
11465 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
11466 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
11467 return -ENODEV;
11468 }
11469 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
11470 if (!AscFindSignature(iop_base))
11471 goto release_region;
11472 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
11473 goto release_region;
11474
11475 err = -ENOMEM;
11476 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11477 if (!shost)
11478 goto release_region;
11479
11480 board = shost_priv(shost);
11481 board->irq = advansys_isa_irq_no(iop_base);
11482 board->dev = dev;
11483 board->shost = shost;
11484
11485 err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
11486 if (err)
11487 goto free_host;
11488
11489 dev_set_drvdata(dev, shost);
11490 return 0;
11491
11492 free_host:
11493 scsi_host_put(shost);
11494 release_region:
11495 release_region(iop_base, ASC_IOADR_GAP);
11496 return err;
11497 }
11498
11499 static int advansys_isa_remove(struct device *dev, unsigned int id)
11500 {
11501 int ioport = _asc_def_iop_base[id];
11502 advansys_release(dev_get_drvdata(dev));
11503 release_region(ioport, ASC_IOADR_GAP);
11504 return 0;
11505 }
11506
11507 static struct isa_driver advansys_isa_driver = {
11508 .probe = advansys_isa_probe,
11509 .remove = advansys_isa_remove,
11510 .driver = {
11511 .owner = THIS_MODULE,
11512 .name = DRV_NAME,
11513 },
11514 };
11515
11516 /*
11517 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
11518 * 000: invalid
11519 * 001: 10
11520 * 010: 11
11521 * 011: 12
11522 * 100: invalid
11523 * 101: 14
11524 * 110: 15
11525 * 111: invalid
11526 */
11527 static unsigned int advansys_vlb_irq_no(PortAddr iop_base)
11528 {
11529 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11530 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
11531 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
11532 return 0;
11533 return chip_irq;
11534 }
11535
11536 static int advansys_vlb_probe(struct device *dev, unsigned int id)
11537 {
11538 int err = -ENODEV;
11539 PortAddr iop_base = _asc_def_iop_base[id];
11540 struct Scsi_Host *shost;
11541 struct asc_board *board;
11542
11543 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
11544 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
11545 return -ENODEV;
11546 }
11547 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
11548 if (!AscFindSignature(iop_base))
11549 goto release_region;
11550 /*
11551 * I don't think this condition can actually happen, but the old
11552 * driver did it, and the chances of finding a VLB setup in 2007
11553 * to do testing with is slight to none.
11554 */
11555 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
11556 goto release_region;
11557
11558 err = -ENOMEM;
11559 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11560 if (!shost)
11561 goto release_region;
11562
11563 board = shost_priv(shost);
11564 board->irq = advansys_vlb_irq_no(iop_base);
11565 board->dev = dev;
11566 board->shost = shost;
11567
11568 err = advansys_board_found(shost, iop_base, ASC_IS_VL);
11569 if (err)
11570 goto free_host;
11571
11572 dev_set_drvdata(dev, shost);
11573 return 0;
11574
11575 free_host:
11576 scsi_host_put(shost);
11577 release_region:
11578 release_region(iop_base, ASC_IOADR_GAP);
11579 return -ENODEV;
11580 }
11581
11582 static struct isa_driver advansys_vlb_driver = {
11583 .probe = advansys_vlb_probe,
11584 .remove = advansys_isa_remove,
11585 .driver = {
11586 .owner = THIS_MODULE,
11587 .name = "advansys_vlb",
11588 },
11589 };
11590
11591 static struct eisa_device_id advansys_eisa_table[] = {
11592 { "ABP7401" },
11593 { "ABP7501" },
11594 { "" }
11595 };
11596
11597 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
11598
11599 /*
11600 * EISA is a little more tricky than PCI; each EISA device may have two
11601 * channels, and this driver is written to make each channel its own Scsi_Host
11602 */
11603 struct eisa_scsi_data {
11604 struct Scsi_Host *host[2];
11605 };
11606
11607 /*
11608 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
11609 * 000: 10
11610 * 001: 11
11611 * 010: 12
11612 * 011: invalid
11613 * 100: 14
11614 * 101: 15
11615 * 110: invalid
11616 * 111: invalid
11617 */
11618 static unsigned int advansys_eisa_irq_no(struct eisa_device *edev)
11619 {
11620 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
11621 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
11622 if ((chip_irq == 13) || (chip_irq > 15))
11623 return 0;
11624 return chip_irq;
11625 }
11626
11627 static int advansys_eisa_probe(struct device *dev)
11628 {
11629 int i, ioport, irq = 0;
11630 int err;
11631 struct eisa_device *edev = to_eisa_device(dev);
11632 struct eisa_scsi_data *data;
11633
11634 err = -ENOMEM;
11635 data = kzalloc(sizeof(*data), GFP_KERNEL);
11636 if (!data)
11637 goto fail;
11638 ioport = edev->base_addr + 0xc30;
11639
11640 err = -ENODEV;
11641 for (i = 0; i < 2; i++, ioport += 0x20) {
11642 struct asc_board *board;
11643 struct Scsi_Host *shost;
11644 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
11645 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
11646 ioport + ASC_IOADR_GAP - 1);
11647 continue;
11648 }
11649 if (!AscFindSignature(ioport)) {
11650 release_region(ioport, ASC_IOADR_GAP);
11651 continue;
11652 }
11653
11654 /*
11655 * I don't know why we need to do this for EISA chips, but
11656 * not for any others. It looks to be equivalent to
11657 * AscGetChipCfgMsw, but I may have overlooked something,
11658 * so I'm not converting it until I get an EISA board to
11659 * test with.
11660 */
11661 inw(ioport + 4);
11662
11663 if (!irq)
11664 irq = advansys_eisa_irq_no(edev);
11665
11666 err = -ENOMEM;
11667 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11668 if (!shost)
11669 goto release_region;
11670
11671 board = shost_priv(shost);
11672 board->irq = irq;
11673 board->dev = dev;
11674 board->shost = shost;
11675
11676 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
11677 if (!err) {
11678 data->host[i] = shost;
11679 continue;
11680 }
11681
11682 scsi_host_put(shost);
11683 release_region:
11684 release_region(ioport, ASC_IOADR_GAP);
11685 break;
11686 }
11687
11688 if (err)
11689 goto free_data;
11690 dev_set_drvdata(dev, data);
11691 return 0;
11692
11693 free_data:
11694 kfree(data->host[0]);
11695 kfree(data->host[1]);
11696 kfree(data);
11697 fail:
11698 return err;
11699 }
11700
11701 static int advansys_eisa_remove(struct device *dev)
11702 {
11703 int i;
11704 struct eisa_scsi_data *data = dev_get_drvdata(dev);
11705
11706 for (i = 0; i < 2; i++) {
11707 int ioport;
11708 struct Scsi_Host *shost = data->host[i];
11709 if (!shost)
11710 continue;
11711 ioport = shost->io_port;
11712 advansys_release(shost);
11713 release_region(ioport, ASC_IOADR_GAP);
11714 }
11715
11716 kfree(data);
11717 return 0;
11718 }
11719
11720 static struct eisa_driver advansys_eisa_driver = {
11721 .id_table = advansys_eisa_table,
11722 .driver = {
11723 .name = DRV_NAME,
11724 .probe = advansys_eisa_probe,
11725 .remove = advansys_eisa_remove,
11726 }
11727 };
11728
11729 /* PCI Devices supported by this driver */
11730 static struct pci_device_id advansys_pci_tbl[] = {
11731 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
11732 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11733 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
11734 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11735 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
11736 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11737 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
11738 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11739 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
11740 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11741 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
11742 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11743 {}
11744 };
11745
11746 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
11747
11748 static void advansys_set_latency(struct pci_dev *pdev)
11749 {
11750 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
11751 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
11752 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
11753 } else {
11754 u8 latency;
11755 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
11756 if (latency < 0x20)
11757 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
11758 }
11759 }
11760
11761 static int advansys_pci_probe(struct pci_dev *pdev,
11762 const struct pci_device_id *ent)
11763 {
11764 int err, ioport;
11765 struct Scsi_Host *shost;
11766 struct asc_board *board;
11767
11768 err = pci_enable_device(pdev);
11769 if (err)
11770 goto fail;
11771 err = pci_request_regions(pdev, DRV_NAME);
11772 if (err)
11773 goto disable_device;
11774 pci_set_master(pdev);
11775 advansys_set_latency(pdev);
11776
11777 err = -ENODEV;
11778 if (pci_resource_len(pdev, 0) == 0)
11779 goto release_region;
11780
11781 ioport = pci_resource_start(pdev, 0);
11782
11783 err = -ENOMEM;
11784 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11785 if (!shost)
11786 goto release_region;
11787
11788 board = shost_priv(shost);
11789 board->irq = pdev->irq;
11790 board->dev = &pdev->dev;
11791 board->shost = shost;
11792
11793 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
11794 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
11795 pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
11796 board->flags |= ASC_IS_WIDE_BOARD;
11797 }
11798
11799 err = advansys_board_found(shost, ioport, ASC_IS_PCI);
11800 if (err)
11801 goto free_host;
11802
11803 pci_set_drvdata(pdev, shost);
11804 return 0;
11805
11806 free_host:
11807 scsi_host_put(shost);
11808 release_region:
11809 pci_release_regions(pdev);
11810 disable_device:
11811 pci_disable_device(pdev);
11812 fail:
11813 return err;
11814 }
11815
11816 static void advansys_pci_remove(struct pci_dev *pdev)
11817 {
11818 advansys_release(pci_get_drvdata(pdev));
11819 pci_release_regions(pdev);
11820 pci_disable_device(pdev);
11821 }
11822
11823 static struct pci_driver advansys_pci_driver = {
11824 .name = DRV_NAME,
11825 .id_table = advansys_pci_tbl,
11826 .probe = advansys_pci_probe,
11827 .remove = advansys_pci_remove,
11828 };
11829
11830 static int __init advansys_init(void)
11831 {
11832 int error;
11833
11834 error = isa_register_driver(&advansys_isa_driver,
11835 ASC_IOADR_TABLE_MAX_IX);
11836 if (error)
11837 goto fail;
11838
11839 error = isa_register_driver(&advansys_vlb_driver,
11840 ASC_IOADR_TABLE_MAX_IX);
11841 if (error)
11842 goto unregister_isa;
11843
11844 error = eisa_driver_register(&advansys_eisa_driver);
11845 if (error)
11846 goto unregister_vlb;
11847
11848 error = pci_register_driver(&advansys_pci_driver);
11849 if (error)
11850 goto unregister_eisa;
11851
11852 return 0;
11853
11854 unregister_eisa:
11855 eisa_driver_unregister(&advansys_eisa_driver);
11856 unregister_vlb:
11857 isa_unregister_driver(&advansys_vlb_driver);
11858 unregister_isa:
11859 isa_unregister_driver(&advansys_isa_driver);
11860 fail:
11861 return error;
11862 }
11863
11864 static void __exit advansys_exit(void)
11865 {
11866 pci_unregister_driver(&advansys_pci_driver);
11867 eisa_driver_unregister(&advansys_eisa_driver);
11868 isa_unregister_driver(&advansys_vlb_driver);
11869 isa_unregister_driver(&advansys_isa_driver);
11870 }
11871
11872 module_init(advansys_init);
11873 module_exit(advansys_exit);
11874
11875 MODULE_LICENSE("GPL");
11876 MODULE_FIRMWARE("advansys/mcode.bin");
11877 MODULE_FIRMWARE("advansys/3550.bin");
11878 MODULE_FIRMWARE("advansys/38C0800.bin");
11879 MODULE_FIRMWARE("advansys/38C1600.bin");
Linux kernel - Deliverables
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