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advansys: remove 'ERR' definition
[deliverable/linux.git] / drivers / scsi / advansys.c
1 #define DRV_NAME "advansys"
2 #define ASC_VERSION "3.4" /* AdvanSys Driver Version */
3
4 /*
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
6 *
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
10 * All Rights Reserved.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18 /*
19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
22 */
23
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/ioport.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/slab.h>
32 #include <linux/mm.h>
33 #include <linux/proc_fs.h>
34 #include <linux/init.h>
35 #include <linux/blkdev.h>
36 #include <linux/isa.h>
37 #include <linux/eisa.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/firmware.h>
42
43 #include <asm/io.h>
44 #include <asm/dma.h>
45
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <scsi/scsi_tcq.h>
49 #include <scsi/scsi.h>
50 #include <scsi/scsi_host.h>
51
52 /* FIXME:
53 *
54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
61 * safely?
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
69 * 8. Add module_param to override ISA/VLB ioport array
70 */
71 #warning this driver is still not properly converted to the DMA API
72
73 /* Enable driver /proc statistics. */
74 #define ADVANSYS_STATS
75
76 /* Enable driver tracing. */
77 #undef ADVANSYS_DEBUG
78
79 typedef unsigned char uchar;
80
81 #define UW_ERR (uint)(0xFFFF)
82 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
83
84 #define PCI_VENDOR_ID_ASP 0x10cd
85 #define PCI_DEVICE_ID_ASP_1200A 0x1100
86 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
87 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
88 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
89 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
90 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
91
92 /*
93 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
94 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
95 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
96 * SRB structure.
97 */
98 #define CC_VERY_LONG_SG_LIST 0
99 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
100
101 #define PortAddr unsigned int /* port address size */
102 #define inp(port) inb(port)
103 #define outp(port, byte) outb((byte), (port))
104
105 #define inpw(port) inw(port)
106 #define outpw(port, word) outw((word), (port))
107
108 #define ASC_MAX_SG_QUEUE 7
109 #define ASC_MAX_SG_LIST 255
110
111 #define ASC_CS_TYPE unsigned short
112
113 #define ASC_IS_ISA (0x0001)
114 #define ASC_IS_ISAPNP (0x0081)
115 #define ASC_IS_EISA (0x0002)
116 #define ASC_IS_PCI (0x0004)
117 #define ASC_IS_PCI_ULTRA (0x0104)
118 #define ASC_IS_PCMCIA (0x0008)
119 #define ASC_IS_MCA (0x0020)
120 #define ASC_IS_VL (0x0040)
121 #define ASC_IS_WIDESCSI_16 (0x0100)
122 #define ASC_IS_WIDESCSI_32 (0x0200)
123 #define ASC_IS_BIG_ENDIAN (0x8000)
124
125 #define ASC_CHIP_MIN_VER_VL (0x01)
126 #define ASC_CHIP_MAX_VER_VL (0x07)
127 #define ASC_CHIP_MIN_VER_PCI (0x09)
128 #define ASC_CHIP_MAX_VER_PCI (0x0F)
129 #define ASC_CHIP_VER_PCI_BIT (0x08)
130 #define ASC_CHIP_MIN_VER_ISA (0x11)
131 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
132 #define ASC_CHIP_MAX_VER_ISA (0x27)
133 #define ASC_CHIP_VER_ISA_BIT (0x30)
134 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
135 #define ASC_CHIP_VER_ASYN_BUG (0x21)
136 #define ASC_CHIP_VER_PCI 0x08
137 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
138 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
139 #define ASC_CHIP_MIN_VER_EISA (0x41)
140 #define ASC_CHIP_MAX_VER_EISA (0x47)
141 #define ASC_CHIP_VER_EISA_BIT (0x40)
142 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
143 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
144 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
145 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
146
147 #define ASC_SCSI_ID_BITS 3
148 #define ASC_SCSI_TIX_TYPE uchar
149 #define ASC_ALL_DEVICE_BIT_SET 0xFF
150 #define ASC_SCSI_BIT_ID_TYPE uchar
151 #define ASC_MAX_TID 7
152 #define ASC_MAX_LUN 7
153 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
154 #define ASC_MAX_SENSE_LEN 32
155 #define ASC_MIN_SENSE_LEN 14
156 #define ASC_SCSI_RESET_HOLD_TIME_US 60
157
158 /*
159 * Narrow boards only support 12-byte commands, while wide boards
160 * extend to 16-byte commands.
161 */
162 #define ASC_MAX_CDB_LEN 12
163 #define ADV_MAX_CDB_LEN 16
164
165 #define MS_SDTR_LEN 0x03
166 #define MS_WDTR_LEN 0x02
167
168 #define ASC_SG_LIST_PER_Q 7
169 #define QS_FREE 0x00
170 #define QS_READY 0x01
171 #define QS_DISC1 0x02
172 #define QS_DISC2 0x04
173 #define QS_BUSY 0x08
174 #define QS_ABORTED 0x40
175 #define QS_DONE 0x80
176 #define QC_NO_CALLBACK 0x01
177 #define QC_SG_SWAP_QUEUE 0x02
178 #define QC_SG_HEAD 0x04
179 #define QC_DATA_IN 0x08
180 #define QC_DATA_OUT 0x10
181 #define QC_URGENT 0x20
182 #define QC_MSG_OUT 0x40
183 #define QC_REQ_SENSE 0x80
184 #define QCSG_SG_XFER_LIST 0x02
185 #define QCSG_SG_XFER_MORE 0x04
186 #define QCSG_SG_XFER_END 0x08
187 #define QD_IN_PROGRESS 0x00
188 #define QD_NO_ERROR 0x01
189 #define QD_ABORTED_BY_HOST 0x02
190 #define QD_WITH_ERROR 0x04
191 #define QD_INVALID_REQUEST 0x80
192 #define QD_INVALID_HOST_NUM 0x81
193 #define QD_INVALID_DEVICE 0x82
194 #define QD_ERR_INTERNAL 0xFF
195 #define QHSTA_NO_ERROR 0x00
196 #define QHSTA_M_SEL_TIMEOUT 0x11
197 #define QHSTA_M_DATA_OVER_RUN 0x12
198 #define QHSTA_M_DATA_UNDER_RUN 0x12
199 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
200 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
201 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
202 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
203 #define QHSTA_D_HOST_ABORT_FAILED 0x23
204 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
205 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
206 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
207 #define QHSTA_M_WTM_TIMEOUT 0x41
208 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
209 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
210 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
211 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
212 #define QHSTA_M_BAD_TAG_CODE 0x46
213 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
214 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
215 #define QHSTA_D_LRAM_CMP_ERROR 0x81
216 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
217 #define ASC_FLAG_SCSIQ_REQ 0x01
218 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
219 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
220 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
221 #define ASC_FLAG_WIN16 0x10
222 #define ASC_FLAG_WIN32 0x20
223 #define ASC_FLAG_ISA_OVER_16MB 0x40
224 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
225 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
226 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
227 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
228 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
229 #define ASC_SCSIQ_CPY_BEG 4
230 #define ASC_SCSIQ_SGHD_CPY_BEG 2
231 #define ASC_SCSIQ_B_FWD 0
232 #define ASC_SCSIQ_B_BWD 1
233 #define ASC_SCSIQ_B_STATUS 2
234 #define ASC_SCSIQ_B_QNO 3
235 #define ASC_SCSIQ_B_CNTL 4
236 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
237 #define ASC_SCSIQ_D_DATA_ADDR 8
238 #define ASC_SCSIQ_D_DATA_CNT 12
239 #define ASC_SCSIQ_B_SENSE_LEN 20
240 #define ASC_SCSIQ_DONE_INFO_BEG 22
241 #define ASC_SCSIQ_D_SRBPTR 22
242 #define ASC_SCSIQ_B_TARGET_IX 26
243 #define ASC_SCSIQ_B_CDB_LEN 28
244 #define ASC_SCSIQ_B_TAG_CODE 29
245 #define ASC_SCSIQ_W_VM_ID 30
246 #define ASC_SCSIQ_DONE_STATUS 32
247 #define ASC_SCSIQ_HOST_STATUS 33
248 #define ASC_SCSIQ_SCSI_STATUS 34
249 #define ASC_SCSIQ_CDB_BEG 36
250 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
251 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
252 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
253 #define ASC_SCSIQ_B_SG_WK_QP 49
254 #define ASC_SCSIQ_B_SG_WK_IX 50
255 #define ASC_SCSIQ_W_ALT_DC1 52
256 #define ASC_SCSIQ_B_LIST_CNT 6
257 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
258 #define ASC_SGQ_B_SG_CNTL 4
259 #define ASC_SGQ_B_SG_HEAD_QP 5
260 #define ASC_SGQ_B_SG_LIST_CNT 6
261 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
262 #define ASC_SGQ_LIST_BEG 8
263 #define ASC_DEF_SCSI1_QNG 4
264 #define ASC_MAX_SCSI1_QNG 4
265 #define ASC_DEF_SCSI2_QNG 16
266 #define ASC_MAX_SCSI2_QNG 32
267 #define ASC_TAG_CODE_MASK 0x23
268 #define ASC_STOP_REQ_RISC_STOP 0x01
269 #define ASC_STOP_ACK_RISC_STOP 0x03
270 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
271 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
272 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
273 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
274 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
275 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
276 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
277 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
278 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
279 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
280
281 typedef struct asc_scsiq_1 {
282 uchar status;
283 uchar q_no;
284 uchar cntl;
285 uchar sg_queue_cnt;
286 uchar target_id;
287 uchar target_lun;
288 __le32 data_addr;
289 __le32 data_cnt;
290 __le32 sense_addr;
291 uchar sense_len;
292 uchar extra_bytes;
293 } ASC_SCSIQ_1;
294
295 typedef struct asc_scsiq_2 {
296 u32 srb_tag;
297 uchar target_ix;
298 uchar flag;
299 uchar cdb_len;
300 uchar tag_code;
301 ushort vm_id;
302 } ASC_SCSIQ_2;
303
304 typedef struct asc_scsiq_3 {
305 uchar done_stat;
306 uchar host_stat;
307 uchar scsi_stat;
308 uchar scsi_msg;
309 } ASC_SCSIQ_3;
310
311 typedef struct asc_scsiq_4 {
312 uchar cdb[ASC_MAX_CDB_LEN];
313 uchar y_first_sg_list_qp;
314 uchar y_working_sg_qp;
315 uchar y_working_sg_ix;
316 uchar y_res;
317 ushort x_req_count;
318 ushort x_reconnect_rtn;
319 __le32 x_saved_data_addr;
320 __le32 x_saved_data_cnt;
321 } ASC_SCSIQ_4;
322
323 typedef struct asc_q_done_info {
324 ASC_SCSIQ_2 d2;
325 ASC_SCSIQ_3 d3;
326 uchar q_status;
327 uchar q_no;
328 uchar cntl;
329 uchar sense_len;
330 uchar extra_bytes;
331 uchar res;
332 u32 remain_bytes;
333 } ASC_QDONE_INFO;
334
335 typedef struct asc_sg_list {
336 __le32 addr;
337 __le32 bytes;
338 } ASC_SG_LIST;
339
340 typedef struct asc_sg_head {
341 ushort entry_cnt;
342 ushort queue_cnt;
343 ushort entry_to_copy;
344 ushort res;
345 ASC_SG_LIST sg_list[0];
346 } ASC_SG_HEAD;
347
348 typedef struct asc_scsi_q {
349 ASC_SCSIQ_1 q1;
350 ASC_SCSIQ_2 q2;
351 uchar *cdbptr;
352 ASC_SG_HEAD *sg_head;
353 ushort remain_sg_entry_cnt;
354 ushort next_sg_index;
355 } ASC_SCSI_Q;
356
357 typedef struct asc_scsi_req_q {
358 ASC_SCSIQ_1 r1;
359 ASC_SCSIQ_2 r2;
360 uchar *cdbptr;
361 ASC_SG_HEAD *sg_head;
362 uchar *sense_ptr;
363 ASC_SCSIQ_3 r3;
364 uchar cdb[ASC_MAX_CDB_LEN];
365 uchar sense[ASC_MIN_SENSE_LEN];
366 } ASC_SCSI_REQ_Q;
367
368 typedef struct asc_scsi_bios_req_q {
369 ASC_SCSIQ_1 r1;
370 ASC_SCSIQ_2 r2;
371 uchar *cdbptr;
372 ASC_SG_HEAD *sg_head;
373 uchar *sense_ptr;
374 ASC_SCSIQ_3 r3;
375 uchar cdb[ASC_MAX_CDB_LEN];
376 uchar sense[ASC_MIN_SENSE_LEN];
377 } ASC_SCSI_BIOS_REQ_Q;
378
379 typedef struct asc_risc_q {
380 uchar fwd;
381 uchar bwd;
382 ASC_SCSIQ_1 i1;
383 ASC_SCSIQ_2 i2;
384 ASC_SCSIQ_3 i3;
385 ASC_SCSIQ_4 i4;
386 } ASC_RISC_Q;
387
388 typedef struct asc_sg_list_q {
389 uchar seq_no;
390 uchar q_no;
391 uchar cntl;
392 uchar sg_head_qp;
393 uchar sg_list_cnt;
394 uchar sg_cur_list_cnt;
395 } ASC_SG_LIST_Q;
396
397 typedef struct asc_risc_sg_list_q {
398 uchar fwd;
399 uchar bwd;
400 ASC_SG_LIST_Q sg;
401 ASC_SG_LIST sg_list[7];
402 } ASC_RISC_SG_LIST_Q;
403
404 #define ASCQ_ERR_Q_STATUS 0x0D
405 #define ASCQ_ERR_CUR_QNG 0x17
406 #define ASCQ_ERR_SG_Q_LINKS 0x18
407 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
408 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
409 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
410
411 /*
412 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
413 */
414 #define ASC_WARN_NO_ERROR 0x0000
415 #define ASC_WARN_IO_PORT_ROTATE 0x0001
416 #define ASC_WARN_EEPROM_CHKSUM 0x0002
417 #define ASC_WARN_IRQ_MODIFIED 0x0004
418 #define ASC_WARN_AUTO_CONFIG 0x0008
419 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
420 #define ASC_WARN_EEPROM_RECOVER 0x0020
421 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
422
423 /*
424 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
425 */
426 #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
427 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
428 #define ASC_IERR_SET_PC_ADDR 0x0004
429 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
430 #define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
431 #define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
432 #define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
433 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
434 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
435 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
436 #define ASC_IERR_NO_BUS_TYPE 0x0400
437 #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
438 #define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
439 #define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
440
441 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
442 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
443 #define ASC_MIN_FREE_Q (0x02)
444 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
445 #define ASC_MAX_TOTAL_QNG 240
446 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
447 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
448 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
449 #define ASC_MAX_INRAM_TAG_QNG 16
450 #define ASC_IOADR_GAP 0x10
451 #define ASC_SYN_MAX_OFFSET 0x0F
452 #define ASC_DEF_SDTR_OFFSET 0x0F
453 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
454 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
455
456 /* The narrow chip only supports a limited selection of transfer rates.
457 * These are encoded in the range 0..7 or 0..15 depending whether the chip
458 * is Ultra-capable or not. These tables let us convert from one to the other.
459 */
460 static const unsigned char asc_syn_xfer_period[8] = {
461 25, 30, 35, 40, 50, 60, 70, 85
462 };
463
464 static const unsigned char asc_syn_ultra_xfer_period[16] = {
465 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
466 };
467
468 typedef struct ext_msg {
469 uchar msg_type;
470 uchar msg_len;
471 uchar msg_req;
472 union {
473 struct {
474 uchar sdtr_xfer_period;
475 uchar sdtr_req_ack_offset;
476 } sdtr;
477 struct {
478 uchar wdtr_width;
479 } wdtr;
480 struct {
481 uchar mdp_b3;
482 uchar mdp_b2;
483 uchar mdp_b1;
484 uchar mdp_b0;
485 } mdp;
486 } u_ext_msg;
487 uchar res;
488 } EXT_MSG;
489
490 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
491 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
492 #define wdtr_width u_ext_msg.wdtr.wdtr_width
493 #define mdp_b3 u_ext_msg.mdp_b3
494 #define mdp_b2 u_ext_msg.mdp_b2
495 #define mdp_b1 u_ext_msg.mdp_b1
496 #define mdp_b0 u_ext_msg.mdp_b0
497
498 typedef struct asc_dvc_cfg {
499 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
500 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
501 ASC_SCSI_BIT_ID_TYPE disc_enable;
502 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
503 uchar chip_scsi_id;
504 uchar isa_dma_speed;
505 uchar isa_dma_channel;
506 uchar chip_version;
507 ushort mcode_date;
508 ushort mcode_version;
509 uchar max_tag_qng[ASC_MAX_TID + 1];
510 uchar sdtr_period_offset[ASC_MAX_TID + 1];
511 uchar adapter_info[6];
512 } ASC_DVC_CFG;
513
514 #define ASC_DEF_DVC_CNTL 0xFFFF
515 #define ASC_DEF_CHIP_SCSI_ID 7
516 #define ASC_DEF_ISA_DMA_SPEED 4
517 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
518 #define ASC_INIT_STATE_END_GET_CFG 0x0002
519 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
520 #define ASC_INIT_STATE_END_SET_CFG 0x0008
521 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
522 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
523 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
524 #define ASC_INIT_STATE_END_INQUIRY 0x0080
525 #define ASC_INIT_RESET_SCSI_DONE 0x0100
526 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
527 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
528 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
529 #define ASC_MIN_TAGGED_CMD 7
530 #define ASC_MAX_SCSI_RESET_WAIT 30
531 #define ASC_OVERRUN_BSIZE 64
532
533 struct asc_dvc_var; /* Forward Declaration. */
534
535 typedef struct asc_dvc_var {
536 PortAddr iop_base;
537 ushort err_code;
538 ushort dvc_cntl;
539 ushort bug_fix_cntl;
540 ushort bus_type;
541 ASC_SCSI_BIT_ID_TYPE init_sdtr;
542 ASC_SCSI_BIT_ID_TYPE sdtr_done;
543 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
544 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
545 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
546 ASC_SCSI_BIT_ID_TYPE start_motor;
547 uchar *overrun_buf;
548 dma_addr_t overrun_dma;
549 uchar scsi_reset_wait;
550 uchar chip_no;
551 bool is_in_int;
552 uchar max_total_qng;
553 uchar cur_total_qng;
554 uchar in_critical_cnt;
555 uchar last_q_shortage;
556 ushort init_state;
557 uchar cur_dvc_qng[ASC_MAX_TID + 1];
558 uchar max_dvc_qng[ASC_MAX_TID + 1];
559 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
560 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
561 const uchar *sdtr_period_tbl;
562 ASC_DVC_CFG *cfg;
563 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
564 char redo_scam;
565 ushort res2;
566 uchar dos_int13_table[ASC_MAX_TID + 1];
567 unsigned int max_dma_count;
568 ASC_SCSI_BIT_ID_TYPE no_scam;
569 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
570 uchar min_sdtr_index;
571 uchar max_sdtr_index;
572 struct asc_board *drv_ptr;
573 unsigned int uc_break;
574 } ASC_DVC_VAR;
575
576 typedef struct asc_dvc_inq_info {
577 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
578 } ASC_DVC_INQ_INFO;
579
580 typedef struct asc_cap_info {
581 u32 lba;
582 u32 blk_size;
583 } ASC_CAP_INFO;
584
585 typedef struct asc_cap_info_array {
586 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
587 } ASC_CAP_INFO_ARRAY;
588
589 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
590 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
591 #define ASC_CNTL_INITIATOR (ushort)0x0001
592 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
593 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
594 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
595 #define ASC_CNTL_NO_SCAM (ushort)0x0010
596 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
597 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
598 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
599 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
600 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
601 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
602 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
603 #define ASC_CNTL_BURST_MODE (ushort)0x2000
604 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
605 #define ASC_EEP_DVC_CFG_BEG_VL 2
606 #define ASC_EEP_MAX_DVC_ADDR_VL 15
607 #define ASC_EEP_DVC_CFG_BEG 32
608 #define ASC_EEP_MAX_DVC_ADDR 45
609 #define ASC_EEP_MAX_RETRY 20
610
611 /*
612 * These macros keep the chip SCSI id and ISA DMA speed
613 * bitfields in board order. C bitfields aren't portable
614 * between big and little-endian platforms so they are
615 * not used.
616 */
617
618 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
619 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
620 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
621 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
622 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
623 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
624
625 typedef struct asceep_config {
626 ushort cfg_lsw;
627 ushort cfg_msw;
628 uchar init_sdtr;
629 uchar disc_enable;
630 uchar use_cmd_qng;
631 uchar start_motor;
632 uchar max_total_qng;
633 uchar max_tag_qng;
634 uchar bios_scan;
635 uchar power_up_wait;
636 uchar no_scam;
637 uchar id_speed; /* low order 4 bits is chip scsi id */
638 /* high order 4 bits is isa dma speed */
639 uchar dos_int13_table[ASC_MAX_TID + 1];
640 uchar adapter_info[6];
641 ushort cntl;
642 ushort chksum;
643 } ASCEEP_CONFIG;
644
645 #define ASC_EEP_CMD_READ 0x80
646 #define ASC_EEP_CMD_WRITE 0x40
647 #define ASC_EEP_CMD_WRITE_ABLE 0x30
648 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
649 #define ASCV_MSGOUT_BEG 0x0000
650 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
651 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
652 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
653 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
654 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
655 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
656 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
657 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
658 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
659 #define ASCV_BREAK_ADDR (ushort)0x0028
660 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
661 #define ASCV_BREAK_CONTROL (ushort)0x002C
662 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
663
664 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
665 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
666 #define ASCV_MCODE_SIZE_W (ushort)0x0034
667 #define ASCV_STOP_CODE_B (ushort)0x0036
668 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
669 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
670 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
671 #define ASCV_HALTCODE_W (ushort)0x0040
672 #define ASCV_CHKSUM_W (ushort)0x0042
673 #define ASCV_MC_DATE_W (ushort)0x0044
674 #define ASCV_MC_VER_W (ushort)0x0046
675 #define ASCV_NEXTRDY_B (ushort)0x0048
676 #define ASCV_DONENEXT_B (ushort)0x0049
677 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
678 #define ASCV_SCSIBUSY_B (ushort)0x004B
679 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
680 #define ASCV_CURCDB_B (ushort)0x004D
681 #define ASCV_RCLUN_B (ushort)0x004E
682 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
683 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
684 #define ASCV_DISC_ENABLE_B (ushort)0x0052
685 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
686 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
687 #define ASCV_MCODE_CNTL_B (ushort)0x0056
688 #define ASCV_NULL_TARGET_B (ushort)0x0057
689 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
690 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
691 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
692 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
693 #define ASCV_HOST_FLAG_B (ushort)0x005D
694 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
695 #define ASCV_VER_SERIAL_B (ushort)0x0065
696 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
697 #define ASCV_WTM_FLAG_B (ushort)0x0068
698 #define ASCV_RISC_FLAG_B (ushort)0x006A
699 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
700 #define ASC_HOST_FLAG_IN_ISR 0x01
701 #define ASC_HOST_FLAG_ACK_INT 0x02
702 #define ASC_RISC_FLAG_GEN_INT 0x01
703 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
704 #define IOP_CTRL (0x0F)
705 #define IOP_STATUS (0x0E)
706 #define IOP_INT_ACK IOP_STATUS
707 #define IOP_REG_IFC (0x0D)
708 #define IOP_SYN_OFFSET (0x0B)
709 #define IOP_EXTRA_CONTROL (0x0D)
710 #define IOP_REG_PC (0x0C)
711 #define IOP_RAM_ADDR (0x0A)
712 #define IOP_RAM_DATA (0x08)
713 #define IOP_EEP_DATA (0x06)
714 #define IOP_EEP_CMD (0x07)
715 #define IOP_VERSION (0x03)
716 #define IOP_CONFIG_HIGH (0x04)
717 #define IOP_CONFIG_LOW (0x02)
718 #define IOP_SIG_BYTE (0x01)
719 #define IOP_SIG_WORD (0x00)
720 #define IOP_REG_DC1 (0x0E)
721 #define IOP_REG_DC0 (0x0C)
722 #define IOP_REG_SB (0x0B)
723 #define IOP_REG_DA1 (0x0A)
724 #define IOP_REG_DA0 (0x08)
725 #define IOP_REG_SC (0x09)
726 #define IOP_DMA_SPEED (0x07)
727 #define IOP_REG_FLAG (0x07)
728 #define IOP_FIFO_H (0x06)
729 #define IOP_FIFO_L (0x04)
730 #define IOP_REG_ID (0x05)
731 #define IOP_REG_QP (0x03)
732 #define IOP_REG_IH (0x02)
733 #define IOP_REG_IX (0x01)
734 #define IOP_REG_AX (0x00)
735 #define IFC_REG_LOCK (0x00)
736 #define IFC_REG_UNLOCK (0x09)
737 #define IFC_WR_EN_FILTER (0x10)
738 #define IFC_RD_NO_EEPROM (0x10)
739 #define IFC_SLEW_RATE (0x20)
740 #define IFC_ACT_NEG (0x40)
741 #define IFC_INP_FILTER (0x80)
742 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
743 #define SC_SEL (uchar)(0x80)
744 #define SC_BSY (uchar)(0x40)
745 #define SC_ACK (uchar)(0x20)
746 #define SC_REQ (uchar)(0x10)
747 #define SC_ATN (uchar)(0x08)
748 #define SC_IO (uchar)(0x04)
749 #define SC_CD (uchar)(0x02)
750 #define SC_MSG (uchar)(0x01)
751 #define SEC_SCSI_CTL (uchar)(0x80)
752 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
753 #define SEC_SLEW_RATE (uchar)(0x20)
754 #define SEC_ENABLE_FILTER (uchar)(0x10)
755 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
756 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
757 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
758 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
759 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
760 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
761 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
762 #define ASC_MAX_QNO 0xF8
763 #define ASC_DATA_SEC_BEG (ushort)0x0080
764 #define ASC_DATA_SEC_END (ushort)0x0080
765 #define ASC_CODE_SEC_BEG (ushort)0x0080
766 #define ASC_CODE_SEC_END (ushort)0x0080
767 #define ASC_QADR_BEG (0x4000)
768 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
769 #define ASC_QADR_END (ushort)0x7FFF
770 #define ASC_QLAST_ADR (ushort)0x7FC0
771 #define ASC_QBLK_SIZE 0x40
772 #define ASC_BIOS_DATA_QBEG 0xF8
773 #define ASC_MIN_ACTIVE_QNO 0x01
774 #define ASC_QLINK_END 0xFF
775 #define ASC_EEPROM_WORDS 0x10
776 #define ASC_MAX_MGS_LEN 0x10
777 #define ASC_BIOS_ADDR_DEF 0xDC00
778 #define ASC_BIOS_SIZE 0x3800
779 #define ASC_BIOS_RAM_OFF 0x3800
780 #define ASC_BIOS_RAM_SIZE 0x800
781 #define ASC_BIOS_MIN_ADDR 0xC000
782 #define ASC_BIOS_MAX_ADDR 0xEC00
783 #define ASC_BIOS_BANK_SIZE 0x0400
784 #define ASC_MCODE_START_ADDR 0x0080
785 #define ASC_CFG0_HOST_INT_ON 0x0020
786 #define ASC_CFG0_BIOS_ON 0x0040
787 #define ASC_CFG0_VERA_BURST_ON 0x0080
788 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
789 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
790 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
791 #define ASC_CFG_MSW_CLR_MASK 0x3080
792 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
793 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
794 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
795 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
796 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
797 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
798 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
799 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
800 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
801 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
802 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
803 #define CSW_HALTED (ASC_CS_TYPE)0x0010
804 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
805 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
806 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
807 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
808 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
809 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
810 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
811 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
812 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
813 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
814 #define CC_CHIP_RESET (uchar)0x80
815 #define CC_SCSI_RESET (uchar)0x40
816 #define CC_HALT (uchar)0x20
817 #define CC_SINGLE_STEP (uchar)0x10
818 #define CC_DMA_ABLE (uchar)0x08
819 #define CC_TEST (uchar)0x04
820 #define CC_BANK_ONE (uchar)0x02
821 #define CC_DIAG (uchar)0x01
822 #define ASC_1000_ID0W 0x04C1
823 #define ASC_1000_ID0W_FIX 0x00C1
824 #define ASC_1000_ID1B 0x25
825 #define ASC_EISA_REV_IOP_MASK (0x0C83)
826 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
827 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
828 #define INS_HALTINT (ushort)0x6281
829 #define INS_HALT (ushort)0x6280
830 #define INS_SINT (ushort)0x6200
831 #define INS_RFLAG_WTM (ushort)0x7380
832 #define ASC_MC_SAVE_CODE_WSIZE 0x500
833 #define ASC_MC_SAVE_DATA_WSIZE 0x40
834
835 typedef struct asc_mc_saved {
836 ushort data[ASC_MC_SAVE_DATA_WSIZE];
837 ushort code[ASC_MC_SAVE_CODE_WSIZE];
838 } ASC_MC_SAVED;
839
840 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
841 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
842 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
843 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
844 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
845 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
846 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
847 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
848 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
849 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
850 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
851 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
852 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
853 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
854 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
855 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
856 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
857 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
858 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
859 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
860 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
861 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
862 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
863 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
864 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
865 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
866 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
867 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
868 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
869 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
870 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
871 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
872 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
873 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
874 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
875 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
876 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
877 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
878 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
879 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
880 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
881 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
882 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
883 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
884 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
885 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
886 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
887 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
888 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
889 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
890 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
891 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
892 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
893 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
894 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
895 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
896 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
897 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
898 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
899 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
900 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
901 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
902 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
903 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
904 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
905 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
906 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
907
908 /*
909 * These macros are used to convert a virtual address to a
910 * 32-bit value. This currently can be used on Linux Alpha
911 * which uses 64-bit virtual address but a 32-bit bus address.
912 * This is likely to break in the future, but doing this now
913 * will give us time to change the HW and FW to handle 64-bit
914 * addresses.
915 */
916 #define ADV_U32_TO_VADDR bus_to_virt
917
918 #define AdvPortAddr void __iomem * /* Virtual memory address size */
919
920 /*
921 * Define Adv Library required memory access macros.
922 */
923 #define ADV_MEM_READB(addr) readb(addr)
924 #define ADV_MEM_READW(addr) readw(addr)
925 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
926 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
927 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
928
929 /*
930 * Define total number of simultaneous maximum element scatter-gather
931 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
932 * maximum number of outstanding commands per wide host adapter. Each
933 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
934 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
935 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
936 * structures or 255 scatter-gather elements.
937 */
938 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
939
940 /*
941 * Define maximum number of scatter-gather elements per request.
942 */
943 #define ADV_MAX_SG_LIST 255
944 #define NO_OF_SG_PER_BLOCK 15
945
946 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
947 #define ADV_EEP_DVC_CFG_END (0x15)
948 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
949 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
950
951 #define ADV_EEP_DELAY_MS 100
952
953 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
954 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
955 /*
956 * For the ASC3550 Bit 13 is Termination Polarity control bit.
957 * For later ICs Bit 13 controls whether the CIS (Card Information
958 * Service Section) is loaded from EEPROM.
959 */
960 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
961 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
962 /*
963 * ASC38C1600 Bit 11
964 *
965 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
966 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
967 * Function 0 will specify INT B.
968 *
969 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
970 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
971 * Function 1 will specify INT A.
972 */
973 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
974
975 typedef struct adveep_3550_config {
976 /* Word Offset, Description */
977
978 ushort cfg_lsw; /* 00 power up initialization */
979 /* bit 13 set - Term Polarity Control */
980 /* bit 14 set - BIOS Enable */
981 /* bit 15 set - Big Endian Mode */
982 ushort cfg_msw; /* 01 unused */
983 ushort disc_enable; /* 02 disconnect enable */
984 ushort wdtr_able; /* 03 Wide DTR able */
985 ushort sdtr_able; /* 04 Synchronous DTR able */
986 ushort start_motor; /* 05 send start up motor */
987 ushort tagqng_able; /* 06 tag queuing able */
988 ushort bios_scan; /* 07 BIOS device control */
989 ushort scam_tolerant; /* 08 no scam */
990
991 uchar adapter_scsi_id; /* 09 Host Adapter ID */
992 uchar bios_boot_delay; /* power up wait */
993
994 uchar scsi_reset_delay; /* 10 reset delay */
995 uchar bios_id_lun; /* first boot device scsi id & lun */
996 /* high nibble is lun */
997 /* low nibble is scsi id */
998
999 uchar termination; /* 11 0 - automatic */
1000 /* 1 - low off / high off */
1001 /* 2 - low off / high on */
1002 /* 3 - low on / high on */
1003 /* There is no low on / high off */
1004
1005 uchar reserved1; /* reserved byte (not used) */
1006
1007 ushort bios_ctrl; /* 12 BIOS control bits */
1008 /* bit 0 BIOS don't act as initiator. */
1009 /* bit 1 BIOS > 1 GB support */
1010 /* bit 2 BIOS > 2 Disk Support */
1011 /* bit 3 BIOS don't support removables */
1012 /* bit 4 BIOS support bootable CD */
1013 /* bit 5 BIOS scan enabled */
1014 /* bit 6 BIOS support multiple LUNs */
1015 /* bit 7 BIOS display of message */
1016 /* bit 8 SCAM disabled */
1017 /* bit 9 Reset SCSI bus during init. */
1018 /* bit 10 */
1019 /* bit 11 No verbose initialization. */
1020 /* bit 12 SCSI parity enabled */
1021 /* bit 13 */
1022 /* bit 14 */
1023 /* bit 15 */
1024 ushort ultra_able; /* 13 ULTRA speed able */
1025 ushort reserved2; /* 14 reserved */
1026 uchar max_host_qng; /* 15 maximum host queuing */
1027 uchar max_dvc_qng; /* maximum per device queuing */
1028 ushort dvc_cntl; /* 16 control bit for driver */
1029 ushort bug_fix; /* 17 control bit for bug fix */
1030 ushort serial_number_word1; /* 18 Board serial number word 1 */
1031 ushort serial_number_word2; /* 19 Board serial number word 2 */
1032 ushort serial_number_word3; /* 20 Board serial number word 3 */
1033 ushort check_sum; /* 21 EEP check sum */
1034 uchar oem_name[16]; /* 22 OEM name */
1035 ushort dvc_err_code; /* 30 last device driver error code */
1036 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1037 ushort adv_err_addr; /* 32 last uc error address */
1038 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1039 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1040 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1041 ushort num_of_err; /* 36 number of error */
1042 } ADVEEP_3550_CONFIG;
1043
1044 typedef struct adveep_38C0800_config {
1045 /* Word Offset, Description */
1046
1047 ushort cfg_lsw; /* 00 power up initialization */
1048 /* bit 13 set - Load CIS */
1049 /* bit 14 set - BIOS Enable */
1050 /* bit 15 set - Big Endian Mode */
1051 ushort cfg_msw; /* 01 unused */
1052 ushort disc_enable; /* 02 disconnect enable */
1053 ushort wdtr_able; /* 03 Wide DTR able */
1054 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1055 ushort start_motor; /* 05 send start up motor */
1056 ushort tagqng_able; /* 06 tag queuing able */
1057 ushort bios_scan; /* 07 BIOS device control */
1058 ushort scam_tolerant; /* 08 no scam */
1059
1060 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1061 uchar bios_boot_delay; /* power up wait */
1062
1063 uchar scsi_reset_delay; /* 10 reset delay */
1064 uchar bios_id_lun; /* first boot device scsi id & lun */
1065 /* high nibble is lun */
1066 /* low nibble is scsi id */
1067
1068 uchar termination_se; /* 11 0 - automatic */
1069 /* 1 - low off / high off */
1070 /* 2 - low off / high on */
1071 /* 3 - low on / high on */
1072 /* There is no low on / high off */
1073
1074 uchar termination_lvd; /* 11 0 - automatic */
1075 /* 1 - low off / high off */
1076 /* 2 - low off / high on */
1077 /* 3 - low on / high on */
1078 /* There is no low on / high off */
1079
1080 ushort bios_ctrl; /* 12 BIOS control bits */
1081 /* bit 0 BIOS don't act as initiator. */
1082 /* bit 1 BIOS > 1 GB support */
1083 /* bit 2 BIOS > 2 Disk Support */
1084 /* bit 3 BIOS don't support removables */
1085 /* bit 4 BIOS support bootable CD */
1086 /* bit 5 BIOS scan enabled */
1087 /* bit 6 BIOS support multiple LUNs */
1088 /* bit 7 BIOS display of message */
1089 /* bit 8 SCAM disabled */
1090 /* bit 9 Reset SCSI bus during init. */
1091 /* bit 10 */
1092 /* bit 11 No verbose initialization. */
1093 /* bit 12 SCSI parity enabled */
1094 /* bit 13 */
1095 /* bit 14 */
1096 /* bit 15 */
1097 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1098 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1099 uchar max_host_qng; /* 15 maximum host queueing */
1100 uchar max_dvc_qng; /* maximum per device queuing */
1101 ushort dvc_cntl; /* 16 control bit for driver */
1102 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1103 ushort serial_number_word1; /* 18 Board serial number word 1 */
1104 ushort serial_number_word2; /* 19 Board serial number word 2 */
1105 ushort serial_number_word3; /* 20 Board serial number word 3 */
1106 ushort check_sum; /* 21 EEP check sum */
1107 uchar oem_name[16]; /* 22 OEM name */
1108 ushort dvc_err_code; /* 30 last device driver error code */
1109 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1110 ushort adv_err_addr; /* 32 last uc error address */
1111 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1112 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1113 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1114 ushort reserved36; /* 36 reserved */
1115 ushort reserved37; /* 37 reserved */
1116 ushort reserved38; /* 38 reserved */
1117 ushort reserved39; /* 39 reserved */
1118 ushort reserved40; /* 40 reserved */
1119 ushort reserved41; /* 41 reserved */
1120 ushort reserved42; /* 42 reserved */
1121 ushort reserved43; /* 43 reserved */
1122 ushort reserved44; /* 44 reserved */
1123 ushort reserved45; /* 45 reserved */
1124 ushort reserved46; /* 46 reserved */
1125 ushort reserved47; /* 47 reserved */
1126 ushort reserved48; /* 48 reserved */
1127 ushort reserved49; /* 49 reserved */
1128 ushort reserved50; /* 50 reserved */
1129 ushort reserved51; /* 51 reserved */
1130 ushort reserved52; /* 52 reserved */
1131 ushort reserved53; /* 53 reserved */
1132 ushort reserved54; /* 54 reserved */
1133 ushort reserved55; /* 55 reserved */
1134 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1135 ushort cisprt_msw; /* 57 CIS PTR MSW */
1136 ushort subsysvid; /* 58 SubSystem Vendor ID */
1137 ushort subsysid; /* 59 SubSystem ID */
1138 ushort reserved60; /* 60 reserved */
1139 ushort reserved61; /* 61 reserved */
1140 ushort reserved62; /* 62 reserved */
1141 ushort reserved63; /* 63 reserved */
1142 } ADVEEP_38C0800_CONFIG;
1143
1144 typedef struct adveep_38C1600_config {
1145 /* Word Offset, Description */
1146
1147 ushort cfg_lsw; /* 00 power up initialization */
1148 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1149 /* clear - Func. 0 INTA, Func. 1 INTB */
1150 /* bit 13 set - Load CIS */
1151 /* bit 14 set - BIOS Enable */
1152 /* bit 15 set - Big Endian Mode */
1153 ushort cfg_msw; /* 01 unused */
1154 ushort disc_enable; /* 02 disconnect enable */
1155 ushort wdtr_able; /* 03 Wide DTR able */
1156 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1157 ushort start_motor; /* 05 send start up motor */
1158 ushort tagqng_able; /* 06 tag queuing able */
1159 ushort bios_scan; /* 07 BIOS device control */
1160 ushort scam_tolerant; /* 08 no scam */
1161
1162 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1163 uchar bios_boot_delay; /* power up wait */
1164
1165 uchar scsi_reset_delay; /* 10 reset delay */
1166 uchar bios_id_lun; /* first boot device scsi id & lun */
1167 /* high nibble is lun */
1168 /* low nibble is scsi id */
1169
1170 uchar termination_se; /* 11 0 - automatic */
1171 /* 1 - low off / high off */
1172 /* 2 - low off / high on */
1173 /* 3 - low on / high on */
1174 /* There is no low on / high off */
1175
1176 uchar termination_lvd; /* 11 0 - automatic */
1177 /* 1 - low off / high off */
1178 /* 2 - low off / high on */
1179 /* 3 - low on / high on */
1180 /* There is no low on / high off */
1181
1182 ushort bios_ctrl; /* 12 BIOS control bits */
1183 /* bit 0 BIOS don't act as initiator. */
1184 /* bit 1 BIOS > 1 GB support */
1185 /* bit 2 BIOS > 2 Disk Support */
1186 /* bit 3 BIOS don't support removables */
1187 /* bit 4 BIOS support bootable CD */
1188 /* bit 5 BIOS scan enabled */
1189 /* bit 6 BIOS support multiple LUNs */
1190 /* bit 7 BIOS display of message */
1191 /* bit 8 SCAM disabled */
1192 /* bit 9 Reset SCSI bus during init. */
1193 /* bit 10 Basic Integrity Checking disabled */
1194 /* bit 11 No verbose initialization. */
1195 /* bit 12 SCSI parity enabled */
1196 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1197 /* bit 14 */
1198 /* bit 15 */
1199 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1200 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1201 uchar max_host_qng; /* 15 maximum host queueing */
1202 uchar max_dvc_qng; /* maximum per device queuing */
1203 ushort dvc_cntl; /* 16 control bit for driver */
1204 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1205 ushort serial_number_word1; /* 18 Board serial number word 1 */
1206 ushort serial_number_word2; /* 19 Board serial number word 2 */
1207 ushort serial_number_word3; /* 20 Board serial number word 3 */
1208 ushort check_sum; /* 21 EEP check sum */
1209 uchar oem_name[16]; /* 22 OEM name */
1210 ushort dvc_err_code; /* 30 last device driver error code */
1211 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1212 ushort adv_err_addr; /* 32 last uc error address */
1213 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1214 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1215 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1216 ushort reserved36; /* 36 reserved */
1217 ushort reserved37; /* 37 reserved */
1218 ushort reserved38; /* 38 reserved */
1219 ushort reserved39; /* 39 reserved */
1220 ushort reserved40; /* 40 reserved */
1221 ushort reserved41; /* 41 reserved */
1222 ushort reserved42; /* 42 reserved */
1223 ushort reserved43; /* 43 reserved */
1224 ushort reserved44; /* 44 reserved */
1225 ushort reserved45; /* 45 reserved */
1226 ushort reserved46; /* 46 reserved */
1227 ushort reserved47; /* 47 reserved */
1228 ushort reserved48; /* 48 reserved */
1229 ushort reserved49; /* 49 reserved */
1230 ushort reserved50; /* 50 reserved */
1231 ushort reserved51; /* 51 reserved */
1232 ushort reserved52; /* 52 reserved */
1233 ushort reserved53; /* 53 reserved */
1234 ushort reserved54; /* 54 reserved */
1235 ushort reserved55; /* 55 reserved */
1236 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1237 ushort cisprt_msw; /* 57 CIS PTR MSW */
1238 ushort subsysvid; /* 58 SubSystem Vendor ID */
1239 ushort subsysid; /* 59 SubSystem ID */
1240 ushort reserved60; /* 60 reserved */
1241 ushort reserved61; /* 61 reserved */
1242 ushort reserved62; /* 62 reserved */
1243 ushort reserved63; /* 63 reserved */
1244 } ADVEEP_38C1600_CONFIG;
1245
1246 /*
1247 * EEPROM Commands
1248 */
1249 #define ASC_EEP_CMD_DONE 0x0200
1250
1251 /* bios_ctrl */
1252 #define BIOS_CTRL_BIOS 0x0001
1253 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
1254 #define BIOS_CTRL_GT_2_DISK 0x0004
1255 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1256 #define BIOS_CTRL_BOOTABLE_CD 0x0010
1257 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
1258 #define BIOS_CTRL_DISPLAY_MSG 0x0080
1259 #define BIOS_CTRL_NO_SCAM 0x0100
1260 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1261 #define BIOS_CTRL_INIT_VERBOSE 0x0800
1262 #define BIOS_CTRL_SCSI_PARITY 0x1000
1263 #define BIOS_CTRL_AIPP_DIS 0x2000
1264
1265 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1266
1267 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1268
1269 /*
1270 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1271 * a special 16K Adv Library and Microcode version. After the issue is
1272 * resolved, should restore 32K support.
1273 *
1274 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1275 */
1276 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1277
1278 /*
1279 * Byte I/O register address from base of 'iop_base'.
1280 */
1281 #define IOPB_INTR_STATUS_REG 0x00
1282 #define IOPB_CHIP_ID_1 0x01
1283 #define IOPB_INTR_ENABLES 0x02
1284 #define IOPB_CHIP_TYPE_REV 0x03
1285 #define IOPB_RES_ADDR_4 0x04
1286 #define IOPB_RES_ADDR_5 0x05
1287 #define IOPB_RAM_DATA 0x06
1288 #define IOPB_RES_ADDR_7 0x07
1289 #define IOPB_FLAG_REG 0x08
1290 #define IOPB_RES_ADDR_9 0x09
1291 #define IOPB_RISC_CSR 0x0A
1292 #define IOPB_RES_ADDR_B 0x0B
1293 #define IOPB_RES_ADDR_C 0x0C
1294 #define IOPB_RES_ADDR_D 0x0D
1295 #define IOPB_SOFT_OVER_WR 0x0E
1296 #define IOPB_RES_ADDR_F 0x0F
1297 #define IOPB_MEM_CFG 0x10
1298 #define IOPB_RES_ADDR_11 0x11
1299 #define IOPB_GPIO_DATA 0x12
1300 #define IOPB_RES_ADDR_13 0x13
1301 #define IOPB_FLASH_PAGE 0x14
1302 #define IOPB_RES_ADDR_15 0x15
1303 #define IOPB_GPIO_CNTL 0x16
1304 #define IOPB_RES_ADDR_17 0x17
1305 #define IOPB_FLASH_DATA 0x18
1306 #define IOPB_RES_ADDR_19 0x19
1307 #define IOPB_RES_ADDR_1A 0x1A
1308 #define IOPB_RES_ADDR_1B 0x1B
1309 #define IOPB_RES_ADDR_1C 0x1C
1310 #define IOPB_RES_ADDR_1D 0x1D
1311 #define IOPB_RES_ADDR_1E 0x1E
1312 #define IOPB_RES_ADDR_1F 0x1F
1313 #define IOPB_DMA_CFG0 0x20
1314 #define IOPB_DMA_CFG1 0x21
1315 #define IOPB_TICKLE 0x22
1316 #define IOPB_DMA_REG_WR 0x23
1317 #define IOPB_SDMA_STATUS 0x24
1318 #define IOPB_SCSI_BYTE_CNT 0x25
1319 #define IOPB_HOST_BYTE_CNT 0x26
1320 #define IOPB_BYTE_LEFT_TO_XFER 0x27
1321 #define IOPB_BYTE_TO_XFER_0 0x28
1322 #define IOPB_BYTE_TO_XFER_1 0x29
1323 #define IOPB_BYTE_TO_XFER_2 0x2A
1324 #define IOPB_BYTE_TO_XFER_3 0x2B
1325 #define IOPB_ACC_GRP 0x2C
1326 #define IOPB_RES_ADDR_2D 0x2D
1327 #define IOPB_DEV_ID 0x2E
1328 #define IOPB_RES_ADDR_2F 0x2F
1329 #define IOPB_SCSI_DATA 0x30
1330 #define IOPB_RES_ADDR_31 0x31
1331 #define IOPB_RES_ADDR_32 0x32
1332 #define IOPB_SCSI_DATA_HSHK 0x33
1333 #define IOPB_SCSI_CTRL 0x34
1334 #define IOPB_RES_ADDR_35 0x35
1335 #define IOPB_RES_ADDR_36 0x36
1336 #define IOPB_RES_ADDR_37 0x37
1337 #define IOPB_RAM_BIST 0x38
1338 #define IOPB_PLL_TEST 0x39
1339 #define IOPB_PCI_INT_CFG 0x3A
1340 #define IOPB_RES_ADDR_3B 0x3B
1341 #define IOPB_RFIFO_CNT 0x3C
1342 #define IOPB_RES_ADDR_3D 0x3D
1343 #define IOPB_RES_ADDR_3E 0x3E
1344 #define IOPB_RES_ADDR_3F 0x3F
1345
1346 /*
1347 * Word I/O register address from base of 'iop_base'.
1348 */
1349 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
1350 #define IOPW_CTRL_REG 0x02 /* CC */
1351 #define IOPW_RAM_ADDR 0x04 /* LA */
1352 #define IOPW_RAM_DATA 0x06 /* LD */
1353 #define IOPW_RES_ADDR_08 0x08
1354 #define IOPW_RISC_CSR 0x0A /* CSR */
1355 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1356 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1357 #define IOPW_RES_ADDR_10 0x10
1358 #define IOPW_SEL_MASK 0x12 /* SM */
1359 #define IOPW_RES_ADDR_14 0x14
1360 #define IOPW_FLASH_ADDR 0x16 /* FA */
1361 #define IOPW_RES_ADDR_18 0x18
1362 #define IOPW_EE_CMD 0x1A /* EC */
1363 #define IOPW_EE_DATA 0x1C /* ED */
1364 #define IOPW_SFIFO_CNT 0x1E /* SFC */
1365 #define IOPW_RES_ADDR_20 0x20
1366 #define IOPW_Q_BASE 0x22 /* QB */
1367 #define IOPW_QP 0x24 /* QP */
1368 #define IOPW_IX 0x26 /* IX */
1369 #define IOPW_SP 0x28 /* SP */
1370 #define IOPW_PC 0x2A /* PC */
1371 #define IOPW_RES_ADDR_2C 0x2C
1372 #define IOPW_RES_ADDR_2E 0x2E
1373 #define IOPW_SCSI_DATA 0x30 /* SD */
1374 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1375 #define IOPW_SCSI_CTRL 0x34 /* SC */
1376 #define IOPW_HSHK_CFG 0x36 /* HCFG */
1377 #define IOPW_SXFR_STATUS 0x36 /* SXS */
1378 #define IOPW_SXFR_CNTL 0x38 /* SXL */
1379 #define IOPW_SXFR_CNTH 0x3A /* SXH */
1380 #define IOPW_RES_ADDR_3C 0x3C
1381 #define IOPW_RFIFO_DATA 0x3E /* RFD */
1382
1383 /*
1384 * Doubleword I/O register address from base of 'iop_base'.
1385 */
1386 #define IOPDW_RES_ADDR_0 0x00
1387 #define IOPDW_RAM_DATA 0x04
1388 #define IOPDW_RES_ADDR_8 0x08
1389 #define IOPDW_RES_ADDR_C 0x0C
1390 #define IOPDW_RES_ADDR_10 0x10
1391 #define IOPDW_COMMA 0x14
1392 #define IOPDW_COMMB 0x18
1393 #define IOPDW_RES_ADDR_1C 0x1C
1394 #define IOPDW_SDMA_ADDR0 0x20
1395 #define IOPDW_SDMA_ADDR1 0x24
1396 #define IOPDW_SDMA_COUNT 0x28
1397 #define IOPDW_SDMA_ERROR 0x2C
1398 #define IOPDW_RDMA_ADDR0 0x30
1399 #define IOPDW_RDMA_ADDR1 0x34
1400 #define IOPDW_RDMA_COUNT 0x38
1401 #define IOPDW_RDMA_ERROR 0x3C
1402
1403 #define ADV_CHIP_ID_BYTE 0x25
1404 #define ADV_CHIP_ID_WORD 0x04C1
1405
1406 #define ADV_INTR_ENABLE_HOST_INTR 0x01
1407 #define ADV_INTR_ENABLE_SEL_INTR 0x02
1408 #define ADV_INTR_ENABLE_DPR_INTR 0x04
1409 #define ADV_INTR_ENABLE_RTA_INTR 0x08
1410 #define ADV_INTR_ENABLE_RMA_INTR 0x10
1411 #define ADV_INTR_ENABLE_RST_INTR 0x20
1412 #define ADV_INTR_ENABLE_DPE_INTR 0x40
1413 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1414
1415 #define ADV_INTR_STATUS_INTRA 0x01
1416 #define ADV_INTR_STATUS_INTRB 0x02
1417 #define ADV_INTR_STATUS_INTRC 0x04
1418
1419 #define ADV_RISC_CSR_STOP (0x0000)
1420 #define ADV_RISC_TEST_COND (0x2000)
1421 #define ADV_RISC_CSR_RUN (0x4000)
1422 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1423
1424 #define ADV_CTRL_REG_HOST_INTR 0x0100
1425 #define ADV_CTRL_REG_SEL_INTR 0x0200
1426 #define ADV_CTRL_REG_DPR_INTR 0x0400
1427 #define ADV_CTRL_REG_RTA_INTR 0x0800
1428 #define ADV_CTRL_REG_RMA_INTR 0x1000
1429 #define ADV_CTRL_REG_RES_BIT14 0x2000
1430 #define ADV_CTRL_REG_DPE_INTR 0x4000
1431 #define ADV_CTRL_REG_POWER_DONE 0x8000
1432 #define ADV_CTRL_REG_ANY_INTR 0xFF00
1433
1434 #define ADV_CTRL_REG_CMD_RESET 0x00C6
1435 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1436 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1437 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1438 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1439
1440 #define ADV_TICKLE_NOP 0x00
1441 #define ADV_TICKLE_A 0x01
1442 #define ADV_TICKLE_B 0x02
1443 #define ADV_TICKLE_C 0x03
1444
1445 #define AdvIsIntPending(port) \
1446 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1447
1448 /*
1449 * SCSI_CFG0 Register bit definitions
1450 */
1451 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1452 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1453 #define EVEN_PARITY 0x1000 /* Select Even Parity */
1454 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1455 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1456 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1457 #define SCAM_EN 0x0080 /* Enable SCAM selection */
1458 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1459 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1460 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1461 #define OUR_ID 0x000F /* SCSI ID */
1462
1463 /*
1464 * SCSI_CFG1 Register bit definitions
1465 */
1466 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1467 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1468 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1469 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
1470 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1471 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1472 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1473 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1474 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1475 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1476 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1477 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1478 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1479 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1480 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1481
1482 /*
1483 * Addendum for ASC-38C0800 Chip
1484 *
1485 * The ASC-38C1600 Chip uses the same definitions except that the
1486 * bus mode override bits [12:10] have been moved to byte register
1487 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1488 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1489 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1490 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1491 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1492 */
1493 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1494 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1495 #define HVD 0x1000 /* HVD Device Detect */
1496 #define LVD 0x0800 /* LVD Device Detect */
1497 #define SE 0x0400 /* SE Device Detect */
1498 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
1499 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1500 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1501 #define TERM_SE 0x0030 /* SE Termination Bits */
1502 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1503 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1504 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1505 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1506 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1507 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1508 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1509 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1510
1511 #define CABLE_ILLEGAL_A 0x7
1512 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1513
1514 #define CABLE_ILLEGAL_B 0xB
1515 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1516
1517 /*
1518 * MEM_CFG Register bit definitions
1519 */
1520 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1521 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1522 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1523 #define RAM_SZ_2KB 0x00 /* 2 KB */
1524 #define RAM_SZ_4KB 0x04 /* 4 KB */
1525 #define RAM_SZ_8KB 0x08 /* 8 KB */
1526 #define RAM_SZ_16KB 0x0C /* 16 KB */
1527 #define RAM_SZ_32KB 0x10 /* 32 KB */
1528 #define RAM_SZ_64KB 0x14 /* 64 KB */
1529
1530 /*
1531 * DMA_CFG0 Register bit definitions
1532 *
1533 * This register is only accessible to the host.
1534 */
1535 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1536 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1537 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
1538 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
1539 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
1540 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
1541 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1542 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
1543 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
1544 #define START_CTL 0x0C /* DMA start conditions */
1545 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
1546 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1547 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1548 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1549 #define READ_CMD 0x03 /* Memory Read Method */
1550 #define READ_CMD_MR 0x00 /* Memory Read */
1551 #define READ_CMD_MRL 0x02 /* Memory Read Long */
1552 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1553
1554 /*
1555 * ASC-38C0800 RAM BIST Register bit definitions
1556 */
1557 #define RAM_TEST_MODE 0x80
1558 #define PRE_TEST_MODE 0x40
1559 #define NORMAL_MODE 0x00
1560 #define RAM_TEST_DONE 0x10
1561 #define RAM_TEST_STATUS 0x0F
1562 #define RAM_TEST_HOST_ERROR 0x08
1563 #define RAM_TEST_INTRAM_ERROR 0x04
1564 #define RAM_TEST_RISC_ERROR 0x02
1565 #define RAM_TEST_SCSI_ERROR 0x01
1566 #define RAM_TEST_SUCCESS 0x00
1567 #define PRE_TEST_VALUE 0x05
1568 #define NORMAL_VALUE 0x00
1569
1570 /*
1571 * ASC38C1600 Definitions
1572 *
1573 * IOPB_PCI_INT_CFG Bit Field Definitions
1574 */
1575
1576 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1577
1578 /*
1579 * Bit 1 can be set to change the interrupt for the Function to operate in
1580 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1581 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1582 * mode, otherwise the operating mode is undefined.
1583 */
1584 #define TOTEMPOLE 0x02
1585
1586 /*
1587 * Bit 0 can be used to change the Int Pin for the Function. The value is
1588 * 0 by default for both Functions with Function 0 using INT A and Function
1589 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1590 * INT A is used.
1591 *
1592 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1593 * value specified in the PCI Configuration Space.
1594 */
1595 #define INTAB 0x01
1596
1597 /*
1598 * Adv Library Status Definitions
1599 */
1600 #define ADV_TRUE 1
1601 #define ADV_FALSE 0
1602 #define ADV_SUCCESS 1
1603 #define ADV_BUSY 0
1604 #define ADV_ERROR (-1)
1605
1606 /*
1607 * ADV_DVC_VAR 'warn_code' values
1608 */
1609 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1610 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1611 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
1612 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1613
1614 #define ADV_MAX_TID 15 /* max. target identifier */
1615 #define ADV_MAX_LUN 7 /* max. logical unit number */
1616
1617 /*
1618 * Fixed locations of microcode operating variables.
1619 */
1620 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1621 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1622 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1623 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1624 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1625 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1626 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1627 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1628 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1629 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1630 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1631 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1632 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1633 #define ASC_MC_CHIP_TYPE 0x009A
1634 #define ASC_MC_INTRB_CODE 0x009B
1635 #define ASC_MC_WDTR_ABLE 0x009C
1636 #define ASC_MC_SDTR_ABLE 0x009E
1637 #define ASC_MC_TAGQNG_ABLE 0x00A0
1638 #define ASC_MC_DISC_ENABLE 0x00A2
1639 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
1640 #define ASC_MC_IDLE_CMD 0x00A6
1641 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1642 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1643 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1644 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1645 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1646 #define ASC_MC_SDTR_DONE 0x00B6
1647 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1648 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1649 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
1650 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1651 #define ASC_MC_WDTR_DONE 0x0124
1652 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1653 #define ASC_MC_ICQ 0x0160
1654 #define ASC_MC_IRQ 0x0164
1655 #define ASC_MC_PPR_ABLE 0x017A
1656
1657 /*
1658 * BIOS LRAM variable absolute offsets.
1659 */
1660 #define BIOS_CODESEG 0x54
1661 #define BIOS_CODELEN 0x56
1662 #define BIOS_SIGNATURE 0x58
1663 #define BIOS_VERSION 0x5A
1664
1665 /*
1666 * Microcode Control Flags
1667 *
1668 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1669 * and handled by the microcode.
1670 */
1671 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1672 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1673
1674 /*
1675 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1676 */
1677 #define HSHK_CFG_WIDE_XFR 0x8000
1678 #define HSHK_CFG_RATE 0x0F00
1679 #define HSHK_CFG_OFFSET 0x001F
1680
1681 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1682 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1683 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1684 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1685
1686 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1687 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1688 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1689 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1690 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1691
1692 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1693 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1694 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1695 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1696 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1697 /*
1698 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1699 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1700 */
1701 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1702 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1703
1704 /*
1705 * All fields here are accessed by the board microcode and need to be
1706 * little-endian.
1707 */
1708 typedef struct adv_carr_t {
1709 __le32 carr_va; /* Carrier Virtual Address */
1710 __le32 carr_pa; /* Carrier Physical Address */
1711 __le32 areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1712 /*
1713 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1714 *
1715 * next_vpa [3:1] Reserved Bits
1716 * next_vpa [0] Done Flag set in Response Queue.
1717 */
1718 __le32 next_vpa;
1719 } ADV_CARR_T;
1720
1721 /*
1722 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1723 */
1724 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
1725
1726 #define ASC_RQ_DONE 0x00000001
1727 #define ASC_RQ_GOOD 0x00000002
1728 #define ASC_CQ_STOPPER 0x00000000
1729
1730 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1731
1732 /*
1733 * Each carrier is 64 bytes, and we need three additional
1734 * carrier for icq, irq, and the termination carrier.
1735 */
1736 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 3)
1737
1738 #define ADV_CARRIER_BUFSIZE \
1739 (ADV_CARRIER_COUNT * sizeof(ADV_CARR_T))
1740
1741 /*
1742 * ASC_SCSI_REQ_Q 'a_flag' definitions
1743 *
1744 * The Adv Library should limit use to the lower nibble (4 bits) of
1745 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1746 */
1747 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
1748 #define ADV_SCSIQ_DONE 0x02 /* request done */
1749 #define ADV_DONT_RETRY 0x08 /* don't do retry */
1750
1751 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1752 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1753 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1754
1755 /*
1756 * Adapter temporary configuration structure
1757 *
1758 * This structure can be discarded after initialization. Don't add
1759 * fields here needed after initialization.
1760 *
1761 * Field naming convention:
1762 *
1763 * *_enable indicates the field enables or disables a feature. The
1764 * value of the field is never reset.
1765 */
1766 typedef struct adv_dvc_cfg {
1767 ushort disc_enable; /* enable disconnection */
1768 uchar chip_version; /* chip version */
1769 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1770 ushort control_flag; /* Microcode Control Flag */
1771 ushort mcode_date; /* Microcode date */
1772 ushort mcode_version; /* Microcode version */
1773 ushort serial1; /* EEPROM serial number word 1 */
1774 ushort serial2; /* EEPROM serial number word 2 */
1775 ushort serial3; /* EEPROM serial number word 3 */
1776 } ADV_DVC_CFG;
1777
1778 struct adv_dvc_var;
1779 struct adv_scsi_req_q;
1780
1781 typedef struct adv_sg_block {
1782 uchar reserved1;
1783 uchar reserved2;
1784 uchar reserved3;
1785 uchar sg_cnt; /* Valid entries in block. */
1786 __le32 sg_ptr; /* Pointer to next sg block. */
1787 struct {
1788 __le32 sg_addr; /* SG element address. */
1789 __le32 sg_count; /* SG element count. */
1790 } sg_list[NO_OF_SG_PER_BLOCK];
1791 } ADV_SG_BLOCK;
1792
1793 /*
1794 * ADV_SCSI_REQ_Q - microcode request structure
1795 *
1796 * All fields in this structure up to byte 60 are used by the microcode.
1797 * The microcode makes assumptions about the size and ordering of fields
1798 * in this structure. Do not change the structure definition here without
1799 * coordinating the change with the microcode.
1800 *
1801 * All fields accessed by microcode must be maintained in little_endian
1802 * order.
1803 */
1804 typedef struct adv_scsi_req_q {
1805 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1806 uchar target_cmd;
1807 uchar target_id; /* Device target identifier. */
1808 uchar target_lun; /* Device target logical unit number. */
1809 __le32 data_addr; /* Data buffer physical address. */
1810 __le32 data_cnt; /* Data count. Ucode sets to residual. */
1811 __le32 sense_addr;
1812 __le32 carr_pa;
1813 uchar mflag;
1814 uchar sense_len;
1815 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1816 uchar scsi_cntl;
1817 uchar done_status; /* Completion status. */
1818 uchar scsi_status; /* SCSI status byte. */
1819 uchar host_status; /* Ucode host status. */
1820 uchar sg_working_ix;
1821 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
1822 __le32 sg_real_addr; /* SG list physical address. */
1823 __le32 scsiq_rptr;
1824 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
1825 __le32 scsiq_ptr;
1826 __le32 carr_va;
1827 /*
1828 * End of microcode structure - 60 bytes. The rest of the structure
1829 * is used by the Adv Library and ignored by the microcode.
1830 */
1831 u32 srb_tag;
1832 uchar a_flag;
1833 uchar pad[3]; /* Pad out to a word boundary. */
1834 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1835 } ADV_SCSI_REQ_Q;
1836
1837 /*
1838 * The following two structures are used to process Wide Board requests.
1839 *
1840 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1841 * and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the
1842 * SCSI request tag. The adv_req_t structure 'cmndp' field in turn points
1843 * to the Mid-Level SCSI request structure.
1844 *
1845 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1846 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1847 * up to 255 scatter-gather elements may be used per request or
1848 * ADV_SCSI_REQ_Q.
1849 *
1850 * Both structures must be 32 byte aligned.
1851 */
1852 typedef struct adv_sgblk {
1853 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
1854 dma_addr_t sg_addr; /* Physical address */
1855 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
1856 } adv_sgblk_t;
1857
1858 typedef struct adv_req {
1859 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
1860 uchar align[24]; /* Request structure padding. */
1861 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
1862 dma_addr_t req_addr;
1863 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
1864 } adv_req_t __aligned(32);
1865
1866 /*
1867 * Adapter operation variable structure.
1868 *
1869 * One structure is required per host adapter.
1870 *
1871 * Field naming convention:
1872 *
1873 * *_able indicates both whether a feature should be enabled or disabled
1874 * and whether a device isi capable of the feature. At initialization
1875 * this field may be set, but later if a device is found to be incapable
1876 * of the feature, the field is cleared.
1877 */
1878 typedef struct adv_dvc_var {
1879 AdvPortAddr iop_base; /* I/O port address */
1880 ushort err_code; /* fatal error code */
1881 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1882 ushort wdtr_able; /* try WDTR for a device */
1883 ushort sdtr_able; /* try SDTR for a device */
1884 ushort ultra_able; /* try SDTR Ultra speed for a device */
1885 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1886 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1887 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1888 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1889 ushort tagqng_able; /* try tagged queuing with a device */
1890 ushort ppr_able; /* PPR message capable per TID bitmask. */
1891 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1892 ushort start_motor; /* start motor command allowed */
1893 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1894 uchar chip_no; /* should be assigned by caller */
1895 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1896 ushort no_scam; /* scam_tolerant of EEPROM */
1897 struct asc_board *drv_ptr; /* driver pointer to private structure */
1898 uchar chip_scsi_id; /* chip SCSI target ID */
1899 uchar chip_type;
1900 uchar bist_err_code;
1901 ADV_CARR_T *carrier;
1902 ADV_CARR_T *carr_freelist; /* Carrier free list. */
1903 dma_addr_t carrier_addr;
1904 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1905 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1906 ushort carr_pending_cnt; /* Count of pending carriers. */
1907 /*
1908 * Note: The following fields will not be used after initialization. The
1909 * driver may discard the buffer after initialization is done.
1910 */
1911 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1912 } ADV_DVC_VAR;
1913
1914 /*
1915 * Microcode idle loop commands
1916 */
1917 #define IDLE_CMD_COMPLETED 0
1918 #define IDLE_CMD_STOP_CHIP 0x0001
1919 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
1920 #define IDLE_CMD_SEND_INT 0x0004
1921 #define IDLE_CMD_ABORT 0x0008
1922 #define IDLE_CMD_DEVICE_RESET 0x0010
1923 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
1924 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
1925 #define IDLE_CMD_SCSIREQ 0x0080
1926
1927 #define IDLE_CMD_STATUS_SUCCESS 0x0001
1928 #define IDLE_CMD_STATUS_FAILURE 0x0002
1929
1930 /*
1931 * AdvSendIdleCmd() flag definitions.
1932 */
1933 #define ADV_NOWAIT 0x01
1934
1935 /*
1936 * Wait loop time out values.
1937 */
1938 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
1939 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
1940 #define SCSI_MAX_RETRY 10 /* retry count */
1941
1942 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
1943 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
1944 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
1945 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
1946
1947 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
1948
1949 /* Read byte from a register. */
1950 #define AdvReadByteRegister(iop_base, reg_off) \
1951 (ADV_MEM_READB((iop_base) + (reg_off)))
1952
1953 /* Write byte to a register. */
1954 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
1955 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1956
1957 /* Read word (2 bytes) from a register. */
1958 #define AdvReadWordRegister(iop_base, reg_off) \
1959 (ADV_MEM_READW((iop_base) + (reg_off)))
1960
1961 /* Write word (2 bytes) to a register. */
1962 #define AdvWriteWordRegister(iop_base, reg_off, word) \
1963 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
1964
1965 /* Write dword (4 bytes) to a register. */
1966 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
1967 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
1968
1969 /* Read byte from LRAM. */
1970 #define AdvReadByteLram(iop_base, addr, byte) \
1971 do { \
1972 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1973 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
1974 } while (0)
1975
1976 /* Write byte to LRAM. */
1977 #define AdvWriteByteLram(iop_base, addr, byte) \
1978 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1979 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
1980
1981 /* Read word (2 bytes) from LRAM. */
1982 #define AdvReadWordLram(iop_base, addr, word) \
1983 do { \
1984 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1985 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
1986 } while (0)
1987
1988 /* Write word (2 bytes) to LRAM. */
1989 #define AdvWriteWordLram(iop_base, addr, word) \
1990 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1991 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
1992
1993 /* Write little-endian double word (4 bytes) to LRAM */
1994 /* Because of unspecified C language ordering don't use auto-increment. */
1995 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
1996 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1997 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
1998 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
1999 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2000 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2001 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2002
2003 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2004 #define AdvReadWordAutoIncLram(iop_base) \
2005 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2006
2007 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2008 #define AdvWriteWordAutoIncLram(iop_base, word) \
2009 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2010
2011 /*
2012 * Define macro to check for Condor signature.
2013 *
2014 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2015 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2016 */
2017 #define AdvFindSignature(iop_base) \
2018 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2019 ADV_CHIP_ID_BYTE) && \
2020 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2021 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2022
2023 /*
2024 * Define macro to Return the version number of the chip at 'iop_base'.
2025 *
2026 * The second parameter 'bus_type' is currently unused.
2027 */
2028 #define AdvGetChipVersion(iop_base, bus_type) \
2029 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2030
2031 /*
2032 * Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must
2033 * match the ASC_SCSI_REQ_Q 'srb_tag' field.
2034 *
2035 * If the request has not yet been sent to the device it will simply be
2036 * aborted from RISC memory. If the request is disconnected it will be
2037 * aborted on reselection by sending an Abort Message to the target ID.
2038 *
2039 * Return value:
2040 * ADV_TRUE(1) - Queue was successfully aborted.
2041 * ADV_FALSE(0) - Queue was not found on the active queue list.
2042 */
2043 #define AdvAbortQueue(asc_dvc, srb_tag) \
2044 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2045 (ADV_DCNT) (srb_tag))
2046
2047 /*
2048 * Send a Bus Device Reset Message to the specified target ID.
2049 *
2050 * All outstanding commands will be purged if sending the
2051 * Bus Device Reset Message is successful.
2052 *
2053 * Return Value:
2054 * ADV_TRUE(1) - All requests on the target are purged.
2055 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2056 * are not purged.
2057 */
2058 #define AdvResetDevice(asc_dvc, target_id) \
2059 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2060 (ADV_DCNT) (target_id))
2061
2062 /*
2063 * SCSI Wide Type definition.
2064 */
2065 #define ADV_SCSI_BIT_ID_TYPE ushort
2066
2067 /*
2068 * AdvInitScsiTarget() 'cntl_flag' options.
2069 */
2070 #define ADV_SCAN_LUN 0x01
2071 #define ADV_CAPINFO_NOLUN 0x02
2072
2073 /*
2074 * Convert target id to target id bit mask.
2075 */
2076 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2077
2078 /*
2079 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2080 */
2081
2082 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
2083 #define QD_NO_ERROR 0x01
2084 #define QD_ABORTED_BY_HOST 0x02
2085 #define QD_WITH_ERROR 0x04
2086
2087 #define QHSTA_NO_ERROR 0x00
2088 #define QHSTA_M_SEL_TIMEOUT 0x11
2089 #define QHSTA_M_DATA_OVER_RUN 0x12
2090 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2091 #define QHSTA_M_QUEUE_ABORTED 0x15
2092 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2093 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2094 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2095 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2096 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2097 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2098 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
2099 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2100 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2101 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2102 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2103 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2104 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2105 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2106 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2107 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
2108 #define QHSTA_M_WTM_TIMEOUT 0x41
2109 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2110 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2111 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2112 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2113 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2114 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
2115
2116 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2117 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2118
2119 /*
2120 * Total contiguous memory needed for driver SG blocks.
2121 *
2122 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2123 * number of scatter-gather elements the driver supports in a
2124 * single request.
2125 */
2126
2127 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2128 (sizeof(ADV_SG_BLOCK) * \
2129 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2130
2131 /* struct asc_board flags */
2132 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
2133
2134 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2135
2136 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
2137
2138 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
2139
2140 /* Asc Library return codes */
2141 #define ASC_TRUE 1
2142 #define ASC_FALSE 0
2143 #define ASC_NOERROR 1
2144 #define ASC_BUSY 0
2145 #define ASC_ERROR (-1)
2146
2147 /* struct scsi_cmnd function return codes */
2148 #define STATUS_BYTE(byte) (byte)
2149 #define MSG_BYTE(byte) ((byte) << 8)
2150 #define HOST_BYTE(byte) ((byte) << 16)
2151 #define DRIVER_BYTE(byte) ((byte) << 24)
2152
2153 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2154 #ifndef ADVANSYS_STATS
2155 #define ASC_STATS_ADD(shost, counter, count)
2156 #else /* ADVANSYS_STATS */
2157 #define ASC_STATS_ADD(shost, counter, count) \
2158 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2159 #endif /* ADVANSYS_STATS */
2160
2161 /* If the result wraps when calculating tenths, return 0. */
2162 #define ASC_TENTHS(num, den) \
2163 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2164 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2165
2166 /*
2167 * Display a message to the console.
2168 */
2169 #define ASC_PRINT(s) \
2170 { \
2171 printk("advansys: "); \
2172 printk(s); \
2173 }
2174
2175 #define ASC_PRINT1(s, a1) \
2176 { \
2177 printk("advansys: "); \
2178 printk((s), (a1)); \
2179 }
2180
2181 #define ASC_PRINT2(s, a1, a2) \
2182 { \
2183 printk("advansys: "); \
2184 printk((s), (a1), (a2)); \
2185 }
2186
2187 #define ASC_PRINT3(s, a1, a2, a3) \
2188 { \
2189 printk("advansys: "); \
2190 printk((s), (a1), (a2), (a3)); \
2191 }
2192
2193 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2194 { \
2195 printk("advansys: "); \
2196 printk((s), (a1), (a2), (a3), (a4)); \
2197 }
2198
2199 #ifndef ADVANSYS_DEBUG
2200
2201 #define ASC_DBG(lvl, s...)
2202 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2203 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2204 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2205 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2206 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2207 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2208 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2209 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2210 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2211
2212 #else /* ADVANSYS_DEBUG */
2213
2214 /*
2215 * Debugging Message Levels:
2216 * 0: Errors Only
2217 * 1: High-Level Tracing
2218 * 2-N: Verbose Tracing
2219 */
2220
2221 #define ASC_DBG(lvl, format, arg...) { \
2222 if (asc_dbglvl >= (lvl)) \
2223 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
2224 __func__ , ## arg); \
2225 }
2226
2227 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2228 { \
2229 if (asc_dbglvl >= (lvl)) { \
2230 asc_prt_scsi_host(s); \
2231 } \
2232 }
2233
2234 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2235 { \
2236 if (asc_dbglvl >= (lvl)) { \
2237 asc_prt_asc_scsi_q(scsiqp); \
2238 } \
2239 }
2240
2241 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2242 { \
2243 if (asc_dbglvl >= (lvl)) { \
2244 asc_prt_asc_qdone_info(qdone); \
2245 } \
2246 }
2247
2248 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2249 { \
2250 if (asc_dbglvl >= (lvl)) { \
2251 asc_prt_adv_scsi_req_q(scsiqp); \
2252 } \
2253 }
2254
2255 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2256 { \
2257 if (asc_dbglvl >= (lvl)) { \
2258 asc_prt_hex((name), (start), (length)); \
2259 } \
2260 }
2261
2262 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2263 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2264
2265 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2266 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2267
2268 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2269 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2270 #endif /* ADVANSYS_DEBUG */
2271
2272 #ifdef ADVANSYS_STATS
2273
2274 /* Per board statistics structure */
2275 struct asc_stats {
2276 /* Driver Entrypoint Statistics */
2277 unsigned int queuecommand; /* # calls to advansys_queuecommand() */
2278 unsigned int reset; /* # calls to advansys_eh_bus_reset() */
2279 unsigned int biosparam; /* # calls to advansys_biosparam() */
2280 unsigned int interrupt; /* # advansys_interrupt() calls */
2281 unsigned int callback; /* # calls to asc/adv_isr_callback() */
2282 unsigned int done; /* # calls to request's scsi_done function */
2283 unsigned int build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2284 unsigned int adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2285 unsigned int adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2286 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2287 unsigned int exe_noerror; /* # ASC_NOERROR returns. */
2288 unsigned int exe_busy; /* # ASC_BUSY returns. */
2289 unsigned int exe_error; /* # ASC_ERROR returns. */
2290 unsigned int exe_unknown; /* # unknown returns. */
2291 /* Data Transfer Statistics */
2292 unsigned int xfer_cnt; /* # I/O requests received */
2293 unsigned int xfer_elem; /* # scatter-gather elements */
2294 unsigned int xfer_sect; /* # 512-byte blocks */
2295 };
2296 #endif /* ADVANSYS_STATS */
2297
2298 /*
2299 * Structure allocated for each board.
2300 *
2301 * This structure is allocated by scsi_host_alloc() at the end
2302 * of the 'Scsi_Host' structure starting at the 'hostdata'
2303 * field. It is guaranteed to be allocated from DMA-able memory.
2304 */
2305 struct asc_board {
2306 struct device *dev;
2307 struct Scsi_Host *shost;
2308 uint flags; /* Board flags */
2309 unsigned int irq;
2310 union {
2311 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2312 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2313 } dvc_var;
2314 union {
2315 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2316 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2317 } dvc_cfg;
2318 ushort asc_n_io_port; /* Number I/O ports. */
2319 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
2320 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2321 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2322 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2323 union {
2324 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2325 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2326 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2327 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2328 } eep_config;
2329 /* /proc/scsi/advansys/[0...] */
2330 #ifdef ADVANSYS_STATS
2331 struct asc_stats asc_stats; /* Board statistics */
2332 #endif /* ADVANSYS_STATS */
2333 /*
2334 * The following fields are used only for Narrow Boards.
2335 */
2336 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2337 /*
2338 * The following fields are used only for Wide Boards.
2339 */
2340 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2341 ushort ioport; /* I/O Port address. */
2342 adv_req_t *adv_reqp; /* Request structures. */
2343 dma_addr_t adv_reqp_addr;
2344 size_t adv_reqp_size;
2345 struct dma_pool *adv_sgblk_pool; /* Scatter-gather structures. */
2346 ushort bios_signature; /* BIOS Signature. */
2347 ushort bios_version; /* BIOS Version. */
2348 ushort bios_codeseg; /* BIOS Code Segment. */
2349 ushort bios_codelen; /* BIOS Code Segment Length. */
2350 };
2351
2352 #define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2353 dvc_var.asc_dvc_var)
2354 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2355 dvc_var.adv_dvc_var)
2356 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2357
2358 #ifdef ADVANSYS_DEBUG
2359 static int asc_dbglvl = 3;
2360
2361 /*
2362 * asc_prt_asc_dvc_var()
2363 */
2364 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2365 {
2366 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2367
2368 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2369 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2370
2371 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2372 (unsigned)h->init_sdtr);
2373
2374 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2375 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2376 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2377 (unsigned)h->chip_no);
2378
2379 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2380 "%u,\n", (unsigned)h->queue_full_or_busy,
2381 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2382
2383 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2384 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2385 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2386 (unsigned)h->in_critical_cnt);
2387
2388 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2389 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2390 (unsigned)h->init_state, (unsigned)h->no_scam,
2391 (unsigned)h->pci_fix_asyn_xfer);
2392
2393 printk(" cfg 0x%lx\n", (ulong)h->cfg);
2394 }
2395
2396 /*
2397 * asc_prt_asc_dvc_cfg()
2398 */
2399 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2400 {
2401 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2402
2403 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2404 h->can_tagged_qng, h->cmd_qng_enabled);
2405 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2406 h->disc_enable, h->sdtr_enable);
2407
2408 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2409 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2410 h->isa_dma_channel, h->chip_version);
2411
2412 printk(" mcode_date 0x%x, mcode_version %d\n",
2413 h->mcode_date, h->mcode_version);
2414 }
2415
2416 /*
2417 * asc_prt_adv_dvc_var()
2418 *
2419 * Display an ADV_DVC_VAR structure.
2420 */
2421 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2422 {
2423 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2424
2425 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2426 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2427
2428 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
2429 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2430
2431 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
2432 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2433
2434 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%p\n",
2435 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2436 h->carr_freelist);
2437
2438 printk(" icq_sp 0x%p, irq_sp 0x%p\n", h->icq_sp, h->irq_sp);
2439
2440 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2441 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2442
2443 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2444 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2445 }
2446
2447 /*
2448 * asc_prt_adv_dvc_cfg()
2449 *
2450 * Display an ADV_DVC_CFG structure.
2451 */
2452 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2453 {
2454 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2455
2456 printk(" disc_enable 0x%x, termination 0x%x\n",
2457 h->disc_enable, h->termination);
2458
2459 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2460 h->chip_version, h->mcode_date);
2461
2462 printk(" mcode_version 0x%x, control_flag 0x%x\n",
2463 h->mcode_version, h->control_flag);
2464 }
2465
2466 /*
2467 * asc_prt_scsi_host()
2468 */
2469 static void asc_prt_scsi_host(struct Scsi_Host *s)
2470 {
2471 struct asc_board *boardp = shost_priv(s);
2472
2473 printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
2474 printk(" host_busy %u, host_no %d,\n",
2475 atomic_read(&s->host_busy), s->host_no);
2476
2477 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2478 (ulong)s->base, (ulong)s->io_port, boardp->irq);
2479
2480 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2481 s->dma_channel, s->this_id, s->can_queue);
2482
2483 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2484 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2485
2486 if (ASC_NARROW_BOARD(boardp)) {
2487 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2488 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2489 } else {
2490 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2491 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2492 }
2493 }
2494
2495 /*
2496 * asc_prt_hex()
2497 *
2498 * Print hexadecimal output in 4 byte groupings 32 bytes
2499 * or 8 double-words per line.
2500 */
2501 static void asc_prt_hex(char *f, uchar *s, int l)
2502 {
2503 int i;
2504 int j;
2505 int k;
2506 int m;
2507
2508 printk("%s: (%d bytes)\n", f, l);
2509
2510 for (i = 0; i < l; i += 32) {
2511
2512 /* Display a maximum of 8 double-words per line. */
2513 if ((k = (l - i) / 4) >= 8) {
2514 k = 8;
2515 m = 0;
2516 } else {
2517 m = (l - i) % 4;
2518 }
2519
2520 for (j = 0; j < k; j++) {
2521 printk(" %2.2X%2.2X%2.2X%2.2X",
2522 (unsigned)s[i + (j * 4)],
2523 (unsigned)s[i + (j * 4) + 1],
2524 (unsigned)s[i + (j * 4) + 2],
2525 (unsigned)s[i + (j * 4) + 3]);
2526 }
2527
2528 switch (m) {
2529 case 0:
2530 default:
2531 break;
2532 case 1:
2533 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2534 break;
2535 case 2:
2536 printk(" %2.2X%2.2X",
2537 (unsigned)s[i + (j * 4)],
2538 (unsigned)s[i + (j * 4) + 1]);
2539 break;
2540 case 3:
2541 printk(" %2.2X%2.2X%2.2X",
2542 (unsigned)s[i + (j * 4) + 1],
2543 (unsigned)s[i + (j * 4) + 2],
2544 (unsigned)s[i + (j * 4) + 3]);
2545 break;
2546 }
2547
2548 printk("\n");
2549 }
2550 }
2551
2552 /*
2553 * asc_prt_asc_scsi_q()
2554 */
2555 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2556 {
2557 ASC_SG_HEAD *sgp;
2558 int i;
2559
2560 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2561
2562 printk
2563 (" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n",
2564 q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag,
2565 q->q2.tag_code);
2566
2567 printk
2568 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2569 (ulong)le32_to_cpu(q->q1.data_addr),
2570 (ulong)le32_to_cpu(q->q1.data_cnt),
2571 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2572
2573 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2574 (ulong)q->cdbptr, q->q2.cdb_len,
2575 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2576
2577 if (q->sg_head) {
2578 sgp = q->sg_head;
2579 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2580 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2581 sgp->queue_cnt);
2582 for (i = 0; i < sgp->entry_cnt; i++) {
2583 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2584 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2585 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2586 }
2587
2588 }
2589 }
2590
2591 /*
2592 * asc_prt_asc_qdone_info()
2593 */
2594 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2595 {
2596 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2597 printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n",
2598 q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len,
2599 q->d2.tag_code);
2600 printk
2601 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2602 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2603 }
2604
2605 /*
2606 * asc_prt_adv_sgblock()
2607 *
2608 * Display an ADV_SG_BLOCK structure.
2609 */
2610 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2611 {
2612 int i;
2613
2614 printk(" ADV_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2615 (ulong)b, sgblockno);
2616 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
2617 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2618 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2619 if (b->sg_ptr != 0)
2620 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2621 for (i = 0; i < b->sg_cnt; i++) {
2622 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2623 i, (ulong)b->sg_list[i].sg_addr,
2624 (ulong)b->sg_list[i].sg_count);
2625 }
2626 }
2627
2628 /*
2629 * asc_prt_adv_scsi_req_q()
2630 *
2631 * Display an ADV_SCSI_REQ_Q structure.
2632 */
2633 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2634 {
2635 int sg_blk_cnt;
2636 struct adv_sg_block *sg_ptr;
2637 adv_sgblk_t *sgblkp;
2638
2639 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2640
2641 printk(" target_id %u, target_lun %u, srb_tag 0x%x, a_flag 0x%x\n",
2642 q->target_id, q->target_lun, q->srb_tag, q->a_flag);
2643
2644 printk(" cntl 0x%x, data_addr 0x%lx\n",
2645 q->cntl, (ulong)le32_to_cpu(q->data_addr));
2646
2647 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2648 (ulong)le32_to_cpu(q->data_cnt),
2649 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2650
2651 printk
2652 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2653 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2654
2655 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2656 q->sg_working_ix, q->target_cmd);
2657
2658 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2659 (ulong)le32_to_cpu(q->scsiq_rptr),
2660 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2661
2662 /* Display the request's ADV_SG_BLOCK structures. */
2663 if (q->sg_list_ptr != NULL) {
2664 sgblkp = container_of(q->sg_list_ptr, adv_sgblk_t, sg_block);
2665 sg_blk_cnt = 0;
2666 while (sgblkp) {
2667 sg_ptr = &sgblkp->sg_block;
2668 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2669 if (sg_ptr->sg_ptr == 0) {
2670 break;
2671 }
2672 sgblkp = sgblkp->next_sgblkp;
2673 sg_blk_cnt++;
2674 }
2675 }
2676 }
2677 #endif /* ADVANSYS_DEBUG */
2678
2679 /*
2680 * advansys_info()
2681 *
2682 * Return suitable for printing on the console with the argument
2683 * adapter's configuration information.
2684 *
2685 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2686 * otherwise the static 'info' array will be overrun.
2687 */
2688 static const char *advansys_info(struct Scsi_Host *shost)
2689 {
2690 static char info[ASC_INFO_SIZE];
2691 struct asc_board *boardp = shost_priv(shost);
2692 ASC_DVC_VAR *asc_dvc_varp;
2693 ADV_DVC_VAR *adv_dvc_varp;
2694 char *busname;
2695 char *widename = NULL;
2696
2697 if (ASC_NARROW_BOARD(boardp)) {
2698 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2699 ASC_DBG(1, "begin\n");
2700 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2701 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2702 ASC_IS_ISAPNP) {
2703 busname = "ISA PnP";
2704 } else {
2705 busname = "ISA";
2706 }
2707 sprintf(info,
2708 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2709 ASC_VERSION, busname,
2710 (ulong)shost->io_port,
2711 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2712 boardp->irq, shost->dma_channel);
2713 } else {
2714 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2715 busname = "VL";
2716 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2717 busname = "EISA";
2718 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2719 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2720 == ASC_IS_PCI_ULTRA) {
2721 busname = "PCI Ultra";
2722 } else {
2723 busname = "PCI";
2724 }
2725 } else {
2726 busname = "?";
2727 shost_printk(KERN_ERR, shost, "unknown bus "
2728 "type %d\n", asc_dvc_varp->bus_type);
2729 }
2730 sprintf(info,
2731 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2732 ASC_VERSION, busname, (ulong)shost->io_port,
2733 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2734 boardp->irq);
2735 }
2736 } else {
2737 /*
2738 * Wide Adapter Information
2739 *
2740 * Memory-mapped I/O is used instead of I/O space to access
2741 * the adapter, but display the I/O Port range. The Memory
2742 * I/O address is displayed through the driver /proc file.
2743 */
2744 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2745 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2746 widename = "Ultra-Wide";
2747 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2748 widename = "Ultra2-Wide";
2749 } else {
2750 widename = "Ultra3-Wide";
2751 }
2752 sprintf(info,
2753 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2754 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2755 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2756 }
2757 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2758 ASC_DBG(1, "end\n");
2759 return info;
2760 }
2761
2762 #ifdef CONFIG_PROC_FS
2763
2764 /*
2765 * asc_prt_board_devices()
2766 *
2767 * Print driver information for devices attached to the board.
2768 */
2769 static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
2770 {
2771 struct asc_board *boardp = shost_priv(shost);
2772 int chip_scsi_id;
2773 int i;
2774
2775 seq_printf(m,
2776 "\nDevice Information for AdvanSys SCSI Host %d:\n",
2777 shost->host_no);
2778
2779 if (ASC_NARROW_BOARD(boardp)) {
2780 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2781 } else {
2782 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2783 }
2784
2785 seq_puts(m, "Target IDs Detected:");
2786 for (i = 0; i <= ADV_MAX_TID; i++) {
2787 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2788 seq_printf(m, " %X,", i);
2789 }
2790 seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
2791 }
2792
2793 /*
2794 * Display Wide Board BIOS Information.
2795 */
2796 static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
2797 {
2798 struct asc_board *boardp = shost_priv(shost);
2799 ushort major, minor, letter;
2800
2801 seq_puts(m, "\nROM BIOS Version: ");
2802
2803 /*
2804 * If the BIOS saved a valid signature, then fill in
2805 * the BIOS code segment base address.
2806 */
2807 if (boardp->bios_signature != 0x55AA) {
2808 seq_puts(m, "Disabled or Pre-3.1\n"
2809 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"
2810 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2811 } else {
2812 major = (boardp->bios_version >> 12) & 0xF;
2813 minor = (boardp->bios_version >> 8) & 0xF;
2814 letter = (boardp->bios_version & 0xFF);
2815
2816 seq_printf(m, "%d.%d%c\n",
2817 major, minor,
2818 letter >= 26 ? '?' : letter + 'A');
2819 /*
2820 * Current available ROM BIOS release is 3.1I for UW
2821 * and 3.2I for U2W. This code doesn't differentiate
2822 * UW and U2W boards.
2823 */
2824 if (major < 3 || (major <= 3 && minor < 1) ||
2825 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
2826 seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"
2827 "ftp://ftp.connectcom.net/pub\n");
2828 }
2829 }
2830 }
2831
2832 /*
2833 * Add serial number to information bar if signature AAh
2834 * is found in at bit 15-9 (7 bits) of word 1.
2835 *
2836 * Serial Number consists fo 12 alpha-numeric digits.
2837 *
2838 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
2839 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
2840 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
2841 * 5 - Product revision (A-J) Word0: " "
2842 *
2843 * Signature Word1: 15-9 (7 bits)
2844 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2845 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
2846 *
2847 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
2848 *
2849 * Note 1: Only production cards will have a serial number.
2850 *
2851 * Note 2: Signature is most significant 7 bits (0xFE).
2852 *
2853 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
2854 */
2855 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
2856 {
2857 ushort w, num;
2858
2859 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2860 return ASC_FALSE;
2861 } else {
2862 /*
2863 * First word - 6 digits.
2864 */
2865 w = serialnum[0];
2866
2867 /* Product type - 1st digit. */
2868 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2869 /* Product type is P=Prototype */
2870 *cp += 0x8;
2871 }
2872 cp++;
2873
2874 /* Manufacturing location - 2nd digit. */
2875 *cp++ = 'A' + ((w & 0x1C00) >> 10);
2876
2877 /* Product ID - 3rd, 4th digits. */
2878 num = w & 0x3FF;
2879 *cp++ = '0' + (num / 100);
2880 num %= 100;
2881 *cp++ = '0' + (num / 10);
2882
2883 /* Product revision - 5th digit. */
2884 *cp++ = 'A' + (num % 10);
2885
2886 /*
2887 * Second word
2888 */
2889 w = serialnum[1];
2890
2891 /*
2892 * Year - 6th digit.
2893 *
2894 * If bit 15 of third word is set, then the
2895 * last digit of the year is greater than 7.
2896 */
2897 if (serialnum[2] & 0x8000) {
2898 *cp++ = '8' + ((w & 0x1C0) >> 6);
2899 } else {
2900 *cp++ = '0' + ((w & 0x1C0) >> 6);
2901 }
2902
2903 /* Week of year - 7th, 8th digits. */
2904 num = w & 0x003F;
2905 *cp++ = '0' + num / 10;
2906 num %= 10;
2907 *cp++ = '0' + num;
2908
2909 /*
2910 * Third word
2911 */
2912 w = serialnum[2] & 0x7FFF;
2913
2914 /* Serial number - 9th digit. */
2915 *cp++ = 'A' + (w / 1000);
2916
2917 /* 10th, 11th, 12th digits. */
2918 num = w % 1000;
2919 *cp++ = '0' + num / 100;
2920 num %= 100;
2921 *cp++ = '0' + num / 10;
2922 num %= 10;
2923 *cp++ = '0' + num;
2924
2925 *cp = '\0'; /* Null Terminate the string. */
2926 return ASC_TRUE;
2927 }
2928 }
2929
2930 /*
2931 * asc_prt_asc_board_eeprom()
2932 *
2933 * Print board EEPROM configuration.
2934 */
2935 static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
2936 {
2937 struct asc_board *boardp = shost_priv(shost);
2938 ASC_DVC_VAR *asc_dvc_varp;
2939 ASCEEP_CONFIG *ep;
2940 int i;
2941 #ifdef CONFIG_ISA
2942 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
2943 #endif /* CONFIG_ISA */
2944 uchar serialstr[13];
2945
2946 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2947 ep = &boardp->eep_config.asc_eep;
2948
2949 seq_printf(m,
2950 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
2951 shost->host_no);
2952
2953 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
2954 == ASC_TRUE)
2955 seq_printf(m, " Serial Number: %s\n", serialstr);
2956 else if (ep->adapter_info[5] == 0xBB)
2957 seq_puts(m,
2958 " Default Settings Used for EEPROM-less Adapter.\n");
2959 else
2960 seq_puts(m, " Serial Number Signature Not Present.\n");
2961
2962 seq_printf(m,
2963 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2964 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
2965 ep->max_tag_qng);
2966
2967 seq_printf(m,
2968 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
2969
2970 seq_puts(m, " Target ID: ");
2971 for (i = 0; i <= ASC_MAX_TID; i++)
2972 seq_printf(m, " %d", i);
2973
2974 seq_puts(m, "\n Disconnects: ");
2975 for (i = 0; i <= ASC_MAX_TID; i++)
2976 seq_printf(m, " %c",
2977 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2978
2979 seq_puts(m, "\n Command Queuing: ");
2980 for (i = 0; i <= ASC_MAX_TID; i++)
2981 seq_printf(m, " %c",
2982 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2983
2984 seq_puts(m, "\n Start Motor: ");
2985 for (i = 0; i <= ASC_MAX_TID; i++)
2986 seq_printf(m, " %c",
2987 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2988
2989 seq_puts(m, "\n Synchronous Transfer:");
2990 for (i = 0; i <= ASC_MAX_TID; i++)
2991 seq_printf(m, " %c",
2992 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2993 seq_putc(m, '\n');
2994
2995 #ifdef CONFIG_ISA
2996 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2997 seq_printf(m,
2998 " Host ISA DMA speed: %d MB/S\n",
2999 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3000 }
3001 #endif /* CONFIG_ISA */
3002 }
3003
3004 /*
3005 * asc_prt_adv_board_eeprom()
3006 *
3007 * Print board EEPROM configuration.
3008 */
3009 static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
3010 {
3011 struct asc_board *boardp = shost_priv(shost);
3012 ADV_DVC_VAR *adv_dvc_varp;
3013 int i;
3014 char *termstr;
3015 uchar serialstr[13];
3016 ADVEEP_3550_CONFIG *ep_3550 = NULL;
3017 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3018 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3019 ushort word;
3020 ushort *wordp;
3021 ushort sdtr_speed = 0;
3022
3023 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3024 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3025 ep_3550 = &boardp->eep_config.adv_3550_eep;
3026 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3027 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3028 } else {
3029 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3030 }
3031
3032 seq_printf(m,
3033 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3034 shost->host_no);
3035
3036 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3037 wordp = &ep_3550->serial_number_word1;
3038 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3039 wordp = &ep_38C0800->serial_number_word1;
3040 } else {
3041 wordp = &ep_38C1600->serial_number_word1;
3042 }
3043
3044 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
3045 seq_printf(m, " Serial Number: %s\n", serialstr);
3046 else
3047 seq_puts(m, " Serial Number Signature Not Present.\n");
3048
3049 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3050 seq_printf(m,
3051 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3052 ep_3550->adapter_scsi_id,
3053 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3054 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3055 seq_printf(m,
3056 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3057 ep_38C0800->adapter_scsi_id,
3058 ep_38C0800->max_host_qng,
3059 ep_38C0800->max_dvc_qng);
3060 else
3061 seq_printf(m,
3062 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3063 ep_38C1600->adapter_scsi_id,
3064 ep_38C1600->max_host_qng,
3065 ep_38C1600->max_dvc_qng);
3066 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3067 word = ep_3550->termination;
3068 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3069 word = ep_38C0800->termination_lvd;
3070 } else {
3071 word = ep_38C1600->termination_lvd;
3072 }
3073 switch (word) {
3074 case 1:
3075 termstr = "Low Off/High Off";
3076 break;
3077 case 2:
3078 termstr = "Low Off/High On";
3079 break;
3080 case 3:
3081 termstr = "Low On/High On";
3082 break;
3083 default:
3084 case 0:
3085 termstr = "Automatic";
3086 break;
3087 }
3088
3089 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3090 seq_printf(m,
3091 " termination: %u (%s), bios_ctrl: 0x%x\n",
3092 ep_3550->termination, termstr,
3093 ep_3550->bios_ctrl);
3094 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3095 seq_printf(m,
3096 " termination: %u (%s), bios_ctrl: 0x%x\n",
3097 ep_38C0800->termination_lvd, termstr,
3098 ep_38C0800->bios_ctrl);
3099 else
3100 seq_printf(m,
3101 " termination: %u (%s), bios_ctrl: 0x%x\n",
3102 ep_38C1600->termination_lvd, termstr,
3103 ep_38C1600->bios_ctrl);
3104
3105 seq_puts(m, " Target ID: ");
3106 for (i = 0; i <= ADV_MAX_TID; i++)
3107 seq_printf(m, " %X", i);
3108 seq_putc(m, '\n');
3109
3110 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3111 word = ep_3550->disc_enable;
3112 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3113 word = ep_38C0800->disc_enable;
3114 } else {
3115 word = ep_38C1600->disc_enable;
3116 }
3117 seq_puts(m, " Disconnects: ");
3118 for (i = 0; i <= ADV_MAX_TID; i++)
3119 seq_printf(m, " %c",
3120 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3121 seq_putc(m, '\n');
3122
3123 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3124 word = ep_3550->tagqng_able;
3125 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3126 word = ep_38C0800->tagqng_able;
3127 } else {
3128 word = ep_38C1600->tagqng_able;
3129 }
3130 seq_puts(m, " Command Queuing: ");
3131 for (i = 0; i <= ADV_MAX_TID; i++)
3132 seq_printf(m, " %c",
3133 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3134 seq_putc(m, '\n');
3135
3136 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3137 word = ep_3550->start_motor;
3138 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3139 word = ep_38C0800->start_motor;
3140 } else {
3141 word = ep_38C1600->start_motor;
3142 }
3143 seq_puts(m, " Start Motor: ");
3144 for (i = 0; i <= ADV_MAX_TID; i++)
3145 seq_printf(m, " %c",
3146 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3147 seq_putc(m, '\n');
3148
3149 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3150 seq_puts(m, " Synchronous Transfer:");
3151 for (i = 0; i <= ADV_MAX_TID; i++)
3152 seq_printf(m, " %c",
3153 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3154 'Y' : 'N');
3155 seq_putc(m, '\n');
3156 }
3157
3158 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3159 seq_puts(m, " Ultra Transfer: ");
3160 for (i = 0; i <= ADV_MAX_TID; i++)
3161 seq_printf(m, " %c",
3162 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3163 ? 'Y' : 'N');
3164 seq_putc(m, '\n');
3165 }
3166
3167 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3168 word = ep_3550->wdtr_able;
3169 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3170 word = ep_38C0800->wdtr_able;
3171 } else {
3172 word = ep_38C1600->wdtr_able;
3173 }
3174 seq_puts(m, " Wide Transfer: ");
3175 for (i = 0; i <= ADV_MAX_TID; i++)
3176 seq_printf(m, " %c",
3177 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3178 seq_putc(m, '\n');
3179
3180 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3181 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3182 seq_puts(m, " Synchronous Transfer Speed (Mhz):\n ");
3183 for (i = 0; i <= ADV_MAX_TID; i++) {
3184 char *speed_str;
3185
3186 if (i == 0) {
3187 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3188 } else if (i == 4) {
3189 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3190 } else if (i == 8) {
3191 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3192 } else if (i == 12) {
3193 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3194 }
3195 switch (sdtr_speed & ADV_MAX_TID) {
3196 case 0:
3197 speed_str = "Off";
3198 break;
3199 case 1:
3200 speed_str = " 5";
3201 break;
3202 case 2:
3203 speed_str = " 10";
3204 break;
3205 case 3:
3206 speed_str = " 20";
3207 break;
3208 case 4:
3209 speed_str = " 40";
3210 break;
3211 case 5:
3212 speed_str = " 80";
3213 break;
3214 default:
3215 speed_str = "Unk";
3216 break;
3217 }
3218 seq_printf(m, "%X:%s ", i, speed_str);
3219 if (i == 7)
3220 seq_puts(m, "\n ");
3221 sdtr_speed >>= 4;
3222 }
3223 seq_putc(m, '\n');
3224 }
3225 }
3226
3227 /*
3228 * asc_prt_driver_conf()
3229 */
3230 static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
3231 {
3232 struct asc_board *boardp = shost_priv(shost);
3233 int chip_scsi_id;
3234
3235 seq_printf(m,
3236 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3237 shost->host_no);
3238
3239 seq_printf(m,
3240 " host_busy %u, max_id %u, max_lun %llu, max_channel %u\n",
3241 atomic_read(&shost->host_busy), shost->max_id,
3242 shost->max_lun, shost->max_channel);
3243
3244 seq_printf(m,
3245 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3246 shost->unique_id, shost->can_queue, shost->this_id,
3247 shost->sg_tablesize, shost->cmd_per_lun);
3248
3249 seq_printf(m,
3250 " unchecked_isa_dma %d, use_clustering %d\n",
3251 shost->unchecked_isa_dma, shost->use_clustering);
3252
3253 seq_printf(m,
3254 " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
3255 boardp->flags, shost->last_reset, jiffies,
3256 boardp->asc_n_io_port);
3257
3258 seq_printf(m, " io_port 0x%lx\n", shost->io_port);
3259
3260 if (ASC_NARROW_BOARD(boardp)) {
3261 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3262 } else {
3263 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3264 }
3265 }
3266
3267 /*
3268 * asc_prt_asc_board_info()
3269 *
3270 * Print dynamic board configuration information.
3271 */
3272 static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
3273 {
3274 struct asc_board *boardp = shost_priv(shost);
3275 int chip_scsi_id;
3276 ASC_DVC_VAR *v;
3277 ASC_DVC_CFG *c;
3278 int i;
3279 int renegotiate = 0;
3280
3281 v = &boardp->dvc_var.asc_dvc_var;
3282 c = &boardp->dvc_cfg.asc_dvc_cfg;
3283 chip_scsi_id = c->chip_scsi_id;
3284
3285 seq_printf(m,
3286 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3287 shost->host_no);
3288
3289 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3290 "mcode_version 0x%x, err_code %u\n",
3291 c->chip_version, c->mcode_date, c->mcode_version,
3292 v->err_code);
3293
3294 /* Current number of commands waiting for the host. */
3295 seq_printf(m,
3296 " Total Command Pending: %d\n", v->cur_total_qng);
3297
3298 seq_puts(m, " Command Queuing:");
3299 for (i = 0; i <= ASC_MAX_TID; i++) {
3300 if ((chip_scsi_id == i) ||
3301 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3302 continue;
3303 }
3304 seq_printf(m, " %X:%c",
3305 i,
3306 (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3307 }
3308
3309 /* Current number of commands waiting for a device. */
3310 seq_puts(m, "\n Command Queue Pending:");
3311 for (i = 0; i <= ASC_MAX_TID; i++) {
3312 if ((chip_scsi_id == i) ||
3313 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3314 continue;
3315 }
3316 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
3317 }
3318
3319 /* Current limit on number of commands that can be sent to a device. */
3320 seq_puts(m, "\n Command Queue Limit:");
3321 for (i = 0; i <= ASC_MAX_TID; i++) {
3322 if ((chip_scsi_id == i) ||
3323 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3324 continue;
3325 }
3326 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
3327 }
3328
3329 /* Indicate whether the device has returned queue full status. */
3330 seq_puts(m, "\n Command Queue Full:");
3331 for (i = 0; i <= ASC_MAX_TID; i++) {
3332 if ((chip_scsi_id == i) ||
3333 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3334 continue;
3335 }
3336 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3337 seq_printf(m, " %X:Y-%d",
3338 i, boardp->queue_full_cnt[i]);
3339 else
3340 seq_printf(m, " %X:N", i);
3341 }
3342
3343 seq_puts(m, "\n Synchronous Transfer:");
3344 for (i = 0; i <= ASC_MAX_TID; i++) {
3345 if ((chip_scsi_id == i) ||
3346 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3347 continue;
3348 }
3349 seq_printf(m, " %X:%c",
3350 i,
3351 (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3352 }
3353 seq_putc(m, '\n');
3354
3355 for (i = 0; i <= ASC_MAX_TID; i++) {
3356 uchar syn_period_ix;
3357
3358 if ((chip_scsi_id == i) ||
3359 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3360 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3361 continue;
3362 }
3363
3364 seq_printf(m, " %X:", i);
3365
3366 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3367 seq_puts(m, " Asynchronous");
3368 } else {
3369 syn_period_ix =
3370 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3371 1);
3372
3373 seq_printf(m,
3374 " Transfer Period Factor: %d (%d.%d Mhz),",
3375 v->sdtr_period_tbl[syn_period_ix],
3376 250 / v->sdtr_period_tbl[syn_period_ix],
3377 ASC_TENTHS(250,
3378 v->sdtr_period_tbl[syn_period_ix]));
3379
3380 seq_printf(m, " REQ/ACK Offset: %d",
3381 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3382 }
3383
3384 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3385 seq_puts(m, "*\n");
3386 renegotiate = 1;
3387 } else {
3388 seq_putc(m, '\n');
3389 }
3390 }
3391
3392 if (renegotiate) {
3393 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3394 }
3395 }
3396
3397 /*
3398 * asc_prt_adv_board_info()
3399 *
3400 * Print dynamic board configuration information.
3401 */
3402 static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
3403 {
3404 struct asc_board *boardp = shost_priv(shost);
3405 int i;
3406 ADV_DVC_VAR *v;
3407 ADV_DVC_CFG *c;
3408 AdvPortAddr iop_base;
3409 ushort chip_scsi_id;
3410 ushort lramword;
3411 uchar lrambyte;
3412 ushort tagqng_able;
3413 ushort sdtr_able, wdtr_able;
3414 ushort wdtr_done, sdtr_done;
3415 ushort period = 0;
3416 int renegotiate = 0;
3417
3418 v = &boardp->dvc_var.adv_dvc_var;
3419 c = &boardp->dvc_cfg.adv_dvc_cfg;
3420 iop_base = v->iop_base;
3421 chip_scsi_id = v->chip_scsi_id;
3422
3423 seq_printf(m,
3424 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3425 shost->host_no);
3426
3427 seq_printf(m,
3428 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3429 (unsigned long)v->iop_base,
3430 AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3431 v->err_code);
3432
3433 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3434 "mcode_version 0x%x\n", c->chip_version,
3435 c->mcode_date, c->mcode_version);
3436
3437 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3438 seq_puts(m, " Queuing Enabled:");
3439 for (i = 0; i <= ADV_MAX_TID; i++) {
3440 if ((chip_scsi_id == i) ||
3441 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3442 continue;
3443 }
3444
3445 seq_printf(m, " %X:%c",
3446 i,
3447 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3448 }
3449
3450 seq_puts(m, "\n Queue Limit:");
3451 for (i = 0; i <= ADV_MAX_TID; i++) {
3452 if ((chip_scsi_id == i) ||
3453 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3454 continue;
3455 }
3456
3457 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3458 lrambyte);
3459
3460 seq_printf(m, " %X:%d", i, lrambyte);
3461 }
3462
3463 seq_puts(m, "\n Command Pending:");
3464 for (i = 0; i <= ADV_MAX_TID; i++) {
3465 if ((chip_scsi_id == i) ||
3466 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3467 continue;
3468 }
3469
3470 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3471 lrambyte);
3472
3473 seq_printf(m, " %X:%d", i, lrambyte);
3474 }
3475 seq_putc(m, '\n');
3476
3477 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3478 seq_puts(m, " Wide Enabled:");
3479 for (i = 0; i <= ADV_MAX_TID; i++) {
3480 if ((chip_scsi_id == i) ||
3481 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3482 continue;
3483 }
3484
3485 seq_printf(m, " %X:%c",
3486 i,
3487 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3488 }
3489 seq_putc(m, '\n');
3490
3491 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3492 seq_puts(m, " Transfer Bit Width:");
3493 for (i = 0; i <= ADV_MAX_TID; i++) {
3494 if ((chip_scsi_id == i) ||
3495 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3496 continue;
3497 }
3498
3499 AdvReadWordLram(iop_base,
3500 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3501 lramword);
3502
3503 seq_printf(m, " %X:%d",
3504 i, (lramword & 0x8000) ? 16 : 8);
3505
3506 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3507 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3508 seq_putc(m, '*');
3509 renegotiate = 1;
3510 }
3511 }
3512 seq_putc(m, '\n');
3513
3514 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3515 seq_puts(m, " Synchronous Enabled:");
3516 for (i = 0; i <= ADV_MAX_TID; i++) {
3517 if ((chip_scsi_id == i) ||
3518 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3519 continue;
3520 }
3521
3522 seq_printf(m, " %X:%c",
3523 i,
3524 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3525 }
3526 seq_putc(m, '\n');
3527
3528 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3529 for (i = 0; i <= ADV_MAX_TID; i++) {
3530
3531 AdvReadWordLram(iop_base,
3532 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3533 lramword);
3534 lramword &= ~0x8000;
3535
3536 if ((chip_scsi_id == i) ||
3537 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3538 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3539 continue;
3540 }
3541
3542 seq_printf(m, " %X:", i);
3543
3544 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
3545 seq_puts(m, " Asynchronous");
3546 } else {
3547 seq_puts(m, " Transfer Period Factor: ");
3548
3549 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
3550 seq_puts(m, "9 (80.0 Mhz),");
3551 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
3552 seq_puts(m, "10 (40.0 Mhz),");
3553 } else { /* 20 Mhz or below. */
3554
3555 period = (((lramword >> 8) * 25) + 50) / 4;
3556
3557 if (period == 0) { /* Should never happen. */
3558 seq_printf(m, "%d (? Mhz), ", period);
3559 } else {
3560 seq_printf(m,
3561 "%d (%d.%d Mhz),",
3562 period, 250 / period,
3563 ASC_TENTHS(250, period));
3564 }
3565 }
3566
3567 seq_printf(m, " REQ/ACK Offset: %d",
3568 lramword & 0x1F);
3569 }
3570
3571 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3572 seq_puts(m, "*\n");
3573 renegotiate = 1;
3574 } else {
3575 seq_putc(m, '\n');
3576 }
3577 }
3578
3579 if (renegotiate) {
3580 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3581 }
3582 }
3583
3584 #ifdef ADVANSYS_STATS
3585 /*
3586 * asc_prt_board_stats()
3587 */
3588 static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
3589 {
3590 struct asc_board *boardp = shost_priv(shost);
3591 struct asc_stats *s = &boardp->asc_stats;
3592
3593 seq_printf(m,
3594 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3595 shost->host_no);
3596
3597 seq_printf(m,
3598 " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
3599 s->queuecommand, s->reset, s->biosparam,
3600 s->interrupt);
3601
3602 seq_printf(m,
3603 " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
3604 s->callback, s->done, s->build_error,
3605 s->adv_build_noreq, s->adv_build_nosg);
3606
3607 seq_printf(m,
3608 " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
3609 s->exe_noerror, s->exe_busy, s->exe_error,
3610 s->exe_unknown);
3611
3612 /*
3613 * Display data transfer statistics.
3614 */
3615 if (s->xfer_cnt > 0) {
3616 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
3617 s->xfer_cnt, s->xfer_elem);
3618
3619 seq_printf(m, "xfer_bytes %u.%01u kb\n",
3620 s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
3621
3622 /* Scatter gather transfer statistics */
3623 seq_printf(m, " avg_num_elem %u.%01u, ",
3624 s->xfer_elem / s->xfer_cnt,
3625 ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
3626
3627 seq_printf(m, "avg_elem_size %u.%01u kb, ",
3628 (s->xfer_sect / 2) / s->xfer_elem,
3629 ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
3630
3631 seq_printf(m, "avg_xfer_size %u.%01u kb\n",
3632 (s->xfer_sect / 2) / s->xfer_cnt,
3633 ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
3634 }
3635 }
3636 #endif /* ADVANSYS_STATS */
3637
3638 /*
3639 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
3640 *
3641 * m: seq_file to print into
3642 * shost: Scsi_Host
3643 *
3644 * Return the number of bytes read from or written to a
3645 * /proc/scsi/advansys/[0...] file.
3646 */
3647 static int
3648 advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
3649 {
3650 struct asc_board *boardp = shost_priv(shost);
3651
3652 ASC_DBG(1, "begin\n");
3653
3654 /*
3655 * User read of /proc/scsi/advansys/[0...] file.
3656 */
3657
3658 /*
3659 * Get board configuration information.
3660 *
3661 * advansys_info() returns the board string from its own static buffer.
3662 */
3663 /* Copy board information. */
3664 seq_printf(m, "%s\n", (char *)advansys_info(shost));
3665 /*
3666 * Display Wide Board BIOS Information.
3667 */
3668 if (!ASC_NARROW_BOARD(boardp))
3669 asc_prt_adv_bios(m, shost);
3670
3671 /*
3672 * Display driver information for each device attached to the board.
3673 */
3674 asc_prt_board_devices(m, shost);
3675
3676 /*
3677 * Display EEPROM configuration for the board.
3678 */
3679 if (ASC_NARROW_BOARD(boardp))
3680 asc_prt_asc_board_eeprom(m, shost);
3681 else
3682 asc_prt_adv_board_eeprom(m, shost);
3683
3684 /*
3685 * Display driver configuration and information for the board.
3686 */
3687 asc_prt_driver_conf(m, shost);
3688
3689 #ifdef ADVANSYS_STATS
3690 /*
3691 * Display driver statistics for the board.
3692 */
3693 asc_prt_board_stats(m, shost);
3694 #endif /* ADVANSYS_STATS */
3695
3696 /*
3697 * Display Asc Library dynamic configuration information
3698 * for the board.
3699 */
3700 if (ASC_NARROW_BOARD(boardp))
3701 asc_prt_asc_board_info(m, shost);
3702 else
3703 asc_prt_adv_board_info(m, shost);
3704 return 0;
3705 }
3706 #endif /* CONFIG_PROC_FS */
3707
3708 static void asc_scsi_done(struct scsi_cmnd *scp)
3709 {
3710 scsi_dma_unmap(scp);
3711 ASC_STATS(scp->device->host, done);
3712 scp->scsi_done(scp);
3713 }
3714
3715 static void AscSetBank(PortAddr iop_base, uchar bank)
3716 {
3717 uchar val;
3718
3719 val = AscGetChipControl(iop_base) &
3720 (~
3721 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3722 CC_CHIP_RESET));
3723 if (bank == 1) {
3724 val |= CC_BANK_ONE;
3725 } else if (bank == 2) {
3726 val |= CC_DIAG | CC_BANK_ONE;
3727 } else {
3728 val &= ~CC_BANK_ONE;
3729 }
3730 AscSetChipControl(iop_base, val);
3731 }
3732
3733 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3734 {
3735 AscSetBank(iop_base, 1);
3736 AscWriteChipIH(iop_base, ins_code);
3737 AscSetBank(iop_base, 0);
3738 }
3739
3740 static int AscStartChip(PortAddr iop_base)
3741 {
3742 AscSetChipControl(iop_base, 0);
3743 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3744 return (0);
3745 }
3746 return (1);
3747 }
3748
3749 static bool AscStopChip(PortAddr iop_base)
3750 {
3751 uchar cc_val;
3752
3753 cc_val =
3754 AscGetChipControl(iop_base) &
3755 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3756 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3757 AscSetChipIH(iop_base, INS_HALT);
3758 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3759 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
3760 return false;
3761 }
3762 return true;
3763 }
3764
3765 static bool AscIsChipHalted(PortAddr iop_base)
3766 {
3767 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3768 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
3769 return true;
3770 }
3771 }
3772 return false;
3773 }
3774
3775 static bool AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
3776 {
3777 PortAddr iop_base;
3778 int i = 10;
3779
3780 iop_base = asc_dvc->iop_base;
3781 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3782 && (i-- > 0)) {
3783 mdelay(100);
3784 }
3785 AscStopChip(iop_base);
3786 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3787 udelay(60);
3788 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3789 AscSetChipIH(iop_base, INS_HALT);
3790 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3791 AscSetChipControl(iop_base, CC_HALT);
3792 mdelay(200);
3793 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3794 AscSetChipStatus(iop_base, 0);
3795 return (AscIsChipHalted(iop_base));
3796 }
3797
3798 static int AscFindSignature(PortAddr iop_base)
3799 {
3800 ushort sig_word;
3801
3802 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
3803 iop_base, AscGetChipSignatureByte(iop_base));
3804 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
3805 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
3806 iop_base, AscGetChipSignatureWord(iop_base));
3807 sig_word = AscGetChipSignatureWord(iop_base);
3808 if ((sig_word == (ushort)ASC_1000_ID0W) ||
3809 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3810 return (1);
3811 }
3812 }
3813 return (0);
3814 }
3815
3816 static void AscEnableInterrupt(PortAddr iop_base)
3817 {
3818 ushort cfg;
3819
3820 cfg = AscGetChipCfgLsw(iop_base);
3821 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
3822 }
3823
3824 static void AscDisableInterrupt(PortAddr iop_base)
3825 {
3826 ushort cfg;
3827
3828 cfg = AscGetChipCfgLsw(iop_base);
3829 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
3830 }
3831
3832 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3833 {
3834 unsigned char byte_data;
3835 unsigned short word_data;
3836
3837 if (isodd_word(addr)) {
3838 AscSetChipLramAddr(iop_base, addr - 1);
3839 word_data = AscGetChipLramData(iop_base);
3840 byte_data = (word_data >> 8) & 0xFF;
3841 } else {
3842 AscSetChipLramAddr(iop_base, addr);
3843 word_data = AscGetChipLramData(iop_base);
3844 byte_data = word_data & 0xFF;
3845 }
3846 return byte_data;
3847 }
3848
3849 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3850 {
3851 ushort word_data;
3852
3853 AscSetChipLramAddr(iop_base, addr);
3854 word_data = AscGetChipLramData(iop_base);
3855 return (word_data);
3856 }
3857
3858 #if CC_VERY_LONG_SG_LIST
3859 static u32 AscReadLramDWord(PortAddr iop_base, ushort addr)
3860 {
3861 ushort val_low, val_high;
3862 u32 dword_data;
3863
3864 AscSetChipLramAddr(iop_base, addr);
3865 val_low = AscGetChipLramData(iop_base);
3866 val_high = AscGetChipLramData(iop_base);
3867 dword_data = ((u32) val_high << 16) | (u32) val_low;
3868 return (dword_data);
3869 }
3870 #endif /* CC_VERY_LONG_SG_LIST */
3871
3872 static void
3873 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3874 {
3875 int i;
3876
3877 AscSetChipLramAddr(iop_base, s_addr);
3878 for (i = 0; i < words; i++) {
3879 AscSetChipLramData(iop_base, set_wval);
3880 }
3881 }
3882
3883 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
3884 {
3885 AscSetChipLramAddr(iop_base, addr);
3886 AscSetChipLramData(iop_base, word_val);
3887 }
3888
3889 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
3890 {
3891 ushort word_data;
3892
3893 if (isodd_word(addr)) {
3894 addr--;
3895 word_data = AscReadLramWord(iop_base, addr);
3896 word_data &= 0x00FF;
3897 word_data |= (((ushort)byte_val << 8) & 0xFF00);
3898 } else {
3899 word_data = AscReadLramWord(iop_base, addr);
3900 word_data &= 0xFF00;
3901 word_data |= ((ushort)byte_val & 0x00FF);
3902 }
3903 AscWriteLramWord(iop_base, addr, word_data);
3904 }
3905
3906 /*
3907 * Copy 2 bytes to LRAM.
3908 *
3909 * The source data is assumed to be in little-endian order in memory
3910 * and is maintained in little-endian order when written to LRAM.
3911 */
3912 static void
3913 AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
3914 const uchar *s_buffer, int words)
3915 {
3916 int i;
3917
3918 AscSetChipLramAddr(iop_base, s_addr);
3919 for (i = 0; i < 2 * words; i += 2) {
3920 /*
3921 * On a little-endian system the second argument below
3922 * produces a little-endian ushort which is written to
3923 * LRAM in little-endian order. On a big-endian system
3924 * the second argument produces a big-endian ushort which
3925 * is "transparently" byte-swapped by outpw() and written
3926 * in little-endian order to LRAM.
3927 */
3928 outpw(iop_base + IOP_RAM_DATA,
3929 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
3930 }
3931 }
3932
3933 /*
3934 * Copy 4 bytes to LRAM.
3935 *
3936 * The source data is assumed to be in little-endian order in memory
3937 * and is maintained in little-endian order when written to LRAM.
3938 */
3939 static void
3940 AscMemDWordCopyPtrToLram(PortAddr iop_base,
3941 ushort s_addr, uchar *s_buffer, int dwords)
3942 {
3943 int i;
3944
3945 AscSetChipLramAddr(iop_base, s_addr);
3946 for (i = 0; i < 4 * dwords; i += 4) {
3947 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
3948 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
3949 }
3950 }
3951
3952 /*
3953 * Copy 2 bytes from LRAM.
3954 *
3955 * The source data is assumed to be in little-endian order in LRAM
3956 * and is maintained in little-endian order when written to memory.
3957 */
3958 static void
3959 AscMemWordCopyPtrFromLram(PortAddr iop_base,
3960 ushort s_addr, uchar *d_buffer, int words)
3961 {
3962 int i;
3963 ushort word;
3964
3965 AscSetChipLramAddr(iop_base, s_addr);
3966 for (i = 0; i < 2 * words; i += 2) {
3967 word = inpw(iop_base + IOP_RAM_DATA);
3968 d_buffer[i] = word & 0xff;
3969 d_buffer[i + 1] = (word >> 8) & 0xff;
3970 }
3971 }
3972
3973 static u32 AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
3974 {
3975 u32 sum = 0;
3976 int i;
3977
3978 for (i = 0; i < words; i++, s_addr += 2) {
3979 sum += AscReadLramWord(iop_base, s_addr);
3980 }
3981 return (sum);
3982 }
3983
3984 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
3985 {
3986 uchar i;
3987 ushort s_addr;
3988 PortAddr iop_base;
3989 ushort warn_code;
3990
3991 iop_base = asc_dvc->iop_base;
3992 warn_code = 0;
3993 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
3994 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
3995 64) >> 1));
3996 i = ASC_MIN_ACTIVE_QNO;
3997 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
3998 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3999 (uchar)(i + 1));
4000 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4001 (uchar)(asc_dvc->max_total_qng));
4002 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4003 (uchar)i);
4004 i++;
4005 s_addr += ASC_QBLK_SIZE;
4006 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4007 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4008 (uchar)(i + 1));
4009 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4010 (uchar)(i - 1));
4011 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4012 (uchar)i);
4013 }
4014 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4015 (uchar)ASC_QLINK_END);
4016 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4017 (uchar)(asc_dvc->max_total_qng - 1));
4018 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4019 (uchar)asc_dvc->max_total_qng);
4020 i++;
4021 s_addr += ASC_QBLK_SIZE;
4022 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4023 i++, s_addr += ASC_QBLK_SIZE) {
4024 AscWriteLramByte(iop_base,
4025 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4026 AscWriteLramByte(iop_base,
4027 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4028 AscWriteLramByte(iop_base,
4029 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4030 }
4031 return warn_code;
4032 }
4033
4034 static u32
4035 AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
4036 const uchar *mcode_buf, ushort mcode_size)
4037 {
4038 u32 chksum;
4039 ushort mcode_word_size;
4040 ushort mcode_chksum;
4041
4042 /* Write the microcode buffer starting at LRAM address 0. */
4043 mcode_word_size = (ushort)(mcode_size >> 1);
4044 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4045 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4046
4047 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4048 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
4049 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4050 (ushort)ASC_CODE_SEC_BEG,
4051 (ushort)((mcode_size -
4052 s_addr - (ushort)
4053 ASC_CODE_SEC_BEG) /
4054 2));
4055 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
4056 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4057 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4058 return chksum;
4059 }
4060
4061 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
4062 {
4063 PortAddr iop_base;
4064 int i;
4065 ushort lram_addr;
4066
4067 iop_base = asc_dvc->iop_base;
4068 AscPutRiscVarFreeQHead(iop_base, 1);
4069 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4070 AscPutVarFreeQHead(iop_base, 1);
4071 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4072 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4073 (uchar)((int)asc_dvc->max_total_qng + 1));
4074 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4075 (uchar)((int)asc_dvc->max_total_qng + 2));
4076 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4077 asc_dvc->max_total_qng);
4078 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4079 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4080 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4081 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4082 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4083 AscPutQDoneInProgress(iop_base, 0);
4084 lram_addr = ASC_QADR_BEG;
4085 for (i = 0; i < 32; i++, lram_addr += 2) {
4086 AscWriteLramWord(iop_base, lram_addr, 0);
4087 }
4088 }
4089
4090 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
4091 {
4092 int i;
4093 ushort warn_code;
4094 PortAddr iop_base;
4095 __le32 phy_addr;
4096 __le32 phy_size;
4097 struct asc_board *board = asc_dvc_to_board(asc_dvc);
4098
4099 iop_base = asc_dvc->iop_base;
4100 warn_code = 0;
4101 for (i = 0; i <= ASC_MAX_TID; i++) {
4102 AscPutMCodeInitSDTRAtID(iop_base, i,
4103 asc_dvc->cfg->sdtr_period_offset[i]);
4104 }
4105
4106 AscInitQLinkVar(asc_dvc);
4107 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4108 asc_dvc->cfg->disc_enable);
4109 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4110 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4111
4112 /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4113 BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4114 asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4115 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4116 if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4117 warn_code = -ENOMEM;
4118 goto err_dma_map;
4119 }
4120 phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
4121 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4122 (uchar *)&phy_addr, 1);
4123 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
4124 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4125 (uchar *)&phy_size, 1);
4126
4127 asc_dvc->cfg->mcode_date =
4128 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4129 asc_dvc->cfg->mcode_version =
4130 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4131
4132 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4133 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4134 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
4135 warn_code = UW_ERR;
4136 goto err_mcode_start;
4137 }
4138 if (AscStartChip(iop_base) != 1) {
4139 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
4140 warn_code = UW_ERR;
4141 goto err_mcode_start;
4142 }
4143
4144 return warn_code;
4145
4146 err_mcode_start:
4147 dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4148 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4149 err_dma_map:
4150 asc_dvc->overrun_dma = 0;
4151 return warn_code;
4152 }
4153
4154 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4155 {
4156 const struct firmware *fw;
4157 const char fwname[] = "advansys/mcode.bin";
4158 int err;
4159 unsigned long chksum;
4160 ushort warn_code;
4161 PortAddr iop_base;
4162
4163 iop_base = asc_dvc->iop_base;
4164 warn_code = 0;
4165 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4166 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4167 AscResetChipAndScsiBus(asc_dvc);
4168 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4169 }
4170 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4171 if (asc_dvc->err_code != 0)
4172 return UW_ERR;
4173 if (!AscFindSignature(asc_dvc->iop_base)) {
4174 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4175 return warn_code;
4176 }
4177 AscDisableInterrupt(iop_base);
4178 warn_code |= AscInitLram(asc_dvc);
4179 if (asc_dvc->err_code != 0)
4180 return UW_ERR;
4181
4182 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4183 if (err) {
4184 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4185 fwname, err);
4186 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4187 return err;
4188 }
4189 if (fw->size < 4) {
4190 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4191 fw->size, fwname);
4192 release_firmware(fw);
4193 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4194 return -EINVAL;
4195 }
4196 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4197 (fw->data[1] << 8) | fw->data[0];
4198 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4199 if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4200 fw->size - 4) != chksum) {
4201 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4202 release_firmware(fw);
4203 return warn_code;
4204 }
4205 release_firmware(fw);
4206 warn_code |= AscInitMicroCodeVar(asc_dvc);
4207 if (!asc_dvc->overrun_dma)
4208 return warn_code;
4209 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4210 AscEnableInterrupt(iop_base);
4211 return warn_code;
4212 }
4213
4214 /*
4215 * Load the Microcode
4216 *
4217 * Write the microcode image to RISC memory starting at address 0.
4218 *
4219 * The microcode is stored compressed in the following format:
4220 *
4221 * 254 word (508 byte) table indexed by byte code followed
4222 * by the following byte codes:
4223 *
4224 * 1-Byte Code:
4225 * 00: Emit word 0 in table.
4226 * 01: Emit word 1 in table.
4227 * .
4228 * FD: Emit word 253 in table.
4229 *
4230 * Multi-Byte Code:
4231 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4232 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4233 *
4234 * Returns 0 or an error if the checksum doesn't match
4235 */
4236 static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4237 int size, int memsize, int chksum)
4238 {
4239 int i, j, end, len = 0;
4240 u32 sum;
4241
4242 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4243
4244 for (i = 253 * 2; i < size; i++) {
4245 if (buf[i] == 0xff) {
4246 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4247 for (j = 0; j < buf[i + 1]; j++) {
4248 AdvWriteWordAutoIncLram(iop_base, word);
4249 len += 2;
4250 }
4251 i += 3;
4252 } else if (buf[i] == 0xfe) {
4253 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4254 AdvWriteWordAutoIncLram(iop_base, word);
4255 i += 2;
4256 len += 2;
4257 } else {
4258 unsigned int off = buf[i] * 2;
4259 unsigned short word = (buf[off + 1] << 8) | buf[off];
4260 AdvWriteWordAutoIncLram(iop_base, word);
4261 len += 2;
4262 }
4263 }
4264
4265 end = len;
4266
4267 while (len < memsize) {
4268 AdvWriteWordAutoIncLram(iop_base, 0);
4269 len += 2;
4270 }
4271
4272 /* Verify the microcode checksum. */
4273 sum = 0;
4274 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4275
4276 for (len = 0; len < end; len += 2) {
4277 sum += AdvReadWordAutoIncLram(iop_base);
4278 }
4279
4280 if (sum != chksum)
4281 return ASC_IERR_MCODE_CHKSUM;
4282
4283 return 0;
4284 }
4285
4286 static void AdvBuildCarrierFreelist(struct adv_dvc_var *adv_dvc)
4287 {
4288 off_t carr_offset = 0, next_offset;
4289 dma_addr_t carr_paddr;
4290 int carr_num = ADV_CARRIER_BUFSIZE / sizeof(ADV_CARR_T), i;
4291
4292 for (i = 0; i < carr_num; i++) {
4293 carr_offset = i * sizeof(ADV_CARR_T);
4294 /* Get physical address of the carrier 'carrp'. */
4295 carr_paddr = adv_dvc->carrier_addr + carr_offset;
4296
4297 adv_dvc->carrier[i].carr_pa = cpu_to_le32(carr_paddr);
4298 adv_dvc->carrier[i].carr_va = cpu_to_le32(carr_offset);
4299 adv_dvc->carrier[i].areq_vpa = 0;
4300 next_offset = carr_offset + sizeof(ADV_CARR_T);
4301 if (i == carr_num)
4302 next_offset = ~0;
4303 adv_dvc->carrier[i].next_vpa = cpu_to_le32(next_offset);
4304 }
4305 /*
4306 * We cannot have a carrier with 'carr_va' of '0', as
4307 * a reference to this carrier would be interpreted as
4308 * list termination.
4309 * So start at carrier 1 with the freelist.
4310 */
4311 adv_dvc->carr_freelist = &adv_dvc->carrier[1];
4312 }
4313
4314 static ADV_CARR_T *adv_get_carrier(struct adv_dvc_var *adv_dvc, u32 offset)
4315 {
4316 int index;
4317
4318 BUG_ON(offset > ADV_CARRIER_BUFSIZE);
4319
4320 index = offset / sizeof(ADV_CARR_T);
4321 return &adv_dvc->carrier[index];
4322 }
4323
4324 static ADV_CARR_T *adv_get_next_carrier(struct adv_dvc_var *adv_dvc)
4325 {
4326 ADV_CARR_T *carrp = adv_dvc->carr_freelist;
4327 u32 next_vpa = le32_to_cpu(carrp->next_vpa);
4328
4329 if (next_vpa == 0 || next_vpa == ~0) {
4330 ASC_DBG(1, "invalid vpa offset 0x%x\n", next_vpa);
4331 return NULL;
4332 }
4333
4334 adv_dvc->carr_freelist = adv_get_carrier(adv_dvc, next_vpa);
4335 /*
4336 * insert stopper carrier to terminate list
4337 */
4338 carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4339
4340 return carrp;
4341 }
4342
4343 /*
4344 * 'offset' is the index in the request pointer array
4345 */
4346 static adv_req_t * adv_get_reqp(struct adv_dvc_var *adv_dvc, u32 offset)
4347 {
4348 struct asc_board *boardp = adv_dvc->drv_ptr;
4349
4350 BUG_ON(offset > adv_dvc->max_host_qng);
4351 return &boardp->adv_reqp[offset];
4352 }
4353
4354 /*
4355 * Send an idle command to the chip and wait for completion.
4356 *
4357 * Command completion is polled for once per microsecond.
4358 *
4359 * The function can be called from anywhere including an interrupt handler.
4360 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4361 * functions to prevent reentrancy.
4362 *
4363 * Return Values:
4364 * ADV_TRUE - command completed successfully
4365 * ADV_FALSE - command failed
4366 * ADV_ERROR - command timed out
4367 */
4368 static int
4369 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4370 ushort idle_cmd, u32 idle_cmd_parameter)
4371 {
4372 int result, i, j;
4373 AdvPortAddr iop_base;
4374
4375 iop_base = asc_dvc->iop_base;
4376
4377 /*
4378 * Clear the idle command status which is set by the microcode
4379 * to a non-zero value to indicate when the command is completed.
4380 * The non-zero result is one of the IDLE_CMD_STATUS_* values
4381 */
4382 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4383
4384 /*
4385 * Write the idle command value after the idle command parameter
4386 * has been written to avoid a race condition. If the order is not
4387 * followed, the microcode may process the idle command before the
4388 * parameters have been written to LRAM.
4389 */
4390 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4391 cpu_to_le32(idle_cmd_parameter));
4392 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4393
4394 /*
4395 * Tickle the RISC to tell it to process the idle command.
4396 */
4397 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4398 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4399 /*
4400 * Clear the tickle value. In the ASC-3550 the RISC flag
4401 * command 'clr_tickle_b' does not work unless the host
4402 * value is cleared.
4403 */
4404 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4405 }
4406
4407 /* Wait for up to 100 millisecond for the idle command to timeout. */
4408 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4409 /* Poll once each microsecond for command completion. */
4410 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4411 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4412 result);
4413 if (result != 0)
4414 return result;
4415 udelay(1);
4416 }
4417 }
4418
4419 BUG(); /* The idle command should never timeout. */
4420 return ADV_ERROR;
4421 }
4422
4423 /*
4424 * Reset SCSI Bus and purge all outstanding requests.
4425 *
4426 * Return Value:
4427 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
4428 * ADV_FALSE(0) - Microcode command failed.
4429 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4430 * may be hung which requires driver recovery.
4431 */
4432 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4433 {
4434 int status;
4435
4436 /*
4437 * Send the SCSI Bus Reset idle start idle command which asserts
4438 * the SCSI Bus Reset signal.
4439 */
4440 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4441 if (status != ADV_TRUE) {
4442 return status;
4443 }
4444
4445 /*
4446 * Delay for the specified SCSI Bus Reset hold time.
4447 *
4448 * The hold time delay is done on the host because the RISC has no
4449 * microsecond accurate timer.
4450 */
4451 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4452
4453 /*
4454 * Send the SCSI Bus Reset end idle command which de-asserts
4455 * the SCSI Bus Reset signal and purges any pending requests.
4456 */
4457 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4458 if (status != ADV_TRUE) {
4459 return status;
4460 }
4461
4462 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4463
4464 return status;
4465 }
4466
4467 /*
4468 * Initialize the ASC-3550.
4469 *
4470 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4471 *
4472 * For a non-fatal error return a warning code. If there are no warnings
4473 * then 0 is returned.
4474 *
4475 * Needed after initialization for error recovery.
4476 */
4477 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4478 {
4479 const struct firmware *fw;
4480 const char fwname[] = "advansys/3550.bin";
4481 AdvPortAddr iop_base;
4482 ushort warn_code;
4483 int begin_addr;
4484 int end_addr;
4485 ushort code_sum;
4486 int word;
4487 int i;
4488 int err;
4489 unsigned long chksum;
4490 ushort scsi_cfg1;
4491 uchar tid;
4492 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4493 ushort wdtr_able = 0, sdtr_able, tagqng_able;
4494 uchar max_cmd[ADV_MAX_TID + 1];
4495
4496 /* If there is already an error, don't continue. */
4497 if (asc_dvc->err_code != 0)
4498 return ADV_ERROR;
4499
4500 /*
4501 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4502 */
4503 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4504 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4505 return ADV_ERROR;
4506 }
4507
4508 warn_code = 0;
4509 iop_base = asc_dvc->iop_base;
4510
4511 /*
4512 * Save the RISC memory BIOS region before writing the microcode.
4513 * The BIOS may already be loaded and using its RISC LRAM region
4514 * so its region must be saved and restored.
4515 *
4516 * Note: This code makes the assumption, which is currently true,
4517 * that a chip reset does not clear RISC LRAM.
4518 */
4519 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4520 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4521 bios_mem[i]);
4522 }
4523
4524 /*
4525 * Save current per TID negotiated values.
4526 */
4527 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
4528 ushort bios_version, major, minor;
4529
4530 bios_version =
4531 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
4532 major = (bios_version >> 12) & 0xF;
4533 minor = (bios_version >> 8) & 0xF;
4534 if (major < 3 || (major == 3 && minor == 1)) {
4535 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
4536 AdvReadWordLram(iop_base, 0x120, wdtr_able);
4537 } else {
4538 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4539 }
4540 }
4541 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4542 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4543 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4544 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4545 max_cmd[tid]);
4546 }
4547
4548 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4549 if (err) {
4550 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4551 fwname, err);
4552 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4553 return err;
4554 }
4555 if (fw->size < 4) {
4556 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4557 fw->size, fwname);
4558 release_firmware(fw);
4559 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4560 return -EINVAL;
4561 }
4562 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4563 (fw->data[1] << 8) | fw->data[0];
4564 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4565 fw->size - 4, ADV_3550_MEMSIZE,
4566 chksum);
4567 release_firmware(fw);
4568 if (asc_dvc->err_code)
4569 return ADV_ERROR;
4570
4571 /*
4572 * Restore the RISC memory BIOS region.
4573 */
4574 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4575 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4576 bios_mem[i]);
4577 }
4578
4579 /*
4580 * Calculate and write the microcode code checksum to the microcode
4581 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4582 */
4583 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4584 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4585 code_sum = 0;
4586 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4587 for (word = begin_addr; word < end_addr; word += 2) {
4588 code_sum += AdvReadWordAutoIncLram(iop_base);
4589 }
4590 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4591
4592 /*
4593 * Read and save microcode version and date.
4594 */
4595 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4596 asc_dvc->cfg->mcode_date);
4597 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4598 asc_dvc->cfg->mcode_version);
4599
4600 /*
4601 * Set the chip type to indicate the ASC3550.
4602 */
4603 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
4604
4605 /*
4606 * If the PCI Configuration Command Register "Parity Error Response
4607 * Control" Bit was clear (0), then set the microcode variable
4608 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4609 * to ignore DMA parity errors.
4610 */
4611 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4612 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4613 word |= CONTROL_FLAG_IGNORE_PERR;
4614 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4615 }
4616
4617 /*
4618 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
4619 * threshold of 128 bytes. This register is only accessible to the host.
4620 */
4621 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
4622 START_CTL_EMFU | READ_CMD_MRM);
4623
4624 /*
4625 * Microcode operating variables for WDTR, SDTR, and command tag
4626 * queuing will be set in slave_configure() based on what a
4627 * device reports it is capable of in Inquiry byte 7.
4628 *
4629 * If SCSI Bus Resets have been disabled, then directly set
4630 * SDTR and WDTR from the EEPROM configuration. This will allow
4631 * the BIOS and warm boot to work without a SCSI bus hang on
4632 * the Inquiry caused by host and target mismatched DTR values.
4633 * Without the SCSI Bus Reset, before an Inquiry a device can't
4634 * be assumed to be in Asynchronous, Narrow mode.
4635 */
4636 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
4637 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
4638 asc_dvc->wdtr_able);
4639 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
4640 asc_dvc->sdtr_able);
4641 }
4642
4643 /*
4644 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
4645 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
4646 * bitmask. These values determine the maximum SDTR speed negotiated
4647 * with a device.
4648 *
4649 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
4650 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
4651 * without determining here whether the device supports SDTR.
4652 *
4653 * 4-bit speed SDTR speed name
4654 * =========== ===============
4655 * 0000b (0x0) SDTR disabled
4656 * 0001b (0x1) 5 Mhz
4657 * 0010b (0x2) 10 Mhz
4658 * 0011b (0x3) 20 Mhz (Ultra)
4659 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
4660 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
4661 * 0110b (0x6) Undefined
4662 * .
4663 * 1111b (0xF) Undefined
4664 */
4665 word = 0;
4666 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4667 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
4668 /* Set Ultra speed for TID 'tid'. */
4669 word |= (0x3 << (4 * (tid % 4)));
4670 } else {
4671 /* Set Fast speed for TID 'tid'. */
4672 word |= (0x2 << (4 * (tid % 4)));
4673 }
4674 if (tid == 3) { /* Check if done with sdtr_speed1. */
4675 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
4676 word = 0;
4677 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
4678 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
4679 word = 0;
4680 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
4681 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
4682 word = 0;
4683 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
4684 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
4685 /* End of loop. */
4686 }
4687 }
4688
4689 /*
4690 * Set microcode operating variable for the disconnect per TID bitmask.
4691 */
4692 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
4693 asc_dvc->cfg->disc_enable);
4694
4695 /*
4696 * Set SCSI_CFG0 Microcode Default Value.
4697 *
4698 * The microcode will set the SCSI_CFG0 register using this value
4699 * after it is started below.
4700 */
4701 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
4702 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
4703 asc_dvc->chip_scsi_id);
4704
4705 /*
4706 * Determine SCSI_CFG1 Microcode Default Value.
4707 *
4708 * The microcode will set the SCSI_CFG1 register using this value
4709 * after it is started below.
4710 */
4711
4712 /* Read current SCSI_CFG1 Register value. */
4713 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4714
4715 /*
4716 * If all three connectors are in use, return an error.
4717 */
4718 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
4719 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
4720 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
4721 return ADV_ERROR;
4722 }
4723
4724 /*
4725 * If the internal narrow cable is reversed all of the SCSI_CTRL
4726 * register signals will be set. Check for and return an error if
4727 * this condition is found.
4728 */
4729 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
4730 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
4731 return ADV_ERROR;
4732 }
4733
4734 /*
4735 * If this is a differential board and a single-ended device
4736 * is attached to one of the connectors, return an error.
4737 */
4738 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
4739 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
4740 return ADV_ERROR;
4741 }
4742
4743 /*
4744 * If automatic termination control is enabled, then set the
4745 * termination value based on a table listed in a_condor.h.
4746 *
4747 * If manual termination was specified with an EEPROM setting
4748 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
4749 * is ready to be 'ored' into SCSI_CFG1.
4750 */
4751 if (asc_dvc->cfg->termination == 0) {
4752 /*
4753 * The software always controls termination by setting TERM_CTL_SEL.
4754 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
4755 */
4756 asc_dvc->cfg->termination |= TERM_CTL_SEL;
4757
4758 switch (scsi_cfg1 & CABLE_DETECT) {
4759 /* TERM_CTL_H: on, TERM_CTL_L: on */
4760 case 0x3:
4761 case 0x7:
4762 case 0xB:
4763 case 0xD:
4764 case 0xE:
4765 case 0xF:
4766 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
4767 break;
4768
4769 /* TERM_CTL_H: on, TERM_CTL_L: off */
4770 case 0x1:
4771 case 0x5:
4772 case 0x9:
4773 case 0xA:
4774 case 0xC:
4775 asc_dvc->cfg->termination |= TERM_CTL_H;
4776 break;
4777
4778 /* TERM_CTL_H: off, TERM_CTL_L: off */
4779 case 0x2:
4780 case 0x6:
4781 break;
4782 }
4783 }
4784
4785 /*
4786 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
4787 */
4788 scsi_cfg1 &= ~TERM_CTL;
4789
4790 /*
4791 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
4792 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
4793 * referenced, because the hardware internally inverts
4794 * the Termination High and Low bits if TERM_POL is set.
4795 */
4796 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
4797
4798 /*
4799 * Set SCSI_CFG1 Microcode Default Value
4800 *
4801 * Set filter value and possibly modified termination control
4802 * bits in the Microcode SCSI_CFG1 Register Value.
4803 *
4804 * The microcode will set the SCSI_CFG1 register using this value
4805 * after it is started below.
4806 */
4807 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
4808 FLTR_DISABLE | scsi_cfg1);
4809
4810 /*
4811 * Set MEM_CFG Microcode Default Value
4812 *
4813 * The microcode will set the MEM_CFG register using this value
4814 * after it is started below.
4815 *
4816 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4817 * are defined.
4818 *
4819 * ASC-3550 has 8KB internal memory.
4820 */
4821 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
4822 BIOS_EN | RAM_SZ_8KB);
4823
4824 /*
4825 * Set SEL_MASK Microcode Default Value
4826 *
4827 * The microcode will set the SEL_MASK register using this value
4828 * after it is started below.
4829 */
4830 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
4831 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
4832
4833 AdvBuildCarrierFreelist(asc_dvc);
4834
4835 /*
4836 * Set-up the Host->RISC Initiator Command Queue (ICQ).
4837 */
4838
4839 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
4840 if (!asc_dvc->icq_sp) {
4841 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4842 return ADV_ERROR;
4843 }
4844
4845 /*
4846 * Set RISC ICQ physical address start value.
4847 */
4848 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
4849
4850 /*
4851 * Set-up the RISC->Host Initiator Response Queue (IRQ).
4852 */
4853 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
4854 if (!asc_dvc->irq_sp) {
4855 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4856 return ADV_ERROR;
4857 }
4858
4859 /*
4860 * Set RISC IRQ physical address start value.
4861 */
4862 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
4863 asc_dvc->carr_pending_cnt = 0;
4864
4865 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
4866 (ADV_INTR_ENABLE_HOST_INTR |
4867 ADV_INTR_ENABLE_GLOBAL_INTR));
4868
4869 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
4870 AdvWriteWordRegister(iop_base, IOPW_PC, word);
4871
4872 /* finally, finally, gentlemen, start your engine */
4873 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
4874
4875 /*
4876 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
4877 * Resets should be performed. The RISC has to be running
4878 * to issue a SCSI Bus Reset.
4879 */
4880 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
4881 /*
4882 * If the BIOS Signature is present in memory, restore the
4883 * BIOS Handshake Configuration Table and do not perform
4884 * a SCSI Bus Reset.
4885 */
4886 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
4887 0x55AA) {
4888 /*
4889 * Restore per TID negotiated values.
4890 */
4891 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4892 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4893 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
4894 tagqng_able);
4895 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4896 AdvWriteByteLram(iop_base,
4897 ASC_MC_NUMBER_OF_MAX_CMD + tid,
4898 max_cmd[tid]);
4899 }
4900 } else {
4901 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
4902 warn_code = ASC_WARN_BUSRESET_ERROR;
4903 }
4904 }
4905 }
4906
4907 return warn_code;
4908 }
4909
4910 /*
4911 * Initialize the ASC-38C0800.
4912 *
4913 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4914 *
4915 * For a non-fatal error return a warning code. If there are no warnings
4916 * then 0 is returned.
4917 *
4918 * Needed after initialization for error recovery.
4919 */
4920 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
4921 {
4922 const struct firmware *fw;
4923 const char fwname[] = "advansys/38C0800.bin";
4924 AdvPortAddr iop_base;
4925 ushort warn_code;
4926 int begin_addr;
4927 int end_addr;
4928 ushort code_sum;
4929 int word;
4930 int i;
4931 int err;
4932 unsigned long chksum;
4933 ushort scsi_cfg1;
4934 uchar byte;
4935 uchar tid;
4936 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4937 ushort wdtr_able, sdtr_able, tagqng_able;
4938 uchar max_cmd[ADV_MAX_TID + 1];
4939
4940 /* If there is already an error, don't continue. */
4941 if (asc_dvc->err_code != 0)
4942 return ADV_ERROR;
4943
4944 /*
4945 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
4946 */
4947 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
4948 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4949 return ADV_ERROR;
4950 }
4951
4952 warn_code = 0;
4953 iop_base = asc_dvc->iop_base;
4954
4955 /*
4956 * Save the RISC memory BIOS region before writing the microcode.
4957 * The BIOS may already be loaded and using its RISC LRAM region
4958 * so its region must be saved and restored.
4959 *
4960 * Note: This code makes the assumption, which is currently true,
4961 * that a chip reset does not clear RISC LRAM.
4962 */
4963 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4964 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4965 bios_mem[i]);
4966 }
4967
4968 /*
4969 * Save current per TID negotiated values.
4970 */
4971 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4972 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4973 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4974 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4975 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4976 max_cmd[tid]);
4977 }
4978
4979 /*
4980 * RAM BIST (RAM Built-In Self Test)
4981 *
4982 * Address : I/O base + offset 0x38h register (byte).
4983 * Function: Bit 7-6(RW) : RAM mode
4984 * Normal Mode : 0x00
4985 * Pre-test Mode : 0x40
4986 * RAM Test Mode : 0x80
4987 * Bit 5 : unused
4988 * Bit 4(RO) : Done bit
4989 * Bit 3-0(RO) : Status
4990 * Host Error : 0x08
4991 * Int_RAM Error : 0x04
4992 * RISC Error : 0x02
4993 * SCSI Error : 0x01
4994 * No Error : 0x00
4995 *
4996 * Note: RAM BIST code should be put right here, before loading the
4997 * microcode and after saving the RISC memory BIOS region.
4998 */
4999
5000 /*
5001 * LRAM Pre-test
5002 *
5003 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5004 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5005 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5006 * to NORMAL_MODE, return an error too.
5007 */
5008 for (i = 0; i < 2; i++) {
5009 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5010 mdelay(10); /* Wait for 10ms before reading back. */
5011 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5012 if ((byte & RAM_TEST_DONE) == 0
5013 || (byte & 0x0F) != PRE_TEST_VALUE) {
5014 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5015 return ADV_ERROR;
5016 }
5017
5018 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5019 mdelay(10); /* Wait for 10ms before reading back. */
5020 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5021 != NORMAL_VALUE) {
5022 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5023 return ADV_ERROR;
5024 }
5025 }
5026
5027 /*
5028 * LRAM Test - It takes about 1.5 ms to run through the test.
5029 *
5030 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5031 * If Done bit not set or Status not 0, save register byte, set the
5032 * err_code, and return an error.
5033 */
5034 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5035 mdelay(10); /* Wait for 10ms before checking status. */
5036
5037 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5038 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5039 /* Get here if Done bit not set or Status not 0. */
5040 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5041 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5042 return ADV_ERROR;
5043 }
5044
5045 /* We need to reset back to normal mode after LRAM test passes. */
5046 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5047
5048 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5049 if (err) {
5050 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5051 fwname, err);
5052 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5053 return err;
5054 }
5055 if (fw->size < 4) {
5056 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5057 fw->size, fwname);
5058 release_firmware(fw);
5059 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5060 return -EINVAL;
5061 }
5062 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5063 (fw->data[1] << 8) | fw->data[0];
5064 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5065 fw->size - 4, ADV_38C0800_MEMSIZE,
5066 chksum);
5067 release_firmware(fw);
5068 if (asc_dvc->err_code)
5069 return ADV_ERROR;
5070
5071 /*
5072 * Restore the RISC memory BIOS region.
5073 */
5074 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5075 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5076 bios_mem[i]);
5077 }
5078
5079 /*
5080 * Calculate and write the microcode code checksum to the microcode
5081 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5082 */
5083 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5084 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5085 code_sum = 0;
5086 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5087 for (word = begin_addr; word < end_addr; word += 2) {
5088 code_sum += AdvReadWordAutoIncLram(iop_base);
5089 }
5090 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5091
5092 /*
5093 * Read microcode version and date.
5094 */
5095 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5096 asc_dvc->cfg->mcode_date);
5097 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5098 asc_dvc->cfg->mcode_version);
5099
5100 /*
5101 * Set the chip type to indicate the ASC38C0800.
5102 */
5103 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
5104
5105 /*
5106 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5107 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5108 * cable detection and then we are able to read C_DET[3:0].
5109 *
5110 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5111 * Microcode Default Value' section below.
5112 */
5113 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5114 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5115 scsi_cfg1 | DIS_TERM_DRV);
5116
5117 /*
5118 * If the PCI Configuration Command Register "Parity Error Response
5119 * Control" Bit was clear (0), then set the microcode variable
5120 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5121 * to ignore DMA parity errors.
5122 */
5123 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5124 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5125 word |= CONTROL_FLAG_IGNORE_PERR;
5126 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5127 }
5128
5129 /*
5130 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
5131 * bits for the default FIFO threshold.
5132 *
5133 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
5134 *
5135 * For DMA Errata #4 set the BC_THRESH_ENB bit.
5136 */
5137 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5138 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
5139 READ_CMD_MRM);
5140
5141 /*
5142 * Microcode operating variables for WDTR, SDTR, and command tag
5143 * queuing will be set in slave_configure() based on what a
5144 * device reports it is capable of in Inquiry byte 7.
5145 *
5146 * If SCSI Bus Resets have been disabled, then directly set
5147 * SDTR and WDTR from the EEPROM configuration. This will allow
5148 * the BIOS and warm boot to work without a SCSI bus hang on
5149 * the Inquiry caused by host and target mismatched DTR values.
5150 * Without the SCSI Bus Reset, before an Inquiry a device can't
5151 * be assumed to be in Asynchronous, Narrow mode.
5152 */
5153 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5154 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5155 asc_dvc->wdtr_able);
5156 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5157 asc_dvc->sdtr_able);
5158 }
5159
5160 /*
5161 * Set microcode operating variables for DISC and SDTR_SPEED1,
5162 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5163 * configuration values.
5164 *
5165 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5166 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5167 * without determining here whether the device supports SDTR.
5168 */
5169 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5170 asc_dvc->cfg->disc_enable);
5171 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5172 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5173 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5174 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5175
5176 /*
5177 * Set SCSI_CFG0 Microcode Default Value.
5178 *
5179 * The microcode will set the SCSI_CFG0 register using this value
5180 * after it is started below.
5181 */
5182 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5183 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5184 asc_dvc->chip_scsi_id);
5185
5186 /*
5187 * Determine SCSI_CFG1 Microcode Default Value.
5188 *
5189 * The microcode will set the SCSI_CFG1 register using this value
5190 * after it is started below.
5191 */
5192
5193 /* Read current SCSI_CFG1 Register value. */
5194 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5195
5196 /*
5197 * If the internal narrow cable is reversed all of the SCSI_CTRL
5198 * register signals will be set. Check for and return an error if
5199 * this condition is found.
5200 */
5201 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5202 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5203 return ADV_ERROR;
5204 }
5205
5206 /*
5207 * All kind of combinations of devices attached to one of four
5208 * connectors are acceptable except HVD device attached. For example,
5209 * LVD device can be attached to SE connector while SE device attached
5210 * to LVD connector. If LVD device attached to SE connector, it only
5211 * runs up to Ultra speed.
5212 *
5213 * If an HVD device is attached to one of LVD connectors, return an
5214 * error. However, there is no way to detect HVD device attached to
5215 * SE connectors.
5216 */
5217 if (scsi_cfg1 & HVD) {
5218 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
5219 return ADV_ERROR;
5220 }
5221
5222 /*
5223 * If either SE or LVD automatic termination control is enabled, then
5224 * set the termination value based on a table listed in a_condor.h.
5225 *
5226 * If manual termination was specified with an EEPROM setting then
5227 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
5228 * to be 'ored' into SCSI_CFG1.
5229 */
5230 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5231 /* SE automatic termination control is enabled. */
5232 switch (scsi_cfg1 & C_DET_SE) {
5233 /* TERM_SE_HI: on, TERM_SE_LO: on */
5234 case 0x1:
5235 case 0x2:
5236 case 0x3:
5237 asc_dvc->cfg->termination |= TERM_SE;
5238 break;
5239
5240 /* TERM_SE_HI: on, TERM_SE_LO: off */
5241 case 0x0:
5242 asc_dvc->cfg->termination |= TERM_SE_HI;
5243 break;
5244 }
5245 }
5246
5247 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
5248 /* LVD automatic termination control is enabled. */
5249 switch (scsi_cfg1 & C_DET_LVD) {
5250 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
5251 case 0x4:
5252 case 0x8:
5253 case 0xC:
5254 asc_dvc->cfg->termination |= TERM_LVD;
5255 break;
5256
5257 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
5258 case 0x0:
5259 break;
5260 }
5261 }
5262
5263 /*
5264 * Clear any set TERM_SE and TERM_LVD bits.
5265 */
5266 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
5267
5268 /*
5269 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
5270 */
5271 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
5272
5273 /*
5274 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
5275 * bits and set possibly modified termination control bits in the
5276 * Microcode SCSI_CFG1 Register Value.
5277 */
5278 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
5279
5280 /*
5281 * Set SCSI_CFG1 Microcode Default Value
5282 *
5283 * Set possibly modified termination control and reset DIS_TERM_DRV
5284 * bits in the Microcode SCSI_CFG1 Register Value.
5285 *
5286 * The microcode will set the SCSI_CFG1 register using this value
5287 * after it is started below.
5288 */
5289 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5290
5291 /*
5292 * Set MEM_CFG Microcode Default Value
5293 *
5294 * The microcode will set the MEM_CFG register using this value
5295 * after it is started below.
5296 *
5297 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5298 * are defined.
5299 *
5300 * ASC-38C0800 has 16KB internal memory.
5301 */
5302 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5303 BIOS_EN | RAM_SZ_16KB);
5304
5305 /*
5306 * Set SEL_MASK Microcode Default Value
5307 *
5308 * The microcode will set the SEL_MASK register using this value
5309 * after it is started below.
5310 */
5311 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5312 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5313
5314 AdvBuildCarrierFreelist(asc_dvc);
5315
5316 /*
5317 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5318 */
5319
5320 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5321 if (!asc_dvc->icq_sp) {
5322 ASC_DBG(0, "Failed to get ICQ carrier\n");
5323 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5324 return ADV_ERROR;
5325 }
5326
5327 /*
5328 * Set RISC ICQ physical address start value.
5329 * carr_pa is LE, must be native before write
5330 */
5331 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5332
5333 /*
5334 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5335 */
5336 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5337 if (!asc_dvc->irq_sp) {
5338 ASC_DBG(0, "Failed to get IRQ carrier\n");
5339 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5340 return ADV_ERROR;
5341 }
5342
5343 /*
5344 * Set RISC IRQ physical address start value.
5345 *
5346 * carr_pa is LE, must be native before write *
5347 */
5348 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5349 asc_dvc->carr_pending_cnt = 0;
5350
5351 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5352 (ADV_INTR_ENABLE_HOST_INTR |
5353 ADV_INTR_ENABLE_GLOBAL_INTR));
5354
5355 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5356 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5357
5358 /* finally, finally, gentlemen, start your engine */
5359 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5360
5361 /*
5362 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5363 * Resets should be performed. The RISC has to be running
5364 * to issue a SCSI Bus Reset.
5365 */
5366 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5367 /*
5368 * If the BIOS Signature is present in memory, restore the
5369 * BIOS Handshake Configuration Table and do not perform
5370 * a SCSI Bus Reset.
5371 */
5372 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5373 0x55AA) {
5374 /*
5375 * Restore per TID negotiated values.
5376 */
5377 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5378 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5379 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5380 tagqng_able);
5381 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5382 AdvWriteByteLram(iop_base,
5383 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5384 max_cmd[tid]);
5385 }
5386 } else {
5387 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5388 warn_code = ASC_WARN_BUSRESET_ERROR;
5389 }
5390 }
5391 }
5392
5393 return warn_code;
5394 }
5395
5396 /*
5397 * Initialize the ASC-38C1600.
5398 *
5399 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
5400 *
5401 * For a non-fatal error return a warning code. If there are no warnings
5402 * then 0 is returned.
5403 *
5404 * Needed after initialization for error recovery.
5405 */
5406 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
5407 {
5408 const struct firmware *fw;
5409 const char fwname[] = "advansys/38C1600.bin";
5410 AdvPortAddr iop_base;
5411 ushort warn_code;
5412 int begin_addr;
5413 int end_addr;
5414 ushort code_sum;
5415 long word;
5416 int i;
5417 int err;
5418 unsigned long chksum;
5419 ushort scsi_cfg1;
5420 uchar byte;
5421 uchar tid;
5422 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
5423 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
5424 uchar max_cmd[ASC_MAX_TID + 1];
5425
5426 /* If there is already an error, don't continue. */
5427 if (asc_dvc->err_code != 0) {
5428 return ADV_ERROR;
5429 }
5430
5431 /*
5432 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
5433 */
5434 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
5435 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5436 return ADV_ERROR;
5437 }
5438
5439 warn_code = 0;
5440 iop_base = asc_dvc->iop_base;
5441
5442 /*
5443 * Save the RISC memory BIOS region before writing the microcode.
5444 * The BIOS may already be loaded and using its RISC LRAM region
5445 * so its region must be saved and restored.
5446 *
5447 * Note: This code makes the assumption, which is currently true,
5448 * that a chip reset does not clear RISC LRAM.
5449 */
5450 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5451 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5452 bios_mem[i]);
5453 }
5454
5455 /*
5456 * Save current per TID negotiated values.
5457 */
5458 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5459 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5460 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5461 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5462 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5463 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5464 max_cmd[tid]);
5465 }
5466
5467 /*
5468 * RAM BIST (Built-In Self Test)
5469 *
5470 * Address : I/O base + offset 0x38h register (byte).
5471 * Function: Bit 7-6(RW) : RAM mode
5472 * Normal Mode : 0x00
5473 * Pre-test Mode : 0x40
5474 * RAM Test Mode : 0x80
5475 * Bit 5 : unused
5476 * Bit 4(RO) : Done bit
5477 * Bit 3-0(RO) : Status
5478 * Host Error : 0x08
5479 * Int_RAM Error : 0x04
5480 * RISC Error : 0x02
5481 * SCSI Error : 0x01
5482 * No Error : 0x00
5483 *
5484 * Note: RAM BIST code should be put right here, before loading the
5485 * microcode and after saving the RISC memory BIOS region.
5486 */
5487
5488 /*
5489 * LRAM Pre-test
5490 *
5491 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5492 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5493 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5494 * to NORMAL_MODE, return an error too.
5495 */
5496 for (i = 0; i < 2; i++) {
5497 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5498 mdelay(10); /* Wait for 10ms before reading back. */
5499 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5500 if ((byte & RAM_TEST_DONE) == 0
5501 || (byte & 0x0F) != PRE_TEST_VALUE) {
5502 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5503 return ADV_ERROR;
5504 }
5505
5506 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5507 mdelay(10); /* Wait for 10ms before reading back. */
5508 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5509 != NORMAL_VALUE) {
5510 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5511 return ADV_ERROR;
5512 }
5513 }
5514
5515 /*
5516 * LRAM Test - It takes about 1.5 ms to run through the test.
5517 *
5518 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5519 * If Done bit not set or Status not 0, save register byte, set the
5520 * err_code, and return an error.
5521 */
5522 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5523 mdelay(10); /* Wait for 10ms before checking status. */
5524
5525 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5526 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5527 /* Get here if Done bit not set or Status not 0. */
5528 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5529 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5530 return ADV_ERROR;
5531 }
5532
5533 /* We need to reset back to normal mode after LRAM test passes. */
5534 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5535
5536 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5537 if (err) {
5538 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5539 fwname, err);
5540 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5541 return err;
5542 }
5543 if (fw->size < 4) {
5544 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5545 fw->size, fwname);
5546 release_firmware(fw);
5547 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5548 return -EINVAL;
5549 }
5550 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5551 (fw->data[1] << 8) | fw->data[0];
5552 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5553 fw->size - 4, ADV_38C1600_MEMSIZE,
5554 chksum);
5555 release_firmware(fw);
5556 if (asc_dvc->err_code)
5557 return ADV_ERROR;
5558
5559 /*
5560 * Restore the RISC memory BIOS region.
5561 */
5562 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5563 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5564 bios_mem[i]);
5565 }
5566
5567 /*
5568 * Calculate and write the microcode code checksum to the microcode
5569 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5570 */
5571 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5572 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5573 code_sum = 0;
5574 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5575 for (word = begin_addr; word < end_addr; word += 2) {
5576 code_sum += AdvReadWordAutoIncLram(iop_base);
5577 }
5578 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5579
5580 /*
5581 * Read microcode version and date.
5582 */
5583 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5584 asc_dvc->cfg->mcode_date);
5585 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5586 asc_dvc->cfg->mcode_version);
5587
5588 /*
5589 * Set the chip type to indicate the ASC38C1600.
5590 */
5591 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
5592
5593 /*
5594 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5595 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5596 * cable detection and then we are able to read C_DET[3:0].
5597 *
5598 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5599 * Microcode Default Value' section below.
5600 */
5601 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5602 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5603 scsi_cfg1 | DIS_TERM_DRV);
5604
5605 /*
5606 * If the PCI Configuration Command Register "Parity Error Response
5607 * Control" Bit was clear (0), then set the microcode variable
5608 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5609 * to ignore DMA parity errors.
5610 */
5611 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5612 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5613 word |= CONTROL_FLAG_IGNORE_PERR;
5614 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5615 }
5616
5617 /*
5618 * If the BIOS control flag AIPP (Asynchronous Information
5619 * Phase Protection) disable bit is not set, then set the firmware
5620 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
5621 * AIPP checking and encoding.
5622 */
5623 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
5624 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5625 word |= CONTROL_FLAG_ENABLE_AIPP;
5626 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5627 }
5628
5629 /*
5630 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
5631 * and START_CTL_TH [3:2].
5632 */
5633 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5634 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
5635
5636 /*
5637 * Microcode operating variables for WDTR, SDTR, and command tag
5638 * queuing will be set in slave_configure() based on what a
5639 * device reports it is capable of in Inquiry byte 7.
5640 *
5641 * If SCSI Bus Resets have been disabled, then directly set
5642 * SDTR and WDTR from the EEPROM configuration. This will allow
5643 * the BIOS and warm boot to work without a SCSI bus hang on
5644 * the Inquiry caused by host and target mismatched DTR values.
5645 * Without the SCSI Bus Reset, before an Inquiry a device can't
5646 * be assumed to be in Asynchronous, Narrow mode.
5647 */
5648 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5649 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5650 asc_dvc->wdtr_able);
5651 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5652 asc_dvc->sdtr_able);
5653 }
5654
5655 /*
5656 * Set microcode operating variables for DISC and SDTR_SPEED1,
5657 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5658 * configuration values.
5659 *
5660 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5661 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5662 * without determining here whether the device supports SDTR.
5663 */
5664 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5665 asc_dvc->cfg->disc_enable);
5666 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5667 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5668 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5669 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5670
5671 /*
5672 * Set SCSI_CFG0 Microcode Default Value.
5673 *
5674 * The microcode will set the SCSI_CFG0 register using this value
5675 * after it is started below.
5676 */
5677 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5678 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5679 asc_dvc->chip_scsi_id);
5680
5681 /*
5682 * Calculate SCSI_CFG1 Microcode Default Value.
5683 *
5684 * The microcode will set the SCSI_CFG1 register using this value
5685 * after it is started below.
5686 *
5687 * Each ASC-38C1600 function has only two cable detect bits.
5688 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
5689 */
5690 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5691
5692 /*
5693 * If the cable is reversed all of the SCSI_CTRL register signals
5694 * will be set. Check for and return an error if this condition is
5695 * found.
5696 */
5697 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5698 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5699 return ADV_ERROR;
5700 }
5701
5702 /*
5703 * Each ASC-38C1600 function has two connectors. Only an HVD device
5704 * can not be connected to either connector. An LVD device or SE device
5705 * may be connected to either connecor. If an SE device is connected,
5706 * then at most Ultra speed (20 Mhz) can be used on both connectors.
5707 *
5708 * If an HVD device is attached, return an error.
5709 */
5710 if (scsi_cfg1 & HVD) {
5711 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
5712 return ADV_ERROR;
5713 }
5714
5715 /*
5716 * Each function in the ASC-38C1600 uses only the SE cable detect and
5717 * termination because there are two connectors for each function. Each
5718 * function may use either LVD or SE mode. Corresponding the SE automatic
5719 * termination control EEPROM bits are used for each function. Each
5720 * function has its own EEPROM. If SE automatic control is enabled for
5721 * the function, then set the termination value based on a table listed
5722 * in a_condor.h.
5723 *
5724 * If manual termination is specified in the EEPROM for the function,
5725 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
5726 * ready to be 'ored' into SCSI_CFG1.
5727 */
5728 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5729 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
5730 /* SE automatic termination control is enabled. */
5731 switch (scsi_cfg1 & C_DET_SE) {
5732 /* TERM_SE_HI: on, TERM_SE_LO: on */
5733 case 0x1:
5734 case 0x2:
5735 case 0x3:
5736 asc_dvc->cfg->termination |= TERM_SE;
5737 break;
5738
5739 case 0x0:
5740 if (PCI_FUNC(pdev->devfn) == 0) {
5741 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
5742 } else {
5743 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
5744 asc_dvc->cfg->termination |= TERM_SE_HI;
5745 }
5746 break;
5747 }
5748 }
5749
5750 /*
5751 * Clear any set TERM_SE bits.
5752 */
5753 scsi_cfg1 &= ~TERM_SE;
5754
5755 /*
5756 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
5757 */
5758 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
5759
5760 /*
5761 * Clear Big Endian and Terminator Polarity bits and set possibly
5762 * modified termination control bits in the Microcode SCSI_CFG1
5763 * Register Value.
5764 *
5765 * Big Endian bit is not used even on big endian machines.
5766 */
5767 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
5768
5769 /*
5770 * Set SCSI_CFG1 Microcode Default Value
5771 *
5772 * Set possibly modified termination control bits in the Microcode
5773 * SCSI_CFG1 Register Value.
5774 *
5775 * The microcode will set the SCSI_CFG1 register using this value
5776 * after it is started below.
5777 */
5778 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5779
5780 /*
5781 * Set MEM_CFG Microcode Default Value
5782 *
5783 * The microcode will set the MEM_CFG register using this value
5784 * after it is started below.
5785 *
5786 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5787 * are defined.
5788 *
5789 * ASC-38C1600 has 32KB internal memory.
5790 *
5791 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
5792 * out a special 16K Adv Library and Microcode version. After the issue
5793 * resolved, we should turn back to the 32K support. Both a_condor.h and
5794 * mcode.sas files also need to be updated.
5795 *
5796 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5797 * BIOS_EN | RAM_SZ_32KB);
5798 */
5799 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5800 BIOS_EN | RAM_SZ_16KB);
5801
5802 /*
5803 * Set SEL_MASK Microcode Default Value
5804 *
5805 * The microcode will set the SEL_MASK register using this value
5806 * after it is started below.
5807 */
5808 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5809 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5810
5811 AdvBuildCarrierFreelist(asc_dvc);
5812
5813 /*
5814 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5815 */
5816 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5817 if (!asc_dvc->icq_sp) {
5818 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5819 return ADV_ERROR;
5820 }
5821
5822 /*
5823 * Set RISC ICQ physical address start value. Initialize the
5824 * COMMA register to the same value otherwise the RISC will
5825 * prematurely detect a command is available.
5826 */
5827 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5828 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
5829 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
5830
5831 /*
5832 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5833 */
5834 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5835 if (!asc_dvc->irq_sp) {
5836 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5837 return ADV_ERROR;
5838 }
5839
5840 /*
5841 * Set RISC IRQ physical address start value.
5842 */
5843 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5844 asc_dvc->carr_pending_cnt = 0;
5845
5846 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5847 (ADV_INTR_ENABLE_HOST_INTR |
5848 ADV_INTR_ENABLE_GLOBAL_INTR));
5849 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5850 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5851
5852 /* finally, finally, gentlemen, start your engine */
5853 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5854
5855 /*
5856 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5857 * Resets should be performed. The RISC has to be running
5858 * to issue a SCSI Bus Reset.
5859 */
5860 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5861 /*
5862 * If the BIOS Signature is present in memory, restore the
5863 * per TID microcode operating variables.
5864 */
5865 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5866 0x55AA) {
5867 /*
5868 * Restore per TID negotiated values.
5869 */
5870 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5871 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5872 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5873 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5874 tagqng_able);
5875 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5876 AdvWriteByteLram(iop_base,
5877 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5878 max_cmd[tid]);
5879 }
5880 } else {
5881 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5882 warn_code = ASC_WARN_BUSRESET_ERROR;
5883 }
5884 }
5885 }
5886
5887 return warn_code;
5888 }
5889
5890 /*
5891 * Reset chip and SCSI Bus.
5892 *
5893 * Return Value:
5894 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
5895 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
5896 */
5897 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
5898 {
5899 int status;
5900 ushort wdtr_able, sdtr_able, tagqng_able;
5901 ushort ppr_able = 0;
5902 uchar tid, max_cmd[ADV_MAX_TID + 1];
5903 AdvPortAddr iop_base;
5904 ushort bios_sig;
5905
5906 iop_base = asc_dvc->iop_base;
5907
5908 /*
5909 * Save current per TID negotiated values.
5910 */
5911 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5912 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5913 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5914 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5915 }
5916 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5917 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5918 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5919 max_cmd[tid]);
5920 }
5921
5922 /*
5923 * Force the AdvInitAsc3550/38C0800Driver() function to
5924 * perform a SCSI Bus Reset by clearing the BIOS signature word.
5925 * The initialization functions assumes a SCSI Bus Reset is not
5926 * needed if the BIOS signature word is present.
5927 */
5928 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5929 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
5930
5931 /*
5932 * Stop chip and reset it.
5933 */
5934 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
5935 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
5936 mdelay(100);
5937 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
5938 ADV_CTRL_REG_CMD_WR_IO_REG);
5939
5940 /*
5941 * Reset Adv Library error code, if any, and try
5942 * re-initializing the chip.
5943 */
5944 asc_dvc->err_code = 0;
5945 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5946 status = AdvInitAsc38C1600Driver(asc_dvc);
5947 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
5948 status = AdvInitAsc38C0800Driver(asc_dvc);
5949 } else {
5950 status = AdvInitAsc3550Driver(asc_dvc);
5951 }
5952
5953 /* Translate initialization return value to status value. */
5954 if (status == 0) {
5955 status = ADV_TRUE;
5956 } else {
5957 status = ADV_FALSE;
5958 }
5959
5960 /*
5961 * Restore the BIOS signature word.
5962 */
5963 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5964
5965 /*
5966 * Restore per TID negotiated values.
5967 */
5968 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5969 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5970 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5971 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5972 }
5973 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5974 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5975 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5976 max_cmd[tid]);
5977 }
5978
5979 return status;
5980 }
5981
5982 /*
5983 * adv_async_callback() - Adv Library asynchronous event callback function.
5984 */
5985 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
5986 {
5987 switch (code) {
5988 case ADV_ASYNC_SCSI_BUS_RESET_DET:
5989 /*
5990 * The firmware detected a SCSI Bus reset.
5991 */
5992 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
5993 break;
5994
5995 case ADV_ASYNC_RDMA_FAILURE:
5996 /*
5997 * Handle RDMA failure by resetting the SCSI Bus and
5998 * possibly the chip if it is unresponsive. Log the error
5999 * with a unique code.
6000 */
6001 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
6002 AdvResetChipAndSB(adv_dvc_varp);
6003 break;
6004
6005 case ADV_HOST_SCSI_BUS_RESET:
6006 /*
6007 * Host generated SCSI bus reset occurred.
6008 */
6009 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
6010 break;
6011
6012 default:
6013 ASC_DBG(0, "unknown code 0x%x\n", code);
6014 break;
6015 }
6016 }
6017
6018 /*
6019 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
6020 *
6021 * Callback function for the Wide SCSI Adv Library.
6022 */
6023 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
6024 {
6025 struct asc_board *boardp = adv_dvc_varp->drv_ptr;
6026 u32 srb_tag;
6027 adv_req_t *reqp;
6028 adv_sgblk_t *sgblkp;
6029 struct scsi_cmnd *scp;
6030 u32 resid_cnt;
6031 dma_addr_t sense_addr;
6032
6033 ASC_DBG(1, "adv_dvc_varp 0x%p, scsiqp 0x%p\n",
6034 adv_dvc_varp, scsiqp);
6035 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6036
6037 /*
6038 * Get the adv_req_t structure for the command that has been
6039 * completed. The adv_req_t structure actually contains the
6040 * completed ADV_SCSI_REQ_Q structure.
6041 */
6042 srb_tag = le32_to_cpu(scsiqp->srb_tag);
6043 scp = scsi_host_find_tag(boardp->shost, scsiqp->srb_tag);
6044
6045 ASC_DBG(1, "scp 0x%p\n", scp);
6046 if (scp == NULL) {
6047 ASC_PRINT
6048 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
6049 return;
6050 }
6051 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6052
6053 reqp = (adv_req_t *)scp->host_scribble;
6054 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
6055 if (reqp == NULL) {
6056 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
6057 return;
6058 }
6059 /*
6060 * Remove backreferences to avoid duplicate
6061 * command completions.
6062 */
6063 scp->host_scribble = NULL;
6064 reqp->cmndp = NULL;
6065
6066 ASC_STATS(boardp->shost, callback);
6067 ASC_DBG(1, "shost 0x%p\n", boardp->shost);
6068
6069 sense_addr = le32_to_cpu(scsiqp->sense_addr);
6070 dma_unmap_single(boardp->dev, sense_addr,
6071 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
6072
6073 /*
6074 * 'done_status' contains the command's ending status.
6075 */
6076 switch (scsiqp->done_status) {
6077 case QD_NO_ERROR:
6078 ASC_DBG(2, "QD_NO_ERROR\n");
6079 scp->result = 0;
6080
6081 /*
6082 * Check for an underrun condition.
6083 *
6084 * If there was no error and an underrun condition, then
6085 * then return the number of underrun bytes.
6086 */
6087 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
6088 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
6089 resid_cnt <= scsi_bufflen(scp)) {
6090 ASC_DBG(1, "underrun condition %lu bytes\n",
6091 (ulong)resid_cnt);
6092 scsi_set_resid(scp, resid_cnt);
6093 }
6094 break;
6095
6096 case QD_WITH_ERROR:
6097 ASC_DBG(2, "QD_WITH_ERROR\n");
6098 switch (scsiqp->host_status) {
6099 case QHSTA_NO_ERROR:
6100 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
6101 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
6102 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6103 SCSI_SENSE_BUFFERSIZE);
6104 /*
6105 * Note: The 'status_byte()' macro used by
6106 * target drivers defined in scsi.h shifts the
6107 * status byte returned by host drivers right
6108 * by 1 bit. This is why target drivers also
6109 * use right shifted status byte definitions.
6110 * For instance target drivers use
6111 * CHECK_CONDITION, defined to 0x1, instead of
6112 * the SCSI defined check condition value of
6113 * 0x2. Host drivers are supposed to return
6114 * the status byte as it is defined by SCSI.
6115 */
6116 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6117 STATUS_BYTE(scsiqp->scsi_status);
6118 } else {
6119 scp->result = STATUS_BYTE(scsiqp->scsi_status);
6120 }
6121 break;
6122
6123 default:
6124 /* Some other QHSTA error occurred. */
6125 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
6126 scp->result = HOST_BYTE(DID_BAD_TARGET);
6127 break;
6128 }
6129 break;
6130
6131 case QD_ABORTED_BY_HOST:
6132 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
6133 scp->result =
6134 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
6135 break;
6136
6137 default:
6138 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
6139 scp->result =
6140 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
6141 break;
6142 }
6143
6144 /*
6145 * If the 'init_tidmask' bit isn't already set for the target and the
6146 * current request finished normally, then set the bit for the target
6147 * to indicate that a device is present.
6148 */
6149 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6150 scsiqp->done_status == QD_NO_ERROR &&
6151 scsiqp->host_status == QHSTA_NO_ERROR) {
6152 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6153 }
6154
6155 asc_scsi_done(scp);
6156
6157 /*
6158 * Free all 'adv_sgblk_t' structures allocated for the request.
6159 */
6160 while ((sgblkp = reqp->sgblkp) != NULL) {
6161 /* Remove 'sgblkp' from the request list. */
6162 reqp->sgblkp = sgblkp->next_sgblkp;
6163
6164 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
6165 sgblkp->sg_addr);
6166 }
6167
6168 ASC_DBG(1, "done\n");
6169 }
6170
6171 /*
6172 * Adv Library Interrupt Service Routine
6173 *
6174 * This function is called by a driver's interrupt service routine.
6175 * The function disables and re-enables interrupts.
6176 *
6177 * When a microcode idle command is completed, the ADV_DVC_VAR
6178 * 'idle_cmd_done' field is set to ADV_TRUE.
6179 *
6180 * Note: AdvISR() can be called when interrupts are disabled or even
6181 * when there is no hardware interrupt condition present. It will
6182 * always check for completed idle commands and microcode requests.
6183 * This is an important feature that shouldn't be changed because it
6184 * allows commands to be completed from polling mode loops.
6185 *
6186 * Return:
6187 * ADV_TRUE(1) - interrupt was pending
6188 * ADV_FALSE(0) - no interrupt was pending
6189 */
6190 static int AdvISR(ADV_DVC_VAR *asc_dvc)
6191 {
6192 AdvPortAddr iop_base;
6193 uchar int_stat;
6194 ushort target_bit;
6195 ADV_CARR_T *free_carrp;
6196 __le32 irq_next_vpa;
6197 ADV_SCSI_REQ_Q *scsiq;
6198 adv_req_t *reqp;
6199
6200 iop_base = asc_dvc->iop_base;
6201
6202 /* Reading the register clears the interrupt. */
6203 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
6204
6205 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
6206 ADV_INTR_STATUS_INTRC)) == 0) {
6207 return ADV_FALSE;
6208 }
6209
6210 /*
6211 * Notify the driver of an asynchronous microcode condition by
6212 * calling the adv_async_callback function. The function
6213 * is passed the microcode ASC_MC_INTRB_CODE byte value.
6214 */
6215 if (int_stat & ADV_INTR_STATUS_INTRB) {
6216 uchar intrb_code;
6217
6218 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
6219
6220 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
6221 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6222 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
6223 asc_dvc->carr_pending_cnt != 0) {
6224 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
6225 ADV_TICKLE_A);
6226 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6227 AdvWriteByteRegister(iop_base,
6228 IOPB_TICKLE,
6229 ADV_TICKLE_NOP);
6230 }
6231 }
6232 }
6233
6234 adv_async_callback(asc_dvc, intrb_code);
6235 }
6236
6237 /*
6238 * Check if the IRQ stopper carrier contains a completed request.
6239 */
6240 while (((irq_next_vpa =
6241 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
6242 /*
6243 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
6244 * The RISC will have set 'areq_vpa' to a virtual address.
6245 *
6246 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
6247 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
6248 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
6249 * in AdvExeScsiQueue().
6250 */
6251 u32 pa_offset = le32_to_cpu(asc_dvc->irq_sp->areq_vpa);
6252 ASC_DBG(1, "irq_sp %p areq_vpa %u\n",
6253 asc_dvc->irq_sp, pa_offset);
6254 reqp = adv_get_reqp(asc_dvc, pa_offset);
6255 scsiq = &reqp->scsi_req_q;
6256
6257 /*
6258 * Request finished with good status and the queue was not
6259 * DMAed to host memory by the firmware. Set all status fields
6260 * to indicate good status.
6261 */
6262 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
6263 scsiq->done_status = QD_NO_ERROR;
6264 scsiq->host_status = scsiq->scsi_status = 0;
6265 scsiq->data_cnt = 0L;
6266 }
6267
6268 /*
6269 * Advance the stopper pointer to the next carrier
6270 * ignoring the lower four bits. Free the previous
6271 * stopper carrier.
6272 */
6273 free_carrp = asc_dvc->irq_sp;
6274 asc_dvc->irq_sp = adv_get_carrier(asc_dvc,
6275 ASC_GET_CARRP(irq_next_vpa));
6276
6277 free_carrp->next_vpa = asc_dvc->carr_freelist->carr_va;
6278 asc_dvc->carr_freelist = free_carrp;
6279 asc_dvc->carr_pending_cnt--;
6280
6281 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
6282
6283 /*
6284 * Clear request microcode control flag.
6285 */
6286 scsiq->cntl = 0;
6287
6288 /*
6289 * Notify the driver of the completed request by passing
6290 * the ADV_SCSI_REQ_Q pointer to its callback function.
6291 */
6292 scsiq->a_flag |= ADV_SCSIQ_DONE;
6293 adv_isr_callback(asc_dvc, scsiq);
6294 /*
6295 * Note: After the driver callback function is called, 'scsiq'
6296 * can no longer be referenced.
6297 *
6298 * Fall through and continue processing other completed
6299 * requests...
6300 */
6301 }
6302 return ADV_TRUE;
6303 }
6304
6305 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
6306 {
6307 if (asc_dvc->err_code == 0) {
6308 asc_dvc->err_code = err_code;
6309 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
6310 err_code);
6311 }
6312 return err_code;
6313 }
6314
6315 static void AscAckInterrupt(PortAddr iop_base)
6316 {
6317 uchar host_flag;
6318 uchar risc_flag;
6319 ushort loop;
6320
6321 loop = 0;
6322 do {
6323 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
6324 if (loop++ > 0x7FFF) {
6325 break;
6326 }
6327 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
6328 host_flag =
6329 AscReadLramByte(iop_base,
6330 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
6331 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6332 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
6333 AscSetChipStatus(iop_base, CIW_INT_ACK);
6334 loop = 0;
6335 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
6336 AscSetChipStatus(iop_base, CIW_INT_ACK);
6337 if (loop++ > 3) {
6338 break;
6339 }
6340 }
6341 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
6342 }
6343
6344 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
6345 {
6346 const uchar *period_table;
6347 int max_index;
6348 int min_index;
6349 int i;
6350
6351 period_table = asc_dvc->sdtr_period_tbl;
6352 max_index = (int)asc_dvc->max_sdtr_index;
6353 min_index = (int)asc_dvc->min_sdtr_index;
6354 if ((syn_time <= period_table[max_index])) {
6355 for (i = min_index; i < (max_index - 1); i++) {
6356 if (syn_time <= period_table[i]) {
6357 return (uchar)i;
6358 }
6359 }
6360 return (uchar)max_index;
6361 } else {
6362 return (uchar)(max_index + 1);
6363 }
6364 }
6365
6366 static uchar
6367 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
6368 {
6369 EXT_MSG sdtr_buf;
6370 uchar sdtr_period_index;
6371 PortAddr iop_base;
6372
6373 iop_base = asc_dvc->iop_base;
6374 sdtr_buf.msg_type = EXTENDED_MESSAGE;
6375 sdtr_buf.msg_len = MS_SDTR_LEN;
6376 sdtr_buf.msg_req = EXTENDED_SDTR;
6377 sdtr_buf.xfer_period = sdtr_period;
6378 sdtr_offset &= ASC_SYN_MAX_OFFSET;
6379 sdtr_buf.req_ack_offset = sdtr_offset;
6380 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6381 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
6382 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6383 (uchar *)&sdtr_buf,
6384 sizeof(EXT_MSG) >> 1);
6385 return ((sdtr_period_index << 4) | sdtr_offset);
6386 } else {
6387 sdtr_buf.req_ack_offset = 0;
6388 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6389 (uchar *)&sdtr_buf,
6390 sizeof(EXT_MSG) >> 1);
6391 return 0;
6392 }
6393 }
6394
6395 static uchar
6396 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
6397 {
6398 uchar byte;
6399 uchar sdtr_period_ix;
6400
6401 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6402 if (sdtr_period_ix > asc_dvc->max_sdtr_index)
6403 return 0xFF;
6404 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
6405 return byte;
6406 }
6407
6408 static bool AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
6409 {
6410 ASC_SCSI_BIT_ID_TYPE org_id;
6411 int i;
6412 bool sta = true;
6413
6414 AscSetBank(iop_base, 1);
6415 org_id = AscReadChipDvcID(iop_base);
6416 for (i = 0; i <= ASC_MAX_TID; i++) {
6417 if (org_id == (0x01 << i))
6418 break;
6419 }
6420 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
6421 AscWriteChipDvcID(iop_base, id);
6422 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
6423 AscSetBank(iop_base, 0);
6424 AscSetChipSyn(iop_base, sdtr_data);
6425 if (AscGetChipSyn(iop_base) != sdtr_data) {
6426 sta = false;
6427 }
6428 } else {
6429 sta = false;
6430 }
6431 AscSetBank(iop_base, 1);
6432 AscWriteChipDvcID(iop_base, org_id);
6433 AscSetBank(iop_base, 0);
6434 return (sta);
6435 }
6436
6437 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
6438 {
6439 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
6440 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
6441 }
6442
6443 static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
6444 {
6445 EXT_MSG ext_msg;
6446 EXT_MSG out_msg;
6447 ushort halt_q_addr;
6448 bool sdtr_accept;
6449 ushort int_halt_code;
6450 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6451 ASC_SCSI_BIT_ID_TYPE target_id;
6452 PortAddr iop_base;
6453 uchar tag_code;
6454 uchar q_status;
6455 uchar halt_qp;
6456 uchar sdtr_data;
6457 uchar target_ix;
6458 uchar q_cntl, tid_no;
6459 uchar cur_dvc_qng;
6460 uchar asyn_sdtr;
6461 uchar scsi_status;
6462 struct asc_board *boardp;
6463
6464 BUG_ON(!asc_dvc->drv_ptr);
6465 boardp = asc_dvc->drv_ptr;
6466
6467 iop_base = asc_dvc->iop_base;
6468 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
6469
6470 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
6471 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
6472 target_ix = AscReadLramByte(iop_base,
6473 (ushort)(halt_q_addr +
6474 (ushort)ASC_SCSIQ_B_TARGET_IX));
6475 q_cntl = AscReadLramByte(iop_base,
6476 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6477 tid_no = ASC_TIX_TO_TID(target_ix);
6478 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
6479 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6480 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
6481 } else {
6482 asyn_sdtr = 0;
6483 }
6484 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
6485 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6486 AscSetChipSDTR(iop_base, 0, tid_no);
6487 boardp->sdtr_data[tid_no] = 0;
6488 }
6489 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6490 return (0);
6491 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
6492 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6493 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6494 boardp->sdtr_data[tid_no] = asyn_sdtr;
6495 }
6496 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6497 return (0);
6498 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
6499 AscMemWordCopyPtrFromLram(iop_base,
6500 ASCV_MSGIN_BEG,
6501 (uchar *)&ext_msg,
6502 sizeof(EXT_MSG) >> 1);
6503
6504 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6505 ext_msg.msg_req == EXTENDED_SDTR &&
6506 ext_msg.msg_len == MS_SDTR_LEN) {
6507 sdtr_accept = true;
6508 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
6509
6510 sdtr_accept = false;
6511 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
6512 }
6513 if ((ext_msg.xfer_period <
6514 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
6515 || (ext_msg.xfer_period >
6516 asc_dvc->sdtr_period_tbl[asc_dvc->
6517 max_sdtr_index])) {
6518 sdtr_accept = false;
6519 ext_msg.xfer_period =
6520 asc_dvc->sdtr_period_tbl[asc_dvc->
6521 min_sdtr_index];
6522 }
6523 if (sdtr_accept) {
6524 sdtr_data =
6525 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
6526 ext_msg.req_ack_offset);
6527 if ((sdtr_data == 0xFF)) {
6528
6529 q_cntl |= QC_MSG_OUT;
6530 asc_dvc->init_sdtr &= ~target_id;
6531 asc_dvc->sdtr_done &= ~target_id;
6532 AscSetChipSDTR(iop_base, asyn_sdtr,
6533 tid_no);
6534 boardp->sdtr_data[tid_no] = asyn_sdtr;
6535 }
6536 }
6537 if (ext_msg.req_ack_offset == 0) {
6538
6539 q_cntl &= ~QC_MSG_OUT;
6540 asc_dvc->init_sdtr &= ~target_id;
6541 asc_dvc->sdtr_done &= ~target_id;
6542 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6543 } else {
6544 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
6545 q_cntl &= ~QC_MSG_OUT;
6546 asc_dvc->sdtr_done |= target_id;
6547 asc_dvc->init_sdtr |= target_id;
6548 asc_dvc->pci_fix_asyn_xfer &=
6549 ~target_id;
6550 sdtr_data =
6551 AscCalSDTRData(asc_dvc,
6552 ext_msg.xfer_period,
6553 ext_msg.
6554 req_ack_offset);
6555 AscSetChipSDTR(iop_base, sdtr_data,
6556 tid_no);
6557 boardp->sdtr_data[tid_no] = sdtr_data;
6558 } else {
6559 q_cntl |= QC_MSG_OUT;
6560 AscMsgOutSDTR(asc_dvc,
6561 ext_msg.xfer_period,
6562 ext_msg.req_ack_offset);
6563 asc_dvc->pci_fix_asyn_xfer &=
6564 ~target_id;
6565 sdtr_data =
6566 AscCalSDTRData(asc_dvc,
6567 ext_msg.xfer_period,
6568 ext_msg.
6569 req_ack_offset);
6570 AscSetChipSDTR(iop_base, sdtr_data,
6571 tid_no);
6572 boardp->sdtr_data[tid_no] = sdtr_data;
6573 asc_dvc->sdtr_done |= target_id;
6574 asc_dvc->init_sdtr |= target_id;
6575 }
6576 }
6577
6578 AscWriteLramByte(iop_base,
6579 (ushort)(halt_q_addr +
6580 (ushort)ASC_SCSIQ_B_CNTL),
6581 q_cntl);
6582 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6583 return (0);
6584 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6585 ext_msg.msg_req == EXTENDED_WDTR &&
6586 ext_msg.msg_len == MS_WDTR_LEN) {
6587
6588 ext_msg.wdtr_width = 0;
6589 AscMemWordCopyPtrToLram(iop_base,
6590 ASCV_MSGOUT_BEG,
6591 (uchar *)&ext_msg,
6592 sizeof(EXT_MSG) >> 1);
6593 q_cntl |= QC_MSG_OUT;
6594 AscWriteLramByte(iop_base,
6595 (ushort)(halt_q_addr +
6596 (ushort)ASC_SCSIQ_B_CNTL),
6597 q_cntl);
6598 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6599 return (0);
6600 } else {
6601
6602 ext_msg.msg_type = MESSAGE_REJECT;
6603 AscMemWordCopyPtrToLram(iop_base,
6604 ASCV_MSGOUT_BEG,
6605 (uchar *)&ext_msg,
6606 sizeof(EXT_MSG) >> 1);
6607 q_cntl |= QC_MSG_OUT;
6608 AscWriteLramByte(iop_base,
6609 (ushort)(halt_q_addr +
6610 (ushort)ASC_SCSIQ_B_CNTL),
6611 q_cntl);
6612 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6613 return (0);
6614 }
6615 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
6616
6617 q_cntl |= QC_REQ_SENSE;
6618
6619 if ((asc_dvc->init_sdtr & target_id) != 0) {
6620
6621 asc_dvc->sdtr_done &= ~target_id;
6622
6623 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
6624 q_cntl |= QC_MSG_OUT;
6625 AscMsgOutSDTR(asc_dvc,
6626 asc_dvc->
6627 sdtr_period_tbl[(sdtr_data >> 4) &
6628 (uchar)(asc_dvc->
6629 max_sdtr_index -
6630 1)],
6631 (uchar)(sdtr_data & (uchar)
6632 ASC_SYN_MAX_OFFSET));
6633 }
6634
6635 AscWriteLramByte(iop_base,
6636 (ushort)(halt_q_addr +
6637 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6638
6639 tag_code = AscReadLramByte(iop_base,
6640 (ushort)(halt_q_addr + (ushort)
6641 ASC_SCSIQ_B_TAG_CODE));
6642 tag_code &= 0xDC;
6643 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
6644 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
6645 ) {
6646
6647 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
6648 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
6649
6650 }
6651 AscWriteLramByte(iop_base,
6652 (ushort)(halt_q_addr +
6653 (ushort)ASC_SCSIQ_B_TAG_CODE),
6654 tag_code);
6655
6656 q_status = AscReadLramByte(iop_base,
6657 (ushort)(halt_q_addr + (ushort)
6658 ASC_SCSIQ_B_STATUS));
6659 q_status |= (QS_READY | QS_BUSY);
6660 AscWriteLramByte(iop_base,
6661 (ushort)(halt_q_addr +
6662 (ushort)ASC_SCSIQ_B_STATUS),
6663 q_status);
6664
6665 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
6666 scsi_busy &= ~target_id;
6667 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6668
6669 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6670 return (0);
6671 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
6672
6673 AscMemWordCopyPtrFromLram(iop_base,
6674 ASCV_MSGOUT_BEG,
6675 (uchar *)&out_msg,
6676 sizeof(EXT_MSG) >> 1);
6677
6678 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
6679 (out_msg.msg_len == MS_SDTR_LEN) &&
6680 (out_msg.msg_req == EXTENDED_SDTR)) {
6681
6682 asc_dvc->init_sdtr &= ~target_id;
6683 asc_dvc->sdtr_done &= ~target_id;
6684 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6685 boardp->sdtr_data[tid_no] = asyn_sdtr;
6686 }
6687 q_cntl &= ~QC_MSG_OUT;
6688 AscWriteLramByte(iop_base,
6689 (ushort)(halt_q_addr +
6690 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6691 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6692 return (0);
6693 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
6694
6695 scsi_status = AscReadLramByte(iop_base,
6696 (ushort)((ushort)halt_q_addr +
6697 (ushort)
6698 ASC_SCSIQ_SCSI_STATUS));
6699 cur_dvc_qng =
6700 AscReadLramByte(iop_base,
6701 (ushort)((ushort)ASC_QADR_BEG +
6702 (ushort)target_ix));
6703 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
6704
6705 scsi_busy = AscReadLramByte(iop_base,
6706 (ushort)ASCV_SCSIBUSY_B);
6707 scsi_busy |= target_id;
6708 AscWriteLramByte(iop_base,
6709 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6710 asc_dvc->queue_full_or_busy |= target_id;
6711
6712 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
6713 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
6714 cur_dvc_qng -= 1;
6715 asc_dvc->max_dvc_qng[tid_no] =
6716 cur_dvc_qng;
6717
6718 AscWriteLramByte(iop_base,
6719 (ushort)((ushort)
6720 ASCV_MAX_DVC_QNG_BEG
6721 + (ushort)
6722 tid_no),
6723 cur_dvc_qng);
6724
6725 /*
6726 * Set the device queue depth to the
6727 * number of active requests when the
6728 * QUEUE FULL condition was encountered.
6729 */
6730 boardp->queue_full |= target_id;
6731 boardp->queue_full_cnt[tid_no] =
6732 cur_dvc_qng;
6733 }
6734 }
6735 }
6736 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6737 return (0);
6738 }
6739 #if CC_VERY_LONG_SG_LIST
6740 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
6741 uchar q_no;
6742 ushort q_addr;
6743 uchar sg_wk_q_no;
6744 uchar first_sg_wk_q_no;
6745 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
6746 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
6747 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
6748 ushort sg_list_dwords;
6749 ushort sg_entry_cnt;
6750 uchar next_qp;
6751 int i;
6752
6753 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
6754 if (q_no == ASC_QLINK_END)
6755 return 0;
6756
6757 q_addr = ASC_QNO_TO_QADDR(q_no);
6758
6759 /*
6760 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
6761 * structure pointer using a macro provided by the driver.
6762 * The ASC_SCSI_REQ pointer provides a pointer to the
6763 * host ASC_SG_HEAD structure.
6764 */
6765 /* Read request's SRB pointer. */
6766 scsiq = (ASC_SCSI_Q *)
6767 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
6768 (ushort)
6769 (q_addr +
6770 ASC_SCSIQ_D_SRBPTR))));
6771
6772 /*
6773 * Get request's first and working SG queue.
6774 */
6775 sg_wk_q_no = AscReadLramByte(iop_base,
6776 (ushort)(q_addr +
6777 ASC_SCSIQ_B_SG_WK_QP));
6778
6779 first_sg_wk_q_no = AscReadLramByte(iop_base,
6780 (ushort)(q_addr +
6781 ASC_SCSIQ_B_FIRST_SG_WK_QP));
6782
6783 /*
6784 * Reset request's working SG queue back to the
6785 * first SG queue.
6786 */
6787 AscWriteLramByte(iop_base,
6788 (ushort)(q_addr +
6789 (ushort)ASC_SCSIQ_B_SG_WK_QP),
6790 first_sg_wk_q_no);
6791
6792 sg_head = scsiq->sg_head;
6793
6794 /*
6795 * Set sg_entry_cnt to the number of SG elements
6796 * that will be completed on this interrupt.
6797 *
6798 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
6799 * SG elements. The data_cnt and data_addr fields which
6800 * add 1 to the SG element capacity are not used when
6801 * restarting SG handling after a halt.
6802 */
6803 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
6804 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
6805
6806 /*
6807 * Keep track of remaining number of SG elements that
6808 * will need to be handled on the next interrupt.
6809 */
6810 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
6811 } else {
6812 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
6813 scsiq->remain_sg_entry_cnt = 0;
6814 }
6815
6816 /*
6817 * Copy SG elements into the list of allocated SG queues.
6818 *
6819 * Last index completed is saved in scsiq->next_sg_index.
6820 */
6821 next_qp = first_sg_wk_q_no;
6822 q_addr = ASC_QNO_TO_QADDR(next_qp);
6823 scsi_sg_q.sg_head_qp = q_no;
6824 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
6825 for (i = 0; i < sg_head->queue_cnt; i++) {
6826 scsi_sg_q.seq_no = i + 1;
6827 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
6828 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
6829 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
6830 /*
6831 * After very first SG queue RISC FW uses next
6832 * SG queue first element then checks sg_list_cnt
6833 * against zero and then decrements, so set
6834 * sg_list_cnt 1 less than number of SG elements
6835 * in each SG queue.
6836 */
6837 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
6838 scsi_sg_q.sg_cur_list_cnt =
6839 ASC_SG_LIST_PER_Q - 1;
6840 } else {
6841 /*
6842 * This is the last SG queue in the list of
6843 * allocated SG queues. If there are more
6844 * SG elements than will fit in the allocated
6845 * queues, then set the QCSG_SG_XFER_MORE flag.
6846 */
6847 if (scsiq->remain_sg_entry_cnt != 0) {
6848 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
6849 } else {
6850 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
6851 }
6852 /* equals sg_entry_cnt * 2 */
6853 sg_list_dwords = sg_entry_cnt << 1;
6854 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
6855 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
6856 sg_entry_cnt = 0;
6857 }
6858
6859 scsi_sg_q.q_no = next_qp;
6860 AscMemWordCopyPtrToLram(iop_base,
6861 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
6862 (uchar *)&scsi_sg_q,
6863 sizeof(ASC_SG_LIST_Q) >> 1);
6864
6865 AscMemDWordCopyPtrToLram(iop_base,
6866 q_addr + ASC_SGQ_LIST_BEG,
6867 (uchar *)&sg_head->
6868 sg_list[scsiq->next_sg_index],
6869 sg_list_dwords);
6870
6871 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
6872
6873 /*
6874 * If the just completed SG queue contained the
6875 * last SG element, then no more SG queues need
6876 * to be written.
6877 */
6878 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
6879 break;
6880 }
6881
6882 next_qp = AscReadLramByte(iop_base,
6883 (ushort)(q_addr +
6884 ASC_SCSIQ_B_FWD));
6885 q_addr = ASC_QNO_TO_QADDR(next_qp);
6886 }
6887
6888 /*
6889 * Clear the halt condition so the RISC will be restarted
6890 * after the return.
6891 */
6892 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6893 return (0);
6894 }
6895 #endif /* CC_VERY_LONG_SG_LIST */
6896 return (0);
6897 }
6898
6899 /*
6900 * void
6901 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6902 *
6903 * Calling/Exit State:
6904 * none
6905 *
6906 * Description:
6907 * Input an ASC_QDONE_INFO structure from the chip
6908 */
6909 static void
6910 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6911 {
6912 int i;
6913 ushort word;
6914
6915 AscSetChipLramAddr(iop_base, s_addr);
6916 for (i = 0; i < 2 * words; i += 2) {
6917 if (i == 10) {
6918 continue;
6919 }
6920 word = inpw(iop_base + IOP_RAM_DATA);
6921 inbuf[i] = word & 0xff;
6922 inbuf[i + 1] = (word >> 8) & 0xff;
6923 }
6924 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
6925 }
6926
6927 static uchar
6928 _AscCopyLramScsiDoneQ(PortAddr iop_base,
6929 ushort q_addr,
6930 ASC_QDONE_INFO *scsiq, unsigned int max_dma_count)
6931 {
6932 ushort _val;
6933 uchar sg_queue_cnt;
6934
6935 DvcGetQinfo(iop_base,
6936 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
6937 (uchar *)scsiq,
6938 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
6939
6940 _val = AscReadLramWord(iop_base,
6941 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
6942 scsiq->q_status = (uchar)_val;
6943 scsiq->q_no = (uchar)(_val >> 8);
6944 _val = AscReadLramWord(iop_base,
6945 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6946 scsiq->cntl = (uchar)_val;
6947 sg_queue_cnt = (uchar)(_val >> 8);
6948 _val = AscReadLramWord(iop_base,
6949 (ushort)(q_addr +
6950 (ushort)ASC_SCSIQ_B_SENSE_LEN));
6951 scsiq->sense_len = (uchar)_val;
6952 scsiq->extra_bytes = (uchar)(_val >> 8);
6953
6954 /*
6955 * Read high word of remain bytes from alternate location.
6956 */
6957 scsiq->remain_bytes = (((u32)AscReadLramWord(iop_base,
6958 (ushort)(q_addr +
6959 (ushort)
6960 ASC_SCSIQ_W_ALT_DC1)))
6961 << 16);
6962 /*
6963 * Read low word of remain bytes from original location.
6964 */
6965 scsiq->remain_bytes += AscReadLramWord(iop_base,
6966 (ushort)(q_addr + (ushort)
6967 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
6968
6969 scsiq->remain_bytes &= max_dma_count;
6970 return sg_queue_cnt;
6971 }
6972
6973 /*
6974 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
6975 *
6976 * Interrupt callback function for the Narrow SCSI Asc Library.
6977 */
6978 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
6979 {
6980 struct asc_board *boardp = asc_dvc_varp->drv_ptr;
6981 u32 srb_tag;
6982 struct scsi_cmnd *scp;
6983
6984 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
6985 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
6986
6987 /*
6988 * Decrease the srb_tag by 1 to find the SCSI command
6989 */
6990 srb_tag = qdonep->d2.srb_tag - 1;
6991 scp = scsi_host_find_tag(boardp->shost, srb_tag);
6992 if (!scp)
6993 return;
6994
6995 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6996
6997 ASC_STATS(boardp->shost, callback);
6998
6999 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
7000 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7001 /*
7002 * 'qdonep' contains the command's ending status.
7003 */
7004 switch (qdonep->d3.done_stat) {
7005 case QD_NO_ERROR:
7006 ASC_DBG(2, "QD_NO_ERROR\n");
7007 scp->result = 0;
7008
7009 /*
7010 * Check for an underrun condition.
7011 *
7012 * If there was no error and an underrun condition, then
7013 * return the number of underrun bytes.
7014 */
7015 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
7016 qdonep->remain_bytes <= scsi_bufflen(scp)) {
7017 ASC_DBG(1, "underrun condition %u bytes\n",
7018 (unsigned)qdonep->remain_bytes);
7019 scsi_set_resid(scp, qdonep->remain_bytes);
7020 }
7021 break;
7022
7023 case QD_WITH_ERROR:
7024 ASC_DBG(2, "QD_WITH_ERROR\n");
7025 switch (qdonep->d3.host_stat) {
7026 case QHSTA_NO_ERROR:
7027 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
7028 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
7029 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
7030 SCSI_SENSE_BUFFERSIZE);
7031 /*
7032 * Note: The 'status_byte()' macro used by
7033 * target drivers defined in scsi.h shifts the
7034 * status byte returned by host drivers right
7035 * by 1 bit. This is why target drivers also
7036 * use right shifted status byte definitions.
7037 * For instance target drivers use
7038 * CHECK_CONDITION, defined to 0x1, instead of
7039 * the SCSI defined check condition value of
7040 * 0x2. Host drivers are supposed to return
7041 * the status byte as it is defined by SCSI.
7042 */
7043 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
7044 STATUS_BYTE(qdonep->d3.scsi_stat);
7045 } else {
7046 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
7047 }
7048 break;
7049
7050 default:
7051 /* QHSTA error occurred */
7052 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
7053 scp->result = HOST_BYTE(DID_BAD_TARGET);
7054 break;
7055 }
7056 break;
7057
7058 case QD_ABORTED_BY_HOST:
7059 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
7060 scp->result =
7061 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
7062 scsi_msg) |
7063 STATUS_BYTE(qdonep->d3.scsi_stat);
7064 break;
7065
7066 default:
7067 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
7068 scp->result =
7069 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
7070 scsi_msg) |
7071 STATUS_BYTE(qdonep->d3.scsi_stat);
7072 break;
7073 }
7074
7075 /*
7076 * If the 'init_tidmask' bit isn't already set for the target and the
7077 * current request finished normally, then set the bit for the target
7078 * to indicate that a device is present.
7079 */
7080 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
7081 qdonep->d3.done_stat == QD_NO_ERROR &&
7082 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
7083 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
7084 }
7085
7086 asc_scsi_done(scp);
7087 }
7088
7089 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
7090 {
7091 uchar next_qp;
7092 uchar n_q_used;
7093 uchar sg_list_qp;
7094 uchar sg_queue_cnt;
7095 uchar q_cnt;
7096 uchar done_q_tail;
7097 uchar tid_no;
7098 ASC_SCSI_BIT_ID_TYPE scsi_busy;
7099 ASC_SCSI_BIT_ID_TYPE target_id;
7100 PortAddr iop_base;
7101 ushort q_addr;
7102 ushort sg_q_addr;
7103 uchar cur_target_qng;
7104 ASC_QDONE_INFO scsiq_buf;
7105 ASC_QDONE_INFO *scsiq;
7106 bool false_overrun;
7107
7108 iop_base = asc_dvc->iop_base;
7109 n_q_used = 1;
7110 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
7111 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
7112 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
7113 next_qp = AscReadLramByte(iop_base,
7114 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
7115 if (next_qp != ASC_QLINK_END) {
7116 AscPutVarDoneQTail(iop_base, next_qp);
7117 q_addr = ASC_QNO_TO_QADDR(next_qp);
7118 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
7119 asc_dvc->max_dma_count);
7120 AscWriteLramByte(iop_base,
7121 (ushort)(q_addr +
7122 (ushort)ASC_SCSIQ_B_STATUS),
7123 (uchar)(scsiq->
7124 q_status & (uchar)~(QS_READY |
7125 QS_ABORTED)));
7126 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
7127 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
7128 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
7129 sg_q_addr = q_addr;
7130 sg_list_qp = next_qp;
7131 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
7132 sg_list_qp = AscReadLramByte(iop_base,
7133 (ushort)(sg_q_addr
7134 + (ushort)
7135 ASC_SCSIQ_B_FWD));
7136 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
7137 if (sg_list_qp == ASC_QLINK_END) {
7138 AscSetLibErrorCode(asc_dvc,
7139 ASCQ_ERR_SG_Q_LINKS);
7140 scsiq->d3.done_stat = QD_WITH_ERROR;
7141 scsiq->d3.host_stat =
7142 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
7143 goto FATAL_ERR_QDONE;
7144 }
7145 AscWriteLramByte(iop_base,
7146 (ushort)(sg_q_addr + (ushort)
7147 ASC_SCSIQ_B_STATUS),
7148 QS_FREE);
7149 }
7150 n_q_used = sg_queue_cnt + 1;
7151 AscPutVarDoneQTail(iop_base, sg_list_qp);
7152 }
7153 if (asc_dvc->queue_full_or_busy & target_id) {
7154 cur_target_qng = AscReadLramByte(iop_base,
7155 (ushort)((ushort)
7156 ASC_QADR_BEG
7157 + (ushort)
7158 scsiq->d2.
7159 target_ix));
7160 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
7161 scsi_busy = AscReadLramByte(iop_base, (ushort)
7162 ASCV_SCSIBUSY_B);
7163 scsi_busy &= ~target_id;
7164 AscWriteLramByte(iop_base,
7165 (ushort)ASCV_SCSIBUSY_B,
7166 scsi_busy);
7167 asc_dvc->queue_full_or_busy &= ~target_id;
7168 }
7169 }
7170 if (asc_dvc->cur_total_qng >= n_q_used) {
7171 asc_dvc->cur_total_qng -= n_q_used;
7172 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
7173 asc_dvc->cur_dvc_qng[tid_no]--;
7174 }
7175 } else {
7176 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
7177 scsiq->d3.done_stat = QD_WITH_ERROR;
7178 goto FATAL_ERR_QDONE;
7179 }
7180 if ((scsiq->d2.srb_tag == 0UL) ||
7181 ((scsiq->q_status & QS_ABORTED) != 0)) {
7182 return (0x11);
7183 } else if (scsiq->q_status == QS_DONE) {
7184 /*
7185 * This is also curious.
7186 * false_overrun will _always_ be set to 'false'
7187 */
7188 false_overrun = false;
7189 if (scsiq->extra_bytes != 0) {
7190 scsiq->remain_bytes += scsiq->extra_bytes;
7191 }
7192 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
7193 if (scsiq->d3.host_stat ==
7194 QHSTA_M_DATA_OVER_RUN) {
7195 if ((scsiq->
7196 cntl & (QC_DATA_IN | QC_DATA_OUT))
7197 == 0) {
7198 scsiq->d3.done_stat =
7199 QD_NO_ERROR;
7200 scsiq->d3.host_stat =
7201 QHSTA_NO_ERROR;
7202 } else if (false_overrun) {
7203 scsiq->d3.done_stat =
7204 QD_NO_ERROR;
7205 scsiq->d3.host_stat =
7206 QHSTA_NO_ERROR;
7207 }
7208 } else if (scsiq->d3.host_stat ==
7209 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
7210 AscStopChip(iop_base);
7211 AscSetChipControl(iop_base,
7212 (uchar)(CC_SCSI_RESET
7213 | CC_HALT));
7214 udelay(60);
7215 AscSetChipControl(iop_base, CC_HALT);
7216 AscSetChipStatus(iop_base,
7217 CIW_CLR_SCSI_RESET_INT);
7218 AscSetChipStatus(iop_base, 0);
7219 AscSetChipControl(iop_base, 0);
7220 }
7221 }
7222 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7223 asc_isr_callback(asc_dvc, scsiq);
7224 } else {
7225 if ((AscReadLramByte(iop_base,
7226 (ushort)(q_addr + (ushort)
7227 ASC_SCSIQ_CDB_BEG))
7228 == START_STOP)) {
7229 asc_dvc->unit_not_ready &= ~target_id;
7230 if (scsiq->d3.done_stat != QD_NO_ERROR) {
7231 asc_dvc->start_motor &=
7232 ~target_id;
7233 }
7234 }
7235 }
7236 return (1);
7237 } else {
7238 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
7239 FATAL_ERR_QDONE:
7240 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7241 asc_isr_callback(asc_dvc, scsiq);
7242 }
7243 return (0x80);
7244 }
7245 }
7246 return (0);
7247 }
7248
7249 static int AscISR(ASC_DVC_VAR *asc_dvc)
7250 {
7251 ASC_CS_TYPE chipstat;
7252 PortAddr iop_base;
7253 ushort saved_ram_addr;
7254 uchar ctrl_reg;
7255 uchar saved_ctrl_reg;
7256 int int_pending;
7257 int status;
7258 uchar host_flag;
7259
7260 iop_base = asc_dvc->iop_base;
7261 int_pending = ASC_FALSE;
7262
7263 if (AscIsIntPending(iop_base) == 0)
7264 return int_pending;
7265
7266 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
7267 return ASC_ERROR;
7268 }
7269 if (asc_dvc->in_critical_cnt != 0) {
7270 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
7271 return ASC_ERROR;
7272 }
7273 if (asc_dvc->is_in_int) {
7274 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
7275 return ASC_ERROR;
7276 }
7277 asc_dvc->is_in_int = true;
7278 ctrl_reg = AscGetChipControl(iop_base);
7279 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
7280 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
7281 chipstat = AscGetChipStatus(iop_base);
7282 if (chipstat & CSW_SCSI_RESET_LATCH) {
7283 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
7284 int i = 10;
7285 int_pending = ASC_TRUE;
7286 asc_dvc->sdtr_done = 0;
7287 saved_ctrl_reg &= (uchar)(~CC_HALT);
7288 while ((AscGetChipStatus(iop_base) &
7289 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
7290 mdelay(100);
7291 }
7292 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
7293 AscSetChipControl(iop_base, CC_HALT);
7294 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
7295 AscSetChipStatus(iop_base, 0);
7296 chipstat = AscGetChipStatus(iop_base);
7297 }
7298 }
7299 saved_ram_addr = AscGetChipLramAddr(iop_base);
7300 host_flag = AscReadLramByte(iop_base,
7301 ASCV_HOST_FLAG_B) &
7302 (uchar)(~ASC_HOST_FLAG_IN_ISR);
7303 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
7304 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
7305 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
7306 AscAckInterrupt(iop_base);
7307 int_pending = ASC_TRUE;
7308 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
7309 if (AscIsrChipHalted(asc_dvc) == ASC_ERROR) {
7310 goto ISR_REPORT_QDONE_FATAL_ERROR;
7311 } else {
7312 saved_ctrl_reg &= (uchar)(~CC_HALT);
7313 }
7314 } else {
7315 ISR_REPORT_QDONE_FATAL_ERROR:
7316 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
7317 while (((status =
7318 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
7319 }
7320 } else {
7321 do {
7322 if ((status =
7323 AscIsrQDone(asc_dvc)) == 1) {
7324 break;
7325 }
7326 } while (status == 0x11);
7327 }
7328 if ((status & 0x80) != 0)
7329 int_pending = ASC_ERROR;
7330 }
7331 }
7332 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
7333 AscSetChipLramAddr(iop_base, saved_ram_addr);
7334 AscSetChipControl(iop_base, saved_ctrl_reg);
7335 asc_dvc->is_in_int = false;
7336 return int_pending;
7337 }
7338
7339 /*
7340 * advansys_reset()
7341 *
7342 * Reset the host associated with the command 'scp'.
7343 *
7344 * This function runs its own thread. Interrupts must be blocked but
7345 * sleeping is allowed and no locking other than for host structures is
7346 * required. Returns SUCCESS or FAILED.
7347 */
7348 static int advansys_reset(struct scsi_cmnd *scp)
7349 {
7350 struct Scsi_Host *shost = scp->device->host;
7351 struct asc_board *boardp = shost_priv(shost);
7352 unsigned long flags;
7353 int status;
7354 int ret = SUCCESS;
7355
7356 ASC_DBG(1, "0x%p\n", scp);
7357
7358 ASC_STATS(shost, reset);
7359
7360 scmd_printk(KERN_INFO, scp, "SCSI host reset started...\n");
7361
7362 if (ASC_NARROW_BOARD(boardp)) {
7363 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7364
7365 /* Reset the chip and SCSI bus. */
7366 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
7367 status = AscInitAsc1000Driver(asc_dvc);
7368
7369 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */
7370 if (asc_dvc->err_code || !asc_dvc->overrun_dma) {
7371 scmd_printk(KERN_INFO, scp, "SCSI host reset error: "
7372 "0x%x, status: 0x%x\n", asc_dvc->err_code,
7373 status);
7374 ret = FAILED;
7375 } else if (status) {
7376 scmd_printk(KERN_INFO, scp, "SCSI host reset warning: "
7377 "0x%x\n", status);
7378 } else {
7379 scmd_printk(KERN_INFO, scp, "SCSI host reset "
7380 "successful\n");
7381 }
7382
7383 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
7384 } else {
7385 /*
7386 * If the suggest reset bus flags are set, then reset the bus.
7387 * Otherwise only reset the device.
7388 */
7389 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
7390
7391 /*
7392 * Reset the chip and SCSI bus.
7393 */
7394 ASC_DBG(1, "before AdvResetChipAndSB()\n");
7395 switch (AdvResetChipAndSB(adv_dvc)) {
7396 case ASC_TRUE:
7397 scmd_printk(KERN_INFO, scp, "SCSI host reset "
7398 "successful\n");
7399 break;
7400 case ASC_FALSE:
7401 default:
7402 scmd_printk(KERN_INFO, scp, "SCSI host reset error\n");
7403 ret = FAILED;
7404 break;
7405 }
7406 spin_lock_irqsave(shost->host_lock, flags);
7407 AdvISR(adv_dvc);
7408 spin_unlock_irqrestore(shost->host_lock, flags);
7409 }
7410
7411 ASC_DBG(1, "ret %d\n", ret);
7412
7413 return ret;
7414 }
7415
7416 /*
7417 * advansys_biosparam()
7418 *
7419 * Translate disk drive geometry if the "BIOS greater than 1 GB"
7420 * support is enabled for a drive.
7421 *
7422 * ip (information pointer) is an int array with the following definition:
7423 * ip[0]: heads
7424 * ip[1]: sectors
7425 * ip[2]: cylinders
7426 */
7427 static int
7428 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
7429 sector_t capacity, int ip[])
7430 {
7431 struct asc_board *boardp = shost_priv(sdev->host);
7432
7433 ASC_DBG(1, "begin\n");
7434 ASC_STATS(sdev->host, biosparam);
7435 if (ASC_NARROW_BOARD(boardp)) {
7436 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
7437 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
7438 ip[0] = 255;
7439 ip[1] = 63;
7440 } else {
7441 ip[0] = 64;
7442 ip[1] = 32;
7443 }
7444 } else {
7445 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
7446 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
7447 ip[0] = 255;
7448 ip[1] = 63;
7449 } else {
7450 ip[0] = 64;
7451 ip[1] = 32;
7452 }
7453 }
7454 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
7455 ASC_DBG(1, "end\n");
7456 return 0;
7457 }
7458
7459 /*
7460 * First-level interrupt handler.
7461 *
7462 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
7463 */
7464 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
7465 {
7466 struct Scsi_Host *shost = dev_id;
7467 struct asc_board *boardp = shost_priv(shost);
7468 irqreturn_t result = IRQ_NONE;
7469
7470 ASC_DBG(2, "boardp 0x%p\n", boardp);
7471 spin_lock(shost->host_lock);
7472 if (ASC_NARROW_BOARD(boardp)) {
7473 if (AscIsIntPending(shost->io_port)) {
7474 result = IRQ_HANDLED;
7475 ASC_STATS(shost, interrupt);
7476 ASC_DBG(1, "before AscISR()\n");
7477 AscISR(&boardp->dvc_var.asc_dvc_var);
7478 }
7479 } else {
7480 ASC_DBG(1, "before AdvISR()\n");
7481 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
7482 result = IRQ_HANDLED;
7483 ASC_STATS(shost, interrupt);
7484 }
7485 }
7486 spin_unlock(shost->host_lock);
7487
7488 ASC_DBG(1, "end\n");
7489 return result;
7490 }
7491
7492 static bool AscHostReqRiscHalt(PortAddr iop_base)
7493 {
7494 int count = 0;
7495 bool sta = false;
7496 uchar saved_stop_code;
7497
7498 if (AscIsChipHalted(iop_base))
7499 return true;
7500 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
7501 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
7502 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
7503 do {
7504 if (AscIsChipHalted(iop_base)) {
7505 sta = true;
7506 break;
7507 }
7508 mdelay(100);
7509 } while (count++ < 20);
7510 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
7511 return sta;
7512 }
7513
7514 static bool
7515 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
7516 {
7517 bool sta = false;
7518
7519 if (AscHostReqRiscHalt(iop_base)) {
7520 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
7521 AscStartChip(iop_base);
7522 }
7523 return sta;
7524 }
7525
7526 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
7527 {
7528 char type = sdev->type;
7529 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
7530
7531 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
7532 return;
7533 if (asc_dvc->init_sdtr & tid_bits)
7534 return;
7535
7536 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
7537 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
7538
7539 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
7540 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
7541 (type == TYPE_ROM) || (type == TYPE_TAPE))
7542 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
7543
7544 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
7545 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
7546 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
7547 }
7548
7549 static void
7550 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
7551 {
7552 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
7553 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
7554
7555 if (sdev->lun == 0) {
7556 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
7557 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
7558 asc_dvc->init_sdtr |= tid_bit;
7559 } else {
7560 asc_dvc->init_sdtr &= ~tid_bit;
7561 }
7562
7563 if (orig_init_sdtr != asc_dvc->init_sdtr)
7564 AscAsyncFix(asc_dvc, sdev);
7565 }
7566
7567 if (sdev->tagged_supported) {
7568 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
7569 if (sdev->lun == 0) {
7570 asc_dvc->cfg->can_tagged_qng |= tid_bit;
7571 asc_dvc->use_tagged_qng |= tid_bit;
7572 }
7573 scsi_change_queue_depth(sdev,
7574 asc_dvc->max_dvc_qng[sdev->id]);
7575 }
7576 } else {
7577 if (sdev->lun == 0) {
7578 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
7579 asc_dvc->use_tagged_qng &= ~tid_bit;
7580 }
7581 }
7582
7583 if ((sdev->lun == 0) &&
7584 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
7585 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
7586 asc_dvc->cfg->disc_enable);
7587 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
7588 asc_dvc->use_tagged_qng);
7589 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
7590 asc_dvc->cfg->can_tagged_qng);
7591
7592 asc_dvc->max_dvc_qng[sdev->id] =
7593 asc_dvc->cfg->max_tag_qng[sdev->id];
7594 AscWriteLramByte(asc_dvc->iop_base,
7595 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
7596 asc_dvc->max_dvc_qng[sdev->id]);
7597 }
7598 }
7599
7600 /*
7601 * Wide Transfers
7602 *
7603 * If the EEPROM enabled WDTR for the device and the device supports wide
7604 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
7605 * write the new value to the microcode.
7606 */
7607 static void
7608 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
7609 {
7610 unsigned short cfg_word;
7611 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7612 if ((cfg_word & tidmask) != 0)
7613 return;
7614
7615 cfg_word |= tidmask;
7616 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7617
7618 /*
7619 * Clear the microcode SDTR and WDTR negotiation done indicators for
7620 * the target to cause it to negotiate with the new setting set above.
7621 * WDTR when accepted causes the target to enter asynchronous mode, so
7622 * SDTR must be negotiated.
7623 */
7624 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7625 cfg_word &= ~tidmask;
7626 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7627 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7628 cfg_word &= ~tidmask;
7629 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7630 }
7631
7632 /*
7633 * Synchronous Transfers
7634 *
7635 * If the EEPROM enabled SDTR for the device and the device
7636 * supports synchronous transfers, then turn on the device's
7637 * 'sdtr_able' bit. Write the new value to the microcode.
7638 */
7639 static void
7640 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
7641 {
7642 unsigned short cfg_word;
7643 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7644 if ((cfg_word & tidmask) != 0)
7645 return;
7646
7647 cfg_word |= tidmask;
7648 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7649
7650 /*
7651 * Clear the microcode "SDTR negotiation" done indicator for the
7652 * target to cause it to negotiate with the new setting set above.
7653 */
7654 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7655 cfg_word &= ~tidmask;
7656 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7657 }
7658
7659 /*
7660 * PPR (Parallel Protocol Request) Capable
7661 *
7662 * If the device supports DT mode, then it must be PPR capable.
7663 * The PPR message will be used in place of the SDTR and WDTR
7664 * messages to negotiate synchronous speed and offset, transfer
7665 * width, and protocol options.
7666 */
7667 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
7668 AdvPortAddr iop_base, unsigned short tidmask)
7669 {
7670 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7671 adv_dvc->ppr_able |= tidmask;
7672 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7673 }
7674
7675 static void
7676 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
7677 {
7678 AdvPortAddr iop_base = adv_dvc->iop_base;
7679 unsigned short tidmask = 1 << sdev->id;
7680
7681 if (sdev->lun == 0) {
7682 /*
7683 * Handle WDTR, SDTR, and Tag Queuing. If the feature
7684 * is enabled in the EEPROM and the device supports the
7685 * feature, then enable it in the microcode.
7686 */
7687
7688 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
7689 advansys_wide_enable_wdtr(iop_base, tidmask);
7690 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
7691 advansys_wide_enable_sdtr(iop_base, tidmask);
7692 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
7693 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
7694
7695 /*
7696 * Tag Queuing is disabled for the BIOS which runs in polled
7697 * mode and would see no benefit from Tag Queuing. Also by
7698 * disabling Tag Queuing in the BIOS devices with Tag Queuing
7699 * bugs will at least work with the BIOS.
7700 */
7701 if ((adv_dvc->tagqng_able & tidmask) &&
7702 sdev->tagged_supported) {
7703 unsigned short cfg_word;
7704 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
7705 cfg_word |= tidmask;
7706 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7707 cfg_word);
7708 AdvWriteByteLram(iop_base,
7709 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
7710 adv_dvc->max_dvc_qng);
7711 }
7712 }
7713
7714 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported)
7715 scsi_change_queue_depth(sdev, adv_dvc->max_dvc_qng);
7716 }
7717
7718 /*
7719 * Set the number of commands to queue per device for the
7720 * specified host adapter.
7721 */
7722 static int advansys_slave_configure(struct scsi_device *sdev)
7723 {
7724 struct asc_board *boardp = shost_priv(sdev->host);
7725
7726 if (ASC_NARROW_BOARD(boardp))
7727 advansys_narrow_slave_configure(sdev,
7728 &boardp->dvc_var.asc_dvc_var);
7729 else
7730 advansys_wide_slave_configure(sdev,
7731 &boardp->dvc_var.adv_dvc_var);
7732
7733 return 0;
7734 }
7735
7736 static __le32 advansys_get_sense_buffer_dma(struct scsi_cmnd *scp)
7737 {
7738 struct asc_board *board = shost_priv(scp->device->host);
7739 scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer,
7740 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7741 dma_cache_sync(board->dev, scp->sense_buffer,
7742 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7743 return cpu_to_le32(scp->SCp.dma_handle);
7744 }
7745
7746 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
7747 struct asc_scsi_q *asc_scsi_q)
7748 {
7749 struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7750 int use_sg;
7751 u32 srb_tag;
7752
7753 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
7754
7755 /*
7756 * Set the srb_tag to the command tag + 1, as
7757 * srb_tag '0' is used internally by the chip.
7758 */
7759 srb_tag = scp->request->tag + 1;
7760 asc_scsi_q->q2.srb_tag = srb_tag;
7761
7762 /*
7763 * Build the ASC_SCSI_Q request.
7764 */
7765 asc_scsi_q->cdbptr = &scp->cmnd[0];
7766 asc_scsi_q->q2.cdb_len = scp->cmd_len;
7767 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
7768 asc_scsi_q->q1.target_lun = scp->device->lun;
7769 asc_scsi_q->q2.target_ix =
7770 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
7771 asc_scsi_q->q1.sense_addr = advansys_get_sense_buffer_dma(scp);
7772 asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE;
7773
7774 /*
7775 * If there are any outstanding requests for the current target,
7776 * then every 255th request send an ORDERED request. This heuristic
7777 * tries to retain the benefit of request sorting while preventing
7778 * request starvation. 255 is the max number of tags or pending commands
7779 * a device may have outstanding.
7780 *
7781 * The request count is incremented below for every successfully
7782 * started request.
7783 *
7784 */
7785 if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
7786 (boardp->reqcnt[scp->device->id] % 255) == 0) {
7787 asc_scsi_q->q2.tag_code = ORDERED_QUEUE_TAG;
7788 } else {
7789 asc_scsi_q->q2.tag_code = SIMPLE_QUEUE_TAG;
7790 }
7791
7792 /* Build ASC_SCSI_Q */
7793 use_sg = scsi_dma_map(scp);
7794 if (use_sg != 0) {
7795 int sgcnt;
7796 struct scatterlist *slp;
7797 struct asc_sg_head *asc_sg_head;
7798
7799 if (use_sg > scp->device->host->sg_tablesize) {
7800 scmd_printk(KERN_ERR, scp, "use_sg %d > "
7801 "sg_tablesize %d\n", use_sg,
7802 scp->device->host->sg_tablesize);
7803 scsi_dma_unmap(scp);
7804 scp->result = HOST_BYTE(DID_ERROR);
7805 return ASC_ERROR;
7806 }
7807
7808 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
7809 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
7810 if (!asc_sg_head) {
7811 scsi_dma_unmap(scp);
7812 scp->result = HOST_BYTE(DID_SOFT_ERROR);
7813 return ASC_ERROR;
7814 }
7815
7816 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
7817 asc_scsi_q->sg_head = asc_sg_head;
7818 asc_scsi_q->q1.data_cnt = 0;
7819 asc_scsi_q->q1.data_addr = 0;
7820 /* This is a byte value, otherwise it would need to be swapped. */
7821 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
7822 ASC_STATS_ADD(scp->device->host, xfer_elem,
7823 asc_sg_head->entry_cnt);
7824
7825 /*
7826 * Convert scatter-gather list into ASC_SG_HEAD list.
7827 */
7828 scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
7829 asc_sg_head->sg_list[sgcnt].addr =
7830 cpu_to_le32(sg_dma_address(slp));
7831 asc_sg_head->sg_list[sgcnt].bytes =
7832 cpu_to_le32(sg_dma_len(slp));
7833 ASC_STATS_ADD(scp->device->host, xfer_sect,
7834 DIV_ROUND_UP(sg_dma_len(slp), 512));
7835 }
7836 }
7837
7838 ASC_STATS(scp->device->host, xfer_cnt);
7839
7840 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
7841 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
7842
7843 return ASC_NOERROR;
7844 }
7845
7846 /*
7847 * Build scatter-gather list for Adv Library (Wide Board).
7848 *
7849 * Additional ADV_SG_BLOCK structures will need to be allocated
7850 * if the total number of scatter-gather elements exceeds
7851 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
7852 * assumed to be physically contiguous.
7853 *
7854 * Return:
7855 * ADV_SUCCESS(1) - SG List successfully created
7856 * ADV_ERROR(-1) - SG List creation failed
7857 */
7858 static int
7859 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp,
7860 ADV_SCSI_REQ_Q *scsiqp, struct scsi_cmnd *scp, int use_sg)
7861 {
7862 adv_sgblk_t *sgblkp, *prev_sgblkp;
7863 struct scatterlist *slp;
7864 int sg_elem_cnt;
7865 ADV_SG_BLOCK *sg_block, *prev_sg_block;
7866 dma_addr_t sgblk_paddr;
7867 int i;
7868
7869 slp = scsi_sglist(scp);
7870 sg_elem_cnt = use_sg;
7871 prev_sgblkp = NULL;
7872 prev_sg_block = NULL;
7873 reqp->sgblkp = NULL;
7874
7875 for (;;) {
7876 /*
7877 * Allocate a 'adv_sgblk_t' structure from the board free
7878 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
7879 * (15) scatter-gather elements.
7880 */
7881 sgblkp = dma_pool_alloc(boardp->adv_sgblk_pool, GFP_ATOMIC,
7882 &sgblk_paddr);
7883 if (!sgblkp) {
7884 ASC_DBG(1, "no free adv_sgblk_t\n");
7885 ASC_STATS(scp->device->host, adv_build_nosg);
7886
7887 /*
7888 * Allocation failed. Free 'adv_sgblk_t' structures
7889 * already allocated for the request.
7890 */
7891 while ((sgblkp = reqp->sgblkp) != NULL) {
7892 /* Remove 'sgblkp' from the request list. */
7893 reqp->sgblkp = sgblkp->next_sgblkp;
7894 sgblkp->next_sgblkp = NULL;
7895 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
7896 sgblkp->sg_addr);
7897 }
7898 return ASC_BUSY;
7899 }
7900 /* Complete 'adv_sgblk_t' board allocation. */
7901 sgblkp->sg_addr = sgblk_paddr;
7902 sgblkp->next_sgblkp = NULL;
7903 sg_block = &sgblkp->sg_block;
7904
7905 /*
7906 * Check if this is the first 'adv_sgblk_t' for the
7907 * request.
7908 */
7909 if (reqp->sgblkp == NULL) {
7910 /* Request's first scatter-gather block. */
7911 reqp->sgblkp = sgblkp;
7912
7913 /*
7914 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
7915 * address pointers.
7916 */
7917 scsiqp->sg_list_ptr = sg_block;
7918 scsiqp->sg_real_addr = cpu_to_le32(sgblk_paddr);
7919 } else {
7920 /* Request's second or later scatter-gather block. */
7921 prev_sgblkp->next_sgblkp = sgblkp;
7922
7923 /*
7924 * Point the previous ADV_SG_BLOCK structure to
7925 * the newly allocated ADV_SG_BLOCK structure.
7926 */
7927 prev_sg_block->sg_ptr = cpu_to_le32(sgblk_paddr);
7928 }
7929
7930 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
7931 sg_block->sg_list[i].sg_addr =
7932 cpu_to_le32(sg_dma_address(slp));
7933 sg_block->sg_list[i].sg_count =
7934 cpu_to_le32(sg_dma_len(slp));
7935 ASC_STATS_ADD(scp->device->host, xfer_sect,
7936 DIV_ROUND_UP(sg_dma_len(slp), 512));
7937
7938 if (--sg_elem_cnt == 0) {
7939 /*
7940 * Last ADV_SG_BLOCK and scatter-gather entry.
7941 */
7942 sg_block->sg_cnt = i + 1;
7943 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
7944 return ADV_SUCCESS;
7945 }
7946 slp++;
7947 }
7948 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
7949 prev_sg_block = sg_block;
7950 prev_sgblkp = sgblkp;
7951 }
7952 }
7953
7954 /*
7955 * Build a request structure for the Adv Library (Wide Board).
7956 *
7957 * If an adv_req_t can not be allocated to issue the request,
7958 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
7959 *
7960 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
7961 * microcode for DMA addresses or math operations are byte swapped
7962 * to little-endian order.
7963 */
7964 static int
7965 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
7966 adv_req_t **adv_reqpp)
7967 {
7968 u32 srb_tag = scp->request->tag;
7969 adv_req_t *reqp;
7970 ADV_SCSI_REQ_Q *scsiqp;
7971 int ret;
7972 int use_sg;
7973 dma_addr_t sense_addr;
7974
7975 /*
7976 * Allocate an adv_req_t structure from the board to execute
7977 * the command.
7978 */
7979 reqp = &boardp->adv_reqp[srb_tag];
7980 if (reqp->cmndp && reqp->cmndp != scp ) {
7981 ASC_DBG(1, "no free adv_req_t\n");
7982 ASC_STATS(scp->device->host, adv_build_noreq);
7983 return ASC_BUSY;
7984 }
7985
7986 reqp->req_addr = boardp->adv_reqp_addr + (srb_tag * sizeof(adv_req_t));
7987
7988 scsiqp = &reqp->scsi_req_q;
7989
7990 /*
7991 * Initialize the structure.
7992 */
7993 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
7994
7995 /*
7996 * Set the srb_tag to the command tag.
7997 */
7998 scsiqp->srb_tag = srb_tag;
7999
8000 /*
8001 * Set 'host_scribble' to point to the adv_req_t structure.
8002 */
8003 reqp->cmndp = scp;
8004 scp->host_scribble = (void *)reqp;
8005
8006 /*
8007 * Build the ADV_SCSI_REQ_Q request.
8008 */
8009
8010 /* Set CDB length and copy it to the request structure. */
8011 scsiqp->cdb_len = scp->cmd_len;
8012 /* Copy first 12 CDB bytes to cdb[]. */
8013 memcpy(scsiqp->cdb, scp->cmnd, scp->cmd_len < 12 ? scp->cmd_len : 12);
8014 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
8015 if (scp->cmd_len > 12) {
8016 int cdb16_len = scp->cmd_len - 12;
8017
8018 memcpy(scsiqp->cdb16, &scp->cmnd[12], cdb16_len);
8019 }
8020
8021 scsiqp->target_id = scp->device->id;
8022 scsiqp->target_lun = scp->device->lun;
8023
8024 sense_addr = dma_map_single(boardp->dev, scp->sense_buffer,
8025 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
8026 scsiqp->sense_addr = cpu_to_le32(sense_addr);
8027 scsiqp->sense_len = cpu_to_le32(SCSI_SENSE_BUFFERSIZE);
8028
8029 /* Build ADV_SCSI_REQ_Q */
8030
8031 use_sg = scsi_dma_map(scp);
8032 if (use_sg == 0) {
8033 /* Zero-length transfer */
8034 reqp->sgblkp = NULL;
8035 scsiqp->data_cnt = 0;
8036
8037 scsiqp->data_addr = 0;
8038 scsiqp->sg_list_ptr = NULL;
8039 scsiqp->sg_real_addr = 0;
8040 } else {
8041 if (use_sg > ADV_MAX_SG_LIST) {
8042 scmd_printk(KERN_ERR, scp, "use_sg %d > "
8043 "ADV_MAX_SG_LIST %d\n", use_sg,
8044 scp->device->host->sg_tablesize);
8045 scsi_dma_unmap(scp);
8046 scp->result = HOST_BYTE(DID_ERROR);
8047 reqp->cmndp = NULL;
8048 scp->host_scribble = NULL;
8049
8050 return ASC_ERROR;
8051 }
8052
8053 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
8054
8055 ret = adv_get_sglist(boardp, reqp, scsiqp, scp, use_sg);
8056 if (ret != ADV_SUCCESS) {
8057 scsi_dma_unmap(scp);
8058 scp->result = HOST_BYTE(DID_ERROR);
8059 reqp->cmndp = NULL;
8060 scp->host_scribble = NULL;
8061
8062 return ret;
8063 }
8064
8065 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
8066 }
8067
8068 ASC_STATS(scp->device->host, xfer_cnt);
8069
8070 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8071 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
8072
8073 *adv_reqpp = reqp;
8074
8075 return ASC_NOERROR;
8076 }
8077
8078 static int AscSgListToQueue(int sg_list)
8079 {
8080 int n_sg_list_qs;
8081
8082 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
8083 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
8084 n_sg_list_qs++;
8085 return n_sg_list_qs + 1;
8086 }
8087
8088 static uint
8089 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
8090 {
8091 uint cur_used_qs;
8092 uint cur_free_qs;
8093 ASC_SCSI_BIT_ID_TYPE target_id;
8094 uchar tid_no;
8095
8096 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
8097 tid_no = ASC_TIX_TO_TID(target_ix);
8098 if ((asc_dvc->unit_not_ready & target_id) ||
8099 (asc_dvc->queue_full_or_busy & target_id)) {
8100 return 0;
8101 }
8102 if (n_qs == 1) {
8103 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8104 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
8105 } else {
8106 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8107 (uint) ASC_MIN_FREE_Q;
8108 }
8109 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
8110 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
8111 if (asc_dvc->cur_dvc_qng[tid_no] >=
8112 asc_dvc->max_dvc_qng[tid_no]) {
8113 return 0;
8114 }
8115 return cur_free_qs;
8116 }
8117 if (n_qs > 1) {
8118 if ((n_qs > asc_dvc->last_q_shortage)
8119 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
8120 asc_dvc->last_q_shortage = n_qs;
8121 }
8122 }
8123 return 0;
8124 }
8125
8126 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
8127 {
8128 ushort q_addr;
8129 uchar next_qp;
8130 uchar q_status;
8131
8132 q_addr = ASC_QNO_TO_QADDR(free_q_head);
8133 q_status = (uchar)AscReadLramByte(iop_base,
8134 (ushort)(q_addr +
8135 ASC_SCSIQ_B_STATUS));
8136 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
8137 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
8138 return next_qp;
8139 return ASC_QLINK_END;
8140 }
8141
8142 static uchar
8143 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
8144 {
8145 uchar i;
8146
8147 for (i = 0; i < n_free_q; i++) {
8148 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
8149 if (free_q_head == ASC_QLINK_END)
8150 break;
8151 }
8152 return free_q_head;
8153 }
8154
8155 /*
8156 * void
8157 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8158 *
8159 * Calling/Exit State:
8160 * none
8161 *
8162 * Description:
8163 * Output an ASC_SCSI_Q structure to the chip
8164 */
8165 static void
8166 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8167 {
8168 int i;
8169
8170 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
8171 AscSetChipLramAddr(iop_base, s_addr);
8172 for (i = 0; i < 2 * words; i += 2) {
8173 if (i == 4 || i == 20) {
8174 continue;
8175 }
8176 outpw(iop_base + IOP_RAM_DATA,
8177 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
8178 }
8179 }
8180
8181 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8182 {
8183 ushort q_addr;
8184 uchar tid_no;
8185 uchar sdtr_data;
8186 uchar syn_period_ix;
8187 uchar syn_offset;
8188 PortAddr iop_base;
8189
8190 iop_base = asc_dvc->iop_base;
8191 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
8192 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
8193 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
8194 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8195 syn_period_ix =
8196 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
8197 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
8198 AscMsgOutSDTR(asc_dvc,
8199 asc_dvc->sdtr_period_tbl[syn_period_ix],
8200 syn_offset);
8201 scsiq->q1.cntl |= QC_MSG_OUT;
8202 }
8203 q_addr = ASC_QNO_TO_QADDR(q_no);
8204 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
8205 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
8206 }
8207 scsiq->q1.status = QS_FREE;
8208 AscMemWordCopyPtrToLram(iop_base,
8209 q_addr + ASC_SCSIQ_CDB_BEG,
8210 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
8211
8212 DvcPutScsiQ(iop_base,
8213 q_addr + ASC_SCSIQ_CPY_BEG,
8214 (uchar *)&scsiq->q1.cntl,
8215 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
8216 AscWriteLramWord(iop_base,
8217 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
8218 (ushort)(((ushort)scsiq->q1.
8219 q_no << 8) | (ushort)QS_READY));
8220 return 1;
8221 }
8222
8223 static int
8224 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8225 {
8226 int sta;
8227 int i;
8228 ASC_SG_HEAD *sg_head;
8229 ASC_SG_LIST_Q scsi_sg_q;
8230 __le32 saved_data_addr;
8231 __le32 saved_data_cnt;
8232 PortAddr iop_base;
8233 ushort sg_list_dwords;
8234 ushort sg_index;
8235 ushort sg_entry_cnt;
8236 ushort q_addr;
8237 uchar next_qp;
8238
8239 iop_base = asc_dvc->iop_base;
8240 sg_head = scsiq->sg_head;
8241 saved_data_addr = scsiq->q1.data_addr;
8242 saved_data_cnt = scsiq->q1.data_cnt;
8243 scsiq->q1.data_addr = sg_head->sg_list[0].addr;
8244 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes;
8245 #if CC_VERY_LONG_SG_LIST
8246 /*
8247 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
8248 * then not all SG elements will fit in the allocated queues.
8249 * The rest of the SG elements will be copied when the RISC
8250 * completes the SG elements that fit and halts.
8251 */
8252 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8253 /*
8254 * Set sg_entry_cnt to be the number of SG elements that
8255 * will fit in the allocated SG queues. It is minus 1, because
8256 * the first SG element is handled above. ASC_MAX_SG_LIST is
8257 * already inflated by 1 to account for this. For example it
8258 * may be 50 which is 1 + 7 queues * 7 SG elements.
8259 */
8260 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
8261
8262 /*
8263 * Keep track of remaining number of SG elements that will
8264 * need to be handled from a_isr.c.
8265 */
8266 scsiq->remain_sg_entry_cnt =
8267 sg_head->entry_cnt - ASC_MAX_SG_LIST;
8268 } else {
8269 #endif /* CC_VERY_LONG_SG_LIST */
8270 /*
8271 * Set sg_entry_cnt to be the number of SG elements that
8272 * will fit in the allocated SG queues. It is minus 1, because
8273 * the first SG element is handled above.
8274 */
8275 sg_entry_cnt = sg_head->entry_cnt - 1;
8276 #if CC_VERY_LONG_SG_LIST
8277 }
8278 #endif /* CC_VERY_LONG_SG_LIST */
8279 if (sg_entry_cnt != 0) {
8280 scsiq->q1.cntl |= QC_SG_HEAD;
8281 q_addr = ASC_QNO_TO_QADDR(q_no);
8282 sg_index = 1;
8283 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
8284 scsi_sg_q.sg_head_qp = q_no;
8285 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
8286 for (i = 0; i < sg_head->queue_cnt; i++) {
8287 scsi_sg_q.seq_no = i + 1;
8288 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
8289 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
8290 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
8291 if (i == 0) {
8292 scsi_sg_q.sg_list_cnt =
8293 ASC_SG_LIST_PER_Q;
8294 scsi_sg_q.sg_cur_list_cnt =
8295 ASC_SG_LIST_PER_Q;
8296 } else {
8297 scsi_sg_q.sg_list_cnt =
8298 ASC_SG_LIST_PER_Q - 1;
8299 scsi_sg_q.sg_cur_list_cnt =
8300 ASC_SG_LIST_PER_Q - 1;
8301 }
8302 } else {
8303 #if CC_VERY_LONG_SG_LIST
8304 /*
8305 * This is the last SG queue in the list of
8306 * allocated SG queues. If there are more
8307 * SG elements than will fit in the allocated
8308 * queues, then set the QCSG_SG_XFER_MORE flag.
8309 */
8310 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8311 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
8312 } else {
8313 #endif /* CC_VERY_LONG_SG_LIST */
8314 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
8315 #if CC_VERY_LONG_SG_LIST
8316 }
8317 #endif /* CC_VERY_LONG_SG_LIST */
8318 sg_list_dwords = sg_entry_cnt << 1;
8319 if (i == 0) {
8320 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
8321 scsi_sg_q.sg_cur_list_cnt =
8322 sg_entry_cnt;
8323 } else {
8324 scsi_sg_q.sg_list_cnt =
8325 sg_entry_cnt - 1;
8326 scsi_sg_q.sg_cur_list_cnt =
8327 sg_entry_cnt - 1;
8328 }
8329 sg_entry_cnt = 0;
8330 }
8331 next_qp = AscReadLramByte(iop_base,
8332 (ushort)(q_addr +
8333 ASC_SCSIQ_B_FWD));
8334 scsi_sg_q.q_no = next_qp;
8335 q_addr = ASC_QNO_TO_QADDR(next_qp);
8336 AscMemWordCopyPtrToLram(iop_base,
8337 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
8338 (uchar *)&scsi_sg_q,
8339 sizeof(ASC_SG_LIST_Q) >> 1);
8340 AscMemDWordCopyPtrToLram(iop_base,
8341 q_addr + ASC_SGQ_LIST_BEG,
8342 (uchar *)&sg_head->
8343 sg_list[sg_index],
8344 sg_list_dwords);
8345 sg_index += ASC_SG_LIST_PER_Q;
8346 scsiq->next_sg_index = sg_index;
8347 }
8348 } else {
8349 scsiq->q1.cntl &= ~QC_SG_HEAD;
8350 }
8351 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
8352 scsiq->q1.data_addr = saved_data_addr;
8353 scsiq->q1.data_cnt = saved_data_cnt;
8354 return (sta);
8355 }
8356
8357 static int
8358 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
8359 {
8360 PortAddr iop_base;
8361 uchar free_q_head;
8362 uchar next_qp;
8363 uchar tid_no;
8364 uchar target_ix;
8365 int sta;
8366
8367 iop_base = asc_dvc->iop_base;
8368 target_ix = scsiq->q2.target_ix;
8369 tid_no = ASC_TIX_TO_TID(target_ix);
8370 sta = 0;
8371 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
8372 if (n_q_required > 1) {
8373 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
8374 (uchar)n_q_required);
8375 if (next_qp != ASC_QLINK_END) {
8376 asc_dvc->last_q_shortage = 0;
8377 scsiq->sg_head->queue_cnt = n_q_required - 1;
8378 scsiq->q1.q_no = free_q_head;
8379 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
8380 free_q_head);
8381 }
8382 } else if (n_q_required == 1) {
8383 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
8384 if (next_qp != ASC_QLINK_END) {
8385 scsiq->q1.q_no = free_q_head;
8386 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
8387 }
8388 }
8389 if (sta == 1) {
8390 AscPutVarFreeQHead(iop_base, next_qp);
8391 asc_dvc->cur_total_qng += n_q_required;
8392 asc_dvc->cur_dvc_qng[tid_no]++;
8393 }
8394 return sta;
8395 }
8396
8397 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
8398 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
8399 INQUIRY,
8400 REQUEST_SENSE,
8401 READ_CAPACITY,
8402 READ_TOC,
8403 MODE_SELECT,
8404 MODE_SENSE,
8405 MODE_SELECT_10,
8406 MODE_SENSE_10,
8407 0xFF,
8408 0xFF,
8409 0xFF,
8410 0xFF,
8411 0xFF,
8412 0xFF,
8413 0xFF,
8414 0xFF
8415 };
8416
8417 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
8418 {
8419 PortAddr iop_base;
8420 int sta;
8421 int n_q_required;
8422 bool disable_syn_offset_one_fix;
8423 int i;
8424 u32 addr;
8425 ushort sg_entry_cnt = 0;
8426 ushort sg_entry_cnt_minus_one = 0;
8427 uchar target_ix;
8428 uchar tid_no;
8429 uchar sdtr_data;
8430 uchar extra_bytes;
8431 uchar scsi_cmd;
8432 uchar disable_cmd;
8433 ASC_SG_HEAD *sg_head;
8434 unsigned long data_cnt;
8435
8436 iop_base = asc_dvc->iop_base;
8437 sg_head = scsiq->sg_head;
8438 if (asc_dvc->err_code != 0)
8439 return ASC_ERROR;
8440 scsiq->q1.q_no = 0;
8441 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
8442 scsiq->q1.extra_bytes = 0;
8443 }
8444 sta = 0;
8445 target_ix = scsiq->q2.target_ix;
8446 tid_no = ASC_TIX_TO_TID(target_ix);
8447 n_q_required = 1;
8448 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
8449 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
8450 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
8451 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8452 AscMsgOutSDTR(asc_dvc,
8453 asc_dvc->
8454 sdtr_period_tbl[(sdtr_data >> 4) &
8455 (uchar)(asc_dvc->
8456 max_sdtr_index -
8457 1)],
8458 (uchar)(sdtr_data & (uchar)
8459 ASC_SYN_MAX_OFFSET));
8460 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
8461 }
8462 }
8463 if (asc_dvc->in_critical_cnt != 0) {
8464 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
8465 return ASC_ERROR;
8466 }
8467 asc_dvc->in_critical_cnt++;
8468 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8469 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
8470 asc_dvc->in_critical_cnt--;
8471 return ASC_ERROR;
8472 }
8473 #if !CC_VERY_LONG_SG_LIST
8474 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8475 asc_dvc->in_critical_cnt--;
8476 return ASC_ERROR;
8477 }
8478 #endif /* !CC_VERY_LONG_SG_LIST */
8479 if (sg_entry_cnt == 1) {
8480 scsiq->q1.data_addr = sg_head->sg_list[0].addr;
8481 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes;
8482 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
8483 }
8484 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
8485 }
8486 scsi_cmd = scsiq->cdbptr[0];
8487 disable_syn_offset_one_fix = false;
8488 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
8489 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
8490 if (scsiq->q1.cntl & QC_SG_HEAD) {
8491 data_cnt = 0;
8492 for (i = 0; i < sg_entry_cnt; i++) {
8493 data_cnt += le32_to_cpu(sg_head->sg_list[i].
8494 bytes);
8495 }
8496 } else {
8497 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
8498 }
8499 if (data_cnt != 0UL) {
8500 if (data_cnt < 512UL) {
8501 disable_syn_offset_one_fix = true;
8502 } else {
8503 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
8504 i++) {
8505 disable_cmd =
8506 _syn_offset_one_disable_cmd[i];
8507 if (disable_cmd == 0xFF) {
8508 break;
8509 }
8510 if (scsi_cmd == disable_cmd) {
8511 disable_syn_offset_one_fix =
8512 true;
8513 break;
8514 }
8515 }
8516 }
8517 }
8518 }
8519 if (disable_syn_offset_one_fix) {
8520 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
8521 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
8522 ASC_TAG_FLAG_DISABLE_DISCONNECT);
8523 } else {
8524 scsiq->q2.tag_code &= 0x27;
8525 }
8526 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8527 if (asc_dvc->bug_fix_cntl) {
8528 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8529 if ((scsi_cmd == READ_6) ||
8530 (scsi_cmd == READ_10)) {
8531 addr = le32_to_cpu(sg_head->
8532 sg_list
8533 [sg_entry_cnt_minus_one].
8534 addr) +
8535 le32_to_cpu(sg_head->
8536 sg_list
8537 [sg_entry_cnt_minus_one].
8538 bytes);
8539 extra_bytes =
8540 (uchar)((ushort)addr & 0x0003);
8541 if ((extra_bytes != 0)
8542 &&
8543 ((scsiq->q2.
8544 tag_code &
8545 ASC_TAG_FLAG_EXTRA_BYTES)
8546 == 0)) {
8547 scsiq->q2.tag_code |=
8548 ASC_TAG_FLAG_EXTRA_BYTES;
8549 scsiq->q1.extra_bytes =
8550 extra_bytes;
8551 data_cnt =
8552 le32_to_cpu(sg_head->
8553 sg_list
8554 [sg_entry_cnt_minus_one].
8555 bytes);
8556 data_cnt -= extra_bytes;
8557 sg_head->
8558 sg_list
8559 [sg_entry_cnt_minus_one].
8560 bytes =
8561 cpu_to_le32(data_cnt);
8562 }
8563 }
8564 }
8565 }
8566 sg_head->entry_to_copy = sg_head->entry_cnt;
8567 #if CC_VERY_LONG_SG_LIST
8568 /*
8569 * Set the sg_entry_cnt to the maximum possible. The rest of
8570 * the SG elements will be copied when the RISC completes the
8571 * SG elements that fit and halts.
8572 */
8573 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8574 sg_entry_cnt = ASC_MAX_SG_LIST;
8575 }
8576 #endif /* CC_VERY_LONG_SG_LIST */
8577 n_q_required = AscSgListToQueue(sg_entry_cnt);
8578 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
8579 (uint) n_q_required)
8580 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8581 if ((sta =
8582 AscSendScsiQueue(asc_dvc, scsiq,
8583 n_q_required)) == 1) {
8584 asc_dvc->in_critical_cnt--;
8585 return (sta);
8586 }
8587 }
8588 } else {
8589 if (asc_dvc->bug_fix_cntl) {
8590 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8591 if ((scsi_cmd == READ_6) ||
8592 (scsi_cmd == READ_10)) {
8593 addr =
8594 le32_to_cpu(scsiq->q1.data_addr) +
8595 le32_to_cpu(scsiq->q1.data_cnt);
8596 extra_bytes =
8597 (uchar)((ushort)addr & 0x0003);
8598 if ((extra_bytes != 0)
8599 &&
8600 ((scsiq->q2.
8601 tag_code &
8602 ASC_TAG_FLAG_EXTRA_BYTES)
8603 == 0)) {
8604 data_cnt =
8605 le32_to_cpu(scsiq->q1.
8606 data_cnt);
8607 if (((ushort)data_cnt & 0x01FF)
8608 == 0) {
8609 scsiq->q2.tag_code |=
8610 ASC_TAG_FLAG_EXTRA_BYTES;
8611 data_cnt -= extra_bytes;
8612 scsiq->q1.data_cnt =
8613 cpu_to_le32
8614 (data_cnt);
8615 scsiq->q1.extra_bytes =
8616 extra_bytes;
8617 }
8618 }
8619 }
8620 }
8621 }
8622 n_q_required = 1;
8623 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
8624 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8625 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
8626 n_q_required)) == 1) {
8627 asc_dvc->in_critical_cnt--;
8628 return (sta);
8629 }
8630 }
8631 }
8632 asc_dvc->in_critical_cnt--;
8633 return (sta);
8634 }
8635
8636 /*
8637 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
8638 *
8639 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
8640 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
8641 * RISC to notify it a new command is ready to be executed.
8642 *
8643 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
8644 * set to SCSI_MAX_RETRY.
8645 *
8646 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
8647 * for DMA addresses or math operations are byte swapped to little-endian
8648 * order.
8649 *
8650 * Return:
8651 * ADV_SUCCESS(1) - The request was successfully queued.
8652 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
8653 * request completes.
8654 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
8655 * host IC error.
8656 */
8657 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, adv_req_t *reqp)
8658 {
8659 AdvPortAddr iop_base;
8660 ADV_CARR_T *new_carrp;
8661 ADV_SCSI_REQ_Q *scsiq = &reqp->scsi_req_q;
8662
8663 /*
8664 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
8665 */
8666 if (scsiq->target_id > ADV_MAX_TID) {
8667 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
8668 scsiq->done_status = QD_WITH_ERROR;
8669 return ADV_ERROR;
8670 }
8671
8672 iop_base = asc_dvc->iop_base;
8673
8674 /*
8675 * Allocate a carrier ensuring at least one carrier always
8676 * remains on the freelist and initialize fields.
8677 */
8678 new_carrp = adv_get_next_carrier(asc_dvc);
8679 if (!new_carrp) {
8680 ASC_DBG(1, "No free carriers\n");
8681 return ADV_BUSY;
8682 }
8683
8684 asc_dvc->carr_pending_cnt++;
8685
8686 /*
8687 * Clear the ADV_SCSI_REQ_Q done flag.
8688 */
8689 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
8690
8691 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
8692 scsiq->scsiq_ptr = cpu_to_le32(scsiq->srb_tag);
8693 scsiq->scsiq_rptr = cpu_to_le32(reqp->req_addr);
8694
8695 scsiq->carr_va = asc_dvc->icq_sp->carr_va;
8696 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
8697
8698 /*
8699 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
8700 * the microcode. The newly allocated stopper will become the new
8701 * stopper.
8702 */
8703 asc_dvc->icq_sp->areq_vpa = scsiq->scsiq_rptr;
8704
8705 /*
8706 * Set the 'next_vpa' pointer for the old stopper to be the
8707 * physical address of the new stopper. The RISC can only
8708 * follow physical addresses.
8709 */
8710 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
8711
8712 /*
8713 * Set the host adapter stopper pointer to point to the new carrier.
8714 */
8715 asc_dvc->icq_sp = new_carrp;
8716
8717 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8718 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8719 /*
8720 * Tickle the RISC to tell it to read its Command Queue Head pointer.
8721 */
8722 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
8723 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8724 /*
8725 * Clear the tickle value. In the ASC-3550 the RISC flag
8726 * command 'clr_tickle_a' does not work unless the host
8727 * value is cleared.
8728 */
8729 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8730 ADV_TICKLE_NOP);
8731 }
8732 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8733 /*
8734 * Notify the RISC a carrier is ready by writing the physical
8735 * address of the new carrier stopper to the COMMA register.
8736 */
8737 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8738 le32_to_cpu(new_carrp->carr_pa));
8739 }
8740
8741 return ADV_SUCCESS;
8742 }
8743
8744 /*
8745 * Execute a single 'Scsi_Cmnd'.
8746 */
8747 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
8748 {
8749 int ret, err_code;
8750 struct asc_board *boardp = shost_priv(scp->device->host);
8751
8752 ASC_DBG(1, "scp 0x%p\n", scp);
8753
8754 if (ASC_NARROW_BOARD(boardp)) {
8755 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
8756 struct asc_scsi_q asc_scsi_q;
8757
8758 /* asc_build_req() can not return ASC_BUSY. */
8759 ret = asc_build_req(boardp, scp, &asc_scsi_q);
8760 if (ret == ASC_ERROR) {
8761 ASC_STATS(scp->device->host, build_error);
8762 return ASC_ERROR;
8763 }
8764
8765 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
8766 kfree(asc_scsi_q.sg_head);
8767 err_code = asc_dvc->err_code;
8768 } else {
8769 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
8770 adv_req_t *adv_reqp;
8771
8772 switch (adv_build_req(boardp, scp, &adv_reqp)) {
8773 case ASC_NOERROR:
8774 ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
8775 break;
8776 case ASC_BUSY:
8777 ASC_DBG(1, "adv_build_req ASC_BUSY\n");
8778 /*
8779 * The asc_stats fields 'adv_build_noreq' and
8780 * 'adv_build_nosg' count wide board busy conditions.
8781 * They are updated in adv_build_req and
8782 * adv_get_sglist, respectively.
8783 */
8784 return ASC_BUSY;
8785 case ASC_ERROR:
8786 default:
8787 ASC_DBG(1, "adv_build_req ASC_ERROR\n");
8788 ASC_STATS(scp->device->host, build_error);
8789 return ASC_ERROR;
8790 }
8791
8792 ret = AdvExeScsiQueue(adv_dvc, adv_reqp);
8793 err_code = adv_dvc->err_code;
8794 }
8795
8796 switch (ret) {
8797 case ASC_NOERROR:
8798 ASC_STATS(scp->device->host, exe_noerror);
8799 /*
8800 * Increment monotonically increasing per device
8801 * successful request counter. Wrapping doesn't matter.
8802 */
8803 boardp->reqcnt[scp->device->id]++;
8804 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
8805 break;
8806 case ASC_BUSY:
8807 ASC_DBG(1, "ExeScsiQueue() ASC_BUSY\n");
8808 ASC_STATS(scp->device->host, exe_busy);
8809 break;
8810 case ASC_ERROR:
8811 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
8812 "err_code 0x%x\n", err_code);
8813 ASC_STATS(scp->device->host, exe_error);
8814 scp->result = HOST_BYTE(DID_ERROR);
8815 break;
8816 default:
8817 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
8818 "err_code 0x%x\n", err_code);
8819 ASC_STATS(scp->device->host, exe_unknown);
8820 scp->result = HOST_BYTE(DID_ERROR);
8821 break;
8822 }
8823
8824 ASC_DBG(1, "end\n");
8825 return ret;
8826 }
8827
8828 /*
8829 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
8830 *
8831 * This function always returns 0. Command return status is saved
8832 * in the 'scp' result field.
8833 */
8834 static int
8835 advansys_queuecommand_lck(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
8836 {
8837 struct Scsi_Host *shost = scp->device->host;
8838 int asc_res, result = 0;
8839
8840 ASC_STATS(shost, queuecommand);
8841 scp->scsi_done = done;
8842
8843 asc_res = asc_execute_scsi_cmnd(scp);
8844
8845 switch (asc_res) {
8846 case ASC_NOERROR:
8847 break;
8848 case ASC_BUSY:
8849 result = SCSI_MLQUEUE_HOST_BUSY;
8850 break;
8851 case ASC_ERROR:
8852 default:
8853 asc_scsi_done(scp);
8854 break;
8855 }
8856
8857 return result;
8858 }
8859
8860 static DEF_SCSI_QCMD(advansys_queuecommand)
8861
8862 static ushort AscGetEisaChipCfg(PortAddr iop_base)
8863 {
8864 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8865 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
8866 return inpw(eisa_cfg_iop);
8867 }
8868
8869 /*
8870 * Return the BIOS address of the adapter at the specified
8871 * I/O port and with the specified bus type.
8872 */
8873 static unsigned short AscGetChipBiosAddress(PortAddr iop_base,
8874 unsigned short bus_type)
8875 {
8876 unsigned short cfg_lsw;
8877 unsigned short bios_addr;
8878
8879 /*
8880 * The PCI BIOS is re-located by the motherboard BIOS. Because
8881 * of this the driver can not determine where a PCI BIOS is
8882 * loaded and executes.
8883 */
8884 if (bus_type & ASC_IS_PCI)
8885 return 0;
8886
8887 if ((bus_type & ASC_IS_EISA) != 0) {
8888 cfg_lsw = AscGetEisaChipCfg(iop_base);
8889 cfg_lsw &= 0x000F;
8890 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
8891 return bios_addr;
8892 }
8893
8894 cfg_lsw = AscGetChipCfgLsw(iop_base);
8895
8896 /*
8897 * ISA PnP uses the top bit as the 32K BIOS flag
8898 */
8899 if (bus_type == ASC_IS_ISAPNP)
8900 cfg_lsw &= 0x7FFF;
8901 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
8902 return bios_addr;
8903 }
8904
8905 static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
8906 {
8907 ushort cfg_lsw;
8908
8909 if (AscGetChipScsiID(iop_base) == new_host_id) {
8910 return (new_host_id);
8911 }
8912 cfg_lsw = AscGetChipCfgLsw(iop_base);
8913 cfg_lsw &= 0xF8FF;
8914 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
8915 AscSetChipCfgLsw(iop_base, cfg_lsw);
8916 return (AscGetChipScsiID(iop_base));
8917 }
8918
8919 static unsigned char AscGetChipScsiCtrl(PortAddr iop_base)
8920 {
8921 unsigned char sc;
8922
8923 AscSetBank(iop_base, 1);
8924 sc = inp(iop_base + IOP_REG_SC);
8925 AscSetBank(iop_base, 0);
8926 return sc;
8927 }
8928
8929 static unsigned char AscGetChipVersion(PortAddr iop_base,
8930 unsigned short bus_type)
8931 {
8932 if (bus_type & ASC_IS_EISA) {
8933 PortAddr eisa_iop;
8934 unsigned char revision;
8935 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8936 (PortAddr) ASC_EISA_REV_IOP_MASK;
8937 revision = inp(eisa_iop);
8938 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
8939 }
8940 return AscGetChipVerNo(iop_base);
8941 }
8942
8943 #ifdef CONFIG_ISA
8944 static void AscEnableIsaDma(uchar dma_channel)
8945 {
8946 if (dma_channel < 4) {
8947 outp(0x000B, (ushort)(0xC0 | dma_channel));
8948 outp(0x000A, dma_channel);
8949 } else if (dma_channel < 8) {
8950 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
8951 outp(0x00D4, (ushort)(dma_channel - 4));
8952 }
8953 }
8954 #endif /* CONFIG_ISA */
8955
8956 static int AscStopQueueExe(PortAddr iop_base)
8957 {
8958 int count = 0;
8959
8960 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
8961 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
8962 ASC_STOP_REQ_RISC_STOP);
8963 do {
8964 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
8965 ASC_STOP_ACK_RISC_STOP) {
8966 return (1);
8967 }
8968 mdelay(100);
8969 } while (count++ < 20);
8970 }
8971 return (0);
8972 }
8973
8974 static unsigned int AscGetMaxDmaCount(ushort bus_type)
8975 {
8976 if (bus_type & ASC_IS_ISA)
8977 return ASC_MAX_ISA_DMA_COUNT;
8978 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
8979 return ASC_MAX_VL_DMA_COUNT;
8980 return ASC_MAX_PCI_DMA_COUNT;
8981 }
8982
8983 #ifdef CONFIG_ISA
8984 static ushort AscGetIsaDmaChannel(PortAddr iop_base)
8985 {
8986 ushort channel;
8987
8988 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
8989 if (channel == 0x03)
8990 return (0);
8991 else if (channel == 0x00)
8992 return (7);
8993 return (channel + 4);
8994 }
8995
8996 static ushort AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
8997 {
8998 ushort cfg_lsw;
8999 uchar value;
9000
9001 if ((dma_channel >= 5) && (dma_channel <= 7)) {
9002 if (dma_channel == 7)
9003 value = 0x00;
9004 else
9005 value = dma_channel - 4;
9006 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
9007 cfg_lsw |= value;
9008 AscSetChipCfgLsw(iop_base, cfg_lsw);
9009 return (AscGetIsaDmaChannel(iop_base));
9010 }
9011 return 0;
9012 }
9013
9014 static uchar AscGetIsaDmaSpeed(PortAddr iop_base)
9015 {
9016 uchar speed_value;
9017
9018 AscSetBank(iop_base, 1);
9019 speed_value = AscReadChipDmaSpeed(iop_base);
9020 speed_value &= 0x07;
9021 AscSetBank(iop_base, 0);
9022 return speed_value;
9023 }
9024
9025 static uchar AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
9026 {
9027 speed_value &= 0x07;
9028 AscSetBank(iop_base, 1);
9029 AscWriteChipDmaSpeed(iop_base, speed_value);
9030 AscSetBank(iop_base, 0);
9031 return AscGetIsaDmaSpeed(iop_base);
9032 }
9033 #endif /* CONFIG_ISA */
9034
9035 static ushort AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
9036 {
9037 int i;
9038 PortAddr iop_base;
9039 ushort warn_code;
9040 uchar chip_version;
9041
9042 iop_base = asc_dvc->iop_base;
9043 warn_code = 0;
9044 asc_dvc->err_code = 0;
9045 if ((asc_dvc->bus_type &
9046 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
9047 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
9048 }
9049 AscSetChipControl(iop_base, CC_HALT);
9050 AscSetChipStatus(iop_base, 0);
9051 asc_dvc->bug_fix_cntl = 0;
9052 asc_dvc->pci_fix_asyn_xfer = 0;
9053 asc_dvc->pci_fix_asyn_xfer_always = 0;
9054 /* asc_dvc->init_state initialized in AscInitGetConfig(). */
9055 asc_dvc->sdtr_done = 0;
9056 asc_dvc->cur_total_qng = 0;
9057 asc_dvc->is_in_int = false;
9058 asc_dvc->in_critical_cnt = 0;
9059 asc_dvc->last_q_shortage = 0;
9060 asc_dvc->use_tagged_qng = 0;
9061 asc_dvc->no_scam = 0;
9062 asc_dvc->unit_not_ready = 0;
9063 asc_dvc->queue_full_or_busy = 0;
9064 asc_dvc->redo_scam = 0;
9065 asc_dvc->res2 = 0;
9066 asc_dvc->min_sdtr_index = 0;
9067 asc_dvc->cfg->can_tagged_qng = 0;
9068 asc_dvc->cfg->cmd_qng_enabled = 0;
9069 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
9070 asc_dvc->init_sdtr = 0;
9071 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
9072 asc_dvc->scsi_reset_wait = 3;
9073 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
9074 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
9075 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
9076 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
9077 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
9078 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
9079 asc_dvc->cfg->chip_version = chip_version;
9080 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
9081 asc_dvc->max_sdtr_index = 7;
9082 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
9083 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
9084 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
9085 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
9086 asc_dvc->max_sdtr_index = 15;
9087 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
9088 AscSetExtraControl(iop_base,
9089 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9090 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
9091 AscSetExtraControl(iop_base,
9092 (SEC_ACTIVE_NEGATE |
9093 SEC_ENABLE_FILTER));
9094 }
9095 }
9096 if (asc_dvc->bus_type == ASC_IS_PCI) {
9097 AscSetExtraControl(iop_base,
9098 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9099 }
9100
9101 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
9102 #ifdef CONFIG_ISA
9103 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
9104 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
9105 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
9106 asc_dvc->bus_type = ASC_IS_ISAPNP;
9107 }
9108 asc_dvc->cfg->isa_dma_channel =
9109 (uchar)AscGetIsaDmaChannel(iop_base);
9110 }
9111 #endif /* CONFIG_ISA */
9112 for (i = 0; i <= ASC_MAX_TID; i++) {
9113 asc_dvc->cur_dvc_qng[i] = 0;
9114 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
9115 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
9116 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
9117 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
9118 }
9119 return warn_code;
9120 }
9121
9122 static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
9123 {
9124 int retry;
9125
9126 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
9127 unsigned char read_back;
9128 AscSetChipEEPCmd(iop_base, cmd_reg);
9129 mdelay(1);
9130 read_back = AscGetChipEEPCmd(iop_base);
9131 if (read_back == cmd_reg)
9132 return 1;
9133 }
9134 return 0;
9135 }
9136
9137 static void AscWaitEEPRead(void)
9138 {
9139 mdelay(1);
9140 }
9141
9142 static ushort AscReadEEPWord(PortAddr iop_base, uchar addr)
9143 {
9144 ushort read_wval;
9145 uchar cmd_reg;
9146
9147 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9148 AscWaitEEPRead();
9149 cmd_reg = addr | ASC_EEP_CMD_READ;
9150 AscWriteEEPCmdReg(iop_base, cmd_reg);
9151 AscWaitEEPRead();
9152 read_wval = AscGetChipEEPData(iop_base);
9153 AscWaitEEPRead();
9154 return read_wval;
9155 }
9156
9157 static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9158 ushort bus_type)
9159 {
9160 ushort wval;
9161 ushort sum;
9162 ushort *wbuf;
9163 int cfg_beg;
9164 int cfg_end;
9165 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9166 int s_addr;
9167
9168 wbuf = (ushort *)cfg_buf;
9169 sum = 0;
9170 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
9171 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9172 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9173 sum += *wbuf;
9174 }
9175 if (bus_type & ASC_IS_VL) {
9176 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9177 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9178 } else {
9179 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9180 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9181 }
9182 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9183 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
9184 if (s_addr <= uchar_end_in_config) {
9185 /*
9186 * Swap all char fields - must unswap bytes already swapped
9187 * by AscReadEEPWord().
9188 */
9189 *wbuf = le16_to_cpu(wval);
9190 } else {
9191 /* Don't swap word field at the end - cntl field. */
9192 *wbuf = wval;
9193 }
9194 sum += wval; /* Checksum treats all EEPROM data as words. */
9195 }
9196 /*
9197 * Read the checksum word which will be compared against 'sum'
9198 * by the caller. Word field already swapped.
9199 */
9200 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9201 return sum;
9202 }
9203
9204 static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
9205 {
9206 PortAddr iop_base;
9207 ushort q_addr;
9208 ushort saved_word;
9209 int sta;
9210
9211 iop_base = asc_dvc->iop_base;
9212 sta = 0;
9213 q_addr = ASC_QNO_TO_QADDR(241);
9214 saved_word = AscReadLramWord(iop_base, q_addr);
9215 AscSetChipLramAddr(iop_base, q_addr);
9216 AscSetChipLramData(iop_base, 0x55AA);
9217 mdelay(10);
9218 AscSetChipLramAddr(iop_base, q_addr);
9219 if (AscGetChipLramData(iop_base) == 0x55AA) {
9220 sta = 1;
9221 AscWriteLramWord(iop_base, q_addr, saved_word);
9222 }
9223 return (sta);
9224 }
9225
9226 static void AscWaitEEPWrite(void)
9227 {
9228 mdelay(20);
9229 }
9230
9231 static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
9232 {
9233 ushort read_back;
9234 int retry;
9235
9236 retry = 0;
9237 while (true) {
9238 AscSetChipEEPData(iop_base, data_reg);
9239 mdelay(1);
9240 read_back = AscGetChipEEPData(iop_base);
9241 if (read_back == data_reg) {
9242 return (1);
9243 }
9244 if (retry++ > ASC_EEP_MAX_RETRY) {
9245 return (0);
9246 }
9247 }
9248 }
9249
9250 static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
9251 {
9252 ushort read_wval;
9253
9254 read_wval = AscReadEEPWord(iop_base, addr);
9255 if (read_wval != word_val) {
9256 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
9257 AscWaitEEPRead();
9258 AscWriteEEPDataReg(iop_base, word_val);
9259 AscWaitEEPRead();
9260 AscWriteEEPCmdReg(iop_base,
9261 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
9262 AscWaitEEPWrite();
9263 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9264 AscWaitEEPRead();
9265 return (AscReadEEPWord(iop_base, addr));
9266 }
9267 return (read_wval);
9268 }
9269
9270 static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9271 ushort bus_type)
9272 {
9273 int n_error;
9274 ushort *wbuf;
9275 ushort word;
9276 ushort sum;
9277 int s_addr;
9278 int cfg_beg;
9279 int cfg_end;
9280 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9281
9282 wbuf = (ushort *)cfg_buf;
9283 n_error = 0;
9284 sum = 0;
9285 /* Write two config words; AscWriteEEPWord() will swap bytes. */
9286 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9287 sum += *wbuf;
9288 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9289 n_error++;
9290 }
9291 }
9292 if (bus_type & ASC_IS_VL) {
9293 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9294 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9295 } else {
9296 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9297 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9298 }
9299 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9300 if (s_addr <= uchar_end_in_config) {
9301 /*
9302 * This is a char field. Swap char fields before they are
9303 * swapped again by AscWriteEEPWord().
9304 */
9305 word = cpu_to_le16(*wbuf);
9306 if (word !=
9307 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
9308 n_error++;
9309 }
9310 } else {
9311 /* Don't swap word field at the end - cntl field. */
9312 if (*wbuf !=
9313 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9314 n_error++;
9315 }
9316 }
9317 sum += *wbuf; /* Checksum calculated from word values. */
9318 }
9319 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
9320 *wbuf = sum;
9321 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
9322 n_error++;
9323 }
9324
9325 /* Read EEPROM back again. */
9326 wbuf = (ushort *)cfg_buf;
9327 /*
9328 * Read two config words; Byte-swapping done by AscReadEEPWord().
9329 */
9330 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9331 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
9332 n_error++;
9333 }
9334 }
9335 if (bus_type & ASC_IS_VL) {
9336 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9337 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9338 } else {
9339 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9340 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9341 }
9342 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9343 if (s_addr <= uchar_end_in_config) {
9344 /*
9345 * Swap all char fields. Must unswap bytes already swapped
9346 * by AscReadEEPWord().
9347 */
9348 word =
9349 le16_to_cpu(AscReadEEPWord
9350 (iop_base, (uchar)s_addr));
9351 } else {
9352 /* Don't swap word field at the end - cntl field. */
9353 word = AscReadEEPWord(iop_base, (uchar)s_addr);
9354 }
9355 if (*wbuf != word) {
9356 n_error++;
9357 }
9358 }
9359 /* Read checksum; Byte swapping not needed. */
9360 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
9361 n_error++;
9362 }
9363 return n_error;
9364 }
9365
9366 static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9367 ushort bus_type)
9368 {
9369 int retry;
9370 int n_error;
9371
9372 retry = 0;
9373 while (true) {
9374 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
9375 bus_type)) == 0) {
9376 break;
9377 }
9378 if (++retry > ASC_EEP_MAX_RETRY) {
9379 break;
9380 }
9381 }
9382 return n_error;
9383 }
9384
9385 static ushort AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
9386 {
9387 ASCEEP_CONFIG eep_config_buf;
9388 ASCEEP_CONFIG *eep_config;
9389 PortAddr iop_base;
9390 ushort chksum;
9391 ushort warn_code;
9392 ushort cfg_msw, cfg_lsw;
9393 int i;
9394 int write_eep = 0;
9395
9396 iop_base = asc_dvc->iop_base;
9397 warn_code = 0;
9398 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
9399 AscStopQueueExe(iop_base);
9400 if ((AscStopChip(iop_base)) ||
9401 (AscGetChipScsiCtrl(iop_base) != 0)) {
9402 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
9403 AscResetChipAndScsiBus(asc_dvc);
9404 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
9405 }
9406 if (!AscIsChipHalted(iop_base)) {
9407 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
9408 return (warn_code);
9409 }
9410 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
9411 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
9412 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
9413 return (warn_code);
9414 }
9415 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
9416 cfg_msw = AscGetChipCfgMsw(iop_base);
9417 cfg_lsw = AscGetChipCfgLsw(iop_base);
9418 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9419 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9420 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9421 AscSetChipCfgMsw(iop_base, cfg_msw);
9422 }
9423 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
9424 ASC_DBG(1, "chksum 0x%x\n", chksum);
9425 if (chksum == 0) {
9426 chksum = 0xaa55;
9427 }
9428 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9429 warn_code |= ASC_WARN_AUTO_CONFIG;
9430 if (asc_dvc->cfg->chip_version == 3) {
9431 if (eep_config->cfg_lsw != cfg_lsw) {
9432 warn_code |= ASC_WARN_EEPROM_RECOVER;
9433 eep_config->cfg_lsw =
9434 AscGetChipCfgLsw(iop_base);
9435 }
9436 if (eep_config->cfg_msw != cfg_msw) {
9437 warn_code |= ASC_WARN_EEPROM_RECOVER;
9438 eep_config->cfg_msw =
9439 AscGetChipCfgMsw(iop_base);
9440 }
9441 }
9442 }
9443 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9444 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
9445 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
9446 if (chksum != eep_config->chksum) {
9447 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
9448 ASC_CHIP_VER_PCI_ULTRA_3050) {
9449 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
9450 eep_config->init_sdtr = 0xFF;
9451 eep_config->disc_enable = 0xFF;
9452 eep_config->start_motor = 0xFF;
9453 eep_config->use_cmd_qng = 0;
9454 eep_config->max_total_qng = 0xF0;
9455 eep_config->max_tag_qng = 0x20;
9456 eep_config->cntl = 0xBFFF;
9457 ASC_EEP_SET_CHIP_ID(eep_config, 7);
9458 eep_config->no_scam = 0;
9459 eep_config->adapter_info[0] = 0;
9460 eep_config->adapter_info[1] = 0;
9461 eep_config->adapter_info[2] = 0;
9462 eep_config->adapter_info[3] = 0;
9463 eep_config->adapter_info[4] = 0;
9464 /* Indicate EEPROM-less board. */
9465 eep_config->adapter_info[5] = 0xBB;
9466 } else {
9467 ASC_PRINT
9468 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
9469 write_eep = 1;
9470 warn_code |= ASC_WARN_EEPROM_CHKSUM;
9471 }
9472 }
9473 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
9474 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
9475 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
9476 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
9477 asc_dvc->start_motor = eep_config->start_motor;
9478 asc_dvc->dvc_cntl = eep_config->cntl;
9479 asc_dvc->no_scam = eep_config->no_scam;
9480 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
9481 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
9482 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
9483 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
9484 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
9485 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
9486 if (!AscTestExternalLram(asc_dvc)) {
9487 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
9488 ASC_IS_PCI_ULTRA)) {
9489 eep_config->max_total_qng =
9490 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
9491 eep_config->max_tag_qng =
9492 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
9493 } else {
9494 eep_config->cfg_msw |= 0x0800;
9495 cfg_msw |= 0x0800;
9496 AscSetChipCfgMsw(iop_base, cfg_msw);
9497 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
9498 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
9499 }
9500 } else {
9501 }
9502 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
9503 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
9504 }
9505 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
9506 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
9507 }
9508 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
9509 eep_config->max_tag_qng = eep_config->max_total_qng;
9510 }
9511 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
9512 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
9513 }
9514 asc_dvc->max_total_qng = eep_config->max_total_qng;
9515 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
9516 eep_config->use_cmd_qng) {
9517 eep_config->disc_enable = eep_config->use_cmd_qng;
9518 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9519 }
9520 ASC_EEP_SET_CHIP_ID(eep_config,
9521 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
9522 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
9523 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
9524 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
9525 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
9526 }
9527
9528 for (i = 0; i <= ASC_MAX_TID; i++) {
9529 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
9530 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
9531 asc_dvc->cfg->sdtr_period_offset[i] =
9532 (uchar)(ASC_DEF_SDTR_OFFSET |
9533 (asc_dvc->min_sdtr_index << 4));
9534 }
9535 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
9536 if (write_eep) {
9537 if ((i = AscSetEEPConfig(iop_base, eep_config,
9538 asc_dvc->bus_type)) != 0) {
9539 ASC_PRINT1
9540 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
9541 i);
9542 } else {
9543 ASC_PRINT
9544 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
9545 }
9546 }
9547 return (warn_code);
9548 }
9549
9550 static int AscInitGetConfig(struct Scsi_Host *shost)
9551 {
9552 struct asc_board *board = shost_priv(shost);
9553 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9554 unsigned short warn_code = 0;
9555
9556 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
9557 if (asc_dvc->err_code != 0)
9558 return asc_dvc->err_code;
9559
9560 if (AscFindSignature(asc_dvc->iop_base)) {
9561 warn_code |= AscInitAscDvcVar(asc_dvc);
9562 warn_code |= AscInitFromEEP(asc_dvc);
9563 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
9564 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
9565 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
9566 } else {
9567 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9568 }
9569
9570 switch (warn_code) {
9571 case 0: /* No error */
9572 break;
9573 case ASC_WARN_IO_PORT_ROTATE:
9574 shost_printk(KERN_WARNING, shost, "I/O port address "
9575 "modified\n");
9576 break;
9577 case ASC_WARN_AUTO_CONFIG:
9578 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9579 "enabled\n");
9580 break;
9581 case ASC_WARN_EEPROM_CHKSUM:
9582 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9583 break;
9584 case ASC_WARN_IRQ_MODIFIED:
9585 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9586 break;
9587 case ASC_WARN_CMD_QNG_CONFLICT:
9588 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
9589 "disconnects\n");
9590 break;
9591 default:
9592 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9593 warn_code);
9594 break;
9595 }
9596
9597 if (asc_dvc->err_code != 0)
9598 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9599 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9600
9601 return asc_dvc->err_code;
9602 }
9603
9604 static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
9605 {
9606 struct asc_board *board = shost_priv(shost);
9607 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9608 PortAddr iop_base = asc_dvc->iop_base;
9609 unsigned short cfg_msw;
9610 unsigned short warn_code = 0;
9611
9612 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
9613 if (asc_dvc->err_code != 0)
9614 return asc_dvc->err_code;
9615 if (!AscFindSignature(asc_dvc->iop_base)) {
9616 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9617 return asc_dvc->err_code;
9618 }
9619
9620 cfg_msw = AscGetChipCfgMsw(iop_base);
9621 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9622 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9623 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9624 AscSetChipCfgMsw(iop_base, cfg_msw);
9625 }
9626 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
9627 asc_dvc->cfg->cmd_qng_enabled) {
9628 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
9629 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9630 }
9631 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9632 warn_code |= ASC_WARN_AUTO_CONFIG;
9633 }
9634 #ifdef CONFIG_PCI
9635 if (asc_dvc->bus_type & ASC_IS_PCI) {
9636 cfg_msw &= 0xFFC0;
9637 AscSetChipCfgMsw(iop_base, cfg_msw);
9638 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
9639 } else {
9640 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
9641 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
9642 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
9643 asc_dvc->bug_fix_cntl |=
9644 ASC_BUG_FIX_ASYN_USE_SYN;
9645 }
9646 }
9647 } else
9648 #endif /* CONFIG_PCI */
9649 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
9650 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
9651 == ASC_CHIP_VER_ASYN_BUG) {
9652 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
9653 }
9654 }
9655 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
9656 asc_dvc->cfg->chip_scsi_id) {
9657 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
9658 }
9659 #ifdef CONFIG_ISA
9660 if (asc_dvc->bus_type & ASC_IS_ISA) {
9661 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
9662 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
9663 }
9664 #endif /* CONFIG_ISA */
9665
9666 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
9667
9668 switch (warn_code) {
9669 case 0: /* No error. */
9670 break;
9671 case ASC_WARN_IO_PORT_ROTATE:
9672 shost_printk(KERN_WARNING, shost, "I/O port address "
9673 "modified\n");
9674 break;
9675 case ASC_WARN_AUTO_CONFIG:
9676 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9677 "enabled\n");
9678 break;
9679 case ASC_WARN_EEPROM_CHKSUM:
9680 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9681 break;
9682 case ASC_WARN_IRQ_MODIFIED:
9683 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9684 break;
9685 case ASC_WARN_CMD_QNG_CONFLICT:
9686 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
9687 "disconnects\n");
9688 break;
9689 default:
9690 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9691 warn_code);
9692 break;
9693 }
9694
9695 if (asc_dvc->err_code != 0)
9696 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9697 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9698
9699 return asc_dvc->err_code;
9700 }
9701
9702 /*
9703 * EEPROM Configuration.
9704 *
9705 * All drivers should use this structure to set the default EEPROM
9706 * configuration. The BIOS now uses this structure when it is built.
9707 * Additional structure information can be found in a_condor.h where
9708 * the structure is defined.
9709 *
9710 * The *_Field_IsChar structs are needed to correct for endianness.
9711 * These values are read from the board 16 bits at a time directly
9712 * into the structs. Because some fields are char, the values will be
9713 * in the wrong order. The *_Field_IsChar tells when to flip the
9714 * bytes. Data read and written to PCI memory is automatically swapped
9715 * on big-endian platforms so char fields read as words are actually being
9716 * unswapped on big-endian platforms.
9717 */
9718 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = {
9719 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
9720 0x0000, /* cfg_msw */
9721 0xFFFF, /* disc_enable */
9722 0xFFFF, /* wdtr_able */
9723 0xFFFF, /* sdtr_able */
9724 0xFFFF, /* start_motor */
9725 0xFFFF, /* tagqng_able */
9726 0xFFFF, /* bios_scan */
9727 0, /* scam_tolerant */
9728 7, /* adapter_scsi_id */
9729 0, /* bios_boot_delay */
9730 3, /* scsi_reset_delay */
9731 0, /* bios_id_lun */
9732 0, /* termination */
9733 0, /* reserved1 */
9734 0xFFE7, /* bios_ctrl */
9735 0xFFFF, /* ultra_able */
9736 0, /* reserved2 */
9737 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
9738 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9739 0, /* dvc_cntl */
9740 0, /* bug_fix */
9741 0, /* serial_number_word1 */
9742 0, /* serial_number_word2 */
9743 0, /* serial_number_word3 */
9744 0, /* check_sum */
9745 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9746 , /* oem_name[16] */
9747 0, /* dvc_err_code */
9748 0, /* adv_err_code */
9749 0, /* adv_err_addr */
9750 0, /* saved_dvc_err_code */
9751 0, /* saved_adv_err_code */
9752 0, /* saved_adv_err_addr */
9753 0 /* num_of_err */
9754 };
9755
9756 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = {
9757 0, /* cfg_lsw */
9758 0, /* cfg_msw */
9759 0, /* -disc_enable */
9760 0, /* wdtr_able */
9761 0, /* sdtr_able */
9762 0, /* start_motor */
9763 0, /* tagqng_able */
9764 0, /* bios_scan */
9765 0, /* scam_tolerant */
9766 1, /* adapter_scsi_id */
9767 1, /* bios_boot_delay */
9768 1, /* scsi_reset_delay */
9769 1, /* bios_id_lun */
9770 1, /* termination */
9771 1, /* reserved1 */
9772 0, /* bios_ctrl */
9773 0, /* ultra_able */
9774 0, /* reserved2 */
9775 1, /* max_host_qng */
9776 1, /* max_dvc_qng */
9777 0, /* dvc_cntl */
9778 0, /* bug_fix */
9779 0, /* serial_number_word1 */
9780 0, /* serial_number_word2 */
9781 0, /* serial_number_word3 */
9782 0, /* check_sum */
9783 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9784 , /* oem_name[16] */
9785 0, /* dvc_err_code */
9786 0, /* adv_err_code */
9787 0, /* adv_err_addr */
9788 0, /* saved_dvc_err_code */
9789 0, /* saved_adv_err_code */
9790 0, /* saved_adv_err_addr */
9791 0 /* num_of_err */
9792 };
9793
9794 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = {
9795 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9796 0x0000, /* 01 cfg_msw */
9797 0xFFFF, /* 02 disc_enable */
9798 0xFFFF, /* 03 wdtr_able */
9799 0x4444, /* 04 sdtr_speed1 */
9800 0xFFFF, /* 05 start_motor */
9801 0xFFFF, /* 06 tagqng_able */
9802 0xFFFF, /* 07 bios_scan */
9803 0, /* 08 scam_tolerant */
9804 7, /* 09 adapter_scsi_id */
9805 0, /* bios_boot_delay */
9806 3, /* 10 scsi_reset_delay */
9807 0, /* bios_id_lun */
9808 0, /* 11 termination_se */
9809 0, /* termination_lvd */
9810 0xFFE7, /* 12 bios_ctrl */
9811 0x4444, /* 13 sdtr_speed2 */
9812 0x4444, /* 14 sdtr_speed3 */
9813 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9814 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9815 0, /* 16 dvc_cntl */
9816 0x4444, /* 17 sdtr_speed4 */
9817 0, /* 18 serial_number_word1 */
9818 0, /* 19 serial_number_word2 */
9819 0, /* 20 serial_number_word3 */
9820 0, /* 21 check_sum */
9821 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9822 , /* 22-29 oem_name[16] */
9823 0, /* 30 dvc_err_code */
9824 0, /* 31 adv_err_code */
9825 0, /* 32 adv_err_addr */
9826 0, /* 33 saved_dvc_err_code */
9827 0, /* 34 saved_adv_err_code */
9828 0, /* 35 saved_adv_err_addr */
9829 0, /* 36 reserved */
9830 0, /* 37 reserved */
9831 0, /* 38 reserved */
9832 0, /* 39 reserved */
9833 0, /* 40 reserved */
9834 0, /* 41 reserved */
9835 0, /* 42 reserved */
9836 0, /* 43 reserved */
9837 0, /* 44 reserved */
9838 0, /* 45 reserved */
9839 0, /* 46 reserved */
9840 0, /* 47 reserved */
9841 0, /* 48 reserved */
9842 0, /* 49 reserved */
9843 0, /* 50 reserved */
9844 0, /* 51 reserved */
9845 0, /* 52 reserved */
9846 0, /* 53 reserved */
9847 0, /* 54 reserved */
9848 0, /* 55 reserved */
9849 0, /* 56 cisptr_lsw */
9850 0, /* 57 cisprt_msw */
9851 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9852 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
9853 0, /* 60 reserved */
9854 0, /* 61 reserved */
9855 0, /* 62 reserved */
9856 0 /* 63 reserved */
9857 };
9858
9859 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = {
9860 0, /* 00 cfg_lsw */
9861 0, /* 01 cfg_msw */
9862 0, /* 02 disc_enable */
9863 0, /* 03 wdtr_able */
9864 0, /* 04 sdtr_speed1 */
9865 0, /* 05 start_motor */
9866 0, /* 06 tagqng_able */
9867 0, /* 07 bios_scan */
9868 0, /* 08 scam_tolerant */
9869 1, /* 09 adapter_scsi_id */
9870 1, /* bios_boot_delay */
9871 1, /* 10 scsi_reset_delay */
9872 1, /* bios_id_lun */
9873 1, /* 11 termination_se */
9874 1, /* termination_lvd */
9875 0, /* 12 bios_ctrl */
9876 0, /* 13 sdtr_speed2 */
9877 0, /* 14 sdtr_speed3 */
9878 1, /* 15 max_host_qng */
9879 1, /* max_dvc_qng */
9880 0, /* 16 dvc_cntl */
9881 0, /* 17 sdtr_speed4 */
9882 0, /* 18 serial_number_word1 */
9883 0, /* 19 serial_number_word2 */
9884 0, /* 20 serial_number_word3 */
9885 0, /* 21 check_sum */
9886 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9887 , /* 22-29 oem_name[16] */
9888 0, /* 30 dvc_err_code */
9889 0, /* 31 adv_err_code */
9890 0, /* 32 adv_err_addr */
9891 0, /* 33 saved_dvc_err_code */
9892 0, /* 34 saved_adv_err_code */
9893 0, /* 35 saved_adv_err_addr */
9894 0, /* 36 reserved */
9895 0, /* 37 reserved */
9896 0, /* 38 reserved */
9897 0, /* 39 reserved */
9898 0, /* 40 reserved */
9899 0, /* 41 reserved */
9900 0, /* 42 reserved */
9901 0, /* 43 reserved */
9902 0, /* 44 reserved */
9903 0, /* 45 reserved */
9904 0, /* 46 reserved */
9905 0, /* 47 reserved */
9906 0, /* 48 reserved */
9907 0, /* 49 reserved */
9908 0, /* 50 reserved */
9909 0, /* 51 reserved */
9910 0, /* 52 reserved */
9911 0, /* 53 reserved */
9912 0, /* 54 reserved */
9913 0, /* 55 reserved */
9914 0, /* 56 cisptr_lsw */
9915 0, /* 57 cisprt_msw */
9916 0, /* 58 subsysvid */
9917 0, /* 59 subsysid */
9918 0, /* 60 reserved */
9919 0, /* 61 reserved */
9920 0, /* 62 reserved */
9921 0 /* 63 reserved */
9922 };
9923
9924 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = {
9925 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9926 0x0000, /* 01 cfg_msw */
9927 0xFFFF, /* 02 disc_enable */
9928 0xFFFF, /* 03 wdtr_able */
9929 0x5555, /* 04 sdtr_speed1 */
9930 0xFFFF, /* 05 start_motor */
9931 0xFFFF, /* 06 tagqng_able */
9932 0xFFFF, /* 07 bios_scan */
9933 0, /* 08 scam_tolerant */
9934 7, /* 09 adapter_scsi_id */
9935 0, /* bios_boot_delay */
9936 3, /* 10 scsi_reset_delay */
9937 0, /* bios_id_lun */
9938 0, /* 11 termination_se */
9939 0, /* termination_lvd */
9940 0xFFE7, /* 12 bios_ctrl */
9941 0x5555, /* 13 sdtr_speed2 */
9942 0x5555, /* 14 sdtr_speed3 */
9943 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9944 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9945 0, /* 16 dvc_cntl */
9946 0x5555, /* 17 sdtr_speed4 */
9947 0, /* 18 serial_number_word1 */
9948 0, /* 19 serial_number_word2 */
9949 0, /* 20 serial_number_word3 */
9950 0, /* 21 check_sum */
9951 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9952 , /* 22-29 oem_name[16] */
9953 0, /* 30 dvc_err_code */
9954 0, /* 31 adv_err_code */
9955 0, /* 32 adv_err_addr */
9956 0, /* 33 saved_dvc_err_code */
9957 0, /* 34 saved_adv_err_code */
9958 0, /* 35 saved_adv_err_addr */
9959 0, /* 36 reserved */
9960 0, /* 37 reserved */
9961 0, /* 38 reserved */
9962 0, /* 39 reserved */
9963 0, /* 40 reserved */
9964 0, /* 41 reserved */
9965 0, /* 42 reserved */
9966 0, /* 43 reserved */
9967 0, /* 44 reserved */
9968 0, /* 45 reserved */
9969 0, /* 46 reserved */
9970 0, /* 47 reserved */
9971 0, /* 48 reserved */
9972 0, /* 49 reserved */
9973 0, /* 50 reserved */
9974 0, /* 51 reserved */
9975 0, /* 52 reserved */
9976 0, /* 53 reserved */
9977 0, /* 54 reserved */
9978 0, /* 55 reserved */
9979 0, /* 56 cisptr_lsw */
9980 0, /* 57 cisprt_msw */
9981 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9982 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
9983 0, /* 60 reserved */
9984 0, /* 61 reserved */
9985 0, /* 62 reserved */
9986 0 /* 63 reserved */
9987 };
9988
9989 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = {
9990 0, /* 00 cfg_lsw */
9991 0, /* 01 cfg_msw */
9992 0, /* 02 disc_enable */
9993 0, /* 03 wdtr_able */
9994 0, /* 04 sdtr_speed1 */
9995 0, /* 05 start_motor */
9996 0, /* 06 tagqng_able */
9997 0, /* 07 bios_scan */
9998 0, /* 08 scam_tolerant */
9999 1, /* 09 adapter_scsi_id */
10000 1, /* bios_boot_delay */
10001 1, /* 10 scsi_reset_delay */
10002 1, /* bios_id_lun */
10003 1, /* 11 termination_se */
10004 1, /* termination_lvd */
10005 0, /* 12 bios_ctrl */
10006 0, /* 13 sdtr_speed2 */
10007 0, /* 14 sdtr_speed3 */
10008 1, /* 15 max_host_qng */
10009 1, /* max_dvc_qng */
10010 0, /* 16 dvc_cntl */
10011 0, /* 17 sdtr_speed4 */
10012 0, /* 18 serial_number_word1 */
10013 0, /* 19 serial_number_word2 */
10014 0, /* 20 serial_number_word3 */
10015 0, /* 21 check_sum */
10016 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
10017 , /* 22-29 oem_name[16] */
10018 0, /* 30 dvc_err_code */
10019 0, /* 31 adv_err_code */
10020 0, /* 32 adv_err_addr */
10021 0, /* 33 saved_dvc_err_code */
10022 0, /* 34 saved_adv_err_code */
10023 0, /* 35 saved_adv_err_addr */
10024 0, /* 36 reserved */
10025 0, /* 37 reserved */
10026 0, /* 38 reserved */
10027 0, /* 39 reserved */
10028 0, /* 40 reserved */
10029 0, /* 41 reserved */
10030 0, /* 42 reserved */
10031 0, /* 43 reserved */
10032 0, /* 44 reserved */
10033 0, /* 45 reserved */
10034 0, /* 46 reserved */
10035 0, /* 47 reserved */
10036 0, /* 48 reserved */
10037 0, /* 49 reserved */
10038 0, /* 50 reserved */
10039 0, /* 51 reserved */
10040 0, /* 52 reserved */
10041 0, /* 53 reserved */
10042 0, /* 54 reserved */
10043 0, /* 55 reserved */
10044 0, /* 56 cisptr_lsw */
10045 0, /* 57 cisprt_msw */
10046 0, /* 58 subsysvid */
10047 0, /* 59 subsysid */
10048 0, /* 60 reserved */
10049 0, /* 61 reserved */
10050 0, /* 62 reserved */
10051 0 /* 63 reserved */
10052 };
10053
10054 #ifdef CONFIG_PCI
10055 /*
10056 * Wait for EEPROM command to complete
10057 */
10058 static void AdvWaitEEPCmd(AdvPortAddr iop_base)
10059 {
10060 int eep_delay_ms;
10061
10062 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
10063 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
10064 ASC_EEP_CMD_DONE) {
10065 break;
10066 }
10067 mdelay(1);
10068 }
10069 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
10070 0)
10071 BUG();
10072 }
10073
10074 /*
10075 * Read the EEPROM from specified location
10076 */
10077 static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
10078 {
10079 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10080 ASC_EEP_CMD_READ | eep_word_addr);
10081 AdvWaitEEPCmd(iop_base);
10082 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
10083 }
10084
10085 /*
10086 * Write the EEPROM from 'cfg_buf'.
10087 */
10088 static void AdvSet3550EEPConfig(AdvPortAddr iop_base,
10089 ADVEEP_3550_CONFIG *cfg_buf)
10090 {
10091 ushort *wbuf;
10092 ushort addr, chksum;
10093 ushort *charfields;
10094
10095 wbuf = (ushort *)cfg_buf;
10096 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
10097 chksum = 0;
10098
10099 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10100 AdvWaitEEPCmd(iop_base);
10101
10102 /*
10103 * Write EEPROM from word 0 to word 20.
10104 */
10105 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10106 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10107 ushort word;
10108
10109 if (*charfields++) {
10110 word = cpu_to_le16(*wbuf);
10111 } else {
10112 word = *wbuf;
10113 }
10114 chksum += *wbuf; /* Checksum is calculated from word values. */
10115 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10116 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10117 ASC_EEP_CMD_WRITE | addr);
10118 AdvWaitEEPCmd(iop_base);
10119 mdelay(ADV_EEP_DELAY_MS);
10120 }
10121
10122 /*
10123 * Write EEPROM checksum at word 21.
10124 */
10125 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10126 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10127 AdvWaitEEPCmd(iop_base);
10128 wbuf++;
10129 charfields++;
10130
10131 /*
10132 * Write EEPROM OEM name at words 22 to 29.
10133 */
10134 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10135 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10136 ushort word;
10137
10138 if (*charfields++) {
10139 word = cpu_to_le16(*wbuf);
10140 } else {
10141 word = *wbuf;
10142 }
10143 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10144 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10145 ASC_EEP_CMD_WRITE | addr);
10146 AdvWaitEEPCmd(iop_base);
10147 }
10148 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10149 AdvWaitEEPCmd(iop_base);
10150 }
10151
10152 /*
10153 * Write the EEPROM from 'cfg_buf'.
10154 */
10155 static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
10156 ADVEEP_38C0800_CONFIG *cfg_buf)
10157 {
10158 ushort *wbuf;
10159 ushort *charfields;
10160 ushort addr, chksum;
10161
10162 wbuf = (ushort *)cfg_buf;
10163 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10164 chksum = 0;
10165
10166 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10167 AdvWaitEEPCmd(iop_base);
10168
10169 /*
10170 * Write EEPROM from word 0 to word 20.
10171 */
10172 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10173 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10174 ushort word;
10175
10176 if (*charfields++) {
10177 word = cpu_to_le16(*wbuf);
10178 } else {
10179 word = *wbuf;
10180 }
10181 chksum += *wbuf; /* Checksum is calculated from word values. */
10182 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10183 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10184 ASC_EEP_CMD_WRITE | addr);
10185 AdvWaitEEPCmd(iop_base);
10186 mdelay(ADV_EEP_DELAY_MS);
10187 }
10188
10189 /*
10190 * Write EEPROM checksum at word 21.
10191 */
10192 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10193 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10194 AdvWaitEEPCmd(iop_base);
10195 wbuf++;
10196 charfields++;
10197
10198 /*
10199 * Write EEPROM OEM name at words 22 to 29.
10200 */
10201 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10202 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10203 ushort word;
10204
10205 if (*charfields++) {
10206 word = cpu_to_le16(*wbuf);
10207 } else {
10208 word = *wbuf;
10209 }
10210 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10211 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10212 ASC_EEP_CMD_WRITE | addr);
10213 AdvWaitEEPCmd(iop_base);
10214 }
10215 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10216 AdvWaitEEPCmd(iop_base);
10217 }
10218
10219 /*
10220 * Write the EEPROM from 'cfg_buf'.
10221 */
10222 static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
10223 ADVEEP_38C1600_CONFIG *cfg_buf)
10224 {
10225 ushort *wbuf;
10226 ushort *charfields;
10227 ushort addr, chksum;
10228
10229 wbuf = (ushort *)cfg_buf;
10230 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
10231 chksum = 0;
10232
10233 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10234 AdvWaitEEPCmd(iop_base);
10235
10236 /*
10237 * Write EEPROM from word 0 to word 20.
10238 */
10239 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10240 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10241 ushort word;
10242
10243 if (*charfields++) {
10244 word = cpu_to_le16(*wbuf);
10245 } else {
10246 word = *wbuf;
10247 }
10248 chksum += *wbuf; /* Checksum is calculated from word values. */
10249 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10250 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10251 ASC_EEP_CMD_WRITE | addr);
10252 AdvWaitEEPCmd(iop_base);
10253 mdelay(ADV_EEP_DELAY_MS);
10254 }
10255
10256 /*
10257 * Write EEPROM checksum at word 21.
10258 */
10259 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10260 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10261 AdvWaitEEPCmd(iop_base);
10262 wbuf++;
10263 charfields++;
10264
10265 /*
10266 * Write EEPROM OEM name at words 22 to 29.
10267 */
10268 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10269 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10270 ushort word;
10271
10272 if (*charfields++) {
10273 word = cpu_to_le16(*wbuf);
10274 } else {
10275 word = *wbuf;
10276 }
10277 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10278 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10279 ASC_EEP_CMD_WRITE | addr);
10280 AdvWaitEEPCmd(iop_base);
10281 }
10282 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10283 AdvWaitEEPCmd(iop_base);
10284 }
10285
10286 /*
10287 * Read EEPROM configuration into the specified buffer.
10288 *
10289 * Return a checksum based on the EEPROM configuration read.
10290 */
10291 static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base,
10292 ADVEEP_3550_CONFIG *cfg_buf)
10293 {
10294 ushort wval, chksum;
10295 ushort *wbuf;
10296 int eep_addr;
10297 ushort *charfields;
10298
10299 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
10300 wbuf = (ushort *)cfg_buf;
10301 chksum = 0;
10302
10303 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10304 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10305 wval = AdvReadEEPWord(iop_base, eep_addr);
10306 chksum += wval; /* Checksum is calculated from word values. */
10307 if (*charfields++) {
10308 *wbuf = le16_to_cpu(wval);
10309 } else {
10310 *wbuf = wval;
10311 }
10312 }
10313 /* Read checksum word. */
10314 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10315 wbuf++;
10316 charfields++;
10317
10318 /* Read rest of EEPROM not covered by the checksum. */
10319 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10320 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10321 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10322 if (*charfields++) {
10323 *wbuf = le16_to_cpu(*wbuf);
10324 }
10325 }
10326 return chksum;
10327 }
10328
10329 /*
10330 * Read EEPROM configuration into the specified buffer.
10331 *
10332 * Return a checksum based on the EEPROM configuration read.
10333 */
10334 static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
10335 ADVEEP_38C0800_CONFIG *cfg_buf)
10336 {
10337 ushort wval, chksum;
10338 ushort *wbuf;
10339 int eep_addr;
10340 ushort *charfields;
10341
10342 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10343 wbuf = (ushort *)cfg_buf;
10344 chksum = 0;
10345
10346 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10347 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10348 wval = AdvReadEEPWord(iop_base, eep_addr);
10349 chksum += wval; /* Checksum is calculated from word values. */
10350 if (*charfields++) {
10351 *wbuf = le16_to_cpu(wval);
10352 } else {
10353 *wbuf = wval;
10354 }
10355 }
10356 /* Read checksum word. */
10357 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10358 wbuf++;
10359 charfields++;
10360
10361 /* Read rest of EEPROM not covered by the checksum. */
10362 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10363 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10364 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10365 if (*charfields++) {
10366 *wbuf = le16_to_cpu(*wbuf);
10367 }
10368 }
10369 return chksum;
10370 }
10371
10372 /*
10373 * Read EEPROM configuration into the specified buffer.
10374 *
10375 * Return a checksum based on the EEPROM configuration read.
10376 */
10377 static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
10378 ADVEEP_38C1600_CONFIG *cfg_buf)
10379 {
10380 ushort wval, chksum;
10381 ushort *wbuf;
10382 int eep_addr;
10383 ushort *charfields;
10384
10385 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
10386 wbuf = (ushort *)cfg_buf;
10387 chksum = 0;
10388
10389 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10390 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10391 wval = AdvReadEEPWord(iop_base, eep_addr);
10392 chksum += wval; /* Checksum is calculated from word values. */
10393 if (*charfields++) {
10394 *wbuf = le16_to_cpu(wval);
10395 } else {
10396 *wbuf = wval;
10397 }
10398 }
10399 /* Read checksum word. */
10400 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10401 wbuf++;
10402 charfields++;
10403
10404 /* Read rest of EEPROM not covered by the checksum. */
10405 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10406 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10407 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10408 if (*charfields++) {
10409 *wbuf = le16_to_cpu(*wbuf);
10410 }
10411 }
10412 return chksum;
10413 }
10414
10415 /*
10416 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10417 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10418 * all of this is done.
10419 *
10420 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10421 *
10422 * For a non-fatal error return a warning code. If there are no warnings
10423 * then 0 is returned.
10424 *
10425 * Note: Chip is stopped on entry.
10426 */
10427 static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
10428 {
10429 AdvPortAddr iop_base;
10430 ushort warn_code;
10431 ADVEEP_3550_CONFIG eep_config;
10432
10433 iop_base = asc_dvc->iop_base;
10434
10435 warn_code = 0;
10436
10437 /*
10438 * Read the board's EEPROM configuration.
10439 *
10440 * Set default values if a bad checksum is found.
10441 */
10442 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
10443 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10444
10445 /*
10446 * Set EEPROM default values.
10447 */
10448 memcpy(&eep_config, &Default_3550_EEPROM_Config,
10449 sizeof(ADVEEP_3550_CONFIG));
10450
10451 /*
10452 * Assume the 6 byte board serial number that was read from
10453 * EEPROM is correct even if the EEPROM checksum failed.
10454 */
10455 eep_config.serial_number_word3 =
10456 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10457
10458 eep_config.serial_number_word2 =
10459 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10460
10461 eep_config.serial_number_word1 =
10462 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10463
10464 AdvSet3550EEPConfig(iop_base, &eep_config);
10465 }
10466 /*
10467 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10468 * EEPROM configuration that was read.
10469 *
10470 * This is the mapping of EEPROM fields to Adv Library fields.
10471 */
10472 asc_dvc->wdtr_able = eep_config.wdtr_able;
10473 asc_dvc->sdtr_able = eep_config.sdtr_able;
10474 asc_dvc->ultra_able = eep_config.ultra_able;
10475 asc_dvc->tagqng_able = eep_config.tagqng_able;
10476 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10477 asc_dvc->max_host_qng = eep_config.max_host_qng;
10478 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10479 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10480 asc_dvc->start_motor = eep_config.start_motor;
10481 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10482 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10483 asc_dvc->no_scam = eep_config.scam_tolerant;
10484 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10485 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10486 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10487
10488 /*
10489 * Set the host maximum queuing (max. 253, min. 16) and the per device
10490 * maximum queuing (max. 63, min. 4).
10491 */
10492 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10493 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10494 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10495 /* If the value is zero, assume it is uninitialized. */
10496 if (eep_config.max_host_qng == 0) {
10497 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10498 } else {
10499 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10500 }
10501 }
10502
10503 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10504 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10505 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10506 /* If the value is zero, assume it is uninitialized. */
10507 if (eep_config.max_dvc_qng == 0) {
10508 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10509 } else {
10510 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10511 }
10512 }
10513
10514 /*
10515 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10516 * set 'max_dvc_qng' to 'max_host_qng'.
10517 */
10518 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10519 eep_config.max_dvc_qng = eep_config.max_host_qng;
10520 }
10521
10522 /*
10523 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10524 * values based on possibly adjusted EEPROM values.
10525 */
10526 asc_dvc->max_host_qng = eep_config.max_host_qng;
10527 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10528
10529 /*
10530 * If the EEPROM 'termination' field is set to automatic (0), then set
10531 * the ADV_DVC_CFG 'termination' field to automatic also.
10532 *
10533 * If the termination is specified with a non-zero 'termination'
10534 * value check that a legal value is set and set the ADV_DVC_CFG
10535 * 'termination' field appropriately.
10536 */
10537 if (eep_config.termination == 0) {
10538 asc_dvc->cfg->termination = 0; /* auto termination */
10539 } else {
10540 /* Enable manual control with low off / high off. */
10541 if (eep_config.termination == 1) {
10542 asc_dvc->cfg->termination = TERM_CTL_SEL;
10543
10544 /* Enable manual control with low off / high on. */
10545 } else if (eep_config.termination == 2) {
10546 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
10547
10548 /* Enable manual control with low on / high on. */
10549 } else if (eep_config.termination == 3) {
10550 asc_dvc->cfg->termination =
10551 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
10552 } else {
10553 /*
10554 * The EEPROM 'termination' field contains a bad value. Use
10555 * automatic termination instead.
10556 */
10557 asc_dvc->cfg->termination = 0;
10558 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10559 }
10560 }
10561
10562 return warn_code;
10563 }
10564
10565 /*
10566 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10567 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10568 * all of this is done.
10569 *
10570 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10571 *
10572 * For a non-fatal error return a warning code. If there are no warnings
10573 * then 0 is returned.
10574 *
10575 * Note: Chip is stopped on entry.
10576 */
10577 static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
10578 {
10579 AdvPortAddr iop_base;
10580 ushort warn_code;
10581 ADVEEP_38C0800_CONFIG eep_config;
10582 uchar tid, termination;
10583 ushort sdtr_speed = 0;
10584
10585 iop_base = asc_dvc->iop_base;
10586
10587 warn_code = 0;
10588
10589 /*
10590 * Read the board's EEPROM configuration.
10591 *
10592 * Set default values if a bad checksum is found.
10593 */
10594 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
10595 eep_config.check_sum) {
10596 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10597
10598 /*
10599 * Set EEPROM default values.
10600 */
10601 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
10602 sizeof(ADVEEP_38C0800_CONFIG));
10603
10604 /*
10605 * Assume the 6 byte board serial number that was read from
10606 * EEPROM is correct even if the EEPROM checksum failed.
10607 */
10608 eep_config.serial_number_word3 =
10609 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10610
10611 eep_config.serial_number_word2 =
10612 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10613
10614 eep_config.serial_number_word1 =
10615 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10616
10617 AdvSet38C0800EEPConfig(iop_base, &eep_config);
10618 }
10619 /*
10620 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
10621 * EEPROM configuration that was read.
10622 *
10623 * This is the mapping of EEPROM fields to Adv Library fields.
10624 */
10625 asc_dvc->wdtr_able = eep_config.wdtr_able;
10626 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10627 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10628 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10629 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10630 asc_dvc->tagqng_able = eep_config.tagqng_able;
10631 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10632 asc_dvc->max_host_qng = eep_config.max_host_qng;
10633 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10634 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10635 asc_dvc->start_motor = eep_config.start_motor;
10636 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10637 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10638 asc_dvc->no_scam = eep_config.scam_tolerant;
10639 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10640 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10641 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10642
10643 /*
10644 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10645 * are set, then set an 'sdtr_able' bit for it.
10646 */
10647 asc_dvc->sdtr_able = 0;
10648 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
10649 if (tid == 0) {
10650 sdtr_speed = asc_dvc->sdtr_speed1;
10651 } else if (tid == 4) {
10652 sdtr_speed = asc_dvc->sdtr_speed2;
10653 } else if (tid == 8) {
10654 sdtr_speed = asc_dvc->sdtr_speed3;
10655 } else if (tid == 12) {
10656 sdtr_speed = asc_dvc->sdtr_speed4;
10657 }
10658 if (sdtr_speed & ADV_MAX_TID) {
10659 asc_dvc->sdtr_able |= (1 << tid);
10660 }
10661 sdtr_speed >>= 4;
10662 }
10663
10664 /*
10665 * Set the host maximum queuing (max. 253, min. 16) and the per device
10666 * maximum queuing (max. 63, min. 4).
10667 */
10668 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10669 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10670 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10671 /* If the value is zero, assume it is uninitialized. */
10672 if (eep_config.max_host_qng == 0) {
10673 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10674 } else {
10675 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10676 }
10677 }
10678
10679 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10680 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10681 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10682 /* If the value is zero, assume it is uninitialized. */
10683 if (eep_config.max_dvc_qng == 0) {
10684 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10685 } else {
10686 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10687 }
10688 }
10689
10690 /*
10691 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10692 * set 'max_dvc_qng' to 'max_host_qng'.
10693 */
10694 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10695 eep_config.max_dvc_qng = eep_config.max_host_qng;
10696 }
10697
10698 /*
10699 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10700 * values based on possibly adjusted EEPROM values.
10701 */
10702 asc_dvc->max_host_qng = eep_config.max_host_qng;
10703 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10704
10705 /*
10706 * If the EEPROM 'termination' field is set to automatic (0), then set
10707 * the ADV_DVC_CFG 'termination' field to automatic also.
10708 *
10709 * If the termination is specified with a non-zero 'termination'
10710 * value check that a legal value is set and set the ADV_DVC_CFG
10711 * 'termination' field appropriately.
10712 */
10713 if (eep_config.termination_se == 0) {
10714 termination = 0; /* auto termination for SE */
10715 } else {
10716 /* Enable manual control with low off / high off. */
10717 if (eep_config.termination_se == 1) {
10718 termination = 0;
10719
10720 /* Enable manual control with low off / high on. */
10721 } else if (eep_config.termination_se == 2) {
10722 termination = TERM_SE_HI;
10723
10724 /* Enable manual control with low on / high on. */
10725 } else if (eep_config.termination_se == 3) {
10726 termination = TERM_SE;
10727 } else {
10728 /*
10729 * The EEPROM 'termination_se' field contains a bad value.
10730 * Use automatic termination instead.
10731 */
10732 termination = 0;
10733 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10734 }
10735 }
10736
10737 if (eep_config.termination_lvd == 0) {
10738 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10739 } else {
10740 /* Enable manual control with low off / high off. */
10741 if (eep_config.termination_lvd == 1) {
10742 asc_dvc->cfg->termination = termination;
10743
10744 /* Enable manual control with low off / high on. */
10745 } else if (eep_config.termination_lvd == 2) {
10746 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10747
10748 /* Enable manual control with low on / high on. */
10749 } else if (eep_config.termination_lvd == 3) {
10750 asc_dvc->cfg->termination = termination | TERM_LVD;
10751 } else {
10752 /*
10753 * The EEPROM 'termination_lvd' field contains a bad value.
10754 * Use automatic termination instead.
10755 */
10756 asc_dvc->cfg->termination = termination;
10757 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10758 }
10759 }
10760
10761 return warn_code;
10762 }
10763
10764 /*
10765 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
10766 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
10767 * all of this is done.
10768 *
10769 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
10770 *
10771 * For a non-fatal error return a warning code. If there are no warnings
10772 * then 0 is returned.
10773 *
10774 * Note: Chip is stopped on entry.
10775 */
10776 static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
10777 {
10778 AdvPortAddr iop_base;
10779 ushort warn_code;
10780 ADVEEP_38C1600_CONFIG eep_config;
10781 uchar tid, termination;
10782 ushort sdtr_speed = 0;
10783
10784 iop_base = asc_dvc->iop_base;
10785
10786 warn_code = 0;
10787
10788 /*
10789 * Read the board's EEPROM configuration.
10790 *
10791 * Set default values if a bad checksum is found.
10792 */
10793 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
10794 eep_config.check_sum) {
10795 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
10796 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10797
10798 /*
10799 * Set EEPROM default values.
10800 */
10801 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
10802 sizeof(ADVEEP_38C1600_CONFIG));
10803
10804 if (PCI_FUNC(pdev->devfn) != 0) {
10805 u8 ints;
10806 /*
10807 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
10808 * and old Mac system booting problem. The Expansion
10809 * ROM must be disabled in Function 1 for these systems
10810 */
10811 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
10812 /*
10813 * Clear the INTAB (bit 11) if the GPIO 0 input
10814 * indicates the Function 1 interrupt line is wired
10815 * to INTB.
10816 *
10817 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
10818 * 1 - Function 1 interrupt line wired to INT A.
10819 * 0 - Function 1 interrupt line wired to INT B.
10820 *
10821 * Note: Function 0 is always wired to INTA.
10822 * Put all 5 GPIO bits in input mode and then read
10823 * their input values.
10824 */
10825 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
10826 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
10827 if ((ints & 0x01) == 0)
10828 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
10829 }
10830
10831 /*
10832 * Assume the 6 byte board serial number that was read from
10833 * EEPROM is correct even if the EEPROM checksum failed.
10834 */
10835 eep_config.serial_number_word3 =
10836 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10837 eep_config.serial_number_word2 =
10838 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10839 eep_config.serial_number_word1 =
10840 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10841
10842 AdvSet38C1600EEPConfig(iop_base, &eep_config);
10843 }
10844
10845 /*
10846 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10847 * EEPROM configuration that was read.
10848 *
10849 * This is the mapping of EEPROM fields to Adv Library fields.
10850 */
10851 asc_dvc->wdtr_able = eep_config.wdtr_able;
10852 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10853 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10854 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10855 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10856 asc_dvc->ppr_able = 0;
10857 asc_dvc->tagqng_able = eep_config.tagqng_able;
10858 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10859 asc_dvc->max_host_qng = eep_config.max_host_qng;
10860 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10861 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
10862 asc_dvc->start_motor = eep_config.start_motor;
10863 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10864 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10865 asc_dvc->no_scam = eep_config.scam_tolerant;
10866
10867 /*
10868 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10869 * are set, then set an 'sdtr_able' bit for it.
10870 */
10871 asc_dvc->sdtr_able = 0;
10872 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
10873 if (tid == 0) {
10874 sdtr_speed = asc_dvc->sdtr_speed1;
10875 } else if (tid == 4) {
10876 sdtr_speed = asc_dvc->sdtr_speed2;
10877 } else if (tid == 8) {
10878 sdtr_speed = asc_dvc->sdtr_speed3;
10879 } else if (tid == 12) {
10880 sdtr_speed = asc_dvc->sdtr_speed4;
10881 }
10882 if (sdtr_speed & ASC_MAX_TID) {
10883 asc_dvc->sdtr_able |= (1 << tid);
10884 }
10885 sdtr_speed >>= 4;
10886 }
10887
10888 /*
10889 * Set the host maximum queuing (max. 253, min. 16) and the per device
10890 * maximum queuing (max. 63, min. 4).
10891 */
10892 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10893 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10894 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10895 /* If the value is zero, assume it is uninitialized. */
10896 if (eep_config.max_host_qng == 0) {
10897 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10898 } else {
10899 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10900 }
10901 }
10902
10903 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10904 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10905 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10906 /* If the value is zero, assume it is uninitialized. */
10907 if (eep_config.max_dvc_qng == 0) {
10908 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10909 } else {
10910 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10911 }
10912 }
10913
10914 /*
10915 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10916 * set 'max_dvc_qng' to 'max_host_qng'.
10917 */
10918 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10919 eep_config.max_dvc_qng = eep_config.max_host_qng;
10920 }
10921
10922 /*
10923 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
10924 * values based on possibly adjusted EEPROM values.
10925 */
10926 asc_dvc->max_host_qng = eep_config.max_host_qng;
10927 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10928
10929 /*
10930 * If the EEPROM 'termination' field is set to automatic (0), then set
10931 * the ASC_DVC_CFG 'termination' field to automatic also.
10932 *
10933 * If the termination is specified with a non-zero 'termination'
10934 * value check that a legal value is set and set the ASC_DVC_CFG
10935 * 'termination' field appropriately.
10936 */
10937 if (eep_config.termination_se == 0) {
10938 termination = 0; /* auto termination for SE */
10939 } else {
10940 /* Enable manual control with low off / high off. */
10941 if (eep_config.termination_se == 1) {
10942 termination = 0;
10943
10944 /* Enable manual control with low off / high on. */
10945 } else if (eep_config.termination_se == 2) {
10946 termination = TERM_SE_HI;
10947
10948 /* Enable manual control with low on / high on. */
10949 } else if (eep_config.termination_se == 3) {
10950 termination = TERM_SE;
10951 } else {
10952 /*
10953 * The EEPROM 'termination_se' field contains a bad value.
10954 * Use automatic termination instead.
10955 */
10956 termination = 0;
10957 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10958 }
10959 }
10960
10961 if (eep_config.termination_lvd == 0) {
10962 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10963 } else {
10964 /* Enable manual control with low off / high off. */
10965 if (eep_config.termination_lvd == 1) {
10966 asc_dvc->cfg->termination = termination;
10967
10968 /* Enable manual control with low off / high on. */
10969 } else if (eep_config.termination_lvd == 2) {
10970 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10971
10972 /* Enable manual control with low on / high on. */
10973 } else if (eep_config.termination_lvd == 3) {
10974 asc_dvc->cfg->termination = termination | TERM_LVD;
10975 } else {
10976 /*
10977 * The EEPROM 'termination_lvd' field contains a bad value.
10978 * Use automatic termination instead.
10979 */
10980 asc_dvc->cfg->termination = termination;
10981 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10982 }
10983 }
10984
10985 return warn_code;
10986 }
10987
10988 /*
10989 * Initialize the ADV_DVC_VAR structure.
10990 *
10991 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10992 *
10993 * For a non-fatal error return a warning code. If there are no warnings
10994 * then 0 is returned.
10995 */
10996 static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
10997 {
10998 struct asc_board *board = shost_priv(shost);
10999 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
11000 unsigned short warn_code = 0;
11001 AdvPortAddr iop_base = asc_dvc->iop_base;
11002 u16 cmd;
11003 int status;
11004
11005 asc_dvc->err_code = 0;
11006
11007 /*
11008 * Save the state of the PCI Configuration Command Register
11009 * "Parity Error Response Control" Bit. If the bit is clear (0),
11010 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
11011 * DMA parity errors.
11012 */
11013 asc_dvc->cfg->control_flag = 0;
11014 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
11015 if ((cmd & PCI_COMMAND_PARITY) == 0)
11016 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
11017
11018 asc_dvc->cfg->chip_version =
11019 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
11020
11021 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
11022 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
11023 (ushort)ADV_CHIP_ID_BYTE);
11024
11025 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
11026 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
11027 (ushort)ADV_CHIP_ID_WORD);
11028
11029 /*
11030 * Reset the chip to start and allow register writes.
11031 */
11032 if (AdvFindSignature(iop_base) == 0) {
11033 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11034 return ADV_ERROR;
11035 } else {
11036 /*
11037 * The caller must set 'chip_type' to a valid setting.
11038 */
11039 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
11040 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
11041 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
11042 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
11043 return ADV_ERROR;
11044 }
11045
11046 /*
11047 * Reset Chip.
11048 */
11049 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11050 ADV_CTRL_REG_CMD_RESET);
11051 mdelay(100);
11052 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11053 ADV_CTRL_REG_CMD_WR_IO_REG);
11054
11055 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11056 status = AdvInitFrom38C1600EEP(asc_dvc);
11057 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11058 status = AdvInitFrom38C0800EEP(asc_dvc);
11059 } else {
11060 status = AdvInitFrom3550EEP(asc_dvc);
11061 }
11062 warn_code |= status;
11063 }
11064
11065 if (warn_code != 0)
11066 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
11067
11068 if (asc_dvc->err_code)
11069 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
11070 asc_dvc->err_code);
11071
11072 return asc_dvc->err_code;
11073 }
11074 #endif
11075
11076 static struct scsi_host_template advansys_template = {
11077 .proc_name = DRV_NAME,
11078 #ifdef CONFIG_PROC_FS
11079 .show_info = advansys_show_info,
11080 #endif
11081 .name = DRV_NAME,
11082 .info = advansys_info,
11083 .queuecommand = advansys_queuecommand,
11084 .eh_host_reset_handler = advansys_reset,
11085 .bios_param = advansys_biosparam,
11086 .slave_configure = advansys_slave_configure,
11087 /*
11088 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
11089 * must be set. The flag will be cleared in advansys_board_found
11090 * for non-ISA adapters.
11091 */
11092 .unchecked_isa_dma = true,
11093 /*
11094 * All adapters controlled by this driver are capable of large
11095 * scatter-gather lists. According to the mid-level SCSI documentation
11096 * this obviates any performance gain provided by setting
11097 * 'use_clustering'. But empirically while CPU utilization is increased
11098 * by enabling clustering, I/O throughput increases as well.
11099 */
11100 .use_clustering = ENABLE_CLUSTERING,
11101 .use_blk_tags = 1,
11102 };
11103
11104 static int advansys_wide_init_chip(struct Scsi_Host *shost)
11105 {
11106 struct asc_board *board = shost_priv(shost);
11107 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11108 size_t sgblk_pool_size;
11109 int warn_code, err_code;
11110
11111 /*
11112 * Allocate buffer carrier structures. The total size
11113 * is about 8 KB, so allocate all at once.
11114 */
11115 adv_dvc->carrier = dma_alloc_coherent(board->dev,
11116 ADV_CARRIER_BUFSIZE, &adv_dvc->carrier_addr, GFP_KERNEL);
11117 ASC_DBG(1, "carrier 0x%p\n", adv_dvc->carrier);
11118
11119 if (!adv_dvc->carrier)
11120 goto kmalloc_failed;
11121
11122 /*
11123 * Allocate up to 'max_host_qng' request structures for the Wide
11124 * board. The total size is about 16 KB, so allocate all at once.
11125 * If the allocation fails decrement and try again.
11126 */
11127 board->adv_reqp_size = adv_dvc->max_host_qng * sizeof(adv_req_t);
11128 if (board->adv_reqp_size & 0x1f) {
11129 ASC_DBG(1, "unaligned reqp %lu bytes\n", sizeof(adv_req_t));
11130 board->adv_reqp_size = ADV_32BALIGN(board->adv_reqp_size);
11131 }
11132 board->adv_reqp = dma_alloc_coherent(board->dev, board->adv_reqp_size,
11133 &board->adv_reqp_addr, GFP_KERNEL);
11134
11135 if (!board->adv_reqp)
11136 goto kmalloc_failed;
11137
11138 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", board->adv_reqp,
11139 adv_dvc->max_host_qng, board->adv_reqp_size);
11140
11141 /*
11142 * Allocate up to ADV_TOT_SG_BLOCK request structures for
11143 * the Wide board. Each structure is about 136 bytes.
11144 */
11145 sgblk_pool_size = sizeof(adv_sgblk_t) * ADV_TOT_SG_BLOCK;
11146 board->adv_sgblk_pool = dma_pool_create("adv_sgblk", board->dev,
11147 sgblk_pool_size, 32, 0);
11148
11149 ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", ADV_TOT_SG_BLOCK,
11150 sizeof(adv_sgblk_t), sgblk_pool_size);
11151
11152 if (!board->adv_sgblk_pool)
11153 goto kmalloc_failed;
11154
11155 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
11156 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
11157 warn_code = AdvInitAsc3550Driver(adv_dvc);
11158 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11159 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
11160 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
11161 } else {
11162 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
11163 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
11164 }
11165 err_code = adv_dvc->err_code;
11166
11167 if (warn_code || err_code) {
11168 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
11169 "0x%x\n", warn_code, err_code);
11170 }
11171
11172 goto exit;
11173
11174 kmalloc_failed:
11175 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
11176 err_code = ADV_ERROR;
11177 exit:
11178 return err_code;
11179 }
11180
11181 static void advansys_wide_free_mem(struct asc_board *board)
11182 {
11183 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11184
11185 if (adv_dvc->carrier) {
11186 dma_free_coherent(board->dev, ADV_CARRIER_BUFSIZE,
11187 adv_dvc->carrier, adv_dvc->carrier_addr);
11188 adv_dvc->carrier = NULL;
11189 }
11190 if (board->adv_reqp) {
11191 dma_free_coherent(board->dev, board->adv_reqp_size,
11192 board->adv_reqp, board->adv_reqp_addr);
11193 board->adv_reqp = NULL;
11194 }
11195 if (board->adv_sgblk_pool) {
11196 dma_pool_destroy(board->adv_sgblk_pool);
11197 board->adv_sgblk_pool = NULL;
11198 }
11199 }
11200
11201 static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop,
11202 int bus_type)
11203 {
11204 struct pci_dev *pdev;
11205 struct asc_board *boardp = shost_priv(shost);
11206 ASC_DVC_VAR *asc_dvc_varp = NULL;
11207 ADV_DVC_VAR *adv_dvc_varp = NULL;
11208 int share_irq, warn_code, ret;
11209
11210 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
11211
11212 if (ASC_NARROW_BOARD(boardp)) {
11213 ASC_DBG(1, "narrow board\n");
11214 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
11215 asc_dvc_varp->bus_type = bus_type;
11216 asc_dvc_varp->drv_ptr = boardp;
11217 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
11218 asc_dvc_varp->iop_base = iop;
11219 } else {
11220 #ifdef CONFIG_PCI
11221 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
11222 adv_dvc_varp->drv_ptr = boardp;
11223 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
11224 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
11225 ASC_DBG(1, "wide board ASC-3550\n");
11226 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
11227 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
11228 ASC_DBG(1, "wide board ASC-38C0800\n");
11229 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
11230 } else {
11231 ASC_DBG(1, "wide board ASC-38C1600\n");
11232 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
11233 }
11234
11235 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
11236 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1);
11237 if (!boardp->ioremap_addr) {
11238 shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) "
11239 "returned NULL\n",
11240 (long)pci_resource_start(pdev, 1),
11241 boardp->asc_n_io_port);
11242 ret = -ENODEV;
11243 goto err_shost;
11244 }
11245 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
11246 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
11247
11248 /*
11249 * Even though it isn't used to access wide boards, other
11250 * than for the debug line below, save I/O Port address so
11251 * that it can be reported.
11252 */
11253 boardp->ioport = iop;
11254
11255 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
11256 (ushort)inp(iop + 1), (ushort)inpw(iop));
11257 #endif /* CONFIG_PCI */
11258 }
11259
11260 if (ASC_NARROW_BOARD(boardp)) {
11261 /*
11262 * Set the board bus type and PCI IRQ before
11263 * calling AscInitGetConfig().
11264 */
11265 switch (asc_dvc_varp->bus_type) {
11266 #ifdef CONFIG_ISA
11267 case ASC_IS_ISA:
11268 shost->unchecked_isa_dma = true;
11269 share_irq = 0;
11270 break;
11271 case ASC_IS_VL:
11272 shost->unchecked_isa_dma = false;
11273 share_irq = 0;
11274 break;
11275 case ASC_IS_EISA:
11276 shost->unchecked_isa_dma = false;
11277 share_irq = IRQF_SHARED;
11278 break;
11279 #endif /* CONFIG_ISA */
11280 #ifdef CONFIG_PCI
11281 case ASC_IS_PCI:
11282 shost->unchecked_isa_dma = false;
11283 share_irq = IRQF_SHARED;
11284 break;
11285 #endif /* CONFIG_PCI */
11286 default:
11287 shost_printk(KERN_ERR, shost, "unknown adapter type: "
11288 "%d\n", asc_dvc_varp->bus_type);
11289 shost->unchecked_isa_dma = false;
11290 share_irq = 0;
11291 break;
11292 }
11293
11294 /*
11295 * NOTE: AscInitGetConfig() may change the board's
11296 * bus_type value. The bus_type value should no
11297 * longer be used. If the bus_type field must be
11298 * referenced only use the bit-wise AND operator "&".
11299 */
11300 ASC_DBG(2, "AscInitGetConfig()\n");
11301 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
11302 } else {
11303 #ifdef CONFIG_PCI
11304 /*
11305 * For Wide boards set PCI information before calling
11306 * AdvInitGetConfig().
11307 */
11308 shost->unchecked_isa_dma = false;
11309 share_irq = IRQF_SHARED;
11310 ASC_DBG(2, "AdvInitGetConfig()\n");
11311
11312 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
11313 #endif /* CONFIG_PCI */
11314 }
11315
11316 if (ret)
11317 goto err_unmap;
11318
11319 /*
11320 * Save the EEPROM configuration so that it can be displayed
11321 * from /proc/scsi/advansys/[0...].
11322 */
11323 if (ASC_NARROW_BOARD(boardp)) {
11324
11325 ASCEEP_CONFIG *ep;
11326
11327 /*
11328 * Set the adapter's target id bit in the 'init_tidmask' field.
11329 */
11330 boardp->init_tidmask |=
11331 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
11332
11333 /*
11334 * Save EEPROM settings for the board.
11335 */
11336 ep = &boardp->eep_config.asc_eep;
11337
11338 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
11339 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
11340 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
11341 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
11342 ep->start_motor = asc_dvc_varp->start_motor;
11343 ep->cntl = asc_dvc_varp->dvc_cntl;
11344 ep->no_scam = asc_dvc_varp->no_scam;
11345 ep->max_total_qng = asc_dvc_varp->max_total_qng;
11346 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
11347 /* 'max_tag_qng' is set to the same value for every device. */
11348 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
11349 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
11350 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
11351 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
11352 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
11353 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
11354 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
11355
11356 /*
11357 * Modify board configuration.
11358 */
11359 ASC_DBG(2, "AscInitSetConfig()\n");
11360 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
11361 if (ret)
11362 goto err_unmap;
11363 } else {
11364 ADVEEP_3550_CONFIG *ep_3550;
11365 ADVEEP_38C0800_CONFIG *ep_38C0800;
11366 ADVEEP_38C1600_CONFIG *ep_38C1600;
11367
11368 /*
11369 * Save Wide EEP Configuration Information.
11370 */
11371 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
11372 ep_3550 = &boardp->eep_config.adv_3550_eep;
11373
11374 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
11375 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
11376 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11377 ep_3550->termination = adv_dvc_varp->cfg->termination;
11378 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
11379 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
11380 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
11381 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
11382 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
11383 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
11384 ep_3550->start_motor = adv_dvc_varp->start_motor;
11385 ep_3550->scsi_reset_delay =
11386 adv_dvc_varp->scsi_reset_wait;
11387 ep_3550->serial_number_word1 =
11388 adv_dvc_varp->cfg->serial1;
11389 ep_3550->serial_number_word2 =
11390 adv_dvc_varp->cfg->serial2;
11391 ep_3550->serial_number_word3 =
11392 adv_dvc_varp->cfg->serial3;
11393 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
11394 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
11395
11396 ep_38C0800->adapter_scsi_id =
11397 adv_dvc_varp->chip_scsi_id;
11398 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
11399 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11400 ep_38C0800->termination_lvd =
11401 adv_dvc_varp->cfg->termination;
11402 ep_38C0800->disc_enable =
11403 adv_dvc_varp->cfg->disc_enable;
11404 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
11405 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
11406 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11407 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11408 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11409 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11410 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11411 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11412 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
11413 ep_38C0800->scsi_reset_delay =
11414 adv_dvc_varp->scsi_reset_wait;
11415 ep_38C0800->serial_number_word1 =
11416 adv_dvc_varp->cfg->serial1;
11417 ep_38C0800->serial_number_word2 =
11418 adv_dvc_varp->cfg->serial2;
11419 ep_38C0800->serial_number_word3 =
11420 adv_dvc_varp->cfg->serial3;
11421 } else {
11422 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
11423
11424 ep_38C1600->adapter_scsi_id =
11425 adv_dvc_varp->chip_scsi_id;
11426 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
11427 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11428 ep_38C1600->termination_lvd =
11429 adv_dvc_varp->cfg->termination;
11430 ep_38C1600->disc_enable =
11431 adv_dvc_varp->cfg->disc_enable;
11432 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
11433 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
11434 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11435 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11436 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11437 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11438 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11439 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11440 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
11441 ep_38C1600->scsi_reset_delay =
11442 adv_dvc_varp->scsi_reset_wait;
11443 ep_38C1600->serial_number_word1 =
11444 adv_dvc_varp->cfg->serial1;
11445 ep_38C1600->serial_number_word2 =
11446 adv_dvc_varp->cfg->serial2;
11447 ep_38C1600->serial_number_word3 =
11448 adv_dvc_varp->cfg->serial3;
11449 }
11450
11451 /*
11452 * Set the adapter's target id bit in the 'init_tidmask' field.
11453 */
11454 boardp->init_tidmask |=
11455 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
11456 }
11457
11458 /*
11459 * Channels are numbered beginning with 0. For AdvanSys one host
11460 * structure supports one channel. Multi-channel boards have a
11461 * separate host structure for each channel.
11462 */
11463 shost->max_channel = 0;
11464 if (ASC_NARROW_BOARD(boardp)) {
11465 shost->max_id = ASC_MAX_TID + 1;
11466 shost->max_lun = ASC_MAX_LUN + 1;
11467 shost->max_cmd_len = ASC_MAX_CDB_LEN;
11468
11469 shost->io_port = asc_dvc_varp->iop_base;
11470 boardp->asc_n_io_port = ASC_IOADR_GAP;
11471 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
11472
11473 /* Set maximum number of queues the adapter can handle. */
11474 shost->can_queue = asc_dvc_varp->max_total_qng;
11475 } else {
11476 shost->max_id = ADV_MAX_TID + 1;
11477 shost->max_lun = ADV_MAX_LUN + 1;
11478 shost->max_cmd_len = ADV_MAX_CDB_LEN;
11479
11480 /*
11481 * Save the I/O Port address and length even though
11482 * I/O ports are not used to access Wide boards.
11483 * Instead the Wide boards are accessed with
11484 * PCI Memory Mapped I/O.
11485 */
11486 shost->io_port = iop;
11487
11488 shost->this_id = adv_dvc_varp->chip_scsi_id;
11489
11490 /* Set maximum number of queues the adapter can handle. */
11491 shost->can_queue = adv_dvc_varp->max_host_qng;
11492 }
11493 ret = scsi_init_shared_tag_map(shost, shost->can_queue);
11494 if (ret) {
11495 shost_printk(KERN_ERR, shost, "init tag map failed\n");
11496 goto err_free_dma;
11497 }
11498
11499 /*
11500 * Following v1.3.89, 'cmd_per_lun' is no longer needed
11501 * and should be set to zero.
11502 *
11503 * But because of a bug introduced in v1.3.89 if the driver is
11504 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
11505 * SCSI function 'allocate_device' will panic. To allow the driver
11506 * to work as a module in these kernels set 'cmd_per_lun' to 1.
11507 *
11508 * Note: This is wrong. cmd_per_lun should be set to the depth
11509 * you want on untagged devices always.
11510 #ifdef MODULE
11511 */
11512 shost->cmd_per_lun = 1;
11513 /* #else
11514 shost->cmd_per_lun = 0;
11515 #endif */
11516
11517 /*
11518 * Set the maximum number of scatter-gather elements the
11519 * adapter can handle.
11520 */
11521 if (ASC_NARROW_BOARD(boardp)) {
11522 /*
11523 * Allow two commands with 'sg_tablesize' scatter-gather
11524 * elements to be executed simultaneously. This value is
11525 * the theoretical hardware limit. It may be decreased
11526 * below.
11527 */
11528 shost->sg_tablesize =
11529 (((asc_dvc_varp->max_total_qng - 2) / 2) *
11530 ASC_SG_LIST_PER_Q) + 1;
11531 } else {
11532 shost->sg_tablesize = ADV_MAX_SG_LIST;
11533 }
11534
11535 /*
11536 * The value of 'sg_tablesize' can not exceed the SCSI
11537 * mid-level driver definition of SG_ALL. SG_ALL also
11538 * must not be exceeded, because it is used to define the
11539 * size of the scatter-gather table in 'struct asc_sg_head'.
11540 */
11541 if (shost->sg_tablesize > SG_ALL) {
11542 shost->sg_tablesize = SG_ALL;
11543 }
11544
11545 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
11546
11547 /* BIOS start address. */
11548 if (ASC_NARROW_BOARD(boardp)) {
11549 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
11550 asc_dvc_varp->bus_type);
11551 } else {
11552 /*
11553 * Fill-in BIOS board variables. The Wide BIOS saves
11554 * information in LRAM that is used by the driver.
11555 */
11556 AdvReadWordLram(adv_dvc_varp->iop_base,
11557 BIOS_SIGNATURE, boardp->bios_signature);
11558 AdvReadWordLram(adv_dvc_varp->iop_base,
11559 BIOS_VERSION, boardp->bios_version);
11560 AdvReadWordLram(adv_dvc_varp->iop_base,
11561 BIOS_CODESEG, boardp->bios_codeseg);
11562 AdvReadWordLram(adv_dvc_varp->iop_base,
11563 BIOS_CODELEN, boardp->bios_codelen);
11564
11565 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
11566 boardp->bios_signature, boardp->bios_version);
11567
11568 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
11569 boardp->bios_codeseg, boardp->bios_codelen);
11570
11571 /*
11572 * If the BIOS saved a valid signature, then fill in
11573 * the BIOS code segment base address.
11574 */
11575 if (boardp->bios_signature == 0x55AA) {
11576 /*
11577 * Convert x86 realmode code segment to a linear
11578 * address by shifting left 4.
11579 */
11580 shost->base = ((ulong)boardp->bios_codeseg << 4);
11581 } else {
11582 shost->base = 0;
11583 }
11584 }
11585
11586 /*
11587 * Register Board Resources - I/O Port, DMA, IRQ
11588 */
11589
11590 /* Register DMA Channel for Narrow boards. */
11591 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
11592 #ifdef CONFIG_ISA
11593 if (ASC_NARROW_BOARD(boardp)) {
11594 /* Register DMA channel for ISA bus. */
11595 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
11596 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
11597 ret = request_dma(shost->dma_channel, DRV_NAME);
11598 if (ret) {
11599 shost_printk(KERN_ERR, shost, "request_dma() "
11600 "%d failed %d\n",
11601 shost->dma_channel, ret);
11602 goto err_unmap;
11603 }
11604 AscEnableIsaDma(shost->dma_channel);
11605 }
11606 }
11607 #endif /* CONFIG_ISA */
11608
11609 /* Register IRQ Number. */
11610 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
11611
11612 ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
11613 DRV_NAME, shost);
11614
11615 if (ret) {
11616 if (ret == -EBUSY) {
11617 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11618 "already in use\n", boardp->irq);
11619 } else if (ret == -EINVAL) {
11620 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11621 "not valid\n", boardp->irq);
11622 } else {
11623 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11624 "failed with %d\n", boardp->irq, ret);
11625 }
11626 goto err_free_dma;
11627 }
11628
11629 /*
11630 * Initialize board RISC chip and enable interrupts.
11631 */
11632 if (ASC_NARROW_BOARD(boardp)) {
11633 ASC_DBG(2, "AscInitAsc1000Driver()\n");
11634
11635 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL);
11636 if (!asc_dvc_varp->overrun_buf) {
11637 ret = -ENOMEM;
11638 goto err_free_irq;
11639 }
11640 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
11641
11642 if (warn_code || asc_dvc_varp->err_code) {
11643 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
11644 "warn 0x%x, error 0x%x\n",
11645 asc_dvc_varp->init_state, warn_code,
11646 asc_dvc_varp->err_code);
11647 if (!asc_dvc_varp->overrun_dma) {
11648 ret = -ENODEV;
11649 goto err_free_mem;
11650 }
11651 }
11652 } else {
11653 if (advansys_wide_init_chip(shost)) {
11654 ret = -ENODEV;
11655 goto err_free_mem;
11656 }
11657 }
11658
11659 ASC_DBG_PRT_SCSI_HOST(2, shost);
11660
11661 ret = scsi_add_host(shost, boardp->dev);
11662 if (ret)
11663 goto err_free_mem;
11664
11665 scsi_scan_host(shost);
11666 return 0;
11667
11668 err_free_mem:
11669 if (ASC_NARROW_BOARD(boardp)) {
11670 if (asc_dvc_varp->overrun_dma)
11671 dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma,
11672 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11673 kfree(asc_dvc_varp->overrun_buf);
11674 } else
11675 advansys_wide_free_mem(boardp);
11676 err_free_irq:
11677 free_irq(boardp->irq, shost);
11678 err_free_dma:
11679 #ifdef CONFIG_ISA
11680 if (shost->dma_channel != NO_ISA_DMA)
11681 free_dma(shost->dma_channel);
11682 #endif
11683 err_unmap:
11684 if (boardp->ioremap_addr)
11685 iounmap(boardp->ioremap_addr);
11686 err_shost:
11687 return ret;
11688 }
11689
11690 /*
11691 * advansys_release()
11692 *
11693 * Release resources allocated for a single AdvanSys adapter.
11694 */
11695 static int advansys_release(struct Scsi_Host *shost)
11696 {
11697 struct asc_board *board = shost_priv(shost);
11698 ASC_DBG(1, "begin\n");
11699 scsi_remove_host(shost);
11700 free_irq(board->irq, shost);
11701 #ifdef CONFIG_ISA
11702 if (shost->dma_channel != NO_ISA_DMA) {
11703 ASC_DBG(1, "free_dma()\n");
11704 free_dma(shost->dma_channel);
11705 }
11706 #endif
11707 if (ASC_NARROW_BOARD(board)) {
11708 dma_unmap_single(board->dev,
11709 board->dvc_var.asc_dvc_var.overrun_dma,
11710 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11711 kfree(board->dvc_var.asc_dvc_var.overrun_buf);
11712 } else {
11713 iounmap(board->ioremap_addr);
11714 advansys_wide_free_mem(board);
11715 }
11716 scsi_host_put(shost);
11717 ASC_DBG(1, "end\n");
11718 return 0;
11719 }
11720
11721 #define ASC_IOADR_TABLE_MAX_IX 11
11722
11723 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = {
11724 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
11725 0x0210, 0x0230, 0x0250, 0x0330
11726 };
11727
11728 /*
11729 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
11730 * 00: 10
11731 * 01: 11
11732 * 10: 12
11733 * 11: 15
11734 */
11735 static unsigned int advansys_isa_irq_no(PortAddr iop_base)
11736 {
11737 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11738 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
11739 if (chip_irq == 13)
11740 chip_irq = 15;
11741 return chip_irq;
11742 }
11743
11744 static int advansys_isa_probe(struct device *dev, unsigned int id)
11745 {
11746 int err = -ENODEV;
11747 PortAddr iop_base = _asc_def_iop_base[id];
11748 struct Scsi_Host *shost;
11749 struct asc_board *board;
11750
11751 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
11752 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
11753 return -ENODEV;
11754 }
11755 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
11756 if (!AscFindSignature(iop_base))
11757 goto release_region;
11758 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
11759 goto release_region;
11760
11761 err = -ENOMEM;
11762 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11763 if (!shost)
11764 goto release_region;
11765
11766 board = shost_priv(shost);
11767 board->irq = advansys_isa_irq_no(iop_base);
11768 board->dev = dev;
11769 board->shost = shost;
11770
11771 err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
11772 if (err)
11773 goto free_host;
11774
11775 dev_set_drvdata(dev, shost);
11776 return 0;
11777
11778 free_host:
11779 scsi_host_put(shost);
11780 release_region:
11781 release_region(iop_base, ASC_IOADR_GAP);
11782 return err;
11783 }
11784
11785 static int advansys_isa_remove(struct device *dev, unsigned int id)
11786 {
11787 int ioport = _asc_def_iop_base[id];
11788 advansys_release(dev_get_drvdata(dev));
11789 release_region(ioport, ASC_IOADR_GAP);
11790 return 0;
11791 }
11792
11793 static struct isa_driver advansys_isa_driver = {
11794 .probe = advansys_isa_probe,
11795 .remove = advansys_isa_remove,
11796 .driver = {
11797 .owner = THIS_MODULE,
11798 .name = DRV_NAME,
11799 },
11800 };
11801
11802 /*
11803 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
11804 * 000: invalid
11805 * 001: 10
11806 * 010: 11
11807 * 011: 12
11808 * 100: invalid
11809 * 101: 14
11810 * 110: 15
11811 * 111: invalid
11812 */
11813 static unsigned int advansys_vlb_irq_no(PortAddr iop_base)
11814 {
11815 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11816 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
11817 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
11818 return 0;
11819 return chip_irq;
11820 }
11821
11822 static int advansys_vlb_probe(struct device *dev, unsigned int id)
11823 {
11824 int err = -ENODEV;
11825 PortAddr iop_base = _asc_def_iop_base[id];
11826 struct Scsi_Host *shost;
11827 struct asc_board *board;
11828
11829 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
11830 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
11831 return -ENODEV;
11832 }
11833 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
11834 if (!AscFindSignature(iop_base))
11835 goto release_region;
11836 /*
11837 * I don't think this condition can actually happen, but the old
11838 * driver did it, and the chances of finding a VLB setup in 2007
11839 * to do testing with is slight to none.
11840 */
11841 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
11842 goto release_region;
11843
11844 err = -ENOMEM;
11845 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11846 if (!shost)
11847 goto release_region;
11848
11849 board = shost_priv(shost);
11850 board->irq = advansys_vlb_irq_no(iop_base);
11851 board->dev = dev;
11852 board->shost = shost;
11853
11854 err = advansys_board_found(shost, iop_base, ASC_IS_VL);
11855 if (err)
11856 goto free_host;
11857
11858 dev_set_drvdata(dev, shost);
11859 return 0;
11860
11861 free_host:
11862 scsi_host_put(shost);
11863 release_region:
11864 release_region(iop_base, ASC_IOADR_GAP);
11865 return -ENODEV;
11866 }
11867
11868 static struct isa_driver advansys_vlb_driver = {
11869 .probe = advansys_vlb_probe,
11870 .remove = advansys_isa_remove,
11871 .driver = {
11872 .owner = THIS_MODULE,
11873 .name = "advansys_vlb",
11874 },
11875 };
11876
11877 static struct eisa_device_id advansys_eisa_table[] = {
11878 { "ABP7401" },
11879 { "ABP7501" },
11880 { "" }
11881 };
11882
11883 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
11884
11885 /*
11886 * EISA is a little more tricky than PCI; each EISA device may have two
11887 * channels, and this driver is written to make each channel its own Scsi_Host
11888 */
11889 struct eisa_scsi_data {
11890 struct Scsi_Host *host[2];
11891 };
11892
11893 /*
11894 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
11895 * 000: 10
11896 * 001: 11
11897 * 010: 12
11898 * 011: invalid
11899 * 100: 14
11900 * 101: 15
11901 * 110: invalid
11902 * 111: invalid
11903 */
11904 static unsigned int advansys_eisa_irq_no(struct eisa_device *edev)
11905 {
11906 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
11907 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
11908 if ((chip_irq == 13) || (chip_irq > 15))
11909 return 0;
11910 return chip_irq;
11911 }
11912
11913 static int advansys_eisa_probe(struct device *dev)
11914 {
11915 int i, ioport, irq = 0;
11916 int err;
11917 struct eisa_device *edev = to_eisa_device(dev);
11918 struct eisa_scsi_data *data;
11919
11920 err = -ENOMEM;
11921 data = kzalloc(sizeof(*data), GFP_KERNEL);
11922 if (!data)
11923 goto fail;
11924 ioport = edev->base_addr + 0xc30;
11925
11926 err = -ENODEV;
11927 for (i = 0; i < 2; i++, ioport += 0x20) {
11928 struct asc_board *board;
11929 struct Scsi_Host *shost;
11930 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
11931 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
11932 ioport + ASC_IOADR_GAP - 1);
11933 continue;
11934 }
11935 if (!AscFindSignature(ioport)) {
11936 release_region(ioport, ASC_IOADR_GAP);
11937 continue;
11938 }
11939
11940 /*
11941 * I don't know why we need to do this for EISA chips, but
11942 * not for any others. It looks to be equivalent to
11943 * AscGetChipCfgMsw, but I may have overlooked something,
11944 * so I'm not converting it until I get an EISA board to
11945 * test with.
11946 */
11947 inw(ioport + 4);
11948
11949 if (!irq)
11950 irq = advansys_eisa_irq_no(edev);
11951
11952 err = -ENOMEM;
11953 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11954 if (!shost)
11955 goto release_region;
11956
11957 board = shost_priv(shost);
11958 board->irq = irq;
11959 board->dev = dev;
11960 board->shost = shost;
11961
11962 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
11963 if (!err) {
11964 data->host[i] = shost;
11965 continue;
11966 }
11967
11968 scsi_host_put(shost);
11969 release_region:
11970 release_region(ioport, ASC_IOADR_GAP);
11971 break;
11972 }
11973
11974 if (err)
11975 goto free_data;
11976 dev_set_drvdata(dev, data);
11977 return 0;
11978
11979 free_data:
11980 kfree(data->host[0]);
11981 kfree(data->host[1]);
11982 kfree(data);
11983 fail:
11984 return err;
11985 }
11986
11987 static int advansys_eisa_remove(struct device *dev)
11988 {
11989 int i;
11990 struct eisa_scsi_data *data = dev_get_drvdata(dev);
11991
11992 for (i = 0; i < 2; i++) {
11993 int ioport;
11994 struct Scsi_Host *shost = data->host[i];
11995 if (!shost)
11996 continue;
11997 ioport = shost->io_port;
11998 advansys_release(shost);
11999 release_region(ioport, ASC_IOADR_GAP);
12000 }
12001
12002 kfree(data);
12003 return 0;
12004 }
12005
12006 static struct eisa_driver advansys_eisa_driver = {
12007 .id_table = advansys_eisa_table,
12008 .driver = {
12009 .name = DRV_NAME,
12010 .probe = advansys_eisa_probe,
12011 .remove = advansys_eisa_remove,
12012 }
12013 };
12014
12015 /* PCI Devices supported by this driver */
12016 static struct pci_device_id advansys_pci_tbl[] = {
12017 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
12018 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12019 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
12020 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12021 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
12022 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12023 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
12024 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12025 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
12026 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12027 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
12028 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12029 {}
12030 };
12031
12032 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
12033
12034 static void advansys_set_latency(struct pci_dev *pdev)
12035 {
12036 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
12037 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
12038 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
12039 } else {
12040 u8 latency;
12041 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
12042 if (latency < 0x20)
12043 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
12044 }
12045 }
12046
12047 static int advansys_pci_probe(struct pci_dev *pdev,
12048 const struct pci_device_id *ent)
12049 {
12050 int err, ioport;
12051 struct Scsi_Host *shost;
12052 struct asc_board *board;
12053
12054 err = pci_enable_device(pdev);
12055 if (err)
12056 goto fail;
12057 err = pci_request_regions(pdev, DRV_NAME);
12058 if (err)
12059 goto disable_device;
12060 pci_set_master(pdev);
12061 advansys_set_latency(pdev);
12062
12063 err = -ENODEV;
12064 if (pci_resource_len(pdev, 0) == 0)
12065 goto release_region;
12066
12067 ioport = pci_resource_start(pdev, 0);
12068
12069 err = -ENOMEM;
12070 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12071 if (!shost)
12072 goto release_region;
12073
12074 board = shost_priv(shost);
12075 board->irq = pdev->irq;
12076 board->dev = &pdev->dev;
12077 board->shost = shost;
12078
12079 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
12080 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
12081 pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
12082 board->flags |= ASC_IS_WIDE_BOARD;
12083 }
12084
12085 err = advansys_board_found(shost, ioport, ASC_IS_PCI);
12086 if (err)
12087 goto free_host;
12088
12089 pci_set_drvdata(pdev, shost);
12090 return 0;
12091
12092 free_host:
12093 scsi_host_put(shost);
12094 release_region:
12095 pci_release_regions(pdev);
12096 disable_device:
12097 pci_disable_device(pdev);
12098 fail:
12099 return err;
12100 }
12101
12102 static void advansys_pci_remove(struct pci_dev *pdev)
12103 {
12104 advansys_release(pci_get_drvdata(pdev));
12105 pci_release_regions(pdev);
12106 pci_disable_device(pdev);
12107 }
12108
12109 static struct pci_driver advansys_pci_driver = {
12110 .name = DRV_NAME,
12111 .id_table = advansys_pci_tbl,
12112 .probe = advansys_pci_probe,
12113 .remove = advansys_pci_remove,
12114 };
12115
12116 static int __init advansys_init(void)
12117 {
12118 int error;
12119
12120 error = isa_register_driver(&advansys_isa_driver,
12121 ASC_IOADR_TABLE_MAX_IX);
12122 if (error)
12123 goto fail;
12124
12125 error = isa_register_driver(&advansys_vlb_driver,
12126 ASC_IOADR_TABLE_MAX_IX);
12127 if (error)
12128 goto unregister_isa;
12129
12130 error = eisa_driver_register(&advansys_eisa_driver);
12131 if (error)
12132 goto unregister_vlb;
12133
12134 error = pci_register_driver(&advansys_pci_driver);
12135 if (error)
12136 goto unregister_eisa;
12137
12138 return 0;
12139
12140 unregister_eisa:
12141 eisa_driver_unregister(&advansys_eisa_driver);
12142 unregister_vlb:
12143 isa_unregister_driver(&advansys_vlb_driver);
12144 unregister_isa:
12145 isa_unregister_driver(&advansys_isa_driver);
12146 fail:
12147 return error;
12148 }
12149
12150 static void __exit advansys_exit(void)
12151 {
12152 pci_unregister_driver(&advansys_pci_driver);
12153 eisa_driver_unregister(&advansys_eisa_driver);
12154 isa_unregister_driver(&advansys_vlb_driver);
12155 isa_unregister_driver(&advansys_isa_driver);
12156 }
12157
12158 module_init(advansys_init);
12159 module_exit(advansys_exit);
12160
12161 MODULE_LICENSE("GPL");
12162 MODULE_FIRMWARE("advansys/mcode.bin");
12163 MODULE_FIRMWARE("advansys/3550.bin");
12164 MODULE_FIRMWARE("advansys/38C0800.bin");
12165 MODULE_FIRMWARE("advansys/38C1600.bin");
Linux kernel - Deliverables
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