1 #define DRV_NAME "advansys"
2 #define ASC_VERSION "3.4" /* AdvanSys Driver Version */
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
10 * All Rights Reserved.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/ioport.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/slab.h>
33 #include <linux/proc_fs.h>
34 #include <linux/init.h>
35 #include <linux/blkdev.h>
36 #include <linux/isa.h>
37 #include <linux/eisa.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock.h>
40 #include <linux/dma-mapping.h>
43 #include <asm/system.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <scsi/scsi_tcq.h>
49 #include <scsi/scsi.h>
50 #include <scsi/scsi_host.h>
54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
69 * 8. Add module_param to override ISA/VLB ioport array
71 #warning this driver is still not properly converted to the DMA API
73 /* Enable driver /proc statistics. */
74 #define ADVANSYS_STATS
76 /* Enable driver tracing. */
82 * Any instance where a 32-bit long or pointer type is assumed
83 * for precision or HW defined structures, the following define
84 * types must be used. In Linux the char, short, and int types
85 * are all consistent at 8, 16, and 32 bits respectively. Pointers
86 * and long types are 64 bits on Alpha and UltraSPARC.
88 #define ASC_PADDR __u32 /* Physical/Bus address data type. */
89 #define ASC_VADDR __u32 /* Virtual address data type. */
90 #define ASC_DCNT __u32 /* Unsigned Data count type. */
91 #define ASC_SDCNT __s32 /* Signed Data count type. */
93 typedef unsigned char uchar
;
103 #define UW_ERR (uint)(0xFFFF)
104 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
106 #define PCI_VENDOR_ID_ASP 0x10cd
107 #define PCI_DEVICE_ID_ASP_1200A 0x1100
108 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
109 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
110 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
111 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
112 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
115 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
116 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
117 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
120 #define CC_VERY_LONG_SG_LIST 0
121 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
123 #define PortAddr unsigned short /* port address size */
124 #define inp(port) inb(port)
125 #define outp(port, byte) outb((byte), (port))
127 #define inpw(port) inw(port)
128 #define outpw(port, word) outw((word), (port))
130 #define ASC_MAX_SG_QUEUE 7
131 #define ASC_MAX_SG_LIST 255
133 #define ASC_CS_TYPE unsigned short
135 #define ASC_IS_ISA (0x0001)
136 #define ASC_IS_ISAPNP (0x0081)
137 #define ASC_IS_EISA (0x0002)
138 #define ASC_IS_PCI (0x0004)
139 #define ASC_IS_PCI_ULTRA (0x0104)
140 #define ASC_IS_PCMCIA (0x0008)
141 #define ASC_IS_MCA (0x0020)
142 #define ASC_IS_VL (0x0040)
143 #define ASC_IS_WIDESCSI_16 (0x0100)
144 #define ASC_IS_WIDESCSI_32 (0x0200)
145 #define ASC_IS_BIG_ENDIAN (0x8000)
147 #define ASC_CHIP_MIN_VER_VL (0x01)
148 #define ASC_CHIP_MAX_VER_VL (0x07)
149 #define ASC_CHIP_MIN_VER_PCI (0x09)
150 #define ASC_CHIP_MAX_VER_PCI (0x0F)
151 #define ASC_CHIP_VER_PCI_BIT (0x08)
152 #define ASC_CHIP_MIN_VER_ISA (0x11)
153 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
154 #define ASC_CHIP_MAX_VER_ISA (0x27)
155 #define ASC_CHIP_VER_ISA_BIT (0x30)
156 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
157 #define ASC_CHIP_VER_ASYN_BUG (0x21)
158 #define ASC_CHIP_VER_PCI 0x08
159 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
160 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
161 #define ASC_CHIP_MIN_VER_EISA (0x41)
162 #define ASC_CHIP_MAX_VER_EISA (0x47)
163 #define ASC_CHIP_VER_EISA_BIT (0x40)
164 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
165 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
166 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
167 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
169 #define ASC_SCSI_ID_BITS 3
170 #define ASC_SCSI_TIX_TYPE uchar
171 #define ASC_ALL_DEVICE_BIT_SET 0xFF
172 #define ASC_SCSI_BIT_ID_TYPE uchar
173 #define ASC_MAX_TID 7
174 #define ASC_MAX_LUN 7
175 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
176 #define ASC_MAX_SENSE_LEN 32
177 #define ASC_MIN_SENSE_LEN 14
178 #define ASC_SCSI_RESET_HOLD_TIME_US 60
181 * Narrow boards only support 12-byte commands, while wide boards
182 * extend to 16-byte commands.
184 #define ASC_MAX_CDB_LEN 12
185 #define ADV_MAX_CDB_LEN 16
187 #define MS_SDTR_LEN 0x03
188 #define MS_WDTR_LEN 0x02
190 #define ASC_SG_LIST_PER_Q 7
192 #define QS_READY 0x01
193 #define QS_DISC1 0x02
194 #define QS_DISC2 0x04
196 #define QS_ABORTED 0x40
198 #define QC_NO_CALLBACK 0x01
199 #define QC_SG_SWAP_QUEUE 0x02
200 #define QC_SG_HEAD 0x04
201 #define QC_DATA_IN 0x08
202 #define QC_DATA_OUT 0x10
203 #define QC_URGENT 0x20
204 #define QC_MSG_OUT 0x40
205 #define QC_REQ_SENSE 0x80
206 #define QCSG_SG_XFER_LIST 0x02
207 #define QCSG_SG_XFER_MORE 0x04
208 #define QCSG_SG_XFER_END 0x08
209 #define QD_IN_PROGRESS 0x00
210 #define QD_NO_ERROR 0x01
211 #define QD_ABORTED_BY_HOST 0x02
212 #define QD_WITH_ERROR 0x04
213 #define QD_INVALID_REQUEST 0x80
214 #define QD_INVALID_HOST_NUM 0x81
215 #define QD_INVALID_DEVICE 0x82
216 #define QD_ERR_INTERNAL 0xFF
217 #define QHSTA_NO_ERROR 0x00
218 #define QHSTA_M_SEL_TIMEOUT 0x11
219 #define QHSTA_M_DATA_OVER_RUN 0x12
220 #define QHSTA_M_DATA_UNDER_RUN 0x12
221 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
222 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
223 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
224 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
225 #define QHSTA_D_HOST_ABORT_FAILED 0x23
226 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
227 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
228 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
229 #define QHSTA_M_WTM_TIMEOUT 0x41
230 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
231 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
232 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
233 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
234 #define QHSTA_M_BAD_TAG_CODE 0x46
235 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
236 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
237 #define QHSTA_D_LRAM_CMP_ERROR 0x81
238 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
239 #define ASC_FLAG_SCSIQ_REQ 0x01
240 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
241 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
242 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
243 #define ASC_FLAG_WIN16 0x10
244 #define ASC_FLAG_WIN32 0x20
245 #define ASC_FLAG_ISA_OVER_16MB 0x40
246 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
247 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
248 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
249 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
250 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
251 #define ASC_SCSIQ_CPY_BEG 4
252 #define ASC_SCSIQ_SGHD_CPY_BEG 2
253 #define ASC_SCSIQ_B_FWD 0
254 #define ASC_SCSIQ_B_BWD 1
255 #define ASC_SCSIQ_B_STATUS 2
256 #define ASC_SCSIQ_B_QNO 3
257 #define ASC_SCSIQ_B_CNTL 4
258 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
259 #define ASC_SCSIQ_D_DATA_ADDR 8
260 #define ASC_SCSIQ_D_DATA_CNT 12
261 #define ASC_SCSIQ_B_SENSE_LEN 20
262 #define ASC_SCSIQ_DONE_INFO_BEG 22
263 #define ASC_SCSIQ_D_SRBPTR 22
264 #define ASC_SCSIQ_B_TARGET_IX 26
265 #define ASC_SCSIQ_B_CDB_LEN 28
266 #define ASC_SCSIQ_B_TAG_CODE 29
267 #define ASC_SCSIQ_W_VM_ID 30
268 #define ASC_SCSIQ_DONE_STATUS 32
269 #define ASC_SCSIQ_HOST_STATUS 33
270 #define ASC_SCSIQ_SCSI_STATUS 34
271 #define ASC_SCSIQ_CDB_BEG 36
272 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
273 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
274 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
275 #define ASC_SCSIQ_B_SG_WK_QP 49
276 #define ASC_SCSIQ_B_SG_WK_IX 50
277 #define ASC_SCSIQ_W_ALT_DC1 52
278 #define ASC_SCSIQ_B_LIST_CNT 6
279 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
280 #define ASC_SGQ_B_SG_CNTL 4
281 #define ASC_SGQ_B_SG_HEAD_QP 5
282 #define ASC_SGQ_B_SG_LIST_CNT 6
283 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
284 #define ASC_SGQ_LIST_BEG 8
285 #define ASC_DEF_SCSI1_QNG 4
286 #define ASC_MAX_SCSI1_QNG 4
287 #define ASC_DEF_SCSI2_QNG 16
288 #define ASC_MAX_SCSI2_QNG 32
289 #define ASC_TAG_CODE_MASK 0x23
290 #define ASC_STOP_REQ_RISC_STOP 0x01
291 #define ASC_STOP_ACK_RISC_STOP 0x03
292 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
293 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
294 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
295 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
296 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
297 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
298 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
299 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
300 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
301 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
303 typedef struct asc_scsiq_1
{
312 ASC_PADDR sense_addr
;
317 typedef struct asc_scsiq_2
{
326 typedef struct asc_scsiq_3
{
333 typedef struct asc_scsiq_4
{
334 uchar cdb
[ASC_MAX_CDB_LEN
];
335 uchar y_first_sg_list_qp
;
336 uchar y_working_sg_qp
;
337 uchar y_working_sg_ix
;
340 ushort x_reconnect_rtn
;
341 ASC_PADDR x_saved_data_addr
;
342 ASC_DCNT x_saved_data_cnt
;
345 typedef struct asc_q_done_info
{
354 ASC_DCNT remain_bytes
;
357 typedef struct asc_sg_list
{
362 typedef struct asc_sg_head
{
365 ushort entry_to_copy
;
367 ASC_SG_LIST sg_list
[0];
370 typedef struct asc_scsi_q
{
374 ASC_SG_HEAD
*sg_head
;
375 ushort remain_sg_entry_cnt
;
376 ushort next_sg_index
;
379 typedef struct asc_scsi_req_q
{
383 ASC_SG_HEAD
*sg_head
;
386 uchar cdb
[ASC_MAX_CDB_LEN
];
387 uchar sense
[ASC_MIN_SENSE_LEN
];
390 typedef struct asc_scsi_bios_req_q
{
394 ASC_SG_HEAD
*sg_head
;
397 uchar cdb
[ASC_MAX_CDB_LEN
];
398 uchar sense
[ASC_MIN_SENSE_LEN
];
399 } ASC_SCSI_BIOS_REQ_Q
;
401 typedef struct asc_risc_q
{
410 typedef struct asc_sg_list_q
{
416 uchar sg_cur_list_cnt
;
419 typedef struct asc_risc_sg_list_q
{
423 ASC_SG_LIST sg_list
[7];
424 } ASC_RISC_SG_LIST_Q
;
426 #define ASCQ_ERR_Q_STATUS 0x0D
427 #define ASCQ_ERR_CUR_QNG 0x17
428 #define ASCQ_ERR_SG_Q_LINKS 0x18
429 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
430 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
431 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
434 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
436 #define ASC_WARN_NO_ERROR 0x0000
437 #define ASC_WARN_IO_PORT_ROTATE 0x0001
438 #define ASC_WARN_EEPROM_CHKSUM 0x0002
439 #define ASC_WARN_IRQ_MODIFIED 0x0004
440 #define ASC_WARN_AUTO_CONFIG 0x0008
441 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
442 #define ASC_WARN_EEPROM_RECOVER 0x0020
443 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
446 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
448 #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
449 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
450 #define ASC_IERR_SET_PC_ADDR 0x0004
451 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
452 #define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
453 #define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
454 #define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
455 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
456 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
457 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
458 #define ASC_IERR_NO_BUS_TYPE 0x0400
459 #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
460 #define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
461 #define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
463 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
464 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
465 #define ASC_MIN_FREE_Q (0x02)
466 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
467 #define ASC_MAX_TOTAL_QNG 240
468 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
469 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
470 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
471 #define ASC_MAX_INRAM_TAG_QNG 16
472 #define ASC_IOADR_GAP 0x10
473 #define ASC_SYN_MAX_OFFSET 0x0F
474 #define ASC_DEF_SDTR_OFFSET 0x0F
475 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
476 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
478 /* The narrow chip only supports a limited selection of transfer rates.
479 * These are encoded in the range 0..7 or 0..15 depending whether the chip
480 * is Ultra-capable or not. These tables let us convert from one to the other.
482 static const unsigned char asc_syn_xfer_period
[8] = {
483 25, 30, 35, 40, 50, 60, 70, 85
486 static const unsigned char asc_syn_ultra_xfer_period
[16] = {
487 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
490 typedef struct ext_msg
{
496 uchar sdtr_xfer_period
;
497 uchar sdtr_req_ack_offset
;
512 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
513 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
514 #define wdtr_width u_ext_msg.wdtr.wdtr_width
515 #define mdp_b3 u_ext_msg.mdp_b3
516 #define mdp_b2 u_ext_msg.mdp_b2
517 #define mdp_b1 u_ext_msg.mdp_b1
518 #define mdp_b0 u_ext_msg.mdp_b0
520 typedef struct asc_dvc_cfg
{
521 ASC_SCSI_BIT_ID_TYPE can_tagged_qng
;
522 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled
;
523 ASC_SCSI_BIT_ID_TYPE disc_enable
;
524 ASC_SCSI_BIT_ID_TYPE sdtr_enable
;
527 uchar isa_dma_channel
;
530 ushort mcode_version
;
531 uchar max_tag_qng
[ASC_MAX_TID
+ 1];
533 uchar sdtr_period_offset
[ASC_MAX_TID
+ 1];
534 uchar adapter_info
[6];
537 #define ASC_DEF_DVC_CNTL 0xFFFF
538 #define ASC_DEF_CHIP_SCSI_ID 7
539 #define ASC_DEF_ISA_DMA_SPEED 4
540 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
541 #define ASC_INIT_STATE_END_GET_CFG 0x0002
542 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
543 #define ASC_INIT_STATE_END_SET_CFG 0x0008
544 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
545 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
546 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
547 #define ASC_INIT_STATE_END_INQUIRY 0x0080
548 #define ASC_INIT_RESET_SCSI_DONE 0x0100
549 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
550 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
551 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
552 #define ASC_MIN_TAGGED_CMD 7
553 #define ASC_MAX_SCSI_RESET_WAIT 30
555 struct asc_dvc_var
; /* Forward Declaration. */
557 typedef struct asc_dvc_var
{
563 ASC_SCSI_BIT_ID_TYPE init_sdtr
;
564 ASC_SCSI_BIT_ID_TYPE sdtr_done
;
565 ASC_SCSI_BIT_ID_TYPE use_tagged_qng
;
566 ASC_SCSI_BIT_ID_TYPE unit_not_ready
;
567 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy
;
568 ASC_SCSI_BIT_ID_TYPE start_motor
;
569 uchar scsi_reset_wait
;
574 uchar in_critical_cnt
;
575 uchar last_q_shortage
;
577 uchar cur_dvc_qng
[ASC_MAX_TID
+ 1];
578 uchar max_dvc_qng
[ASC_MAX_TID
+ 1];
579 ASC_SCSI_Q
*scsiq_busy_head
[ASC_MAX_TID
+ 1];
580 ASC_SCSI_Q
*scsiq_busy_tail
[ASC_MAX_TID
+ 1];
581 const uchar
*sdtr_period_tbl
;
583 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always
;
586 uchar dos_int13_table
[ASC_MAX_TID
+ 1];
587 ASC_DCNT max_dma_count
;
588 ASC_SCSI_BIT_ID_TYPE no_scam
;
589 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer
;
590 uchar min_sdtr_index
;
591 uchar max_sdtr_index
;
592 struct asc_board
*drv_ptr
;
598 typedef struct asc_dvc_inq_info
{
599 uchar type
[ASC_MAX_TID
+ 1][ASC_MAX_LUN
+ 1];
602 typedef struct asc_cap_info
{
607 typedef struct asc_cap_info_array
{
608 ASC_CAP_INFO cap_info
[ASC_MAX_TID
+ 1][ASC_MAX_LUN
+ 1];
609 } ASC_CAP_INFO_ARRAY
;
611 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
612 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
613 #define ASC_CNTL_INITIATOR (ushort)0x0001
614 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
615 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
616 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
617 #define ASC_CNTL_NO_SCAM (ushort)0x0010
618 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
619 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
620 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
621 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
622 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
623 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
624 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
625 #define ASC_CNTL_BURST_MODE (ushort)0x2000
626 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
627 #define ASC_EEP_DVC_CFG_BEG_VL 2
628 #define ASC_EEP_MAX_DVC_ADDR_VL 15
629 #define ASC_EEP_DVC_CFG_BEG 32
630 #define ASC_EEP_MAX_DVC_ADDR 45
631 #define ASC_EEP_MAX_RETRY 20
634 * These macros keep the chip SCSI id and ISA DMA speed
635 * bitfields in board order. C bitfields aren't portable
636 * between big and little-endian platforms so they are
640 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
641 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
642 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
643 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
644 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
645 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
647 typedef struct asceep_config
{
659 uchar id_speed
; /* low order 4 bits is chip scsi id */
660 /* high order 4 bits is isa dma speed */
661 uchar dos_int13_table
[ASC_MAX_TID
+ 1];
662 uchar adapter_info
[6];
667 #define ASC_EEP_CMD_READ 0x80
668 #define ASC_EEP_CMD_WRITE 0x40
669 #define ASC_EEP_CMD_WRITE_ABLE 0x30
670 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
671 #define ASC_OVERRUN_BSIZE 0x00000048UL
672 #define ASCV_MSGOUT_BEG 0x0000
673 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
674 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
675 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
676 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
677 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
678 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
679 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
680 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
681 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
682 #define ASCV_BREAK_ADDR (ushort)0x0028
683 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
684 #define ASCV_BREAK_CONTROL (ushort)0x002C
685 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
687 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
688 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
689 #define ASCV_MCODE_SIZE_W (ushort)0x0034
690 #define ASCV_STOP_CODE_B (ushort)0x0036
691 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
692 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
693 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
694 #define ASCV_HALTCODE_W (ushort)0x0040
695 #define ASCV_CHKSUM_W (ushort)0x0042
696 #define ASCV_MC_DATE_W (ushort)0x0044
697 #define ASCV_MC_VER_W (ushort)0x0046
698 #define ASCV_NEXTRDY_B (ushort)0x0048
699 #define ASCV_DONENEXT_B (ushort)0x0049
700 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
701 #define ASCV_SCSIBUSY_B (ushort)0x004B
702 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
703 #define ASCV_CURCDB_B (ushort)0x004D
704 #define ASCV_RCLUN_B (ushort)0x004E
705 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
706 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
707 #define ASCV_DISC_ENABLE_B (ushort)0x0052
708 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
709 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
710 #define ASCV_MCODE_CNTL_B (ushort)0x0056
711 #define ASCV_NULL_TARGET_B (ushort)0x0057
712 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
713 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
714 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
715 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
716 #define ASCV_HOST_FLAG_B (ushort)0x005D
717 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
718 #define ASCV_VER_SERIAL_B (ushort)0x0065
719 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
720 #define ASCV_WTM_FLAG_B (ushort)0x0068
721 #define ASCV_RISC_FLAG_B (ushort)0x006A
722 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
723 #define ASC_HOST_FLAG_IN_ISR 0x01
724 #define ASC_HOST_FLAG_ACK_INT 0x02
725 #define ASC_RISC_FLAG_GEN_INT 0x01
726 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
727 #define IOP_CTRL (0x0F)
728 #define IOP_STATUS (0x0E)
729 #define IOP_INT_ACK IOP_STATUS
730 #define IOP_REG_IFC (0x0D)
731 #define IOP_SYN_OFFSET (0x0B)
732 #define IOP_EXTRA_CONTROL (0x0D)
733 #define IOP_REG_PC (0x0C)
734 #define IOP_RAM_ADDR (0x0A)
735 #define IOP_RAM_DATA (0x08)
736 #define IOP_EEP_DATA (0x06)
737 #define IOP_EEP_CMD (0x07)
738 #define IOP_VERSION (0x03)
739 #define IOP_CONFIG_HIGH (0x04)
740 #define IOP_CONFIG_LOW (0x02)
741 #define IOP_SIG_BYTE (0x01)
742 #define IOP_SIG_WORD (0x00)
743 #define IOP_REG_DC1 (0x0E)
744 #define IOP_REG_DC0 (0x0C)
745 #define IOP_REG_SB (0x0B)
746 #define IOP_REG_DA1 (0x0A)
747 #define IOP_REG_DA0 (0x08)
748 #define IOP_REG_SC (0x09)
749 #define IOP_DMA_SPEED (0x07)
750 #define IOP_REG_FLAG (0x07)
751 #define IOP_FIFO_H (0x06)
752 #define IOP_FIFO_L (0x04)
753 #define IOP_REG_ID (0x05)
754 #define IOP_REG_QP (0x03)
755 #define IOP_REG_IH (0x02)
756 #define IOP_REG_IX (0x01)
757 #define IOP_REG_AX (0x00)
758 #define IFC_REG_LOCK (0x00)
759 #define IFC_REG_UNLOCK (0x09)
760 #define IFC_WR_EN_FILTER (0x10)
761 #define IFC_RD_NO_EEPROM (0x10)
762 #define IFC_SLEW_RATE (0x20)
763 #define IFC_ACT_NEG (0x40)
764 #define IFC_INP_FILTER (0x80)
765 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
766 #define SC_SEL (uchar)(0x80)
767 #define SC_BSY (uchar)(0x40)
768 #define SC_ACK (uchar)(0x20)
769 #define SC_REQ (uchar)(0x10)
770 #define SC_ATN (uchar)(0x08)
771 #define SC_IO (uchar)(0x04)
772 #define SC_CD (uchar)(0x02)
773 #define SC_MSG (uchar)(0x01)
774 #define SEC_SCSI_CTL (uchar)(0x80)
775 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
776 #define SEC_SLEW_RATE (uchar)(0x20)
777 #define SEC_ENABLE_FILTER (uchar)(0x10)
778 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
779 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
780 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
781 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
782 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
783 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
784 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
785 #define ASC_MAX_QNO 0xF8
786 #define ASC_DATA_SEC_BEG (ushort)0x0080
787 #define ASC_DATA_SEC_END (ushort)0x0080
788 #define ASC_CODE_SEC_BEG (ushort)0x0080
789 #define ASC_CODE_SEC_END (ushort)0x0080
790 #define ASC_QADR_BEG (0x4000)
791 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
792 #define ASC_QADR_END (ushort)0x7FFF
793 #define ASC_QLAST_ADR (ushort)0x7FC0
794 #define ASC_QBLK_SIZE 0x40
795 #define ASC_BIOS_DATA_QBEG 0xF8
796 #define ASC_MIN_ACTIVE_QNO 0x01
797 #define ASC_QLINK_END 0xFF
798 #define ASC_EEPROM_WORDS 0x10
799 #define ASC_MAX_MGS_LEN 0x10
800 #define ASC_BIOS_ADDR_DEF 0xDC00
801 #define ASC_BIOS_SIZE 0x3800
802 #define ASC_BIOS_RAM_OFF 0x3800
803 #define ASC_BIOS_RAM_SIZE 0x800
804 #define ASC_BIOS_MIN_ADDR 0xC000
805 #define ASC_BIOS_MAX_ADDR 0xEC00
806 #define ASC_BIOS_BANK_SIZE 0x0400
807 #define ASC_MCODE_START_ADDR 0x0080
808 #define ASC_CFG0_HOST_INT_ON 0x0020
809 #define ASC_CFG0_BIOS_ON 0x0040
810 #define ASC_CFG0_VERA_BURST_ON 0x0080
811 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
812 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
813 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
814 #define ASC_CFG_MSW_CLR_MASK 0x3080
815 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
816 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
817 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
818 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
819 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
820 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
821 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
822 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
823 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
824 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
825 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
826 #define CSW_HALTED (ASC_CS_TYPE)0x0010
827 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
828 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
829 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
830 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
831 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
832 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
833 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
834 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
835 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
836 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
837 #define CC_CHIP_RESET (uchar)0x80
838 #define CC_SCSI_RESET (uchar)0x40
839 #define CC_HALT (uchar)0x20
840 #define CC_SINGLE_STEP (uchar)0x10
841 #define CC_DMA_ABLE (uchar)0x08
842 #define CC_TEST (uchar)0x04
843 #define CC_BANK_ONE (uchar)0x02
844 #define CC_DIAG (uchar)0x01
845 #define ASC_1000_ID0W 0x04C1
846 #define ASC_1000_ID0W_FIX 0x00C1
847 #define ASC_1000_ID1B 0x25
848 #define ASC_EISA_REV_IOP_MASK (0x0C83)
849 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
850 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
851 #define INS_HALTINT (ushort)0x6281
852 #define INS_HALT (ushort)0x6280
853 #define INS_SINT (ushort)0x6200
854 #define INS_RFLAG_WTM (ushort)0x7380
855 #define ASC_MC_SAVE_CODE_WSIZE 0x500
856 #define ASC_MC_SAVE_DATA_WSIZE 0x40
858 typedef struct asc_mc_saved
{
859 ushort data
[ASC_MC_SAVE_DATA_WSIZE
];
860 ushort code
[ASC_MC_SAVE_CODE_WSIZE
];
863 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
864 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
865 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
866 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
867 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
868 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
869 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
870 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
871 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
872 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
873 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
874 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
875 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
876 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
877 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
878 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
879 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
880 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
881 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
882 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
883 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
884 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
885 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
886 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
887 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
888 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
889 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
890 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
891 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
892 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
893 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
894 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
895 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
896 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
897 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
898 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
899 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
900 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
901 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
902 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
903 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
904 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
905 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
906 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
907 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
908 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
909 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
910 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
911 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
912 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
913 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
914 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
915 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
916 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
917 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
918 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
919 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
920 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
921 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
922 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
923 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
924 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
925 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
926 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
927 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
928 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
929 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
932 * Portable Data Types
934 * Any instance where a 32-bit long or pointer type is assumed
935 * for precision or HW defined structures, the following define
936 * types must be used. In Linux the char, short, and int types
937 * are all consistent at 8, 16, and 32 bits respectively. Pointers
938 * and long types are 64 bits on Alpha and UltraSPARC.
940 #define ADV_PADDR __u32 /* Physical address data type. */
941 #define ADV_VADDR __u32 /* Virtual address data type. */
942 #define ADV_DCNT __u32 /* Unsigned Data count type. */
943 #define ADV_SDCNT __s32 /* Signed Data count type. */
946 * These macros are used to convert a virtual address to a
947 * 32-bit value. This currently can be used on Linux Alpha
948 * which uses 64-bit virtual address but a 32-bit bus address.
949 * This is likely to break in the future, but doing this now
950 * will give us time to change the HW and FW to handle 64-bit
953 #define ADV_VADDR_TO_U32 virt_to_bus
954 #define ADV_U32_TO_VADDR bus_to_virt
956 #define AdvPortAddr void __iomem * /* Virtual memory address size */
959 * Define Adv Library required memory access macros.
961 #define ADV_MEM_READB(addr) readb(addr)
962 #define ADV_MEM_READW(addr) readw(addr)
963 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
964 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
965 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
967 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
970 * Define total number of simultaneous maximum element scatter-gather
971 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
972 * maximum number of outstanding commands per wide host adapter. Each
973 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
974 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
975 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
976 * structures or 255 scatter-gather elements.
978 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
981 * Define maximum number of scatter-gather elements per request.
983 #define ADV_MAX_SG_LIST 255
984 #define NO_OF_SG_PER_BLOCK 15
986 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
987 #define ADV_EEP_DVC_CFG_END (0x15)
988 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
989 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
991 #define ADV_EEP_DELAY_MS 100
993 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
994 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
996 * For the ASC3550 Bit 13 is Termination Polarity control bit.
997 * For later ICs Bit 13 controls whether the CIS (Card Information
998 * Service Section) is loaded from EEPROM.
1000 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
1001 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
1005 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1006 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1007 * Function 0 will specify INT B.
1009 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1010 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1011 * Function 1 will specify INT A.
1013 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
1015 typedef struct adveep_3550_config
{
1016 /* Word Offset, Description */
1018 ushort cfg_lsw
; /* 00 power up initialization */
1019 /* bit 13 set - Term Polarity Control */
1020 /* bit 14 set - BIOS Enable */
1021 /* bit 15 set - Big Endian Mode */
1022 ushort cfg_msw
; /* 01 unused */
1023 ushort disc_enable
; /* 02 disconnect enable */
1024 ushort wdtr_able
; /* 03 Wide DTR able */
1025 ushort sdtr_able
; /* 04 Synchronous DTR able */
1026 ushort start_motor
; /* 05 send start up motor */
1027 ushort tagqng_able
; /* 06 tag queuing able */
1028 ushort bios_scan
; /* 07 BIOS device control */
1029 ushort scam_tolerant
; /* 08 no scam */
1031 uchar adapter_scsi_id
; /* 09 Host Adapter ID */
1032 uchar bios_boot_delay
; /* power up wait */
1034 uchar scsi_reset_delay
; /* 10 reset delay */
1035 uchar bios_id_lun
; /* first boot device scsi id & lun */
1036 /* high nibble is lun */
1037 /* low nibble is scsi id */
1039 uchar termination
; /* 11 0 - automatic */
1040 /* 1 - low off / high off */
1041 /* 2 - low off / high on */
1042 /* 3 - low on / high on */
1043 /* There is no low on / high off */
1045 uchar reserved1
; /* reserved byte (not used) */
1047 ushort bios_ctrl
; /* 12 BIOS control bits */
1048 /* bit 0 BIOS don't act as initiator. */
1049 /* bit 1 BIOS > 1 GB support */
1050 /* bit 2 BIOS > 2 Disk Support */
1051 /* bit 3 BIOS don't support removables */
1052 /* bit 4 BIOS support bootable CD */
1053 /* bit 5 BIOS scan enabled */
1054 /* bit 6 BIOS support multiple LUNs */
1055 /* bit 7 BIOS display of message */
1056 /* bit 8 SCAM disabled */
1057 /* bit 9 Reset SCSI bus during init. */
1059 /* bit 11 No verbose initialization. */
1060 /* bit 12 SCSI parity enabled */
1064 ushort ultra_able
; /* 13 ULTRA speed able */
1065 ushort reserved2
; /* 14 reserved */
1066 uchar max_host_qng
; /* 15 maximum host queuing */
1067 uchar max_dvc_qng
; /* maximum per device queuing */
1068 ushort dvc_cntl
; /* 16 control bit for driver */
1069 ushort bug_fix
; /* 17 control bit for bug fix */
1070 ushort serial_number_word1
; /* 18 Board serial number word 1 */
1071 ushort serial_number_word2
; /* 19 Board serial number word 2 */
1072 ushort serial_number_word3
; /* 20 Board serial number word 3 */
1073 ushort check_sum
; /* 21 EEP check sum */
1074 uchar oem_name
[16]; /* 22 OEM name */
1075 ushort dvc_err_code
; /* 30 last device driver error code */
1076 ushort adv_err_code
; /* 31 last uc and Adv Lib error code */
1077 ushort adv_err_addr
; /* 32 last uc error address */
1078 ushort saved_dvc_err_code
; /* 33 saved last dev. driver error code */
1079 ushort saved_adv_err_code
; /* 34 saved last uc and Adv Lib error code */
1080 ushort saved_adv_err_addr
; /* 35 saved last uc error address */
1081 ushort num_of_err
; /* 36 number of error */
1082 } ADVEEP_3550_CONFIG
;
1084 typedef struct adveep_38C0800_config
{
1085 /* Word Offset, Description */
1087 ushort cfg_lsw
; /* 00 power up initialization */
1088 /* bit 13 set - Load CIS */
1089 /* bit 14 set - BIOS Enable */
1090 /* bit 15 set - Big Endian Mode */
1091 ushort cfg_msw
; /* 01 unused */
1092 ushort disc_enable
; /* 02 disconnect enable */
1093 ushort wdtr_able
; /* 03 Wide DTR able */
1094 ushort sdtr_speed1
; /* 04 SDTR Speed TID 0-3 */
1095 ushort start_motor
; /* 05 send start up motor */
1096 ushort tagqng_able
; /* 06 tag queuing able */
1097 ushort bios_scan
; /* 07 BIOS device control */
1098 ushort scam_tolerant
; /* 08 no scam */
1100 uchar adapter_scsi_id
; /* 09 Host Adapter ID */
1101 uchar bios_boot_delay
; /* power up wait */
1103 uchar scsi_reset_delay
; /* 10 reset delay */
1104 uchar bios_id_lun
; /* first boot device scsi id & lun */
1105 /* high nibble is lun */
1106 /* low nibble is scsi id */
1108 uchar termination_se
; /* 11 0 - automatic */
1109 /* 1 - low off / high off */
1110 /* 2 - low off / high on */
1111 /* 3 - low on / high on */
1112 /* There is no low on / high off */
1114 uchar termination_lvd
; /* 11 0 - automatic */
1115 /* 1 - low off / high off */
1116 /* 2 - low off / high on */
1117 /* 3 - low on / high on */
1118 /* There is no low on / high off */
1120 ushort bios_ctrl
; /* 12 BIOS control bits */
1121 /* bit 0 BIOS don't act as initiator. */
1122 /* bit 1 BIOS > 1 GB support */
1123 /* bit 2 BIOS > 2 Disk Support */
1124 /* bit 3 BIOS don't support removables */
1125 /* bit 4 BIOS support bootable CD */
1126 /* bit 5 BIOS scan enabled */
1127 /* bit 6 BIOS support multiple LUNs */
1128 /* bit 7 BIOS display of message */
1129 /* bit 8 SCAM disabled */
1130 /* bit 9 Reset SCSI bus during init. */
1132 /* bit 11 No verbose initialization. */
1133 /* bit 12 SCSI parity enabled */
1137 ushort sdtr_speed2
; /* 13 SDTR speed TID 4-7 */
1138 ushort sdtr_speed3
; /* 14 SDTR speed TID 8-11 */
1139 uchar max_host_qng
; /* 15 maximum host queueing */
1140 uchar max_dvc_qng
; /* maximum per device queuing */
1141 ushort dvc_cntl
; /* 16 control bit for driver */
1142 ushort sdtr_speed4
; /* 17 SDTR speed 4 TID 12-15 */
1143 ushort serial_number_word1
; /* 18 Board serial number word 1 */
1144 ushort serial_number_word2
; /* 19 Board serial number word 2 */
1145 ushort serial_number_word3
; /* 20 Board serial number word 3 */
1146 ushort check_sum
; /* 21 EEP check sum */
1147 uchar oem_name
[16]; /* 22 OEM name */
1148 ushort dvc_err_code
; /* 30 last device driver error code */
1149 ushort adv_err_code
; /* 31 last uc and Adv Lib error code */
1150 ushort adv_err_addr
; /* 32 last uc error address */
1151 ushort saved_dvc_err_code
; /* 33 saved last dev. driver error code */
1152 ushort saved_adv_err_code
; /* 34 saved last uc and Adv Lib error code */
1153 ushort saved_adv_err_addr
; /* 35 saved last uc error address */
1154 ushort reserved36
; /* 36 reserved */
1155 ushort reserved37
; /* 37 reserved */
1156 ushort reserved38
; /* 38 reserved */
1157 ushort reserved39
; /* 39 reserved */
1158 ushort reserved40
; /* 40 reserved */
1159 ushort reserved41
; /* 41 reserved */
1160 ushort reserved42
; /* 42 reserved */
1161 ushort reserved43
; /* 43 reserved */
1162 ushort reserved44
; /* 44 reserved */
1163 ushort reserved45
; /* 45 reserved */
1164 ushort reserved46
; /* 46 reserved */
1165 ushort reserved47
; /* 47 reserved */
1166 ushort reserved48
; /* 48 reserved */
1167 ushort reserved49
; /* 49 reserved */
1168 ushort reserved50
; /* 50 reserved */
1169 ushort reserved51
; /* 51 reserved */
1170 ushort reserved52
; /* 52 reserved */
1171 ushort reserved53
; /* 53 reserved */
1172 ushort reserved54
; /* 54 reserved */
1173 ushort reserved55
; /* 55 reserved */
1174 ushort cisptr_lsw
; /* 56 CIS PTR LSW */
1175 ushort cisprt_msw
; /* 57 CIS PTR MSW */
1176 ushort subsysvid
; /* 58 SubSystem Vendor ID */
1177 ushort subsysid
; /* 59 SubSystem ID */
1178 ushort reserved60
; /* 60 reserved */
1179 ushort reserved61
; /* 61 reserved */
1180 ushort reserved62
; /* 62 reserved */
1181 ushort reserved63
; /* 63 reserved */
1182 } ADVEEP_38C0800_CONFIG
;
1184 typedef struct adveep_38C1600_config
{
1185 /* Word Offset, Description */
1187 ushort cfg_lsw
; /* 00 power up initialization */
1188 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1189 /* clear - Func. 0 INTA, Func. 1 INTB */
1190 /* bit 13 set - Load CIS */
1191 /* bit 14 set - BIOS Enable */
1192 /* bit 15 set - Big Endian Mode */
1193 ushort cfg_msw
; /* 01 unused */
1194 ushort disc_enable
; /* 02 disconnect enable */
1195 ushort wdtr_able
; /* 03 Wide DTR able */
1196 ushort sdtr_speed1
; /* 04 SDTR Speed TID 0-3 */
1197 ushort start_motor
; /* 05 send start up motor */
1198 ushort tagqng_able
; /* 06 tag queuing able */
1199 ushort bios_scan
; /* 07 BIOS device control */
1200 ushort scam_tolerant
; /* 08 no scam */
1202 uchar adapter_scsi_id
; /* 09 Host Adapter ID */
1203 uchar bios_boot_delay
; /* power up wait */
1205 uchar scsi_reset_delay
; /* 10 reset delay */
1206 uchar bios_id_lun
; /* first boot device scsi id & lun */
1207 /* high nibble is lun */
1208 /* low nibble is scsi id */
1210 uchar termination_se
; /* 11 0 - automatic */
1211 /* 1 - low off / high off */
1212 /* 2 - low off / high on */
1213 /* 3 - low on / high on */
1214 /* There is no low on / high off */
1216 uchar termination_lvd
; /* 11 0 - automatic */
1217 /* 1 - low off / high off */
1218 /* 2 - low off / high on */
1219 /* 3 - low on / high on */
1220 /* There is no low on / high off */
1222 ushort bios_ctrl
; /* 12 BIOS control bits */
1223 /* bit 0 BIOS don't act as initiator. */
1224 /* bit 1 BIOS > 1 GB support */
1225 /* bit 2 BIOS > 2 Disk Support */
1226 /* bit 3 BIOS don't support removables */
1227 /* bit 4 BIOS support bootable CD */
1228 /* bit 5 BIOS scan enabled */
1229 /* bit 6 BIOS support multiple LUNs */
1230 /* bit 7 BIOS display of message */
1231 /* bit 8 SCAM disabled */
1232 /* bit 9 Reset SCSI bus during init. */
1233 /* bit 10 Basic Integrity Checking disabled */
1234 /* bit 11 No verbose initialization. */
1235 /* bit 12 SCSI parity enabled */
1236 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1239 ushort sdtr_speed2
; /* 13 SDTR speed TID 4-7 */
1240 ushort sdtr_speed3
; /* 14 SDTR speed TID 8-11 */
1241 uchar max_host_qng
; /* 15 maximum host queueing */
1242 uchar max_dvc_qng
; /* maximum per device queuing */
1243 ushort dvc_cntl
; /* 16 control bit for driver */
1244 ushort sdtr_speed4
; /* 17 SDTR speed 4 TID 12-15 */
1245 ushort serial_number_word1
; /* 18 Board serial number word 1 */
1246 ushort serial_number_word2
; /* 19 Board serial number word 2 */
1247 ushort serial_number_word3
; /* 20 Board serial number word 3 */
1248 ushort check_sum
; /* 21 EEP check sum */
1249 uchar oem_name
[16]; /* 22 OEM name */
1250 ushort dvc_err_code
; /* 30 last device driver error code */
1251 ushort adv_err_code
; /* 31 last uc and Adv Lib error code */
1252 ushort adv_err_addr
; /* 32 last uc error address */
1253 ushort saved_dvc_err_code
; /* 33 saved last dev. driver error code */
1254 ushort saved_adv_err_code
; /* 34 saved last uc and Adv Lib error code */
1255 ushort saved_adv_err_addr
; /* 35 saved last uc error address */
1256 ushort reserved36
; /* 36 reserved */
1257 ushort reserved37
; /* 37 reserved */
1258 ushort reserved38
; /* 38 reserved */
1259 ushort reserved39
; /* 39 reserved */
1260 ushort reserved40
; /* 40 reserved */
1261 ushort reserved41
; /* 41 reserved */
1262 ushort reserved42
; /* 42 reserved */
1263 ushort reserved43
; /* 43 reserved */
1264 ushort reserved44
; /* 44 reserved */
1265 ushort reserved45
; /* 45 reserved */
1266 ushort reserved46
; /* 46 reserved */
1267 ushort reserved47
; /* 47 reserved */
1268 ushort reserved48
; /* 48 reserved */
1269 ushort reserved49
; /* 49 reserved */
1270 ushort reserved50
; /* 50 reserved */
1271 ushort reserved51
; /* 51 reserved */
1272 ushort reserved52
; /* 52 reserved */
1273 ushort reserved53
; /* 53 reserved */
1274 ushort reserved54
; /* 54 reserved */
1275 ushort reserved55
; /* 55 reserved */
1276 ushort cisptr_lsw
; /* 56 CIS PTR LSW */
1277 ushort cisprt_msw
; /* 57 CIS PTR MSW */
1278 ushort subsysvid
; /* 58 SubSystem Vendor ID */
1279 ushort subsysid
; /* 59 SubSystem ID */
1280 ushort reserved60
; /* 60 reserved */
1281 ushort reserved61
; /* 61 reserved */
1282 ushort reserved62
; /* 62 reserved */
1283 ushort reserved63
; /* 63 reserved */
1284 } ADVEEP_38C1600_CONFIG
;
1289 #define ASC_EEP_CMD_DONE 0x0200
1292 #define BIOS_CTRL_BIOS 0x0001
1293 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
1294 #define BIOS_CTRL_GT_2_DISK 0x0004
1295 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1296 #define BIOS_CTRL_BOOTABLE_CD 0x0010
1297 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
1298 #define BIOS_CTRL_DISPLAY_MSG 0x0080
1299 #define BIOS_CTRL_NO_SCAM 0x0100
1300 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1301 #define BIOS_CTRL_INIT_VERBOSE 0x0800
1302 #define BIOS_CTRL_SCSI_PARITY 0x1000
1303 #define BIOS_CTRL_AIPP_DIS 0x2000
1305 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1307 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1310 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1311 * a special 16K Adv Library and Microcode version. After the issue is
1312 * resolved, should restore 32K support.
1314 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1316 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1319 * Byte I/O register address from base of 'iop_base'.
1321 #define IOPB_INTR_STATUS_REG 0x00
1322 #define IOPB_CHIP_ID_1 0x01
1323 #define IOPB_INTR_ENABLES 0x02
1324 #define IOPB_CHIP_TYPE_REV 0x03
1325 #define IOPB_RES_ADDR_4 0x04
1326 #define IOPB_RES_ADDR_5 0x05
1327 #define IOPB_RAM_DATA 0x06
1328 #define IOPB_RES_ADDR_7 0x07
1329 #define IOPB_FLAG_REG 0x08
1330 #define IOPB_RES_ADDR_9 0x09
1331 #define IOPB_RISC_CSR 0x0A
1332 #define IOPB_RES_ADDR_B 0x0B
1333 #define IOPB_RES_ADDR_C 0x0C
1334 #define IOPB_RES_ADDR_D 0x0D
1335 #define IOPB_SOFT_OVER_WR 0x0E
1336 #define IOPB_RES_ADDR_F 0x0F
1337 #define IOPB_MEM_CFG 0x10
1338 #define IOPB_RES_ADDR_11 0x11
1339 #define IOPB_GPIO_DATA 0x12
1340 #define IOPB_RES_ADDR_13 0x13
1341 #define IOPB_FLASH_PAGE 0x14
1342 #define IOPB_RES_ADDR_15 0x15
1343 #define IOPB_GPIO_CNTL 0x16
1344 #define IOPB_RES_ADDR_17 0x17
1345 #define IOPB_FLASH_DATA 0x18
1346 #define IOPB_RES_ADDR_19 0x19
1347 #define IOPB_RES_ADDR_1A 0x1A
1348 #define IOPB_RES_ADDR_1B 0x1B
1349 #define IOPB_RES_ADDR_1C 0x1C
1350 #define IOPB_RES_ADDR_1D 0x1D
1351 #define IOPB_RES_ADDR_1E 0x1E
1352 #define IOPB_RES_ADDR_1F 0x1F
1353 #define IOPB_DMA_CFG0 0x20
1354 #define IOPB_DMA_CFG1 0x21
1355 #define IOPB_TICKLE 0x22
1356 #define IOPB_DMA_REG_WR 0x23
1357 #define IOPB_SDMA_STATUS 0x24
1358 #define IOPB_SCSI_BYTE_CNT 0x25
1359 #define IOPB_HOST_BYTE_CNT 0x26
1360 #define IOPB_BYTE_LEFT_TO_XFER 0x27
1361 #define IOPB_BYTE_TO_XFER_0 0x28
1362 #define IOPB_BYTE_TO_XFER_1 0x29
1363 #define IOPB_BYTE_TO_XFER_2 0x2A
1364 #define IOPB_BYTE_TO_XFER_3 0x2B
1365 #define IOPB_ACC_GRP 0x2C
1366 #define IOPB_RES_ADDR_2D 0x2D
1367 #define IOPB_DEV_ID 0x2E
1368 #define IOPB_RES_ADDR_2F 0x2F
1369 #define IOPB_SCSI_DATA 0x30
1370 #define IOPB_RES_ADDR_31 0x31
1371 #define IOPB_RES_ADDR_32 0x32
1372 #define IOPB_SCSI_DATA_HSHK 0x33
1373 #define IOPB_SCSI_CTRL 0x34
1374 #define IOPB_RES_ADDR_35 0x35
1375 #define IOPB_RES_ADDR_36 0x36
1376 #define IOPB_RES_ADDR_37 0x37
1377 #define IOPB_RAM_BIST 0x38
1378 #define IOPB_PLL_TEST 0x39
1379 #define IOPB_PCI_INT_CFG 0x3A
1380 #define IOPB_RES_ADDR_3B 0x3B
1381 #define IOPB_RFIFO_CNT 0x3C
1382 #define IOPB_RES_ADDR_3D 0x3D
1383 #define IOPB_RES_ADDR_3E 0x3E
1384 #define IOPB_RES_ADDR_3F 0x3F
1387 * Word I/O register address from base of 'iop_base'.
1389 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
1390 #define IOPW_CTRL_REG 0x02 /* CC */
1391 #define IOPW_RAM_ADDR 0x04 /* LA */
1392 #define IOPW_RAM_DATA 0x06 /* LD */
1393 #define IOPW_RES_ADDR_08 0x08
1394 #define IOPW_RISC_CSR 0x0A /* CSR */
1395 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1396 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1397 #define IOPW_RES_ADDR_10 0x10
1398 #define IOPW_SEL_MASK 0x12 /* SM */
1399 #define IOPW_RES_ADDR_14 0x14
1400 #define IOPW_FLASH_ADDR 0x16 /* FA */
1401 #define IOPW_RES_ADDR_18 0x18
1402 #define IOPW_EE_CMD 0x1A /* EC */
1403 #define IOPW_EE_DATA 0x1C /* ED */
1404 #define IOPW_SFIFO_CNT 0x1E /* SFC */
1405 #define IOPW_RES_ADDR_20 0x20
1406 #define IOPW_Q_BASE 0x22 /* QB */
1407 #define IOPW_QP 0x24 /* QP */
1408 #define IOPW_IX 0x26 /* IX */
1409 #define IOPW_SP 0x28 /* SP */
1410 #define IOPW_PC 0x2A /* PC */
1411 #define IOPW_RES_ADDR_2C 0x2C
1412 #define IOPW_RES_ADDR_2E 0x2E
1413 #define IOPW_SCSI_DATA 0x30 /* SD */
1414 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1415 #define IOPW_SCSI_CTRL 0x34 /* SC */
1416 #define IOPW_HSHK_CFG 0x36 /* HCFG */
1417 #define IOPW_SXFR_STATUS 0x36 /* SXS */
1418 #define IOPW_SXFR_CNTL 0x38 /* SXL */
1419 #define IOPW_SXFR_CNTH 0x3A /* SXH */
1420 #define IOPW_RES_ADDR_3C 0x3C
1421 #define IOPW_RFIFO_DATA 0x3E /* RFD */
1424 * Doubleword I/O register address from base of 'iop_base'.
1426 #define IOPDW_RES_ADDR_0 0x00
1427 #define IOPDW_RAM_DATA 0x04
1428 #define IOPDW_RES_ADDR_8 0x08
1429 #define IOPDW_RES_ADDR_C 0x0C
1430 #define IOPDW_RES_ADDR_10 0x10
1431 #define IOPDW_COMMA 0x14
1432 #define IOPDW_COMMB 0x18
1433 #define IOPDW_RES_ADDR_1C 0x1C
1434 #define IOPDW_SDMA_ADDR0 0x20
1435 #define IOPDW_SDMA_ADDR1 0x24
1436 #define IOPDW_SDMA_COUNT 0x28
1437 #define IOPDW_SDMA_ERROR 0x2C
1438 #define IOPDW_RDMA_ADDR0 0x30
1439 #define IOPDW_RDMA_ADDR1 0x34
1440 #define IOPDW_RDMA_COUNT 0x38
1441 #define IOPDW_RDMA_ERROR 0x3C
1443 #define ADV_CHIP_ID_BYTE 0x25
1444 #define ADV_CHIP_ID_WORD 0x04C1
1446 #define ADV_INTR_ENABLE_HOST_INTR 0x01
1447 #define ADV_INTR_ENABLE_SEL_INTR 0x02
1448 #define ADV_INTR_ENABLE_DPR_INTR 0x04
1449 #define ADV_INTR_ENABLE_RTA_INTR 0x08
1450 #define ADV_INTR_ENABLE_RMA_INTR 0x10
1451 #define ADV_INTR_ENABLE_RST_INTR 0x20
1452 #define ADV_INTR_ENABLE_DPE_INTR 0x40
1453 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1455 #define ADV_INTR_STATUS_INTRA 0x01
1456 #define ADV_INTR_STATUS_INTRB 0x02
1457 #define ADV_INTR_STATUS_INTRC 0x04
1459 #define ADV_RISC_CSR_STOP (0x0000)
1460 #define ADV_RISC_TEST_COND (0x2000)
1461 #define ADV_RISC_CSR_RUN (0x4000)
1462 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1464 #define ADV_CTRL_REG_HOST_INTR 0x0100
1465 #define ADV_CTRL_REG_SEL_INTR 0x0200
1466 #define ADV_CTRL_REG_DPR_INTR 0x0400
1467 #define ADV_CTRL_REG_RTA_INTR 0x0800
1468 #define ADV_CTRL_REG_RMA_INTR 0x1000
1469 #define ADV_CTRL_REG_RES_BIT14 0x2000
1470 #define ADV_CTRL_REG_DPE_INTR 0x4000
1471 #define ADV_CTRL_REG_POWER_DONE 0x8000
1472 #define ADV_CTRL_REG_ANY_INTR 0xFF00
1474 #define ADV_CTRL_REG_CMD_RESET 0x00C6
1475 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1476 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1477 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1478 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1480 #define ADV_TICKLE_NOP 0x00
1481 #define ADV_TICKLE_A 0x01
1482 #define ADV_TICKLE_B 0x02
1483 #define ADV_TICKLE_C 0x03
1485 #define AdvIsIntPending(port) \
1486 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1489 * SCSI_CFG0 Register bit definitions
1491 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1492 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1493 #define EVEN_PARITY 0x1000 /* Select Even Parity */
1494 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1495 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1496 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1497 #define SCAM_EN 0x0080 /* Enable SCAM selection */
1498 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1499 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1500 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1501 #define OUR_ID 0x000F /* SCSI ID */
1504 * SCSI_CFG1 Register bit definitions
1506 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1507 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1508 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1509 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
1510 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1511 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1512 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1513 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1514 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1515 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1516 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1517 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1518 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1519 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1520 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1523 * Addendum for ASC-38C0800 Chip
1525 * The ASC-38C1600 Chip uses the same definitions except that the
1526 * bus mode override bits [12:10] have been moved to byte register
1527 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1528 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1529 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1530 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1531 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1533 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1534 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1535 #define HVD 0x1000 /* HVD Device Detect */
1536 #define LVD 0x0800 /* LVD Device Detect */
1537 #define SE 0x0400 /* SE Device Detect */
1538 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
1539 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1540 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1541 #define TERM_SE 0x0030 /* SE Termination Bits */
1542 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1543 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1544 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1545 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1546 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1547 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1548 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1549 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1551 #define CABLE_ILLEGAL_A 0x7
1552 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1554 #define CABLE_ILLEGAL_B 0xB
1555 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1558 * MEM_CFG Register bit definitions
1560 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1561 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1562 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1563 #define RAM_SZ_2KB 0x00 /* 2 KB */
1564 #define RAM_SZ_4KB 0x04 /* 4 KB */
1565 #define RAM_SZ_8KB 0x08 /* 8 KB */
1566 #define RAM_SZ_16KB 0x0C /* 16 KB */
1567 #define RAM_SZ_32KB 0x10 /* 32 KB */
1568 #define RAM_SZ_64KB 0x14 /* 64 KB */
1571 * DMA_CFG0 Register bit definitions
1573 * This register is only accessible to the host.
1575 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1576 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1577 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
1578 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
1579 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
1580 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
1581 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1582 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
1583 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
1584 #define START_CTL 0x0C /* DMA start conditions */
1585 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
1586 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1587 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1588 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1589 #define READ_CMD 0x03 /* Memory Read Method */
1590 #define READ_CMD_MR 0x00 /* Memory Read */
1591 #define READ_CMD_MRL 0x02 /* Memory Read Long */
1592 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1595 * ASC-38C0800 RAM BIST Register bit definitions
1597 #define RAM_TEST_MODE 0x80
1598 #define PRE_TEST_MODE 0x40
1599 #define NORMAL_MODE 0x00
1600 #define RAM_TEST_DONE 0x10
1601 #define RAM_TEST_STATUS 0x0F
1602 #define RAM_TEST_HOST_ERROR 0x08
1603 #define RAM_TEST_INTRAM_ERROR 0x04
1604 #define RAM_TEST_RISC_ERROR 0x02
1605 #define RAM_TEST_SCSI_ERROR 0x01
1606 #define RAM_TEST_SUCCESS 0x00
1607 #define PRE_TEST_VALUE 0x05
1608 #define NORMAL_VALUE 0x00
1611 * ASC38C1600 Definitions
1613 * IOPB_PCI_INT_CFG Bit Field Definitions
1616 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1619 * Bit 1 can be set to change the interrupt for the Function to operate in
1620 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1621 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1622 * mode, otherwise the operating mode is undefined.
1624 #define TOTEMPOLE 0x02
1627 * Bit 0 can be used to change the Int Pin for the Function. The value is
1628 * 0 by default for both Functions with Function 0 using INT A and Function
1629 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1632 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1633 * value specified in the PCI Configuration Space.
1638 * Adv Library Status Definitions
1642 #define ADV_SUCCESS 1
1644 #define ADV_ERROR (-1)
1647 * ADV_DVC_VAR 'warn_code' values
1649 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1650 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1651 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
1652 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1654 #define ADV_MAX_TID 15 /* max. target identifier */
1655 #define ADV_MAX_LUN 7 /* max. logical unit number */
1658 * Fixed locations of microcode operating variables.
1660 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1661 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1662 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1663 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1664 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1665 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1666 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1667 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1668 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1669 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1670 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1671 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1672 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1673 #define ASC_MC_CHIP_TYPE 0x009A
1674 #define ASC_MC_INTRB_CODE 0x009B
1675 #define ASC_MC_WDTR_ABLE 0x009C
1676 #define ASC_MC_SDTR_ABLE 0x009E
1677 #define ASC_MC_TAGQNG_ABLE 0x00A0
1678 #define ASC_MC_DISC_ENABLE 0x00A2
1679 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
1680 #define ASC_MC_IDLE_CMD 0x00A6
1681 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1682 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1683 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1684 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1685 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1686 #define ASC_MC_SDTR_DONE 0x00B6
1687 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1688 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1689 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
1690 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1691 #define ASC_MC_WDTR_DONE 0x0124
1692 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1693 #define ASC_MC_ICQ 0x0160
1694 #define ASC_MC_IRQ 0x0164
1695 #define ASC_MC_PPR_ABLE 0x017A
1698 * BIOS LRAM variable absolute offsets.
1700 #define BIOS_CODESEG 0x54
1701 #define BIOS_CODELEN 0x56
1702 #define BIOS_SIGNATURE 0x58
1703 #define BIOS_VERSION 0x5A
1706 * Microcode Control Flags
1708 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1709 * and handled by the microcode.
1711 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1712 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1715 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1717 #define HSHK_CFG_WIDE_XFR 0x8000
1718 #define HSHK_CFG_RATE 0x0F00
1719 #define HSHK_CFG_OFFSET 0x001F
1721 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1722 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1723 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1724 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1726 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1727 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1728 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1729 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1730 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1732 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1733 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1734 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1735 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1736 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1738 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1739 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1741 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1742 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1745 * All fields here are accessed by the board microcode and need to be
1748 typedef struct adv_carr_t
{
1749 ADV_VADDR carr_va
; /* Carrier Virtual Address */
1750 ADV_PADDR carr_pa
; /* Carrier Physical Address */
1751 ADV_VADDR areq_vpa
; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1753 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1755 * next_vpa [3:1] Reserved Bits
1756 * next_vpa [0] Done Flag set in Response Queue.
1762 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1764 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
1766 #define ASC_RQ_DONE 0x00000001
1767 #define ASC_RQ_GOOD 0x00000002
1768 #define ASC_CQ_STOPPER 0x00000000
1770 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1772 #define ADV_CARRIER_NUM_PAGE_CROSSING \
1773 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + (PAGE_SIZE - 1))/PAGE_SIZE)
1775 #define ADV_CARRIER_BUFSIZE \
1776 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
1779 * ASC_SCSI_REQ_Q 'a_flag' definitions
1781 * The Adv Library should limit use to the lower nibble (4 bits) of
1782 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1784 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
1785 #define ADV_SCSIQ_DONE 0x02 /* request done */
1786 #define ADV_DONT_RETRY 0x08 /* don't do retry */
1788 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1789 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1790 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1793 * Adapter temporary configuration structure
1795 * This structure can be discarded after initialization. Don't add
1796 * fields here needed after initialization.
1798 * Field naming convention:
1800 * *_enable indicates the field enables or disables a feature. The
1801 * value of the field is never reset.
1803 typedef struct adv_dvc_cfg
{
1804 ushort disc_enable
; /* enable disconnection */
1805 uchar chip_version
; /* chip version */
1806 uchar termination
; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1807 ushort control_flag
; /* Microcode Control Flag */
1808 ushort mcode_date
; /* Microcode date */
1809 ushort mcode_version
; /* Microcode version */
1810 ushort serial1
; /* EEPROM serial number word 1 */
1811 ushort serial2
; /* EEPROM serial number word 2 */
1812 ushort serial3
; /* EEPROM serial number word 3 */
1816 struct adv_scsi_req_q
;
1818 typedef struct asc_sg_block
{
1822 uchar sg_cnt
; /* Valid entries in block. */
1823 ADV_PADDR sg_ptr
; /* Pointer to next sg block. */
1825 ADV_PADDR sg_addr
; /* SG element address. */
1826 ADV_DCNT sg_count
; /* SG element count. */
1827 } sg_list
[NO_OF_SG_PER_BLOCK
];
1831 * ADV_SCSI_REQ_Q - microcode request structure
1833 * All fields in this structure up to byte 60 are used by the microcode.
1834 * The microcode makes assumptions about the size and ordering of fields
1835 * in this structure. Do not change the structure definition here without
1836 * coordinating the change with the microcode.
1838 * All fields accessed by microcode must be maintained in little_endian
1841 typedef struct adv_scsi_req_q
{
1842 uchar cntl
; /* Ucode flags and state (ASC_MC_QC_*). */
1844 uchar target_id
; /* Device target identifier. */
1845 uchar target_lun
; /* Device target logical unit number. */
1846 ADV_PADDR data_addr
; /* Data buffer physical address. */
1847 ADV_DCNT data_cnt
; /* Data count. Ucode sets to residual. */
1848 ADV_PADDR sense_addr
;
1852 uchar cdb_len
; /* SCSI CDB length. Must <= 16 bytes. */
1854 uchar done_status
; /* Completion status. */
1855 uchar scsi_status
; /* SCSI status byte. */
1856 uchar host_status
; /* Ucode host status. */
1857 uchar sg_working_ix
;
1858 uchar cdb
[12]; /* SCSI CDB bytes 0-11. */
1859 ADV_PADDR sg_real_addr
; /* SG list physical address. */
1860 ADV_PADDR scsiq_rptr
;
1861 uchar cdb16
[4]; /* SCSI CDB bytes 12-15. */
1862 ADV_VADDR scsiq_ptr
;
1865 * End of microcode structure - 60 bytes. The rest of the structure
1866 * is used by the Adv Library and ignored by the microcode.
1869 ADV_SG_BLOCK
*sg_list_ptr
; /* SG list virtual address. */
1870 char *vdata_addr
; /* Data buffer virtual address. */
1872 uchar pad
[2]; /* Pad out to a word boundary. */
1876 * The following two structures are used to process Wide Board requests.
1878 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1879 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
1880 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
1881 * Mid-Level SCSI request structure.
1883 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1884 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1885 * up to 255 scatter-gather elements may be used per request or
1888 * Both structures must be 32 byte aligned.
1890 typedef struct adv_sgblk
{
1891 ADV_SG_BLOCK sg_block
; /* Sgblock structure. */
1892 uchar align
[32]; /* Sgblock structure padding. */
1893 struct adv_sgblk
*next_sgblkp
; /* Next scatter-gather structure. */
1896 typedef struct adv_req
{
1897 ADV_SCSI_REQ_Q scsi_req_q
; /* Adv Library request structure. */
1898 uchar align
[32]; /* Request structure padding. */
1899 struct scsi_cmnd
*cmndp
; /* Mid-Level SCSI command pointer. */
1900 adv_sgblk_t
*sgblkp
; /* Adv Library scatter-gather pointer. */
1901 struct adv_req
*next_reqp
; /* Next Request Structure. */
1905 * Adapter operation variable structure.
1907 * One structure is required per host adapter.
1909 * Field naming convention:
1911 * *_able indicates both whether a feature should be enabled or disabled
1912 * and whether a device isi capable of the feature. At initialization
1913 * this field may be set, but later if a device is found to be incapable
1914 * of the feature, the field is cleared.
1916 typedef struct adv_dvc_var
{
1917 AdvPortAddr iop_base
; /* I/O port address */
1918 ushort err_code
; /* fatal error code */
1919 ushort bios_ctrl
; /* BIOS control word, EEPROM word 12 */
1920 ushort wdtr_able
; /* try WDTR for a device */
1921 ushort sdtr_able
; /* try SDTR for a device */
1922 ushort ultra_able
; /* try SDTR Ultra speed for a device */
1923 ushort sdtr_speed1
; /* EEPROM SDTR Speed for TID 0-3 */
1924 ushort sdtr_speed2
; /* EEPROM SDTR Speed for TID 4-7 */
1925 ushort sdtr_speed3
; /* EEPROM SDTR Speed for TID 8-11 */
1926 ushort sdtr_speed4
; /* EEPROM SDTR Speed for TID 12-15 */
1927 ushort tagqng_able
; /* try tagged queuing with a device */
1928 ushort ppr_able
; /* PPR message capable per TID bitmask. */
1929 uchar max_dvc_qng
; /* maximum number of tagged commands per device */
1930 ushort start_motor
; /* start motor command allowed */
1931 uchar scsi_reset_wait
; /* delay in seconds after scsi bus reset */
1932 uchar chip_no
; /* should be assigned by caller */
1933 uchar max_host_qng
; /* maximum number of Q'ed command allowed */
1934 ushort no_scam
; /* scam_tolerant of EEPROM */
1935 struct asc_board
*drv_ptr
; /* driver pointer to private structure */
1936 uchar chip_scsi_id
; /* chip SCSI target ID */
1938 uchar bist_err_code
;
1939 ADV_CARR_T
*carrier_buf
;
1940 ADV_CARR_T
*carr_freelist
; /* Carrier free list. */
1941 ADV_CARR_T
*icq_sp
; /* Initiator command queue stopper pointer. */
1942 ADV_CARR_T
*irq_sp
; /* Initiator response queue stopper pointer. */
1943 ushort carr_pending_cnt
; /* Count of pending carriers. */
1944 struct adv_req
*orig_reqp
; /* adv_req_t memory block. */
1946 * Note: The following fields will not be used after initialization. The
1947 * driver may discard the buffer after initialization is done.
1949 ADV_DVC_CFG
*cfg
; /* temporary configuration structure */
1953 * Microcode idle loop commands
1955 #define IDLE_CMD_COMPLETED 0
1956 #define IDLE_CMD_STOP_CHIP 0x0001
1957 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
1958 #define IDLE_CMD_SEND_INT 0x0004
1959 #define IDLE_CMD_ABORT 0x0008
1960 #define IDLE_CMD_DEVICE_RESET 0x0010
1961 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
1962 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
1963 #define IDLE_CMD_SCSIREQ 0x0080
1965 #define IDLE_CMD_STATUS_SUCCESS 0x0001
1966 #define IDLE_CMD_STATUS_FAILURE 0x0002
1969 * AdvSendIdleCmd() flag definitions.
1971 #define ADV_NOWAIT 0x01
1974 * Wait loop time out values.
1976 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
1977 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
1978 #define SCSI_MAX_RETRY 10 /* retry count */
1980 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
1981 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
1982 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
1983 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
1985 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
1987 /* Read byte from a register. */
1988 #define AdvReadByteRegister(iop_base, reg_off) \
1989 (ADV_MEM_READB((iop_base) + (reg_off)))
1991 /* Write byte to a register. */
1992 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
1993 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1995 /* Read word (2 bytes) from a register. */
1996 #define AdvReadWordRegister(iop_base, reg_off) \
1997 (ADV_MEM_READW((iop_base) + (reg_off)))
1999 /* Write word (2 bytes) to a register. */
2000 #define AdvWriteWordRegister(iop_base, reg_off, word) \
2001 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2003 /* Write dword (4 bytes) to a register. */
2004 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2005 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2007 /* Read byte from LRAM. */
2008 #define AdvReadByteLram(iop_base, addr, byte) \
2010 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2011 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2014 /* Write byte to LRAM. */
2015 #define AdvWriteByteLram(iop_base, addr, byte) \
2016 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2017 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2019 /* Read word (2 bytes) from LRAM. */
2020 #define AdvReadWordLram(iop_base, addr, word) \
2022 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2023 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2026 /* Write word (2 bytes) to LRAM. */
2027 #define AdvWriteWordLram(iop_base, addr, word) \
2028 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2029 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2031 /* Write little-endian double word (4 bytes) to LRAM */
2032 /* Because of unspecified C language ordering don't use auto-increment. */
2033 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2034 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2035 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2036 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2037 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2038 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2039 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2041 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2042 #define AdvReadWordAutoIncLram(iop_base) \
2043 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2045 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2046 #define AdvWriteWordAutoIncLram(iop_base, word) \
2047 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2050 * Define macro to check for Condor signature.
2052 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2053 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2055 #define AdvFindSignature(iop_base) \
2056 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2057 ADV_CHIP_ID_BYTE) && \
2058 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2059 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2062 * Define macro to Return the version number of the chip at 'iop_base'.
2064 * The second parameter 'bus_type' is currently unused.
2066 #define AdvGetChipVersion(iop_base, bus_type) \
2067 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2070 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
2071 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
2073 * If the request has not yet been sent to the device it will simply be
2074 * aborted from RISC memory. If the request is disconnected it will be
2075 * aborted on reselection by sending an Abort Message to the target ID.
2078 * ADV_TRUE(1) - Queue was successfully aborted.
2079 * ADV_FALSE(0) - Queue was not found on the active queue list.
2081 #define AdvAbortQueue(asc_dvc, scsiq) \
2082 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2086 * Send a Bus Device Reset Message to the specified target ID.
2088 * All outstanding commands will be purged if sending the
2089 * Bus Device Reset Message is successful.
2092 * ADV_TRUE(1) - All requests on the target are purged.
2093 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2096 #define AdvResetDevice(asc_dvc, target_id) \
2097 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2098 (ADV_DCNT) (target_id))
2101 * SCSI Wide Type definition.
2103 #define ADV_SCSI_BIT_ID_TYPE ushort
2106 * AdvInitScsiTarget() 'cntl_flag' options.
2108 #define ADV_SCAN_LUN 0x01
2109 #define ADV_CAPINFO_NOLUN 0x02
2112 * Convert target id to target id bit mask.
2114 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2117 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2120 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
2121 #define QD_NO_ERROR 0x01
2122 #define QD_ABORTED_BY_HOST 0x02
2123 #define QD_WITH_ERROR 0x04
2125 #define QHSTA_NO_ERROR 0x00
2126 #define QHSTA_M_SEL_TIMEOUT 0x11
2127 #define QHSTA_M_DATA_OVER_RUN 0x12
2128 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2129 #define QHSTA_M_QUEUE_ABORTED 0x15
2130 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2131 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2132 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2133 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2134 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2135 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2136 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
2137 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2138 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2139 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2140 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2141 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2142 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2143 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2144 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2145 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
2146 #define QHSTA_M_WTM_TIMEOUT 0x41
2147 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2148 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2149 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2150 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2151 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2152 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
2154 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2155 #define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
2156 #define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
2157 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2160 * Total contiguous memory needed for driver SG blocks.
2162 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2163 * number of scatter-gather elements the driver supports in a
2167 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2168 (sizeof(ADV_SG_BLOCK) * \
2169 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2171 /* struct asc_board flags */
2172 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
2174 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2176 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
2178 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
2180 #ifdef CONFIG_PROC_FS
2181 /* /proc/scsi/advansys/[0...] related definitions */
2182 #define ASC_PRTBUF_SIZE 2048
2183 #define ASC_PRTLINE_SIZE 160
2185 #define ASC_PRT_NEXT() \
2189 if (leftlen == 0) { \
2194 #endif /* CONFIG_PROC_FS */
2196 /* Asc Library return codes */
2199 #define ASC_NOERROR 1
2201 #define ASC_ERROR (-1)
2203 /* struct scsi_cmnd function return codes */
2204 #define STATUS_BYTE(byte) (byte)
2205 #define MSG_BYTE(byte) ((byte) << 8)
2206 #define HOST_BYTE(byte) ((byte) << 16)
2207 #define DRIVER_BYTE(byte) ((byte) << 24)
2209 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2210 #ifndef ADVANSYS_STATS
2211 #define ASC_STATS_ADD(shost, counter, count)
2212 #else /* ADVANSYS_STATS */
2213 #define ASC_STATS_ADD(shost, counter, count) \
2214 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2215 #endif /* ADVANSYS_STATS */
2217 /* If the result wraps when calculating tenths, return 0. */
2218 #define ASC_TENTHS(num, den) \
2219 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2220 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2223 * Display a message to the console.
2225 #define ASC_PRINT(s) \
2227 printk("advansys: "); \
2231 #define ASC_PRINT1(s, a1) \
2233 printk("advansys: "); \
2234 printk((s), (a1)); \
2237 #define ASC_PRINT2(s, a1, a2) \
2239 printk("advansys: "); \
2240 printk((s), (a1), (a2)); \
2243 #define ASC_PRINT3(s, a1, a2, a3) \
2245 printk("advansys: "); \
2246 printk((s), (a1), (a2), (a3)); \
2249 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2251 printk("advansys: "); \
2252 printk((s), (a1), (a2), (a3), (a4)); \
2255 #ifndef ADVANSYS_DEBUG
2257 #define ASC_DBG(lvl, s...)
2258 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2259 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2260 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2261 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2262 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2263 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2264 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2265 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2266 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2268 #else /* ADVANSYS_DEBUG */
2271 * Debugging Message Levels:
2273 * 1: High-Level Tracing
2274 * 2-N: Verbose Tracing
2277 #define ASC_DBG(lvl, format, arg...) { \
2278 if (asc_dbglvl >= (lvl)) \
2279 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
2280 __FUNCTION__ , ## arg); \
2283 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2285 if (asc_dbglvl >= (lvl)) { \
2286 asc_prt_scsi_host(s); \
2290 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2292 if (asc_dbglvl >= (lvl)) { \
2293 asc_prt_asc_scsi_q(scsiqp); \
2297 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2299 if (asc_dbglvl >= (lvl)) { \
2300 asc_prt_asc_qdone_info(qdone); \
2304 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2306 if (asc_dbglvl >= (lvl)) { \
2307 asc_prt_adv_scsi_req_q(scsiqp); \
2311 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2313 if (asc_dbglvl >= (lvl)) { \
2314 asc_prt_hex((name), (start), (length)); \
2318 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2319 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2321 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2322 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2324 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2325 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2326 #endif /* ADVANSYS_DEBUG */
2328 #ifdef ADVANSYS_STATS
2330 /* Per board statistics structure */
2332 /* Driver Entrypoint Statistics */
2333 ADV_DCNT queuecommand
; /* # calls to advansys_queuecommand() */
2334 ADV_DCNT reset
; /* # calls to advansys_eh_bus_reset() */
2335 ADV_DCNT biosparam
; /* # calls to advansys_biosparam() */
2336 ADV_DCNT interrupt
; /* # advansys_interrupt() calls */
2337 ADV_DCNT callback
; /* # calls to asc/adv_isr_callback() */
2338 ADV_DCNT done
; /* # calls to request's scsi_done function */
2339 ADV_DCNT build_error
; /* # asc/adv_build_req() ASC_ERROR returns. */
2340 ADV_DCNT adv_build_noreq
; /* # adv_build_req() adv_req_t alloc. fail. */
2341 ADV_DCNT adv_build_nosg
; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2342 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2343 ADV_DCNT exe_noerror
; /* # ASC_NOERROR returns. */
2344 ADV_DCNT exe_busy
; /* # ASC_BUSY returns. */
2345 ADV_DCNT exe_error
; /* # ASC_ERROR returns. */
2346 ADV_DCNT exe_unknown
; /* # unknown returns. */
2347 /* Data Transfer Statistics */
2348 ADV_DCNT xfer_cnt
; /* # I/O requests received */
2349 ADV_DCNT xfer_elem
; /* # scatter-gather elements */
2350 ADV_DCNT xfer_sect
; /* # 512-byte blocks */
2352 #endif /* ADVANSYS_STATS */
2355 * Structure allocated for each board.
2357 * This structure is allocated by scsi_host_alloc() at the end
2358 * of the 'Scsi_Host' structure starting at the 'hostdata'
2359 * field. It is guaranteed to be allocated from DMA-able memory.
2363 uint flags
; /* Board flags */
2366 ASC_DVC_VAR asc_dvc_var
; /* Narrow board */
2367 ADV_DVC_VAR adv_dvc_var
; /* Wide board */
2370 ASC_DVC_CFG asc_dvc_cfg
; /* Narrow board */
2371 ADV_DVC_CFG adv_dvc_cfg
; /* Wide board */
2373 ushort asc_n_io_port
; /* Number I/O ports. */
2374 ADV_SCSI_BIT_ID_TYPE init_tidmask
; /* Target init./valid mask */
2375 ushort reqcnt
[ADV_MAX_TID
+ 1]; /* Starvation request count */
2376 ADV_SCSI_BIT_ID_TYPE queue_full
; /* Queue full mask */
2377 ushort queue_full_cnt
[ADV_MAX_TID
+ 1]; /* Queue full count */
2379 ASCEEP_CONFIG asc_eep
; /* Narrow EEPROM config. */
2380 ADVEEP_3550_CONFIG adv_3550_eep
; /* 3550 EEPROM config. */
2381 ADVEEP_38C0800_CONFIG adv_38C0800_eep
; /* 38C0800 EEPROM config. */
2382 ADVEEP_38C1600_CONFIG adv_38C1600_eep
; /* 38C1600 EEPROM config. */
2384 ulong last_reset
; /* Saved last reset time */
2385 /* /proc/scsi/advansys/[0...] */
2386 char *prtbuf
; /* /proc print buffer */
2387 #ifdef ADVANSYS_STATS
2388 struct asc_stats asc_stats
; /* Board statistics */
2389 #endif /* ADVANSYS_STATS */
2391 * The following fields are used only for Narrow Boards.
2393 uchar sdtr_data
[ASC_MAX_TID
+ 1]; /* SDTR information */
2395 * The following fields are used only for Wide Boards.
2397 void __iomem
*ioremap_addr
; /* I/O Memory remap address. */
2398 ushort ioport
; /* I/O Port address. */
2399 adv_req_t
*adv_reqp
; /* Request structures. */
2400 adv_sgblk_t
*adv_sgblkp
; /* Scatter-gather structures. */
2401 ushort bios_signature
; /* BIOS Signature. */
2402 ushort bios_version
; /* BIOS Version. */
2403 ushort bios_codeseg
; /* BIOS Code Segment. */
2404 ushort bios_codelen
; /* BIOS Code Segment Length. */
2407 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2408 dvc_var.adv_dvc_var)
2409 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2411 /* Overrun buffer used by all narrow boards. */
2412 static uchar overrun_buf
[ASC_OVERRUN_BSIZE
] = { 0 };
2414 #ifdef ADVANSYS_DEBUG
2415 static int asc_dbglvl
= 3;
2418 * asc_prt_asc_dvc_var()
2420 static void asc_prt_asc_dvc_var(ASC_DVC_VAR
*h
)
2422 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong
)h
);
2424 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2425 "%d,\n", h
->iop_base
, h
->err_code
, h
->dvc_cntl
, h
->bug_fix_cntl
);
2427 printk(" bus_type %d, init_sdtr 0x%x,\n", h
->bus_type
,
2428 (unsigned)h
->init_sdtr
);
2430 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2431 "chip_no 0x%x,\n", (unsigned)h
->sdtr_done
,
2432 (unsigned)h
->use_tagged_qng
, (unsigned)h
->unit_not_ready
,
2433 (unsigned)h
->chip_no
);
2435 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2436 "%u,\n", (unsigned)h
->queue_full_or_busy
,
2437 (unsigned)h
->start_motor
, (unsigned)h
->scsi_reset_wait
);
2439 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2440 "in_critical_cnt %u,\n", (unsigned)h
->is_in_int
,
2441 (unsigned)h
->max_total_qng
, (unsigned)h
->cur_total_qng
,
2442 (unsigned)h
->in_critical_cnt
);
2444 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2445 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h
->last_q_shortage
,
2446 (unsigned)h
->init_state
, (unsigned)h
->no_scam
,
2447 (unsigned)h
->pci_fix_asyn_xfer
);
2449 printk(" cfg 0x%lx\n", (ulong
)h
->cfg
);
2453 * asc_prt_asc_dvc_cfg()
2455 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG
*h
)
2457 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong
)h
);
2459 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2460 h
->can_tagged_qng
, h
->cmd_qng_enabled
);
2461 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2462 h
->disc_enable
, h
->sdtr_enable
);
2464 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2465 "chip_version %d,\n", h
->chip_scsi_id
, h
->isa_dma_speed
,
2466 h
->isa_dma_channel
, h
->chip_version
);
2468 printk(" mcode_date 0x%x, mcode_version %d, overrun_buf 0x%p\n",
2469 h
->mcode_date
, h
->mcode_version
, h
->overrun_buf
);
2473 * asc_prt_adv_dvc_var()
2475 * Display an ADV_DVC_VAR structure.
2477 static void asc_prt_adv_dvc_var(ADV_DVC_VAR
*h
)
2479 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong
)h
);
2481 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2482 (ulong
)h
->iop_base
, h
->err_code
, (unsigned)h
->ultra_able
);
2484 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
2485 (unsigned)h
->sdtr_able
, (unsigned)h
->wdtr_able
);
2487 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
2488 (unsigned)h
->start_motor
, (unsigned)h
->scsi_reset_wait
);
2490 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
2491 (unsigned)h
->max_host_qng
, (unsigned)h
->max_dvc_qng
,
2492 (ulong
)h
->carr_freelist
);
2494 printk(" icq_sp 0x%lx, irq_sp 0x%lx\n",
2495 (ulong
)h
->icq_sp
, (ulong
)h
->irq_sp
);
2497 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2498 (unsigned)h
->no_scam
, (unsigned)h
->tagqng_able
);
2500 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2501 (unsigned)h
->chip_scsi_id
, (ulong
)h
->cfg
);
2505 * asc_prt_adv_dvc_cfg()
2507 * Display an ADV_DVC_CFG structure.
2509 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG
*h
)
2511 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong
)h
);
2513 printk(" disc_enable 0x%x, termination 0x%x\n",
2514 h
->disc_enable
, h
->termination
);
2516 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2517 h
->chip_version
, h
->mcode_date
);
2519 printk(" mcode_version 0x%x, control_flag 0x%x\n",
2520 h
->mcode_version
, h
->control_flag
);
2524 * asc_prt_scsi_host()
2526 static void asc_prt_scsi_host(struct Scsi_Host
*s
)
2528 struct asc_board
*boardp
= shost_priv(s
);
2530 printk("Scsi_Host at addr 0x%p, device %s\n", s
, boardp
->dev
->bus_id
);
2531 printk(" host_busy %u, host_no %d, last_reset %d,\n",
2532 s
->host_busy
, s
->host_no
, (unsigned)s
->last_reset
);
2534 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2535 (ulong
)s
->base
, (ulong
)s
->io_port
, boardp
->irq
);
2537 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2538 s
->dma_channel
, s
->this_id
, s
->can_queue
);
2540 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2541 s
->cmd_per_lun
, s
->sg_tablesize
, s
->unchecked_isa_dma
);
2543 if (ASC_NARROW_BOARD(boardp
)) {
2544 asc_prt_asc_dvc_var(&boardp
->dvc_var
.asc_dvc_var
);
2545 asc_prt_asc_dvc_cfg(&boardp
->dvc_cfg
.asc_dvc_cfg
);
2547 asc_prt_adv_dvc_var(&boardp
->dvc_var
.adv_dvc_var
);
2548 asc_prt_adv_dvc_cfg(&boardp
->dvc_cfg
.adv_dvc_cfg
);
2555 * Print hexadecimal output in 4 byte groupings 32 bytes
2556 * or 8 double-words per line.
2558 static void asc_prt_hex(char *f
, uchar
*s
, int l
)
2565 printk("%s: (%d bytes)\n", f
, l
);
2567 for (i
= 0; i
< l
; i
+= 32) {
2569 /* Display a maximum of 8 double-words per line. */
2570 if ((k
= (l
- i
) / 4) >= 8) {
2577 for (j
= 0; j
< k
; j
++) {
2578 printk(" %2.2X%2.2X%2.2X%2.2X",
2579 (unsigned)s
[i
+ (j
* 4)],
2580 (unsigned)s
[i
+ (j
* 4) + 1],
2581 (unsigned)s
[i
+ (j
* 4) + 2],
2582 (unsigned)s
[i
+ (j
* 4) + 3]);
2590 printk(" %2.2X", (unsigned)s
[i
+ (j
* 4)]);
2593 printk(" %2.2X%2.2X",
2594 (unsigned)s
[i
+ (j
* 4)],
2595 (unsigned)s
[i
+ (j
* 4) + 1]);
2598 printk(" %2.2X%2.2X%2.2X",
2599 (unsigned)s
[i
+ (j
* 4) + 1],
2600 (unsigned)s
[i
+ (j
* 4) + 2],
2601 (unsigned)s
[i
+ (j
* 4) + 3]);
2610 * asc_prt_asc_scsi_q()
2612 static void asc_prt_asc_scsi_q(ASC_SCSI_Q
*q
)
2617 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong
)q
);
2620 (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
2621 q
->q2
.target_ix
, q
->q1
.target_lun
, (ulong
)q
->q2
.srb_ptr
,
2625 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2626 (ulong
)le32_to_cpu(q
->q1
.data_addr
),
2627 (ulong
)le32_to_cpu(q
->q1
.data_cnt
),
2628 (ulong
)le32_to_cpu(q
->q1
.sense_addr
), q
->q1
.sense_len
);
2630 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2631 (ulong
)q
->cdbptr
, q
->q2
.cdb_len
,
2632 (ulong
)q
->sg_head
, q
->q1
.sg_queue_cnt
);
2636 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong
)sgp
);
2637 printk(" entry_cnt %u, queue_cnt %u\n", sgp
->entry_cnt
,
2639 for (i
= 0; i
< sgp
->entry_cnt
; i
++) {
2640 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2641 i
, (ulong
)le32_to_cpu(sgp
->sg_list
[i
].addr
),
2642 (ulong
)le32_to_cpu(sgp
->sg_list
[i
].bytes
));
2649 * asc_prt_asc_qdone_info()
2651 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO
*q
)
2653 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong
)q
);
2654 printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
2655 (ulong
)q
->d2
.srb_ptr
, q
->d2
.target_ix
, q
->d2
.cdb_len
,
2658 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2659 q
->d3
.done_stat
, q
->d3
.host_stat
, q
->d3
.scsi_stat
, q
->d3
.scsi_msg
);
2663 * asc_prt_adv_sgblock()
2665 * Display an ADV_SG_BLOCK structure.
2667 static void asc_prt_adv_sgblock(int sgblockno
, ADV_SG_BLOCK
*b
)
2671 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2672 (ulong
)b
, sgblockno
);
2673 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
2674 b
->sg_cnt
, (ulong
)le32_to_cpu(b
->sg_ptr
));
2675 BUG_ON(b
->sg_cnt
> NO_OF_SG_PER_BLOCK
);
2677 BUG_ON(b
->sg_cnt
!= NO_OF_SG_PER_BLOCK
);
2678 for (i
= 0; i
< b
->sg_cnt
; i
++) {
2679 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2680 i
, (ulong
)b
->sg_list
[i
].sg_addr
,
2681 (ulong
)b
->sg_list
[i
].sg_count
);
2686 * asc_prt_adv_scsi_req_q()
2688 * Display an ADV_SCSI_REQ_Q structure.
2690 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q
*q
)
2693 struct asc_sg_block
*sg_ptr
;
2695 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong
)q
);
2697 printk(" target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
2698 q
->target_id
, q
->target_lun
, (ulong
)q
->srb_ptr
, q
->a_flag
);
2700 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
2701 q
->cntl
, (ulong
)le32_to_cpu(q
->data_addr
), (ulong
)q
->vdata_addr
);
2703 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2704 (ulong
)le32_to_cpu(q
->data_cnt
),
2705 (ulong
)le32_to_cpu(q
->sense_addr
), q
->sense_len
);
2708 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2709 q
->cdb_len
, q
->done_status
, q
->host_status
, q
->scsi_status
);
2711 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2712 q
->sg_working_ix
, q
->target_cmd
);
2714 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2715 (ulong
)le32_to_cpu(q
->scsiq_rptr
),
2716 (ulong
)le32_to_cpu(q
->sg_real_addr
), (ulong
)q
->sg_list_ptr
);
2718 /* Display the request's ADV_SG_BLOCK structures. */
2719 if (q
->sg_list_ptr
!= NULL
) {
2723 * 'sg_ptr' is a physical address. Convert it to a virtual
2724 * address by indexing 'sg_blk_cnt' into the virtual address
2725 * array 'sg_list_ptr'.
2727 * XXX - Assumes all SG physical blocks are virtually contiguous.
2730 &(((ADV_SG_BLOCK
*)(q
->sg_list_ptr
))[sg_blk_cnt
]);
2731 asc_prt_adv_sgblock(sg_blk_cnt
, sg_ptr
);
2732 if (sg_ptr
->sg_ptr
== 0) {
2739 #endif /* ADVANSYS_DEBUG */
2742 * The advansys chip/microcode contains a 32-bit identifier for each command
2743 * known as the 'srb'. I don't know what it stands for. The driver used
2744 * to encode the scsi_cmnd pointer by calling virt_to_bus and retrieve it
2745 * with bus_to_virt. Now the driver keeps a per-host map of integers to
2746 * pointers. It auto-expands when full, unless it can't allocate memory.
2747 * Note that an srb of 0 is treated specially by the chip/firmware, hence
2748 * the return of i+1 in this routine, and the corresponding subtraction in
2749 * the inverse routine.
2752 static u32
advansys_ptr_to_srb(struct asc_dvc_var
*asc_dvc
, void *ptr
)
2757 for (i
= 0; i
< asc_dvc
->ptr_map_count
; i
++) {
2758 if (!asc_dvc
->ptr_map
[i
])
2762 if (asc_dvc
->ptr_map_count
== 0)
2763 asc_dvc
->ptr_map_count
= 1;
2765 asc_dvc
->ptr_map_count
*= 2;
2767 new_ptr
= krealloc(asc_dvc
->ptr_map
,
2768 asc_dvc
->ptr_map_count
* sizeof(void *), GFP_ATOMIC
);
2771 asc_dvc
->ptr_map
= new_ptr
;
2773 ASC_DBG(3, "Putting ptr %p into array offset %d\n", ptr
, i
);
2774 asc_dvc
->ptr_map
[i
] = ptr
;
2778 static void * advansys_srb_to_ptr(struct asc_dvc_var
*asc_dvc
, u32 srb
)
2783 if (srb
>= asc_dvc
->ptr_map_count
) {
2784 printk("advansys: bad SRB %u, max %u\n", srb
,
2785 asc_dvc
->ptr_map_count
);
2788 ptr
= asc_dvc
->ptr_map
[srb
];
2789 asc_dvc
->ptr_map
[srb
] = NULL
;
2790 ASC_DBG(3, "Returning ptr %p from array offset %d\n", ptr
, srb
);
2797 * Return suitable for printing on the console with the argument
2798 * adapter's configuration information.
2800 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2801 * otherwise the static 'info' array will be overrun.
2803 static const char *advansys_info(struct Scsi_Host
*shost
)
2805 static char info
[ASC_INFO_SIZE
];
2806 struct asc_board
*boardp
= shost_priv(shost
);
2807 ASC_DVC_VAR
*asc_dvc_varp
;
2808 ADV_DVC_VAR
*adv_dvc_varp
;
2810 char *widename
= NULL
;
2812 if (ASC_NARROW_BOARD(boardp
)) {
2813 asc_dvc_varp
= &boardp
->dvc_var
.asc_dvc_var
;
2814 ASC_DBG(1, "begin\n");
2815 if (asc_dvc_varp
->bus_type
& ASC_IS_ISA
) {
2816 if ((asc_dvc_varp
->bus_type
& ASC_IS_ISAPNP
) ==
2818 busname
= "ISA PnP";
2823 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2824 ASC_VERSION
, busname
,
2825 (ulong
)shost
->io_port
,
2826 (ulong
)shost
->io_port
+ ASC_IOADR_GAP
- 1,
2827 boardp
->irq
, shost
->dma_channel
);
2829 if (asc_dvc_varp
->bus_type
& ASC_IS_VL
) {
2831 } else if (asc_dvc_varp
->bus_type
& ASC_IS_EISA
) {
2833 } else if (asc_dvc_varp
->bus_type
& ASC_IS_PCI
) {
2834 if ((asc_dvc_varp
->bus_type
& ASC_IS_PCI_ULTRA
)
2835 == ASC_IS_PCI_ULTRA
) {
2836 busname
= "PCI Ultra";
2842 shost_printk(KERN_ERR
, shost
, "unknown bus "
2843 "type %d\n", asc_dvc_varp
->bus_type
);
2846 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2847 ASC_VERSION
, busname
, (ulong
)shost
->io_port
,
2848 (ulong
)shost
->io_port
+ ASC_IOADR_GAP
- 1,
2853 * Wide Adapter Information
2855 * Memory-mapped I/O is used instead of I/O space to access
2856 * the adapter, but display the I/O Port range. The Memory
2857 * I/O address is displayed through the driver /proc file.
2859 adv_dvc_varp
= &boardp
->dvc_var
.adv_dvc_var
;
2860 if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC3550
) {
2861 widename
= "Ultra-Wide";
2862 } else if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC38C0800
) {
2863 widename
= "Ultra2-Wide";
2865 widename
= "Ultra3-Wide";
2868 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2869 ASC_VERSION
, widename
, (ulong
)adv_dvc_varp
->iop_base
,
2870 (ulong
)adv_dvc_varp
->iop_base
+ boardp
->asc_n_io_port
- 1, boardp
->irq
);
2872 BUG_ON(strlen(info
) >= ASC_INFO_SIZE
);
2873 ASC_DBG(1, "end\n");
2877 #ifdef CONFIG_PROC_FS
2881 * If 'cp' is NULL print to the console, otherwise print to a buffer.
2883 * Return 0 if printing to the console, otherwise return the number of
2884 * bytes written to the buffer.
2886 * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
2887 * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
2889 static int asc_prt_line(char *buf
, int buflen
, char *fmt
, ...)
2893 char s
[ASC_PRTLINE_SIZE
];
2895 va_start(args
, fmt
);
2896 ret
= vsprintf(s
, fmt
, args
);
2897 BUG_ON(ret
>= ASC_PRTLINE_SIZE
);
2902 ret
= min(buflen
, ret
);
2903 memcpy(buf
, s
, ret
);
2910 * asc_prt_board_devices()
2912 * Print driver information for devices attached to the board.
2914 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
2915 * cf. asc_prt_line().
2917 * Return the number of characters copied into 'cp'. No more than
2918 * 'cplen' characters will be copied to 'cp'.
2920 static int asc_prt_board_devices(struct Scsi_Host
*shost
, char *cp
, int cplen
)
2922 struct asc_board
*boardp
= shost_priv(shost
);
2932 len
= asc_prt_line(cp
, leftlen
,
2933 "\nDevice Information for AdvanSys SCSI Host %d:\n",
2937 if (ASC_NARROW_BOARD(boardp
)) {
2938 chip_scsi_id
= boardp
->dvc_cfg
.asc_dvc_cfg
.chip_scsi_id
;
2940 chip_scsi_id
= boardp
->dvc_var
.adv_dvc_var
.chip_scsi_id
;
2943 len
= asc_prt_line(cp
, leftlen
, "Target IDs Detected:");
2945 for (i
= 0; i
<= ADV_MAX_TID
; i
++) {
2946 if (boardp
->init_tidmask
& ADV_TID_TO_TIDMASK(i
)) {
2947 len
= asc_prt_line(cp
, leftlen
, " %X,", i
);
2951 len
= asc_prt_line(cp
, leftlen
, " (%X=Host Adapter)\n", chip_scsi_id
);
2958 * Display Wide Board BIOS Information.
2960 static int asc_prt_adv_bios(struct Scsi_Host
*shost
, char *cp
, int cplen
)
2962 struct asc_board
*boardp
= shost_priv(shost
);
2966 ushort major
, minor
, letter
;
2971 len
= asc_prt_line(cp
, leftlen
, "\nROM BIOS Version: ");
2975 * If the BIOS saved a valid signature, then fill in
2976 * the BIOS code segment base address.
2978 if (boardp
->bios_signature
!= 0x55AA) {
2979 len
= asc_prt_line(cp
, leftlen
, "Disabled or Pre-3.1\n");
2981 len
= asc_prt_line(cp
, leftlen
,
2982 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
2984 len
= asc_prt_line(cp
, leftlen
,
2985 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2988 major
= (boardp
->bios_version
>> 12) & 0xF;
2989 minor
= (boardp
->bios_version
>> 8) & 0xF;
2990 letter
= (boardp
->bios_version
& 0xFF);
2992 len
= asc_prt_line(cp
, leftlen
, "%d.%d%c\n",
2994 letter
>= 26 ? '?' : letter
+ 'A');
2998 * Current available ROM BIOS release is 3.1I for UW
2999 * and 3.2I for U2W. This code doesn't differentiate
3000 * UW and U2W boards.
3002 if (major
< 3 || (major
<= 3 && minor
< 1) ||
3003 (major
<= 3 && minor
<= 1 && letter
< ('I' - 'A'))) {
3004 len
= asc_prt_line(cp
, leftlen
,
3005 "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
3007 len
= asc_prt_line(cp
, leftlen
,
3008 "ftp://ftp.connectcom.net/pub\n");
3017 * Add serial number to information bar if signature AAh
3018 * is found in at bit 15-9 (7 bits) of word 1.
3020 * Serial Number consists fo 12 alpha-numeric digits.
3022 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
3023 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
3024 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
3025 * 5 - Product revision (A-J) Word0: " "
3027 * Signature Word1: 15-9 (7 bits)
3028 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
3029 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
3031 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
3033 * Note 1: Only production cards will have a serial number.
3035 * Note 2: Signature is most significant 7 bits (0xFE).
3037 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
3039 static int asc_get_eeprom_string(ushort
*serialnum
, uchar
*cp
)
3043 if ((serialnum
[1] & 0xFE00) != ((ushort
)0xAA << 8)) {
3047 * First word - 6 digits.
3051 /* Product type - 1st digit. */
3052 if ((*cp
= 'A' + ((w
& 0xE000) >> 13)) == 'H') {
3053 /* Product type is P=Prototype */
3058 /* Manufacturing location - 2nd digit. */
3059 *cp
++ = 'A' + ((w
& 0x1C00) >> 10);
3061 /* Product ID - 3rd, 4th digits. */
3063 *cp
++ = '0' + (num
/ 100);
3065 *cp
++ = '0' + (num
/ 10);
3067 /* Product revision - 5th digit. */
3068 *cp
++ = 'A' + (num
% 10);
3078 * If bit 15 of third word is set, then the
3079 * last digit of the year is greater than 7.
3081 if (serialnum
[2] & 0x8000) {
3082 *cp
++ = '8' + ((w
& 0x1C0) >> 6);
3084 *cp
++ = '0' + ((w
& 0x1C0) >> 6);
3087 /* Week of year - 7th, 8th digits. */
3089 *cp
++ = '0' + num
/ 10;
3096 w
= serialnum
[2] & 0x7FFF;
3098 /* Serial number - 9th digit. */
3099 *cp
++ = 'A' + (w
/ 1000);
3101 /* 10th, 11th, 12th digits. */
3103 *cp
++ = '0' + num
/ 100;
3105 *cp
++ = '0' + num
/ 10;
3109 *cp
= '\0'; /* Null Terminate the string. */
3115 * asc_prt_asc_board_eeprom()
3117 * Print board EEPROM configuration.
3119 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3120 * cf. asc_prt_line().
3122 * Return the number of characters copied into 'cp'. No more than
3123 * 'cplen' characters will be copied to 'cp'.
3125 static int asc_prt_asc_board_eeprom(struct Scsi_Host
*shost
, char *cp
, int cplen
)
3127 struct asc_board
*boardp
= shost_priv(shost
);
3128 ASC_DVC_VAR
*asc_dvc_varp
;
3135 int isa_dma_speed
[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
3136 #endif /* CONFIG_ISA */
3137 uchar serialstr
[13];
3139 asc_dvc_varp
= &boardp
->dvc_var
.asc_dvc_var
;
3140 ep
= &boardp
->eep_config
.asc_eep
;
3145 len
= asc_prt_line(cp
, leftlen
,
3146 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3150 if (asc_get_eeprom_string((ushort
*)&ep
->adapter_info
[0], serialstr
)
3153 asc_prt_line(cp
, leftlen
, " Serial Number: %s\n",
3157 if (ep
->adapter_info
[5] == 0xBB) {
3158 len
= asc_prt_line(cp
, leftlen
,
3159 " Default Settings Used for EEPROM-less Adapter.\n");
3162 len
= asc_prt_line(cp
, leftlen
,
3163 " Serial Number Signature Not Present.\n");
3168 len
= asc_prt_line(cp
, leftlen
,
3169 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3170 ASC_EEP_GET_CHIP_ID(ep
), ep
->max_total_qng
,
3174 len
= asc_prt_line(cp
, leftlen
,
3175 " cntl 0x%x, no_scam 0x%x\n", ep
->cntl
, ep
->no_scam
);
3178 len
= asc_prt_line(cp
, leftlen
, " Target ID: ");
3180 for (i
= 0; i
<= ASC_MAX_TID
; i
++) {
3181 len
= asc_prt_line(cp
, leftlen
, " %d", i
);
3184 len
= asc_prt_line(cp
, leftlen
, "\n");
3187 len
= asc_prt_line(cp
, leftlen
, " Disconnects: ");
3189 for (i
= 0; i
<= ASC_MAX_TID
; i
++) {
3190 len
= asc_prt_line(cp
, leftlen
, " %c",
3192 disc_enable
& ADV_TID_TO_TIDMASK(i
)) ? 'Y' :
3196 len
= asc_prt_line(cp
, leftlen
, "\n");
3199 len
= asc_prt_line(cp
, leftlen
, " Command Queuing: ");
3201 for (i
= 0; i
<= ASC_MAX_TID
; i
++) {
3202 len
= asc_prt_line(cp
, leftlen
, " %c",
3204 use_cmd_qng
& ADV_TID_TO_TIDMASK(i
)) ? 'Y' :
3208 len
= asc_prt_line(cp
, leftlen
, "\n");
3211 len
= asc_prt_line(cp
, leftlen
, " Start Motor: ");
3213 for (i
= 0; i
<= ASC_MAX_TID
; i
++) {
3214 len
= asc_prt_line(cp
, leftlen
, " %c",
3216 start_motor
& ADV_TID_TO_TIDMASK(i
)) ? 'Y' :
3220 len
= asc_prt_line(cp
, leftlen
, "\n");
3223 len
= asc_prt_line(cp
, leftlen
, " Synchronous Transfer:");
3225 for (i
= 0; i
<= ASC_MAX_TID
; i
++) {
3226 len
= asc_prt_line(cp
, leftlen
, " %c",
3228 init_sdtr
& ADV_TID_TO_TIDMASK(i
)) ? 'Y' :
3232 len
= asc_prt_line(cp
, leftlen
, "\n");
3236 if (asc_dvc_varp
->bus_type
& ASC_IS_ISA
) {
3237 len
= asc_prt_line(cp
, leftlen
,
3238 " Host ISA DMA speed: %d MB/S\n",
3239 isa_dma_speed
[ASC_EEP_GET_DMA_SPD(ep
)]);
3242 #endif /* CONFIG_ISA */
3248 * asc_prt_adv_board_eeprom()
3250 * Print board EEPROM configuration.
3252 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3253 * cf. asc_prt_line().
3255 * Return the number of characters copied into 'cp'. No more than
3256 * 'cplen' characters will be copied to 'cp'.
3258 static int asc_prt_adv_board_eeprom(struct Scsi_Host
*shost
, char *cp
, int cplen
)
3260 struct asc_board
*boardp
= shost_priv(shost
);
3261 ADV_DVC_VAR
*adv_dvc_varp
;
3267 uchar serialstr
[13];
3268 ADVEEP_3550_CONFIG
*ep_3550
= NULL
;
3269 ADVEEP_38C0800_CONFIG
*ep_38C0800
= NULL
;
3270 ADVEEP_38C1600_CONFIG
*ep_38C1600
= NULL
;
3273 ushort sdtr_speed
= 0;
3275 adv_dvc_varp
= &boardp
->dvc_var
.adv_dvc_var
;
3276 if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC3550
) {
3277 ep_3550
= &boardp
->eep_config
.adv_3550_eep
;
3278 } else if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC38C0800
) {
3279 ep_38C0800
= &boardp
->eep_config
.adv_38C0800_eep
;
3281 ep_38C1600
= &boardp
->eep_config
.adv_38C1600_eep
;
3287 len
= asc_prt_line(cp
, leftlen
,
3288 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3292 if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC3550
) {
3293 wordp
= &ep_3550
->serial_number_word1
;
3294 } else if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC38C0800
) {
3295 wordp
= &ep_38C0800
->serial_number_word1
;
3297 wordp
= &ep_38C1600
->serial_number_word1
;
3300 if (asc_get_eeprom_string(wordp
, serialstr
) == ASC_TRUE
) {
3302 asc_prt_line(cp
, leftlen
, " Serial Number: %s\n",
3306 len
= asc_prt_line(cp
, leftlen
,
3307 " Serial Number Signature Not Present.\n");
3311 if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC3550
) {
3312 len
= asc_prt_line(cp
, leftlen
,
3313 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3314 ep_3550
->adapter_scsi_id
,
3315 ep_3550
->max_host_qng
, ep_3550
->max_dvc_qng
);
3317 } else if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC38C0800
) {
3318 len
= asc_prt_line(cp
, leftlen
,
3319 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3320 ep_38C0800
->adapter_scsi_id
,
3321 ep_38C0800
->max_host_qng
,
3322 ep_38C0800
->max_dvc_qng
);
3325 len
= asc_prt_line(cp
, leftlen
,
3326 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3327 ep_38C1600
->adapter_scsi_id
,
3328 ep_38C1600
->max_host_qng
,
3329 ep_38C1600
->max_dvc_qng
);
3332 if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC3550
) {
3333 word
= ep_3550
->termination
;
3334 } else if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC38C0800
) {
3335 word
= ep_38C0800
->termination_lvd
;
3337 word
= ep_38C1600
->termination_lvd
;
3341 termstr
= "Low Off/High Off";
3344 termstr
= "Low Off/High On";
3347 termstr
= "Low On/High On";
3351 termstr
= "Automatic";
3355 if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC3550
) {
3356 len
= asc_prt_line(cp
, leftlen
,
3357 " termination: %u (%s), bios_ctrl: 0x%x\n",
3358 ep_3550
->termination
, termstr
,
3359 ep_3550
->bios_ctrl
);
3361 } else if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC38C0800
) {
3362 len
= asc_prt_line(cp
, leftlen
,
3363 " termination: %u (%s), bios_ctrl: 0x%x\n",
3364 ep_38C0800
->termination_lvd
, termstr
,
3365 ep_38C0800
->bios_ctrl
);
3368 len
= asc_prt_line(cp
, leftlen
,
3369 " termination: %u (%s), bios_ctrl: 0x%x\n",
3370 ep_38C1600
->termination_lvd
, termstr
,
3371 ep_38C1600
->bios_ctrl
);
3375 len
= asc_prt_line(cp
, leftlen
, " Target ID: ");
3377 for (i
= 0; i
<= ADV_MAX_TID
; i
++) {
3378 len
= asc_prt_line(cp
, leftlen
, " %X", i
);
3381 len
= asc_prt_line(cp
, leftlen
, "\n");
3384 if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC3550
) {
3385 word
= ep_3550
->disc_enable
;
3386 } else if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC38C0800
) {
3387 word
= ep_38C0800
->disc_enable
;
3389 word
= ep_38C1600
->disc_enable
;
3391 len
= asc_prt_line(cp
, leftlen
, " Disconnects: ");
3393 for (i
= 0; i
<= ADV_MAX_TID
; i
++) {
3394 len
= asc_prt_line(cp
, leftlen
, " %c",
3395 (word
& ADV_TID_TO_TIDMASK(i
)) ? 'Y' : 'N');
3398 len
= asc_prt_line(cp
, leftlen
, "\n");
3401 if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC3550
) {
3402 word
= ep_3550
->tagqng_able
;
3403 } else if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC38C0800
) {
3404 word
= ep_38C0800
->tagqng_able
;
3406 word
= ep_38C1600
->tagqng_able
;
3408 len
= asc_prt_line(cp
, leftlen
, " Command Queuing: ");
3410 for (i
= 0; i
<= ADV_MAX_TID
; i
++) {
3411 len
= asc_prt_line(cp
, leftlen
, " %c",
3412 (word
& ADV_TID_TO_TIDMASK(i
)) ? 'Y' : 'N');
3415 len
= asc_prt_line(cp
, leftlen
, "\n");
3418 if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC3550
) {
3419 word
= ep_3550
->start_motor
;
3420 } else if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC38C0800
) {
3421 word
= ep_38C0800
->start_motor
;
3423 word
= ep_38C1600
->start_motor
;
3425 len
= asc_prt_line(cp
, leftlen
, " Start Motor: ");
3427 for (i
= 0; i
<= ADV_MAX_TID
; i
++) {
3428 len
= asc_prt_line(cp
, leftlen
, " %c",
3429 (word
& ADV_TID_TO_TIDMASK(i
)) ? 'Y' : 'N');
3432 len
= asc_prt_line(cp
, leftlen
, "\n");
3435 if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC3550
) {
3436 len
= asc_prt_line(cp
, leftlen
, " Synchronous Transfer:");
3438 for (i
= 0; i
<= ADV_MAX_TID
; i
++) {
3439 len
= asc_prt_line(cp
, leftlen
, " %c",
3441 sdtr_able
& ADV_TID_TO_TIDMASK(i
)) ?
3445 len
= asc_prt_line(cp
, leftlen
, "\n");
3449 if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC3550
) {
3450 len
= asc_prt_line(cp
, leftlen
, " Ultra Transfer: ");
3452 for (i
= 0; i
<= ADV_MAX_TID
; i
++) {
3453 len
= asc_prt_line(cp
, leftlen
, " %c",
3455 ultra_able
& ADV_TID_TO_TIDMASK(i
))
3459 len
= asc_prt_line(cp
, leftlen
, "\n");
3463 if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC3550
) {
3464 word
= ep_3550
->wdtr_able
;
3465 } else if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC38C0800
) {
3466 word
= ep_38C0800
->wdtr_able
;
3468 word
= ep_38C1600
->wdtr_able
;
3470 len
= asc_prt_line(cp
, leftlen
, " Wide Transfer: ");
3472 for (i
= 0; i
<= ADV_MAX_TID
; i
++) {
3473 len
= asc_prt_line(cp
, leftlen
, " %c",
3474 (word
& ADV_TID_TO_TIDMASK(i
)) ? 'Y' : 'N');
3477 len
= asc_prt_line(cp
, leftlen
, "\n");
3480 if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC38C0800
||
3481 adv_dvc_varp
->chip_type
== ADV_CHIP_ASC38C1600
) {
3482 len
= asc_prt_line(cp
, leftlen
,
3483 " Synchronous Transfer Speed (Mhz):\n ");
3485 for (i
= 0; i
<= ADV_MAX_TID
; i
++) {
3489 sdtr_speed
= adv_dvc_varp
->sdtr_speed1
;
3490 } else if (i
== 4) {
3491 sdtr_speed
= adv_dvc_varp
->sdtr_speed2
;
3492 } else if (i
== 8) {
3493 sdtr_speed
= adv_dvc_varp
->sdtr_speed3
;
3494 } else if (i
== 12) {
3495 sdtr_speed
= adv_dvc_varp
->sdtr_speed4
;
3497 switch (sdtr_speed
& ADV_MAX_TID
) {
3520 len
= asc_prt_line(cp
, leftlen
, "%X:%s ", i
, speed_str
);
3523 len
= asc_prt_line(cp
, leftlen
, "\n ");
3528 len
= asc_prt_line(cp
, leftlen
, "\n");
3536 * asc_prt_driver_conf()
3538 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3539 * cf. asc_prt_line().
3541 * Return the number of characters copied into 'cp'. No more than
3542 * 'cplen' characters will be copied to 'cp'.
3544 static int asc_prt_driver_conf(struct Scsi_Host
*shost
, char *cp
, int cplen
)
3546 struct asc_board
*boardp
= shost_priv(shost
);
3555 len
= asc_prt_line(cp
, leftlen
,
3556 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3560 len
= asc_prt_line(cp
, leftlen
,
3561 " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
3562 shost
->host_busy
, shost
->last_reset
, shost
->max_id
,
3563 shost
->max_lun
, shost
->max_channel
);
3566 len
= asc_prt_line(cp
, leftlen
,
3567 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3568 shost
->unique_id
, shost
->can_queue
, shost
->this_id
,
3569 shost
->sg_tablesize
, shost
->cmd_per_lun
);
3572 len
= asc_prt_line(cp
, leftlen
,
3573 " unchecked_isa_dma %d, use_clustering %d\n",
3574 shost
->unchecked_isa_dma
, shost
->use_clustering
);
3577 len
= asc_prt_line(cp
, leftlen
,
3578 " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
3579 boardp
->flags
, boardp
->last_reset
, jiffies
,
3580 boardp
->asc_n_io_port
);
3583 len
= asc_prt_line(cp
, leftlen
, " io_port 0x%x\n", shost
->io_port
);
3586 if (ASC_NARROW_BOARD(boardp
)) {
3587 chip_scsi_id
= boardp
->dvc_cfg
.asc_dvc_cfg
.chip_scsi_id
;
3589 chip_scsi_id
= boardp
->dvc_var
.adv_dvc_var
.chip_scsi_id
;
3596 * asc_prt_asc_board_info()
3598 * Print dynamic board configuration information.
3600 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3601 * cf. asc_prt_line().
3603 * Return the number of characters copied into 'cp'. No more than
3604 * 'cplen' characters will be copied to 'cp'.
3606 static int asc_prt_asc_board_info(struct Scsi_Host
*shost
, char *cp
, int cplen
)
3608 struct asc_board
*boardp
= shost_priv(shost
);
3616 int renegotiate
= 0;
3618 v
= &boardp
->dvc_var
.asc_dvc_var
;
3619 c
= &boardp
->dvc_cfg
.asc_dvc_cfg
;
3620 chip_scsi_id
= c
->chip_scsi_id
;
3625 len
= asc_prt_line(cp
, leftlen
,
3626 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3630 len
= asc_prt_line(cp
, leftlen
, " chip_version %u, mcode_date 0x%x, "
3631 "mcode_version 0x%x, err_code %u\n",
3632 c
->chip_version
, c
->mcode_date
, c
->mcode_version
,
3636 /* Current number of commands waiting for the host. */
3637 len
= asc_prt_line(cp
, leftlen
,
3638 " Total Command Pending: %d\n", v
->cur_total_qng
);
3641 len
= asc_prt_line(cp
, leftlen
, " Command Queuing:");
3643 for (i
= 0; i
<= ASC_MAX_TID
; i
++) {
3644 if ((chip_scsi_id
== i
) ||
3645 ((boardp
->init_tidmask
& ADV_TID_TO_TIDMASK(i
)) == 0)) {
3648 len
= asc_prt_line(cp
, leftlen
, " %X:%c",
3651 use_tagged_qng
& ADV_TID_TO_TIDMASK(i
)) ?
3655 len
= asc_prt_line(cp
, leftlen
, "\n");
3658 /* Current number of commands waiting for a device. */
3659 len
= asc_prt_line(cp
, leftlen
, " Command Queue Pending:");
3661 for (i
= 0; i
<= ASC_MAX_TID
; i
++) {
3662 if ((chip_scsi_id
== i
) ||
3663 ((boardp
->init_tidmask
& ADV_TID_TO_TIDMASK(i
)) == 0)) {
3666 len
= asc_prt_line(cp
, leftlen
, " %X:%u", i
, v
->cur_dvc_qng
[i
]);
3669 len
= asc_prt_line(cp
, leftlen
, "\n");
3672 /* Current limit on number of commands that can be sent to a device. */
3673 len
= asc_prt_line(cp
, leftlen
, " Command Queue Limit:");
3675 for (i
= 0; i
<= ASC_MAX_TID
; i
++) {
3676 if ((chip_scsi_id
== i
) ||
3677 ((boardp
->init_tidmask
& ADV_TID_TO_TIDMASK(i
)) == 0)) {
3680 len
= asc_prt_line(cp
, leftlen
, " %X:%u", i
, v
->max_dvc_qng
[i
]);
3683 len
= asc_prt_line(cp
, leftlen
, "\n");
3686 /* Indicate whether the device has returned queue full status. */
3687 len
= asc_prt_line(cp
, leftlen
, " Command Queue Full:");
3689 for (i
= 0; i
<= ASC_MAX_TID
; i
++) {
3690 if ((chip_scsi_id
== i
) ||
3691 ((boardp
->init_tidmask
& ADV_TID_TO_TIDMASK(i
)) == 0)) {
3694 if (boardp
->queue_full
& ADV_TID_TO_TIDMASK(i
)) {
3695 len
= asc_prt_line(cp
, leftlen
, " %X:Y-%d",
3696 i
, boardp
->queue_full_cnt
[i
]);
3698 len
= asc_prt_line(cp
, leftlen
, " %X:N", i
);
3702 len
= asc_prt_line(cp
, leftlen
, "\n");
3705 len
= asc_prt_line(cp
, leftlen
, " Synchronous Transfer:");
3707 for (i
= 0; i
<= ASC_MAX_TID
; i
++) {
3708 if ((chip_scsi_id
== i
) ||
3709 ((boardp
->init_tidmask
& ADV_TID_TO_TIDMASK(i
)) == 0)) {
3712 len
= asc_prt_line(cp
, leftlen
, " %X:%c",
3715 sdtr_done
& ADV_TID_TO_TIDMASK(i
)) ? 'Y' :
3719 len
= asc_prt_line(cp
, leftlen
, "\n");
3722 for (i
= 0; i
<= ASC_MAX_TID
; i
++) {
3723 uchar syn_period_ix
;
3725 if ((chip_scsi_id
== i
) ||
3726 ((boardp
->init_tidmask
& ADV_TID_TO_TIDMASK(i
)) == 0) ||
3727 ((v
->init_sdtr
& ADV_TID_TO_TIDMASK(i
)) == 0)) {
3731 len
= asc_prt_line(cp
, leftlen
, " %X:", i
);
3734 if ((boardp
->sdtr_data
[i
] & ASC_SYN_MAX_OFFSET
) == 0) {
3735 len
= asc_prt_line(cp
, leftlen
, " Asynchronous");
3739 (boardp
->sdtr_data
[i
] >> 4) & (v
->max_sdtr_index
-
3742 len
= asc_prt_line(cp
, leftlen
,
3743 " Transfer Period Factor: %d (%d.%d Mhz),",
3744 v
->sdtr_period_tbl
[syn_period_ix
],
3746 v
->sdtr_period_tbl
[syn_period_ix
],
3753 len
= asc_prt_line(cp
, leftlen
, " REQ/ACK Offset: %d",
3755 sdtr_data
[i
] & ASC_SYN_MAX_OFFSET
);
3759 if ((v
->sdtr_done
& ADV_TID_TO_TIDMASK(i
)) == 0) {
3760 len
= asc_prt_line(cp
, leftlen
, "*\n");
3763 len
= asc_prt_line(cp
, leftlen
, "\n");
3769 len
= asc_prt_line(cp
, leftlen
,
3770 " * = Re-negotiation pending before next command.\n");
3778 * asc_prt_adv_board_info()
3780 * Print dynamic board configuration information.
3782 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3783 * cf. asc_prt_line().
3785 * Return the number of characters copied into 'cp'. No more than
3786 * 'cplen' characters will be copied to 'cp'.
3788 static int asc_prt_adv_board_info(struct Scsi_Host
*shost
, char *cp
, int cplen
)
3790 struct asc_board
*boardp
= shost_priv(shost
);
3797 AdvPortAddr iop_base
;
3798 ushort chip_scsi_id
;
3802 ushort sdtr_able
, wdtr_able
;
3803 ushort wdtr_done
, sdtr_done
;
3805 int renegotiate
= 0;
3807 v
= &boardp
->dvc_var
.adv_dvc_var
;
3808 c
= &boardp
->dvc_cfg
.adv_dvc_cfg
;
3809 iop_base
= v
->iop_base
;
3810 chip_scsi_id
= v
->chip_scsi_id
;
3815 len
= asc_prt_line(cp
, leftlen
,
3816 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3820 len
= asc_prt_line(cp
, leftlen
,
3821 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3823 AdvReadWordRegister(iop_base
,
3824 IOPW_SCSI_CFG1
) & CABLE_DETECT
,
3828 len
= asc_prt_line(cp
, leftlen
, " chip_version %u, mcode_date 0x%x, "
3829 "mcode_version 0x%x\n", c
->chip_version
,
3830 c
->mcode_date
, c
->mcode_version
);
3833 AdvReadWordLram(iop_base
, ASC_MC_TAGQNG_ABLE
, tagqng_able
);
3834 len
= asc_prt_line(cp
, leftlen
, " Queuing Enabled:");
3836 for (i
= 0; i
<= ADV_MAX_TID
; i
++) {
3837 if ((chip_scsi_id
== i
) ||
3838 ((boardp
->init_tidmask
& ADV_TID_TO_TIDMASK(i
)) == 0)) {
3842 len
= asc_prt_line(cp
, leftlen
, " %X:%c",
3844 (tagqng_able
& ADV_TID_TO_TIDMASK(i
)) ? 'Y' :
3848 len
= asc_prt_line(cp
, leftlen
, "\n");
3851 len
= asc_prt_line(cp
, leftlen
, " Queue Limit:");
3853 for (i
= 0; i
<= ADV_MAX_TID
; i
++) {
3854 if ((chip_scsi_id
== i
) ||
3855 ((boardp
->init_tidmask
& ADV_TID_TO_TIDMASK(i
)) == 0)) {
3859 AdvReadByteLram(iop_base
, ASC_MC_NUMBER_OF_MAX_CMD
+ i
,
3862 len
= asc_prt_line(cp
, leftlen
, " %X:%d", i
, lrambyte
);
3865 len
= asc_prt_line(cp
, leftlen
, "\n");
3868 len
= asc_prt_line(cp
, leftlen
, " Command Pending:");
3870 for (i
= 0; i
<= ADV_MAX_TID
; i
++) {
3871 if ((chip_scsi_id
== i
) ||
3872 ((boardp
->init_tidmask
& ADV_TID_TO_TIDMASK(i
)) == 0)) {
3876 AdvReadByteLram(iop_base
, ASC_MC_NUMBER_OF_QUEUED_CMD
+ i
,
3879 len
= asc_prt_line(cp
, leftlen
, " %X:%d", i
, lrambyte
);
3882 len
= asc_prt_line(cp
, leftlen
, "\n");
3885 AdvReadWordLram(iop_base
, ASC_MC_WDTR_ABLE
, wdtr_able
);
3886 len
= asc_prt_line(cp
, leftlen
, " Wide Enabled:");
3888 for (i
= 0; i
<= ADV_MAX_TID
; i
++) {
3889 if ((chip_scsi_id
== i
) ||
3890 ((boardp
->init_tidmask
& ADV_TID_TO_TIDMASK(i
)) == 0)) {
3894 len
= asc_prt_line(cp
, leftlen
, " %X:%c",
3896 (wdtr_able
& ADV_TID_TO_TIDMASK(i
)) ? 'Y' :
3900 len
= asc_prt_line(cp
, leftlen
, "\n");
3903 AdvReadWordLram(iop_base
, ASC_MC_WDTR_DONE
, wdtr_done
);
3904 len
= asc_prt_line(cp
, leftlen
, " Transfer Bit Width:");
3906 for (i
= 0; i
<= ADV_MAX_TID
; i
++) {
3907 if ((chip_scsi_id
== i
) ||
3908 ((boardp
->init_tidmask
& ADV_TID_TO_TIDMASK(i
)) == 0)) {
3912 AdvReadWordLram(iop_base
,
3913 ASC_MC_DEVICE_HSHK_CFG_TABLE
+ (2 * i
),
3916 len
= asc_prt_line(cp
, leftlen
, " %X:%d",
3917 i
, (lramword
& 0x8000) ? 16 : 8);
3920 if ((wdtr_able
& ADV_TID_TO_TIDMASK(i
)) &&
3921 (wdtr_done
& ADV_TID_TO_TIDMASK(i
)) == 0) {
3922 len
= asc_prt_line(cp
, leftlen
, "*");
3927 len
= asc_prt_line(cp
, leftlen
, "\n");
3930 AdvReadWordLram(iop_base
, ASC_MC_SDTR_ABLE
, sdtr_able
);
3931 len
= asc_prt_line(cp
, leftlen
, " Synchronous Enabled:");
3933 for (i
= 0; i
<= ADV_MAX_TID
; i
++) {
3934 if ((chip_scsi_id
== i
) ||
3935 ((boardp
->init_tidmask
& ADV_TID_TO_TIDMASK(i
)) == 0)) {
3939 len
= asc_prt_line(cp
, leftlen
, " %X:%c",
3941 (sdtr_able
& ADV_TID_TO_TIDMASK(i
)) ? 'Y' :
3945 len
= asc_prt_line(cp
, leftlen
, "\n");
3948 AdvReadWordLram(iop_base
, ASC_MC_SDTR_DONE
, sdtr_done
);
3949 for (i
= 0; i
<= ADV_MAX_TID
; i
++) {
3951 AdvReadWordLram(iop_base
,
3952 ASC_MC_DEVICE_HSHK_CFG_TABLE
+ (2 * i
),
3954 lramword
&= ~0x8000;
3956 if ((chip_scsi_id
== i
) ||
3957 ((boardp
->init_tidmask
& ADV_TID_TO_TIDMASK(i
)) == 0) ||
3958 ((sdtr_able
& ADV_TID_TO_TIDMASK(i
)) == 0)) {
3962 len
= asc_prt_line(cp
, leftlen
, " %X:", i
);
3965 if ((lramword
& 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
3966 len
= asc_prt_line(cp
, leftlen
, " Asynchronous");
3970 asc_prt_line(cp
, leftlen
,
3971 " Transfer Period Factor: ");
3974 if ((lramword
& 0x1F00) == 0x1100) { /* 80 Mhz */
3976 asc_prt_line(cp
, leftlen
, "9 (80.0 Mhz),");
3978 } else if ((lramword
& 0x1F00) == 0x1000) { /* 40 Mhz */
3980 asc_prt_line(cp
, leftlen
, "10 (40.0 Mhz),");
3982 } else { /* 20 Mhz or below. */
3984 period
= (((lramword
>> 8) * 25) + 50) / 4;
3986 if (period
== 0) { /* Should never happen. */
3988 asc_prt_line(cp
, leftlen
,
3992 len
= asc_prt_line(cp
, leftlen
,
3994 period
, 250 / period
,
4001 len
= asc_prt_line(cp
, leftlen
, " REQ/ACK Offset: %d",
4006 if ((sdtr_done
& ADV_TID_TO_TIDMASK(i
)) == 0) {
4007 len
= asc_prt_line(cp
, leftlen
, "*\n");
4010 len
= asc_prt_line(cp
, leftlen
, "\n");
4016 len
= asc_prt_line(cp
, leftlen
,
4017 " * = Re-negotiation pending before next command.\n");
4027 * Copy proc information to a read buffer taking into account the current
4028 * read offset in the file and the remaining space in the read buffer.
4031 asc_proc_copy(off_t advoffset
, off_t offset
, char *curbuf
, int leftlen
,
4032 char *cp
, int cplen
)
4036 ASC_DBG(2, "offset %d, advoffset %d, cplen %d\n",
4037 (unsigned)offset
, (unsigned)advoffset
, cplen
);
4038 if (offset
<= advoffset
) {
4039 /* Read offset below current offset, copy everything. */
4040 cnt
= min(cplen
, leftlen
);
4041 ASC_DBG(2, "curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4042 (ulong
)curbuf
, (ulong
)cp
, cnt
);
4043 memcpy(curbuf
, cp
, cnt
);
4044 } else if (offset
< advoffset
+ cplen
) {
4045 /* Read offset within current range, partial copy. */
4046 cnt
= (advoffset
+ cplen
) - offset
;
4047 cp
= (cp
+ cplen
) - cnt
;
4048 cnt
= min(cnt
, leftlen
);
4049 ASC_DBG(2, "curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4050 (ulong
)curbuf
, (ulong
)cp
, cnt
);
4051 memcpy(curbuf
, cp
, cnt
);
4056 #ifdef ADVANSYS_STATS
4058 * asc_prt_board_stats()
4060 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
4061 * cf. asc_prt_line().
4063 * Return the number of characters copied into 'cp'. No more than
4064 * 'cplen' characters will be copied to 'cp'.
4066 static int asc_prt_board_stats(struct Scsi_Host
*shost
, char *cp
, int cplen
)
4068 struct asc_board
*boardp
= shost_priv(shost
);
4069 struct asc_stats
*s
= &boardp
->asc_stats
;
4071 int leftlen
= cplen
;
4072 int len
, totlen
= 0;
4074 len
= asc_prt_line(cp
, leftlen
,
4075 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
4079 len
= asc_prt_line(cp
, leftlen
,
4080 " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
4081 s
->queuecommand
, s
->reset
, s
->biosparam
,
4085 len
= asc_prt_line(cp
, leftlen
,
4086 " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
4087 s
->callback
, s
->done
, s
->build_error
,
4088 s
->adv_build_noreq
, s
->adv_build_nosg
);
4091 len
= asc_prt_line(cp
, leftlen
,
4092 " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
4093 s
->exe_noerror
, s
->exe_busy
, s
->exe_error
,
4098 * Display data transfer statistics.
4100 if (s
->xfer_cnt
> 0) {
4101 len
= asc_prt_line(cp
, leftlen
, " xfer_cnt %lu, xfer_elem %lu, ",
4102 s
->xfer_cnt
, s
->xfer_elem
);
4105 len
= asc_prt_line(cp
, leftlen
, "xfer_bytes %lu.%01lu kb\n",
4106 s
->xfer_sect
/ 2, ASC_TENTHS(s
->xfer_sect
, 2));
4109 /* Scatter gather transfer statistics */
4110 len
= asc_prt_line(cp
, leftlen
, " avg_num_elem %lu.%01lu, ",
4111 s
->xfer_elem
/ s
->xfer_cnt
,
4112 ASC_TENTHS(s
->xfer_elem
, s
->xfer_cnt
));
4115 len
= asc_prt_line(cp
, leftlen
, "avg_elem_size %lu.%01lu kb, ",
4116 (s
->xfer_sect
/ 2) / s
->xfer_elem
,
4117 ASC_TENTHS((s
->xfer_sect
/ 2), s
->xfer_elem
));
4120 len
= asc_prt_line(cp
, leftlen
, "avg_xfer_size %lu.%01lu kb\n",
4121 (s
->xfer_sect
/ 2) / s
->xfer_cnt
,
4122 ASC_TENTHS((s
->xfer_sect
/ 2), s
->xfer_cnt
));
4128 #endif /* ADVANSYS_STATS */
4131 * advansys_proc_info() - /proc/scsi/advansys/{0,1,2,3,...}
4133 * *buffer: I/O buffer
4134 * **start: if inout == FALSE pointer into buffer where user read should start
4135 * offset: current offset into a /proc/scsi/advansys/[0...] file
4136 * length: length of buffer
4137 * hostno: Scsi_Host host_no
4138 * inout: TRUE - user is writing; FALSE - user is reading
4140 * Return the number of bytes read from or written to a
4141 * /proc/scsi/advansys/[0...] file.
4143 * Note: This function uses the per board buffer 'prtbuf' which is
4144 * allocated when the board is initialized in advansys_detect(). The
4145 * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
4146 * used to write to the buffer. The way asc_proc_copy() is written
4147 * if 'prtbuf' is too small it will not be overwritten. Instead the
4148 * user just won't get all the available statistics.
4151 advansys_proc_info(struct Scsi_Host
*shost
, char *buffer
, char **start
,
4152 off_t offset
, int length
, int inout
)
4154 struct asc_board
*boardp
= shost_priv(shost
);
4163 ASC_DBG(1, "begin\n");
4166 * User write not supported.
4172 * User read of /proc/scsi/advansys/[0...] file.
4175 /* Copy read data starting at the beginning of the buffer. */
4183 * Get board configuration information.
4185 * advansys_info() returns the board string from its own static buffer.
4187 cp
= (char *)advansys_info(shost
);
4190 /* Copy board information. */
4191 cnt
= asc_proc_copy(advoffset
, offset
, curbuf
, leftlen
, cp
, cplen
);
4195 ASC_DBG(1, "totcnt %d\n", totcnt
);
4202 * Display Wide Board BIOS Information.
4204 if (!ASC_NARROW_BOARD(boardp
)) {
4205 cp
= boardp
->prtbuf
;
4206 cplen
= asc_prt_adv_bios(shost
, cp
, ASC_PRTBUF_SIZE
);
4207 BUG_ON(cplen
>= ASC_PRTBUF_SIZE
);
4208 cnt
= asc_proc_copy(advoffset
, offset
, curbuf
, leftlen
, cp
,
4213 ASC_DBG(1, "totcnt %d\n", totcnt
);
4221 * Display driver information for each device attached to the board.
4223 cp
= boardp
->prtbuf
;
4224 cplen
= asc_prt_board_devices(shost
, cp
, ASC_PRTBUF_SIZE
);
4225 BUG_ON(cplen
>= ASC_PRTBUF_SIZE
);
4226 cnt
= asc_proc_copy(advoffset
, offset
, curbuf
, leftlen
, cp
, cplen
);
4230 ASC_DBG(1, "totcnt %d\n", totcnt
);
4237 * Display EEPROM configuration for the board.
4239 cp
= boardp
->prtbuf
;
4240 if (ASC_NARROW_BOARD(boardp
)) {
4241 cplen
= asc_prt_asc_board_eeprom(shost
, cp
, ASC_PRTBUF_SIZE
);
4243 cplen
= asc_prt_adv_board_eeprom(shost
, cp
, ASC_PRTBUF_SIZE
);
4245 BUG_ON(cplen
>= ASC_PRTBUF_SIZE
);
4246 cnt
= asc_proc_copy(advoffset
, offset
, curbuf
, leftlen
, cp
, cplen
);
4250 ASC_DBG(1, "totcnt %d\n", totcnt
);
4257 * Display driver configuration and information for the board.
4259 cp
= boardp
->prtbuf
;
4260 cplen
= asc_prt_driver_conf(shost
, cp
, ASC_PRTBUF_SIZE
);
4261 BUG_ON(cplen
>= ASC_PRTBUF_SIZE
);
4262 cnt
= asc_proc_copy(advoffset
, offset
, curbuf
, leftlen
, cp
, cplen
);
4266 ASC_DBG(1, "totcnt %d\n", totcnt
);
4272 #ifdef ADVANSYS_STATS
4274 * Display driver statistics for the board.
4276 cp
= boardp
->prtbuf
;
4277 cplen
= asc_prt_board_stats(shost
, cp
, ASC_PRTBUF_SIZE
);
4278 BUG_ON(cplen
>= ASC_PRTBUF_SIZE
);
4279 cnt
= asc_proc_copy(advoffset
, offset
, curbuf
, leftlen
, cp
, cplen
);
4283 ASC_DBG(1, "totcnt %d\n", totcnt
);
4288 #endif /* ADVANSYS_STATS */
4291 * Display Asc Library dynamic configuration information
4294 cp
= boardp
->prtbuf
;
4295 if (ASC_NARROW_BOARD(boardp
)) {
4296 cplen
= asc_prt_asc_board_info(shost
, cp
, ASC_PRTBUF_SIZE
);
4298 cplen
= asc_prt_adv_board_info(shost
, cp
, ASC_PRTBUF_SIZE
);
4300 BUG_ON(cplen
>= ASC_PRTBUF_SIZE
);
4301 cnt
= asc_proc_copy(advoffset
, offset
, curbuf
, leftlen
, cp
, cplen
);
4305 ASC_DBG(1, "totcnt %d\n", totcnt
);
4311 ASC_DBG(1, "totcnt %d\n", totcnt
);
4315 #endif /* CONFIG_PROC_FS */
4317 static void asc_scsi_done(struct scsi_cmnd
*scp
)
4319 scsi_dma_unmap(scp
);
4320 ASC_STATS(scp
->device
->host
, done
);
4321 scp
->scsi_done(scp
);
4324 static void AscSetBank(PortAddr iop_base
, uchar bank
)
4328 val
= AscGetChipControl(iop_base
) &
4330 (CC_SINGLE_STEP
| CC_TEST
| CC_DIAG
| CC_SCSI_RESET
|
4334 } else if (bank
== 2) {
4335 val
|= CC_DIAG
| CC_BANK_ONE
;
4337 val
&= ~CC_BANK_ONE
;
4339 AscSetChipControl(iop_base
, val
);
4342 static void AscSetChipIH(PortAddr iop_base
, ushort ins_code
)
4344 AscSetBank(iop_base
, 1);
4345 AscWriteChipIH(iop_base
, ins_code
);
4346 AscSetBank(iop_base
, 0);
4349 static int AscStartChip(PortAddr iop_base
)
4351 AscSetChipControl(iop_base
, 0);
4352 if ((AscGetChipStatus(iop_base
) & CSW_HALTED
) != 0) {
4358 static int AscStopChip(PortAddr iop_base
)
4363 AscGetChipControl(iop_base
) &
4364 (~(CC_SINGLE_STEP
| CC_TEST
| CC_DIAG
));
4365 AscSetChipControl(iop_base
, (uchar
)(cc_val
| CC_HALT
));
4366 AscSetChipIH(iop_base
, INS_HALT
);
4367 AscSetChipIH(iop_base
, INS_RFLAG_WTM
);
4368 if ((AscGetChipStatus(iop_base
) & CSW_HALTED
) == 0) {
4374 static int AscIsChipHalted(PortAddr iop_base
)
4376 if ((AscGetChipStatus(iop_base
) & CSW_HALTED
) != 0) {
4377 if ((AscGetChipControl(iop_base
) & CC_HALT
) != 0) {
4384 static int AscResetChipAndScsiBus(ASC_DVC_VAR
*asc_dvc
)
4389 iop_base
= asc_dvc
->iop_base
;
4390 while ((AscGetChipStatus(iop_base
) & CSW_SCSI_RESET_ACTIVE
)
4394 AscStopChip(iop_base
);
4395 AscSetChipControl(iop_base
, CC_CHIP_RESET
| CC_SCSI_RESET
| CC_HALT
);
4397 AscSetChipIH(iop_base
, INS_RFLAG_WTM
);
4398 AscSetChipIH(iop_base
, INS_HALT
);
4399 AscSetChipControl(iop_base
, CC_CHIP_RESET
| CC_HALT
);
4400 AscSetChipControl(iop_base
, CC_HALT
);
4402 AscSetChipStatus(iop_base
, CIW_CLR_SCSI_RESET_INT
);
4403 AscSetChipStatus(iop_base
, 0);
4404 return (AscIsChipHalted(iop_base
));
4407 static int AscFindSignature(PortAddr iop_base
)
4411 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
4412 iop_base
, AscGetChipSignatureByte(iop_base
));
4413 if (AscGetChipSignatureByte(iop_base
) == (uchar
)ASC_1000_ID1B
) {
4414 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
4415 iop_base
, AscGetChipSignatureWord(iop_base
));
4416 sig_word
= AscGetChipSignatureWord(iop_base
);
4417 if ((sig_word
== (ushort
)ASC_1000_ID0W
) ||
4418 (sig_word
== (ushort
)ASC_1000_ID0W_FIX
)) {
4425 static void AscEnableInterrupt(PortAddr iop_base
)
4429 cfg
= AscGetChipCfgLsw(iop_base
);
4430 AscSetChipCfgLsw(iop_base
, cfg
| ASC_CFG0_HOST_INT_ON
);
4433 static void AscDisableInterrupt(PortAddr iop_base
)
4437 cfg
= AscGetChipCfgLsw(iop_base
);
4438 AscSetChipCfgLsw(iop_base
, cfg
& (~ASC_CFG0_HOST_INT_ON
));
4441 static uchar
AscReadLramByte(PortAddr iop_base
, ushort addr
)
4443 unsigned char byte_data
;
4444 unsigned short word_data
;
4446 if (isodd_word(addr
)) {
4447 AscSetChipLramAddr(iop_base
, addr
- 1);
4448 word_data
= AscGetChipLramData(iop_base
);
4449 byte_data
= (word_data
>> 8) & 0xFF;
4451 AscSetChipLramAddr(iop_base
, addr
);
4452 word_data
= AscGetChipLramData(iop_base
);
4453 byte_data
= word_data
& 0xFF;
4458 static ushort
AscReadLramWord(PortAddr iop_base
, ushort addr
)
4462 AscSetChipLramAddr(iop_base
, addr
);
4463 word_data
= AscGetChipLramData(iop_base
);
4467 #if CC_VERY_LONG_SG_LIST
4468 static ASC_DCNT
AscReadLramDWord(PortAddr iop_base
, ushort addr
)
4470 ushort val_low
, val_high
;
4471 ASC_DCNT dword_data
;
4473 AscSetChipLramAddr(iop_base
, addr
);
4474 val_low
= AscGetChipLramData(iop_base
);
4475 val_high
= AscGetChipLramData(iop_base
);
4476 dword_data
= ((ASC_DCNT
) val_high
<< 16) | (ASC_DCNT
) val_low
;
4477 return (dword_data
);
4479 #endif /* CC_VERY_LONG_SG_LIST */
4482 AscMemWordSetLram(PortAddr iop_base
, ushort s_addr
, ushort set_wval
, int words
)
4486 AscSetChipLramAddr(iop_base
, s_addr
);
4487 for (i
= 0; i
< words
; i
++) {
4488 AscSetChipLramData(iop_base
, set_wval
);
4492 static void AscWriteLramWord(PortAddr iop_base
, ushort addr
, ushort word_val
)
4494 AscSetChipLramAddr(iop_base
, addr
);
4495 AscSetChipLramData(iop_base
, word_val
);
4498 static void AscWriteLramByte(PortAddr iop_base
, ushort addr
, uchar byte_val
)
4502 if (isodd_word(addr
)) {
4504 word_data
= AscReadLramWord(iop_base
, addr
);
4505 word_data
&= 0x00FF;
4506 word_data
|= (((ushort
)byte_val
<< 8) & 0xFF00);
4508 word_data
= AscReadLramWord(iop_base
, addr
);
4509 word_data
&= 0xFF00;
4510 word_data
|= ((ushort
)byte_val
& 0x00FF);
4512 AscWriteLramWord(iop_base
, addr
, word_data
);
4516 * Copy 2 bytes to LRAM.
4518 * The source data is assumed to be in little-endian order in memory
4519 * and is maintained in little-endian order when written to LRAM.
4522 AscMemWordCopyPtrToLram(PortAddr iop_base
,
4523 ushort s_addr
, uchar
*s_buffer
, int words
)
4527 AscSetChipLramAddr(iop_base
, s_addr
);
4528 for (i
= 0; i
< 2 * words
; i
+= 2) {
4530 * On a little-endian system the second argument below
4531 * produces a little-endian ushort which is written to
4532 * LRAM in little-endian order. On a big-endian system
4533 * the second argument produces a big-endian ushort which
4534 * is "transparently" byte-swapped by outpw() and written
4535 * in little-endian order to LRAM.
4537 outpw(iop_base
+ IOP_RAM_DATA
,
4538 ((ushort
)s_buffer
[i
+ 1] << 8) | s_buffer
[i
]);
4543 * Copy 4 bytes to LRAM.
4545 * The source data is assumed to be in little-endian order in memory
4546 * and is maintained in little-endian order when writen to LRAM.
4549 AscMemDWordCopyPtrToLram(PortAddr iop_base
,
4550 ushort s_addr
, uchar
*s_buffer
, int dwords
)
4554 AscSetChipLramAddr(iop_base
, s_addr
);
4555 for (i
= 0; i
< 4 * dwords
; i
+= 4) {
4556 outpw(iop_base
+ IOP_RAM_DATA
, ((ushort
)s_buffer
[i
+ 1] << 8) | s_buffer
[i
]); /* LSW */
4557 outpw(iop_base
+ IOP_RAM_DATA
, ((ushort
)s_buffer
[i
+ 3] << 8) | s_buffer
[i
+ 2]); /* MSW */
4562 * Copy 2 bytes from LRAM.
4564 * The source data is assumed to be in little-endian order in LRAM
4565 * and is maintained in little-endian order when written to memory.
4568 AscMemWordCopyPtrFromLram(PortAddr iop_base
,
4569 ushort s_addr
, uchar
*d_buffer
, int words
)
4574 AscSetChipLramAddr(iop_base
, s_addr
);
4575 for (i
= 0; i
< 2 * words
; i
+= 2) {
4576 word
= inpw(iop_base
+ IOP_RAM_DATA
);
4577 d_buffer
[i
] = word
& 0xff;
4578 d_buffer
[i
+ 1] = (word
>> 8) & 0xff;
4582 static ASC_DCNT
AscMemSumLramWord(PortAddr iop_base
, ushort s_addr
, int words
)
4588 for (i
= 0; i
< words
; i
++, s_addr
+= 2) {
4589 sum
+= AscReadLramWord(iop_base
, s_addr
);
4594 static ushort
AscInitLram(ASC_DVC_VAR
*asc_dvc
)
4601 iop_base
= asc_dvc
->iop_base
;
4603 AscMemWordSetLram(iop_base
, ASC_QADR_BEG
, 0,
4604 (ushort
)(((int)(asc_dvc
->max_total_qng
+ 2 + 1) *
4606 i
= ASC_MIN_ACTIVE_QNO
;
4607 s_addr
= ASC_QADR_BEG
+ ASC_QBLK_SIZE
;
4608 AscWriteLramByte(iop_base
, (ushort
)(s_addr
+ ASC_SCSIQ_B_FWD
),
4610 AscWriteLramByte(iop_base
, (ushort
)(s_addr
+ ASC_SCSIQ_B_BWD
),
4611 (uchar
)(asc_dvc
->max_total_qng
));
4612 AscWriteLramByte(iop_base
, (ushort
)(s_addr
+ ASC_SCSIQ_B_QNO
),
4615 s_addr
+= ASC_QBLK_SIZE
;
4616 for (; i
< asc_dvc
->max_total_qng
; i
++, s_addr
+= ASC_QBLK_SIZE
) {
4617 AscWriteLramByte(iop_base
, (ushort
)(s_addr
+ ASC_SCSIQ_B_FWD
),
4619 AscWriteLramByte(iop_base
, (ushort
)(s_addr
+ ASC_SCSIQ_B_BWD
),
4621 AscWriteLramByte(iop_base
, (ushort
)(s_addr
+ ASC_SCSIQ_B_QNO
),
4624 AscWriteLramByte(iop_base
, (ushort
)(s_addr
+ ASC_SCSIQ_B_FWD
),
4625 (uchar
)ASC_QLINK_END
);
4626 AscWriteLramByte(iop_base
, (ushort
)(s_addr
+ ASC_SCSIQ_B_BWD
),
4627 (uchar
)(asc_dvc
->max_total_qng
- 1));
4628 AscWriteLramByte(iop_base
, (ushort
)(s_addr
+ ASC_SCSIQ_B_QNO
),
4629 (uchar
)asc_dvc
->max_total_qng
);
4631 s_addr
+= ASC_QBLK_SIZE
;
4632 for (; i
<= (uchar
)(asc_dvc
->max_total_qng
+ 3);
4633 i
++, s_addr
+= ASC_QBLK_SIZE
) {
4634 AscWriteLramByte(iop_base
,
4635 (ushort
)(s_addr
+ (ushort
)ASC_SCSIQ_B_FWD
), i
);
4636 AscWriteLramByte(iop_base
,
4637 (ushort
)(s_addr
+ (ushort
)ASC_SCSIQ_B_BWD
), i
);
4638 AscWriteLramByte(iop_base
,
4639 (ushort
)(s_addr
+ (ushort
)ASC_SCSIQ_B_QNO
), i
);
4645 AscLoadMicroCode(PortAddr iop_base
,
4646 ushort s_addr
, uchar
*mcode_buf
, ushort mcode_size
)
4649 ushort mcode_word_size
;
4650 ushort mcode_chksum
;
4652 /* Write the microcode buffer starting at LRAM address 0. */
4653 mcode_word_size
= (ushort
)(mcode_size
>> 1);
4654 AscMemWordSetLram(iop_base
, s_addr
, 0, mcode_word_size
);
4655 AscMemWordCopyPtrToLram(iop_base
, s_addr
, mcode_buf
, mcode_word_size
);
4657 chksum
= AscMemSumLramWord(iop_base
, s_addr
, mcode_word_size
);
4658 ASC_DBG(1, "chksum 0x%lx\n", (ulong
)chksum
);
4659 mcode_chksum
= (ushort
)AscMemSumLramWord(iop_base
,
4660 (ushort
)ASC_CODE_SEC_BEG
,
4661 (ushort
)((mcode_size
-
4665 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong
)mcode_chksum
);
4666 AscWriteLramWord(iop_base
, ASCV_MCODE_CHKSUM_W
, mcode_chksum
);
4667 AscWriteLramWord(iop_base
, ASCV_MCODE_SIZE_W
, mcode_size
);
4671 /* Microcode buffer is kept after initialization for error recovery. */
4672 static uchar _asc_mcode_buf
[] = {
4673 0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4674 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
4675 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4676 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4677 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4678 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05,
4679 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4680 0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4681 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF,
4682 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
4683 0x00, 0x00, 0xE4, 0x88, 0x00, 0x00, 0x00, 0x00, 0x80, 0x73, 0x48, 0x04,
4684 0x36, 0x00, 0x00, 0xA2, 0xC2, 0x00, 0x80, 0x73, 0x03, 0x23, 0x36, 0x40,
4685 0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12, 0xDA, 0x00, 0xA2,
4686 0xC2, 0x00, 0x92, 0x80, 0x1E, 0x98, 0x50, 0x00, 0xF5, 0x00, 0x48, 0x98,
4687 0xDF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x4F, 0x00, 0xF5, 0x00,
4688 0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x80, 0x62,
4689 0x92, 0x80, 0x00, 0x46, 0x15, 0xEE, 0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8,
4690 0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23,
4691 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0xD2, 0xC1, 0x80, 0x73, 0xCD, 0x04,
4692 0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01, 0xA6, 0x97, 0xC6, 0x81, 0xC2, 0x88,
4693 0x80, 0x73, 0x80, 0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00,
4694 0x84, 0x97, 0x07, 0xA6, 0x08, 0x01, 0x00, 0x33, 0x03, 0x00, 0xC2, 0x88,
4695 0x03, 0x03, 0x01, 0xDE, 0xC2, 0x88, 0xCE, 0x00, 0x69, 0x60, 0xCE, 0x00,
4696 0x02, 0x03, 0x4A, 0x60, 0x00, 0xA2, 0x78, 0x01, 0x80, 0x63, 0x07, 0xA6,
4697 0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2, 0x00, 0x07, 0xA6,
4698 0x34, 0x01, 0x00, 0x33, 0x04, 0x00, 0xC2, 0x88, 0x03, 0x07, 0x02, 0x01,
4699 0x04, 0xCA, 0x0D, 0x23, 0x68, 0x98, 0x4D, 0x04, 0x04, 0x85, 0x05, 0xD8,
4700 0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23, 0xF8, 0x88, 0xFB, 0x23,
4701 0x02, 0x61, 0x82, 0x01, 0x80, 0x63, 0x02, 0x03, 0x06, 0xA3, 0x62, 0x01,
4702 0x00, 0x33, 0x0A, 0x00, 0xC2, 0x88, 0x4E, 0x00, 0x07, 0xA3, 0x6E, 0x01,
4703 0x00, 0x33, 0x0B, 0x00, 0xC2, 0x88, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33,
4704 0x1A, 0x00, 0xC2, 0x88, 0x50, 0x04, 0x88, 0x81, 0x06, 0xAB, 0x82, 0x01,
4705 0x88, 0x81, 0x4E, 0x00, 0x07, 0xA3, 0x92, 0x01, 0x50, 0x00, 0x00, 0xA3,
4706 0x3C, 0x01, 0x00, 0x05, 0x7C, 0x81, 0x46, 0x97, 0x02, 0x01, 0x05, 0xC6,
4707 0x04, 0x23, 0xA0, 0x01, 0x15, 0x23, 0xA1, 0x01, 0xBE, 0x81, 0xFD, 0x23,
4708 0x02, 0x61, 0x82, 0x01, 0x0A, 0xDA, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0,
4709 0xB4, 0x01, 0x80, 0x63, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33, 0x1B, 0x00,
4710 0xC2, 0x88, 0x06, 0x23, 0x68, 0x98, 0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01,
4711 0x00, 0xA2, 0xD4, 0x01, 0x57, 0x60, 0x00, 0xA0, 0xDA, 0x01, 0xE6, 0x84,
4712 0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73, 0x4B, 0x00, 0x06, 0x61,
4713 0x00, 0xA2, 0x00, 0x02, 0x04, 0x01, 0x0C, 0xDE, 0x02, 0x01, 0x03, 0xCC,
4714 0x4F, 0x00, 0x84, 0x97, 0xFC, 0x81, 0x08, 0x23, 0x02, 0x41, 0x82, 0x01,
4715 0x4F, 0x00, 0x62, 0x97, 0x48, 0x04, 0x84, 0x80, 0xF0, 0x97, 0x00, 0x46,
4716 0x56, 0x00, 0x03, 0xC0, 0x01, 0x23, 0xE8, 0x00, 0x81, 0x73, 0x06, 0x29,
4717 0x03, 0x42, 0x06, 0xE2, 0x03, 0xEE, 0x6B, 0xEB, 0x11, 0x23, 0xF8, 0x88,
4718 0x04, 0x98, 0xF0, 0x80, 0x80, 0x73, 0x80, 0x77, 0x07, 0xA4, 0x2A, 0x02,
4719 0x7C, 0x95, 0x06, 0xA6, 0x34, 0x02, 0x03, 0xA6, 0x4C, 0x04, 0x46, 0x82,
4720 0x04, 0x01, 0x03, 0xD8, 0xB4, 0x98, 0x6A, 0x96, 0x46, 0x82, 0xFE, 0x95,
4721 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02, 0xA6, 0x6C, 0x02,
4722 0x07, 0xA6, 0x5A, 0x02, 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x62, 0x02,
4723 0xC2, 0x88, 0x7C, 0x95, 0x48, 0x82, 0x60, 0x96, 0x48, 0x82, 0x04, 0x23,
4724 0xA0, 0x01, 0x14, 0x23, 0xA1, 0x01, 0x3C, 0x84, 0x04, 0x01, 0x0C, 0xDC,
4725 0xE0, 0x23, 0x25, 0x61, 0xEF, 0x00, 0x14, 0x01, 0x4F, 0x04, 0xA8, 0x01,
4726 0x6F, 0x00, 0xA5, 0x01, 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01,
4727 0x24, 0x2B, 0x1C, 0x01, 0x02, 0xA6, 0xAA, 0x02, 0x07, 0xA6, 0x5A, 0x02,
4728 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x20, 0x04, 0x01, 0xA6, 0xB4, 0x02,
4729 0x00, 0xA6, 0xB4, 0x02, 0x00, 0x33, 0x12, 0x00, 0xC2, 0x88, 0x00, 0x0E,
4730 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0x8C, 0x02, 0x4D, 0x04, 0x04, 0x01,
4731 0x0B, 0xDC, 0xE7, 0x23, 0x04, 0x61, 0x84, 0x01, 0x10, 0x31, 0x12, 0x35,
4732 0x14, 0x01, 0xEC, 0x00, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0xEA, 0x82,
4733 0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04, 0x01, 0xA2, 0xC8,
4734 0x00, 0x33, 0x1F, 0x00, 0xC2, 0x88, 0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39,
4735 0x0E, 0x3D, 0x7E, 0x98, 0xB6, 0x2D, 0x01, 0xA6, 0x14, 0x03, 0x00, 0xA6,
4736 0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6, 0x10, 0x03, 0x03, 0xA6,
4737 0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02, 0x00, 0x33, 0x33, 0x00, 0xC2, 0x88,
4738 0x7C, 0x95, 0xEE, 0x82, 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42,
4739 0x7E, 0x98, 0x64, 0xE4, 0x04, 0x01, 0x2D, 0xC8, 0x31, 0x05, 0x07, 0x01,
4740 0x00, 0xA2, 0x54, 0x03, 0x00, 0x43, 0x87, 0x01, 0x05, 0x05, 0x86, 0x98,
4741 0x7E, 0x98, 0x00, 0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6,
4742 0x3C, 0x04, 0x06, 0xA6, 0x50, 0x03, 0x01, 0xA6, 0x16, 0x03, 0x00, 0x33,
4743 0x25, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x32, 0x83, 0x60, 0x96, 0x32, 0x83,
4744 0x04, 0x01, 0x10, 0xCE, 0x07, 0xC8, 0x05, 0x05, 0xEB, 0x04, 0x00, 0x33,
4745 0x00, 0x20, 0xC0, 0x20, 0x81, 0x62, 0x72, 0x83, 0x00, 0x01, 0x05, 0x05,
4746 0xFF, 0xA2, 0x7A, 0x03, 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83,
4747 0x05, 0x05, 0x15, 0x01, 0x00, 0xA2, 0x9A, 0x03, 0xEC, 0x00, 0x6E, 0x00,
4748 0x95, 0x01, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0x01, 0xA6, 0x96, 0x03,
4749 0x00, 0xA6, 0x96, 0x03, 0x10, 0x84, 0x80, 0x42, 0x7E, 0x98, 0x01, 0xA6,
4750 0xA4, 0x03, 0x00, 0xA6, 0xBC, 0x03, 0x10, 0x84, 0xA8, 0x98, 0x80, 0x42,
4751 0x01, 0xA6, 0xA4, 0x03, 0x07, 0xA6, 0xB2, 0x03, 0xD4, 0x83, 0x7C, 0x95,
4752 0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00, 0xC2, 0x88, 0xA8, 0x98, 0x80, 0x42,
4753 0x00, 0xA6, 0xBC, 0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95,
4754 0xC0, 0x83, 0x00, 0x33, 0x26, 0x00, 0xC2, 0x88, 0x38, 0x2B, 0x80, 0x32,
4755 0x80, 0x36, 0x04, 0x23, 0xA0, 0x01, 0x12, 0x23, 0xA1, 0x01, 0x10, 0x84,
4756 0x07, 0xF0, 0x06, 0xA4, 0xF4, 0x03, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23,
4757 0x83, 0x03, 0x80, 0x63, 0x03, 0xA6, 0x0E, 0x04, 0x07, 0xA6, 0x06, 0x04,
4758 0x06, 0xA6, 0x0A, 0x04, 0x00, 0x33, 0x17, 0x00, 0xC2, 0x88, 0x7C, 0x95,
4759 0xF4, 0x83, 0x60, 0x96, 0xF4, 0x83, 0x20, 0x84, 0x07, 0xF0, 0x06, 0xA4,
4760 0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, 0x83, 0x03, 0x80, 0x63,
4761 0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04, 0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6,
4762 0x38, 0x04, 0x00, 0x33, 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84,
4763 0x60, 0x96, 0x20, 0x84, 0x1D, 0x01, 0x06, 0xCC, 0x00, 0x33, 0x00, 0x84,
4764 0xC0, 0x20, 0x00, 0x23, 0xEA, 0x00, 0x81, 0x62, 0xA2, 0x0D, 0x80, 0x63,
4765 0x07, 0xA6, 0x5A, 0x04, 0x00, 0x33, 0x18, 0x00, 0xC2, 0x88, 0x03, 0x03,
4766 0x80, 0x63, 0xA3, 0x01, 0x07, 0xA4, 0x64, 0x04, 0x23, 0x01, 0x00, 0xA2,
4767 0x86, 0x04, 0x0A, 0xA0, 0x76, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1D, 0x00,
4768 0xC2, 0x88, 0x0B, 0xA0, 0x82, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1E, 0x00,
4769 0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22, 0xA3, 0xE6, 0x04,
4770 0x08, 0x23, 0x22, 0xA3, 0xA2, 0x04, 0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04,
4771 0x02, 0x23, 0x22, 0xA3, 0xC4, 0x04, 0x42, 0x23, 0xF8, 0x88, 0x4A, 0x00,
4772 0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23, 0xF8, 0x88, 0x04, 0x98,
4773 0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x82, 0xC0, 0x20,
4774 0x81, 0x62, 0xE8, 0x81, 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE,
4775 0x04, 0x98, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x81, 0xC0, 0x20, 0x81, 0x62,
4776 0x14, 0x01, 0x00, 0xA0, 0x00, 0x02, 0x43, 0x23, 0xF8, 0x88, 0x04, 0x23,
4777 0xA0, 0x01, 0x44, 0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3,
4778 0xF4, 0x04, 0x00, 0x33, 0x27, 0x00, 0xC2, 0x88, 0x04, 0x01, 0x04, 0xDC,
4779 0x02, 0x23, 0xA2, 0x01, 0x04, 0x23, 0xA0, 0x01, 0x04, 0x98, 0x26, 0x95,
4780 0x4B, 0x00, 0xF6, 0x00, 0x4F, 0x04, 0x4F, 0x00, 0x00, 0xA3, 0x22, 0x05,
4781 0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C, 0x05, 0x0A, 0x85,
4782 0x46, 0x97, 0xCD, 0x04, 0x24, 0x85, 0x48, 0x04, 0x84, 0x80, 0x02, 0x01,
4783 0x03, 0xDA, 0x80, 0x23, 0x82, 0x01, 0x34, 0x85, 0x02, 0x23, 0xA0, 0x01,
4784 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05, 0x1D, 0x01, 0x04, 0xD6,
4785 0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60, 0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01,
4786 0x49, 0x00, 0x81, 0x01, 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01,
4787 0xF7, 0x04, 0x03, 0x01, 0x49, 0x04, 0x80, 0x01, 0xC9, 0x00, 0x00, 0x05,
4788 0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05, 0x77, 0x04, 0x01, 0x23, 0xEA, 0x00,
4789 0x5D, 0x00, 0xFE, 0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63,
4790 0x07, 0xA4, 0xF8, 0x05, 0x03, 0x03, 0x02, 0xA0, 0x8E, 0x05, 0xF4, 0x85,
4791 0x00, 0x33, 0x2D, 0x00, 0xC2, 0x88, 0x04, 0xA0, 0xB8, 0x05, 0x80, 0x63,
4792 0x00, 0x23, 0xDF, 0x00, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0xA4, 0x05,
4793 0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82, 0x01, 0x50, 0x00,
4794 0x62, 0x97, 0x04, 0x85, 0x04, 0x23, 0x02, 0x41, 0x82, 0x01, 0x04, 0x85,
4795 0x08, 0xA0, 0xBE, 0x05, 0xF4, 0x85, 0x03, 0xA0, 0xC4, 0x05, 0xF4, 0x85,
4796 0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63, 0xCC, 0x86, 0x07, 0xA0,
4797 0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B, 0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05,
4798 0x80, 0x67, 0x80, 0x63, 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23,
4799 0x68, 0x98, 0x48, 0x23, 0xF8, 0x88, 0x07, 0x23, 0x80, 0x00, 0x06, 0x87,
4800 0x80, 0x63, 0x7C, 0x85, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x4A, 0x00,
4801 0x06, 0x61, 0x00, 0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23,
4802 0x07, 0x41, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x1C, 0x06, 0x00, 0x33,
4803 0x37, 0x00, 0xC2, 0x88, 0x1D, 0x01, 0x01, 0xD6, 0x20, 0x23, 0x63, 0x60,
4804 0x83, 0x03, 0x80, 0x63, 0x02, 0x23, 0xDF, 0x00, 0x07, 0xA6, 0x7C, 0x05,
4805 0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06, 0x41, 0xCB, 0x00,
4806 0x52, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA,
4807 0xC0, 0x23, 0x07, 0x41, 0x00, 0x63, 0x1D, 0x01, 0x04, 0xCC, 0x00, 0x33,
4808 0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23, 0x07, 0x41, 0x00, 0x63,
4809 0x80, 0x67, 0x08, 0x23, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x01, 0x23,
4810 0xDF, 0x00, 0x06, 0xA6, 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67,
4811 0x80, 0x63, 0x00, 0x33, 0x00, 0x40, 0xC0, 0x20, 0x81, 0x62, 0x00, 0x63,
4812 0x00, 0x00, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x94, 0x06,
4813 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B,
4814 0x40, 0x0E, 0x80, 0x63, 0x01, 0x00, 0x06, 0xA6, 0xAA, 0x06, 0x07, 0xA6,
4815 0x7C, 0x05, 0x40, 0x0E, 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0xA2, 0x06,
4816 0x06, 0xA6, 0xBC, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x40, 0x0E,
4817 0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63,
4818 0x07, 0xA6, 0xD6, 0x06, 0x00, 0x33, 0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03,
4819 0x80, 0x63, 0x89, 0x00, 0x0A, 0x2B, 0x07, 0xA6, 0xE8, 0x06, 0x00, 0x33,
4820 0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2, 0xF4, 0x06, 0xC0, 0x0E,
4821 0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E, 0x00, 0x33, 0x00, 0x80, 0xC0, 0x20,
4822 0x81, 0x62, 0x04, 0x01, 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B,
4823 0x80, 0x63, 0x06, 0xA6, 0x8C, 0x06, 0x00, 0x33, 0x2C, 0x00, 0xC2, 0x88,
4824 0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6,
4825 0x2C, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88,
4826 0x00, 0x00, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0x0C, 0xA0, 0x44, 0x07,
4827 0x07, 0xA6, 0x7C, 0x05, 0xBF, 0x23, 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84,
4828 0x00, 0x63, 0xF0, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x00, 0x01, 0xF2, 0x00,
4829 0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81, 0x01, 0x70, 0x04,
4830 0x80, 0x05, 0x81, 0x05, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04,
4831 0x01, 0x01, 0xF1, 0x00, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04, 0x71, 0x00,
4832 0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04, 0x70, 0x00, 0x80, 0x01,
4833 0x70, 0x04, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x00, 0x01,
4834 0xF1, 0x00, 0x70, 0x00, 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01,
4835 0x72, 0x00, 0x81, 0x01, 0x71, 0x04, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04,
4836 0x00, 0x63, 0x00, 0x23, 0xB3, 0x01, 0x83, 0x05, 0xA3, 0x01, 0xA2, 0x01,
4837 0xA1, 0x01, 0x01, 0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1,
4838 0xC4, 0x07, 0x00, 0x33, 0x07, 0x00, 0xC2, 0x88, 0x80, 0x05, 0x81, 0x05,
4839 0x04, 0x01, 0x11, 0xC8, 0x48, 0x00, 0xB0, 0x01, 0xB1, 0x01, 0x08, 0x23,
4840 0xB2, 0x01, 0x05, 0x01, 0x48, 0x04, 0x00, 0x43, 0x00, 0xA2, 0xE4, 0x07,
4841 0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF, 0x23, 0x80, 0x01,
4842 0x05, 0x05, 0x00, 0x63, 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04,
4843 0x00, 0x02, 0x80, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63,
4844 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x00, 0xA0,
4845 0x14, 0x08, 0x16, 0x88, 0x00, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04,
4846 0x00, 0x63, 0xF3, 0x04, 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43,
4847 0xF4, 0x00, 0xCF, 0x40, 0x00, 0xA2, 0x44, 0x08, 0x74, 0x04, 0x02, 0x01,
4848 0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01, 0x01, 0xA1, 0x24, 0x08, 0x04, 0x98,
4849 0x26, 0x95, 0x24, 0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04,
4850 0x5A, 0x88, 0x02, 0x01, 0x04, 0xD8, 0x46, 0x97, 0x04, 0x98, 0x26, 0x95,
4851 0x4A, 0x88, 0x75, 0x00, 0x00, 0xA3, 0x64, 0x08, 0x00, 0x05, 0x4E, 0x88,
4852 0x73, 0x04, 0x00, 0x63, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x76, 0x08,
4853 0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63,
4854 0x00, 0x63, 0x38, 0x2B, 0x9C, 0x88, 0x38, 0x2B, 0x92, 0x88, 0x32, 0x09,
4855 0x31, 0x05, 0x92, 0x98, 0x05, 0x05, 0xB2, 0x09, 0x00, 0x63, 0x00, 0x32,
4856 0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63, 0x80, 0x32, 0x80, 0x36,
4857 0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D, 0x00, 0x63, 0x38, 0x2B, 0x40, 0x32,
4858 0x40, 0x36, 0x40, 0x3A, 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40,
4859 0x00, 0xA0, 0xB4, 0x08, 0x5D, 0x00, 0xFE, 0xC3, 0x00, 0x63, 0x80, 0x73,
4860 0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00, 0x82, 0x73, 0xFF, 0xFD, 0x80, 0x73,
4861 0x13, 0x23, 0xF8, 0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01,
4862 0xA1, 0x23, 0xA1, 0x01, 0x81, 0x62, 0xE2, 0x88, 0x80, 0x73, 0x80, 0x77,
4863 0x68, 0x00, 0x00, 0xA2, 0x80, 0x00, 0x03, 0xC2, 0xF1, 0xC7, 0x41, 0x23,
4864 0xF8, 0x88, 0x11, 0x23, 0xA1, 0x01, 0x04, 0x23, 0xA0, 0x01, 0xE6, 0x84,
4867 static unsigned short _asc_mcode_size
= sizeof(_asc_mcode_buf
);
4868 static ADV_DCNT _asc_mcode_chksum
= 0x012C453FUL
;
4870 /* Microcode buffer is kept after initialization for error recovery. */
4871 static unsigned char _adv_asc3550_buf
[] = {
4872 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x18, 0xe4, 0x00, 0xfc,
4873 0x01, 0x00, 0x48, 0xe4, 0xbe, 0x18, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00,
4874 0x00, 0xfa, 0xff, 0xff, 0x28, 0x0e, 0x9e, 0xe7, 0xff, 0x00, 0x82, 0xe7,
4875 0x00, 0xea, 0x00, 0xf6, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0, 0x01, 0xf6,
4876 0x01, 0xfa, 0x08, 0x00, 0x03, 0x00, 0x04, 0x00, 0x18, 0xf4, 0x10, 0x00,
4877 0x00, 0xec, 0x85, 0xf0, 0xbc, 0x00, 0xd5, 0xf0, 0x8e, 0x0c, 0x38, 0x54,
4878 0x00, 0xe6, 0x1e, 0xf0, 0x86, 0xf0, 0xb4, 0x00, 0x98, 0x57, 0xd0, 0x01,
4879 0x0c, 0x1c, 0x3e, 0x1c, 0x0c, 0x00, 0xbb, 0x00, 0xaa, 0x18, 0x02, 0x80,
4880 0x32, 0xf0, 0x01, 0xfc, 0x88, 0x0c, 0xc6, 0x12, 0x02, 0x13, 0x18, 0x40,
4881 0x00, 0x57, 0x01, 0xea, 0x3c, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
4882 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
4883 0x3e, 0x01, 0xda, 0x0f, 0x22, 0x10, 0x08, 0x12, 0x02, 0x4a, 0xb9, 0x54,
4884 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x20, 0x00, 0x32, 0x00,
4885 0x3e, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
4886 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x62, 0x0a,
4887 0x92, 0x0c, 0x2c, 0x10, 0x2e, 0x10, 0x06, 0x13, 0x4c, 0x1c, 0xbb, 0x55,
4888 0x3c, 0x56, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0xb1, 0xf0,
4889 0x03, 0xf7, 0x06, 0xf7, 0x03, 0xfc, 0x0f, 0x00, 0x40, 0x00, 0xbe, 0x00,
4890 0x00, 0x01, 0xb0, 0x08, 0x30, 0x13, 0x64, 0x15, 0x32, 0x1c, 0x38, 0x1c,
4891 0x4e, 0x1c, 0x10, 0x44, 0x02, 0x48, 0x00, 0x4c, 0x04, 0xea, 0x5d, 0xf0,
4892 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00,
4893 0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, 0x4e, 0x0b, 0x1e, 0x0e, 0x0c, 0x10,
4894 0x0a, 0x12, 0x04, 0x13, 0x40, 0x13, 0x30, 0x1c, 0x00, 0x4e, 0xbd, 0x56,
4895 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xa7, 0xf0,
4896 0xb8, 0xf0, 0x0e, 0xf7, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00,
4897 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00,
4898 0xde, 0x03, 0x56, 0x0a, 0x14, 0x0e, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10,
4899 0x36, 0x10, 0x0a, 0x13, 0x12, 0x13, 0x52, 0x13, 0x10, 0x15, 0x14, 0x15,
4900 0xac, 0x16, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44,
4901 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x83, 0x55,
4902 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0, 0x0c, 0xf0,
4903 0x5c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8, 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa,
4904 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00, 0x0a, 0x00, 0x0d, 0x00, 0x1c, 0x00,
4905 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0x22, 0x01,
4906 0x26, 0x01, 0x79, 0x01, 0x7a, 0x01, 0xc0, 0x01, 0xc2, 0x01, 0x7c, 0x02,
4907 0x5a, 0x03, 0xea, 0x04, 0xe8, 0x07, 0x68, 0x08, 0x69, 0x08, 0xba, 0x08,
4908 0xe9, 0x09, 0x06, 0x0b, 0x3a, 0x0e, 0x00, 0x10, 0x1a, 0x10, 0xed, 0x10,
4909 0xf1, 0x10, 0x06, 0x12, 0x0c, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x82, 0x13,
4910 0x42, 0x14, 0xd6, 0x14, 0x8a, 0x15, 0xc6, 0x17, 0xd2, 0x17, 0x6b, 0x18,
4911 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40, 0x0e, 0x47, 0x48, 0x47,
4912 0x41, 0x48, 0x89, 0x48, 0x80, 0x4c, 0x00, 0x54, 0x44, 0x55, 0xe5, 0x55,
4913 0x14, 0x56, 0x77, 0x57, 0xbf, 0x57, 0x40, 0x5c, 0x06, 0x80, 0x08, 0x90,
4914 0x03, 0xa1, 0xfe, 0x9c, 0xf0, 0x29, 0x02, 0xfe, 0xb8, 0x0c, 0xff, 0x10,
4915 0x00, 0x00, 0xd0, 0xfe, 0xcc, 0x18, 0x00, 0xcf, 0xfe, 0x80, 0x01, 0xff,
4916 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
4917 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x48, 0x00, 0x4f, 0xff, 0x04, 0x00,
4918 0x00, 0x10, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
4919 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x0f,
4920 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
4921 0xfe, 0x04, 0xf7, 0xcf, 0x2a, 0x67, 0x0b, 0x01, 0xfe, 0xce, 0x0e, 0xfe,
4922 0x04, 0xf7, 0xcf, 0x67, 0x0b, 0x3c, 0x2a, 0xfe, 0x3d, 0xf0, 0xfe, 0x02,
4923 0x02, 0xfe, 0x20, 0xf0, 0x9c, 0xfe, 0x91, 0xf0, 0xfe, 0xf0, 0x01, 0xfe,
4924 0x90, 0xf0, 0xfe, 0xf0, 0x01, 0xfe, 0x8f, 0xf0, 0x9c, 0x05, 0x51, 0x3b,
4925 0x02, 0xfe, 0xd4, 0x0c, 0x01, 0xfe, 0x44, 0x0d, 0xfe, 0xdd, 0x12, 0xfe,
4926 0xfc, 0x10, 0xfe, 0x28, 0x1c, 0x05, 0xfe, 0xa6, 0x00, 0xfe, 0xd3, 0x12,
4927 0x47, 0x18, 0xfe, 0xa6, 0x00, 0xb5, 0xfe, 0x48, 0xf0, 0xfe, 0x86, 0x02,
4928 0xfe, 0x49, 0xf0, 0xfe, 0xa0, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xbe, 0x02,
4929 0xfe, 0x46, 0xf0, 0xfe, 0x50, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x56, 0x02,
4930 0xfe, 0x43, 0xf0, 0xfe, 0x44, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x48, 0x02,
4931 0xfe, 0x45, 0xf0, 0xfe, 0x4c, 0x02, 0x17, 0x0b, 0xa0, 0x17, 0x06, 0x18,
4932 0x96, 0x02, 0x29, 0xfe, 0x00, 0x1c, 0xde, 0xfe, 0x02, 0x1c, 0xdd, 0xfe,
4933 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0xfe, 0x20, 0x17, 0xfe, 0xe7, 0x10,
4934 0xfe, 0x06, 0xfc, 0xc7, 0x0a, 0x6b, 0x01, 0x9e, 0x02, 0x29, 0x14, 0x4d,
4935 0x37, 0x97, 0x01, 0xfe, 0x64, 0x0f, 0x0a, 0x6b, 0x01, 0x82, 0xfe, 0xbd,
4936 0x10, 0x0a, 0x6b, 0x01, 0x82, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c, 0xfe,
4937 0x58, 0x1c, 0x17, 0x06, 0x18, 0x96, 0x2a, 0x25, 0x29, 0xfe, 0x3d, 0xf0,
4938 0xfe, 0x02, 0x02, 0x21, 0xfe, 0x94, 0x02, 0xfe, 0x5a, 0x1c, 0xea, 0xfe,
4939 0x14, 0x1c, 0x14, 0xfe, 0x30, 0x00, 0x37, 0x97, 0x01, 0xfe, 0x54, 0x0f,
4940 0x17, 0x06, 0x18, 0x96, 0x02, 0xd0, 0x1e, 0x20, 0x07, 0x10, 0x34, 0xfe,
4941 0x69, 0x10, 0x17, 0x06, 0x18, 0x96, 0xfe, 0x04, 0xec, 0x20, 0x46, 0x3d,
4942 0x12, 0x20, 0xfe, 0x05, 0xf6, 0xc7, 0x01, 0xfe, 0x52, 0x16, 0x09, 0x4a,
4943 0x4c, 0x35, 0x11, 0x2d, 0x3c, 0x8a, 0x01, 0xe6, 0x02, 0x29, 0x0a, 0x40,
4944 0x01, 0x0e, 0x07, 0x00, 0x5d, 0x01, 0x6f, 0xfe, 0x18, 0x10, 0xfe, 0x41,
4945 0x58, 0x0a, 0x99, 0x01, 0x0e, 0xfe, 0xc8, 0x54, 0x64, 0xfe, 0x0c, 0x03,
4946 0x01, 0xe6, 0x02, 0x29, 0x2a, 0x46, 0xfe, 0x02, 0xe8, 0x27, 0xf8, 0xfe,
4947 0x9e, 0x43, 0xf7, 0xfe, 0x27, 0xf0, 0xfe, 0xdc, 0x01, 0xfe, 0x07, 0x4b,
4948 0xfe, 0x20, 0xf0, 0x9c, 0xfe, 0x40, 0x1c, 0x25, 0xd2, 0xfe, 0x26, 0xf0,
4949 0xfe, 0x56, 0x03, 0xfe, 0xa0, 0xf0, 0xfe, 0x44, 0x03, 0xfe, 0x11, 0xf0,
4950 0x9c, 0xfe, 0xef, 0x10, 0xfe, 0x9f, 0xf0, 0xfe, 0x64, 0x03, 0xeb, 0x0f,
4951 0xfe, 0x11, 0x00, 0x02, 0x5a, 0x2a, 0xfe, 0x48, 0x1c, 0xeb, 0x09, 0x04,
4952 0x1d, 0xfe, 0x18, 0x13, 0x23, 0x1e, 0x98, 0xac, 0x12, 0x98, 0x0a, 0x40,
4953 0x01, 0x0e, 0xac, 0x75, 0x01, 0xfe, 0xbc, 0x15, 0x11, 0xca, 0x25, 0xd2,
4954 0xfe, 0x01, 0xf0, 0xd2, 0xfe, 0x82, 0xf0, 0xfe, 0x92, 0x03, 0xec, 0x11,
4955 0xfe, 0xe4, 0x00, 0x65, 0xfe, 0xa4, 0x03, 0x25, 0x32, 0x1f, 0xfe, 0xb4,
4956 0x03, 0x01, 0x43, 0xfe, 0x06, 0xf0, 0xfe, 0xc4, 0x03, 0x8d, 0x81, 0xfe,
4957 0x0a, 0xf0, 0xfe, 0x7a, 0x06, 0x02, 0x22, 0x05, 0x6b, 0x28, 0x16, 0xfe,
4958 0xf6, 0x04, 0x14, 0x2c, 0x01, 0x33, 0x8f, 0xfe, 0x66, 0x02, 0x02, 0xd1,
4959 0xeb, 0x2a, 0x67, 0x1a, 0xfe, 0x67, 0x1b, 0xf8, 0xf7, 0xfe, 0x48, 0x1c,
4960 0x70, 0x01, 0x6e, 0x87, 0x0a, 0x40, 0x01, 0x0e, 0x07, 0x00, 0x16, 0xd3,
4961 0x0a, 0xca, 0x01, 0x0e, 0x74, 0x60, 0x59, 0x76, 0x27, 0x05, 0x6b, 0x28,
4962 0xfe, 0x10, 0x12, 0x14, 0x2c, 0x01, 0x33, 0x8f, 0xfe, 0x66, 0x02, 0x02,
4963 0xd1, 0xbc, 0x7d, 0xbd, 0x7f, 0x25, 0x22, 0x65, 0xfe, 0x3c, 0x04, 0x1f,
4964 0xfe, 0x38, 0x04, 0x68, 0xfe, 0xa0, 0x00, 0xfe, 0x9b, 0x57, 0xfe, 0x4e,
4965 0x12, 0x2b, 0xff, 0x02, 0x00, 0x10, 0x01, 0x08, 0x1f, 0xfe, 0xe0, 0x04,
4966 0x2b, 0x01, 0x08, 0x1f, 0x22, 0x30, 0x2e, 0xd5, 0xfe, 0x4c, 0x44, 0xfe,
4967 0x4c, 0x12, 0x60, 0xfe, 0x44, 0x48, 0x13, 0x2c, 0xfe, 0x4c, 0x54, 0x64,
4968 0xd3, 0x46, 0x76, 0x27, 0xfa, 0xef, 0xfe, 0x62, 0x13, 0x09, 0x04, 0x1d,
4969 0xfe, 0x2a, 0x13, 0x2f, 0x07, 0x7e, 0xa5, 0xfe, 0x20, 0x10, 0x13, 0x2c,
4970 0xfe, 0x4c, 0x54, 0x64, 0xd3, 0xfa, 0xef, 0x86, 0x09, 0x04, 0x1d, 0xfe,
4971 0x08, 0x13, 0x2f, 0x07, 0x7e, 0x6e, 0x09, 0x04, 0x1d, 0xfe, 0x1c, 0x12,
4972 0x14, 0x92, 0x09, 0x04, 0x06, 0x3b, 0x14, 0xc4, 0x01, 0x33, 0x8f, 0xfe,
4973 0x70, 0x0c, 0x02, 0x22, 0x2b, 0x11, 0xfe, 0xe6, 0x00, 0xfe, 0x1c, 0x90,
4974 0xf9, 0x03, 0x14, 0x92, 0x01, 0x33, 0x02, 0x29, 0xfe, 0x42, 0x5b, 0x67,
4975 0x1a, 0xfe, 0x46, 0x59, 0xf8, 0xf7, 0xfe, 0x87, 0x80, 0xfe, 0x31, 0xe4,
4976 0x4f, 0x09, 0x04, 0x0b, 0xfe, 0x78, 0x13, 0xfe, 0x20, 0x80, 0x07, 0x1a,
4977 0xfe, 0x70, 0x12, 0x49, 0x04, 0x06, 0xfe, 0x60, 0x13, 0x05, 0xfe, 0xa2,
4978 0x00, 0x28, 0x16, 0xfe, 0x80, 0x05, 0xfe, 0x31, 0xe4, 0x6a, 0x49, 0x04,
4979 0x0b, 0xfe, 0x4a, 0x13, 0x05, 0xfe, 0xa0, 0x00, 0x28, 0xfe, 0x42, 0x12,
4980 0x5e, 0x01, 0x08, 0x25, 0x32, 0xf1, 0x01, 0x08, 0x26, 0xfe, 0x98, 0x05,
4981 0x11, 0xfe, 0xe3, 0x00, 0x23, 0x49, 0xfe, 0x4a, 0xf0, 0xfe, 0x6a, 0x05,
4982 0xfe, 0x49, 0xf0, 0xfe, 0x64, 0x05, 0x83, 0x24, 0xfe, 0x21, 0x00, 0xa1,
4983 0x24, 0xfe, 0x22, 0x00, 0xa0, 0x24, 0x4c, 0xfe, 0x09, 0x48, 0x01, 0x08,
4984 0x26, 0xfe, 0x98, 0x05, 0xfe, 0xe2, 0x08, 0x49, 0x04, 0xc5, 0x3b, 0x01,
4985 0x86, 0x24, 0x06, 0x12, 0xcc, 0x37, 0xfe, 0x27, 0x01, 0x09, 0x04, 0x1d,
4986 0xfe, 0x22, 0x12, 0x47, 0x01, 0xa7, 0x14, 0x92, 0x09, 0x04, 0x06, 0x3b,
4987 0x14, 0xc4, 0x01, 0x33, 0x8f, 0xfe, 0x70, 0x0c, 0x02, 0x22, 0x05, 0xfe,
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5283 0xaf, 0xff, 0x04, 0x68, 0x54, 0xde, 0x1c, 0x69, 0x03, 0x07, 0x7a, 0xfe,
5284 0x5a, 0xf0, 0xfe, 0x74, 0x18, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10,
5285 0x07, 0x1b, 0xfe, 0x5a, 0xf0, 0xfe, 0x82, 0x18, 0x24, 0xc3, 0xfe, 0x26,
5286 0x10, 0x07, 0x1a, 0x5d, 0x24, 0x2c, 0xdc, 0x07, 0x0b, 0x5d, 0x24, 0x93,
5287 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x5d, 0x24, 0x4d, 0x9f, 0xad, 0x03, 0x14,
5288 0xfe, 0x09, 0x00, 0x01, 0x33, 0xfe, 0x04, 0xfe, 0x7d, 0x05, 0x7f, 0xf9,
5289 0x03, 0x25, 0xfe, 0xca, 0x18, 0xfe, 0x14, 0xf0, 0x08, 0x65, 0xfe, 0xc6,
5290 0x18, 0x03, 0xff, 0x1a, 0x00, 0x00,
5293 static unsigned short _adv_asc3550_size
= sizeof(_adv_asc3550_buf
); /* 0x13AD */
5294 static ADV_DCNT _adv_asc3550_chksum
= 0x04D52DDDUL
; /* Expanded little-endian checksum. */
5296 /* Microcode buffer is kept after initialization for error recovery. */
5297 static unsigned char _adv_asc38C0800_buf
[] = {
5298 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x18, 0xe4,
5299 0x01, 0x00, 0x48, 0xe4, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0xce, 0x19,
5300 0x00, 0xfa, 0xff, 0xff, 0x1c, 0x0f, 0x00, 0xf6, 0x9e, 0xe7, 0xff, 0x00,
5301 0x82, 0xe7, 0x00, 0xea, 0x01, 0xfa, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0,
5302 0x01, 0xf6, 0x03, 0x00, 0x04, 0x00, 0x10, 0x00, 0x1e, 0xf0, 0x85, 0xf0,
5303 0x18, 0xf4, 0x08, 0x00, 0xbc, 0x00, 0x38, 0x54, 0x00, 0xec, 0xd5, 0xf0,
5304 0x82, 0x0d, 0x00, 0xe6, 0x86, 0xf0, 0xb1, 0xf0, 0x98, 0x57, 0x01, 0xfc,
5305 0xb4, 0x00, 0xd4, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x3c, 0x00, 0xbb, 0x00,
5306 0x00, 0x10, 0xba, 0x19, 0x02, 0x80, 0x32, 0xf0, 0x7c, 0x0d, 0x02, 0x13,
5307 0xba, 0x13, 0x18, 0x40, 0x00, 0x57, 0x01, 0xea, 0x02, 0xfc, 0x03, 0xfc,
5308 0x3e, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x74, 0x01, 0x76, 0x01, 0xb9, 0x54,
5309 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
5310 0x3e, 0x01, 0x7a, 0x01, 0xca, 0x08, 0xce, 0x10, 0x16, 0x11, 0x04, 0x12,
5311 0x08, 0x12, 0x02, 0x4a, 0xbb, 0x55, 0x3c, 0x56, 0x03, 0x58, 0x1b, 0x80,
5312 0x30, 0xe4, 0x4b, 0xe4, 0x5d, 0xf0, 0x02, 0xfa, 0x20, 0x00, 0x32, 0x00,
5313 0x40, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
5314 0x70, 0x01, 0x72, 0x01, 0x78, 0x01, 0x7c, 0x01, 0x62, 0x0a, 0x86, 0x0d,
5315 0x06, 0x13, 0x4c, 0x1c, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0,
5316 0x03, 0xf7, 0x0c, 0x00, 0x0f, 0x00, 0x47, 0x00, 0xbe, 0x00, 0x00, 0x01,
5317 0x20, 0x11, 0x5c, 0x16, 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44,
5318 0x00, 0x4c, 0x04, 0xea, 0x5c, 0xf0, 0xa7, 0xf0, 0x04, 0xf6, 0x03, 0xfa,
5319 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01,
5320 0x4e, 0x01, 0x4a, 0x0b, 0x42, 0x0c, 0x12, 0x0f, 0x0c, 0x10, 0x22, 0x11,
5321 0x0a, 0x12, 0x04, 0x13, 0x30, 0x1c, 0x02, 0x48, 0x00, 0x4e, 0x42, 0x54,
5322 0x44, 0x55, 0xbd, 0x56, 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0,
5323 0x59, 0xf0, 0xb8, 0xf0, 0x4b, 0xf4, 0x06, 0xf7, 0x0e, 0xf7, 0x04, 0xfc,
5324 0x05, 0xfc, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00, 0xa4, 0x00,
5325 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, 0xe2, 0x03,
5326 0x08, 0x0f, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10, 0x0a, 0x13, 0x0c, 0x13,
5327 0x12, 0x13, 0x24, 0x14, 0x34, 0x14, 0x04, 0x16, 0x08, 0x16, 0xa4, 0x17,
5328 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44,
5329 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x3a, 0x55, 0x83, 0x55,
5330 0xe5, 0x55, 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0,
5331 0x0c, 0xf0, 0x04, 0xf8, 0x05, 0xf8, 0x07, 0x00, 0x0a, 0x00, 0x1c, 0x00,
5332 0x1e, 0x00, 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00,
5333 0x22, 0x01, 0x26, 0x01, 0x79, 0x01, 0x7e, 0x01, 0xc4, 0x01, 0xc6, 0x01,
5334 0x80, 0x02, 0x5e, 0x03, 0xee, 0x04, 0x9a, 0x06, 0xf8, 0x07, 0x62, 0x08,
5335 0x68, 0x08, 0x69, 0x08, 0xd6, 0x08, 0xe9, 0x09, 0xfa, 0x0b, 0x2e, 0x0f,
5336 0x12, 0x10, 0x1a, 0x10, 0xed, 0x10, 0xf1, 0x10, 0x2a, 0x11, 0x06, 0x12,
5337 0x0c, 0x12, 0x3e, 0x12, 0x10, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x46, 0x14,
5338 0x76, 0x14, 0x82, 0x14, 0x36, 0x15, 0xca, 0x15, 0x6b, 0x18, 0xbe, 0x18,
5339 0xca, 0x18, 0xe6, 0x19, 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40,
5340 0x0e, 0x47, 0xfe, 0x9c, 0xf0, 0x2b, 0x02, 0xfe, 0xac, 0x0d, 0xff, 0x10,
5341 0x00, 0x00, 0xd7, 0xfe, 0xe8, 0x19, 0x00, 0xd6, 0xfe, 0x84, 0x01, 0xff,
5342 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
5343 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x4c, 0x00, 0x5b, 0xff, 0x04, 0x00,
5344 0x00, 0x11, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
5345 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x11,
5346 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
5347 0xfe, 0x04, 0xf7, 0xd6, 0x2c, 0x99, 0x0a, 0x01, 0xfe, 0xc2, 0x0f, 0xfe,
5348 0x04, 0xf7, 0xd6, 0x99, 0x0a, 0x42, 0x2c, 0xfe, 0x3d, 0xf0, 0xfe, 0x06,
5349 0x02, 0xfe, 0x20, 0xf0, 0xa7, 0xfe, 0x91, 0xf0, 0xfe, 0xf4, 0x01, 0xfe,
5350 0x90, 0xf0, 0xfe, 0xf4, 0x01, 0xfe, 0x8f, 0xf0, 0xa7, 0x03, 0x5d, 0x4d,
5351 0x02, 0xfe, 0xc8, 0x0d, 0x01, 0xfe, 0x38, 0x0e, 0xfe, 0xdd, 0x12, 0xfe,
5352 0xfc, 0x10, 0xfe, 0x28, 0x1c, 0x03, 0xfe, 0xa6, 0x00, 0xfe, 0xd3, 0x12,
5353 0x41, 0x14, 0xfe, 0xa6, 0x00, 0xc2, 0xfe, 0x48, 0xf0, 0xfe, 0x8a, 0x02,
5354 0xfe, 0x49, 0xf0, 0xfe, 0xa4, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc2, 0x02,
5355 0xfe, 0x46, 0xf0, 0xfe, 0x54, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x5a, 0x02,
5356 0xfe, 0x43, 0xf0, 0xfe, 0x48, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x4c, 0x02,
5357 0xfe, 0x45, 0xf0, 0xfe, 0x50, 0x02, 0x18, 0x0a, 0xaa, 0x18, 0x06, 0x14,
5358 0xa1, 0x02, 0x2b, 0xfe, 0x00, 0x1c, 0xe7, 0xfe, 0x02, 0x1c, 0xe6, 0xfe,
5359 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0xfe, 0x18, 0x18, 0xfe, 0xe7, 0x10,
5360 0xfe, 0x06, 0xfc, 0xce, 0x09, 0x70, 0x01, 0xa8, 0x02, 0x2b, 0x15, 0x59,
5361 0x39, 0xa2, 0x01, 0xfe, 0x58, 0x10, 0x09, 0x70, 0x01, 0x87, 0xfe, 0xbd,
5362 0x10, 0x09, 0x70, 0x01, 0x87, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c, 0xfe,
5363 0x58, 0x1c, 0x18, 0x06, 0x14, 0xa1, 0x2c, 0x1c, 0x2b, 0xfe, 0x3d, 0xf0,
5364 0xfe, 0x06, 0x02, 0x23, 0xfe, 0x98, 0x02, 0xfe, 0x5a, 0x1c, 0xf8, 0xfe,
5365 0x14, 0x1c, 0x15, 0xfe, 0x30, 0x00, 0x39, 0xa2, 0x01, 0xfe, 0x48, 0x10,
5366 0x18, 0x06, 0x14, 0xa1, 0x02, 0xd7, 0x22, 0x20, 0x07, 0x11, 0x35, 0xfe,
5367 0x69, 0x10, 0x18, 0x06, 0x14, 0xa1, 0xfe, 0x04, 0xec, 0x20, 0x4f, 0x43,
5368 0x13, 0x20, 0xfe, 0x05, 0xf6, 0xce, 0x01, 0xfe, 0x4a, 0x17, 0x08, 0x54,
5369 0x58, 0x37, 0x12, 0x2f, 0x42, 0x92, 0x01, 0xfe, 0x82, 0x16, 0x02, 0x2b,
5370 0x09, 0x46, 0x01, 0x0e, 0x07, 0x00, 0x66, 0x01, 0x73, 0xfe, 0x18, 0x10,
5371 0xfe, 0x41, 0x58, 0x09, 0xa4, 0x01, 0x0e, 0xfe, 0xc8, 0x54, 0x6b, 0xfe,
5372 0x10, 0x03, 0x01, 0xfe, 0x82, 0x16, 0x02, 0x2b, 0x2c, 0x4f, 0xfe, 0x02,
5373 0xe8, 0x2a, 0xfe, 0xbf, 0x57, 0xfe, 0x9e, 0x43, 0xfe, 0x77, 0x57, 0xfe,
5374 0x27, 0xf0, 0xfe, 0xe0, 0x01, 0xfe, 0x07, 0x4b, 0xfe, 0x20, 0xf0, 0xa7,
5375 0xfe, 0x40, 0x1c, 0x1c, 0xd9, 0xfe, 0x26, 0xf0, 0xfe, 0x5a, 0x03, 0xfe,
5376 0xa0, 0xf0, 0xfe, 0x48, 0x03, 0xfe, 0x11, 0xf0, 0xa7, 0xfe, 0xef, 0x10,
5377 0xfe, 0x9f, 0xf0, 0xfe, 0x68, 0x03, 0xf9, 0x10, 0xfe, 0x11, 0x00, 0x02,
5378 0x65, 0x2c, 0xfe, 0x48, 0x1c, 0xf9, 0x08, 0x05, 0x1b, 0xfe, 0x18, 0x13,
5379 0x21, 0x22, 0xa3, 0xb7, 0x13, 0xa3, 0x09, 0x46, 0x01, 0x0e, 0xb7, 0x78,
5380 0x01, 0xfe, 0xb4, 0x16, 0x12, 0xd1, 0x1c, 0xd9, 0xfe, 0x01, 0xf0, 0xd9,
5381 0xfe, 0x82, 0xf0, 0xfe, 0x96, 0x03, 0xfa, 0x12, 0xfe, 0xe4, 0x00, 0x27,
5382 0xfe, 0xa8, 0x03, 0x1c, 0x34, 0x1d, 0xfe, 0xb8, 0x03, 0x01, 0x4b, 0xfe,
5383 0x06, 0xf0, 0xfe, 0xc8, 0x03, 0x95, 0x86, 0xfe, 0x0a, 0xf0, 0xfe, 0x8a,
5384 0x06, 0x02, 0x24, 0x03, 0x70, 0x28, 0x17, 0xfe, 0xfa, 0x04, 0x15, 0x6d,
5385 0x01, 0x36, 0x7b, 0xfe, 0x6a, 0x02, 0x02, 0xd8, 0xf9, 0x2c, 0x99, 0x19,
5386 0xfe, 0x67, 0x1b, 0xfe, 0xbf, 0x57, 0xfe, 0x77, 0x57, 0xfe, 0x48, 0x1c,
5387 0x74, 0x01, 0xaf, 0x8c, 0x09, 0x46, 0x01, 0x0e, 0x07, 0x00, 0x17, 0xda,
5388 0x09, 0xd1, 0x01, 0x0e, 0x8d, 0x51, 0x64, 0x79, 0x2a, 0x03, 0x70, 0x28,
5389 0xfe, 0x10, 0x12, 0x15, 0x6d, 0x01, 0x36, 0x7b, 0xfe, 0x6a, 0x02, 0x02,
5390 0xd8, 0xc7, 0x81, 0xc8, 0x83, 0x1c, 0x24, 0x27, 0xfe, 0x40, 0x04, 0x1d,
5391 0xfe, 0x3c, 0x04, 0x3b, 0xfe, 0xa0, 0x00, 0xfe, 0x9b, 0x57, 0xfe, 0x4e,
5392 0x12, 0x2d, 0xff, 0x02, 0x00, 0x10, 0x01, 0x0b, 0x1d, 0xfe, 0xe4, 0x04,
5393 0x2d, 0x01, 0x0b, 0x1d, 0x24, 0x33, 0x31, 0xde, 0xfe, 0x4c, 0x44, 0xfe,
5394 0x4c, 0x12, 0x51, 0xfe, 0x44, 0x48, 0x0f, 0x6f, 0xfe, 0x4c, 0x54, 0x6b,
5395 0xda, 0x4f, 0x79, 0x2a, 0xfe, 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x62,
5396 0x13, 0x08, 0x05, 0x1b, 0xfe, 0x2a, 0x13, 0x32, 0x07, 0x82, 0xfe, 0x52,
5397 0x13, 0xfe, 0x20, 0x10, 0x0f, 0x6f, 0xfe, 0x4c, 0x54, 0x6b, 0xda, 0xfe,
5398 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x40, 0x13, 0x08, 0x05, 0x1b, 0xfe,
5399 0x08, 0x13, 0x32, 0x07, 0x82, 0xfe, 0x30, 0x13, 0x08, 0x05, 0x1b, 0xfe,
5400 0x1c, 0x12, 0x15, 0x9d, 0x08, 0x05, 0x06, 0x4d, 0x15, 0xfe, 0x0d, 0x00,
5401 0x01, 0x36, 0x7b, 0xfe, 0x64, 0x0d, 0x02, 0x24, 0x2d, 0x12, 0xfe, 0xe6,
5402 0x00, 0xfe, 0x1c, 0x90, 0xfe, 0x40, 0x5c, 0x04, 0x15, 0x9d, 0x01, 0x36,
5403 0x02, 0x2b, 0xfe, 0x42, 0x5b, 0x99, 0x19, 0xfe, 0x46, 0x59, 0xfe, 0xbf,
5404 0x57, 0xfe, 0x77, 0x57, 0xfe, 0x87, 0x80, 0xfe, 0x31, 0xe4, 0x5b, 0x08,
5405 0x05, 0x0a, 0xfe, 0x84, 0x13, 0xfe, 0x20, 0x80, 0x07, 0x19, 0xfe, 0x7c,
5406 0x12, 0x53, 0x05, 0x06, 0xfe, 0x6c, 0x13, 0x03, 0xfe, 0xa2, 0x00, 0x28,
5407 0x17, 0xfe, 0x90, 0x05, 0xfe, 0x31, 0xe4, 0x5a, 0x53, 0x05, 0x0a, 0xfe,
5408 0x56, 0x13, 0x03, 0xfe, 0xa0, 0x00, 0x28, 0xfe, 0x4e, 0x12, 0x67, 0xff,
5409 0x02, 0x00, 0x10, 0x27, 0xfe, 0x48, 0x05, 0x1c, 0x34, 0xfe, 0x89, 0x48,
5410 0xff, 0x02, 0x00, 0x10, 0x27, 0xfe, 0x56, 0x05, 0x26, 0xfe, 0xa8, 0x05,
5411 0x12, 0xfe, 0xe3, 0x00, 0x21, 0x53, 0xfe, 0x4a, 0xf0, 0xfe, 0x76, 0x05,
5412 0xfe, 0x49, 0xf0, 0xfe, 0x70, 0x05, 0x88, 0x25, 0xfe, 0x21, 0x00, 0xab,
5413 0x25, 0xfe, 0x22, 0x00, 0xaa, 0x25, 0x58, 0xfe, 0x09, 0x48, 0xff, 0x02,
5414 0x00, 0x10, 0x27, 0xfe, 0x86, 0x05, 0x26, 0xfe, 0xa8, 0x05, 0xfe, 0xe2,
5415 0x08, 0x53, 0x05, 0xcb, 0x4d, 0x01, 0xb0, 0x25, 0x06, 0x13, 0xd3, 0x39,
5416 0xfe, 0x27, 0x01, 0x08, 0x05, 0x1b, 0xfe, 0x22, 0x12, 0x41, 0x01, 0xb2,
5417 0x15, 0x9d, 0x08, 0x05, 0x06, 0x4d, 0x15, 0xfe, 0x0d, 0x00, 0x01, 0x36,
5418 0x7b, 0xfe, 0x64, 0x0d, 0x02, 0x24, 0x03, 0xfe, 0x9c, 0x00, 0x28, 0xeb,
5419 0x03, 0x5c, 0x28, 0xfe, 0x36, 0x13, 0x41, 0x01, 0xb2, 0x26, 0xfe, 0x18,
5420 0x06, 0x09, 0x06, 0x53, 0x05, 0x1f, 0xfe, 0x02, 0x12, 0x50, 0x01, 0xfe,
5421 0x9e, 0x15, 0x1d, 0xfe, 0x0e, 0x06, 0x12, 0xa5, 0x01, 0x4b, 0x12, 0xfe,
5422 0xe5, 0x00, 0x03, 0x5c, 0xc1, 0x0c, 0x5c, 0x03, 0xcd, 0x28, 0xfe, 0x62,
5423 0x12, 0x03, 0x45, 0x28, 0xfe, 0x5a, 0x13, 0x01, 0xfe, 0x0c, 0x19, 0x01,
5424 0xfe, 0x76, 0x19, 0xfe, 0x43, 0x48, 0xc4, 0xcc, 0x0f, 0x71, 0xff, 0x02,
5425 0x00, 0x57, 0x52, 0x93, 0x1e, 0x43, 0x8b, 0xc4, 0x6e, 0x41, 0x01, 0xb2,
5426 0x26, 0xfe, 0x82, 0x06, 0x53, 0x05, 0x1a, 0xe9, 0x91, 0x09, 0x59, 0x01,
5427 0xfe, 0xcc, 0x15, 0x1d, 0xfe, 0x78, 0x06, 0x12, 0xa5, 0x01, 0x4b, 0x12,
5428 0xfe, 0xe5, 0x00, 0x03, 0x45, 0xc1, 0x0c, 0x45, 0x18, 0x06, 0x01, 0xb2,
5429 0xfa, 0x76, 0x74, 0x01, 0xaf, 0x8c, 0x12, 0xfe, 0xe2, 0x00, 0x27, 0xdb,
5430 0x1c, 0x34, 0xfe, 0x0a, 0xf0, 0xfe, 0xb6, 0x06, 0x94, 0xfe, 0x6c, 0x07,
5431 0xfe, 0x06, 0xf0, 0xfe, 0x74, 0x07, 0x95, 0x86, 0x02, 0x24, 0x08, 0x05,
5432 0x0a, 0xfe, 0x2e, 0x12, 0x16, 0x19, 0x01, 0x0b, 0x16, 0x00, 0x01, 0x0b,
5433 0x16, 0x00, 0x01, 0x0b, 0x16, 0x00, 0x01, 0x0b, 0xfe, 0x99, 0xa4, 0x01,
5434 0x0b, 0x16, 0x00, 0x02, 0xfe, 0x42, 0x08, 0x68, 0x05, 0x1a, 0xfe, 0x38,
5435 0x12, 0x08, 0x05, 0x1a, 0xfe, 0x30, 0x13, 0x16, 0xfe, 0x1b, 0x00, 0x01,
5436 0x0b, 0x16, 0x00, 0x01, 0x0b, 0x16, 0x00, 0x01, 0x0b, 0x16, 0x00, 0x01,
5437 0x0b, 0x16, 0x06, 0x01, 0x0b, 0x16, 0x00, 0x02, 0xe2, 0x6c, 0x58, 0xbe,
5438 0x50, 0xfe, 0x9a, 0x81, 0x55, 0x1b, 0x7a, 0xfe, 0x42, 0x07, 0x09, 0x1b,
5439 0xfe, 0x09, 0x6f, 0xba, 0xfe, 0xca, 0x45, 0xfe, 0x32, 0x12, 0x69, 0x6d,
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5736 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1a, 0xfe, 0x5a, 0xf0, 0xfe, 0x92, 0x19,
5737 0x25, 0xca, 0xfe, 0x26, 0x10, 0x07, 0x19, 0x66, 0x25, 0x6d, 0xe5, 0x07,
5738 0x0a, 0x66, 0x25, 0x9e, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x66, 0x25, 0x59,
5739 0xa9, 0xb8, 0x04, 0x15, 0xfe, 0x09, 0x00, 0x01, 0x36, 0xfe, 0x04, 0xfe,
5740 0x81, 0x03, 0x83, 0xfe, 0x40, 0x5c, 0x04, 0x1c, 0xf7, 0xfe, 0x14, 0xf0,
5741 0x0b, 0x27, 0xfe, 0xd6, 0x19, 0x1c, 0xf7, 0x7b, 0xf7, 0xfe, 0x82, 0xf0,
5742 0xfe, 0xda, 0x19, 0x04, 0xff, 0xcc, 0x00, 0x00,
5745 static unsigned short _adv_asc38C0800_size
= sizeof(_adv_asc38C0800_buf
); /* 0x14E1 */
5746 static ADV_DCNT _adv_asc38C0800_chksum
= 0x050D3FD8UL
; /* Expanded little-endian checksum. */
5748 /* Microcode buffer is kept after initialization for error recovery. */
5749 static unsigned char _adv_asc38C1600_buf
[] = {
5750 0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xfc, 0x00, 0x10, 0x00, 0xf0,
5751 0x18, 0xe4, 0x01, 0x00, 0x04, 0x1e, 0x48, 0xe4, 0x03, 0xf6, 0xf7, 0x13,
5752 0x2e, 0x1e, 0x02, 0x00, 0x07, 0x17, 0xc0, 0x5f, 0x00, 0xfa, 0xff, 0xff,
5753 0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7, 0x85, 0xf0, 0x86, 0xf0,
5754 0x4e, 0x10, 0x9e, 0xe7, 0xff, 0x00, 0x55, 0xf0, 0x01, 0xf6, 0x03, 0x00,
5755 0x98, 0x57, 0x01, 0xe6, 0x00, 0xea, 0x00, 0xec, 0x01, 0xfa, 0x18, 0xf4,
5756 0x08, 0x00, 0xf0, 0x1d, 0x38, 0x54, 0x32, 0xf0, 0x10, 0x00, 0xc2, 0x0e,
5757 0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4, 0x00, 0xe6, 0xb1, 0xf0,
5758 0xb4, 0x00, 0x02, 0x13, 0x3e, 0x1c, 0xc8, 0x47, 0x3e, 0x00, 0xd8, 0x01,
5759 0x06, 0x13, 0x0c, 0x1c, 0x5e, 0x1e, 0x00, 0x57, 0xc8, 0x57, 0x01, 0xfc,
5760 0xbc, 0x0e, 0xa2, 0x12, 0xb9, 0x54, 0x00, 0x80, 0x62, 0x0a, 0x5a, 0x12,
5761 0xc8, 0x15, 0x3e, 0x1e, 0x18, 0x40, 0xbd, 0x56, 0x03, 0xe6, 0x01, 0xea,
5762 0x5c, 0xf0, 0x0f, 0x00, 0x20, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
5763 0x04, 0x13, 0xbb, 0x55, 0x3c, 0x56, 0x3e, 0x57, 0x03, 0x58, 0x4a, 0xe4,
5764 0x40, 0x00, 0xb6, 0x00, 0xbb, 0x00, 0xc0, 0x00, 0x00, 0x01, 0x01, 0x01,
5765 0x3e, 0x01, 0x58, 0x0a, 0x44, 0x10, 0x0a, 0x12, 0x4c, 0x1c, 0x4e, 0x1c,
5766 0x02, 0x4a, 0x30, 0xe4, 0x05, 0xe6, 0x0c, 0x00, 0x3c, 0x00, 0x80, 0x00,
5767 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01,
5768 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x7c, 0x01, 0xc6, 0x0e, 0x0c, 0x10,
5769 0xac, 0x12, 0xae, 0x12, 0x16, 0x1a, 0x32, 0x1c, 0x6e, 0x1e, 0x02, 0x48,
5770 0x3a, 0x55, 0xc9, 0x57, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x06, 0xf7,
5771 0x03, 0xfc, 0x06, 0x00, 0x1e, 0x00, 0xbe, 0x00, 0xe1, 0x00, 0x0c, 0x12,
5772 0x18, 0x1a, 0x70, 0x1a, 0x30, 0x1c, 0x38, 0x1c, 0x10, 0x44, 0x00, 0x4c,
5773 0xb0, 0x57, 0x40, 0x5c, 0x4d, 0xe4, 0x04, 0xea, 0x5d, 0xf0, 0xa7, 0xf0,
5774 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x09, 0x00, 0x19, 0x00, 0x32, 0x00,
5775 0x33, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0x9e, 0x00, 0xcc, 0x00,
5776 0x20, 0x01, 0x4e, 0x01, 0x79, 0x01, 0x3c, 0x09, 0x68, 0x0d, 0x02, 0x10,
5777 0x04, 0x10, 0x3a, 0x10, 0x08, 0x12, 0x0a, 0x13, 0x40, 0x16, 0x50, 0x16,
5778 0x00, 0x17, 0x4a, 0x19, 0x00, 0x4e, 0x00, 0x54, 0x01, 0x58, 0x00, 0xdc,
5779 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xb8, 0xf0, 0x48, 0xf4, 0x0e, 0xf7,
5780 0x0a, 0x00, 0x9b, 0x00, 0x9c, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00,
5781 0xd0, 0x00, 0xe7, 0x00, 0xf0, 0x03, 0x69, 0x08, 0xe9, 0x09, 0x5c, 0x0c,
5782 0xb6, 0x12, 0xbc, 0x19, 0xd8, 0x1b, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c,
5783 0x42, 0x1d, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46,
5784 0x89, 0x48, 0x68, 0x54, 0x83, 0x55, 0x83, 0x59, 0x31, 0xe4, 0x02, 0xe6,
5785 0x07, 0xf0, 0x08, 0xf0, 0x0b, 0xf0, 0x0c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8,
5786 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa, 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00,
5787 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0xe5, 0x00, 0x22, 0x01,
5788 0x26, 0x01, 0x60, 0x01, 0x7a, 0x01, 0x82, 0x01, 0xc8, 0x01, 0xca, 0x01,
5789 0x86, 0x02, 0x6a, 0x03, 0x18, 0x05, 0xb2, 0x07, 0x68, 0x08, 0x10, 0x0d,
5790 0x06, 0x10, 0x0a, 0x10, 0x0e, 0x10, 0x12, 0x10, 0x60, 0x10, 0xed, 0x10,
5791 0xf3, 0x10, 0x06, 0x12, 0x10, 0x12, 0x1e, 0x12, 0x0c, 0x13, 0x0e, 0x13,
5792 0x10, 0x13, 0xfe, 0x9c, 0xf0, 0x35, 0x05, 0xfe, 0xec, 0x0e, 0xff, 0x10,
5793 0x00, 0x00, 0xe9, 0xfe, 0x34, 0x1f, 0x00, 0xe8, 0xfe, 0x88, 0x01, 0xff,
5794 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
5795 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x4c, 0x00, 0x65, 0xff, 0x04, 0x00,
5796 0x00, 0x1a, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
5797 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x13,
5798 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
5799 0xfe, 0x04, 0xf7, 0xe8, 0x37, 0x7d, 0x0d, 0x01, 0xfe, 0x4a, 0x11, 0xfe,
5800 0x04, 0xf7, 0xe8, 0x7d, 0x0d, 0x51, 0x37, 0xfe, 0x3d, 0xf0, 0xfe, 0x0c,
5801 0x02, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x91, 0xf0, 0xfe, 0xf8, 0x01, 0xfe,
5802 0x90, 0xf0, 0xfe, 0xf8, 0x01, 0xfe, 0x8f, 0xf0, 0xbc, 0x03, 0x67, 0x4d,
5803 0x05, 0xfe, 0x08, 0x0f, 0x01, 0xfe, 0x78, 0x0f, 0xfe, 0xdd, 0x12, 0x05,
5804 0xfe, 0x0e, 0x03, 0xfe, 0x28, 0x1c, 0x03, 0xfe, 0xa6, 0x00, 0xfe, 0xd1,
5805 0x12, 0x3e, 0x22, 0xfe, 0xa6, 0x00, 0xac, 0xfe, 0x48, 0xf0, 0xfe, 0x90,
5806 0x02, 0xfe, 0x49, 0xf0, 0xfe, 0xaa, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc8,
5807 0x02, 0xfe, 0x46, 0xf0, 0xfe, 0x5a, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x60,
5808 0x02, 0xfe, 0x43, 0xf0, 0xfe, 0x4e, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x52,
5809 0x02, 0xfe, 0x45, 0xf0, 0xfe, 0x56, 0x02, 0x1c, 0x0d, 0xa2, 0x1c, 0x07,
5810 0x22, 0xb7, 0x05, 0x35, 0xfe, 0x00, 0x1c, 0xfe, 0xf1, 0x10, 0xfe, 0x02,
5811 0x1c, 0xf5, 0xfe, 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0x5f, 0xfe, 0xe7,
5812 0x10, 0xfe, 0x06, 0xfc, 0xde, 0x0a, 0x81, 0x01, 0xa3, 0x05, 0x35, 0x1f,
5813 0x95, 0x47, 0xb8, 0x01, 0xfe, 0xe4, 0x11, 0x0a, 0x81, 0x01, 0x5c, 0xfe,
5814 0xbd, 0x10, 0x0a, 0x81, 0x01, 0x5c, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c,
5815 0xfe, 0x58, 0x1c, 0x1c, 0x07, 0x22, 0xb7, 0x37, 0x2a, 0x35, 0xfe, 0x3d,
5816 0xf0, 0xfe, 0x0c, 0x02, 0x2b, 0xfe, 0x9e, 0x02, 0xfe, 0x5a, 0x1c, 0xfe,
5817 0x12, 0x1c, 0xfe, 0x14, 0x1c, 0x1f, 0xfe, 0x30, 0x00, 0x47, 0xb8, 0x01,
5818 0xfe, 0xd4, 0x11, 0x1c, 0x07, 0x22, 0xb7, 0x05, 0xe9, 0x21, 0x2c, 0x09,
5819 0x1a, 0x31, 0xfe, 0x69, 0x10, 0x1c, 0x07, 0x22, 0xb7, 0xfe, 0x04, 0xec,
5820 0x2c, 0x60, 0x01, 0xfe, 0x1e, 0x1e, 0x20, 0x2c, 0xfe, 0x05, 0xf6, 0xde,
5821 0x01, 0xfe, 0x62, 0x1b, 0x01, 0x0c, 0x61, 0x4a, 0x44, 0x15, 0x56, 0x51,
5822 0x01, 0xfe, 0x9e, 0x1e, 0x01, 0xfe, 0x96, 0x1a, 0x05, 0x35, 0x0a, 0x57,
5823 0x01, 0x18, 0x09, 0x00, 0x36, 0x01, 0x85, 0xfe, 0x18, 0x10, 0xfe, 0x41,
5824 0x58, 0x0a, 0xba, 0x01, 0x18, 0xfe, 0xc8, 0x54, 0x7b, 0xfe, 0x1c, 0x03,
5825 0x01, 0xfe, 0x96, 0x1a, 0x05, 0x35, 0x37, 0x60, 0xfe, 0x02, 0xe8, 0x30,
5826 0xfe, 0xbf, 0x57, 0xfe, 0x9e, 0x43, 0xfe, 0x77, 0x57, 0xfe, 0x27, 0xf0,
5827 0xfe, 0xe4, 0x01, 0xfe, 0x07, 0x4b, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x40,
5828 0x1c, 0x2a, 0xeb, 0xfe, 0x26, 0xf0, 0xfe, 0x66, 0x03, 0xfe, 0xa0, 0xf0,
5829 0xfe, 0x54, 0x03, 0xfe, 0x11, 0xf0, 0xbc, 0xfe, 0xef, 0x10, 0xfe, 0x9f,
5830 0xf0, 0xfe, 0x74, 0x03, 0xfe, 0x46, 0x1c, 0x19, 0xfe, 0x11, 0x00, 0x05,
5831 0x70, 0x37, 0xfe, 0x48, 0x1c, 0xfe, 0x46, 0x1c, 0x01, 0x0c, 0x06, 0x28,
5832 0xfe, 0x18, 0x13, 0x26, 0x21, 0xb9, 0xc7, 0x20, 0xb9, 0x0a, 0x57, 0x01,
5833 0x18, 0xc7, 0x89, 0x01, 0xfe, 0xc8, 0x1a, 0x15, 0xe1, 0x2a, 0xeb, 0xfe,
5834 0x01, 0xf0, 0xeb, 0xfe, 0x82, 0xf0, 0xfe, 0xa4, 0x03, 0xfe, 0x9c, 0x32,
5835 0x15, 0xfe, 0xe4, 0x00, 0x2f, 0xfe, 0xb6, 0x03, 0x2a, 0x3c, 0x16, 0xfe,
5836 0xc6, 0x03, 0x01, 0x41, 0xfe, 0x06, 0xf0, 0xfe, 0xd6, 0x03, 0xaf, 0xa0,
5837 0xfe, 0x0a, 0xf0, 0xfe, 0xa2, 0x07, 0x05, 0x29, 0x03, 0x81, 0x1e, 0x1b,
5838 0xfe, 0x24, 0x05, 0x1f, 0x63, 0x01, 0x42, 0x8f, 0xfe, 0x70, 0x02, 0x05,
5839 0xea, 0xfe, 0x46, 0x1c, 0x37, 0x7d, 0x1d, 0xfe, 0x67, 0x1b, 0xfe, 0xbf,
5840 0x57, 0xfe, 0x77, 0x57, 0xfe, 0x48, 0x1c, 0x75, 0x01, 0xa6, 0x86, 0x0a,
5841 0x57, 0x01, 0x18, 0x09, 0x00, 0x1b, 0xec, 0x0a, 0xe1, 0x01, 0x18, 0x77,
5842 0x50, 0x40, 0x8d, 0x30, 0x03, 0x81, 0x1e, 0xf8, 0x1f, 0x63, 0x01, 0x42,
5843 0x8f, 0xfe, 0x70, 0x02, 0x05, 0xea, 0xd7, 0x99, 0xd8, 0x9c, 0x2a, 0x29,
5844 0x2f, 0xfe, 0x4e, 0x04, 0x16, 0xfe, 0x4a, 0x04, 0x7e, 0xfe, 0xa0, 0x00,
5845 0xfe, 0x9b, 0x57, 0xfe, 0x54, 0x12, 0x32, 0xff, 0x02, 0x00, 0x10, 0x01,
5846 0x08, 0x16, 0xfe, 0x02, 0x05, 0x32, 0x01, 0x08, 0x16, 0x29, 0x27, 0x25,
5847 0xee, 0xfe, 0x4c, 0x44, 0xfe, 0x58, 0x12, 0x50, 0xfe, 0x44, 0x48, 0x13,
5848 0x34, 0xfe, 0x4c, 0x54, 0x7b, 0xec, 0x60, 0x8d, 0x30, 0x01, 0xfe, 0x4e,
5849 0x1e, 0xfe, 0x48, 0x47, 0xfe, 0x7c, 0x13, 0x01, 0x0c, 0x06, 0x28, 0xfe,
5850 0x32, 0x13, 0x01, 0x43, 0x09, 0x9b, 0xfe, 0x68, 0x13, 0xfe, 0x26, 0x10,
5851 0x13, 0x34, 0xfe, 0x4c, 0x54, 0x7b, 0xec, 0x01, 0xfe, 0x4e, 0x1e, 0xfe,
5852 0x48, 0x47, 0xfe, 0x54, 0x13, 0x01, 0x0c, 0x06, 0x28, 0xa5, 0x01, 0x43,
5853 0x09, 0x9b, 0xfe, 0x40, 0x13, 0x01, 0x0c, 0x06, 0x28, 0xf9, 0x1f, 0x7f,
5854 0x01, 0x0c, 0x06, 0x07, 0x4d, 0x1f, 0xfe, 0x0d, 0x00, 0x01, 0x42, 0x8f,
5855 0xfe, 0xa4, 0x0e, 0x05, 0x29, 0x32, 0x15, 0xfe, 0xe6, 0x00, 0x0f, 0xfe,
5856 0x1c, 0x90, 0x04, 0xfe, 0x9c, 0x93, 0x3a, 0x0b, 0x0e, 0x8b, 0x02, 0x1f,
5857 0x7f, 0x01, 0x42, 0x05, 0x35, 0xfe, 0x42, 0x5b, 0x7d, 0x1d, 0xfe, 0x46,
5858 0x59, 0xfe, 0xbf, 0x57, 0xfe, 0x77, 0x57, 0x0f, 0xfe, 0x87, 0x80, 0x04,
5859 0xfe, 0x87, 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0xd0, 0x65, 0x01, 0x0c,
5860 0x06, 0x0d, 0xfe, 0x98, 0x13, 0x0f, 0xfe, 0x20, 0x80, 0x04, 0xfe, 0xa0,
5861 0x83, 0x33, 0x0b, 0x0e, 0x09, 0x1d, 0xfe, 0x84, 0x12, 0x01, 0x38, 0x06,
5862 0x07, 0xfe, 0x70, 0x13, 0x03, 0xfe, 0xa2, 0x00, 0x1e, 0x1b, 0xfe, 0xda,
5863 0x05, 0xd0, 0x54, 0x01, 0x38, 0x06, 0x0d, 0xfe, 0x58, 0x13, 0x03, 0xfe,
5864 0xa0, 0x00, 0x1e, 0xfe, 0x50, 0x12, 0x5e, 0xff, 0x02, 0x00, 0x10, 0x2f,
5865 0xfe, 0x90, 0x05, 0x2a, 0x3c, 0xcc, 0xff, 0x02, 0x00, 0x10, 0x2f, 0xfe,
5866 0x9e, 0x05, 0x17, 0xfe, 0xf4, 0x05, 0x15, 0xfe, 0xe3, 0x00, 0x26, 0x01,
5867 0x38, 0xfe, 0x4a, 0xf0, 0xfe, 0xc0, 0x05, 0xfe, 0x49, 0xf0, 0xfe, 0xba,
5868 0x05, 0x71, 0x2e, 0xfe, 0x21, 0x00, 0xf1, 0x2e, 0xfe, 0x22, 0x00, 0xa2,
5869 0x2e, 0x4a, 0xfe, 0x09, 0x48, 0xff, 0x02, 0x00, 0x10, 0x2f, 0xfe, 0xd0,
5870 0x05, 0x17, 0xfe, 0xf4, 0x05, 0xfe, 0xe2, 0x08, 0x01, 0x38, 0x06, 0xfe,
5871 0x1c, 0x00, 0x4d, 0x01, 0xa7, 0x2e, 0x07, 0x20, 0xe4, 0x47, 0xfe, 0x27,
5872 0x01, 0x01, 0x0c, 0x06, 0x28, 0xfe, 0x24, 0x12, 0x3e, 0x01, 0x84, 0x1f,
5873 0x7f, 0x01, 0x0c, 0x06, 0x07, 0x4d, 0x1f, 0xfe, 0x0d, 0x00, 0x01, 0x42,
5874 0x8f, 0xfe, 0xa4, 0x0e, 0x05, 0x29, 0x03, 0xe6, 0x1e, 0xfe, 0xca, 0x13,
5875 0x03, 0xb6, 0x1e, 0xfe, 0x40, 0x12, 0x03, 0x66, 0x1e, 0xfe, 0x38, 0x13,
5876 0x3e, 0x01, 0x84, 0x17, 0xfe, 0x72, 0x06, 0x0a, 0x07, 0x01, 0x38, 0x06,
5877 0x24, 0xfe, 0x02, 0x12, 0x4f, 0x01, 0xfe, 0x56, 0x19, 0x16, 0xfe, 0x68,
5878 0x06, 0x15, 0x82, 0x01, 0x41, 0x15, 0xe2, 0x03, 0x66, 0x8a, 0x10, 0x66,
5879 0x03, 0x9a, 0x1e, 0xfe, 0x70, 0x12, 0x03, 0x55, 0x1e, 0xfe, 0x68, 0x13,
5880 0x01, 0xc6, 0x09, 0x12, 0x48, 0xfe, 0x92, 0x06, 0x2e, 0x12, 0x01, 0xfe,
5881 0xac, 0x1d, 0xfe, 0x43, 0x48, 0x62, 0x80, 0x13, 0x58, 0xff, 0x02, 0x00,
5882 0x57, 0x52, 0xad, 0x23, 0x3f, 0x4e, 0x62, 0x49, 0x3e, 0x01, 0x84, 0x17,
5883 0xfe, 0xea, 0x06, 0x01, 0x38, 0x06, 0x12, 0xf7, 0x45, 0x0a, 0x95, 0x01,
5884 0xfe, 0x84, 0x19, 0x16, 0xfe, 0xe0, 0x06, 0x15, 0x82, 0x01, 0x41, 0x15,
5885 0xe2, 0x03, 0x55, 0x8a, 0x10, 0x55, 0x1c, 0x07, 0x01, 0x84, 0xfe, 0xae,
5886 0x10, 0x03, 0x6f, 0x1e, 0xfe, 0x9e, 0x13, 0x3e, 0x01, 0x84, 0x03, 0x9a,
5887 0x1e, 0xfe, 0x1a, 0x12, 0x01, 0x38, 0x06, 0x12, 0xfc, 0x01, 0xc6, 0x01,
5888 0xfe, 0xac, 0x1d, 0xfe, 0x43, 0x48, 0x62, 0x80, 0xf0, 0x45, 0x0a, 0x95,
5889 0x03, 0xb6, 0x1e, 0xf8, 0x01, 0x38, 0x06, 0x24, 0x36, 0xfe, 0x02, 0xf6,
5890 0x07, 0x71, 0x78, 0x8c, 0x00, 0x4d, 0x62, 0x49, 0x3e, 0x2d, 0x93, 0x4e,
5891 0xd0, 0x0d, 0x17, 0xfe, 0x9a, 0x07, 0x01, 0xfe, 0xc0, 0x19, 0x16, 0xfe,
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6187 0x08, 0x02, 0x50, 0x02, 0x14, 0x07, 0x01, 0x08, 0x17, 0x74, 0x14, 0x7f,
6188 0x01, 0x08, 0x17, 0x74, 0x14, 0x12, 0x01, 0x08, 0x17, 0x74, 0xfe, 0x89,
6189 0x49, 0x01, 0x08, 0x17, 0x74, 0x14, 0x00, 0x01, 0x08, 0x17, 0x74, 0xfe,
6190 0x89, 0x4a, 0x01, 0x08, 0x17, 0x74, 0xfe, 0x09, 0x49, 0x01, 0x08, 0x17,
6191 0x74, 0x5f, 0xcc, 0x01, 0x08, 0x02, 0x21, 0xe4, 0x09, 0x07, 0xfe, 0x4c,
6192 0x13, 0xc8, 0x20, 0xe4, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x5f, 0xa1, 0x5e,
6193 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xcc, 0xff, 0x02, 0x00, 0x10, 0x2f,
6194 0xfe, 0x3e, 0x1a, 0x01, 0x43, 0x09, 0xfe, 0xe3, 0x00, 0xfe, 0x22, 0x13,
6195 0x16, 0xfe, 0x64, 0x1a, 0x26, 0x20, 0x9e, 0x01, 0x41, 0x21, 0x9e, 0x09,
6196 0x07, 0x5d, 0x01, 0x0c, 0x61, 0x07, 0x44, 0x02, 0x0a, 0x5a, 0x01, 0x18,
6197 0xfe, 0x00, 0x40, 0xaa, 0x09, 0x1a, 0xfe, 0x12, 0x13, 0x0a, 0x9d, 0x01,
6198 0x18, 0xaa, 0x0a, 0x67, 0x01, 0xa3, 0x02, 0x0a, 0x9d, 0x01, 0x18, 0xaa,
6199 0xfe, 0x80, 0xe7, 0x1a, 0x09, 0x1a, 0x5d, 0xfe, 0x45, 0x58, 0x01, 0xfe,
6200 0xb2, 0x16, 0xaa, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0xaa, 0x0a, 0x67, 0x01,
6201 0xa3, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x01, 0xfe, 0x7e, 0x1e, 0xfe, 0x80,
6202 0x4c, 0xfe, 0x49, 0xe4, 0x1a, 0xfe, 0x12, 0x13, 0x0a, 0x9d, 0x01, 0x18,
6203 0xfe, 0x80, 0x4c, 0x0a, 0x67, 0x01, 0x5c, 0x02, 0x1c, 0x1a, 0x87, 0x7c,
6204 0xe5, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24, 0x1c, 0xfe, 0x1d,
6205 0xf7, 0x28, 0xb1, 0xfe, 0x04, 0x1b, 0x01, 0xfe, 0x2a, 0x1c, 0xfa, 0xb3,
6206 0x28, 0x7c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x02, 0xc9, 0x2b, 0xfe,
6207 0xf4, 0x1a, 0xfe, 0xfa, 0x10, 0x1c, 0x1a, 0x87, 0x03, 0xfe, 0x64, 0x01,
6208 0xfe, 0x00, 0xf4, 0x24, 0xfe, 0x18, 0x58, 0x03, 0xfe, 0x66, 0x01, 0xfe,
6209 0x19, 0x58, 0xb3, 0x24, 0x01, 0xfe, 0x0e, 0x1f, 0xfe, 0x30, 0xf4, 0x07,
6210 0xfe, 0x3c, 0x50, 0x7c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79, 0xfe, 0x1c,
6211 0xf7, 0x24, 0xb1, 0xfe, 0x50, 0x1b, 0xfe, 0xd4, 0x14, 0x31, 0x02, 0xc9,
6212 0x2b, 0xfe, 0x26, 0x1b, 0xfe, 0xba, 0x10, 0x1c, 0x1a, 0x87, 0xfe, 0x83,
6213 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, 0x54, 0xb1,
6214 0xfe, 0x72, 0x1b, 0xfe, 0xb2, 0x14, 0xfc, 0xb3, 0x54, 0x7c, 0x12, 0xfe,
6215 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0x02, 0xc9, 0x2b, 0xfe, 0x66, 0x1b,
6216 0xfe, 0x8a, 0x10, 0x1c, 0x1a, 0x87, 0x8b, 0x0f, 0xfe, 0x30, 0x90, 0x04,
6217 0xfe, 0xb0, 0x93, 0x3a, 0x0b, 0xfe, 0x18, 0x58, 0xfe, 0x32, 0x90, 0x04,
6218 0xfe, 0xb2, 0x93, 0x3a, 0x0b, 0xfe, 0x19, 0x58, 0x0e, 0xa8, 0xb3, 0x4a,
6219 0x7c, 0x12, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x4a, 0xb1, 0xfe, 0xc6,
6220 0x1b, 0xfe, 0x5e, 0x14, 0x31, 0x02, 0xc9, 0x2b, 0xfe, 0x96, 0x1b, 0x5c,
6221 0xfe, 0x02, 0xf6, 0x1a, 0x87, 0xfe, 0x18, 0xfe, 0x6a, 0xfe, 0x19, 0xfe,
6222 0x6b, 0x01, 0xfe, 0x1e, 0x1f, 0xfe, 0x1d, 0xf7, 0x65, 0xb1, 0xfe, 0xee,
6223 0x1b, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13, 0xb3, 0x65, 0x3e, 0xfe, 0x83,
6224 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x1a, 0xfe, 0x81, 0xe7, 0x1a,
6225 0x15, 0xfe, 0xdd, 0x00, 0x7a, 0x30, 0x02, 0x7a, 0x30, 0xfe, 0x12, 0x45,
6226 0x2b, 0xfe, 0xdc, 0x1b, 0x1f, 0x07, 0x47, 0xb5, 0xc3, 0x05, 0x35, 0xfe,
6227 0x39, 0xf0, 0x75, 0x26, 0x02, 0xfe, 0x7e, 0x18, 0x23, 0x1d, 0x36, 0x13,
6228 0x11, 0x02, 0x87, 0x03, 0xe3, 0x23, 0x07, 0xfe, 0xef, 0x12, 0xfe, 0xe1,
6229 0x10, 0x90, 0x34, 0x60, 0xfe, 0x02, 0x80, 0x09, 0x56, 0xfe, 0x3c, 0x13,
6230 0xfe, 0x82, 0x14, 0xfe, 0x42, 0x13, 0x51, 0xfe, 0x06, 0x83, 0x0a, 0x5a,
6231 0x01, 0x18, 0xcb, 0xfe, 0x3e, 0x12, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48,
6232 0x01, 0xfe, 0xb2, 0x16, 0xfe, 0x00, 0xcc, 0xcb, 0xfe, 0xf3, 0x13, 0x3f,
6233 0x89, 0x09, 0x1a, 0xa5, 0x0a, 0x9d, 0x01, 0x18, 0xfe, 0x80, 0x4c, 0x01,
6234 0x85, 0xfe, 0x16, 0x10, 0x09, 0x9b, 0x4e, 0xfe, 0x40, 0x14, 0xfe, 0x24,
6235 0x12, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x52, 0x1c, 0x1c, 0x0d,
6236 0x02, 0xfe, 0x9c, 0xe7, 0x0d, 0x19, 0xfe, 0x15, 0x00, 0x40, 0x8d, 0x30,
6237 0x01, 0xf4, 0x1c, 0x07, 0x02, 0x51, 0xfe, 0x06, 0x83, 0xfe, 0x18, 0x80,
6238 0x61, 0x28, 0x44, 0x15, 0x56, 0x01, 0x85, 0x1c, 0x07, 0x02, 0xfe, 0x38,
6239 0x90, 0xfe, 0xba, 0x90, 0x91, 0xde, 0x7e, 0xdf, 0xfe, 0x48, 0x55, 0x31,
6240 0xfe, 0xc9, 0x55, 0x02, 0x21, 0xb9, 0x88, 0x20, 0xb9, 0x02, 0x0a, 0xba,
6241 0x01, 0x18, 0xfe, 0x41, 0x48, 0x0a, 0x57, 0x01, 0x18, 0xfe, 0x49, 0x44,
6242 0x1b, 0xfe, 0x1e, 0x1d, 0x88, 0x89, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x09,
6243 0x1a, 0xa4, 0x0a, 0x67, 0x01, 0xa3, 0x0a, 0x57, 0x01, 0x18, 0x88, 0x89,
6244 0x02, 0xfe, 0x4e, 0xe4, 0x1d, 0x7b, 0xfe, 0x52, 0x1d, 0x03, 0xfe, 0x90,
6245 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xfe, 0x4e, 0xe4, 0xdd, 0x7b,
6246 0xfe, 0x64, 0x1d, 0x03, 0xfe, 0x92, 0x00, 0xd1, 0x12, 0xfe, 0x1a, 0x10,
6247 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x7b, 0xfe, 0x76, 0x1d, 0x03, 0xfe,
6248 0x94, 0x00, 0xd1, 0x24, 0xfe, 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xd1,
6249 0x63, 0xfe, 0x4e, 0x45, 0x83, 0xca, 0xff, 0x04, 0x68, 0x54, 0xfe, 0xf1,
6250 0x10, 0x23, 0x49, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c,
6251 0xfe, 0x1a, 0xf4, 0xfe, 0x00, 0x04, 0x83, 0xb2, 0x1d, 0x48, 0xfe, 0xaa,
6252 0x1d, 0x13, 0x1d, 0x02, 0x09, 0x92, 0xfe, 0x5a, 0xf0, 0xfe, 0xba, 0x1d,
6253 0x2e, 0x93, 0xfe, 0x34, 0x10, 0x09, 0x12, 0xfe, 0x5a, 0xf0, 0xfe, 0xc8,
6254 0x1d, 0x2e, 0xb4, 0xfe, 0x26, 0x10, 0x09, 0x1d, 0x36, 0x2e, 0x63, 0xfe,
6255 0x1a, 0x10, 0x09, 0x0d, 0x36, 0x2e, 0x94, 0xf2, 0x09, 0x07, 0x36, 0x2e,
6256 0x95, 0xa1, 0xc8, 0x02, 0x1f, 0x93, 0x01, 0x42, 0xfe, 0x04, 0xfe, 0x99,
6257 0x03, 0x9c, 0x8b, 0x02, 0x2a, 0xfe, 0x1c, 0x1e, 0xfe, 0x14, 0xf0, 0x08,
6258 0x2f, 0xfe, 0x0c, 0x1e, 0x2a, 0xfe, 0x1c, 0x1e, 0x8f, 0xfe, 0x1c, 0x1e,
6259 0xfe, 0x82, 0xf0, 0xfe, 0x10, 0x1e, 0x02, 0x0f, 0x3f, 0x04, 0xfe, 0x80,
6260 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x18, 0x80, 0x04, 0xfe, 0x98,
6261 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x02, 0x80, 0x04, 0xfe, 0x82,
6262 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x80, 0x04, 0xfe, 0x86,
6263 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x1b, 0x80, 0x04, 0xfe, 0x9b,
6264 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x04, 0x80, 0x04, 0xfe, 0x84,
6265 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x80, 0x80, 0x04, 0xfe, 0x80,
6266 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x19, 0x81, 0x04,
6267 0xfe, 0x99, 0x83, 0xfe, 0xca, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06,
6268 0x83, 0x04, 0xfe, 0x86, 0x83, 0xfe, 0xce, 0x47, 0x0b, 0x0e, 0x02, 0x0f,
6269 0xfe, 0x2c, 0x90, 0x04, 0xfe, 0xac, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6270 0xfe, 0xae, 0x90, 0x04, 0xfe, 0xae, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6271 0xfe, 0x08, 0x90, 0x04, 0xfe, 0x88, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6272 0xfe, 0x8a, 0x90, 0x04, 0xfe, 0x8a, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6273 0xfe, 0x0c, 0x90, 0x04, 0xfe, 0x8c, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6274 0xfe, 0x8e, 0x90, 0x04, 0xfe, 0x8e, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6275 0xfe, 0x3c, 0x90, 0x04, 0xfe, 0xbc, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x8b,
6276 0x0f, 0xfe, 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83, 0x33, 0x0b, 0x77, 0x0e,
6277 0xa8, 0x02, 0xff, 0x66, 0x00, 0x00,
6280 static unsigned short _adv_asc38C1600_size
= sizeof(_adv_asc38C1600_buf
); /* 0x1673 */
6281 static ADV_DCNT _adv_asc38C1600_chksum
= 0x0604EF77UL
; /* Expanded little-endian checksum. */
6283 static void AscInitQLinkVar(ASC_DVC_VAR
*asc_dvc
)
6289 iop_base
= asc_dvc
->iop_base
;
6290 AscPutRiscVarFreeQHead(iop_base
, 1);
6291 AscPutRiscVarDoneQTail(iop_base
, asc_dvc
->max_total_qng
);
6292 AscPutVarFreeQHead(iop_base
, 1);
6293 AscPutVarDoneQTail(iop_base
, asc_dvc
->max_total_qng
);
6294 AscWriteLramByte(iop_base
, ASCV_BUSY_QHEAD_B
,
6295 (uchar
)((int)asc_dvc
->max_total_qng
+ 1));
6296 AscWriteLramByte(iop_base
, ASCV_DISC1_QHEAD_B
,
6297 (uchar
)((int)asc_dvc
->max_total_qng
+ 2));
6298 AscWriteLramByte(iop_base
, (ushort
)ASCV_TOTAL_READY_Q_B
,
6299 asc_dvc
->max_total_qng
);
6300 AscWriteLramWord(iop_base
, ASCV_ASCDVC_ERR_CODE_W
, 0);
6301 AscWriteLramWord(iop_base
, ASCV_HALTCODE_W
, 0);
6302 AscWriteLramByte(iop_base
, ASCV_STOP_CODE_B
, 0);
6303 AscWriteLramByte(iop_base
, ASCV_SCSIBUSY_B
, 0);
6304 AscWriteLramByte(iop_base
, ASCV_WTM_FLAG_B
, 0);
6305 AscPutQDoneInProgress(iop_base
, 0);
6306 lram_addr
= ASC_QADR_BEG
;
6307 for (i
= 0; i
< 32; i
++, lram_addr
+= 2) {
6308 AscWriteLramWord(iop_base
, lram_addr
, 0);
6312 static ushort
AscInitMicroCodeVar(ASC_DVC_VAR
*asc_dvc
)
6320 iop_base
= asc_dvc
->iop_base
;
6322 for (i
= 0; i
<= ASC_MAX_TID
; i
++) {
6323 AscPutMCodeInitSDTRAtID(iop_base
, i
,
6324 asc_dvc
->cfg
->sdtr_period_offset
[i
]);
6327 AscInitQLinkVar(asc_dvc
);
6328 AscWriteLramByte(iop_base
, ASCV_DISC_ENABLE_B
,
6329 asc_dvc
->cfg
->disc_enable
);
6330 AscWriteLramByte(iop_base
, ASCV_HOSTSCSI_ID_B
,
6331 ASC_TID_TO_TARGET_ID(asc_dvc
->cfg
->chip_scsi_id
));
6333 /* Align overrun buffer on an 8 byte boundary. */
6334 phy_addr
= virt_to_bus(asc_dvc
->cfg
->overrun_buf
);
6335 phy_addr
= cpu_to_le32((phy_addr
+ 7) & ~0x7);
6336 AscMemDWordCopyPtrToLram(iop_base
, ASCV_OVERRUN_PADDR_D
,
6337 (uchar
*)&phy_addr
, 1);
6338 phy_size
= cpu_to_le32(ASC_OVERRUN_BSIZE
- 8);
6339 AscMemDWordCopyPtrToLram(iop_base
, ASCV_OVERRUN_BSIZE_D
,
6340 (uchar
*)&phy_size
, 1);
6342 asc_dvc
->cfg
->mcode_date
=
6343 AscReadLramWord(iop_base
, (ushort
)ASCV_MC_DATE_W
);
6344 asc_dvc
->cfg
->mcode_version
=
6345 AscReadLramWord(iop_base
, (ushort
)ASCV_MC_VER_W
);
6347 AscSetPCAddr(iop_base
, ASC_MCODE_START_ADDR
);
6348 if (AscGetPCAddr(iop_base
) != ASC_MCODE_START_ADDR
) {
6349 asc_dvc
->err_code
|= ASC_IERR_SET_PC_ADDR
;
6352 if (AscStartChip(iop_base
) != 1) {
6353 asc_dvc
->err_code
|= ASC_IERR_START_STOP_CHIP
;
6360 static ushort
AscInitAsc1000Driver(ASC_DVC_VAR
*asc_dvc
)
6365 iop_base
= asc_dvc
->iop_base
;
6367 if ((asc_dvc
->dvc_cntl
& ASC_CNTL_RESET_SCSI
) &&
6368 !(asc_dvc
->init_state
& ASC_INIT_RESET_SCSI_DONE
)) {
6369 AscResetChipAndScsiBus(asc_dvc
);
6370 mdelay(asc_dvc
->scsi_reset_wait
* 1000); /* XXX: msleep? */
6372 asc_dvc
->init_state
|= ASC_INIT_STATE_BEG_LOAD_MC
;
6373 if (asc_dvc
->err_code
!= 0)
6375 if (!AscFindSignature(asc_dvc
->iop_base
)) {
6376 asc_dvc
->err_code
= ASC_IERR_BAD_SIGNATURE
;
6379 AscDisableInterrupt(iop_base
);
6380 warn_code
|= AscInitLram(asc_dvc
);
6381 if (asc_dvc
->err_code
!= 0)
6383 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong
)_asc_mcode_chksum
);
6384 if (AscLoadMicroCode(iop_base
, 0, _asc_mcode_buf
,
6385 _asc_mcode_size
) != _asc_mcode_chksum
) {
6386 asc_dvc
->err_code
|= ASC_IERR_MCODE_CHKSUM
;
6389 warn_code
|= AscInitMicroCodeVar(asc_dvc
);
6390 asc_dvc
->init_state
|= ASC_INIT_STATE_END_LOAD_MC
;
6391 AscEnableInterrupt(iop_base
);
6396 * Load the Microcode
6398 * Write the microcode image to RISC memory starting at address 0.
6400 * The microcode is stored compressed in the following format:
6402 * 254 word (508 byte) table indexed by byte code followed
6403 * by the following byte codes:
6406 * 00: Emit word 0 in table.
6407 * 01: Emit word 1 in table.
6409 * FD: Emit word 253 in table.
6412 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
6413 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
6415 * Returns 0 or an error if the checksum doesn't match
6417 static int AdvLoadMicrocode(AdvPortAddr iop_base
, unsigned char *buf
, int size
,
6418 int memsize
, int chksum
)
6420 int i
, j
, end
, len
= 0;
6423 AdvWriteWordRegister(iop_base
, IOPW_RAM_ADDR
, 0);
6425 for (i
= 253 * 2; i
< size
; i
++) {
6426 if (buf
[i
] == 0xff) {
6427 unsigned short word
= (buf
[i
+ 3] << 8) | buf
[i
+ 2];
6428 for (j
= 0; j
< buf
[i
+ 1]; j
++) {
6429 AdvWriteWordAutoIncLram(iop_base
, word
);
6433 } else if (buf
[i
] == 0xfe) {
6434 unsigned short word
= (buf
[i
+ 2] << 8) | buf
[i
+ 1];
6435 AdvWriteWordAutoIncLram(iop_base
, word
);
6439 unsigned char off
= buf
[i
] * 2;
6440 unsigned short word
= (buf
[off
+ 1] << 8) | buf
[off
];
6441 AdvWriteWordAutoIncLram(iop_base
, word
);
6448 while (len
< memsize
) {
6449 AdvWriteWordAutoIncLram(iop_base
, 0);
6453 /* Verify the microcode checksum. */
6455 AdvWriteWordRegister(iop_base
, IOPW_RAM_ADDR
, 0);
6457 for (len
= 0; len
< end
; len
+= 2) {
6458 sum
+= AdvReadWordAutoIncLram(iop_base
);
6462 return ASC_IERR_MCODE_CHKSUM
;
6467 static void AdvBuildCarrierFreelist(struct adv_dvc_var
*asc_dvc
)
6471 ADV_PADDR carr_paddr
;
6473 carrp
= (ADV_CARR_T
*) ADV_16BALIGN(asc_dvc
->carrier_buf
);
6474 asc_dvc
->carr_freelist
= NULL
;
6475 if (carrp
== asc_dvc
->carrier_buf
) {
6476 buf_size
= ADV_CARRIER_BUFSIZE
;
6478 buf_size
= ADV_CARRIER_BUFSIZE
- sizeof(ADV_CARR_T
);
6482 /* Get physical address of the carrier 'carrp'. */
6483 carr_paddr
= cpu_to_le32(virt_to_bus(carrp
));
6485 buf_size
-= sizeof(ADV_CARR_T
);
6487 carrp
->carr_pa
= carr_paddr
;
6488 carrp
->carr_va
= cpu_to_le32(ADV_VADDR_TO_U32(carrp
));
6491 * Insert the carrier at the beginning of the freelist.
6494 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc
->carr_freelist
));
6495 asc_dvc
->carr_freelist
= carrp
;
6498 } while (buf_size
> 0);
6502 * Send an idle command to the chip and wait for completion.
6504 * Command completion is polled for once per microsecond.
6506 * The function can be called from anywhere including an interrupt handler.
6507 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
6508 * functions to prevent reentrancy.
6511 * ADV_TRUE - command completed successfully
6512 * ADV_FALSE - command failed
6513 * ADV_ERROR - command timed out
6516 AdvSendIdleCmd(ADV_DVC_VAR
*asc_dvc
,
6517 ushort idle_cmd
, ADV_DCNT idle_cmd_parameter
)
6521 AdvPortAddr iop_base
;
6523 iop_base
= asc_dvc
->iop_base
;
6526 * Clear the idle command status which is set by the microcode
6527 * to a non-zero value to indicate when the command is completed.
6528 * The non-zero result is one of the IDLE_CMD_STATUS_* values
6530 AdvWriteWordLram(iop_base
, ASC_MC_IDLE_CMD_STATUS
, (ushort
)0);
6533 * Write the idle command value after the idle command parameter
6534 * has been written to avoid a race condition. If the order is not
6535 * followed, the microcode may process the idle command before the
6536 * parameters have been written to LRAM.
6538 AdvWriteDWordLramNoSwap(iop_base
, ASC_MC_IDLE_CMD_PARAMETER
,
6539 cpu_to_le32(idle_cmd_parameter
));
6540 AdvWriteWordLram(iop_base
, ASC_MC_IDLE_CMD
, idle_cmd
);
6543 * Tickle the RISC to tell it to process the idle command.
6545 AdvWriteByteRegister(iop_base
, IOPB_TICKLE
, ADV_TICKLE_B
);
6546 if (asc_dvc
->chip_type
== ADV_CHIP_ASC3550
) {
6548 * Clear the tickle value. In the ASC-3550 the RISC flag
6549 * command 'clr_tickle_b' does not work unless the host
6552 AdvWriteByteRegister(iop_base
, IOPB_TICKLE
, ADV_TICKLE_NOP
);
6555 /* Wait for up to 100 millisecond for the idle command to timeout. */
6556 for (i
= 0; i
< SCSI_WAIT_100_MSEC
; i
++) {
6557 /* Poll once each microsecond for command completion. */
6558 for (j
= 0; j
< SCSI_US_PER_MSEC
; j
++) {
6559 AdvReadWordLram(iop_base
, ASC_MC_IDLE_CMD_STATUS
,
6567 BUG(); /* The idle command should never timeout. */
6572 * Reset SCSI Bus and purge all outstanding requests.
6575 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
6576 * ADV_FALSE(0) - Microcode command failed.
6577 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
6578 * may be hung which requires driver recovery.
6580 static int AdvResetSB(ADV_DVC_VAR
*asc_dvc
)
6585 * Send the SCSI Bus Reset idle start idle command which asserts
6586 * the SCSI Bus Reset signal.
6588 status
= AdvSendIdleCmd(asc_dvc
, (ushort
)IDLE_CMD_SCSI_RESET_START
, 0L);
6589 if (status
!= ADV_TRUE
) {
6594 * Delay for the specified SCSI Bus Reset hold time.
6596 * The hold time delay is done on the host because the RISC has no
6597 * microsecond accurate timer.
6599 udelay(ASC_SCSI_RESET_HOLD_TIME_US
);
6602 * Send the SCSI Bus Reset end idle command which de-asserts
6603 * the SCSI Bus Reset signal and purges any pending requests.
6605 status
= AdvSendIdleCmd(asc_dvc
, (ushort
)IDLE_CMD_SCSI_RESET_END
, 0L);
6606 if (status
!= ADV_TRUE
) {
6610 mdelay(asc_dvc
->scsi_reset_wait
* 1000); /* XXX: msleep? */
6616 * Initialize the ASC-3550.
6618 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
6620 * For a non-fatal error return a warning code. If there are no warnings
6621 * then 0 is returned.
6623 * Needed after initialization for error recovery.
6625 static int AdvInitAsc3550Driver(ADV_DVC_VAR
*asc_dvc
)
6627 AdvPortAddr iop_base
;
6636 ushort bios_mem
[ASC_MC_BIOSLEN
/ 2]; /* BIOS RISC Memory 0x40-0x8F. */
6637 ushort wdtr_able
= 0, sdtr_able
, tagqng_able
;
6638 uchar max_cmd
[ADV_MAX_TID
+ 1];
6640 /* If there is already an error, don't continue. */
6641 if (asc_dvc
->err_code
!= 0)
6645 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
6647 if (asc_dvc
->chip_type
!= ADV_CHIP_ASC3550
) {
6648 asc_dvc
->err_code
= ASC_IERR_BAD_CHIPTYPE
;
6653 iop_base
= asc_dvc
->iop_base
;
6656 * Save the RISC memory BIOS region before writing the microcode.
6657 * The BIOS may already be loaded and using its RISC LRAM region
6658 * so its region must be saved and restored.
6660 * Note: This code makes the assumption, which is currently true,
6661 * that a chip reset does not clear RISC LRAM.
6663 for (i
= 0; i
< ASC_MC_BIOSLEN
/ 2; i
++) {
6664 AdvReadWordLram(iop_base
, ASC_MC_BIOSMEM
+ (2 * i
),
6669 * Save current per TID negotiated values.
6671 if (bios_mem
[(ASC_MC_BIOS_SIGNATURE
- ASC_MC_BIOSMEM
) / 2] == 0x55AA) {
6672 ushort bios_version
, major
, minor
;
6675 bios_mem
[(ASC_MC_BIOS_VERSION
- ASC_MC_BIOSMEM
) / 2];
6676 major
= (bios_version
>> 12) & 0xF;
6677 minor
= (bios_version
>> 8) & 0xF;
6678 if (major
< 3 || (major
== 3 && minor
== 1)) {
6679 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
6680 AdvReadWordLram(iop_base
, 0x120, wdtr_able
);
6682 AdvReadWordLram(iop_base
, ASC_MC_WDTR_ABLE
, wdtr_able
);
6685 AdvReadWordLram(iop_base
, ASC_MC_SDTR_ABLE
, sdtr_able
);
6686 AdvReadWordLram(iop_base
, ASC_MC_TAGQNG_ABLE
, tagqng_able
);
6687 for (tid
= 0; tid
<= ADV_MAX_TID
; tid
++) {
6688 AdvReadByteLram(iop_base
, ASC_MC_NUMBER_OF_MAX_CMD
+ tid
,
6692 asc_dvc
->err_code
= AdvLoadMicrocode(iop_base
, _adv_asc3550_buf
,
6693 _adv_asc3550_size
, ADV_3550_MEMSIZE
,
6694 _adv_asc3550_chksum
);
6695 if (asc_dvc
->err_code
)
6699 * Restore the RISC memory BIOS region.
6701 for (i
= 0; i
< ASC_MC_BIOSLEN
/ 2; i
++) {
6702 AdvWriteWordLram(iop_base
, ASC_MC_BIOSMEM
+ (2 * i
),
6707 * Calculate and write the microcode code checksum to the microcode
6708 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
6710 AdvReadWordLram(iop_base
, ASC_MC_CODE_BEGIN_ADDR
, begin_addr
);
6711 AdvReadWordLram(iop_base
, ASC_MC_CODE_END_ADDR
, end_addr
);
6713 AdvWriteWordRegister(iop_base
, IOPW_RAM_ADDR
, begin_addr
);
6714 for (word
= begin_addr
; word
< end_addr
; word
+= 2) {
6715 code_sum
+= AdvReadWordAutoIncLram(iop_base
);
6717 AdvWriteWordLram(iop_base
, ASC_MC_CODE_CHK_SUM
, code_sum
);
6720 * Read and save microcode version and date.
6722 AdvReadWordLram(iop_base
, ASC_MC_VERSION_DATE
,
6723 asc_dvc
->cfg
->mcode_date
);
6724 AdvReadWordLram(iop_base
, ASC_MC_VERSION_NUM
,
6725 asc_dvc
->cfg
->mcode_version
);
6728 * Set the chip type to indicate the ASC3550.
6730 AdvWriteWordLram(iop_base
, ASC_MC_CHIP_TYPE
, ADV_CHIP_ASC3550
);
6733 * If the PCI Configuration Command Register "Parity Error Response
6734 * Control" Bit was clear (0), then set the microcode variable
6735 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
6736 * to ignore DMA parity errors.
6738 if (asc_dvc
->cfg
->control_flag
& CONTROL_FLAG_IGNORE_PERR
) {
6739 AdvReadWordLram(iop_base
, ASC_MC_CONTROL_FLAG
, word
);
6740 word
|= CONTROL_FLAG_IGNORE_PERR
;
6741 AdvWriteWordLram(iop_base
, ASC_MC_CONTROL_FLAG
, word
);
6745 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
6746 * threshold of 128 bytes. This register is only accessible to the host.
6748 AdvWriteByteRegister(iop_base
, IOPB_DMA_CFG0
,
6749 START_CTL_EMFU
| READ_CMD_MRM
);
6752 * Microcode operating variables for WDTR, SDTR, and command tag
6753 * queuing will be set in slave_configure() based on what a
6754 * device reports it is capable of in Inquiry byte 7.
6756 * If SCSI Bus Resets have been disabled, then directly set
6757 * SDTR and WDTR from the EEPROM configuration. This will allow
6758 * the BIOS and warm boot to work without a SCSI bus hang on
6759 * the Inquiry caused by host and target mismatched DTR values.
6760 * Without the SCSI Bus Reset, before an Inquiry a device can't
6761 * be assumed to be in Asynchronous, Narrow mode.
6763 if ((asc_dvc
->bios_ctrl
& BIOS_CTRL_RESET_SCSI_BUS
) == 0) {
6764 AdvWriteWordLram(iop_base
, ASC_MC_WDTR_ABLE
,
6765 asc_dvc
->wdtr_able
);
6766 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_ABLE
,
6767 asc_dvc
->sdtr_able
);
6771 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
6772 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
6773 * bitmask. These values determine the maximum SDTR speed negotiated
6776 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
6777 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
6778 * without determining here whether the device supports SDTR.
6780 * 4-bit speed SDTR speed name
6781 * =========== ===============
6782 * 0000b (0x0) SDTR disabled
6784 * 0010b (0x2) 10 Mhz
6785 * 0011b (0x3) 20 Mhz (Ultra)
6786 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
6787 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
6788 * 0110b (0x6) Undefined
6790 * 1111b (0xF) Undefined
6793 for (tid
= 0; tid
<= ADV_MAX_TID
; tid
++) {
6794 if (ADV_TID_TO_TIDMASK(tid
) & asc_dvc
->ultra_able
) {
6795 /* Set Ultra speed for TID 'tid'. */
6796 word
|= (0x3 << (4 * (tid
% 4)));
6798 /* Set Fast speed for TID 'tid'. */
6799 word
|= (0x2 << (4 * (tid
% 4)));
6801 if (tid
== 3) { /* Check if done with sdtr_speed1. */
6802 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_SPEED1
, word
);
6804 } else if (tid
== 7) { /* Check if done with sdtr_speed2. */
6805 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_SPEED2
, word
);
6807 } else if (tid
== 11) { /* Check if done with sdtr_speed3. */
6808 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_SPEED3
, word
);
6810 } else if (tid
== 15) { /* Check if done with sdtr_speed4. */
6811 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_SPEED4
, word
);
6817 * Set microcode operating variable for the disconnect per TID bitmask.
6819 AdvWriteWordLram(iop_base
, ASC_MC_DISC_ENABLE
,
6820 asc_dvc
->cfg
->disc_enable
);
6823 * Set SCSI_CFG0 Microcode Default Value.
6825 * The microcode will set the SCSI_CFG0 register using this value
6826 * after it is started below.
6828 AdvWriteWordLram(iop_base
, ASC_MC_DEFAULT_SCSI_CFG0
,
6829 PARITY_EN
| QUEUE_128
| SEL_TMO_LONG
| OUR_ID_EN
|
6830 asc_dvc
->chip_scsi_id
);
6833 * Determine SCSI_CFG1 Microcode Default Value.
6835 * The microcode will set the SCSI_CFG1 register using this value
6836 * after it is started below.
6839 /* Read current SCSI_CFG1 Register value. */
6840 scsi_cfg1
= AdvReadWordRegister(iop_base
, IOPW_SCSI_CFG1
);
6843 * If all three connectors are in use, return an error.
6845 if ((scsi_cfg1
& CABLE_ILLEGAL_A
) == 0 ||
6846 (scsi_cfg1
& CABLE_ILLEGAL_B
) == 0) {
6847 asc_dvc
->err_code
|= ASC_IERR_ILLEGAL_CONNECTION
;
6852 * If the internal narrow cable is reversed all of the SCSI_CTRL
6853 * register signals will be set. Check for and return an error if
6854 * this condition is found.
6856 if ((AdvReadWordRegister(iop_base
, IOPW_SCSI_CTRL
) & 0x3F07) == 0x3F07) {
6857 asc_dvc
->err_code
|= ASC_IERR_REVERSED_CABLE
;
6862 * If this is a differential board and a single-ended device
6863 * is attached to one of the connectors, return an error.
6865 if ((scsi_cfg1
& DIFF_MODE
) && (scsi_cfg1
& DIFF_SENSE
) == 0) {
6866 asc_dvc
->err_code
|= ASC_IERR_SINGLE_END_DEVICE
;
6871 * If automatic termination control is enabled, then set the
6872 * termination value based on a table listed in a_condor.h.
6874 * If manual termination was specified with an EEPROM setting
6875 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
6876 * is ready to be 'ored' into SCSI_CFG1.
6878 if (asc_dvc
->cfg
->termination
== 0) {
6880 * The software always controls termination by setting TERM_CTL_SEL.
6881 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
6883 asc_dvc
->cfg
->termination
|= TERM_CTL_SEL
;
6885 switch (scsi_cfg1
& CABLE_DETECT
) {
6886 /* TERM_CTL_H: on, TERM_CTL_L: on */
6893 asc_dvc
->cfg
->termination
|= (TERM_CTL_H
| TERM_CTL_L
);
6896 /* TERM_CTL_H: on, TERM_CTL_L: off */
6902 asc_dvc
->cfg
->termination
|= TERM_CTL_H
;
6905 /* TERM_CTL_H: off, TERM_CTL_L: off */
6913 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
6915 scsi_cfg1
&= ~TERM_CTL
;
6918 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
6919 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
6920 * referenced, because the hardware internally inverts
6921 * the Termination High and Low bits if TERM_POL is set.
6923 scsi_cfg1
|= (TERM_CTL_SEL
| (~asc_dvc
->cfg
->termination
& TERM_CTL
));
6926 * Set SCSI_CFG1 Microcode Default Value
6928 * Set filter value and possibly modified termination control
6929 * bits in the Microcode SCSI_CFG1 Register Value.
6931 * The microcode will set the SCSI_CFG1 register using this value
6932 * after it is started below.
6934 AdvWriteWordLram(iop_base
, ASC_MC_DEFAULT_SCSI_CFG1
,
6935 FLTR_DISABLE
| scsi_cfg1
);
6938 * Set MEM_CFG Microcode Default Value
6940 * The microcode will set the MEM_CFG register using this value
6941 * after it is started below.
6943 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
6946 * ASC-3550 has 8KB internal memory.
6948 AdvWriteWordLram(iop_base
, ASC_MC_DEFAULT_MEM_CFG
,
6949 BIOS_EN
| RAM_SZ_8KB
);
6952 * Set SEL_MASK Microcode Default Value
6954 * The microcode will set the SEL_MASK register using this value
6955 * after it is started below.
6957 AdvWriteWordLram(iop_base
, ASC_MC_DEFAULT_SEL_MASK
,
6958 ADV_TID_TO_TIDMASK(asc_dvc
->chip_scsi_id
));
6960 AdvBuildCarrierFreelist(asc_dvc
);
6963 * Set-up the Host->RISC Initiator Command Queue (ICQ).
6966 if ((asc_dvc
->icq_sp
= asc_dvc
->carr_freelist
) == NULL
) {
6967 asc_dvc
->err_code
|= ASC_IERR_NO_CARRIER
;
6970 asc_dvc
->carr_freelist
= (ADV_CARR_T
*)
6971 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc
->icq_sp
->next_vpa
));
6974 * The first command issued will be placed in the stopper carrier.
6976 asc_dvc
->icq_sp
->next_vpa
= cpu_to_le32(ASC_CQ_STOPPER
);
6979 * Set RISC ICQ physical address start value.
6981 AdvWriteDWordLramNoSwap(iop_base
, ASC_MC_ICQ
, asc_dvc
->icq_sp
->carr_pa
);
6984 * Set-up the RISC->Host Initiator Response Queue (IRQ).
6986 if ((asc_dvc
->irq_sp
= asc_dvc
->carr_freelist
) == NULL
) {
6987 asc_dvc
->err_code
|= ASC_IERR_NO_CARRIER
;
6990 asc_dvc
->carr_freelist
= (ADV_CARR_T
*)
6991 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc
->irq_sp
->next_vpa
));
6994 * The first command completed by the RISC will be placed in
6997 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
6998 * completed the RISC will set the ASC_RQ_STOPPER bit.
7000 asc_dvc
->irq_sp
->next_vpa
= cpu_to_le32(ASC_CQ_STOPPER
);
7003 * Set RISC IRQ physical address start value.
7005 AdvWriteDWordLramNoSwap(iop_base
, ASC_MC_IRQ
, asc_dvc
->irq_sp
->carr_pa
);
7006 asc_dvc
->carr_pending_cnt
= 0;
7008 AdvWriteByteRegister(iop_base
, IOPB_INTR_ENABLES
,
7009 (ADV_INTR_ENABLE_HOST_INTR
|
7010 ADV_INTR_ENABLE_GLOBAL_INTR
));
7012 AdvReadWordLram(iop_base
, ASC_MC_CODE_BEGIN_ADDR
, word
);
7013 AdvWriteWordRegister(iop_base
, IOPW_PC
, word
);
7015 /* finally, finally, gentlemen, start your engine */
7016 AdvWriteWordRegister(iop_base
, IOPW_RISC_CSR
, ADV_RISC_CSR_RUN
);
7019 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7020 * Resets should be performed. The RISC has to be running
7021 * to issue a SCSI Bus Reset.
7023 if (asc_dvc
->bios_ctrl
& BIOS_CTRL_RESET_SCSI_BUS
) {
7025 * If the BIOS Signature is present in memory, restore the
7026 * BIOS Handshake Configuration Table and do not perform
7029 if (bios_mem
[(ASC_MC_BIOS_SIGNATURE
- ASC_MC_BIOSMEM
) / 2] ==
7032 * Restore per TID negotiated values.
7034 AdvWriteWordLram(iop_base
, ASC_MC_WDTR_ABLE
, wdtr_able
);
7035 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_ABLE
, sdtr_able
);
7036 AdvWriteWordLram(iop_base
, ASC_MC_TAGQNG_ABLE
,
7038 for (tid
= 0; tid
<= ADV_MAX_TID
; tid
++) {
7039 AdvWriteByteLram(iop_base
,
7040 ASC_MC_NUMBER_OF_MAX_CMD
+ tid
,
7044 if (AdvResetSB(asc_dvc
) != ADV_TRUE
) {
7045 warn_code
= ASC_WARN_BUSRESET_ERROR
;
7054 * Initialize the ASC-38C0800.
7056 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
7058 * For a non-fatal error return a warning code. If there are no warnings
7059 * then 0 is returned.
7061 * Needed after initialization for error recovery.
7063 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR
*asc_dvc
)
7065 AdvPortAddr iop_base
;
7075 ushort bios_mem
[ASC_MC_BIOSLEN
/ 2]; /* BIOS RISC Memory 0x40-0x8F. */
7076 ushort wdtr_able
, sdtr_able
, tagqng_able
;
7077 uchar max_cmd
[ADV_MAX_TID
+ 1];
7079 /* If there is already an error, don't continue. */
7080 if (asc_dvc
->err_code
!= 0)
7084 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
7086 if (asc_dvc
->chip_type
!= ADV_CHIP_ASC38C0800
) {
7087 asc_dvc
->err_code
= ASC_IERR_BAD_CHIPTYPE
;
7092 iop_base
= asc_dvc
->iop_base
;
7095 * Save the RISC memory BIOS region before writing the microcode.
7096 * The BIOS may already be loaded and using its RISC LRAM region
7097 * so its region must be saved and restored.
7099 * Note: This code makes the assumption, which is currently true,
7100 * that a chip reset does not clear RISC LRAM.
7102 for (i
= 0; i
< ASC_MC_BIOSLEN
/ 2; i
++) {
7103 AdvReadWordLram(iop_base
, ASC_MC_BIOSMEM
+ (2 * i
),
7108 * Save current per TID negotiated values.
7110 AdvReadWordLram(iop_base
, ASC_MC_WDTR_ABLE
, wdtr_able
);
7111 AdvReadWordLram(iop_base
, ASC_MC_SDTR_ABLE
, sdtr_able
);
7112 AdvReadWordLram(iop_base
, ASC_MC_TAGQNG_ABLE
, tagqng_able
);
7113 for (tid
= 0; tid
<= ADV_MAX_TID
; tid
++) {
7114 AdvReadByteLram(iop_base
, ASC_MC_NUMBER_OF_MAX_CMD
+ tid
,
7119 * RAM BIST (RAM Built-In Self Test)
7121 * Address : I/O base + offset 0x38h register (byte).
7122 * Function: Bit 7-6(RW) : RAM mode
7123 * Normal Mode : 0x00
7124 * Pre-test Mode : 0x40
7125 * RAM Test Mode : 0x80
7127 * Bit 4(RO) : Done bit
7128 * Bit 3-0(RO) : Status
7130 * Int_RAM Error : 0x04
7135 * Note: RAM BIST code should be put right here, before loading the
7136 * microcode and after saving the RISC memory BIOS region.
7142 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
7143 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
7144 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
7145 * to NORMAL_MODE, return an error too.
7147 for (i
= 0; i
< 2; i
++) {
7148 AdvWriteByteRegister(iop_base
, IOPB_RAM_BIST
, PRE_TEST_MODE
);
7149 mdelay(10); /* Wait for 10ms before reading back. */
7150 byte
= AdvReadByteRegister(iop_base
, IOPB_RAM_BIST
);
7151 if ((byte
& RAM_TEST_DONE
) == 0
7152 || (byte
& 0x0F) != PRE_TEST_VALUE
) {
7153 asc_dvc
->err_code
= ASC_IERR_BIST_PRE_TEST
;
7157 AdvWriteByteRegister(iop_base
, IOPB_RAM_BIST
, NORMAL_MODE
);
7158 mdelay(10); /* Wait for 10ms before reading back. */
7159 if (AdvReadByteRegister(iop_base
, IOPB_RAM_BIST
)
7161 asc_dvc
->err_code
= ASC_IERR_BIST_PRE_TEST
;
7167 * LRAM Test - It takes about 1.5 ms to run through the test.
7169 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
7170 * If Done bit not set or Status not 0, save register byte, set the
7171 * err_code, and return an error.
7173 AdvWriteByteRegister(iop_base
, IOPB_RAM_BIST
, RAM_TEST_MODE
);
7174 mdelay(10); /* Wait for 10ms before checking status. */
7176 byte
= AdvReadByteRegister(iop_base
, IOPB_RAM_BIST
);
7177 if ((byte
& RAM_TEST_DONE
) == 0 || (byte
& RAM_TEST_STATUS
) != 0) {
7178 /* Get here if Done bit not set or Status not 0. */
7179 asc_dvc
->bist_err_code
= byte
; /* for BIOS display message */
7180 asc_dvc
->err_code
= ASC_IERR_BIST_RAM_TEST
;
7184 /* We need to reset back to normal mode after LRAM test passes. */
7185 AdvWriteByteRegister(iop_base
, IOPB_RAM_BIST
, NORMAL_MODE
);
7187 asc_dvc
->err_code
= AdvLoadMicrocode(iop_base
, _adv_asc38C0800_buf
,
7188 _adv_asc38C0800_size
, ADV_38C0800_MEMSIZE
,
7189 _adv_asc38C0800_chksum
);
7190 if (asc_dvc
->err_code
)
7194 * Restore the RISC memory BIOS region.
7196 for (i
= 0; i
< ASC_MC_BIOSLEN
/ 2; i
++) {
7197 AdvWriteWordLram(iop_base
, ASC_MC_BIOSMEM
+ (2 * i
),
7202 * Calculate and write the microcode code checksum to the microcode
7203 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
7205 AdvReadWordLram(iop_base
, ASC_MC_CODE_BEGIN_ADDR
, begin_addr
);
7206 AdvReadWordLram(iop_base
, ASC_MC_CODE_END_ADDR
, end_addr
);
7208 AdvWriteWordRegister(iop_base
, IOPW_RAM_ADDR
, begin_addr
);
7209 for (word
= begin_addr
; word
< end_addr
; word
+= 2) {
7210 code_sum
+= AdvReadWordAutoIncLram(iop_base
);
7212 AdvWriteWordLram(iop_base
, ASC_MC_CODE_CHK_SUM
, code_sum
);
7215 * Read microcode version and date.
7217 AdvReadWordLram(iop_base
, ASC_MC_VERSION_DATE
,
7218 asc_dvc
->cfg
->mcode_date
);
7219 AdvReadWordLram(iop_base
, ASC_MC_VERSION_NUM
,
7220 asc_dvc
->cfg
->mcode_version
);
7223 * Set the chip type to indicate the ASC38C0800.
7225 AdvWriteWordLram(iop_base
, ASC_MC_CHIP_TYPE
, ADV_CHIP_ASC38C0800
);
7228 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
7229 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
7230 * cable detection and then we are able to read C_DET[3:0].
7232 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
7233 * Microcode Default Value' section below.
7235 scsi_cfg1
= AdvReadWordRegister(iop_base
, IOPW_SCSI_CFG1
);
7236 AdvWriteWordRegister(iop_base
, IOPW_SCSI_CFG1
,
7237 scsi_cfg1
| DIS_TERM_DRV
);
7240 * If the PCI Configuration Command Register "Parity Error Response
7241 * Control" Bit was clear (0), then set the microcode variable
7242 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
7243 * to ignore DMA parity errors.
7245 if (asc_dvc
->cfg
->control_flag
& CONTROL_FLAG_IGNORE_PERR
) {
7246 AdvReadWordLram(iop_base
, ASC_MC_CONTROL_FLAG
, word
);
7247 word
|= CONTROL_FLAG_IGNORE_PERR
;
7248 AdvWriteWordLram(iop_base
, ASC_MC_CONTROL_FLAG
, word
);
7252 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
7253 * bits for the default FIFO threshold.
7255 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
7257 * For DMA Errata #4 set the BC_THRESH_ENB bit.
7259 AdvWriteByteRegister(iop_base
, IOPB_DMA_CFG0
,
7260 BC_THRESH_ENB
| FIFO_THRESH_80B
| START_CTL_TH
|
7264 * Microcode operating variables for WDTR, SDTR, and command tag
7265 * queuing will be set in slave_configure() based on what a
7266 * device reports it is capable of in Inquiry byte 7.
7268 * If SCSI Bus Resets have been disabled, then directly set
7269 * SDTR and WDTR from the EEPROM configuration. This will allow
7270 * the BIOS and warm boot to work without a SCSI bus hang on
7271 * the Inquiry caused by host and target mismatched DTR values.
7272 * Without the SCSI Bus Reset, before an Inquiry a device can't
7273 * be assumed to be in Asynchronous, Narrow mode.
7275 if ((asc_dvc
->bios_ctrl
& BIOS_CTRL_RESET_SCSI_BUS
) == 0) {
7276 AdvWriteWordLram(iop_base
, ASC_MC_WDTR_ABLE
,
7277 asc_dvc
->wdtr_able
);
7278 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_ABLE
,
7279 asc_dvc
->sdtr_able
);
7283 * Set microcode operating variables for DISC and SDTR_SPEED1,
7284 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
7285 * configuration values.
7287 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
7288 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
7289 * without determining here whether the device supports SDTR.
7291 AdvWriteWordLram(iop_base
, ASC_MC_DISC_ENABLE
,
7292 asc_dvc
->cfg
->disc_enable
);
7293 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_SPEED1
, asc_dvc
->sdtr_speed1
);
7294 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_SPEED2
, asc_dvc
->sdtr_speed2
);
7295 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_SPEED3
, asc_dvc
->sdtr_speed3
);
7296 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_SPEED4
, asc_dvc
->sdtr_speed4
);
7299 * Set SCSI_CFG0 Microcode Default Value.
7301 * The microcode will set the SCSI_CFG0 register using this value
7302 * after it is started below.
7304 AdvWriteWordLram(iop_base
, ASC_MC_DEFAULT_SCSI_CFG0
,
7305 PARITY_EN
| QUEUE_128
| SEL_TMO_LONG
| OUR_ID_EN
|
7306 asc_dvc
->chip_scsi_id
);
7309 * Determine SCSI_CFG1 Microcode Default Value.
7311 * The microcode will set the SCSI_CFG1 register using this value
7312 * after it is started below.
7315 /* Read current SCSI_CFG1 Register value. */
7316 scsi_cfg1
= AdvReadWordRegister(iop_base
, IOPW_SCSI_CFG1
);
7319 * If the internal narrow cable is reversed all of the SCSI_CTRL
7320 * register signals will be set. Check for and return an error if
7321 * this condition is found.
7323 if ((AdvReadWordRegister(iop_base
, IOPW_SCSI_CTRL
) & 0x3F07) == 0x3F07) {
7324 asc_dvc
->err_code
|= ASC_IERR_REVERSED_CABLE
;
7329 * All kind of combinations of devices attached to one of four
7330 * connectors are acceptable except HVD device attached. For example,
7331 * LVD device can be attached to SE connector while SE device attached
7332 * to LVD connector. If LVD device attached to SE connector, it only
7333 * runs up to Ultra speed.
7335 * If an HVD device is attached to one of LVD connectors, return an
7336 * error. However, there is no way to detect HVD device attached to
7339 if (scsi_cfg1
& HVD
) {
7340 asc_dvc
->err_code
= ASC_IERR_HVD_DEVICE
;
7345 * If either SE or LVD automatic termination control is enabled, then
7346 * set the termination value based on a table listed in a_condor.h.
7348 * If manual termination was specified with an EEPROM setting then
7349 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
7350 * to be 'ored' into SCSI_CFG1.
7352 if ((asc_dvc
->cfg
->termination
& TERM_SE
) == 0) {
7353 /* SE automatic termination control is enabled. */
7354 switch (scsi_cfg1
& C_DET_SE
) {
7355 /* TERM_SE_HI: on, TERM_SE_LO: on */
7359 asc_dvc
->cfg
->termination
|= TERM_SE
;
7362 /* TERM_SE_HI: on, TERM_SE_LO: off */
7364 asc_dvc
->cfg
->termination
|= TERM_SE_HI
;
7369 if ((asc_dvc
->cfg
->termination
& TERM_LVD
) == 0) {
7370 /* LVD automatic termination control is enabled. */
7371 switch (scsi_cfg1
& C_DET_LVD
) {
7372 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
7376 asc_dvc
->cfg
->termination
|= TERM_LVD
;
7379 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
7386 * Clear any set TERM_SE and TERM_LVD bits.
7388 scsi_cfg1
&= (~TERM_SE
& ~TERM_LVD
);
7391 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
7393 scsi_cfg1
|= (~asc_dvc
->cfg
->termination
& 0xF0);
7396 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
7397 * bits and set possibly modified termination control bits in the
7398 * Microcode SCSI_CFG1 Register Value.
7400 scsi_cfg1
&= (~BIG_ENDIAN
& ~DIS_TERM_DRV
& ~TERM_POL
& ~HVD_LVD_SE
);
7403 * Set SCSI_CFG1 Microcode Default Value
7405 * Set possibly modified termination control and reset DIS_TERM_DRV
7406 * bits in the Microcode SCSI_CFG1 Register Value.
7408 * The microcode will set the SCSI_CFG1 register using this value
7409 * after it is started below.
7411 AdvWriteWordLram(iop_base
, ASC_MC_DEFAULT_SCSI_CFG1
, scsi_cfg1
);
7414 * Set MEM_CFG Microcode Default Value
7416 * The microcode will set the MEM_CFG register using this value
7417 * after it is started below.
7419 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7422 * ASC-38C0800 has 16KB internal memory.
7424 AdvWriteWordLram(iop_base
, ASC_MC_DEFAULT_MEM_CFG
,
7425 BIOS_EN
| RAM_SZ_16KB
);
7428 * Set SEL_MASK Microcode Default Value
7430 * The microcode will set the SEL_MASK register using this value
7431 * after it is started below.
7433 AdvWriteWordLram(iop_base
, ASC_MC_DEFAULT_SEL_MASK
,
7434 ADV_TID_TO_TIDMASK(asc_dvc
->chip_scsi_id
));
7436 AdvBuildCarrierFreelist(asc_dvc
);
7439 * Set-up the Host->RISC Initiator Command Queue (ICQ).
7442 if ((asc_dvc
->icq_sp
= asc_dvc
->carr_freelist
) == NULL
) {
7443 asc_dvc
->err_code
|= ASC_IERR_NO_CARRIER
;
7446 asc_dvc
->carr_freelist
= (ADV_CARR_T
*)
7447 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc
->icq_sp
->next_vpa
));
7450 * The first command issued will be placed in the stopper carrier.
7452 asc_dvc
->icq_sp
->next_vpa
= cpu_to_le32(ASC_CQ_STOPPER
);
7455 * Set RISC ICQ physical address start value.
7456 * carr_pa is LE, must be native before write
7458 AdvWriteDWordLramNoSwap(iop_base
, ASC_MC_ICQ
, asc_dvc
->icq_sp
->carr_pa
);
7461 * Set-up the RISC->Host Initiator Response Queue (IRQ).
7463 if ((asc_dvc
->irq_sp
= asc_dvc
->carr_freelist
) == NULL
) {
7464 asc_dvc
->err_code
|= ASC_IERR_NO_CARRIER
;
7467 asc_dvc
->carr_freelist
= (ADV_CARR_T
*)
7468 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc
->irq_sp
->next_vpa
));
7471 * The first command completed by the RISC will be placed in
7474 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
7475 * completed the RISC will set the ASC_RQ_STOPPER bit.
7477 asc_dvc
->irq_sp
->next_vpa
= cpu_to_le32(ASC_CQ_STOPPER
);
7480 * Set RISC IRQ physical address start value.
7482 * carr_pa is LE, must be native before write *
7484 AdvWriteDWordLramNoSwap(iop_base
, ASC_MC_IRQ
, asc_dvc
->irq_sp
->carr_pa
);
7485 asc_dvc
->carr_pending_cnt
= 0;
7487 AdvWriteByteRegister(iop_base
, IOPB_INTR_ENABLES
,
7488 (ADV_INTR_ENABLE_HOST_INTR
|
7489 ADV_INTR_ENABLE_GLOBAL_INTR
));
7491 AdvReadWordLram(iop_base
, ASC_MC_CODE_BEGIN_ADDR
, word
);
7492 AdvWriteWordRegister(iop_base
, IOPW_PC
, word
);
7494 /* finally, finally, gentlemen, start your engine */
7495 AdvWriteWordRegister(iop_base
, IOPW_RISC_CSR
, ADV_RISC_CSR_RUN
);
7498 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7499 * Resets should be performed. The RISC has to be running
7500 * to issue a SCSI Bus Reset.
7502 if (asc_dvc
->bios_ctrl
& BIOS_CTRL_RESET_SCSI_BUS
) {
7504 * If the BIOS Signature is present in memory, restore the
7505 * BIOS Handshake Configuration Table and do not perform
7508 if (bios_mem
[(ASC_MC_BIOS_SIGNATURE
- ASC_MC_BIOSMEM
) / 2] ==
7511 * Restore per TID negotiated values.
7513 AdvWriteWordLram(iop_base
, ASC_MC_WDTR_ABLE
, wdtr_able
);
7514 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_ABLE
, sdtr_able
);
7515 AdvWriteWordLram(iop_base
, ASC_MC_TAGQNG_ABLE
,
7517 for (tid
= 0; tid
<= ADV_MAX_TID
; tid
++) {
7518 AdvWriteByteLram(iop_base
,
7519 ASC_MC_NUMBER_OF_MAX_CMD
+ tid
,
7523 if (AdvResetSB(asc_dvc
) != ADV_TRUE
) {
7524 warn_code
= ASC_WARN_BUSRESET_ERROR
;
7533 * Initialize the ASC-38C1600.
7535 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
7537 * For a non-fatal error return a warning code. If there are no warnings
7538 * then 0 is returned.
7540 * Needed after initialization for error recovery.
7542 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR
*asc_dvc
)
7544 AdvPortAddr iop_base
;
7554 ushort bios_mem
[ASC_MC_BIOSLEN
/ 2]; /* BIOS RISC Memory 0x40-0x8F. */
7555 ushort wdtr_able
, sdtr_able
, ppr_able
, tagqng_able
;
7556 uchar max_cmd
[ASC_MAX_TID
+ 1];
7558 /* If there is already an error, don't continue. */
7559 if (asc_dvc
->err_code
!= 0) {
7564 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
7566 if (asc_dvc
->chip_type
!= ADV_CHIP_ASC38C1600
) {
7567 asc_dvc
->err_code
= ASC_IERR_BAD_CHIPTYPE
;
7572 iop_base
= asc_dvc
->iop_base
;
7575 * Save the RISC memory BIOS region before writing the microcode.
7576 * The BIOS may already be loaded and using its RISC LRAM region
7577 * so its region must be saved and restored.
7579 * Note: This code makes the assumption, which is currently true,
7580 * that a chip reset does not clear RISC LRAM.
7582 for (i
= 0; i
< ASC_MC_BIOSLEN
/ 2; i
++) {
7583 AdvReadWordLram(iop_base
, ASC_MC_BIOSMEM
+ (2 * i
),
7588 * Save current per TID negotiated values.
7590 AdvReadWordLram(iop_base
, ASC_MC_WDTR_ABLE
, wdtr_able
);
7591 AdvReadWordLram(iop_base
, ASC_MC_SDTR_ABLE
, sdtr_able
);
7592 AdvReadWordLram(iop_base
, ASC_MC_PPR_ABLE
, ppr_able
);
7593 AdvReadWordLram(iop_base
, ASC_MC_TAGQNG_ABLE
, tagqng_able
);
7594 for (tid
= 0; tid
<= ASC_MAX_TID
; tid
++) {
7595 AdvReadByteLram(iop_base
, ASC_MC_NUMBER_OF_MAX_CMD
+ tid
,
7600 * RAM BIST (Built-In Self Test)
7602 * Address : I/O base + offset 0x38h register (byte).
7603 * Function: Bit 7-6(RW) : RAM mode
7604 * Normal Mode : 0x00
7605 * Pre-test Mode : 0x40
7606 * RAM Test Mode : 0x80
7608 * Bit 4(RO) : Done bit
7609 * Bit 3-0(RO) : Status
7611 * Int_RAM Error : 0x04
7616 * Note: RAM BIST code should be put right here, before loading the
7617 * microcode and after saving the RISC memory BIOS region.
7623 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
7624 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
7625 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
7626 * to NORMAL_MODE, return an error too.
7628 for (i
= 0; i
< 2; i
++) {
7629 AdvWriteByteRegister(iop_base
, IOPB_RAM_BIST
, PRE_TEST_MODE
);
7630 mdelay(10); /* Wait for 10ms before reading back. */
7631 byte
= AdvReadByteRegister(iop_base
, IOPB_RAM_BIST
);
7632 if ((byte
& RAM_TEST_DONE
) == 0
7633 || (byte
& 0x0F) != PRE_TEST_VALUE
) {
7634 asc_dvc
->err_code
= ASC_IERR_BIST_PRE_TEST
;
7638 AdvWriteByteRegister(iop_base
, IOPB_RAM_BIST
, NORMAL_MODE
);
7639 mdelay(10); /* Wait for 10ms before reading back. */
7640 if (AdvReadByteRegister(iop_base
, IOPB_RAM_BIST
)
7642 asc_dvc
->err_code
= ASC_IERR_BIST_PRE_TEST
;
7648 * LRAM Test - It takes about 1.5 ms to run through the test.
7650 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
7651 * If Done bit not set or Status not 0, save register byte, set the
7652 * err_code, and return an error.
7654 AdvWriteByteRegister(iop_base
, IOPB_RAM_BIST
, RAM_TEST_MODE
);
7655 mdelay(10); /* Wait for 10ms before checking status. */
7657 byte
= AdvReadByteRegister(iop_base
, IOPB_RAM_BIST
);
7658 if ((byte
& RAM_TEST_DONE
) == 0 || (byte
& RAM_TEST_STATUS
) != 0) {
7659 /* Get here if Done bit not set or Status not 0. */
7660 asc_dvc
->bist_err_code
= byte
; /* for BIOS display message */
7661 asc_dvc
->err_code
= ASC_IERR_BIST_RAM_TEST
;
7665 /* We need to reset back to normal mode after LRAM test passes. */
7666 AdvWriteByteRegister(iop_base
, IOPB_RAM_BIST
, NORMAL_MODE
);
7668 asc_dvc
->err_code
= AdvLoadMicrocode(iop_base
, _adv_asc38C1600_buf
,
7669 _adv_asc38C1600_size
, ADV_38C1600_MEMSIZE
,
7670 _adv_asc38C1600_chksum
);
7671 if (asc_dvc
->err_code
)
7675 * Restore the RISC memory BIOS region.
7677 for (i
= 0; i
< ASC_MC_BIOSLEN
/ 2; i
++) {
7678 AdvWriteWordLram(iop_base
, ASC_MC_BIOSMEM
+ (2 * i
),
7683 * Calculate and write the microcode code checksum to the microcode
7684 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
7686 AdvReadWordLram(iop_base
, ASC_MC_CODE_BEGIN_ADDR
, begin_addr
);
7687 AdvReadWordLram(iop_base
, ASC_MC_CODE_END_ADDR
, end_addr
);
7689 AdvWriteWordRegister(iop_base
, IOPW_RAM_ADDR
, begin_addr
);
7690 for (word
= begin_addr
; word
< end_addr
; word
+= 2) {
7691 code_sum
+= AdvReadWordAutoIncLram(iop_base
);
7693 AdvWriteWordLram(iop_base
, ASC_MC_CODE_CHK_SUM
, code_sum
);
7696 * Read microcode version and date.
7698 AdvReadWordLram(iop_base
, ASC_MC_VERSION_DATE
,
7699 asc_dvc
->cfg
->mcode_date
);
7700 AdvReadWordLram(iop_base
, ASC_MC_VERSION_NUM
,
7701 asc_dvc
->cfg
->mcode_version
);
7704 * Set the chip type to indicate the ASC38C1600.
7706 AdvWriteWordLram(iop_base
, ASC_MC_CHIP_TYPE
, ADV_CHIP_ASC38C1600
);
7709 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
7710 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
7711 * cable detection and then we are able to read C_DET[3:0].
7713 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
7714 * Microcode Default Value' section below.
7716 scsi_cfg1
= AdvReadWordRegister(iop_base
, IOPW_SCSI_CFG1
);
7717 AdvWriteWordRegister(iop_base
, IOPW_SCSI_CFG1
,
7718 scsi_cfg1
| DIS_TERM_DRV
);
7721 * If the PCI Configuration Command Register "Parity Error Response
7722 * Control" Bit was clear (0), then set the microcode variable
7723 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
7724 * to ignore DMA parity errors.
7726 if (asc_dvc
->cfg
->control_flag
& CONTROL_FLAG_IGNORE_PERR
) {
7727 AdvReadWordLram(iop_base
, ASC_MC_CONTROL_FLAG
, word
);
7728 word
|= CONTROL_FLAG_IGNORE_PERR
;
7729 AdvWriteWordLram(iop_base
, ASC_MC_CONTROL_FLAG
, word
);
7733 * If the BIOS control flag AIPP (Asynchronous Information
7734 * Phase Protection) disable bit is not set, then set the firmware
7735 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
7736 * AIPP checking and encoding.
7738 if ((asc_dvc
->bios_ctrl
& BIOS_CTRL_AIPP_DIS
) == 0) {
7739 AdvReadWordLram(iop_base
, ASC_MC_CONTROL_FLAG
, word
);
7740 word
|= CONTROL_FLAG_ENABLE_AIPP
;
7741 AdvWriteWordLram(iop_base
, ASC_MC_CONTROL_FLAG
, word
);
7745 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
7746 * and START_CTL_TH [3:2].
7748 AdvWriteByteRegister(iop_base
, IOPB_DMA_CFG0
,
7749 FIFO_THRESH_80B
| START_CTL_TH
| READ_CMD_MRM
);
7752 * Microcode operating variables for WDTR, SDTR, and command tag
7753 * queuing will be set in slave_configure() based on what a
7754 * device reports it is capable of in Inquiry byte 7.
7756 * If SCSI Bus Resets have been disabled, then directly set
7757 * SDTR and WDTR from the EEPROM configuration. This will allow
7758 * the BIOS and warm boot to work without a SCSI bus hang on
7759 * the Inquiry caused by host and target mismatched DTR values.
7760 * Without the SCSI Bus Reset, before an Inquiry a device can't
7761 * be assumed to be in Asynchronous, Narrow mode.
7763 if ((asc_dvc
->bios_ctrl
& BIOS_CTRL_RESET_SCSI_BUS
) == 0) {
7764 AdvWriteWordLram(iop_base
, ASC_MC_WDTR_ABLE
,
7765 asc_dvc
->wdtr_able
);
7766 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_ABLE
,
7767 asc_dvc
->sdtr_able
);
7771 * Set microcode operating variables for DISC and SDTR_SPEED1,
7772 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
7773 * configuration values.
7775 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
7776 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
7777 * without determining here whether the device supports SDTR.
7779 AdvWriteWordLram(iop_base
, ASC_MC_DISC_ENABLE
,
7780 asc_dvc
->cfg
->disc_enable
);
7781 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_SPEED1
, asc_dvc
->sdtr_speed1
);
7782 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_SPEED2
, asc_dvc
->sdtr_speed2
);
7783 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_SPEED3
, asc_dvc
->sdtr_speed3
);
7784 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_SPEED4
, asc_dvc
->sdtr_speed4
);
7787 * Set SCSI_CFG0 Microcode Default Value.
7789 * The microcode will set the SCSI_CFG0 register using this value
7790 * after it is started below.
7792 AdvWriteWordLram(iop_base
, ASC_MC_DEFAULT_SCSI_CFG0
,
7793 PARITY_EN
| QUEUE_128
| SEL_TMO_LONG
| OUR_ID_EN
|
7794 asc_dvc
->chip_scsi_id
);
7797 * Calculate SCSI_CFG1 Microcode Default Value.
7799 * The microcode will set the SCSI_CFG1 register using this value
7800 * after it is started below.
7802 * Each ASC-38C1600 function has only two cable detect bits.
7803 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
7805 scsi_cfg1
= AdvReadWordRegister(iop_base
, IOPW_SCSI_CFG1
);
7808 * If the cable is reversed all of the SCSI_CTRL register signals
7809 * will be set. Check for and return an error if this condition is
7812 if ((AdvReadWordRegister(iop_base
, IOPW_SCSI_CTRL
) & 0x3F07) == 0x3F07) {
7813 asc_dvc
->err_code
|= ASC_IERR_REVERSED_CABLE
;
7818 * Each ASC-38C1600 function has two connectors. Only an HVD device
7819 * can not be connected to either connector. An LVD device or SE device
7820 * may be connected to either connecor. If an SE device is connected,
7821 * then at most Ultra speed (20 Mhz) can be used on both connectors.
7823 * If an HVD device is attached, return an error.
7825 if (scsi_cfg1
& HVD
) {
7826 asc_dvc
->err_code
|= ASC_IERR_HVD_DEVICE
;
7831 * Each function in the ASC-38C1600 uses only the SE cable detect and
7832 * termination because there are two connectors for each function. Each
7833 * function may use either LVD or SE mode. Corresponding the SE automatic
7834 * termination control EEPROM bits are used for each function. Each
7835 * function has its own EEPROM. If SE automatic control is enabled for
7836 * the function, then set the termination value based on a table listed
7839 * If manual termination is specified in the EEPROM for the function,
7840 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
7841 * ready to be 'ored' into SCSI_CFG1.
7843 if ((asc_dvc
->cfg
->termination
& TERM_SE
) == 0) {
7844 struct pci_dev
*pdev
= adv_dvc_to_pdev(asc_dvc
);
7845 /* SE automatic termination control is enabled. */
7846 switch (scsi_cfg1
& C_DET_SE
) {
7847 /* TERM_SE_HI: on, TERM_SE_LO: on */
7851 asc_dvc
->cfg
->termination
|= TERM_SE
;
7855 if (PCI_FUNC(pdev
->devfn
) == 0) {
7856 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
7858 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
7859 asc_dvc
->cfg
->termination
|= TERM_SE_HI
;
7866 * Clear any set TERM_SE bits.
7868 scsi_cfg1
&= ~TERM_SE
;
7871 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
7873 scsi_cfg1
|= (~asc_dvc
->cfg
->termination
& TERM_SE
);
7876 * Clear Big Endian and Terminator Polarity bits and set possibly
7877 * modified termination control bits in the Microcode SCSI_CFG1
7880 * Big Endian bit is not used even on big endian machines.
7882 scsi_cfg1
&= (~BIG_ENDIAN
& ~DIS_TERM_DRV
& ~TERM_POL
);
7885 * Set SCSI_CFG1 Microcode Default Value
7887 * Set possibly modified termination control bits in the Microcode
7888 * SCSI_CFG1 Register Value.
7890 * The microcode will set the SCSI_CFG1 register using this value
7891 * after it is started below.
7893 AdvWriteWordLram(iop_base
, ASC_MC_DEFAULT_SCSI_CFG1
, scsi_cfg1
);
7896 * Set MEM_CFG Microcode Default Value
7898 * The microcode will set the MEM_CFG register using this value
7899 * after it is started below.
7901 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7904 * ASC-38C1600 has 32KB internal memory.
7906 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
7907 * out a special 16K Adv Library and Microcode version. After the issue
7908 * resolved, we should turn back to the 32K support. Both a_condor.h and
7909 * mcode.sas files also need to be updated.
7911 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7912 * BIOS_EN | RAM_SZ_32KB);
7914 AdvWriteWordLram(iop_base
, ASC_MC_DEFAULT_MEM_CFG
,
7915 BIOS_EN
| RAM_SZ_16KB
);
7918 * Set SEL_MASK Microcode Default Value
7920 * The microcode will set the SEL_MASK register using this value
7921 * after it is started below.
7923 AdvWriteWordLram(iop_base
, ASC_MC_DEFAULT_SEL_MASK
,
7924 ADV_TID_TO_TIDMASK(asc_dvc
->chip_scsi_id
));
7926 AdvBuildCarrierFreelist(asc_dvc
);
7929 * Set-up the Host->RISC Initiator Command Queue (ICQ).
7931 if ((asc_dvc
->icq_sp
= asc_dvc
->carr_freelist
) == NULL
) {
7932 asc_dvc
->err_code
|= ASC_IERR_NO_CARRIER
;
7935 asc_dvc
->carr_freelist
= (ADV_CARR_T
*)
7936 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc
->icq_sp
->next_vpa
));
7939 * The first command issued will be placed in the stopper carrier.
7941 asc_dvc
->icq_sp
->next_vpa
= cpu_to_le32(ASC_CQ_STOPPER
);
7944 * Set RISC ICQ physical address start value. Initialize the
7945 * COMMA register to the same value otherwise the RISC will
7946 * prematurely detect a command is available.
7948 AdvWriteDWordLramNoSwap(iop_base
, ASC_MC_ICQ
, asc_dvc
->icq_sp
->carr_pa
);
7949 AdvWriteDWordRegister(iop_base
, IOPDW_COMMA
,
7950 le32_to_cpu(asc_dvc
->icq_sp
->carr_pa
));
7953 * Set-up the RISC->Host Initiator Response Queue (IRQ).
7955 if ((asc_dvc
->irq_sp
= asc_dvc
->carr_freelist
) == NULL
) {
7956 asc_dvc
->err_code
|= ASC_IERR_NO_CARRIER
;
7959 asc_dvc
->carr_freelist
= (ADV_CARR_T
*)
7960 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc
->irq_sp
->next_vpa
));
7963 * The first command completed by the RISC will be placed in
7966 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
7967 * completed the RISC will set the ASC_RQ_STOPPER bit.
7969 asc_dvc
->irq_sp
->next_vpa
= cpu_to_le32(ASC_CQ_STOPPER
);
7972 * Set RISC IRQ physical address start value.
7974 AdvWriteDWordLramNoSwap(iop_base
, ASC_MC_IRQ
, asc_dvc
->irq_sp
->carr_pa
);
7975 asc_dvc
->carr_pending_cnt
= 0;
7977 AdvWriteByteRegister(iop_base
, IOPB_INTR_ENABLES
,
7978 (ADV_INTR_ENABLE_HOST_INTR
|
7979 ADV_INTR_ENABLE_GLOBAL_INTR
));
7980 AdvReadWordLram(iop_base
, ASC_MC_CODE_BEGIN_ADDR
, word
);
7981 AdvWriteWordRegister(iop_base
, IOPW_PC
, word
);
7983 /* finally, finally, gentlemen, start your engine */
7984 AdvWriteWordRegister(iop_base
, IOPW_RISC_CSR
, ADV_RISC_CSR_RUN
);
7987 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7988 * Resets should be performed. The RISC has to be running
7989 * to issue a SCSI Bus Reset.
7991 if (asc_dvc
->bios_ctrl
& BIOS_CTRL_RESET_SCSI_BUS
) {
7993 * If the BIOS Signature is present in memory, restore the
7994 * per TID microcode operating variables.
7996 if (bios_mem
[(ASC_MC_BIOS_SIGNATURE
- ASC_MC_BIOSMEM
) / 2] ==
7999 * Restore per TID negotiated values.
8001 AdvWriteWordLram(iop_base
, ASC_MC_WDTR_ABLE
, wdtr_able
);
8002 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_ABLE
, sdtr_able
);
8003 AdvWriteWordLram(iop_base
, ASC_MC_PPR_ABLE
, ppr_able
);
8004 AdvWriteWordLram(iop_base
, ASC_MC_TAGQNG_ABLE
,
8006 for (tid
= 0; tid
<= ASC_MAX_TID
; tid
++) {
8007 AdvWriteByteLram(iop_base
,
8008 ASC_MC_NUMBER_OF_MAX_CMD
+ tid
,
8012 if (AdvResetSB(asc_dvc
) != ADV_TRUE
) {
8013 warn_code
= ASC_WARN_BUSRESET_ERROR
;
8022 * Reset chip and SCSI Bus.
8025 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
8026 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
8028 static int AdvResetChipAndSB(ADV_DVC_VAR
*asc_dvc
)
8031 ushort wdtr_able
, sdtr_able
, tagqng_able
;
8032 ushort ppr_able
= 0;
8033 uchar tid
, max_cmd
[ADV_MAX_TID
+ 1];
8034 AdvPortAddr iop_base
;
8037 iop_base
= asc_dvc
->iop_base
;
8040 * Save current per TID negotiated values.
8042 AdvReadWordLram(iop_base
, ASC_MC_WDTR_ABLE
, wdtr_able
);
8043 AdvReadWordLram(iop_base
, ASC_MC_SDTR_ABLE
, sdtr_able
);
8044 if (asc_dvc
->chip_type
== ADV_CHIP_ASC38C1600
) {
8045 AdvReadWordLram(iop_base
, ASC_MC_PPR_ABLE
, ppr_able
);
8047 AdvReadWordLram(iop_base
, ASC_MC_TAGQNG_ABLE
, tagqng_able
);
8048 for (tid
= 0; tid
<= ADV_MAX_TID
; tid
++) {
8049 AdvReadByteLram(iop_base
, ASC_MC_NUMBER_OF_MAX_CMD
+ tid
,
8054 * Force the AdvInitAsc3550/38C0800Driver() function to
8055 * perform a SCSI Bus Reset by clearing the BIOS signature word.
8056 * The initialization functions assumes a SCSI Bus Reset is not
8057 * needed if the BIOS signature word is present.
8059 AdvReadWordLram(iop_base
, ASC_MC_BIOS_SIGNATURE
, bios_sig
);
8060 AdvWriteWordLram(iop_base
, ASC_MC_BIOS_SIGNATURE
, 0);
8063 * Stop chip and reset it.
8065 AdvWriteWordRegister(iop_base
, IOPW_RISC_CSR
, ADV_RISC_CSR_STOP
);
8066 AdvWriteWordRegister(iop_base
, IOPW_CTRL_REG
, ADV_CTRL_REG_CMD_RESET
);
8068 AdvWriteWordRegister(iop_base
, IOPW_CTRL_REG
,
8069 ADV_CTRL_REG_CMD_WR_IO_REG
);
8072 * Reset Adv Library error code, if any, and try
8073 * re-initializing the chip.
8075 asc_dvc
->err_code
= 0;
8076 if (asc_dvc
->chip_type
== ADV_CHIP_ASC38C1600
) {
8077 status
= AdvInitAsc38C1600Driver(asc_dvc
);
8078 } else if (asc_dvc
->chip_type
== ADV_CHIP_ASC38C0800
) {
8079 status
= AdvInitAsc38C0800Driver(asc_dvc
);
8081 status
= AdvInitAsc3550Driver(asc_dvc
);
8084 /* Translate initialization return value to status value. */
8092 * Restore the BIOS signature word.
8094 AdvWriteWordLram(iop_base
, ASC_MC_BIOS_SIGNATURE
, bios_sig
);
8097 * Restore per TID negotiated values.
8099 AdvWriteWordLram(iop_base
, ASC_MC_WDTR_ABLE
, wdtr_able
);
8100 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_ABLE
, sdtr_able
);
8101 if (asc_dvc
->chip_type
== ADV_CHIP_ASC38C1600
) {
8102 AdvWriteWordLram(iop_base
, ASC_MC_PPR_ABLE
, ppr_able
);
8104 AdvWriteWordLram(iop_base
, ASC_MC_TAGQNG_ABLE
, tagqng_able
);
8105 for (tid
= 0; tid
<= ADV_MAX_TID
; tid
++) {
8106 AdvWriteByteLram(iop_base
, ASC_MC_NUMBER_OF_MAX_CMD
+ tid
,
8114 * adv_async_callback() - Adv Library asynchronous event callback function.
8116 static void adv_async_callback(ADV_DVC_VAR
*adv_dvc_varp
, uchar code
)
8119 case ADV_ASYNC_SCSI_BUS_RESET_DET
:
8121 * The firmware detected a SCSI Bus reset.
8123 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
8126 case ADV_ASYNC_RDMA_FAILURE
:
8128 * Handle RDMA failure by resetting the SCSI Bus and
8129 * possibly the chip if it is unresponsive. Log the error
8130 * with a unique code.
8132 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
8133 AdvResetChipAndSB(adv_dvc_varp
);
8136 case ADV_HOST_SCSI_BUS_RESET
:
8138 * Host generated SCSI bus reset occurred.
8140 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
8144 ASC_DBG(0, "unknown code 0x%x\n", code
);
8150 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
8152 * Callback function for the Wide SCSI Adv Library.
8154 static void adv_isr_callback(ADV_DVC_VAR
*adv_dvc_varp
, ADV_SCSI_REQ_Q
*scsiqp
)
8156 struct asc_board
*boardp
;
8158 adv_sgblk_t
*sgblkp
;
8159 struct scsi_cmnd
*scp
;
8160 struct Scsi_Host
*shost
;
8163 ASC_DBG(1, "adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
8164 (ulong
)adv_dvc_varp
, (ulong
)scsiqp
);
8165 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp
);
8168 * Get the adv_req_t structure for the command that has been
8169 * completed. The adv_req_t structure actually contains the
8170 * completed ADV_SCSI_REQ_Q structure.
8172 reqp
= (adv_req_t
*)ADV_U32_TO_VADDR(scsiqp
->srb_ptr
);
8173 ASC_DBG(1, "reqp 0x%lx\n", (ulong
)reqp
);
8175 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
8180 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
8181 * command that has been completed.
8183 * Note: The adv_req_t request structure and adv_sgblk_t structure,
8184 * if any, are dropped, because a board structure pointer can not be
8188 ASC_DBG(1, "scp 0x%p\n", scp
);
8191 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
8194 ASC_DBG_PRT_CDB(2, scp
->cmnd
, scp
->cmd_len
);
8196 shost
= scp
->device
->host
;
8197 ASC_STATS(shost
, callback
);
8198 ASC_DBG(1, "shost 0x%p\n", shost
);
8200 boardp
= shost_priv(shost
);
8201 BUG_ON(adv_dvc_varp
!= &boardp
->dvc_var
.adv_dvc_var
);
8204 * 'done_status' contains the command's ending status.
8206 switch (scsiqp
->done_status
) {
8208 ASC_DBG(2, "QD_NO_ERROR\n");
8212 * Check for an underrun condition.
8214 * If there was no error and an underrun condition, then
8215 * then return the number of underrun bytes.
8217 resid_cnt
= le32_to_cpu(scsiqp
->data_cnt
);
8218 if (scsi_bufflen(scp
) != 0 && resid_cnt
!= 0 &&
8219 resid_cnt
<= scsi_bufflen(scp
)) {
8220 ASC_DBG(1, "underrun condition %lu bytes\n",
8222 scsi_set_resid(scp
, resid_cnt
);
8227 ASC_DBG(2, "QD_WITH_ERROR\n");
8228 switch (scsiqp
->host_status
) {
8229 case QHSTA_NO_ERROR
:
8230 if (scsiqp
->scsi_status
== SAM_STAT_CHECK_CONDITION
) {
8231 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
8232 ASC_DBG_PRT_SENSE(2, scp
->sense_buffer
,
8233 sizeof(scp
->sense_buffer
));
8235 * Note: The 'status_byte()' macro used by
8236 * target drivers defined in scsi.h shifts the
8237 * status byte returned by host drivers right
8238 * by 1 bit. This is why target drivers also
8239 * use right shifted status byte definitions.
8240 * For instance target drivers use
8241 * CHECK_CONDITION, defined to 0x1, instead of
8242 * the SCSI defined check condition value of
8243 * 0x2. Host drivers are supposed to return
8244 * the status byte as it is defined by SCSI.
8246 scp
->result
= DRIVER_BYTE(DRIVER_SENSE
) |
8247 STATUS_BYTE(scsiqp
->scsi_status
);
8249 scp
->result
= STATUS_BYTE(scsiqp
->scsi_status
);
8254 /* Some other QHSTA error occurred. */
8255 ASC_DBG(1, "host_status 0x%x\n", scsiqp
->host_status
);
8256 scp
->result
= HOST_BYTE(DID_BAD_TARGET
);
8261 case QD_ABORTED_BY_HOST
:
8262 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
8264 HOST_BYTE(DID_ABORT
) | STATUS_BYTE(scsiqp
->scsi_status
);
8268 ASC_DBG(1, "done_status 0x%x\n", scsiqp
->done_status
);
8270 HOST_BYTE(DID_ERROR
) | STATUS_BYTE(scsiqp
->scsi_status
);
8275 * If the 'init_tidmask' bit isn't already set for the target and the
8276 * current request finished normally, then set the bit for the target
8277 * to indicate that a device is present.
8279 if ((boardp
->init_tidmask
& ADV_TID_TO_TIDMASK(scp
->device
->id
)) == 0 &&
8280 scsiqp
->done_status
== QD_NO_ERROR
&&
8281 scsiqp
->host_status
== QHSTA_NO_ERROR
) {
8282 boardp
->init_tidmask
|= ADV_TID_TO_TIDMASK(scp
->device
->id
);
8288 * Free all 'adv_sgblk_t' structures allocated for the request.
8290 while ((sgblkp
= reqp
->sgblkp
) != NULL
) {
8291 /* Remove 'sgblkp' from the request list. */
8292 reqp
->sgblkp
= sgblkp
->next_sgblkp
;
8294 /* Add 'sgblkp' to the board free list. */
8295 sgblkp
->next_sgblkp
= boardp
->adv_sgblkp
;
8296 boardp
->adv_sgblkp
= sgblkp
;
8300 * Free the adv_req_t structure used with the command by adding
8301 * it back to the board free list.
8303 reqp
->next_reqp
= boardp
->adv_reqp
;
8304 boardp
->adv_reqp
= reqp
;
8306 ASC_DBG(1, "done\n");
8310 * Adv Library Interrupt Service Routine
8312 * This function is called by a driver's interrupt service routine.
8313 * The function disables and re-enables interrupts.
8315 * When a microcode idle command is completed, the ADV_DVC_VAR
8316 * 'idle_cmd_done' field is set to ADV_TRUE.
8318 * Note: AdvISR() can be called when interrupts are disabled or even
8319 * when there is no hardware interrupt condition present. It will
8320 * always check for completed idle commands and microcode requests.
8321 * This is an important feature that shouldn't be changed because it
8322 * allows commands to be completed from polling mode loops.
8325 * ADV_TRUE(1) - interrupt was pending
8326 * ADV_FALSE(0) - no interrupt was pending
8328 static int AdvISR(ADV_DVC_VAR
*asc_dvc
)
8330 AdvPortAddr iop_base
;
8333 ADV_CARR_T
*free_carrp
;
8334 ADV_VADDR irq_next_vpa
;
8335 ADV_SCSI_REQ_Q
*scsiq
;
8337 iop_base
= asc_dvc
->iop_base
;
8339 /* Reading the register clears the interrupt. */
8340 int_stat
= AdvReadByteRegister(iop_base
, IOPB_INTR_STATUS_REG
);
8342 if ((int_stat
& (ADV_INTR_STATUS_INTRA
| ADV_INTR_STATUS_INTRB
|
8343 ADV_INTR_STATUS_INTRC
)) == 0) {
8348 * Notify the driver of an asynchronous microcode condition by
8349 * calling the adv_async_callback function. The function
8350 * is passed the microcode ASC_MC_INTRB_CODE byte value.
8352 if (int_stat
& ADV_INTR_STATUS_INTRB
) {
8355 AdvReadByteLram(iop_base
, ASC_MC_INTRB_CODE
, intrb_code
);
8357 if (asc_dvc
->chip_type
== ADV_CHIP_ASC3550
||
8358 asc_dvc
->chip_type
== ADV_CHIP_ASC38C0800
) {
8359 if (intrb_code
== ADV_ASYNC_CARRIER_READY_FAILURE
&&
8360 asc_dvc
->carr_pending_cnt
!= 0) {
8361 AdvWriteByteRegister(iop_base
, IOPB_TICKLE
,
8363 if (asc_dvc
->chip_type
== ADV_CHIP_ASC3550
) {
8364 AdvWriteByteRegister(iop_base
,
8371 adv_async_callback(asc_dvc
, intrb_code
);
8375 * Check if the IRQ stopper carrier contains a completed request.
8377 while (((irq_next_vpa
=
8378 le32_to_cpu(asc_dvc
->irq_sp
->next_vpa
)) & ASC_RQ_DONE
) != 0) {
8380 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
8381 * The RISC will have set 'areq_vpa' to a virtual address.
8383 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
8384 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
8385 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
8386 * in AdvExeScsiQueue().
8388 scsiq
= (ADV_SCSI_REQ_Q
*)
8389 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc
->irq_sp
->areq_vpa
));
8392 * Request finished with good status and the queue was not
8393 * DMAed to host memory by the firmware. Set all status fields
8394 * to indicate good status.
8396 if ((irq_next_vpa
& ASC_RQ_GOOD
) != 0) {
8397 scsiq
->done_status
= QD_NO_ERROR
;
8398 scsiq
->host_status
= scsiq
->scsi_status
= 0;
8399 scsiq
->data_cnt
= 0L;
8403 * Advance the stopper pointer to the next carrier
8404 * ignoring the lower four bits. Free the previous
8407 free_carrp
= asc_dvc
->irq_sp
;
8408 asc_dvc
->irq_sp
= (ADV_CARR_T
*)
8409 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa
));
8411 free_carrp
->next_vpa
=
8412 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc
->carr_freelist
));
8413 asc_dvc
->carr_freelist
= free_carrp
;
8414 asc_dvc
->carr_pending_cnt
--;
8416 target_bit
= ADV_TID_TO_TIDMASK(scsiq
->target_id
);
8419 * Clear request microcode control flag.
8424 * Notify the driver of the completed request by passing
8425 * the ADV_SCSI_REQ_Q pointer to its callback function.
8427 scsiq
->a_flag
|= ADV_SCSIQ_DONE
;
8428 adv_isr_callback(asc_dvc
, scsiq
);
8430 * Note: After the driver callback function is called, 'scsiq'
8431 * can no longer be referenced.
8433 * Fall through and continue processing other completed
8440 static int AscSetLibErrorCode(ASC_DVC_VAR
*asc_dvc
, ushort err_code
)
8442 if (asc_dvc
->err_code
== 0) {
8443 asc_dvc
->err_code
= err_code
;
8444 AscWriteLramWord(asc_dvc
->iop_base
, ASCV_ASCDVC_ERR_CODE_W
,
8450 static void AscAckInterrupt(PortAddr iop_base
)
8458 risc_flag
= AscReadLramByte(iop_base
, ASCV_RISC_FLAG_B
);
8459 if (loop
++ > 0x7FFF) {
8462 } while ((risc_flag
& ASC_RISC_FLAG_GEN_INT
) != 0);
8464 AscReadLramByte(iop_base
,
8465 ASCV_HOST_FLAG_B
) & (~ASC_HOST_FLAG_ACK_INT
);
8466 AscWriteLramByte(iop_base
, ASCV_HOST_FLAG_B
,
8467 (uchar
)(host_flag
| ASC_HOST_FLAG_ACK_INT
));
8468 AscSetChipStatus(iop_base
, CIW_INT_ACK
);
8470 while (AscGetChipStatus(iop_base
) & CSW_INT_PENDING
) {
8471 AscSetChipStatus(iop_base
, CIW_INT_ACK
);
8476 AscWriteLramByte(iop_base
, ASCV_HOST_FLAG_B
, host_flag
);
8479 static uchar
AscGetSynPeriodIndex(ASC_DVC_VAR
*asc_dvc
, uchar syn_time
)
8481 const uchar
*period_table
;
8486 period_table
= asc_dvc
->sdtr_period_tbl
;
8487 max_index
= (int)asc_dvc
->max_sdtr_index
;
8488 min_index
= (int)asc_dvc
->min_sdtr_index
;
8489 if ((syn_time
<= period_table
[max_index
])) {
8490 for (i
= min_index
; i
< (max_index
- 1); i
++) {
8491 if (syn_time
<= period_table
[i
]) {
8495 return (uchar
)max_index
;
8497 return (uchar
)(max_index
+ 1);
8502 AscMsgOutSDTR(ASC_DVC_VAR
*asc_dvc
, uchar sdtr_period
, uchar sdtr_offset
)
8505 uchar sdtr_period_index
;
8508 iop_base
= asc_dvc
->iop_base
;
8509 sdtr_buf
.msg_type
= EXTENDED_MESSAGE
;
8510 sdtr_buf
.msg_len
= MS_SDTR_LEN
;
8511 sdtr_buf
.msg_req
= EXTENDED_SDTR
;
8512 sdtr_buf
.xfer_period
= sdtr_period
;
8513 sdtr_offset
&= ASC_SYN_MAX_OFFSET
;
8514 sdtr_buf
.req_ack_offset
= sdtr_offset
;
8515 sdtr_period_index
= AscGetSynPeriodIndex(asc_dvc
, sdtr_period
);
8516 if (sdtr_period_index
<= asc_dvc
->max_sdtr_index
) {
8517 AscMemWordCopyPtrToLram(iop_base
, ASCV_MSGOUT_BEG
,
8519 sizeof(EXT_MSG
) >> 1);
8520 return ((sdtr_period_index
<< 4) | sdtr_offset
);
8522 sdtr_buf
.req_ack_offset
= 0;
8523 AscMemWordCopyPtrToLram(iop_base
, ASCV_MSGOUT_BEG
,
8525 sizeof(EXT_MSG
) >> 1);
8531 AscCalSDTRData(ASC_DVC_VAR
*asc_dvc
, uchar sdtr_period
, uchar syn_offset
)
8534 uchar sdtr_period_ix
;
8536 sdtr_period_ix
= AscGetSynPeriodIndex(asc_dvc
, sdtr_period
);
8537 if (sdtr_period_ix
> asc_dvc
->max_sdtr_index
)
8539 byte
= (sdtr_period_ix
<< 4) | (syn_offset
& ASC_SYN_MAX_OFFSET
);
8543 static int AscSetChipSynRegAtID(PortAddr iop_base
, uchar id
, uchar sdtr_data
)
8545 ASC_SCSI_BIT_ID_TYPE org_id
;
8549 AscSetBank(iop_base
, 1);
8550 org_id
= AscReadChipDvcID(iop_base
);
8551 for (i
= 0; i
<= ASC_MAX_TID
; i
++) {
8552 if (org_id
== (0x01 << i
))
8555 org_id
= (ASC_SCSI_BIT_ID_TYPE
) i
;
8556 AscWriteChipDvcID(iop_base
, id
);
8557 if (AscReadChipDvcID(iop_base
) == (0x01 << id
)) {
8558 AscSetBank(iop_base
, 0);
8559 AscSetChipSyn(iop_base
, sdtr_data
);
8560 if (AscGetChipSyn(iop_base
) != sdtr_data
) {
8566 AscSetBank(iop_base
, 1);
8567 AscWriteChipDvcID(iop_base
, org_id
);
8568 AscSetBank(iop_base
, 0);
8572 static void AscSetChipSDTR(PortAddr iop_base
, uchar sdtr_data
, uchar tid_no
)
8574 AscSetChipSynRegAtID(iop_base
, tid_no
, sdtr_data
);
8575 AscPutMCodeSDTRDoneAtID(iop_base
, tid_no
, sdtr_data
);
8578 static int AscIsrChipHalted(ASC_DVC_VAR
*asc_dvc
)
8584 ushort int_halt_code
;
8585 ASC_SCSI_BIT_ID_TYPE scsi_busy
;
8586 ASC_SCSI_BIT_ID_TYPE target_id
;
8593 uchar q_cntl
, tid_no
;
8597 struct asc_board
*boardp
;
8599 BUG_ON(!asc_dvc
->drv_ptr
);
8600 boardp
= asc_dvc
->drv_ptr
;
8602 iop_base
= asc_dvc
->iop_base
;
8603 int_halt_code
= AscReadLramWord(iop_base
, ASCV_HALTCODE_W
);
8605 halt_qp
= AscReadLramByte(iop_base
, ASCV_CURCDB_B
);
8606 halt_q_addr
= ASC_QNO_TO_QADDR(halt_qp
);
8607 target_ix
= AscReadLramByte(iop_base
,
8608 (ushort
)(halt_q_addr
+
8609 (ushort
)ASC_SCSIQ_B_TARGET_IX
));
8610 q_cntl
= AscReadLramByte(iop_base
,
8611 (ushort
)(halt_q_addr
+ (ushort
)ASC_SCSIQ_B_CNTL
));
8612 tid_no
= ASC_TIX_TO_TID(target_ix
);
8613 target_id
= (uchar
)ASC_TID_TO_TARGET_ID(tid_no
);
8614 if (asc_dvc
->pci_fix_asyn_xfer
& target_id
) {
8615 asyn_sdtr
= ASYN_SDTR_DATA_FIX_PCI_REV_AB
;
8619 if (int_halt_code
== ASC_HALT_DISABLE_ASYN_USE_SYN_FIX
) {
8620 if (asc_dvc
->pci_fix_asyn_xfer
& target_id
) {
8621 AscSetChipSDTR(iop_base
, 0, tid_no
);
8622 boardp
->sdtr_data
[tid_no
] = 0;
8624 AscWriteLramWord(iop_base
, ASCV_HALTCODE_W
, 0);
8626 } else if (int_halt_code
== ASC_HALT_ENABLE_ASYN_USE_SYN_FIX
) {
8627 if (asc_dvc
->pci_fix_asyn_xfer
& target_id
) {
8628 AscSetChipSDTR(iop_base
, asyn_sdtr
, tid_no
);
8629 boardp
->sdtr_data
[tid_no
] = asyn_sdtr
;
8631 AscWriteLramWord(iop_base
, ASCV_HALTCODE_W
, 0);
8633 } else if (int_halt_code
== ASC_HALT_EXTMSG_IN
) {
8634 AscMemWordCopyPtrFromLram(iop_base
,
8637 sizeof(EXT_MSG
) >> 1);
8639 if (ext_msg
.msg_type
== EXTENDED_MESSAGE
&&
8640 ext_msg
.msg_req
== EXTENDED_SDTR
&&
8641 ext_msg
.msg_len
== MS_SDTR_LEN
) {
8643 if ((ext_msg
.req_ack_offset
> ASC_SYN_MAX_OFFSET
)) {
8645 sdtr_accept
= FALSE
;
8646 ext_msg
.req_ack_offset
= ASC_SYN_MAX_OFFSET
;
8648 if ((ext_msg
.xfer_period
<
8649 asc_dvc
->sdtr_period_tbl
[asc_dvc
->min_sdtr_index
])
8650 || (ext_msg
.xfer_period
>
8651 asc_dvc
->sdtr_period_tbl
[asc_dvc
->
8653 sdtr_accept
= FALSE
;
8654 ext_msg
.xfer_period
=
8655 asc_dvc
->sdtr_period_tbl
[asc_dvc
->
8660 AscCalSDTRData(asc_dvc
, ext_msg
.xfer_period
,
8661 ext_msg
.req_ack_offset
);
8662 if ((sdtr_data
== 0xFF)) {
8664 q_cntl
|= QC_MSG_OUT
;
8665 asc_dvc
->init_sdtr
&= ~target_id
;
8666 asc_dvc
->sdtr_done
&= ~target_id
;
8667 AscSetChipSDTR(iop_base
, asyn_sdtr
,
8669 boardp
->sdtr_data
[tid_no
] = asyn_sdtr
;
8672 if (ext_msg
.req_ack_offset
== 0) {
8674 q_cntl
&= ~QC_MSG_OUT
;
8675 asc_dvc
->init_sdtr
&= ~target_id
;
8676 asc_dvc
->sdtr_done
&= ~target_id
;
8677 AscSetChipSDTR(iop_base
, asyn_sdtr
, tid_no
);
8679 if (sdtr_accept
&& (q_cntl
& QC_MSG_OUT
)) {
8680 q_cntl
&= ~QC_MSG_OUT
;
8681 asc_dvc
->sdtr_done
|= target_id
;
8682 asc_dvc
->init_sdtr
|= target_id
;
8683 asc_dvc
->pci_fix_asyn_xfer
&=
8686 AscCalSDTRData(asc_dvc
,
8687 ext_msg
.xfer_period
,
8690 AscSetChipSDTR(iop_base
, sdtr_data
,
8692 boardp
->sdtr_data
[tid_no
] = sdtr_data
;
8694 q_cntl
|= QC_MSG_OUT
;
8695 AscMsgOutSDTR(asc_dvc
,
8696 ext_msg
.xfer_period
,
8697 ext_msg
.req_ack_offset
);
8698 asc_dvc
->pci_fix_asyn_xfer
&=
8701 AscCalSDTRData(asc_dvc
,
8702 ext_msg
.xfer_period
,
8705 AscSetChipSDTR(iop_base
, sdtr_data
,
8707 boardp
->sdtr_data
[tid_no
] = sdtr_data
;
8708 asc_dvc
->sdtr_done
|= target_id
;
8709 asc_dvc
->init_sdtr
|= target_id
;
8713 AscWriteLramByte(iop_base
,
8714 (ushort
)(halt_q_addr
+
8715 (ushort
)ASC_SCSIQ_B_CNTL
),
8717 AscWriteLramWord(iop_base
, ASCV_HALTCODE_W
, 0);
8719 } else if (ext_msg
.msg_type
== EXTENDED_MESSAGE
&&
8720 ext_msg
.msg_req
== EXTENDED_WDTR
&&
8721 ext_msg
.msg_len
== MS_WDTR_LEN
) {
8723 ext_msg
.wdtr_width
= 0;
8724 AscMemWordCopyPtrToLram(iop_base
,
8727 sizeof(EXT_MSG
) >> 1);
8728 q_cntl
|= QC_MSG_OUT
;
8729 AscWriteLramByte(iop_base
,
8730 (ushort
)(halt_q_addr
+
8731 (ushort
)ASC_SCSIQ_B_CNTL
),
8733 AscWriteLramWord(iop_base
, ASCV_HALTCODE_W
, 0);
8737 ext_msg
.msg_type
= MESSAGE_REJECT
;
8738 AscMemWordCopyPtrToLram(iop_base
,
8741 sizeof(EXT_MSG
) >> 1);
8742 q_cntl
|= QC_MSG_OUT
;
8743 AscWriteLramByte(iop_base
,
8744 (ushort
)(halt_q_addr
+
8745 (ushort
)ASC_SCSIQ_B_CNTL
),
8747 AscWriteLramWord(iop_base
, ASCV_HALTCODE_W
, 0);
8750 } else if (int_halt_code
== ASC_HALT_CHK_CONDITION
) {
8752 q_cntl
|= QC_REQ_SENSE
;
8754 if ((asc_dvc
->init_sdtr
& target_id
) != 0) {
8756 asc_dvc
->sdtr_done
&= ~target_id
;
8758 sdtr_data
= AscGetMCodeInitSDTRAtID(iop_base
, tid_no
);
8759 q_cntl
|= QC_MSG_OUT
;
8760 AscMsgOutSDTR(asc_dvc
,
8762 sdtr_period_tbl
[(sdtr_data
>> 4) &
8766 (uchar
)(sdtr_data
& (uchar
)
8767 ASC_SYN_MAX_OFFSET
));
8770 AscWriteLramByte(iop_base
,
8771 (ushort
)(halt_q_addr
+
8772 (ushort
)ASC_SCSIQ_B_CNTL
), q_cntl
);
8774 tag_code
= AscReadLramByte(iop_base
,
8775 (ushort
)(halt_q_addr
+ (ushort
)
8776 ASC_SCSIQ_B_TAG_CODE
));
8778 if ((asc_dvc
->pci_fix_asyn_xfer
& target_id
)
8779 && !(asc_dvc
->pci_fix_asyn_xfer_always
& target_id
)
8782 tag_code
|= (ASC_TAG_FLAG_DISABLE_DISCONNECT
8783 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX
);
8786 AscWriteLramByte(iop_base
,
8787 (ushort
)(halt_q_addr
+
8788 (ushort
)ASC_SCSIQ_B_TAG_CODE
),
8791 q_status
= AscReadLramByte(iop_base
,
8792 (ushort
)(halt_q_addr
+ (ushort
)
8793 ASC_SCSIQ_B_STATUS
));
8794 q_status
|= (QS_READY
| QS_BUSY
);
8795 AscWriteLramByte(iop_base
,
8796 (ushort
)(halt_q_addr
+
8797 (ushort
)ASC_SCSIQ_B_STATUS
),
8800 scsi_busy
= AscReadLramByte(iop_base
, (ushort
)ASCV_SCSIBUSY_B
);
8801 scsi_busy
&= ~target_id
;
8802 AscWriteLramByte(iop_base
, (ushort
)ASCV_SCSIBUSY_B
, scsi_busy
);
8804 AscWriteLramWord(iop_base
, ASCV_HALTCODE_W
, 0);
8806 } else if (int_halt_code
== ASC_HALT_SDTR_REJECTED
) {
8808 AscMemWordCopyPtrFromLram(iop_base
,
8811 sizeof(EXT_MSG
) >> 1);
8813 if ((out_msg
.msg_type
== EXTENDED_MESSAGE
) &&
8814 (out_msg
.msg_len
== MS_SDTR_LEN
) &&
8815 (out_msg
.msg_req
== EXTENDED_SDTR
)) {
8817 asc_dvc
->init_sdtr
&= ~target_id
;
8818 asc_dvc
->sdtr_done
&= ~target_id
;
8819 AscSetChipSDTR(iop_base
, asyn_sdtr
, tid_no
);
8820 boardp
->sdtr_data
[tid_no
] = asyn_sdtr
;
8822 q_cntl
&= ~QC_MSG_OUT
;
8823 AscWriteLramByte(iop_base
,
8824 (ushort
)(halt_q_addr
+
8825 (ushort
)ASC_SCSIQ_B_CNTL
), q_cntl
);
8826 AscWriteLramWord(iop_base
, ASCV_HALTCODE_W
, 0);
8828 } else if (int_halt_code
== ASC_HALT_SS_QUEUE_FULL
) {
8830 scsi_status
= AscReadLramByte(iop_base
,
8831 (ushort
)((ushort
)halt_q_addr
+
8833 ASC_SCSIQ_SCSI_STATUS
));
8835 AscReadLramByte(iop_base
,
8836 (ushort
)((ushort
)ASC_QADR_BEG
+
8837 (ushort
)target_ix
));
8838 if ((cur_dvc_qng
> 0) && (asc_dvc
->cur_dvc_qng
[tid_no
] > 0)) {
8840 scsi_busy
= AscReadLramByte(iop_base
,
8841 (ushort
)ASCV_SCSIBUSY_B
);
8842 scsi_busy
|= target_id
;
8843 AscWriteLramByte(iop_base
,
8844 (ushort
)ASCV_SCSIBUSY_B
, scsi_busy
);
8845 asc_dvc
->queue_full_or_busy
|= target_id
;
8847 if (scsi_status
== SAM_STAT_TASK_SET_FULL
) {
8848 if (cur_dvc_qng
> ASC_MIN_TAGGED_CMD
) {
8850 asc_dvc
->max_dvc_qng
[tid_no
] =
8853 AscWriteLramByte(iop_base
,
8855 ASCV_MAX_DVC_QNG_BEG
8861 * Set the device queue depth to the
8862 * number of active requests when the
8863 * QUEUE FULL condition was encountered.
8865 boardp
->queue_full
|= target_id
;
8866 boardp
->queue_full_cnt
[tid_no
] =
8871 AscWriteLramWord(iop_base
, ASCV_HALTCODE_W
, 0);
8874 #if CC_VERY_LONG_SG_LIST
8875 else if (int_halt_code
== ASC_HALT_HOST_COPY_SG_LIST_TO_RISC
) {
8879 uchar first_sg_wk_q_no
;
8880 ASC_SCSI_Q
*scsiq
; /* Ptr to driver request. */
8881 ASC_SG_HEAD
*sg_head
; /* Ptr to driver SG request. */
8882 ASC_SG_LIST_Q scsi_sg_q
; /* Structure written to queue. */
8883 ushort sg_list_dwords
;
8884 ushort sg_entry_cnt
;
8888 q_no
= AscReadLramByte(iop_base
, (ushort
)ASCV_REQ_SG_LIST_QP
);
8889 if (q_no
== ASC_QLINK_END
)
8892 q_addr
= ASC_QNO_TO_QADDR(q_no
);
8895 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
8896 * structure pointer using a macro provided by the driver.
8897 * The ASC_SCSI_REQ pointer provides a pointer to the
8898 * host ASC_SG_HEAD structure.
8900 /* Read request's SRB pointer. */
8901 scsiq
= (ASC_SCSI_Q
*)
8902 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base
,
8905 ASC_SCSIQ_D_SRBPTR
))));
8908 * Get request's first and working SG queue.
8910 sg_wk_q_no
= AscReadLramByte(iop_base
,
8912 ASC_SCSIQ_B_SG_WK_QP
));
8914 first_sg_wk_q_no
= AscReadLramByte(iop_base
,
8916 ASC_SCSIQ_B_FIRST_SG_WK_QP
));
8919 * Reset request's working SG queue back to the
8922 AscWriteLramByte(iop_base
,
8924 (ushort
)ASC_SCSIQ_B_SG_WK_QP
),
8927 sg_head
= scsiq
->sg_head
;
8930 * Set sg_entry_cnt to the number of SG elements
8931 * that will be completed on this interrupt.
8933 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
8934 * SG elements. The data_cnt and data_addr fields which
8935 * add 1 to the SG element capacity are not used when
8936 * restarting SG handling after a halt.
8938 if (scsiq
->remain_sg_entry_cnt
> (ASC_MAX_SG_LIST
- 1)) {
8939 sg_entry_cnt
= ASC_MAX_SG_LIST
- 1;
8942 * Keep track of remaining number of SG elements that
8943 * will need to be handled on the next interrupt.
8945 scsiq
->remain_sg_entry_cnt
-= (ASC_MAX_SG_LIST
- 1);
8947 sg_entry_cnt
= scsiq
->remain_sg_entry_cnt
;
8948 scsiq
->remain_sg_entry_cnt
= 0;
8952 * Copy SG elements into the list of allocated SG queues.
8954 * Last index completed is saved in scsiq->next_sg_index.
8956 next_qp
= first_sg_wk_q_no
;
8957 q_addr
= ASC_QNO_TO_QADDR(next_qp
);
8958 scsi_sg_q
.sg_head_qp
= q_no
;
8959 scsi_sg_q
.cntl
= QCSG_SG_XFER_LIST
;
8960 for (i
= 0; i
< sg_head
->queue_cnt
; i
++) {
8961 scsi_sg_q
.seq_no
= i
+ 1;
8962 if (sg_entry_cnt
> ASC_SG_LIST_PER_Q
) {
8963 sg_list_dwords
= (uchar
)(ASC_SG_LIST_PER_Q
* 2);
8964 sg_entry_cnt
-= ASC_SG_LIST_PER_Q
;
8966 * After very first SG queue RISC FW uses next
8967 * SG queue first element then checks sg_list_cnt
8968 * against zero and then decrements, so set
8969 * sg_list_cnt 1 less than number of SG elements
8972 scsi_sg_q
.sg_list_cnt
= ASC_SG_LIST_PER_Q
- 1;
8973 scsi_sg_q
.sg_cur_list_cnt
=
8974 ASC_SG_LIST_PER_Q
- 1;
8977 * This is the last SG queue in the list of
8978 * allocated SG queues. If there are more
8979 * SG elements than will fit in the allocated
8980 * queues, then set the QCSG_SG_XFER_MORE flag.
8982 if (scsiq
->remain_sg_entry_cnt
!= 0) {
8983 scsi_sg_q
.cntl
|= QCSG_SG_XFER_MORE
;
8985 scsi_sg_q
.cntl
|= QCSG_SG_XFER_END
;
8987 /* equals sg_entry_cnt * 2 */
8988 sg_list_dwords
= sg_entry_cnt
<< 1;
8989 scsi_sg_q
.sg_list_cnt
= sg_entry_cnt
- 1;
8990 scsi_sg_q
.sg_cur_list_cnt
= sg_entry_cnt
- 1;
8994 scsi_sg_q
.q_no
= next_qp
;
8995 AscMemWordCopyPtrToLram(iop_base
,
8996 q_addr
+ ASC_SCSIQ_SGHD_CPY_BEG
,
8997 (uchar
*)&scsi_sg_q
,
8998 sizeof(ASC_SG_LIST_Q
) >> 1);
9000 AscMemDWordCopyPtrToLram(iop_base
,
9001 q_addr
+ ASC_SGQ_LIST_BEG
,
9003 sg_list
[scsiq
->next_sg_index
],
9006 scsiq
->next_sg_index
+= ASC_SG_LIST_PER_Q
;
9009 * If the just completed SG queue contained the
9010 * last SG element, then no more SG queues need
9013 if (scsi_sg_q
.cntl
& QCSG_SG_XFER_END
) {
9017 next_qp
= AscReadLramByte(iop_base
,
9020 q_addr
= ASC_QNO_TO_QADDR(next_qp
);
9024 * Clear the halt condition so the RISC will be restarted
9027 AscWriteLramWord(iop_base
, ASCV_HALTCODE_W
, 0);
9030 #endif /* CC_VERY_LONG_SG_LIST */
9036 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
9038 * Calling/Exit State:
9042 * Input an ASC_QDONE_INFO structure from the chip
9045 DvcGetQinfo(PortAddr iop_base
, ushort s_addr
, uchar
*inbuf
, int words
)
9050 AscSetChipLramAddr(iop_base
, s_addr
);
9051 for (i
= 0; i
< 2 * words
; i
+= 2) {
9055 word
= inpw(iop_base
+ IOP_RAM_DATA
);
9056 inbuf
[i
] = word
& 0xff;
9057 inbuf
[i
+ 1] = (word
>> 8) & 0xff;
9059 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf
, 2 * words
);
9063 _AscCopyLramScsiDoneQ(PortAddr iop_base
,
9065 ASC_QDONE_INFO
*scsiq
, ASC_DCNT max_dma_count
)
9070 DvcGetQinfo(iop_base
,
9071 q_addr
+ ASC_SCSIQ_DONE_INFO_BEG
,
9073 (sizeof(ASC_SCSIQ_2
) + sizeof(ASC_SCSIQ_3
)) / 2);
9075 _val
= AscReadLramWord(iop_base
,
9076 (ushort
)(q_addr
+ (ushort
)ASC_SCSIQ_B_STATUS
));
9077 scsiq
->q_status
= (uchar
)_val
;
9078 scsiq
->q_no
= (uchar
)(_val
>> 8);
9079 _val
= AscReadLramWord(iop_base
,
9080 (ushort
)(q_addr
+ (ushort
)ASC_SCSIQ_B_CNTL
));
9081 scsiq
->cntl
= (uchar
)_val
;
9082 sg_queue_cnt
= (uchar
)(_val
>> 8);
9083 _val
= AscReadLramWord(iop_base
,
9085 (ushort
)ASC_SCSIQ_B_SENSE_LEN
));
9086 scsiq
->sense_len
= (uchar
)_val
;
9087 scsiq
->extra_bytes
= (uchar
)(_val
>> 8);
9090 * Read high word of remain bytes from alternate location.
9092 scsiq
->remain_bytes
= (((ADV_DCNT
)AscReadLramWord(iop_base
,
9095 ASC_SCSIQ_W_ALT_DC1
)))
9098 * Read low word of remain bytes from original location.
9100 scsiq
->remain_bytes
+= AscReadLramWord(iop_base
,
9101 (ushort
)(q_addr
+ (ushort
)
9102 ASC_SCSIQ_DW_REMAIN_XFER_CNT
));
9104 scsiq
->remain_bytes
&= max_dma_count
;
9105 return sg_queue_cnt
;
9109 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
9111 * Interrupt callback function for the Narrow SCSI Asc Library.
9113 static void asc_isr_callback(ASC_DVC_VAR
*asc_dvc_varp
, ASC_QDONE_INFO
*qdonep
)
9115 struct asc_board
*boardp
;
9116 struct scsi_cmnd
*scp
;
9117 struct Scsi_Host
*shost
;
9119 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp
, qdonep
);
9120 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep
);
9122 scp
= advansys_srb_to_ptr(asc_dvc_varp
, qdonep
->d2
.srb_ptr
);
9126 ASC_DBG_PRT_CDB(2, scp
->cmnd
, scp
->cmd_len
);
9128 shost
= scp
->device
->host
;
9129 ASC_STATS(shost
, callback
);
9130 ASC_DBG(1, "shost 0x%p\n", shost
);
9132 boardp
= shost_priv(shost
);
9133 BUG_ON(asc_dvc_varp
!= &boardp
->dvc_var
.asc_dvc_var
);
9135 dma_unmap_single(boardp
->dev
, scp
->SCp
.dma_handle
,
9136 sizeof(scp
->sense_buffer
), DMA_FROM_DEVICE
);
9138 * 'qdonep' contains the command's ending status.
9140 switch (qdonep
->d3
.done_stat
) {
9142 ASC_DBG(2, "QD_NO_ERROR\n");
9146 * Check for an underrun condition.
9148 * If there was no error and an underrun condition, then
9149 * return the number of underrun bytes.
9151 if (scsi_bufflen(scp
) != 0 && qdonep
->remain_bytes
!= 0 &&
9152 qdonep
->remain_bytes
<= scsi_bufflen(scp
)) {
9153 ASC_DBG(1, "underrun condition %u bytes\n",
9154 (unsigned)qdonep
->remain_bytes
);
9155 scsi_set_resid(scp
, qdonep
->remain_bytes
);
9160 ASC_DBG(2, "QD_WITH_ERROR\n");
9161 switch (qdonep
->d3
.host_stat
) {
9162 case QHSTA_NO_ERROR
:
9163 if (qdonep
->d3
.scsi_stat
== SAM_STAT_CHECK_CONDITION
) {
9164 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
9165 ASC_DBG_PRT_SENSE(2, scp
->sense_buffer
,
9166 sizeof(scp
->sense_buffer
));
9168 * Note: The 'status_byte()' macro used by
9169 * target drivers defined in scsi.h shifts the
9170 * status byte returned by host drivers right
9171 * by 1 bit. This is why target drivers also
9172 * use right shifted status byte definitions.
9173 * For instance target drivers use
9174 * CHECK_CONDITION, defined to 0x1, instead of
9175 * the SCSI defined check condition value of
9176 * 0x2. Host drivers are supposed to return
9177 * the status byte as it is defined by SCSI.
9179 scp
->result
= DRIVER_BYTE(DRIVER_SENSE
) |
9180 STATUS_BYTE(qdonep
->d3
.scsi_stat
);
9182 scp
->result
= STATUS_BYTE(qdonep
->d3
.scsi_stat
);
9187 /* QHSTA error occurred */
9188 ASC_DBG(1, "host_stat 0x%x\n", qdonep
->d3
.host_stat
);
9189 scp
->result
= HOST_BYTE(DID_BAD_TARGET
);
9194 case QD_ABORTED_BY_HOST
:
9195 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
9197 HOST_BYTE(DID_ABORT
) | MSG_BYTE(qdonep
->d3
.
9199 STATUS_BYTE(qdonep
->d3
.scsi_stat
);
9203 ASC_DBG(1, "done_stat 0x%x\n", qdonep
->d3
.done_stat
);
9205 HOST_BYTE(DID_ERROR
) | MSG_BYTE(qdonep
->d3
.
9207 STATUS_BYTE(qdonep
->d3
.scsi_stat
);
9212 * If the 'init_tidmask' bit isn't already set for the target and the
9213 * current request finished normally, then set the bit for the target
9214 * to indicate that a device is present.
9216 if ((boardp
->init_tidmask
& ADV_TID_TO_TIDMASK(scp
->device
->id
)) == 0 &&
9217 qdonep
->d3
.done_stat
== QD_NO_ERROR
&&
9218 qdonep
->d3
.host_stat
== QHSTA_NO_ERROR
) {
9219 boardp
->init_tidmask
|= ADV_TID_TO_TIDMASK(scp
->device
->id
);
9225 static int AscIsrQDone(ASC_DVC_VAR
*asc_dvc
)
9234 ASC_SCSI_BIT_ID_TYPE scsi_busy
;
9235 ASC_SCSI_BIT_ID_TYPE target_id
;
9239 uchar cur_target_qng
;
9240 ASC_QDONE_INFO scsiq_buf
;
9241 ASC_QDONE_INFO
*scsiq
;
9244 iop_base
= asc_dvc
->iop_base
;
9246 scsiq
= (ASC_QDONE_INFO
*)&scsiq_buf
;
9247 done_q_tail
= (uchar
)AscGetVarDoneQTail(iop_base
);
9248 q_addr
= ASC_QNO_TO_QADDR(done_q_tail
);
9249 next_qp
= AscReadLramByte(iop_base
,
9250 (ushort
)(q_addr
+ (ushort
)ASC_SCSIQ_B_FWD
));
9251 if (next_qp
!= ASC_QLINK_END
) {
9252 AscPutVarDoneQTail(iop_base
, next_qp
);
9253 q_addr
= ASC_QNO_TO_QADDR(next_qp
);
9254 sg_queue_cnt
= _AscCopyLramScsiDoneQ(iop_base
, q_addr
, scsiq
,
9255 asc_dvc
->max_dma_count
);
9256 AscWriteLramByte(iop_base
,
9258 (ushort
)ASC_SCSIQ_B_STATUS
),
9260 q_status
& (uchar
)~(QS_READY
|
9262 tid_no
= ASC_TIX_TO_TID(scsiq
->d2
.target_ix
);
9263 target_id
= ASC_TIX_TO_TARGET_ID(scsiq
->d2
.target_ix
);
9264 if ((scsiq
->cntl
& QC_SG_HEAD
) != 0) {
9266 sg_list_qp
= next_qp
;
9267 for (q_cnt
= 0; q_cnt
< sg_queue_cnt
; q_cnt
++) {
9268 sg_list_qp
= AscReadLramByte(iop_base
,
9272 sg_q_addr
= ASC_QNO_TO_QADDR(sg_list_qp
);
9273 if (sg_list_qp
== ASC_QLINK_END
) {
9274 AscSetLibErrorCode(asc_dvc
,
9275 ASCQ_ERR_SG_Q_LINKS
);
9276 scsiq
->d3
.done_stat
= QD_WITH_ERROR
;
9277 scsiq
->d3
.host_stat
=
9278 QHSTA_D_QDONE_SG_LIST_CORRUPTED
;
9279 goto FATAL_ERR_QDONE
;
9281 AscWriteLramByte(iop_base
,
9282 (ushort
)(sg_q_addr
+ (ushort
)
9283 ASC_SCSIQ_B_STATUS
),
9286 n_q_used
= sg_queue_cnt
+ 1;
9287 AscPutVarDoneQTail(iop_base
, sg_list_qp
);
9289 if (asc_dvc
->queue_full_or_busy
& target_id
) {
9290 cur_target_qng
= AscReadLramByte(iop_base
,
9296 if (cur_target_qng
< asc_dvc
->max_dvc_qng
[tid_no
]) {
9297 scsi_busy
= AscReadLramByte(iop_base
, (ushort
)
9299 scsi_busy
&= ~target_id
;
9300 AscWriteLramByte(iop_base
,
9301 (ushort
)ASCV_SCSIBUSY_B
,
9303 asc_dvc
->queue_full_or_busy
&= ~target_id
;
9306 if (asc_dvc
->cur_total_qng
>= n_q_used
) {
9307 asc_dvc
->cur_total_qng
-= n_q_used
;
9308 if (asc_dvc
->cur_dvc_qng
[tid_no
] != 0) {
9309 asc_dvc
->cur_dvc_qng
[tid_no
]--;
9312 AscSetLibErrorCode(asc_dvc
, ASCQ_ERR_CUR_QNG
);
9313 scsiq
->d3
.done_stat
= QD_WITH_ERROR
;
9314 goto FATAL_ERR_QDONE
;
9316 if ((scsiq
->d2
.srb_ptr
== 0UL) ||
9317 ((scsiq
->q_status
& QS_ABORTED
) != 0)) {
9319 } else if (scsiq
->q_status
== QS_DONE
) {
9320 false_overrun
= FALSE
;
9321 if (scsiq
->extra_bytes
!= 0) {
9322 scsiq
->remain_bytes
+=
9323 (ADV_DCNT
)scsiq
->extra_bytes
;
9325 if (scsiq
->d3
.done_stat
== QD_WITH_ERROR
) {
9326 if (scsiq
->d3
.host_stat
==
9327 QHSTA_M_DATA_OVER_RUN
) {
9329 cntl
& (QC_DATA_IN
| QC_DATA_OUT
))
9331 scsiq
->d3
.done_stat
=
9333 scsiq
->d3
.host_stat
=
9335 } else if (false_overrun
) {
9336 scsiq
->d3
.done_stat
=
9338 scsiq
->d3
.host_stat
=
9341 } else if (scsiq
->d3
.host_stat
==
9342 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET
) {
9343 AscStopChip(iop_base
);
9344 AscSetChipControl(iop_base
,
9345 (uchar
)(CC_SCSI_RESET
9348 AscSetChipControl(iop_base
, CC_HALT
);
9349 AscSetChipStatus(iop_base
,
9350 CIW_CLR_SCSI_RESET_INT
);
9351 AscSetChipStatus(iop_base
, 0);
9352 AscSetChipControl(iop_base
, 0);
9355 if ((scsiq
->cntl
& QC_NO_CALLBACK
) == 0) {
9356 asc_isr_callback(asc_dvc
, scsiq
);
9358 if ((AscReadLramByte(iop_base
,
9359 (ushort
)(q_addr
+ (ushort
)
9362 asc_dvc
->unit_not_ready
&= ~target_id
;
9363 if (scsiq
->d3
.done_stat
!= QD_NO_ERROR
) {
9364 asc_dvc
->start_motor
&=
9371 AscSetLibErrorCode(asc_dvc
, ASCQ_ERR_Q_STATUS
);
9373 if ((scsiq
->cntl
& QC_NO_CALLBACK
) == 0) {
9374 asc_isr_callback(asc_dvc
, scsiq
);
9382 static int AscISR(ASC_DVC_VAR
*asc_dvc
)
9384 ASC_CS_TYPE chipstat
;
9386 ushort saved_ram_addr
;
9388 uchar saved_ctrl_reg
;
9393 iop_base
= asc_dvc
->iop_base
;
9394 int_pending
= FALSE
;
9396 if (AscIsIntPending(iop_base
) == 0)
9399 if ((asc_dvc
->init_state
& ASC_INIT_STATE_END_LOAD_MC
) == 0) {
9402 if (asc_dvc
->in_critical_cnt
!= 0) {
9403 AscSetLibErrorCode(asc_dvc
, ASCQ_ERR_ISR_ON_CRITICAL
);
9406 if (asc_dvc
->is_in_int
) {
9407 AscSetLibErrorCode(asc_dvc
, ASCQ_ERR_ISR_RE_ENTRY
);
9410 asc_dvc
->is_in_int
= TRUE
;
9411 ctrl_reg
= AscGetChipControl(iop_base
);
9412 saved_ctrl_reg
= ctrl_reg
& (~(CC_SCSI_RESET
| CC_CHIP_RESET
|
9413 CC_SINGLE_STEP
| CC_DIAG
| CC_TEST
));
9414 chipstat
= AscGetChipStatus(iop_base
);
9415 if (chipstat
& CSW_SCSI_RESET_LATCH
) {
9416 if (!(asc_dvc
->bus_type
& (ASC_IS_VL
| ASC_IS_EISA
))) {
9419 asc_dvc
->sdtr_done
= 0;
9420 saved_ctrl_reg
&= (uchar
)(~CC_HALT
);
9421 while ((AscGetChipStatus(iop_base
) &
9422 CSW_SCSI_RESET_ACTIVE
) && (i
-- > 0)) {
9425 AscSetChipControl(iop_base
, (CC_CHIP_RESET
| CC_HALT
));
9426 AscSetChipControl(iop_base
, CC_HALT
);
9427 AscSetChipStatus(iop_base
, CIW_CLR_SCSI_RESET_INT
);
9428 AscSetChipStatus(iop_base
, 0);
9429 chipstat
= AscGetChipStatus(iop_base
);
9432 saved_ram_addr
= AscGetChipLramAddr(iop_base
);
9433 host_flag
= AscReadLramByte(iop_base
,
9435 (uchar
)(~ASC_HOST_FLAG_IN_ISR
);
9436 AscWriteLramByte(iop_base
, ASCV_HOST_FLAG_B
,
9437 (uchar
)(host_flag
| (uchar
)ASC_HOST_FLAG_IN_ISR
));
9438 if ((chipstat
& CSW_INT_PENDING
) || (int_pending
)) {
9439 AscAckInterrupt(iop_base
);
9441 if ((chipstat
& CSW_HALTED
) && (ctrl_reg
& CC_SINGLE_STEP
)) {
9442 if (AscIsrChipHalted(asc_dvc
) == ERR
) {
9443 goto ISR_REPORT_QDONE_FATAL_ERROR
;
9445 saved_ctrl_reg
&= (uchar
)(~CC_HALT
);
9448 ISR_REPORT_QDONE_FATAL_ERROR
:
9449 if ((asc_dvc
->dvc_cntl
& ASC_CNTL_INT_MULTI_Q
) != 0) {
9451 AscIsrQDone(asc_dvc
)) & 0x01) != 0) {
9456 AscIsrQDone(asc_dvc
)) == 1) {
9459 } while (status
== 0x11);
9461 if ((status
& 0x80) != 0)
9465 AscWriteLramByte(iop_base
, ASCV_HOST_FLAG_B
, host_flag
);
9466 AscSetChipLramAddr(iop_base
, saved_ram_addr
);
9467 AscSetChipControl(iop_base
, saved_ctrl_reg
);
9468 asc_dvc
->is_in_int
= FALSE
;
9475 * Reset the bus associated with the command 'scp'.
9477 * This function runs its own thread. Interrupts must be blocked but
9478 * sleeping is allowed and no locking other than for host structures is
9479 * required. Returns SUCCESS or FAILED.
9481 static int advansys_reset(struct scsi_cmnd
*scp
)
9483 struct Scsi_Host
*shost
= scp
->device
->host
;
9484 struct asc_board
*boardp
= shost_priv(shost
);
9485 unsigned long flags
;
9489 ASC_DBG(1, "0x%p\n", scp
);
9491 ASC_STATS(shost
, reset
);
9493 scmd_printk(KERN_INFO
, scp
, "SCSI bus reset started...\n");
9495 if (ASC_NARROW_BOARD(boardp
)) {
9496 ASC_DVC_VAR
*asc_dvc
= &boardp
->dvc_var
.asc_dvc_var
;
9498 /* Reset the chip and SCSI bus. */
9499 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
9500 status
= AscInitAsc1000Driver(asc_dvc
);
9502 /* Refer to ASC_IERR_* defintions for meaning of 'err_code'. */
9503 if (asc_dvc
->err_code
) {
9504 scmd_printk(KERN_INFO
, scp
, "SCSI bus reset error: "
9505 "0x%x\n", asc_dvc
->err_code
);
9507 } else if (status
) {
9508 scmd_printk(KERN_INFO
, scp
, "SCSI bus reset warning: "
9511 scmd_printk(KERN_INFO
, scp
, "SCSI bus reset "
9515 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
9516 spin_lock_irqsave(shost
->host_lock
, flags
);
9519 * If the suggest reset bus flags are set, then reset the bus.
9520 * Otherwise only reset the device.
9522 ADV_DVC_VAR
*adv_dvc
= &boardp
->dvc_var
.adv_dvc_var
;
9525 * Reset the target's SCSI bus.
9527 ASC_DBG(1, "before AdvResetChipAndSB()\n");
9528 switch (AdvResetChipAndSB(adv_dvc
)) {
9530 scmd_printk(KERN_INFO
, scp
, "SCSI bus reset "
9535 scmd_printk(KERN_INFO
, scp
, "SCSI bus reset error\n");
9539 spin_lock_irqsave(shost
->host_lock
, flags
);
9543 /* Save the time of the most recently completed reset. */
9544 boardp
->last_reset
= jiffies
;
9545 spin_unlock_irqrestore(shost
->host_lock
, flags
);
9547 ASC_DBG(1, "ret %d\n", ret
);
9553 * advansys_biosparam()
9555 * Translate disk drive geometry if the "BIOS greater than 1 GB"
9556 * support is enabled for a drive.
9558 * ip (information pointer) is an int array with the following definition:
9564 advansys_biosparam(struct scsi_device
*sdev
, struct block_device
*bdev
,
9565 sector_t capacity
, int ip
[])
9567 struct asc_board
*boardp
= shost_priv(sdev
->host
);
9569 ASC_DBG(1, "begin\n");
9570 ASC_STATS(sdev
->host
, biosparam
);
9571 if (ASC_NARROW_BOARD(boardp
)) {
9572 if ((boardp
->dvc_var
.asc_dvc_var
.dvc_cntl
&
9573 ASC_CNTL_BIOS_GT_1GB
) && capacity
> 0x200000) {
9581 if ((boardp
->dvc_var
.adv_dvc_var
.bios_ctrl
&
9582 BIOS_CTRL_EXTENDED_XLAT
) && capacity
> 0x200000) {
9590 ip
[2] = (unsigned long)capacity
/ (ip
[0] * ip
[1]);
9591 ASC_DBG(1, "end\n");
9596 * First-level interrupt handler.
9598 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
9600 static irqreturn_t
advansys_interrupt(int irq
, void *dev_id
)
9602 struct Scsi_Host
*shost
= dev_id
;
9603 struct asc_board
*boardp
= shost_priv(shost
);
9604 irqreturn_t result
= IRQ_NONE
;
9606 ASC_DBG(2, "boardp 0x%p\n", boardp
);
9607 spin_lock(shost
->host_lock
);
9608 if (ASC_NARROW_BOARD(boardp
)) {
9609 if (AscIsIntPending(shost
->io_port
)) {
9610 result
= IRQ_HANDLED
;
9611 ASC_STATS(shost
, interrupt
);
9612 ASC_DBG(1, "before AscISR()\n");
9613 AscISR(&boardp
->dvc_var
.asc_dvc_var
);
9616 ASC_DBG(1, "before AdvISR()\n");
9617 if (AdvISR(&boardp
->dvc_var
.adv_dvc_var
)) {
9618 result
= IRQ_HANDLED
;
9619 ASC_STATS(shost
, interrupt
);
9622 spin_unlock(shost
->host_lock
);
9624 ASC_DBG(1, "end\n");
9628 static int AscHostReqRiscHalt(PortAddr iop_base
)
9632 uchar saved_stop_code
;
9634 if (AscIsChipHalted(iop_base
))
9636 saved_stop_code
= AscReadLramByte(iop_base
, ASCV_STOP_CODE_B
);
9637 AscWriteLramByte(iop_base
, ASCV_STOP_CODE_B
,
9638 ASC_STOP_HOST_REQ_RISC_HALT
| ASC_STOP_REQ_RISC_STOP
);
9640 if (AscIsChipHalted(iop_base
)) {
9645 } while (count
++ < 20);
9646 AscWriteLramByte(iop_base
, ASCV_STOP_CODE_B
, saved_stop_code
);
9651 AscSetRunChipSynRegAtID(PortAddr iop_base
, uchar tid_no
, uchar sdtr_data
)
9655 if (AscHostReqRiscHalt(iop_base
)) {
9656 sta
= AscSetChipSynRegAtID(iop_base
, tid_no
, sdtr_data
);
9657 AscStartChip(iop_base
);
9662 static void AscAsyncFix(ASC_DVC_VAR
*asc_dvc
, struct scsi_device
*sdev
)
9664 char type
= sdev
->type
;
9665 ASC_SCSI_BIT_ID_TYPE tid_bits
= 1 << sdev
->id
;
9667 if (!(asc_dvc
->bug_fix_cntl
& ASC_BUG_FIX_ASYN_USE_SYN
))
9669 if (asc_dvc
->init_sdtr
& tid_bits
)
9672 if ((type
== TYPE_ROM
) && (strncmp(sdev
->vendor
, "HP ", 3) == 0))
9673 asc_dvc
->pci_fix_asyn_xfer_always
|= tid_bits
;
9675 asc_dvc
->pci_fix_asyn_xfer
|= tid_bits
;
9676 if ((type
== TYPE_PROCESSOR
) || (type
== TYPE_SCANNER
) ||
9677 (type
== TYPE_ROM
) || (type
== TYPE_TAPE
))
9678 asc_dvc
->pci_fix_asyn_xfer
&= ~tid_bits
;
9680 if (asc_dvc
->pci_fix_asyn_xfer
& tid_bits
)
9681 AscSetRunChipSynRegAtID(asc_dvc
->iop_base
, sdev
->id
,
9682 ASYN_SDTR_DATA_FIX_PCI_REV_AB
);
9686 advansys_narrow_slave_configure(struct scsi_device
*sdev
, ASC_DVC_VAR
*asc_dvc
)
9688 ASC_SCSI_BIT_ID_TYPE tid_bit
= 1 << sdev
->id
;
9689 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng
= asc_dvc
->use_tagged_qng
;
9691 if (sdev
->lun
== 0) {
9692 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr
= asc_dvc
->init_sdtr
;
9693 if ((asc_dvc
->cfg
->sdtr_enable
& tid_bit
) && sdev
->sdtr
) {
9694 asc_dvc
->init_sdtr
|= tid_bit
;
9696 asc_dvc
->init_sdtr
&= ~tid_bit
;
9699 if (orig_init_sdtr
!= asc_dvc
->init_sdtr
)
9700 AscAsyncFix(asc_dvc
, sdev
);
9703 if (sdev
->tagged_supported
) {
9704 if (asc_dvc
->cfg
->cmd_qng_enabled
& tid_bit
) {
9705 if (sdev
->lun
== 0) {
9706 asc_dvc
->cfg
->can_tagged_qng
|= tid_bit
;
9707 asc_dvc
->use_tagged_qng
|= tid_bit
;
9709 scsi_adjust_queue_depth(sdev
, MSG_ORDERED_TAG
,
9710 asc_dvc
->max_dvc_qng
[sdev
->id
]);
9713 if (sdev
->lun
== 0) {
9714 asc_dvc
->cfg
->can_tagged_qng
&= ~tid_bit
;
9715 asc_dvc
->use_tagged_qng
&= ~tid_bit
;
9717 scsi_adjust_queue_depth(sdev
, 0, sdev
->host
->cmd_per_lun
);
9720 if ((sdev
->lun
== 0) &&
9721 (orig_use_tagged_qng
!= asc_dvc
->use_tagged_qng
)) {
9722 AscWriteLramByte(asc_dvc
->iop_base
, ASCV_DISC_ENABLE_B
,
9723 asc_dvc
->cfg
->disc_enable
);
9724 AscWriteLramByte(asc_dvc
->iop_base
, ASCV_USE_TAGGED_QNG_B
,
9725 asc_dvc
->use_tagged_qng
);
9726 AscWriteLramByte(asc_dvc
->iop_base
, ASCV_CAN_TAGGED_QNG_B
,
9727 asc_dvc
->cfg
->can_tagged_qng
);
9729 asc_dvc
->max_dvc_qng
[sdev
->id
] =
9730 asc_dvc
->cfg
->max_tag_qng
[sdev
->id
];
9731 AscWriteLramByte(asc_dvc
->iop_base
,
9732 (ushort
)(ASCV_MAX_DVC_QNG_BEG
+ sdev
->id
),
9733 asc_dvc
->max_dvc_qng
[sdev
->id
]);
9740 * If the EEPROM enabled WDTR for the device and the device supports wide
9741 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
9742 * write the new value to the microcode.
9745 advansys_wide_enable_wdtr(AdvPortAddr iop_base
, unsigned short tidmask
)
9747 unsigned short cfg_word
;
9748 AdvReadWordLram(iop_base
, ASC_MC_WDTR_ABLE
, cfg_word
);
9749 if ((cfg_word
& tidmask
) != 0)
9752 cfg_word
|= tidmask
;
9753 AdvWriteWordLram(iop_base
, ASC_MC_WDTR_ABLE
, cfg_word
);
9756 * Clear the microcode SDTR and WDTR negotiation done indicators for
9757 * the target to cause it to negotiate with the new setting set above.
9758 * WDTR when accepted causes the target to enter asynchronous mode, so
9759 * SDTR must be negotiated.
9761 AdvReadWordLram(iop_base
, ASC_MC_SDTR_DONE
, cfg_word
);
9762 cfg_word
&= ~tidmask
;
9763 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_DONE
, cfg_word
);
9764 AdvReadWordLram(iop_base
, ASC_MC_WDTR_DONE
, cfg_word
);
9765 cfg_word
&= ~tidmask
;
9766 AdvWriteWordLram(iop_base
, ASC_MC_WDTR_DONE
, cfg_word
);
9770 * Synchronous Transfers
9772 * If the EEPROM enabled SDTR for the device and the device
9773 * supports synchronous transfers, then turn on the device's
9774 * 'sdtr_able' bit. Write the new value to the microcode.
9777 advansys_wide_enable_sdtr(AdvPortAddr iop_base
, unsigned short tidmask
)
9779 unsigned short cfg_word
;
9780 AdvReadWordLram(iop_base
, ASC_MC_SDTR_ABLE
, cfg_word
);
9781 if ((cfg_word
& tidmask
) != 0)
9784 cfg_word
|= tidmask
;
9785 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_ABLE
, cfg_word
);
9788 * Clear the microcode "SDTR negotiation" done indicator for the
9789 * target to cause it to negotiate with the new setting set above.
9791 AdvReadWordLram(iop_base
, ASC_MC_SDTR_DONE
, cfg_word
);
9792 cfg_word
&= ~tidmask
;
9793 AdvWriteWordLram(iop_base
, ASC_MC_SDTR_DONE
, cfg_word
);
9797 * PPR (Parallel Protocol Request) Capable
9799 * If the device supports DT mode, then it must be PPR capable.
9800 * The PPR message will be used in place of the SDTR and WDTR
9801 * messages to negotiate synchronous speed and offset, transfer
9802 * width, and protocol options.
9804 static void advansys_wide_enable_ppr(ADV_DVC_VAR
*adv_dvc
,
9805 AdvPortAddr iop_base
, unsigned short tidmask
)
9807 AdvReadWordLram(iop_base
, ASC_MC_PPR_ABLE
, adv_dvc
->ppr_able
);
9808 adv_dvc
->ppr_able
|= tidmask
;
9809 AdvWriteWordLram(iop_base
, ASC_MC_PPR_ABLE
, adv_dvc
->ppr_able
);
9813 advansys_wide_slave_configure(struct scsi_device
*sdev
, ADV_DVC_VAR
*adv_dvc
)
9815 AdvPortAddr iop_base
= adv_dvc
->iop_base
;
9816 unsigned short tidmask
= 1 << sdev
->id
;
9818 if (sdev
->lun
== 0) {
9820 * Handle WDTR, SDTR, and Tag Queuing. If the feature
9821 * is enabled in the EEPROM and the device supports the
9822 * feature, then enable it in the microcode.
9825 if ((adv_dvc
->wdtr_able
& tidmask
) && sdev
->wdtr
)
9826 advansys_wide_enable_wdtr(iop_base
, tidmask
);
9827 if ((adv_dvc
->sdtr_able
& tidmask
) && sdev
->sdtr
)
9828 advansys_wide_enable_sdtr(iop_base
, tidmask
);
9829 if (adv_dvc
->chip_type
== ADV_CHIP_ASC38C1600
&& sdev
->ppr
)
9830 advansys_wide_enable_ppr(adv_dvc
, iop_base
, tidmask
);
9833 * Tag Queuing is disabled for the BIOS which runs in polled
9834 * mode and would see no benefit from Tag Queuing. Also by
9835 * disabling Tag Queuing in the BIOS devices with Tag Queuing
9836 * bugs will at least work with the BIOS.
9838 if ((adv_dvc
->tagqng_able
& tidmask
) &&
9839 sdev
->tagged_supported
) {
9840 unsigned short cfg_word
;
9841 AdvReadWordLram(iop_base
, ASC_MC_TAGQNG_ABLE
, cfg_word
);
9842 cfg_word
|= tidmask
;
9843 AdvWriteWordLram(iop_base
, ASC_MC_TAGQNG_ABLE
,
9845 AdvWriteByteLram(iop_base
,
9846 ASC_MC_NUMBER_OF_MAX_CMD
+ sdev
->id
,
9847 adv_dvc
->max_dvc_qng
);
9851 if ((adv_dvc
->tagqng_able
& tidmask
) && sdev
->tagged_supported
) {
9852 scsi_adjust_queue_depth(sdev
, MSG_ORDERED_TAG
,
9853 adv_dvc
->max_dvc_qng
);
9855 scsi_adjust_queue_depth(sdev
, 0, sdev
->host
->cmd_per_lun
);
9860 * Set the number of commands to queue per device for the
9861 * specified host adapter.
9863 static int advansys_slave_configure(struct scsi_device
*sdev
)
9865 struct asc_board
*boardp
= shost_priv(sdev
->host
);
9867 if (ASC_NARROW_BOARD(boardp
))
9868 advansys_narrow_slave_configure(sdev
,
9869 &boardp
->dvc_var
.asc_dvc_var
);
9871 advansys_wide_slave_configure(sdev
,
9872 &boardp
->dvc_var
.adv_dvc_var
);
9877 static __le32
advansys_get_sense_buffer_dma(struct scsi_cmnd
*scp
)
9879 struct asc_board
*board
= shost_priv(scp
->device
->host
);
9880 scp
->SCp
.dma_handle
= dma_map_single(board
->dev
, scp
->sense_buffer
,
9881 sizeof(scp
->sense_buffer
), DMA_FROM_DEVICE
);
9882 dma_cache_sync(board
->dev
, scp
->sense_buffer
,
9883 sizeof(scp
->sense_buffer
), DMA_FROM_DEVICE
);
9884 return cpu_to_le32(scp
->SCp
.dma_handle
);
9887 static int asc_build_req(struct asc_board
*boardp
, struct scsi_cmnd
*scp
,
9888 struct asc_scsi_q
*asc_scsi_q
)
9890 struct asc_dvc_var
*asc_dvc
= &boardp
->dvc_var
.asc_dvc_var
;
9893 memset(asc_scsi_q
, 0, sizeof(*asc_scsi_q
));
9896 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
9898 asc_scsi_q
->q2
.srb_ptr
= advansys_ptr_to_srb(asc_dvc
, scp
);
9899 if (asc_scsi_q
->q2
.srb_ptr
== BAD_SRB
) {
9900 scp
->result
= HOST_BYTE(DID_SOFT_ERROR
);
9905 * Build the ASC_SCSI_Q request.
9907 asc_scsi_q
->cdbptr
= &scp
->cmnd
[0];
9908 asc_scsi_q
->q2
.cdb_len
= scp
->cmd_len
;
9909 asc_scsi_q
->q1
.target_id
= ASC_TID_TO_TARGET_ID(scp
->device
->id
);
9910 asc_scsi_q
->q1
.target_lun
= scp
->device
->lun
;
9911 asc_scsi_q
->q2
.target_ix
=
9912 ASC_TIDLUN_TO_IX(scp
->device
->id
, scp
->device
->lun
);
9913 asc_scsi_q
->q1
.sense_addr
= advansys_get_sense_buffer_dma(scp
);
9914 asc_scsi_q
->q1
.sense_len
= sizeof(scp
->sense_buffer
);
9917 * If there are any outstanding requests for the current target,
9918 * then every 255th request send an ORDERED request. This heuristic
9919 * tries to retain the benefit of request sorting while preventing
9920 * request starvation. 255 is the max number of tags or pending commands
9921 * a device may have outstanding.
9923 * The request count is incremented below for every successfully
9927 if ((asc_dvc
->cur_dvc_qng
[scp
->device
->id
] > 0) &&
9928 (boardp
->reqcnt
[scp
->device
->id
] % 255) == 0) {
9929 asc_scsi_q
->q2
.tag_code
= MSG_ORDERED_TAG
;
9931 asc_scsi_q
->q2
.tag_code
= MSG_SIMPLE_TAG
;
9934 /* Build ASC_SCSI_Q */
9935 use_sg
= scsi_dma_map(scp
);
9938 struct scatterlist
*slp
;
9939 struct asc_sg_head
*asc_sg_head
;
9941 if (use_sg
> scp
->device
->host
->sg_tablesize
) {
9942 scmd_printk(KERN_ERR
, scp
, "use_sg %d > "
9943 "sg_tablesize %d\n", use_sg
,
9944 scp
->device
->host
->sg_tablesize
);
9945 scsi_dma_unmap(scp
);
9946 scp
->result
= HOST_BYTE(DID_ERROR
);
9950 asc_sg_head
= kzalloc(sizeof(asc_scsi_q
->sg_head
) +
9951 use_sg
* sizeof(struct asc_sg_list
), GFP_ATOMIC
);
9953 scsi_dma_unmap(scp
);
9954 scp
->result
= HOST_BYTE(DID_SOFT_ERROR
);
9958 asc_scsi_q
->q1
.cntl
|= QC_SG_HEAD
;
9959 asc_scsi_q
->sg_head
= asc_sg_head
;
9960 asc_scsi_q
->q1
.data_cnt
= 0;
9961 asc_scsi_q
->q1
.data_addr
= 0;
9962 /* This is a byte value, otherwise it would need to be swapped. */
9963 asc_sg_head
->entry_cnt
= asc_scsi_q
->q1
.sg_queue_cnt
= use_sg
;
9964 ASC_STATS_ADD(scp
->device
->host
, xfer_elem
,
9965 asc_sg_head
->entry_cnt
);
9968 * Convert scatter-gather list into ASC_SG_HEAD list.
9970 scsi_for_each_sg(scp
, slp
, use_sg
, sgcnt
) {
9971 asc_sg_head
->sg_list
[sgcnt
].addr
=
9972 cpu_to_le32(sg_dma_address(slp
));
9973 asc_sg_head
->sg_list
[sgcnt
].bytes
=
9974 cpu_to_le32(sg_dma_len(slp
));
9975 ASC_STATS_ADD(scp
->device
->host
, xfer_sect
,
9976 DIV_ROUND_UP(sg_dma_len(slp
), 512));
9980 ASC_STATS(scp
->device
->host
, xfer_cnt
);
9982 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q
);
9983 ASC_DBG_PRT_CDB(1, scp
->cmnd
, scp
->cmd_len
);
9989 * Build scatter-gather list for Adv Library (Wide Board).
9991 * Additional ADV_SG_BLOCK structures will need to be allocated
9992 * if the total number of scatter-gather elements exceeds
9993 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
9994 * assumed to be physically contiguous.
9997 * ADV_SUCCESS(1) - SG List successfully created
9998 * ADV_ERROR(-1) - SG List creation failed
10001 adv_get_sglist(struct asc_board
*boardp
, adv_req_t
*reqp
, struct scsi_cmnd
*scp
,
10004 adv_sgblk_t
*sgblkp
;
10005 ADV_SCSI_REQ_Q
*scsiqp
;
10006 struct scatterlist
*slp
;
10008 ADV_SG_BLOCK
*sg_block
, *prev_sg_block
;
10009 ADV_PADDR sg_block_paddr
;
10012 scsiqp
= (ADV_SCSI_REQ_Q
*)ADV_32BALIGN(&reqp
->scsi_req_q
);
10013 slp
= scsi_sglist(scp
);
10014 sg_elem_cnt
= use_sg
;
10015 prev_sg_block
= NULL
;
10016 reqp
->sgblkp
= NULL
;
10020 * Allocate a 'adv_sgblk_t' structure from the board free
10021 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
10022 * (15) scatter-gather elements.
10024 if ((sgblkp
= boardp
->adv_sgblkp
) == NULL
) {
10025 ASC_DBG(1, "no free adv_sgblk_t\n");
10026 ASC_STATS(scp
->device
->host
, adv_build_nosg
);
10029 * Allocation failed. Free 'adv_sgblk_t' structures
10030 * already allocated for the request.
10032 while ((sgblkp
= reqp
->sgblkp
) != NULL
) {
10033 /* Remove 'sgblkp' from the request list. */
10034 reqp
->sgblkp
= sgblkp
->next_sgblkp
;
10036 /* Add 'sgblkp' to the board free list. */
10037 sgblkp
->next_sgblkp
= boardp
->adv_sgblkp
;
10038 boardp
->adv_sgblkp
= sgblkp
;
10043 /* Complete 'adv_sgblk_t' board allocation. */
10044 boardp
->adv_sgblkp
= sgblkp
->next_sgblkp
;
10045 sgblkp
->next_sgblkp
= NULL
;
10048 * Get 8 byte aligned virtual and physical addresses
10049 * for the allocated ADV_SG_BLOCK structure.
10051 sg_block
= (ADV_SG_BLOCK
*)ADV_8BALIGN(&sgblkp
->sg_block
);
10052 sg_block_paddr
= virt_to_bus(sg_block
);
10055 * Check if this is the first 'adv_sgblk_t' for the
10058 if (reqp
->sgblkp
== NULL
) {
10059 /* Request's first scatter-gather block. */
10060 reqp
->sgblkp
= sgblkp
;
10063 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
10064 * address pointers.
10066 scsiqp
->sg_list_ptr
= sg_block
;
10067 scsiqp
->sg_real_addr
= cpu_to_le32(sg_block_paddr
);
10069 /* Request's second or later scatter-gather block. */
10070 sgblkp
->next_sgblkp
= reqp
->sgblkp
;
10071 reqp
->sgblkp
= sgblkp
;
10074 * Point the previous ADV_SG_BLOCK structure to
10075 * the newly allocated ADV_SG_BLOCK structure.
10077 prev_sg_block
->sg_ptr
= cpu_to_le32(sg_block_paddr
);
10080 for (i
= 0; i
< NO_OF_SG_PER_BLOCK
; i
++) {
10081 sg_block
->sg_list
[i
].sg_addr
=
10082 cpu_to_le32(sg_dma_address(slp
));
10083 sg_block
->sg_list
[i
].sg_count
=
10084 cpu_to_le32(sg_dma_len(slp
));
10085 ASC_STATS_ADD(scp
->device
->host
, xfer_sect
,
10086 DIV_ROUND_UP(sg_dma_len(slp
), 512));
10088 if (--sg_elem_cnt
== 0) { /* Last ADV_SG_BLOCK and scatter-gather entry. */
10089 sg_block
->sg_cnt
= i
+ 1;
10090 sg_block
->sg_ptr
= 0L; /* Last ADV_SG_BLOCK in list. */
10091 return ADV_SUCCESS
;
10095 sg_block
->sg_cnt
= NO_OF_SG_PER_BLOCK
;
10096 prev_sg_block
= sg_block
;
10101 * Build a request structure for the Adv Library (Wide Board).
10103 * If an adv_req_t can not be allocated to issue the request,
10104 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
10106 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
10107 * microcode for DMA addresses or math operations are byte swapped
10108 * to little-endian order.
10111 adv_build_req(struct asc_board
*boardp
, struct scsi_cmnd
*scp
,
10112 ADV_SCSI_REQ_Q
**adv_scsiqpp
)
10115 ADV_SCSI_REQ_Q
*scsiqp
;
10121 * Allocate an adv_req_t structure from the board to execute
10124 if (boardp
->adv_reqp
== NULL
) {
10125 ASC_DBG(1, "no free adv_req_t\n");
10126 ASC_STATS(scp
->device
->host
, adv_build_noreq
);
10129 reqp
= boardp
->adv_reqp
;
10130 boardp
->adv_reqp
= reqp
->next_reqp
;
10131 reqp
->next_reqp
= NULL
;
10135 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
10137 scsiqp
= (ADV_SCSI_REQ_Q
*)ADV_32BALIGN(&reqp
->scsi_req_q
);
10140 * Initialize the structure.
10142 scsiqp
->cntl
= scsiqp
->scsi_cntl
= scsiqp
->done_status
= 0;
10145 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
10147 scsiqp
->srb_ptr
= ADV_VADDR_TO_U32(reqp
);
10150 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
10155 * Build the ADV_SCSI_REQ_Q request.
10158 /* Set CDB length and copy it to the request structure. */
10159 scsiqp
->cdb_len
= scp
->cmd_len
;
10160 /* Copy first 12 CDB bytes to cdb[]. */
10161 for (i
= 0; i
< scp
->cmd_len
&& i
< 12; i
++) {
10162 scsiqp
->cdb
[i
] = scp
->cmnd
[i
];
10164 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
10165 for (; i
< scp
->cmd_len
; i
++) {
10166 scsiqp
->cdb16
[i
- 12] = scp
->cmnd
[i
];
10169 scsiqp
->target_id
= scp
->device
->id
;
10170 scsiqp
->target_lun
= scp
->device
->lun
;
10172 scsiqp
->sense_addr
= cpu_to_le32(virt_to_bus(&scp
->sense_buffer
[0]));
10173 scsiqp
->sense_len
= sizeof(scp
->sense_buffer
);
10175 /* Build ADV_SCSI_REQ_Q */
10177 use_sg
= scsi_dma_map(scp
);
10179 /* Zero-length transfer */
10180 reqp
->sgblkp
= NULL
;
10181 scsiqp
->data_cnt
= 0;
10182 scsiqp
->vdata_addr
= NULL
;
10184 scsiqp
->data_addr
= 0;
10185 scsiqp
->sg_list_ptr
= NULL
;
10186 scsiqp
->sg_real_addr
= 0;
10188 if (use_sg
> ADV_MAX_SG_LIST
) {
10189 scmd_printk(KERN_ERR
, scp
, "use_sg %d > "
10190 "ADV_MAX_SG_LIST %d\n", use_sg
,
10191 scp
->device
->host
->sg_tablesize
);
10192 scsi_dma_unmap(scp
);
10193 scp
->result
= HOST_BYTE(DID_ERROR
);
10196 * Free the 'adv_req_t' structure by adding it back
10197 * to the board free list.
10199 reqp
->next_reqp
= boardp
->adv_reqp
;
10200 boardp
->adv_reqp
= reqp
;
10205 scsiqp
->data_cnt
= cpu_to_le32(scsi_bufflen(scp
));
10207 ret
= adv_get_sglist(boardp
, reqp
, scp
, use_sg
);
10208 if (ret
!= ADV_SUCCESS
) {
10210 * Free the adv_req_t structure by adding it back to
10211 * the board free list.
10213 reqp
->next_reqp
= boardp
->adv_reqp
;
10214 boardp
->adv_reqp
= reqp
;
10219 ASC_STATS_ADD(scp
->device
->host
, xfer_elem
, use_sg
);
10222 ASC_STATS(scp
->device
->host
, xfer_cnt
);
10224 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp
);
10225 ASC_DBG_PRT_CDB(1, scp
->cmnd
, scp
->cmd_len
);
10227 *adv_scsiqpp
= scsiqp
;
10229 return ASC_NOERROR
;
10232 static int AscSgListToQueue(int sg_list
)
10236 n_sg_list_qs
= ((sg_list
- 1) / ASC_SG_LIST_PER_Q
);
10237 if (((sg_list
- 1) % ASC_SG_LIST_PER_Q
) != 0)
10239 return n_sg_list_qs
+ 1;
10243 AscGetNumOfFreeQueue(ASC_DVC_VAR
*asc_dvc
, uchar target_ix
, uchar n_qs
)
10247 ASC_SCSI_BIT_ID_TYPE target_id
;
10250 target_id
= ASC_TIX_TO_TARGET_ID(target_ix
);
10251 tid_no
= ASC_TIX_TO_TID(target_ix
);
10252 if ((asc_dvc
->unit_not_ready
& target_id
) ||
10253 (asc_dvc
->queue_full_or_busy
& target_id
)) {
10257 cur_used_qs
= (uint
) asc_dvc
->cur_total_qng
+
10258 (uint
) asc_dvc
->last_q_shortage
+ (uint
) ASC_MIN_FREE_Q
;
10260 cur_used_qs
= (uint
) asc_dvc
->cur_total_qng
+
10261 (uint
) ASC_MIN_FREE_Q
;
10263 if ((uint
) (cur_used_qs
+ n_qs
) <= (uint
) asc_dvc
->max_total_qng
) {
10264 cur_free_qs
= (uint
) asc_dvc
->max_total_qng
- cur_used_qs
;
10265 if (asc_dvc
->cur_dvc_qng
[tid_no
] >=
10266 asc_dvc
->max_dvc_qng
[tid_no
]) {
10269 return cur_free_qs
;
10272 if ((n_qs
> asc_dvc
->last_q_shortage
)
10273 && (n_qs
<= (asc_dvc
->max_total_qng
- ASC_MIN_FREE_Q
))) {
10274 asc_dvc
->last_q_shortage
= n_qs
;
10280 static uchar
AscAllocFreeQueue(PortAddr iop_base
, uchar free_q_head
)
10286 q_addr
= ASC_QNO_TO_QADDR(free_q_head
);
10287 q_status
= (uchar
)AscReadLramByte(iop_base
,
10289 ASC_SCSIQ_B_STATUS
));
10290 next_qp
= AscReadLramByte(iop_base
, (ushort
)(q_addr
+ ASC_SCSIQ_B_FWD
));
10291 if (((q_status
& QS_READY
) == 0) && (next_qp
!= ASC_QLINK_END
))
10293 return ASC_QLINK_END
;
10297 AscAllocMultipleFreeQueue(PortAddr iop_base
, uchar free_q_head
, uchar n_free_q
)
10301 for (i
= 0; i
< n_free_q
; i
++) {
10302 free_q_head
= AscAllocFreeQueue(iop_base
, free_q_head
);
10303 if (free_q_head
== ASC_QLINK_END
)
10306 return free_q_head
;
10311 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
10313 * Calling/Exit State:
10317 * Output an ASC_SCSI_Q structure to the chip
10320 DvcPutScsiQ(PortAddr iop_base
, ushort s_addr
, uchar
*outbuf
, int words
)
10324 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf
, 2 * words
);
10325 AscSetChipLramAddr(iop_base
, s_addr
);
10326 for (i
= 0; i
< 2 * words
; i
+= 2) {
10327 if (i
== 4 || i
== 20) {
10330 outpw(iop_base
+ IOP_RAM_DATA
,
10331 ((ushort
)outbuf
[i
+ 1] << 8) | outbuf
[i
]);
10335 static int AscPutReadyQueue(ASC_DVC_VAR
*asc_dvc
, ASC_SCSI_Q
*scsiq
, uchar q_no
)
10340 uchar syn_period_ix
;
10344 iop_base
= asc_dvc
->iop_base
;
10345 if (((asc_dvc
->init_sdtr
& scsiq
->q1
.target_id
) != 0) &&
10346 ((asc_dvc
->sdtr_done
& scsiq
->q1
.target_id
) == 0)) {
10347 tid_no
= ASC_TIX_TO_TID(scsiq
->q2
.target_ix
);
10348 sdtr_data
= AscGetMCodeInitSDTRAtID(iop_base
, tid_no
);
10350 (sdtr_data
>> 4) & (asc_dvc
->max_sdtr_index
- 1);
10351 syn_offset
= sdtr_data
& ASC_SYN_MAX_OFFSET
;
10352 AscMsgOutSDTR(asc_dvc
,
10353 asc_dvc
->sdtr_period_tbl
[syn_period_ix
],
10355 scsiq
->q1
.cntl
|= QC_MSG_OUT
;
10357 q_addr
= ASC_QNO_TO_QADDR(q_no
);
10358 if ((scsiq
->q1
.target_id
& asc_dvc
->use_tagged_qng
) == 0) {
10359 scsiq
->q2
.tag_code
&= ~MSG_SIMPLE_TAG
;
10361 scsiq
->q1
.status
= QS_FREE
;
10362 AscMemWordCopyPtrToLram(iop_base
,
10363 q_addr
+ ASC_SCSIQ_CDB_BEG
,
10364 (uchar
*)scsiq
->cdbptr
, scsiq
->q2
.cdb_len
>> 1);
10366 DvcPutScsiQ(iop_base
,
10367 q_addr
+ ASC_SCSIQ_CPY_BEG
,
10368 (uchar
*)&scsiq
->q1
.cntl
,
10369 ((sizeof(ASC_SCSIQ_1
) + sizeof(ASC_SCSIQ_2
)) / 2) - 1);
10370 AscWriteLramWord(iop_base
,
10371 (ushort
)(q_addr
+ (ushort
)ASC_SCSIQ_B_STATUS
),
10372 (ushort
)(((ushort
)scsiq
->q1
.
10373 q_no
<< 8) | (ushort
)QS_READY
));
10378 AscPutReadySgListQueue(ASC_DVC_VAR
*asc_dvc
, ASC_SCSI_Q
*scsiq
, uchar q_no
)
10382 ASC_SG_HEAD
*sg_head
;
10383 ASC_SG_LIST_Q scsi_sg_q
;
10384 ASC_DCNT saved_data_addr
;
10385 ASC_DCNT saved_data_cnt
;
10387 ushort sg_list_dwords
;
10389 ushort sg_entry_cnt
;
10393 iop_base
= asc_dvc
->iop_base
;
10394 sg_head
= scsiq
->sg_head
;
10395 saved_data_addr
= scsiq
->q1
.data_addr
;
10396 saved_data_cnt
= scsiq
->q1
.data_cnt
;
10397 scsiq
->q1
.data_addr
= (ASC_PADDR
) sg_head
->sg_list
[0].addr
;
10398 scsiq
->q1
.data_cnt
= (ASC_DCNT
) sg_head
->sg_list
[0].bytes
;
10399 #if CC_VERY_LONG_SG_LIST
10401 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
10402 * then not all SG elements will fit in the allocated queues.
10403 * The rest of the SG elements will be copied when the RISC
10404 * completes the SG elements that fit and halts.
10406 if (sg_head
->entry_cnt
> ASC_MAX_SG_LIST
) {
10408 * Set sg_entry_cnt to be the number of SG elements that
10409 * will fit in the allocated SG queues. It is minus 1, because
10410 * the first SG element is handled above. ASC_MAX_SG_LIST is
10411 * already inflated by 1 to account for this. For example it
10412 * may be 50 which is 1 + 7 queues * 7 SG elements.
10414 sg_entry_cnt
= ASC_MAX_SG_LIST
- 1;
10417 * Keep track of remaining number of SG elements that will
10418 * need to be handled from a_isr.c.
10420 scsiq
->remain_sg_entry_cnt
=
10421 sg_head
->entry_cnt
- ASC_MAX_SG_LIST
;
10423 #endif /* CC_VERY_LONG_SG_LIST */
10425 * Set sg_entry_cnt to be the number of SG elements that
10426 * will fit in the allocated SG queues. It is minus 1, because
10427 * the first SG element is handled above.
10429 sg_entry_cnt
= sg_head
->entry_cnt
- 1;
10430 #if CC_VERY_LONG_SG_LIST
10432 #endif /* CC_VERY_LONG_SG_LIST */
10433 if (sg_entry_cnt
!= 0) {
10434 scsiq
->q1
.cntl
|= QC_SG_HEAD
;
10435 q_addr
= ASC_QNO_TO_QADDR(q_no
);
10437 scsiq
->q1
.sg_queue_cnt
= sg_head
->queue_cnt
;
10438 scsi_sg_q
.sg_head_qp
= q_no
;
10439 scsi_sg_q
.cntl
= QCSG_SG_XFER_LIST
;
10440 for (i
= 0; i
< sg_head
->queue_cnt
; i
++) {
10441 scsi_sg_q
.seq_no
= i
+ 1;
10442 if (sg_entry_cnt
> ASC_SG_LIST_PER_Q
) {
10443 sg_list_dwords
= (uchar
)(ASC_SG_LIST_PER_Q
* 2);
10444 sg_entry_cnt
-= ASC_SG_LIST_PER_Q
;
10446 scsi_sg_q
.sg_list_cnt
=
10448 scsi_sg_q
.sg_cur_list_cnt
=
10451 scsi_sg_q
.sg_list_cnt
=
10452 ASC_SG_LIST_PER_Q
- 1;
10453 scsi_sg_q
.sg_cur_list_cnt
=
10454 ASC_SG_LIST_PER_Q
- 1;
10457 #if CC_VERY_LONG_SG_LIST
10459 * This is the last SG queue in the list of
10460 * allocated SG queues. If there are more
10461 * SG elements than will fit in the allocated
10462 * queues, then set the QCSG_SG_XFER_MORE flag.
10464 if (sg_head
->entry_cnt
> ASC_MAX_SG_LIST
) {
10465 scsi_sg_q
.cntl
|= QCSG_SG_XFER_MORE
;
10467 #endif /* CC_VERY_LONG_SG_LIST */
10468 scsi_sg_q
.cntl
|= QCSG_SG_XFER_END
;
10469 #if CC_VERY_LONG_SG_LIST
10471 #endif /* CC_VERY_LONG_SG_LIST */
10472 sg_list_dwords
= sg_entry_cnt
<< 1;
10474 scsi_sg_q
.sg_list_cnt
= sg_entry_cnt
;
10475 scsi_sg_q
.sg_cur_list_cnt
=
10478 scsi_sg_q
.sg_list_cnt
=
10480 scsi_sg_q
.sg_cur_list_cnt
=
10485 next_qp
= AscReadLramByte(iop_base
,
10488 scsi_sg_q
.q_no
= next_qp
;
10489 q_addr
= ASC_QNO_TO_QADDR(next_qp
);
10490 AscMemWordCopyPtrToLram(iop_base
,
10491 q_addr
+ ASC_SCSIQ_SGHD_CPY_BEG
,
10492 (uchar
*)&scsi_sg_q
,
10493 sizeof(ASC_SG_LIST_Q
) >> 1);
10494 AscMemDWordCopyPtrToLram(iop_base
,
10495 q_addr
+ ASC_SGQ_LIST_BEG
,
10496 (uchar
*)&sg_head
->
10499 sg_index
+= ASC_SG_LIST_PER_Q
;
10500 scsiq
->next_sg_index
= sg_index
;
10503 scsiq
->q1
.cntl
&= ~QC_SG_HEAD
;
10505 sta
= AscPutReadyQueue(asc_dvc
, scsiq
, q_no
);
10506 scsiq
->q1
.data_addr
= saved_data_addr
;
10507 scsiq
->q1
.data_cnt
= saved_data_cnt
;
10512 AscSendScsiQueue(ASC_DVC_VAR
*asc_dvc
, ASC_SCSI_Q
*scsiq
, uchar n_q_required
)
10521 iop_base
= asc_dvc
->iop_base
;
10522 target_ix
= scsiq
->q2
.target_ix
;
10523 tid_no
= ASC_TIX_TO_TID(target_ix
);
10525 free_q_head
= (uchar
)AscGetVarFreeQHead(iop_base
);
10526 if (n_q_required
> 1) {
10527 next_qp
= AscAllocMultipleFreeQueue(iop_base
, free_q_head
,
10528 (uchar
)n_q_required
);
10529 if (next_qp
!= ASC_QLINK_END
) {
10530 asc_dvc
->last_q_shortage
= 0;
10531 scsiq
->sg_head
->queue_cnt
= n_q_required
- 1;
10532 scsiq
->q1
.q_no
= free_q_head
;
10533 sta
= AscPutReadySgListQueue(asc_dvc
, scsiq
,
10536 } else if (n_q_required
== 1) {
10537 next_qp
= AscAllocFreeQueue(iop_base
, free_q_head
);
10538 if (next_qp
!= ASC_QLINK_END
) {
10539 scsiq
->q1
.q_no
= free_q_head
;
10540 sta
= AscPutReadyQueue(asc_dvc
, scsiq
, free_q_head
);
10544 AscPutVarFreeQHead(iop_base
, next_qp
);
10545 asc_dvc
->cur_total_qng
+= n_q_required
;
10546 asc_dvc
->cur_dvc_qng
[tid_no
]++;
10551 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
10552 static uchar _syn_offset_one_disable_cmd
[ASC_SYN_OFFSET_ONE_DISABLE_LIST
] = {
10571 static int AscExeScsiQueue(ASC_DVC_VAR
*asc_dvc
, ASC_SCSI_Q
*scsiq
)
10576 int disable_syn_offset_one_fix
;
10579 ushort sg_entry_cnt
= 0;
10580 ushort sg_entry_cnt_minus_one
= 0;
10587 ASC_SG_HEAD
*sg_head
;
10590 iop_base
= asc_dvc
->iop_base
;
10591 sg_head
= scsiq
->sg_head
;
10592 if (asc_dvc
->err_code
!= 0)
10594 scsiq
->q1
.q_no
= 0;
10595 if ((scsiq
->q2
.tag_code
& ASC_TAG_FLAG_EXTRA_BYTES
) == 0) {
10596 scsiq
->q1
.extra_bytes
= 0;
10599 target_ix
= scsiq
->q2
.target_ix
;
10600 tid_no
= ASC_TIX_TO_TID(target_ix
);
10602 if (scsiq
->cdbptr
[0] == REQUEST_SENSE
) {
10603 if ((asc_dvc
->init_sdtr
& scsiq
->q1
.target_id
) != 0) {
10604 asc_dvc
->sdtr_done
&= ~scsiq
->q1
.target_id
;
10605 sdtr_data
= AscGetMCodeInitSDTRAtID(iop_base
, tid_no
);
10606 AscMsgOutSDTR(asc_dvc
,
10608 sdtr_period_tbl
[(sdtr_data
>> 4) &
10612 (uchar
)(sdtr_data
& (uchar
)
10613 ASC_SYN_MAX_OFFSET
));
10614 scsiq
->q1
.cntl
|= (QC_MSG_OUT
| QC_URGENT
);
10617 if (asc_dvc
->in_critical_cnt
!= 0) {
10618 AscSetLibErrorCode(asc_dvc
, ASCQ_ERR_CRITICAL_RE_ENTRY
);
10621 asc_dvc
->in_critical_cnt
++;
10622 if ((scsiq
->q1
.cntl
& QC_SG_HEAD
) != 0) {
10623 if ((sg_entry_cnt
= sg_head
->entry_cnt
) == 0) {
10624 asc_dvc
->in_critical_cnt
--;
10627 #if !CC_VERY_LONG_SG_LIST
10628 if (sg_entry_cnt
> ASC_MAX_SG_LIST
) {
10629 asc_dvc
->in_critical_cnt
--;
10632 #endif /* !CC_VERY_LONG_SG_LIST */
10633 if (sg_entry_cnt
== 1) {
10634 scsiq
->q1
.data_addr
=
10635 (ADV_PADDR
)sg_head
->sg_list
[0].addr
;
10636 scsiq
->q1
.data_cnt
=
10637 (ADV_DCNT
)sg_head
->sg_list
[0].bytes
;
10638 scsiq
->q1
.cntl
&= ~(QC_SG_HEAD
| QC_SG_SWAP_QUEUE
);
10640 sg_entry_cnt_minus_one
= sg_entry_cnt
- 1;
10642 scsi_cmd
= scsiq
->cdbptr
[0];
10643 disable_syn_offset_one_fix
= FALSE
;
10644 if ((asc_dvc
->pci_fix_asyn_xfer
& scsiq
->q1
.target_id
) &&
10645 !(asc_dvc
->pci_fix_asyn_xfer_always
& scsiq
->q1
.target_id
)) {
10646 if (scsiq
->q1
.cntl
& QC_SG_HEAD
) {
10648 for (i
= 0; i
< sg_entry_cnt
; i
++) {
10650 (ADV_DCNT
)le32_to_cpu(sg_head
->sg_list
[i
].
10654 data_cnt
= le32_to_cpu(scsiq
->q1
.data_cnt
);
10656 if (data_cnt
!= 0UL) {
10657 if (data_cnt
< 512UL) {
10658 disable_syn_offset_one_fix
= TRUE
;
10660 for (i
= 0; i
< ASC_SYN_OFFSET_ONE_DISABLE_LIST
;
10663 _syn_offset_one_disable_cmd
[i
];
10664 if (disable_cmd
== 0xFF) {
10667 if (scsi_cmd
== disable_cmd
) {
10668 disable_syn_offset_one_fix
=
10676 if (disable_syn_offset_one_fix
) {
10677 scsiq
->q2
.tag_code
&= ~MSG_SIMPLE_TAG
;
10678 scsiq
->q2
.tag_code
|= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX
|
10679 ASC_TAG_FLAG_DISABLE_DISCONNECT
);
10681 scsiq
->q2
.tag_code
&= 0x27;
10683 if ((scsiq
->q1
.cntl
& QC_SG_HEAD
) != 0) {
10684 if (asc_dvc
->bug_fix_cntl
) {
10685 if (asc_dvc
->bug_fix_cntl
& ASC_BUG_FIX_IF_NOT_DWB
) {
10686 if ((scsi_cmd
== READ_6
) ||
10687 (scsi_cmd
== READ_10
)) {
10689 (ADV_PADDR
)le32_to_cpu(sg_head
->
10691 [sg_entry_cnt_minus_one
].
10693 (ADV_DCNT
)le32_to_cpu(sg_head
->
10695 [sg_entry_cnt_minus_one
].
10698 (uchar
)((ushort
)addr
& 0x0003);
10699 if ((extra_bytes
!= 0)
10703 ASC_TAG_FLAG_EXTRA_BYTES
)
10705 scsiq
->q2
.tag_code
|=
10706 ASC_TAG_FLAG_EXTRA_BYTES
;
10707 scsiq
->q1
.extra_bytes
=
10710 le32_to_cpu(sg_head
->
10712 [sg_entry_cnt_minus_one
].
10715 (ASC_DCNT
) extra_bytes
;
10718 [sg_entry_cnt_minus_one
].
10720 cpu_to_le32(data_cnt
);
10725 sg_head
->entry_to_copy
= sg_head
->entry_cnt
;
10726 #if CC_VERY_LONG_SG_LIST
10728 * Set the sg_entry_cnt to the maximum possible. The rest of
10729 * the SG elements will be copied when the RISC completes the
10730 * SG elements that fit and halts.
10732 if (sg_entry_cnt
> ASC_MAX_SG_LIST
) {
10733 sg_entry_cnt
= ASC_MAX_SG_LIST
;
10735 #endif /* CC_VERY_LONG_SG_LIST */
10736 n_q_required
= AscSgListToQueue(sg_entry_cnt
);
10737 if ((AscGetNumOfFreeQueue(asc_dvc
, target_ix
, n_q_required
) >=
10738 (uint
) n_q_required
)
10739 || ((scsiq
->q1
.cntl
& QC_URGENT
) != 0)) {
10741 AscSendScsiQueue(asc_dvc
, scsiq
,
10742 n_q_required
)) == 1) {
10743 asc_dvc
->in_critical_cnt
--;
10748 if (asc_dvc
->bug_fix_cntl
) {
10749 if (asc_dvc
->bug_fix_cntl
& ASC_BUG_FIX_IF_NOT_DWB
) {
10750 if ((scsi_cmd
== READ_6
) ||
10751 (scsi_cmd
== READ_10
)) {
10753 le32_to_cpu(scsiq
->q1
.data_addr
) +
10754 le32_to_cpu(scsiq
->q1
.data_cnt
);
10756 (uchar
)((ushort
)addr
& 0x0003);
10757 if ((extra_bytes
!= 0)
10761 ASC_TAG_FLAG_EXTRA_BYTES
)
10764 le32_to_cpu(scsiq
->q1
.
10766 if (((ushort
)data_cnt
& 0x01FF)
10768 scsiq
->q2
.tag_code
|=
10769 ASC_TAG_FLAG_EXTRA_BYTES
;
10770 data_cnt
-= (ASC_DCNT
)
10772 scsiq
->q1
.data_cnt
=
10775 scsiq
->q1
.extra_bytes
=
10783 if ((AscGetNumOfFreeQueue(asc_dvc
, target_ix
, 1) >= 1) ||
10784 ((scsiq
->q1
.cntl
& QC_URGENT
) != 0)) {
10785 if ((sta
= AscSendScsiQueue(asc_dvc
, scsiq
,
10786 n_q_required
)) == 1) {
10787 asc_dvc
->in_critical_cnt
--;
10792 asc_dvc
->in_critical_cnt
--;
10797 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
10799 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
10800 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
10801 * RISC to notify it a new command is ready to be executed.
10803 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
10804 * set to SCSI_MAX_RETRY.
10806 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
10807 * for DMA addresses or math operations are byte swapped to little-endian
10811 * ADV_SUCCESS(1) - The request was successfully queued.
10812 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
10813 * request completes.
10814 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
10817 static int AdvExeScsiQueue(ADV_DVC_VAR
*asc_dvc
, ADV_SCSI_REQ_Q
*scsiq
)
10819 AdvPortAddr iop_base
;
10820 ADV_PADDR req_paddr
;
10821 ADV_CARR_T
*new_carrp
;
10824 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
10826 if (scsiq
->target_id
> ADV_MAX_TID
) {
10827 scsiq
->host_status
= QHSTA_M_INVALID_DEVICE
;
10828 scsiq
->done_status
= QD_WITH_ERROR
;
10832 iop_base
= asc_dvc
->iop_base
;
10835 * Allocate a carrier ensuring at least one carrier always
10836 * remains on the freelist and initialize fields.
10838 if ((new_carrp
= asc_dvc
->carr_freelist
) == NULL
) {
10841 asc_dvc
->carr_freelist
= (ADV_CARR_T
*)
10842 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp
->next_vpa
));
10843 asc_dvc
->carr_pending_cnt
++;
10846 * Set the carrier to be a stopper by setting 'next_vpa'
10847 * to the stopper value. The current stopper will be changed
10848 * below to point to the new stopper.
10850 new_carrp
->next_vpa
= cpu_to_le32(ASC_CQ_STOPPER
);
10853 * Clear the ADV_SCSI_REQ_Q done flag.
10855 scsiq
->a_flag
&= ~ADV_SCSIQ_DONE
;
10857 req_paddr
= virt_to_bus(scsiq
);
10858 BUG_ON(req_paddr
& 31);
10859 /* Wait for assertion before making little-endian */
10860 req_paddr
= cpu_to_le32(req_paddr
);
10862 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
10863 scsiq
->scsiq_ptr
= cpu_to_le32(ADV_VADDR_TO_U32(scsiq
));
10864 scsiq
->scsiq_rptr
= req_paddr
;
10866 scsiq
->carr_va
= cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc
->icq_sp
));
10868 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
10869 * order during initialization.
10871 scsiq
->carr_pa
= asc_dvc
->icq_sp
->carr_pa
;
10874 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
10875 * the microcode. The newly allocated stopper will become the new
10878 asc_dvc
->icq_sp
->areq_vpa
= req_paddr
;
10881 * Set the 'next_vpa' pointer for the old stopper to be the
10882 * physical address of the new stopper. The RISC can only
10883 * follow physical addresses.
10885 asc_dvc
->icq_sp
->next_vpa
= new_carrp
->carr_pa
;
10888 * Set the host adapter stopper pointer to point to the new carrier.
10890 asc_dvc
->icq_sp
= new_carrp
;
10892 if (asc_dvc
->chip_type
== ADV_CHIP_ASC3550
||
10893 asc_dvc
->chip_type
== ADV_CHIP_ASC38C0800
) {
10895 * Tickle the RISC to tell it to read its Command Queue Head pointer.
10897 AdvWriteByteRegister(iop_base
, IOPB_TICKLE
, ADV_TICKLE_A
);
10898 if (asc_dvc
->chip_type
== ADV_CHIP_ASC3550
) {
10900 * Clear the tickle value. In the ASC-3550 the RISC flag
10901 * command 'clr_tickle_a' does not work unless the host
10902 * value is cleared.
10904 AdvWriteByteRegister(iop_base
, IOPB_TICKLE
,
10907 } else if (asc_dvc
->chip_type
== ADV_CHIP_ASC38C1600
) {
10909 * Notify the RISC a carrier is ready by writing the physical
10910 * address of the new carrier stopper to the COMMA register.
10912 AdvWriteDWordRegister(iop_base
, IOPDW_COMMA
,
10913 le32_to_cpu(new_carrp
->carr_pa
));
10916 return ADV_SUCCESS
;
10920 * Execute a single 'Scsi_Cmnd'.
10922 static int asc_execute_scsi_cmnd(struct scsi_cmnd
*scp
)
10925 struct asc_board
*boardp
= shost_priv(scp
->device
->host
);
10927 ASC_DBG(1, "scp 0x%p\n", scp
);
10929 if (ASC_NARROW_BOARD(boardp
)) {
10930 ASC_DVC_VAR
*asc_dvc
= &boardp
->dvc_var
.asc_dvc_var
;
10931 struct asc_scsi_q asc_scsi_q
;
10933 /* asc_build_req() can not return ASC_BUSY. */
10934 ret
= asc_build_req(boardp
, scp
, &asc_scsi_q
);
10935 if (ret
== ASC_ERROR
) {
10936 ASC_STATS(scp
->device
->host
, build_error
);
10940 ret
= AscExeScsiQueue(asc_dvc
, &asc_scsi_q
);
10941 kfree(asc_scsi_q
.sg_head
);
10942 err_code
= asc_dvc
->err_code
;
10944 ADV_DVC_VAR
*adv_dvc
= &boardp
->dvc_var
.adv_dvc_var
;
10945 ADV_SCSI_REQ_Q
*adv_scsiqp
;
10947 switch (adv_build_req(boardp
, scp
, &adv_scsiqp
)) {
10949 ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
10952 ASC_DBG(1, "adv_build_req ASC_BUSY\n");
10954 * The asc_stats fields 'adv_build_noreq' and
10955 * 'adv_build_nosg' count wide board busy conditions.
10956 * They are updated in adv_build_req and
10957 * adv_get_sglist, respectively.
10962 ASC_DBG(1, "adv_build_req ASC_ERROR\n");
10963 ASC_STATS(scp
->device
->host
, build_error
);
10967 ret
= AdvExeScsiQueue(adv_dvc
, adv_scsiqp
);
10968 err_code
= adv_dvc
->err_code
;
10973 ASC_STATS(scp
->device
->host
, exe_noerror
);
10975 * Increment monotonically increasing per device
10976 * successful request counter. Wrapping doesn't matter.
10978 boardp
->reqcnt
[scp
->device
->id
]++;
10979 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
10982 ASC_STATS(scp
->device
->host
, exe_busy
);
10985 scmd_printk(KERN_ERR
, scp
, "ExeScsiQueue() ASC_ERROR, "
10986 "err_code 0x%x\n", err_code
);
10987 ASC_STATS(scp
->device
->host
, exe_error
);
10988 scp
->result
= HOST_BYTE(DID_ERROR
);
10991 scmd_printk(KERN_ERR
, scp
, "ExeScsiQueue() unknown, "
10992 "err_code 0x%x\n", err_code
);
10993 ASC_STATS(scp
->device
->host
, exe_unknown
);
10994 scp
->result
= HOST_BYTE(DID_ERROR
);
10998 ASC_DBG(1, "end\n");
11003 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
11005 * This function always returns 0. Command return status is saved
11006 * in the 'scp' result field.
11009 advansys_queuecommand(struct scsi_cmnd
*scp
, void (*done
)(struct scsi_cmnd
*))
11011 struct Scsi_Host
*shost
= scp
->device
->host
;
11012 int asc_res
, result
= 0;
11014 ASC_STATS(shost
, queuecommand
);
11015 scp
->scsi_done
= done
;
11017 asc_res
= asc_execute_scsi_cmnd(scp
);
11023 result
= SCSI_MLQUEUE_HOST_BUSY
;
11027 asc_scsi_done(scp
);
11034 static ushort __devinit
AscGetEisaChipCfg(PortAddr iop_base
)
11036 PortAddr eisa_cfg_iop
= (PortAddr
) ASC_GET_EISA_SLOT(iop_base
) |
11037 (PortAddr
) (ASC_EISA_CFG_IOP_MASK
);
11038 return inpw(eisa_cfg_iop
);
11042 * Return the BIOS address of the adapter at the specified
11043 * I/O port and with the specified bus type.
11045 static unsigned short __devinit
11046 AscGetChipBiosAddress(PortAddr iop_base
, unsigned short bus_type
)
11048 unsigned short cfg_lsw
;
11049 unsigned short bios_addr
;
11052 * The PCI BIOS is re-located by the motherboard BIOS. Because
11053 * of this the driver can not determine where a PCI BIOS is
11054 * loaded and executes.
11056 if (bus_type
& ASC_IS_PCI
)
11059 if ((bus_type
& ASC_IS_EISA
) != 0) {
11060 cfg_lsw
= AscGetEisaChipCfg(iop_base
);
11062 bios_addr
= ASC_BIOS_MIN_ADDR
+ cfg_lsw
* ASC_BIOS_BANK_SIZE
;
11066 cfg_lsw
= AscGetChipCfgLsw(iop_base
);
11069 * ISA PnP uses the top bit as the 32K BIOS flag
11071 if (bus_type
== ASC_IS_ISAPNP
)
11073 bios_addr
= ASC_BIOS_MIN_ADDR
+ (cfg_lsw
>> 12) * ASC_BIOS_BANK_SIZE
;
11077 static uchar __devinit
AscSetChipScsiID(PortAddr iop_base
, uchar new_host_id
)
11081 if (AscGetChipScsiID(iop_base
) == new_host_id
) {
11082 return (new_host_id
);
11084 cfg_lsw
= AscGetChipCfgLsw(iop_base
);
11086 cfg_lsw
|= (ushort
)((new_host_id
& ASC_MAX_TID
) << 8);
11087 AscSetChipCfgLsw(iop_base
, cfg_lsw
);
11088 return (AscGetChipScsiID(iop_base
));
11091 static unsigned char __devinit
AscGetChipScsiCtrl(PortAddr iop_base
)
11095 AscSetBank(iop_base
, 1);
11096 sc
= inp(iop_base
+ IOP_REG_SC
);
11097 AscSetBank(iop_base
, 0);
11101 static unsigned char __devinit
11102 AscGetChipVersion(PortAddr iop_base
, unsigned short bus_type
)
11104 if (bus_type
& ASC_IS_EISA
) {
11106 unsigned char revision
;
11107 eisa_iop
= (PortAddr
) ASC_GET_EISA_SLOT(iop_base
) |
11108 (PortAddr
) ASC_EISA_REV_IOP_MASK
;
11109 revision
= inp(eisa_iop
);
11110 return ASC_CHIP_MIN_VER_EISA
- 1 + revision
;
11112 return AscGetChipVerNo(iop_base
);
11116 static void __devinit
AscEnableIsaDma(uchar dma_channel
)
11118 if (dma_channel
< 4) {
11119 outp(0x000B, (ushort
)(0xC0 | dma_channel
));
11120 outp(0x000A, dma_channel
);
11121 } else if (dma_channel
< 8) {
11122 outp(0x00D6, (ushort
)(0xC0 | (dma_channel
- 4)));
11123 outp(0x00D4, (ushort
)(dma_channel
- 4));
11126 #endif /* CONFIG_ISA */
11128 static int AscStopQueueExe(PortAddr iop_base
)
11132 if (AscReadLramByte(iop_base
, ASCV_STOP_CODE_B
) == 0) {
11133 AscWriteLramByte(iop_base
, ASCV_STOP_CODE_B
,
11134 ASC_STOP_REQ_RISC_STOP
);
11136 if (AscReadLramByte(iop_base
, ASCV_STOP_CODE_B
) &
11137 ASC_STOP_ACK_RISC_STOP
) {
11141 } while (count
++ < 20);
11146 static ASC_DCNT __devinit
AscGetMaxDmaCount(ushort bus_type
)
11148 if (bus_type
& ASC_IS_ISA
)
11149 return ASC_MAX_ISA_DMA_COUNT
;
11150 else if (bus_type
& (ASC_IS_EISA
| ASC_IS_VL
))
11151 return ASC_MAX_VL_DMA_COUNT
;
11152 return ASC_MAX_PCI_DMA_COUNT
;
11156 static ushort __devinit
AscGetIsaDmaChannel(PortAddr iop_base
)
11160 channel
= AscGetChipCfgLsw(iop_base
) & 0x0003;
11161 if (channel
== 0x03)
11163 else if (channel
== 0x00)
11165 return (channel
+ 4);
11168 static ushort __devinit
AscSetIsaDmaChannel(PortAddr iop_base
, ushort dma_channel
)
11173 if ((dma_channel
>= 5) && (dma_channel
<= 7)) {
11174 if (dma_channel
== 7)
11177 value
= dma_channel
- 4;
11178 cfg_lsw
= AscGetChipCfgLsw(iop_base
) & 0xFFFC;
11180 AscSetChipCfgLsw(iop_base
, cfg_lsw
);
11181 return (AscGetIsaDmaChannel(iop_base
));
11186 static uchar __devinit
AscGetIsaDmaSpeed(PortAddr iop_base
)
11190 AscSetBank(iop_base
, 1);
11191 speed_value
= AscReadChipDmaSpeed(iop_base
);
11192 speed_value
&= 0x07;
11193 AscSetBank(iop_base
, 0);
11194 return speed_value
;
11197 static uchar __devinit
AscSetIsaDmaSpeed(PortAddr iop_base
, uchar speed_value
)
11199 speed_value
&= 0x07;
11200 AscSetBank(iop_base
, 1);
11201 AscWriteChipDmaSpeed(iop_base
, speed_value
);
11202 AscSetBank(iop_base
, 0);
11203 return AscGetIsaDmaSpeed(iop_base
);
11205 #endif /* CONFIG_ISA */
11207 static ushort __devinit
AscInitAscDvcVar(ASC_DVC_VAR
*asc_dvc
)
11212 uchar chip_version
;
11214 iop_base
= asc_dvc
->iop_base
;
11216 asc_dvc
->err_code
= 0;
11217 if ((asc_dvc
->bus_type
&
11218 (ASC_IS_ISA
| ASC_IS_PCI
| ASC_IS_EISA
| ASC_IS_VL
)) == 0) {
11219 asc_dvc
->err_code
|= ASC_IERR_NO_BUS_TYPE
;
11221 AscSetChipControl(iop_base
, CC_HALT
);
11222 AscSetChipStatus(iop_base
, 0);
11223 asc_dvc
->bug_fix_cntl
= 0;
11224 asc_dvc
->pci_fix_asyn_xfer
= 0;
11225 asc_dvc
->pci_fix_asyn_xfer_always
= 0;
11226 /* asc_dvc->init_state initalized in AscInitGetConfig(). */
11227 asc_dvc
->sdtr_done
= 0;
11228 asc_dvc
->cur_total_qng
= 0;
11229 asc_dvc
->is_in_int
= 0;
11230 asc_dvc
->in_critical_cnt
= 0;
11231 asc_dvc
->last_q_shortage
= 0;
11232 asc_dvc
->use_tagged_qng
= 0;
11233 asc_dvc
->no_scam
= 0;
11234 asc_dvc
->unit_not_ready
= 0;
11235 asc_dvc
->queue_full_or_busy
= 0;
11236 asc_dvc
->redo_scam
= 0;
11238 asc_dvc
->min_sdtr_index
= 0;
11239 asc_dvc
->cfg
->can_tagged_qng
= 0;
11240 asc_dvc
->cfg
->cmd_qng_enabled
= 0;
11241 asc_dvc
->dvc_cntl
= ASC_DEF_DVC_CNTL
;
11242 asc_dvc
->init_sdtr
= 0;
11243 asc_dvc
->max_total_qng
= ASC_DEF_MAX_TOTAL_QNG
;
11244 asc_dvc
->scsi_reset_wait
= 3;
11245 asc_dvc
->start_motor
= ASC_SCSI_WIDTH_BIT_SET
;
11246 asc_dvc
->max_dma_count
= AscGetMaxDmaCount(asc_dvc
->bus_type
);
11247 asc_dvc
->cfg
->sdtr_enable
= ASC_SCSI_WIDTH_BIT_SET
;
11248 asc_dvc
->cfg
->disc_enable
= ASC_SCSI_WIDTH_BIT_SET
;
11249 asc_dvc
->cfg
->chip_scsi_id
= ASC_DEF_CHIP_SCSI_ID
;
11250 chip_version
= AscGetChipVersion(iop_base
, asc_dvc
->bus_type
);
11251 asc_dvc
->cfg
->chip_version
= chip_version
;
11252 asc_dvc
->sdtr_period_tbl
= asc_syn_xfer_period
;
11253 asc_dvc
->max_sdtr_index
= 7;
11254 if ((asc_dvc
->bus_type
& ASC_IS_PCI
) &&
11255 (chip_version
>= ASC_CHIP_VER_PCI_ULTRA_3150
)) {
11256 asc_dvc
->bus_type
= ASC_IS_PCI_ULTRA
;
11257 asc_dvc
->sdtr_period_tbl
= asc_syn_ultra_xfer_period
;
11258 asc_dvc
->max_sdtr_index
= 15;
11259 if (chip_version
== ASC_CHIP_VER_PCI_ULTRA_3150
) {
11260 AscSetExtraControl(iop_base
,
11261 (SEC_ACTIVE_NEGATE
| SEC_SLEW_RATE
));
11262 } else if (chip_version
>= ASC_CHIP_VER_PCI_ULTRA_3050
) {
11263 AscSetExtraControl(iop_base
,
11264 (SEC_ACTIVE_NEGATE
|
11265 SEC_ENABLE_FILTER
));
11268 if (asc_dvc
->bus_type
== ASC_IS_PCI
) {
11269 AscSetExtraControl(iop_base
,
11270 (SEC_ACTIVE_NEGATE
| SEC_SLEW_RATE
));
11273 asc_dvc
->cfg
->isa_dma_speed
= ASC_DEF_ISA_DMA_SPEED
;
11275 if ((asc_dvc
->bus_type
& ASC_IS_ISA
) != 0) {
11276 if (chip_version
>= ASC_CHIP_MIN_VER_ISA_PNP
) {
11277 AscSetChipIFC(iop_base
, IFC_INIT_DEFAULT
);
11278 asc_dvc
->bus_type
= ASC_IS_ISAPNP
;
11280 asc_dvc
->cfg
->isa_dma_channel
=
11281 (uchar
)AscGetIsaDmaChannel(iop_base
);
11283 #endif /* CONFIG_ISA */
11284 for (i
= 0; i
<= ASC_MAX_TID
; i
++) {
11285 asc_dvc
->cur_dvc_qng
[i
] = 0;
11286 asc_dvc
->max_dvc_qng
[i
] = ASC_MAX_SCSI1_QNG
;
11287 asc_dvc
->scsiq_busy_head
[i
] = (ASC_SCSI_Q
*)0L;
11288 asc_dvc
->scsiq_busy_tail
[i
] = (ASC_SCSI_Q
*)0L;
11289 asc_dvc
->cfg
->max_tag_qng
[i
] = ASC_MAX_INRAM_TAG_QNG
;
11294 static int __devinit
AscWriteEEPCmdReg(PortAddr iop_base
, uchar cmd_reg
)
11298 for (retry
= 0; retry
< ASC_EEP_MAX_RETRY
; retry
++) {
11299 unsigned char read_back
;
11300 AscSetChipEEPCmd(iop_base
, cmd_reg
);
11302 read_back
= AscGetChipEEPCmd(iop_base
);
11303 if (read_back
== cmd_reg
)
11309 static void __devinit
AscWaitEEPRead(void)
11314 static ushort __devinit
AscReadEEPWord(PortAddr iop_base
, uchar addr
)
11319 AscWriteEEPCmdReg(iop_base
, ASC_EEP_CMD_WRITE_DISABLE
);
11321 cmd_reg
= addr
| ASC_EEP_CMD_READ
;
11322 AscWriteEEPCmdReg(iop_base
, cmd_reg
);
11324 read_wval
= AscGetChipEEPData(iop_base
);
11329 static ushort __devinit
11330 AscGetEEPConfig(PortAddr iop_base
, ASCEEP_CONFIG
*cfg_buf
, ushort bus_type
)
11337 int uchar_end_in_config
= ASC_EEP_MAX_DVC_ADDR
- 2;
11340 wbuf
= (ushort
*)cfg_buf
;
11342 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
11343 for (s_addr
= 0; s_addr
< 2; s_addr
++, wbuf
++) {
11344 *wbuf
= AscReadEEPWord(iop_base
, (uchar
)s_addr
);
11347 if (bus_type
& ASC_IS_VL
) {
11348 cfg_beg
= ASC_EEP_DVC_CFG_BEG_VL
;
11349 cfg_end
= ASC_EEP_MAX_DVC_ADDR_VL
;
11351 cfg_beg
= ASC_EEP_DVC_CFG_BEG
;
11352 cfg_end
= ASC_EEP_MAX_DVC_ADDR
;
11354 for (s_addr
= cfg_beg
; s_addr
<= (cfg_end
- 1); s_addr
++, wbuf
++) {
11355 wval
= AscReadEEPWord(iop_base
, (uchar
)s_addr
);
11356 if (s_addr
<= uchar_end_in_config
) {
11358 * Swap all char fields - must unswap bytes already swapped
11359 * by AscReadEEPWord().
11361 *wbuf
= le16_to_cpu(wval
);
11363 /* Don't swap word field at the end - cntl field. */
11366 sum
+= wval
; /* Checksum treats all EEPROM data as words. */
11369 * Read the checksum word which will be compared against 'sum'
11370 * by the caller. Word field already swapped.
11372 *wbuf
= AscReadEEPWord(iop_base
, (uchar
)s_addr
);
11376 static int __devinit
AscTestExternalLram(ASC_DVC_VAR
*asc_dvc
)
11383 iop_base
= asc_dvc
->iop_base
;
11385 q_addr
= ASC_QNO_TO_QADDR(241);
11386 saved_word
= AscReadLramWord(iop_base
, q_addr
);
11387 AscSetChipLramAddr(iop_base
, q_addr
);
11388 AscSetChipLramData(iop_base
, 0x55AA);
11390 AscSetChipLramAddr(iop_base
, q_addr
);
11391 if (AscGetChipLramData(iop_base
) == 0x55AA) {
11393 AscWriteLramWord(iop_base
, q_addr
, saved_word
);
11398 static void __devinit
AscWaitEEPWrite(void)
11403 static int __devinit
AscWriteEEPDataReg(PortAddr iop_base
, ushort data_reg
)
11410 AscSetChipEEPData(iop_base
, data_reg
);
11412 read_back
= AscGetChipEEPData(iop_base
);
11413 if (read_back
== data_reg
) {
11416 if (retry
++ > ASC_EEP_MAX_RETRY
) {
11422 static ushort __devinit
11423 AscWriteEEPWord(PortAddr iop_base
, uchar addr
, ushort word_val
)
11427 read_wval
= AscReadEEPWord(iop_base
, addr
);
11428 if (read_wval
!= word_val
) {
11429 AscWriteEEPCmdReg(iop_base
, ASC_EEP_CMD_WRITE_ABLE
);
11431 AscWriteEEPDataReg(iop_base
, word_val
);
11433 AscWriteEEPCmdReg(iop_base
,
11434 (uchar
)((uchar
)ASC_EEP_CMD_WRITE
| addr
));
11436 AscWriteEEPCmdReg(iop_base
, ASC_EEP_CMD_WRITE_DISABLE
);
11438 return (AscReadEEPWord(iop_base
, addr
));
11440 return (read_wval
);
11443 static int __devinit
11444 AscSetEEPConfigOnce(PortAddr iop_base
, ASCEEP_CONFIG
*cfg_buf
, ushort bus_type
)
11453 int uchar_end_in_config
= ASC_EEP_MAX_DVC_ADDR
- 2;
11455 wbuf
= (ushort
*)cfg_buf
;
11458 /* Write two config words; AscWriteEEPWord() will swap bytes. */
11459 for (s_addr
= 0; s_addr
< 2; s_addr
++, wbuf
++) {
11461 if (*wbuf
!= AscWriteEEPWord(iop_base
, (uchar
)s_addr
, *wbuf
)) {
11465 if (bus_type
& ASC_IS_VL
) {
11466 cfg_beg
= ASC_EEP_DVC_CFG_BEG_VL
;
11467 cfg_end
= ASC_EEP_MAX_DVC_ADDR_VL
;
11469 cfg_beg
= ASC_EEP_DVC_CFG_BEG
;
11470 cfg_end
= ASC_EEP_MAX_DVC_ADDR
;
11472 for (s_addr
= cfg_beg
; s_addr
<= (cfg_end
- 1); s_addr
++, wbuf
++) {
11473 if (s_addr
<= uchar_end_in_config
) {
11475 * This is a char field. Swap char fields before they are
11476 * swapped again by AscWriteEEPWord().
11478 word
= cpu_to_le16(*wbuf
);
11480 AscWriteEEPWord(iop_base
, (uchar
)s_addr
, word
)) {
11484 /* Don't swap word field at the end - cntl field. */
11486 AscWriteEEPWord(iop_base
, (uchar
)s_addr
, *wbuf
)) {
11490 sum
+= *wbuf
; /* Checksum calculated from word values. */
11492 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
11494 if (sum
!= AscWriteEEPWord(iop_base
, (uchar
)s_addr
, sum
)) {
11498 /* Read EEPROM back again. */
11499 wbuf
= (ushort
*)cfg_buf
;
11501 * Read two config words; Byte-swapping done by AscReadEEPWord().
11503 for (s_addr
= 0; s_addr
< 2; s_addr
++, wbuf
++) {
11504 if (*wbuf
!= AscReadEEPWord(iop_base
, (uchar
)s_addr
)) {
11508 if (bus_type
& ASC_IS_VL
) {
11509 cfg_beg
= ASC_EEP_DVC_CFG_BEG_VL
;
11510 cfg_end
= ASC_EEP_MAX_DVC_ADDR_VL
;
11512 cfg_beg
= ASC_EEP_DVC_CFG_BEG
;
11513 cfg_end
= ASC_EEP_MAX_DVC_ADDR
;
11515 for (s_addr
= cfg_beg
; s_addr
<= (cfg_end
- 1); s_addr
++, wbuf
++) {
11516 if (s_addr
<= uchar_end_in_config
) {
11518 * Swap all char fields. Must unswap bytes already swapped
11519 * by AscReadEEPWord().
11522 le16_to_cpu(AscReadEEPWord
11523 (iop_base
, (uchar
)s_addr
));
11525 /* Don't swap word field at the end - cntl field. */
11526 word
= AscReadEEPWord(iop_base
, (uchar
)s_addr
);
11528 if (*wbuf
!= word
) {
11532 /* Read checksum; Byte swapping not needed. */
11533 if (AscReadEEPWord(iop_base
, (uchar
)s_addr
) != sum
) {
11539 static int __devinit
11540 AscSetEEPConfig(PortAddr iop_base
, ASCEEP_CONFIG
*cfg_buf
, ushort bus_type
)
11547 if ((n_error
= AscSetEEPConfigOnce(iop_base
, cfg_buf
,
11551 if (++retry
> ASC_EEP_MAX_RETRY
) {
11558 static ushort __devinit
AscInitFromEEP(ASC_DVC_VAR
*asc_dvc
)
11560 ASCEEP_CONFIG eep_config_buf
;
11561 ASCEEP_CONFIG
*eep_config
;
11565 ushort cfg_msw
, cfg_lsw
;
11569 iop_base
= asc_dvc
->iop_base
;
11571 AscWriteLramWord(iop_base
, ASCV_HALTCODE_W
, 0x00FE);
11572 AscStopQueueExe(iop_base
);
11573 if ((AscStopChip(iop_base
) == FALSE
) ||
11574 (AscGetChipScsiCtrl(iop_base
) != 0)) {
11575 asc_dvc
->init_state
|= ASC_INIT_RESET_SCSI_DONE
;
11576 AscResetChipAndScsiBus(asc_dvc
);
11577 mdelay(asc_dvc
->scsi_reset_wait
* 1000); /* XXX: msleep? */
11579 if (AscIsChipHalted(iop_base
) == FALSE
) {
11580 asc_dvc
->err_code
|= ASC_IERR_START_STOP_CHIP
;
11581 return (warn_code
);
11583 AscSetPCAddr(iop_base
, ASC_MCODE_START_ADDR
);
11584 if (AscGetPCAddr(iop_base
) != ASC_MCODE_START_ADDR
) {
11585 asc_dvc
->err_code
|= ASC_IERR_SET_PC_ADDR
;
11586 return (warn_code
);
11588 eep_config
= (ASCEEP_CONFIG
*)&eep_config_buf
;
11589 cfg_msw
= AscGetChipCfgMsw(iop_base
);
11590 cfg_lsw
= AscGetChipCfgLsw(iop_base
);
11591 if ((cfg_msw
& ASC_CFG_MSW_CLR_MASK
) != 0) {
11592 cfg_msw
&= ~ASC_CFG_MSW_CLR_MASK
;
11593 warn_code
|= ASC_WARN_CFG_MSW_RECOVER
;
11594 AscSetChipCfgMsw(iop_base
, cfg_msw
);
11596 chksum
= AscGetEEPConfig(iop_base
, eep_config
, asc_dvc
->bus_type
);
11597 ASC_DBG(1, "chksum 0x%x\n", chksum
);
11601 if (AscGetChipStatus(iop_base
) & CSW_AUTO_CONFIG
) {
11602 warn_code
|= ASC_WARN_AUTO_CONFIG
;
11603 if (asc_dvc
->cfg
->chip_version
== 3) {
11604 if (eep_config
->cfg_lsw
!= cfg_lsw
) {
11605 warn_code
|= ASC_WARN_EEPROM_RECOVER
;
11606 eep_config
->cfg_lsw
=
11607 AscGetChipCfgLsw(iop_base
);
11609 if (eep_config
->cfg_msw
!= cfg_msw
) {
11610 warn_code
|= ASC_WARN_EEPROM_RECOVER
;
11611 eep_config
->cfg_msw
=
11612 AscGetChipCfgMsw(iop_base
);
11616 eep_config
->cfg_msw
&= ~ASC_CFG_MSW_CLR_MASK
;
11617 eep_config
->cfg_lsw
|= ASC_CFG0_HOST_INT_ON
;
11618 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config
->chksum
);
11619 if (chksum
!= eep_config
->chksum
) {
11620 if (AscGetChipVersion(iop_base
, asc_dvc
->bus_type
) ==
11621 ASC_CHIP_VER_PCI_ULTRA_3050
) {
11622 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
11623 eep_config
->init_sdtr
= 0xFF;
11624 eep_config
->disc_enable
= 0xFF;
11625 eep_config
->start_motor
= 0xFF;
11626 eep_config
->use_cmd_qng
= 0;
11627 eep_config
->max_total_qng
= 0xF0;
11628 eep_config
->max_tag_qng
= 0x20;
11629 eep_config
->cntl
= 0xBFFF;
11630 ASC_EEP_SET_CHIP_ID(eep_config
, 7);
11631 eep_config
->no_scam
= 0;
11632 eep_config
->adapter_info
[0] = 0;
11633 eep_config
->adapter_info
[1] = 0;
11634 eep_config
->adapter_info
[2] = 0;
11635 eep_config
->adapter_info
[3] = 0;
11636 eep_config
->adapter_info
[4] = 0;
11637 /* Indicate EEPROM-less board. */
11638 eep_config
->adapter_info
[5] = 0xBB;
11641 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
11643 warn_code
|= ASC_WARN_EEPROM_CHKSUM
;
11646 asc_dvc
->cfg
->sdtr_enable
= eep_config
->init_sdtr
;
11647 asc_dvc
->cfg
->disc_enable
= eep_config
->disc_enable
;
11648 asc_dvc
->cfg
->cmd_qng_enabled
= eep_config
->use_cmd_qng
;
11649 asc_dvc
->cfg
->isa_dma_speed
= ASC_EEP_GET_DMA_SPD(eep_config
);
11650 asc_dvc
->start_motor
= eep_config
->start_motor
;
11651 asc_dvc
->dvc_cntl
= eep_config
->cntl
;
11652 asc_dvc
->no_scam
= eep_config
->no_scam
;
11653 asc_dvc
->cfg
->adapter_info
[0] = eep_config
->adapter_info
[0];
11654 asc_dvc
->cfg
->adapter_info
[1] = eep_config
->adapter_info
[1];
11655 asc_dvc
->cfg
->adapter_info
[2] = eep_config
->adapter_info
[2];
11656 asc_dvc
->cfg
->adapter_info
[3] = eep_config
->adapter_info
[3];
11657 asc_dvc
->cfg
->adapter_info
[4] = eep_config
->adapter_info
[4];
11658 asc_dvc
->cfg
->adapter_info
[5] = eep_config
->adapter_info
[5];
11659 if (!AscTestExternalLram(asc_dvc
)) {
11660 if (((asc_dvc
->bus_type
& ASC_IS_PCI_ULTRA
) ==
11661 ASC_IS_PCI_ULTRA
)) {
11662 eep_config
->max_total_qng
=
11663 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG
;
11664 eep_config
->max_tag_qng
=
11665 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG
;
11667 eep_config
->cfg_msw
|= 0x0800;
11669 AscSetChipCfgMsw(iop_base
, cfg_msw
);
11670 eep_config
->max_total_qng
= ASC_MAX_PCI_INRAM_TOTAL_QNG
;
11671 eep_config
->max_tag_qng
= ASC_MAX_INRAM_TAG_QNG
;
11675 if (eep_config
->max_total_qng
< ASC_MIN_TOTAL_QNG
) {
11676 eep_config
->max_total_qng
= ASC_MIN_TOTAL_QNG
;
11678 if (eep_config
->max_total_qng
> ASC_MAX_TOTAL_QNG
) {
11679 eep_config
->max_total_qng
= ASC_MAX_TOTAL_QNG
;
11681 if (eep_config
->max_tag_qng
> eep_config
->max_total_qng
) {
11682 eep_config
->max_tag_qng
= eep_config
->max_total_qng
;
11684 if (eep_config
->max_tag_qng
< ASC_MIN_TAG_Q_PER_DVC
) {
11685 eep_config
->max_tag_qng
= ASC_MIN_TAG_Q_PER_DVC
;
11687 asc_dvc
->max_total_qng
= eep_config
->max_total_qng
;
11688 if ((eep_config
->use_cmd_qng
& eep_config
->disc_enable
) !=
11689 eep_config
->use_cmd_qng
) {
11690 eep_config
->disc_enable
= eep_config
->use_cmd_qng
;
11691 warn_code
|= ASC_WARN_CMD_QNG_CONFLICT
;
11693 ASC_EEP_SET_CHIP_ID(eep_config
,
11694 ASC_EEP_GET_CHIP_ID(eep_config
) & ASC_MAX_TID
);
11695 asc_dvc
->cfg
->chip_scsi_id
= ASC_EEP_GET_CHIP_ID(eep_config
);
11696 if (((asc_dvc
->bus_type
& ASC_IS_PCI_ULTRA
) == ASC_IS_PCI_ULTRA
) &&
11697 !(asc_dvc
->dvc_cntl
& ASC_CNTL_SDTR_ENABLE_ULTRA
)) {
11698 asc_dvc
->min_sdtr_index
= ASC_SDTR_ULTRA_PCI_10MB_INDEX
;
11701 for (i
= 0; i
<= ASC_MAX_TID
; i
++) {
11702 asc_dvc
->dos_int13_table
[i
] = eep_config
->dos_int13_table
[i
];
11703 asc_dvc
->cfg
->max_tag_qng
[i
] = eep_config
->max_tag_qng
;
11704 asc_dvc
->cfg
->sdtr_period_offset
[i
] =
11705 (uchar
)(ASC_DEF_SDTR_OFFSET
|
11706 (asc_dvc
->min_sdtr_index
<< 4));
11708 eep_config
->cfg_msw
= AscGetChipCfgMsw(iop_base
);
11710 if ((i
= AscSetEEPConfig(iop_base
, eep_config
,
11711 asc_dvc
->bus_type
)) != 0) {
11713 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
11717 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
11720 return (warn_code
);
11723 static int __devinit
AscInitGetConfig(struct Scsi_Host
*shost
)
11725 struct asc_board
*board
= shost_priv(shost
);
11726 ASC_DVC_VAR
*asc_dvc
= &board
->dvc_var
.asc_dvc_var
;
11727 unsigned short warn_code
= 0;
11729 asc_dvc
->init_state
= ASC_INIT_STATE_BEG_GET_CFG
;
11730 if (asc_dvc
->err_code
!= 0)
11731 return asc_dvc
->err_code
;
11733 if (AscFindSignature(asc_dvc
->iop_base
)) {
11734 warn_code
|= AscInitAscDvcVar(asc_dvc
);
11735 warn_code
|= AscInitFromEEP(asc_dvc
);
11736 asc_dvc
->init_state
|= ASC_INIT_STATE_END_GET_CFG
;
11737 if (asc_dvc
->scsi_reset_wait
> ASC_MAX_SCSI_RESET_WAIT
)
11738 asc_dvc
->scsi_reset_wait
= ASC_MAX_SCSI_RESET_WAIT
;
11740 asc_dvc
->err_code
= ASC_IERR_BAD_SIGNATURE
;
11743 switch (warn_code
) {
11744 case 0: /* No error */
11746 case ASC_WARN_IO_PORT_ROTATE
:
11747 shost_printk(KERN_WARNING
, shost
, "I/O port address "
11750 case ASC_WARN_AUTO_CONFIG
:
11751 shost_printk(KERN_WARNING
, shost
, "I/O port increment switch "
11754 case ASC_WARN_EEPROM_CHKSUM
:
11755 shost_printk(KERN_WARNING
, shost
, "EEPROM checksum error\n");
11757 case ASC_WARN_IRQ_MODIFIED
:
11758 shost_printk(KERN_WARNING
, shost
, "IRQ modified\n");
11760 case ASC_WARN_CMD_QNG_CONFLICT
:
11761 shost_printk(KERN_WARNING
, shost
, "tag queuing enabled w/o "
11765 shost_printk(KERN_WARNING
, shost
, "unknown warning: 0x%x\n",
11770 if (asc_dvc
->err_code
!= 0)
11771 shost_printk(KERN_ERR
, shost
, "error 0x%x at init_state "
11772 "0x%x\n", asc_dvc
->err_code
, asc_dvc
->init_state
);
11774 return asc_dvc
->err_code
;
11777 static int __devinit
AscInitSetConfig(struct pci_dev
*pdev
, struct Scsi_Host
*shost
)
11779 struct asc_board
*board
= shost_priv(shost
);
11780 ASC_DVC_VAR
*asc_dvc
= &board
->dvc_var
.asc_dvc_var
;
11781 PortAddr iop_base
= asc_dvc
->iop_base
;
11782 unsigned short cfg_msw
;
11783 unsigned short warn_code
= 0;
11785 asc_dvc
->init_state
|= ASC_INIT_STATE_BEG_SET_CFG
;
11786 if (asc_dvc
->err_code
!= 0)
11787 return asc_dvc
->err_code
;
11788 if (!AscFindSignature(asc_dvc
->iop_base
)) {
11789 asc_dvc
->err_code
= ASC_IERR_BAD_SIGNATURE
;
11790 return asc_dvc
->err_code
;
11793 cfg_msw
= AscGetChipCfgMsw(iop_base
);
11794 if ((cfg_msw
& ASC_CFG_MSW_CLR_MASK
) != 0) {
11795 cfg_msw
&= ~ASC_CFG_MSW_CLR_MASK
;
11796 warn_code
|= ASC_WARN_CFG_MSW_RECOVER
;
11797 AscSetChipCfgMsw(iop_base
, cfg_msw
);
11799 if ((asc_dvc
->cfg
->cmd_qng_enabled
& asc_dvc
->cfg
->disc_enable
) !=
11800 asc_dvc
->cfg
->cmd_qng_enabled
) {
11801 asc_dvc
->cfg
->disc_enable
= asc_dvc
->cfg
->cmd_qng_enabled
;
11802 warn_code
|= ASC_WARN_CMD_QNG_CONFLICT
;
11804 if (AscGetChipStatus(iop_base
) & CSW_AUTO_CONFIG
) {
11805 warn_code
|= ASC_WARN_AUTO_CONFIG
;
11808 if (asc_dvc
->bus_type
& ASC_IS_PCI
) {
11810 AscSetChipCfgMsw(iop_base
, cfg_msw
);
11811 if ((asc_dvc
->bus_type
& ASC_IS_PCI_ULTRA
) == ASC_IS_PCI_ULTRA
) {
11813 if ((pdev
->device
== PCI_DEVICE_ID_ASP_1200A
) ||
11814 (pdev
->device
== PCI_DEVICE_ID_ASP_ABP940
)) {
11815 asc_dvc
->bug_fix_cntl
|= ASC_BUG_FIX_IF_NOT_DWB
;
11816 asc_dvc
->bug_fix_cntl
|=
11817 ASC_BUG_FIX_ASYN_USE_SYN
;
11821 #endif /* CONFIG_PCI */
11822 if (asc_dvc
->bus_type
== ASC_IS_ISAPNP
) {
11823 if (AscGetChipVersion(iop_base
, asc_dvc
->bus_type
)
11824 == ASC_CHIP_VER_ASYN_BUG
) {
11825 asc_dvc
->bug_fix_cntl
|= ASC_BUG_FIX_ASYN_USE_SYN
;
11828 if (AscSetChipScsiID(iop_base
, asc_dvc
->cfg
->chip_scsi_id
) !=
11829 asc_dvc
->cfg
->chip_scsi_id
) {
11830 asc_dvc
->err_code
|= ASC_IERR_SET_SCSI_ID
;
11833 if (asc_dvc
->bus_type
& ASC_IS_ISA
) {
11834 AscSetIsaDmaChannel(iop_base
, asc_dvc
->cfg
->isa_dma_channel
);
11835 AscSetIsaDmaSpeed(iop_base
, asc_dvc
->cfg
->isa_dma_speed
);
11837 #endif /* CONFIG_ISA */
11839 asc_dvc
->init_state
|= ASC_INIT_STATE_END_SET_CFG
;
11841 switch (warn_code
) {
11842 case 0: /* No error. */
11844 case ASC_WARN_IO_PORT_ROTATE
:
11845 shost_printk(KERN_WARNING
, shost
, "I/O port address "
11848 case ASC_WARN_AUTO_CONFIG
:
11849 shost_printk(KERN_WARNING
, shost
, "I/O port increment switch "
11852 case ASC_WARN_EEPROM_CHKSUM
:
11853 shost_printk(KERN_WARNING
, shost
, "EEPROM checksum error\n");
11855 case ASC_WARN_IRQ_MODIFIED
:
11856 shost_printk(KERN_WARNING
, shost
, "IRQ modified\n");
11858 case ASC_WARN_CMD_QNG_CONFLICT
:
11859 shost_printk(KERN_WARNING
, shost
, "tag queuing w/o "
11863 shost_printk(KERN_WARNING
, shost
, "unknown warning: 0x%x\n",
11868 if (asc_dvc
->err_code
!= 0)
11869 shost_printk(KERN_ERR
, shost
, "error 0x%x at init_state "
11870 "0x%x\n", asc_dvc
->err_code
, asc_dvc
->init_state
);
11872 return asc_dvc
->err_code
;
11876 * EEPROM Configuration.
11878 * All drivers should use this structure to set the default EEPROM
11879 * configuration. The BIOS now uses this structure when it is built.
11880 * Additional structure information can be found in a_condor.h where
11881 * the structure is defined.
11883 * The *_Field_IsChar structs are needed to correct for endianness.
11884 * These values are read from the board 16 bits at a time directly
11885 * into the structs. Because some fields are char, the values will be
11886 * in the wrong order. The *_Field_IsChar tells when to flip the
11887 * bytes. Data read and written to PCI memory is automatically swapped
11888 * on big-endian platforms so char fields read as words are actually being
11889 * unswapped on big-endian platforms.
11891 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config __devinitdata
= {
11892 ADV_EEPROM_BIOS_ENABLE
, /* cfg_lsw */
11893 0x0000, /* cfg_msw */
11894 0xFFFF, /* disc_enable */
11895 0xFFFF, /* wdtr_able */
11896 0xFFFF, /* sdtr_able */
11897 0xFFFF, /* start_motor */
11898 0xFFFF, /* tagqng_able */
11899 0xFFFF, /* bios_scan */
11900 0, /* scam_tolerant */
11901 7, /* adapter_scsi_id */
11902 0, /* bios_boot_delay */
11903 3, /* scsi_reset_delay */
11904 0, /* bios_id_lun */
11905 0, /* termination */
11907 0xFFE7, /* bios_ctrl */
11908 0xFFFF, /* ultra_able */
11910 ASC_DEF_MAX_HOST_QNG
, /* max_host_qng */
11911 ASC_DEF_MAX_DVC_QNG
, /* max_dvc_qng */
11914 0, /* serial_number_word1 */
11915 0, /* serial_number_word2 */
11916 0, /* serial_number_word3 */
11918 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
11919 , /* oem_name[16] */
11920 0, /* dvc_err_code */
11921 0, /* adv_err_code */
11922 0, /* adv_err_addr */
11923 0, /* saved_dvc_err_code */
11924 0, /* saved_adv_err_code */
11925 0, /* saved_adv_err_addr */
11929 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar __devinitdata
= {
11932 0, /* -disc_enable */
11935 0, /* start_motor */
11936 0, /* tagqng_able */
11938 0, /* scam_tolerant */
11939 1, /* adapter_scsi_id */
11940 1, /* bios_boot_delay */
11941 1, /* scsi_reset_delay */
11942 1, /* bios_id_lun */
11943 1, /* termination */
11946 0, /* ultra_able */
11948 1, /* max_host_qng */
11949 1, /* max_dvc_qng */
11952 0, /* serial_number_word1 */
11953 0, /* serial_number_word2 */
11954 0, /* serial_number_word3 */
11956 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
11957 , /* oem_name[16] */
11958 0, /* dvc_err_code */
11959 0, /* adv_err_code */
11960 0, /* adv_err_addr */
11961 0, /* saved_dvc_err_code */
11962 0, /* saved_adv_err_code */
11963 0, /* saved_adv_err_addr */
11967 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config __devinitdata
= {
11968 ADV_EEPROM_BIOS_ENABLE
, /* 00 cfg_lsw */
11969 0x0000, /* 01 cfg_msw */
11970 0xFFFF, /* 02 disc_enable */
11971 0xFFFF, /* 03 wdtr_able */
11972 0x4444, /* 04 sdtr_speed1 */
11973 0xFFFF, /* 05 start_motor */
11974 0xFFFF, /* 06 tagqng_able */
11975 0xFFFF, /* 07 bios_scan */
11976 0, /* 08 scam_tolerant */
11977 7, /* 09 adapter_scsi_id */
11978 0, /* bios_boot_delay */
11979 3, /* 10 scsi_reset_delay */
11980 0, /* bios_id_lun */
11981 0, /* 11 termination_se */
11982 0, /* termination_lvd */
11983 0xFFE7, /* 12 bios_ctrl */
11984 0x4444, /* 13 sdtr_speed2 */
11985 0x4444, /* 14 sdtr_speed3 */
11986 ASC_DEF_MAX_HOST_QNG
, /* 15 max_host_qng */
11987 ASC_DEF_MAX_DVC_QNG
, /* max_dvc_qng */
11988 0, /* 16 dvc_cntl */
11989 0x4444, /* 17 sdtr_speed4 */
11990 0, /* 18 serial_number_word1 */
11991 0, /* 19 serial_number_word2 */
11992 0, /* 20 serial_number_word3 */
11993 0, /* 21 check_sum */
11994 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
11995 , /* 22-29 oem_name[16] */
11996 0, /* 30 dvc_err_code */
11997 0, /* 31 adv_err_code */
11998 0, /* 32 adv_err_addr */
11999 0, /* 33 saved_dvc_err_code */
12000 0, /* 34 saved_adv_err_code */
12001 0, /* 35 saved_adv_err_addr */
12002 0, /* 36 reserved */
12003 0, /* 37 reserved */
12004 0, /* 38 reserved */
12005 0, /* 39 reserved */
12006 0, /* 40 reserved */
12007 0, /* 41 reserved */
12008 0, /* 42 reserved */
12009 0, /* 43 reserved */
12010 0, /* 44 reserved */
12011 0, /* 45 reserved */
12012 0, /* 46 reserved */
12013 0, /* 47 reserved */
12014 0, /* 48 reserved */
12015 0, /* 49 reserved */
12016 0, /* 50 reserved */
12017 0, /* 51 reserved */
12018 0, /* 52 reserved */
12019 0, /* 53 reserved */
12020 0, /* 54 reserved */
12021 0, /* 55 reserved */
12022 0, /* 56 cisptr_lsw */
12023 0, /* 57 cisprt_msw */
12024 PCI_VENDOR_ID_ASP
, /* 58 subsysvid */
12025 PCI_DEVICE_ID_38C0800_REV1
, /* 59 subsysid */
12026 0, /* 60 reserved */
12027 0, /* 61 reserved */
12028 0, /* 62 reserved */
12029 0 /* 63 reserved */
12032 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar __devinitdata
= {
12033 0, /* 00 cfg_lsw */
12034 0, /* 01 cfg_msw */
12035 0, /* 02 disc_enable */
12036 0, /* 03 wdtr_able */
12037 0, /* 04 sdtr_speed1 */
12038 0, /* 05 start_motor */
12039 0, /* 06 tagqng_able */
12040 0, /* 07 bios_scan */
12041 0, /* 08 scam_tolerant */
12042 1, /* 09 adapter_scsi_id */
12043 1, /* bios_boot_delay */
12044 1, /* 10 scsi_reset_delay */
12045 1, /* bios_id_lun */
12046 1, /* 11 termination_se */
12047 1, /* termination_lvd */
12048 0, /* 12 bios_ctrl */
12049 0, /* 13 sdtr_speed2 */
12050 0, /* 14 sdtr_speed3 */
12051 1, /* 15 max_host_qng */
12052 1, /* max_dvc_qng */
12053 0, /* 16 dvc_cntl */
12054 0, /* 17 sdtr_speed4 */
12055 0, /* 18 serial_number_word1 */
12056 0, /* 19 serial_number_word2 */
12057 0, /* 20 serial_number_word3 */
12058 0, /* 21 check_sum */
12059 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12060 , /* 22-29 oem_name[16] */
12061 0, /* 30 dvc_err_code */
12062 0, /* 31 adv_err_code */
12063 0, /* 32 adv_err_addr */
12064 0, /* 33 saved_dvc_err_code */
12065 0, /* 34 saved_adv_err_code */
12066 0, /* 35 saved_adv_err_addr */
12067 0, /* 36 reserved */
12068 0, /* 37 reserved */
12069 0, /* 38 reserved */
12070 0, /* 39 reserved */
12071 0, /* 40 reserved */
12072 0, /* 41 reserved */
12073 0, /* 42 reserved */
12074 0, /* 43 reserved */
12075 0, /* 44 reserved */
12076 0, /* 45 reserved */
12077 0, /* 46 reserved */
12078 0, /* 47 reserved */
12079 0, /* 48 reserved */
12080 0, /* 49 reserved */
12081 0, /* 50 reserved */
12082 0, /* 51 reserved */
12083 0, /* 52 reserved */
12084 0, /* 53 reserved */
12085 0, /* 54 reserved */
12086 0, /* 55 reserved */
12087 0, /* 56 cisptr_lsw */
12088 0, /* 57 cisprt_msw */
12089 0, /* 58 subsysvid */
12090 0, /* 59 subsysid */
12091 0, /* 60 reserved */
12092 0, /* 61 reserved */
12093 0, /* 62 reserved */
12094 0 /* 63 reserved */
12097 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config __devinitdata
= {
12098 ADV_EEPROM_BIOS_ENABLE
, /* 00 cfg_lsw */
12099 0x0000, /* 01 cfg_msw */
12100 0xFFFF, /* 02 disc_enable */
12101 0xFFFF, /* 03 wdtr_able */
12102 0x5555, /* 04 sdtr_speed1 */
12103 0xFFFF, /* 05 start_motor */
12104 0xFFFF, /* 06 tagqng_able */
12105 0xFFFF, /* 07 bios_scan */
12106 0, /* 08 scam_tolerant */
12107 7, /* 09 adapter_scsi_id */
12108 0, /* bios_boot_delay */
12109 3, /* 10 scsi_reset_delay */
12110 0, /* bios_id_lun */
12111 0, /* 11 termination_se */
12112 0, /* termination_lvd */
12113 0xFFE7, /* 12 bios_ctrl */
12114 0x5555, /* 13 sdtr_speed2 */
12115 0x5555, /* 14 sdtr_speed3 */
12116 ASC_DEF_MAX_HOST_QNG
, /* 15 max_host_qng */
12117 ASC_DEF_MAX_DVC_QNG
, /* max_dvc_qng */
12118 0, /* 16 dvc_cntl */
12119 0x5555, /* 17 sdtr_speed4 */
12120 0, /* 18 serial_number_word1 */
12121 0, /* 19 serial_number_word2 */
12122 0, /* 20 serial_number_word3 */
12123 0, /* 21 check_sum */
12124 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12125 , /* 22-29 oem_name[16] */
12126 0, /* 30 dvc_err_code */
12127 0, /* 31 adv_err_code */
12128 0, /* 32 adv_err_addr */
12129 0, /* 33 saved_dvc_err_code */
12130 0, /* 34 saved_adv_err_code */
12131 0, /* 35 saved_adv_err_addr */
12132 0, /* 36 reserved */
12133 0, /* 37 reserved */
12134 0, /* 38 reserved */
12135 0, /* 39 reserved */
12136 0, /* 40 reserved */
12137 0, /* 41 reserved */
12138 0, /* 42 reserved */
12139 0, /* 43 reserved */
12140 0, /* 44 reserved */
12141 0, /* 45 reserved */
12142 0, /* 46 reserved */
12143 0, /* 47 reserved */
12144 0, /* 48 reserved */
12145 0, /* 49 reserved */
12146 0, /* 50 reserved */
12147 0, /* 51 reserved */
12148 0, /* 52 reserved */
12149 0, /* 53 reserved */
12150 0, /* 54 reserved */
12151 0, /* 55 reserved */
12152 0, /* 56 cisptr_lsw */
12153 0, /* 57 cisprt_msw */
12154 PCI_VENDOR_ID_ASP
, /* 58 subsysvid */
12155 PCI_DEVICE_ID_38C1600_REV1
, /* 59 subsysid */
12156 0, /* 60 reserved */
12157 0, /* 61 reserved */
12158 0, /* 62 reserved */
12159 0 /* 63 reserved */
12162 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar __devinitdata
= {
12163 0, /* 00 cfg_lsw */
12164 0, /* 01 cfg_msw */
12165 0, /* 02 disc_enable */
12166 0, /* 03 wdtr_able */
12167 0, /* 04 sdtr_speed1 */
12168 0, /* 05 start_motor */
12169 0, /* 06 tagqng_able */
12170 0, /* 07 bios_scan */
12171 0, /* 08 scam_tolerant */
12172 1, /* 09 adapter_scsi_id */
12173 1, /* bios_boot_delay */
12174 1, /* 10 scsi_reset_delay */
12175 1, /* bios_id_lun */
12176 1, /* 11 termination_se */
12177 1, /* termination_lvd */
12178 0, /* 12 bios_ctrl */
12179 0, /* 13 sdtr_speed2 */
12180 0, /* 14 sdtr_speed3 */
12181 1, /* 15 max_host_qng */
12182 1, /* max_dvc_qng */
12183 0, /* 16 dvc_cntl */
12184 0, /* 17 sdtr_speed4 */
12185 0, /* 18 serial_number_word1 */
12186 0, /* 19 serial_number_word2 */
12187 0, /* 20 serial_number_word3 */
12188 0, /* 21 check_sum */
12189 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12190 , /* 22-29 oem_name[16] */
12191 0, /* 30 dvc_err_code */
12192 0, /* 31 adv_err_code */
12193 0, /* 32 adv_err_addr */
12194 0, /* 33 saved_dvc_err_code */
12195 0, /* 34 saved_adv_err_code */
12196 0, /* 35 saved_adv_err_addr */
12197 0, /* 36 reserved */
12198 0, /* 37 reserved */
12199 0, /* 38 reserved */
12200 0, /* 39 reserved */
12201 0, /* 40 reserved */
12202 0, /* 41 reserved */
12203 0, /* 42 reserved */
12204 0, /* 43 reserved */
12205 0, /* 44 reserved */
12206 0, /* 45 reserved */
12207 0, /* 46 reserved */
12208 0, /* 47 reserved */
12209 0, /* 48 reserved */
12210 0, /* 49 reserved */
12211 0, /* 50 reserved */
12212 0, /* 51 reserved */
12213 0, /* 52 reserved */
12214 0, /* 53 reserved */
12215 0, /* 54 reserved */
12216 0, /* 55 reserved */
12217 0, /* 56 cisptr_lsw */
12218 0, /* 57 cisprt_msw */
12219 0, /* 58 subsysvid */
12220 0, /* 59 subsysid */
12221 0, /* 60 reserved */
12222 0, /* 61 reserved */
12223 0, /* 62 reserved */
12224 0 /* 63 reserved */
12229 * Wait for EEPROM command to complete
12231 static void __devinit
AdvWaitEEPCmd(AdvPortAddr iop_base
)
12235 for (eep_delay_ms
= 0; eep_delay_ms
< ADV_EEP_DELAY_MS
; eep_delay_ms
++) {
12236 if (AdvReadWordRegister(iop_base
, IOPW_EE_CMD
) &
12237 ASC_EEP_CMD_DONE
) {
12242 if ((AdvReadWordRegister(iop_base
, IOPW_EE_CMD
) & ASC_EEP_CMD_DONE
) ==
12248 * Read the EEPROM from specified location
12250 static ushort __devinit
AdvReadEEPWord(AdvPortAddr iop_base
, int eep_word_addr
)
12252 AdvWriteWordRegister(iop_base
, IOPW_EE_CMD
,
12253 ASC_EEP_CMD_READ
| eep_word_addr
);
12254 AdvWaitEEPCmd(iop_base
);
12255 return AdvReadWordRegister(iop_base
, IOPW_EE_DATA
);
12259 * Write the EEPROM from 'cfg_buf'.
12262 AdvSet3550EEPConfig(AdvPortAddr iop_base
, ADVEEP_3550_CONFIG
*cfg_buf
)
12265 ushort addr
, chksum
;
12266 ushort
*charfields
;
12268 wbuf
= (ushort
*)cfg_buf
;
12269 charfields
= (ushort
*)&ADVEEP_3550_Config_Field_IsChar
;
12272 AdvWriteWordRegister(iop_base
, IOPW_EE_CMD
, ASC_EEP_CMD_WRITE_ABLE
);
12273 AdvWaitEEPCmd(iop_base
);
12276 * Write EEPROM from word 0 to word 20.
12278 for (addr
= ADV_EEP_DVC_CFG_BEGIN
;
12279 addr
< ADV_EEP_DVC_CFG_END
; addr
++, wbuf
++) {
12282 if (*charfields
++) {
12283 word
= cpu_to_le16(*wbuf
);
12287 chksum
+= *wbuf
; /* Checksum is calculated from word values. */
12288 AdvWriteWordRegister(iop_base
, IOPW_EE_DATA
, word
);
12289 AdvWriteWordRegister(iop_base
, IOPW_EE_CMD
,
12290 ASC_EEP_CMD_WRITE
| addr
);
12291 AdvWaitEEPCmd(iop_base
);
12292 mdelay(ADV_EEP_DELAY_MS
);
12296 * Write EEPROM checksum at word 21.
12298 AdvWriteWordRegister(iop_base
, IOPW_EE_DATA
, chksum
);
12299 AdvWriteWordRegister(iop_base
, IOPW_EE_CMD
, ASC_EEP_CMD_WRITE
| addr
);
12300 AdvWaitEEPCmd(iop_base
);
12305 * Write EEPROM OEM name at words 22 to 29.
12307 for (addr
= ADV_EEP_DVC_CTL_BEGIN
;
12308 addr
< ADV_EEP_MAX_WORD_ADDR
; addr
++, wbuf
++) {
12311 if (*charfields
++) {
12312 word
= cpu_to_le16(*wbuf
);
12316 AdvWriteWordRegister(iop_base
, IOPW_EE_DATA
, word
);
12317 AdvWriteWordRegister(iop_base
, IOPW_EE_CMD
,
12318 ASC_EEP_CMD_WRITE
| addr
);
12319 AdvWaitEEPCmd(iop_base
);
12321 AdvWriteWordRegister(iop_base
, IOPW_EE_CMD
, ASC_EEP_CMD_WRITE_DISABLE
);
12322 AdvWaitEEPCmd(iop_base
);
12326 * Write the EEPROM from 'cfg_buf'.
12329 AdvSet38C0800EEPConfig(AdvPortAddr iop_base
, ADVEEP_38C0800_CONFIG
*cfg_buf
)
12332 ushort
*charfields
;
12333 ushort addr
, chksum
;
12335 wbuf
= (ushort
*)cfg_buf
;
12336 charfields
= (ushort
*)&ADVEEP_38C0800_Config_Field_IsChar
;
12339 AdvWriteWordRegister(iop_base
, IOPW_EE_CMD
, ASC_EEP_CMD_WRITE_ABLE
);
12340 AdvWaitEEPCmd(iop_base
);
12343 * Write EEPROM from word 0 to word 20.
12345 for (addr
= ADV_EEP_DVC_CFG_BEGIN
;
12346 addr
< ADV_EEP_DVC_CFG_END
; addr
++, wbuf
++) {
12349 if (*charfields
++) {
12350 word
= cpu_to_le16(*wbuf
);
12354 chksum
+= *wbuf
; /* Checksum is calculated from word values. */
12355 AdvWriteWordRegister(iop_base
, IOPW_EE_DATA
, word
);
12356 AdvWriteWordRegister(iop_base
, IOPW_EE_CMD
,
12357 ASC_EEP_CMD_WRITE
| addr
);
12358 AdvWaitEEPCmd(iop_base
);
12359 mdelay(ADV_EEP_DELAY_MS
);
12363 * Write EEPROM checksum at word 21.
12365 AdvWriteWordRegister(iop_base
, IOPW_EE_DATA
, chksum
);
12366 AdvWriteWordRegister(iop_base
, IOPW_EE_CMD
, ASC_EEP_CMD_WRITE
| addr
);
12367 AdvWaitEEPCmd(iop_base
);
12372 * Write EEPROM OEM name at words 22 to 29.
12374 for (addr
= ADV_EEP_DVC_CTL_BEGIN
;
12375 addr
< ADV_EEP_MAX_WORD_ADDR
; addr
++, wbuf
++) {
12378 if (*charfields
++) {
12379 word
= cpu_to_le16(*wbuf
);
12383 AdvWriteWordRegister(iop_base
, IOPW_EE_DATA
, word
);
12384 AdvWriteWordRegister(iop_base
, IOPW_EE_CMD
,
12385 ASC_EEP_CMD_WRITE
| addr
);
12386 AdvWaitEEPCmd(iop_base
);
12388 AdvWriteWordRegister(iop_base
, IOPW_EE_CMD
, ASC_EEP_CMD_WRITE_DISABLE
);
12389 AdvWaitEEPCmd(iop_base
);
12393 * Write the EEPROM from 'cfg_buf'.
12396 AdvSet38C1600EEPConfig(AdvPortAddr iop_base
, ADVEEP_38C1600_CONFIG
*cfg_buf
)
12399 ushort
*charfields
;
12400 ushort addr
, chksum
;
12402 wbuf
= (ushort
*)cfg_buf
;
12403 charfields
= (ushort
*)&ADVEEP_38C1600_Config_Field_IsChar
;
12406 AdvWriteWordRegister(iop_base
, IOPW_EE_CMD
, ASC_EEP_CMD_WRITE_ABLE
);
12407 AdvWaitEEPCmd(iop_base
);
12410 * Write EEPROM from word 0 to word 20.
12412 for (addr
= ADV_EEP_DVC_CFG_BEGIN
;
12413 addr
< ADV_EEP_DVC_CFG_END
; addr
++, wbuf
++) {
12416 if (*charfields
++) {
12417 word
= cpu_to_le16(*wbuf
);
12421 chksum
+= *wbuf
; /* Checksum is calculated from word values. */
12422 AdvWriteWordRegister(iop_base
, IOPW_EE_DATA
, word
);
12423 AdvWriteWordRegister(iop_base
, IOPW_EE_CMD
,
12424 ASC_EEP_CMD_WRITE
| addr
);
12425 AdvWaitEEPCmd(iop_base
);
12426 mdelay(ADV_EEP_DELAY_MS
);
12430 * Write EEPROM checksum at word 21.
12432 AdvWriteWordRegister(iop_base
, IOPW_EE_DATA
, chksum
);
12433 AdvWriteWordRegister(iop_base
, IOPW_EE_CMD
, ASC_EEP_CMD_WRITE
| addr
);
12434 AdvWaitEEPCmd(iop_base
);
12439 * Write EEPROM OEM name at words 22 to 29.
12441 for (addr
= ADV_EEP_DVC_CTL_BEGIN
;
12442 addr
< ADV_EEP_MAX_WORD_ADDR
; addr
++, wbuf
++) {
12445 if (*charfields
++) {
12446 word
= cpu_to_le16(*wbuf
);
12450 AdvWriteWordRegister(iop_base
, IOPW_EE_DATA
, word
);
12451 AdvWriteWordRegister(iop_base
, IOPW_EE_CMD
,
12452 ASC_EEP_CMD_WRITE
| addr
);
12453 AdvWaitEEPCmd(iop_base
);
12455 AdvWriteWordRegister(iop_base
, IOPW_EE_CMD
, ASC_EEP_CMD_WRITE_DISABLE
);
12456 AdvWaitEEPCmd(iop_base
);
12460 * Read EEPROM configuration into the specified buffer.
12462 * Return a checksum based on the EEPROM configuration read.
12464 static ushort __devinit
12465 AdvGet3550EEPConfig(AdvPortAddr iop_base
, ADVEEP_3550_CONFIG
*cfg_buf
)
12467 ushort wval
, chksum
;
12470 ushort
*charfields
;
12472 charfields
= (ushort
*)&ADVEEP_3550_Config_Field_IsChar
;
12473 wbuf
= (ushort
*)cfg_buf
;
12476 for (eep_addr
= ADV_EEP_DVC_CFG_BEGIN
;
12477 eep_addr
< ADV_EEP_DVC_CFG_END
; eep_addr
++, wbuf
++) {
12478 wval
= AdvReadEEPWord(iop_base
, eep_addr
);
12479 chksum
+= wval
; /* Checksum is calculated from word values. */
12480 if (*charfields
++) {
12481 *wbuf
= le16_to_cpu(wval
);
12486 /* Read checksum word. */
12487 *wbuf
= AdvReadEEPWord(iop_base
, eep_addr
);
12491 /* Read rest of EEPROM not covered by the checksum. */
12492 for (eep_addr
= ADV_EEP_DVC_CTL_BEGIN
;
12493 eep_addr
< ADV_EEP_MAX_WORD_ADDR
; eep_addr
++, wbuf
++) {
12494 *wbuf
= AdvReadEEPWord(iop_base
, eep_addr
);
12495 if (*charfields
++) {
12496 *wbuf
= le16_to_cpu(*wbuf
);
12503 * Read EEPROM configuration into the specified buffer.
12505 * Return a checksum based on the EEPROM configuration read.
12507 static ushort __devinit
12508 AdvGet38C0800EEPConfig(AdvPortAddr iop_base
, ADVEEP_38C0800_CONFIG
*cfg_buf
)
12510 ushort wval
, chksum
;
12513 ushort
*charfields
;
12515 charfields
= (ushort
*)&ADVEEP_38C0800_Config_Field_IsChar
;
12516 wbuf
= (ushort
*)cfg_buf
;
12519 for (eep_addr
= ADV_EEP_DVC_CFG_BEGIN
;
12520 eep_addr
< ADV_EEP_DVC_CFG_END
; eep_addr
++, wbuf
++) {
12521 wval
= AdvReadEEPWord(iop_base
, eep_addr
);
12522 chksum
+= wval
; /* Checksum is calculated from word values. */
12523 if (*charfields
++) {
12524 *wbuf
= le16_to_cpu(wval
);
12529 /* Read checksum word. */
12530 *wbuf
= AdvReadEEPWord(iop_base
, eep_addr
);
12534 /* Read rest of EEPROM not covered by the checksum. */
12535 for (eep_addr
= ADV_EEP_DVC_CTL_BEGIN
;
12536 eep_addr
< ADV_EEP_MAX_WORD_ADDR
; eep_addr
++, wbuf
++) {
12537 *wbuf
= AdvReadEEPWord(iop_base
, eep_addr
);
12538 if (*charfields
++) {
12539 *wbuf
= le16_to_cpu(*wbuf
);
12546 * Read EEPROM configuration into the specified buffer.
12548 * Return a checksum based on the EEPROM configuration read.
12550 static ushort __devinit
12551 AdvGet38C1600EEPConfig(AdvPortAddr iop_base
, ADVEEP_38C1600_CONFIG
*cfg_buf
)
12553 ushort wval
, chksum
;
12556 ushort
*charfields
;
12558 charfields
= (ushort
*)&ADVEEP_38C1600_Config_Field_IsChar
;
12559 wbuf
= (ushort
*)cfg_buf
;
12562 for (eep_addr
= ADV_EEP_DVC_CFG_BEGIN
;
12563 eep_addr
< ADV_EEP_DVC_CFG_END
; eep_addr
++, wbuf
++) {
12564 wval
= AdvReadEEPWord(iop_base
, eep_addr
);
12565 chksum
+= wval
; /* Checksum is calculated from word values. */
12566 if (*charfields
++) {
12567 *wbuf
= le16_to_cpu(wval
);
12572 /* Read checksum word. */
12573 *wbuf
= AdvReadEEPWord(iop_base
, eep_addr
);
12577 /* Read rest of EEPROM not covered by the checksum. */
12578 for (eep_addr
= ADV_EEP_DVC_CTL_BEGIN
;
12579 eep_addr
< ADV_EEP_MAX_WORD_ADDR
; eep_addr
++, wbuf
++) {
12580 *wbuf
= AdvReadEEPWord(iop_base
, eep_addr
);
12581 if (*charfields
++) {
12582 *wbuf
= le16_to_cpu(*wbuf
);
12589 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
12590 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
12591 * all of this is done.
12593 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
12595 * For a non-fatal error return a warning code. If there are no warnings
12596 * then 0 is returned.
12598 * Note: Chip is stopped on entry.
12600 static int __devinit
AdvInitFrom3550EEP(ADV_DVC_VAR
*asc_dvc
)
12602 AdvPortAddr iop_base
;
12604 ADVEEP_3550_CONFIG eep_config
;
12606 iop_base
= asc_dvc
->iop_base
;
12611 * Read the board's EEPROM configuration.
12613 * Set default values if a bad checksum is found.
12615 if (AdvGet3550EEPConfig(iop_base
, &eep_config
) != eep_config
.check_sum
) {
12616 warn_code
|= ASC_WARN_EEPROM_CHKSUM
;
12619 * Set EEPROM default values.
12621 memcpy(&eep_config
, &Default_3550_EEPROM_Config
,
12622 sizeof(ADVEEP_3550_CONFIG
));
12625 * Assume the 6 byte board serial number that was read from
12626 * EEPROM is correct even if the EEPROM checksum failed.
12628 eep_config
.serial_number_word3
=
12629 AdvReadEEPWord(iop_base
, ADV_EEP_DVC_CFG_END
- 1);
12631 eep_config
.serial_number_word2
=
12632 AdvReadEEPWord(iop_base
, ADV_EEP_DVC_CFG_END
- 2);
12634 eep_config
.serial_number_word1
=
12635 AdvReadEEPWord(iop_base
, ADV_EEP_DVC_CFG_END
- 3);
12637 AdvSet3550EEPConfig(iop_base
, &eep_config
);
12640 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
12641 * EEPROM configuration that was read.
12643 * This is the mapping of EEPROM fields to Adv Library fields.
12645 asc_dvc
->wdtr_able
= eep_config
.wdtr_able
;
12646 asc_dvc
->sdtr_able
= eep_config
.sdtr_able
;
12647 asc_dvc
->ultra_able
= eep_config
.ultra_able
;
12648 asc_dvc
->tagqng_able
= eep_config
.tagqng_able
;
12649 asc_dvc
->cfg
->disc_enable
= eep_config
.disc_enable
;
12650 asc_dvc
->max_host_qng
= eep_config
.max_host_qng
;
12651 asc_dvc
->max_dvc_qng
= eep_config
.max_dvc_qng
;
12652 asc_dvc
->chip_scsi_id
= (eep_config
.adapter_scsi_id
& ADV_MAX_TID
);
12653 asc_dvc
->start_motor
= eep_config
.start_motor
;
12654 asc_dvc
->scsi_reset_wait
= eep_config
.scsi_reset_delay
;
12655 asc_dvc
->bios_ctrl
= eep_config
.bios_ctrl
;
12656 asc_dvc
->no_scam
= eep_config
.scam_tolerant
;
12657 asc_dvc
->cfg
->serial1
= eep_config
.serial_number_word1
;
12658 asc_dvc
->cfg
->serial2
= eep_config
.serial_number_word2
;
12659 asc_dvc
->cfg
->serial3
= eep_config
.serial_number_word3
;
12662 * Set the host maximum queuing (max. 253, min. 16) and the per device
12663 * maximum queuing (max. 63, min. 4).
12665 if (eep_config
.max_host_qng
> ASC_DEF_MAX_HOST_QNG
) {
12666 eep_config
.max_host_qng
= ASC_DEF_MAX_HOST_QNG
;
12667 } else if (eep_config
.max_host_qng
< ASC_DEF_MIN_HOST_QNG
) {
12668 /* If the value is zero, assume it is uninitialized. */
12669 if (eep_config
.max_host_qng
== 0) {
12670 eep_config
.max_host_qng
= ASC_DEF_MAX_HOST_QNG
;
12672 eep_config
.max_host_qng
= ASC_DEF_MIN_HOST_QNG
;
12676 if (eep_config
.max_dvc_qng
> ASC_DEF_MAX_DVC_QNG
) {
12677 eep_config
.max_dvc_qng
= ASC_DEF_MAX_DVC_QNG
;
12678 } else if (eep_config
.max_dvc_qng
< ASC_DEF_MIN_DVC_QNG
) {
12679 /* If the value is zero, assume it is uninitialized. */
12680 if (eep_config
.max_dvc_qng
== 0) {
12681 eep_config
.max_dvc_qng
= ASC_DEF_MAX_DVC_QNG
;
12683 eep_config
.max_dvc_qng
= ASC_DEF_MIN_DVC_QNG
;
12688 * If 'max_dvc_qng' is greater than 'max_host_qng', then
12689 * set 'max_dvc_qng' to 'max_host_qng'.
12691 if (eep_config
.max_dvc_qng
> eep_config
.max_host_qng
) {
12692 eep_config
.max_dvc_qng
= eep_config
.max_host_qng
;
12696 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
12697 * values based on possibly adjusted EEPROM values.
12699 asc_dvc
->max_host_qng
= eep_config
.max_host_qng
;
12700 asc_dvc
->max_dvc_qng
= eep_config
.max_dvc_qng
;
12703 * If the EEPROM 'termination' field is set to automatic (0), then set
12704 * the ADV_DVC_CFG 'termination' field to automatic also.
12706 * If the termination is specified with a non-zero 'termination'
12707 * value check that a legal value is set and set the ADV_DVC_CFG
12708 * 'termination' field appropriately.
12710 if (eep_config
.termination
== 0) {
12711 asc_dvc
->cfg
->termination
= 0; /* auto termination */
12713 /* Enable manual control with low off / high off. */
12714 if (eep_config
.termination
== 1) {
12715 asc_dvc
->cfg
->termination
= TERM_CTL_SEL
;
12717 /* Enable manual control with low off / high on. */
12718 } else if (eep_config
.termination
== 2) {
12719 asc_dvc
->cfg
->termination
= TERM_CTL_SEL
| TERM_CTL_H
;
12721 /* Enable manual control with low on / high on. */
12722 } else if (eep_config
.termination
== 3) {
12723 asc_dvc
->cfg
->termination
=
12724 TERM_CTL_SEL
| TERM_CTL_H
| TERM_CTL_L
;
12727 * The EEPROM 'termination' field contains a bad value. Use
12728 * automatic termination instead.
12730 asc_dvc
->cfg
->termination
= 0;
12731 warn_code
|= ASC_WARN_EEPROM_TERMINATION
;
12739 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
12740 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
12741 * all of this is done.
12743 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
12745 * For a non-fatal error return a warning code. If there are no warnings
12746 * then 0 is returned.
12748 * Note: Chip is stopped on entry.
12750 static int __devinit
AdvInitFrom38C0800EEP(ADV_DVC_VAR
*asc_dvc
)
12752 AdvPortAddr iop_base
;
12754 ADVEEP_38C0800_CONFIG eep_config
;
12755 uchar tid
, termination
;
12756 ushort sdtr_speed
= 0;
12758 iop_base
= asc_dvc
->iop_base
;
12763 * Read the board's EEPROM configuration.
12765 * Set default values if a bad checksum is found.
12767 if (AdvGet38C0800EEPConfig(iop_base
, &eep_config
) !=
12768 eep_config
.check_sum
) {
12769 warn_code
|= ASC_WARN_EEPROM_CHKSUM
;
12772 * Set EEPROM default values.
12774 memcpy(&eep_config
, &Default_38C0800_EEPROM_Config
,
12775 sizeof(ADVEEP_38C0800_CONFIG
));
12778 * Assume the 6 byte board serial number that was read from
12779 * EEPROM is correct even if the EEPROM checksum failed.
12781 eep_config
.serial_number_word3
=
12782 AdvReadEEPWord(iop_base
, ADV_EEP_DVC_CFG_END
- 1);
12784 eep_config
.serial_number_word2
=
12785 AdvReadEEPWord(iop_base
, ADV_EEP_DVC_CFG_END
- 2);
12787 eep_config
.serial_number_word1
=
12788 AdvReadEEPWord(iop_base
, ADV_EEP_DVC_CFG_END
- 3);
12790 AdvSet38C0800EEPConfig(iop_base
, &eep_config
);
12793 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
12794 * EEPROM configuration that was read.
12796 * This is the mapping of EEPROM fields to Adv Library fields.
12798 asc_dvc
->wdtr_able
= eep_config
.wdtr_able
;
12799 asc_dvc
->sdtr_speed1
= eep_config
.sdtr_speed1
;
12800 asc_dvc
->sdtr_speed2
= eep_config
.sdtr_speed2
;
12801 asc_dvc
->sdtr_speed3
= eep_config
.sdtr_speed3
;
12802 asc_dvc
->sdtr_speed4
= eep_config
.sdtr_speed4
;
12803 asc_dvc
->tagqng_able
= eep_config
.tagqng_able
;
12804 asc_dvc
->cfg
->disc_enable
= eep_config
.disc_enable
;
12805 asc_dvc
->max_host_qng
= eep_config
.max_host_qng
;
12806 asc_dvc
->max_dvc_qng
= eep_config
.max_dvc_qng
;
12807 asc_dvc
->chip_scsi_id
= (eep_config
.adapter_scsi_id
& ADV_MAX_TID
);
12808 asc_dvc
->start_motor
= eep_config
.start_motor
;
12809 asc_dvc
->scsi_reset_wait
= eep_config
.scsi_reset_delay
;
12810 asc_dvc
->bios_ctrl
= eep_config
.bios_ctrl
;
12811 asc_dvc
->no_scam
= eep_config
.scam_tolerant
;
12812 asc_dvc
->cfg
->serial1
= eep_config
.serial_number_word1
;
12813 asc_dvc
->cfg
->serial2
= eep_config
.serial_number_word2
;
12814 asc_dvc
->cfg
->serial3
= eep_config
.serial_number_word3
;
12817 * For every Target ID if any of its 'sdtr_speed[1234]' bits
12818 * are set, then set an 'sdtr_able' bit for it.
12820 asc_dvc
->sdtr_able
= 0;
12821 for (tid
= 0; tid
<= ADV_MAX_TID
; tid
++) {
12823 sdtr_speed
= asc_dvc
->sdtr_speed1
;
12824 } else if (tid
== 4) {
12825 sdtr_speed
= asc_dvc
->sdtr_speed2
;
12826 } else if (tid
== 8) {
12827 sdtr_speed
= asc_dvc
->sdtr_speed3
;
12828 } else if (tid
== 12) {
12829 sdtr_speed
= asc_dvc
->sdtr_speed4
;
12831 if (sdtr_speed
& ADV_MAX_TID
) {
12832 asc_dvc
->sdtr_able
|= (1 << tid
);
12838 * Set the host maximum queuing (max. 253, min. 16) and the per device
12839 * maximum queuing (max. 63, min. 4).
12841 if (eep_config
.max_host_qng
> ASC_DEF_MAX_HOST_QNG
) {
12842 eep_config
.max_host_qng
= ASC_DEF_MAX_HOST_QNG
;
12843 } else if (eep_config
.max_host_qng
< ASC_DEF_MIN_HOST_QNG
) {
12844 /* If the value is zero, assume it is uninitialized. */
12845 if (eep_config
.max_host_qng
== 0) {
12846 eep_config
.max_host_qng
= ASC_DEF_MAX_HOST_QNG
;
12848 eep_config
.max_host_qng
= ASC_DEF_MIN_HOST_QNG
;
12852 if (eep_config
.max_dvc_qng
> ASC_DEF_MAX_DVC_QNG
) {
12853 eep_config
.max_dvc_qng
= ASC_DEF_MAX_DVC_QNG
;
12854 } else if (eep_config
.max_dvc_qng
< ASC_DEF_MIN_DVC_QNG
) {
12855 /* If the value is zero, assume it is uninitialized. */
12856 if (eep_config
.max_dvc_qng
== 0) {
12857 eep_config
.max_dvc_qng
= ASC_DEF_MAX_DVC_QNG
;
12859 eep_config
.max_dvc_qng
= ASC_DEF_MIN_DVC_QNG
;
12864 * If 'max_dvc_qng' is greater than 'max_host_qng', then
12865 * set 'max_dvc_qng' to 'max_host_qng'.
12867 if (eep_config
.max_dvc_qng
> eep_config
.max_host_qng
) {
12868 eep_config
.max_dvc_qng
= eep_config
.max_host_qng
;
12872 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
12873 * values based on possibly adjusted EEPROM values.
12875 asc_dvc
->max_host_qng
= eep_config
.max_host_qng
;
12876 asc_dvc
->max_dvc_qng
= eep_config
.max_dvc_qng
;
12879 * If the EEPROM 'termination' field is set to automatic (0), then set
12880 * the ADV_DVC_CFG 'termination' field to automatic also.
12882 * If the termination is specified with a non-zero 'termination'
12883 * value check that a legal value is set and set the ADV_DVC_CFG
12884 * 'termination' field appropriately.
12886 if (eep_config
.termination_se
== 0) {
12887 termination
= 0; /* auto termination for SE */
12889 /* Enable manual control with low off / high off. */
12890 if (eep_config
.termination_se
== 1) {
12893 /* Enable manual control with low off / high on. */
12894 } else if (eep_config
.termination_se
== 2) {
12895 termination
= TERM_SE_HI
;
12897 /* Enable manual control with low on / high on. */
12898 } else if (eep_config
.termination_se
== 3) {
12899 termination
= TERM_SE
;
12902 * The EEPROM 'termination_se' field contains a bad value.
12903 * Use automatic termination instead.
12906 warn_code
|= ASC_WARN_EEPROM_TERMINATION
;
12910 if (eep_config
.termination_lvd
== 0) {
12911 asc_dvc
->cfg
->termination
= termination
; /* auto termination for LVD */
12913 /* Enable manual control with low off / high off. */
12914 if (eep_config
.termination_lvd
== 1) {
12915 asc_dvc
->cfg
->termination
= termination
;
12917 /* Enable manual control with low off / high on. */
12918 } else if (eep_config
.termination_lvd
== 2) {
12919 asc_dvc
->cfg
->termination
= termination
| TERM_LVD_HI
;
12921 /* Enable manual control with low on / high on. */
12922 } else if (eep_config
.termination_lvd
== 3) {
12923 asc_dvc
->cfg
->termination
= termination
| TERM_LVD
;
12926 * The EEPROM 'termination_lvd' field contains a bad value.
12927 * Use automatic termination instead.
12929 asc_dvc
->cfg
->termination
= termination
;
12930 warn_code
|= ASC_WARN_EEPROM_TERMINATION
;
12938 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
12939 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
12940 * all of this is done.
12942 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
12944 * For a non-fatal error return a warning code. If there are no warnings
12945 * then 0 is returned.
12947 * Note: Chip is stopped on entry.
12949 static int __devinit
AdvInitFrom38C1600EEP(ADV_DVC_VAR
*asc_dvc
)
12951 AdvPortAddr iop_base
;
12953 ADVEEP_38C1600_CONFIG eep_config
;
12954 uchar tid
, termination
;
12955 ushort sdtr_speed
= 0;
12957 iop_base
= asc_dvc
->iop_base
;
12962 * Read the board's EEPROM configuration.
12964 * Set default values if a bad checksum is found.
12966 if (AdvGet38C1600EEPConfig(iop_base
, &eep_config
) !=
12967 eep_config
.check_sum
) {
12968 struct pci_dev
*pdev
= adv_dvc_to_pdev(asc_dvc
);
12969 warn_code
|= ASC_WARN_EEPROM_CHKSUM
;
12972 * Set EEPROM default values.
12974 memcpy(&eep_config
, &Default_38C1600_EEPROM_Config
,
12975 sizeof(ADVEEP_38C1600_CONFIG
));
12977 if (PCI_FUNC(pdev
->devfn
) != 0) {
12980 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
12981 * and old Mac system booting problem. The Expansion
12982 * ROM must be disabled in Function 1 for these systems
12984 eep_config
.cfg_lsw
&= ~ADV_EEPROM_BIOS_ENABLE
;
12986 * Clear the INTAB (bit 11) if the GPIO 0 input
12987 * indicates the Function 1 interrupt line is wired
12990 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
12991 * 1 - Function 1 interrupt line wired to INT A.
12992 * 0 - Function 1 interrupt line wired to INT B.
12994 * Note: Function 0 is always wired to INTA.
12995 * Put all 5 GPIO bits in input mode and then read
12996 * their input values.
12998 AdvWriteByteRegister(iop_base
, IOPB_GPIO_CNTL
, 0);
12999 ints
= AdvReadByteRegister(iop_base
, IOPB_GPIO_DATA
);
13000 if ((ints
& 0x01) == 0)
13001 eep_config
.cfg_lsw
&= ~ADV_EEPROM_INTAB
;
13005 * Assume the 6 byte board serial number that was read from
13006 * EEPROM is correct even if the EEPROM checksum failed.
13008 eep_config
.serial_number_word3
=
13009 AdvReadEEPWord(iop_base
, ADV_EEP_DVC_CFG_END
- 1);
13010 eep_config
.serial_number_word2
=
13011 AdvReadEEPWord(iop_base
, ADV_EEP_DVC_CFG_END
- 2);
13012 eep_config
.serial_number_word1
=
13013 AdvReadEEPWord(iop_base
, ADV_EEP_DVC_CFG_END
- 3);
13015 AdvSet38C1600EEPConfig(iop_base
, &eep_config
);
13019 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
13020 * EEPROM configuration that was read.
13022 * This is the mapping of EEPROM fields to Adv Library fields.
13024 asc_dvc
->wdtr_able
= eep_config
.wdtr_able
;
13025 asc_dvc
->sdtr_speed1
= eep_config
.sdtr_speed1
;
13026 asc_dvc
->sdtr_speed2
= eep_config
.sdtr_speed2
;
13027 asc_dvc
->sdtr_speed3
= eep_config
.sdtr_speed3
;
13028 asc_dvc
->sdtr_speed4
= eep_config
.sdtr_speed4
;
13029 asc_dvc
->ppr_able
= 0;
13030 asc_dvc
->tagqng_able
= eep_config
.tagqng_able
;
13031 asc_dvc
->cfg
->disc_enable
= eep_config
.disc_enable
;
13032 asc_dvc
->max_host_qng
= eep_config
.max_host_qng
;
13033 asc_dvc
->max_dvc_qng
= eep_config
.max_dvc_qng
;
13034 asc_dvc
->chip_scsi_id
= (eep_config
.adapter_scsi_id
& ASC_MAX_TID
);
13035 asc_dvc
->start_motor
= eep_config
.start_motor
;
13036 asc_dvc
->scsi_reset_wait
= eep_config
.scsi_reset_delay
;
13037 asc_dvc
->bios_ctrl
= eep_config
.bios_ctrl
;
13038 asc_dvc
->no_scam
= eep_config
.scam_tolerant
;
13041 * For every Target ID if any of its 'sdtr_speed[1234]' bits
13042 * are set, then set an 'sdtr_able' bit for it.
13044 asc_dvc
->sdtr_able
= 0;
13045 for (tid
= 0; tid
<= ASC_MAX_TID
; tid
++) {
13047 sdtr_speed
= asc_dvc
->sdtr_speed1
;
13048 } else if (tid
== 4) {
13049 sdtr_speed
= asc_dvc
->sdtr_speed2
;
13050 } else if (tid
== 8) {
13051 sdtr_speed
= asc_dvc
->sdtr_speed3
;
13052 } else if (tid
== 12) {
13053 sdtr_speed
= asc_dvc
->sdtr_speed4
;
13055 if (sdtr_speed
& ASC_MAX_TID
) {
13056 asc_dvc
->sdtr_able
|= (1 << tid
);
13062 * Set the host maximum queuing (max. 253, min. 16) and the per device
13063 * maximum queuing (max. 63, min. 4).
13065 if (eep_config
.max_host_qng
> ASC_DEF_MAX_HOST_QNG
) {
13066 eep_config
.max_host_qng
= ASC_DEF_MAX_HOST_QNG
;
13067 } else if (eep_config
.max_host_qng
< ASC_DEF_MIN_HOST_QNG
) {
13068 /* If the value is zero, assume it is uninitialized. */
13069 if (eep_config
.max_host_qng
== 0) {
13070 eep_config
.max_host_qng
= ASC_DEF_MAX_HOST_QNG
;
13072 eep_config
.max_host_qng
= ASC_DEF_MIN_HOST_QNG
;
13076 if (eep_config
.max_dvc_qng
> ASC_DEF_MAX_DVC_QNG
) {
13077 eep_config
.max_dvc_qng
= ASC_DEF_MAX_DVC_QNG
;
13078 } else if (eep_config
.max_dvc_qng
< ASC_DEF_MIN_DVC_QNG
) {
13079 /* If the value is zero, assume it is uninitialized. */
13080 if (eep_config
.max_dvc_qng
== 0) {
13081 eep_config
.max_dvc_qng
= ASC_DEF_MAX_DVC_QNG
;
13083 eep_config
.max_dvc_qng
= ASC_DEF_MIN_DVC_QNG
;
13088 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13089 * set 'max_dvc_qng' to 'max_host_qng'.
13091 if (eep_config
.max_dvc_qng
> eep_config
.max_host_qng
) {
13092 eep_config
.max_dvc_qng
= eep_config
.max_host_qng
;
13096 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
13097 * values based on possibly adjusted EEPROM values.
13099 asc_dvc
->max_host_qng
= eep_config
.max_host_qng
;
13100 asc_dvc
->max_dvc_qng
= eep_config
.max_dvc_qng
;
13103 * If the EEPROM 'termination' field is set to automatic (0), then set
13104 * the ASC_DVC_CFG 'termination' field to automatic also.
13106 * If the termination is specified with a non-zero 'termination'
13107 * value check that a legal value is set and set the ASC_DVC_CFG
13108 * 'termination' field appropriately.
13110 if (eep_config
.termination_se
== 0) {
13111 termination
= 0; /* auto termination for SE */
13113 /* Enable manual control with low off / high off. */
13114 if (eep_config
.termination_se
== 1) {
13117 /* Enable manual control with low off / high on. */
13118 } else if (eep_config
.termination_se
== 2) {
13119 termination
= TERM_SE_HI
;
13121 /* Enable manual control with low on / high on. */
13122 } else if (eep_config
.termination_se
== 3) {
13123 termination
= TERM_SE
;
13126 * The EEPROM 'termination_se' field contains a bad value.
13127 * Use automatic termination instead.
13130 warn_code
|= ASC_WARN_EEPROM_TERMINATION
;
13134 if (eep_config
.termination_lvd
== 0) {
13135 asc_dvc
->cfg
->termination
= termination
; /* auto termination for LVD */
13137 /* Enable manual control with low off / high off. */
13138 if (eep_config
.termination_lvd
== 1) {
13139 asc_dvc
->cfg
->termination
= termination
;
13141 /* Enable manual control with low off / high on. */
13142 } else if (eep_config
.termination_lvd
== 2) {
13143 asc_dvc
->cfg
->termination
= termination
| TERM_LVD_HI
;
13145 /* Enable manual control with low on / high on. */
13146 } else if (eep_config
.termination_lvd
== 3) {
13147 asc_dvc
->cfg
->termination
= termination
| TERM_LVD
;
13150 * The EEPROM 'termination_lvd' field contains a bad value.
13151 * Use automatic termination instead.
13153 asc_dvc
->cfg
->termination
= termination
;
13154 warn_code
|= ASC_WARN_EEPROM_TERMINATION
;
13162 * Initialize the ADV_DVC_VAR structure.
13164 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
13166 * For a non-fatal error return a warning code. If there are no warnings
13167 * then 0 is returned.
13169 static int __devinit
13170 AdvInitGetConfig(struct pci_dev
*pdev
, struct Scsi_Host
*shost
)
13172 struct asc_board
*board
= shost_priv(shost
);
13173 ADV_DVC_VAR
*asc_dvc
= &board
->dvc_var
.adv_dvc_var
;
13174 unsigned short warn_code
= 0;
13175 AdvPortAddr iop_base
= asc_dvc
->iop_base
;
13179 asc_dvc
->err_code
= 0;
13182 * Save the state of the PCI Configuration Command Register
13183 * "Parity Error Response Control" Bit. If the bit is clear (0),
13184 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
13185 * DMA parity errors.
13187 asc_dvc
->cfg
->control_flag
= 0;
13188 pci_read_config_word(pdev
, PCI_COMMAND
, &cmd
);
13189 if ((cmd
& PCI_COMMAND_PARITY
) == 0)
13190 asc_dvc
->cfg
->control_flag
|= CONTROL_FLAG_IGNORE_PERR
;
13192 asc_dvc
->cfg
->chip_version
=
13193 AdvGetChipVersion(iop_base
, asc_dvc
->bus_type
);
13195 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
13196 (ushort
)AdvReadByteRegister(iop_base
, IOPB_CHIP_ID_1
),
13197 (ushort
)ADV_CHIP_ID_BYTE
);
13199 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
13200 (ushort
)AdvReadWordRegister(iop_base
, IOPW_CHIP_ID_0
),
13201 (ushort
)ADV_CHIP_ID_WORD
);
13204 * Reset the chip to start and allow register writes.
13206 if (AdvFindSignature(iop_base
) == 0) {
13207 asc_dvc
->err_code
= ASC_IERR_BAD_SIGNATURE
;
13211 * The caller must set 'chip_type' to a valid setting.
13213 if (asc_dvc
->chip_type
!= ADV_CHIP_ASC3550
&&
13214 asc_dvc
->chip_type
!= ADV_CHIP_ASC38C0800
&&
13215 asc_dvc
->chip_type
!= ADV_CHIP_ASC38C1600
) {
13216 asc_dvc
->err_code
|= ASC_IERR_BAD_CHIPTYPE
;
13223 AdvWriteWordRegister(iop_base
, IOPW_CTRL_REG
,
13224 ADV_CTRL_REG_CMD_RESET
);
13226 AdvWriteWordRegister(iop_base
, IOPW_CTRL_REG
,
13227 ADV_CTRL_REG_CMD_WR_IO_REG
);
13229 if (asc_dvc
->chip_type
== ADV_CHIP_ASC38C1600
) {
13230 status
= AdvInitFrom38C1600EEP(asc_dvc
);
13231 } else if (asc_dvc
->chip_type
== ADV_CHIP_ASC38C0800
) {
13232 status
= AdvInitFrom38C0800EEP(asc_dvc
);
13234 status
= AdvInitFrom3550EEP(asc_dvc
);
13236 warn_code
|= status
;
13239 if (warn_code
!= 0)
13240 shost_printk(KERN_WARNING
, shost
, "warning: 0x%x\n", warn_code
);
13242 if (asc_dvc
->err_code
)
13243 shost_printk(KERN_ERR
, shost
, "error code 0x%x\n",
13244 asc_dvc
->err_code
);
13246 return asc_dvc
->err_code
;
13250 static struct scsi_host_template advansys_template
= {
13251 .proc_name
= DRV_NAME
,
13252 #ifdef CONFIG_PROC_FS
13253 .proc_info
= advansys_proc_info
,
13256 .info
= advansys_info
,
13257 .queuecommand
= advansys_queuecommand
,
13258 .eh_bus_reset_handler
= advansys_reset
,
13259 .bios_param
= advansys_biosparam
,
13260 .slave_configure
= advansys_slave_configure
,
13262 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
13263 * must be set. The flag will be cleared in advansys_board_found
13264 * for non-ISA adapters.
13266 .unchecked_isa_dma
= 1,
13268 * All adapters controlled by this driver are capable of large
13269 * scatter-gather lists. According to the mid-level SCSI documentation
13270 * this obviates any performance gain provided by setting
13271 * 'use_clustering'. But empirically while CPU utilization is increased
13272 * by enabling clustering, I/O throughput increases as well.
13274 .use_clustering
= ENABLE_CLUSTERING
,
13277 static int __devinit
advansys_wide_init_chip(struct Scsi_Host
*shost
)
13279 struct asc_board
*board
= shost_priv(shost
);
13280 struct adv_dvc_var
*adv_dvc
= &board
->dvc_var
.adv_dvc_var
;
13282 adv_req_t
*reqp
= NULL
;
13285 int warn_code
, err_code
;
13288 * Allocate buffer carrier structures. The total size
13289 * is about 4 KB, so allocate all at once.
13291 adv_dvc
->carrier_buf
= kmalloc(ADV_CARRIER_BUFSIZE
, GFP_KERNEL
);
13292 ASC_DBG(1, "carrier_buf 0x%p\n", adv_dvc
->carrier_buf
);
13294 if (!adv_dvc
->carrier_buf
)
13295 goto kmalloc_failed
;
13298 * Allocate up to 'max_host_qng' request structures for the Wide
13299 * board. The total size is about 16 KB, so allocate all at once.
13300 * If the allocation fails decrement and try again.
13302 for (req_cnt
= adv_dvc
->max_host_qng
; req_cnt
> 0; req_cnt
--) {
13303 reqp
= kmalloc(sizeof(adv_req_t
) * req_cnt
, GFP_KERNEL
);
13305 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", reqp
, req_cnt
,
13306 (ulong
)sizeof(adv_req_t
) * req_cnt
);
13313 goto kmalloc_failed
;
13315 adv_dvc
->orig_reqp
= reqp
;
13318 * Allocate up to ADV_TOT_SG_BLOCK request structures for
13319 * the Wide board. Each structure is about 136 bytes.
13321 board
->adv_sgblkp
= NULL
;
13322 for (sg_cnt
= 0; sg_cnt
< ADV_TOT_SG_BLOCK
; sg_cnt
++) {
13323 sgp
= kmalloc(sizeof(adv_sgblk_t
), GFP_KERNEL
);
13328 sgp
->next_sgblkp
= board
->adv_sgblkp
;
13329 board
->adv_sgblkp
= sgp
;
13333 ASC_DBG(1, "sg_cnt %d * %u = %u bytes\n", sg_cnt
, sizeof(adv_sgblk_t
),
13334 (unsigned)(sizeof(adv_sgblk_t
) * sg_cnt
));
13336 if (!board
->adv_sgblkp
)
13337 goto kmalloc_failed
;
13340 * Point 'adv_reqp' to the request structures and
13341 * link them together.
13344 reqp
[req_cnt
].next_reqp
= NULL
;
13345 for (; req_cnt
> 0; req_cnt
--) {
13346 reqp
[req_cnt
- 1].next_reqp
= &reqp
[req_cnt
];
13348 board
->adv_reqp
= &reqp
[0];
13350 if (adv_dvc
->chip_type
== ADV_CHIP_ASC3550
) {
13351 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
13352 warn_code
= AdvInitAsc3550Driver(adv_dvc
);
13353 } else if (adv_dvc
->chip_type
== ADV_CHIP_ASC38C0800
) {
13354 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
13355 warn_code
= AdvInitAsc38C0800Driver(adv_dvc
);
13357 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
13358 warn_code
= AdvInitAsc38C1600Driver(adv_dvc
);
13360 err_code
= adv_dvc
->err_code
;
13362 if (warn_code
|| err_code
) {
13363 shost_printk(KERN_WARNING
, shost
, "error: warn 0x%x, error "
13364 "0x%x\n", warn_code
, err_code
);
13370 shost_printk(KERN_ERR
, shost
, "error: kmalloc() failed\n");
13371 err_code
= ADV_ERROR
;
13376 static void advansys_wide_free_mem(struct asc_board
*board
)
13378 struct adv_dvc_var
*adv_dvc
= &board
->dvc_var
.adv_dvc_var
;
13379 kfree(adv_dvc
->carrier_buf
);
13380 adv_dvc
->carrier_buf
= NULL
;
13381 kfree(adv_dvc
->orig_reqp
);
13382 adv_dvc
->orig_reqp
= board
->adv_reqp
= NULL
;
13383 while (board
->adv_sgblkp
) {
13384 adv_sgblk_t
*sgp
= board
->adv_sgblkp
;
13385 board
->adv_sgblkp
= sgp
->next_sgblkp
;
13390 static int __devinit
advansys_board_found(struct Scsi_Host
*shost
,
13391 unsigned int iop
, int bus_type
)
13393 struct pci_dev
*pdev
;
13394 struct asc_board
*boardp
= shost_priv(shost
);
13395 ASC_DVC_VAR
*asc_dvc_varp
= NULL
;
13396 ADV_DVC_VAR
*adv_dvc_varp
= NULL
;
13397 int share_irq
, warn_code
, ret
;
13399 pdev
= (bus_type
== ASC_IS_PCI
) ? to_pci_dev(boardp
->dev
) : NULL
;
13401 if (ASC_NARROW_BOARD(boardp
)) {
13402 ASC_DBG(1, "narrow board\n");
13403 asc_dvc_varp
= &boardp
->dvc_var
.asc_dvc_var
;
13404 asc_dvc_varp
->bus_type
= bus_type
;
13405 asc_dvc_varp
->drv_ptr
= boardp
;
13406 asc_dvc_varp
->cfg
= &boardp
->dvc_cfg
.asc_dvc_cfg
;
13407 asc_dvc_varp
->cfg
->overrun_buf
= &overrun_buf
[0];
13408 asc_dvc_varp
->iop_base
= iop
;
13411 adv_dvc_varp
= &boardp
->dvc_var
.adv_dvc_var
;
13412 adv_dvc_varp
->drv_ptr
= boardp
;
13413 adv_dvc_varp
->cfg
= &boardp
->dvc_cfg
.adv_dvc_cfg
;
13414 if (pdev
->device
== PCI_DEVICE_ID_ASP_ABP940UW
) {
13415 ASC_DBG(1, "wide board ASC-3550\n");
13416 adv_dvc_varp
->chip_type
= ADV_CHIP_ASC3550
;
13417 } else if (pdev
->device
== PCI_DEVICE_ID_38C0800_REV1
) {
13418 ASC_DBG(1, "wide board ASC-38C0800\n");
13419 adv_dvc_varp
->chip_type
= ADV_CHIP_ASC38C0800
;
13421 ASC_DBG(1, "wide board ASC-38C1600\n");
13422 adv_dvc_varp
->chip_type
= ADV_CHIP_ASC38C1600
;
13425 boardp
->asc_n_io_port
= pci_resource_len(pdev
, 1);
13426 boardp
->ioremap_addr
= ioremap(pci_resource_start(pdev
, 1),
13427 boardp
->asc_n_io_port
);
13428 if (!boardp
->ioremap_addr
) {
13429 shost_printk(KERN_ERR
, shost
, "ioremap(%x, %d) "
13431 pci_resource_start(pdev
, 1),
13432 boardp
->asc_n_io_port
);
13436 adv_dvc_varp
->iop_base
= (AdvPortAddr
)boardp
->ioremap_addr
;
13437 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp
->iop_base
);
13440 * Even though it isn't used to access wide boards, other
13441 * than for the debug line below, save I/O Port address so
13442 * that it can be reported.
13444 boardp
->ioport
= iop
;
13446 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
13447 (ushort
)inp(iop
+ 1), (ushort
)inpw(iop
));
13448 #endif /* CONFIG_PCI */
13451 #ifdef CONFIG_PROC_FS
13453 * Allocate buffer for printing information from
13454 * /proc/scsi/advansys/[0...].
13456 boardp
->prtbuf
= kmalloc(ASC_PRTBUF_SIZE
, GFP_KERNEL
);
13457 if (!boardp
->prtbuf
) {
13458 shost_printk(KERN_ERR
, shost
, "kmalloc(%d) returned NULL\n",
13463 #endif /* CONFIG_PROC_FS */
13465 if (ASC_NARROW_BOARD(boardp
)) {
13467 * Set the board bus type and PCI IRQ before
13468 * calling AscInitGetConfig().
13470 switch (asc_dvc_varp
->bus_type
) {
13473 shost
->unchecked_isa_dma
= TRUE
;
13477 shost
->unchecked_isa_dma
= FALSE
;
13481 shost
->unchecked_isa_dma
= FALSE
;
13482 share_irq
= IRQF_SHARED
;
13484 #endif /* CONFIG_ISA */
13487 shost
->unchecked_isa_dma
= FALSE
;
13488 share_irq
= IRQF_SHARED
;
13490 #endif /* CONFIG_PCI */
13492 shost_printk(KERN_ERR
, shost
, "unknown adapter type: "
13493 "%d\n", asc_dvc_varp
->bus_type
);
13494 shost
->unchecked_isa_dma
= TRUE
;
13500 * NOTE: AscInitGetConfig() may change the board's
13501 * bus_type value. The bus_type value should no
13502 * longer be used. If the bus_type field must be
13503 * referenced only use the bit-wise AND operator "&".
13505 ASC_DBG(2, "AscInitGetConfig()\n");
13506 ret
= AscInitGetConfig(shost
) ? -ENODEV
: 0;
13510 * For Wide boards set PCI information before calling
13511 * AdvInitGetConfig().
13513 shost
->unchecked_isa_dma
= FALSE
;
13514 share_irq
= IRQF_SHARED
;
13515 ASC_DBG(2, "AdvInitGetConfig()\n");
13517 ret
= AdvInitGetConfig(pdev
, shost
) ? -ENODEV
: 0;
13518 #endif /* CONFIG_PCI */
13522 goto err_free_proc
;
13525 * Save the EEPROM configuration so that it can be displayed
13526 * from /proc/scsi/advansys/[0...].
13528 if (ASC_NARROW_BOARD(boardp
)) {
13533 * Set the adapter's target id bit in the 'init_tidmask' field.
13535 boardp
->init_tidmask
|=
13536 ADV_TID_TO_TIDMASK(asc_dvc_varp
->cfg
->chip_scsi_id
);
13539 * Save EEPROM settings for the board.
13541 ep
= &boardp
->eep_config
.asc_eep
;
13543 ep
->init_sdtr
= asc_dvc_varp
->cfg
->sdtr_enable
;
13544 ep
->disc_enable
= asc_dvc_varp
->cfg
->disc_enable
;
13545 ep
->use_cmd_qng
= asc_dvc_varp
->cfg
->cmd_qng_enabled
;
13546 ASC_EEP_SET_DMA_SPD(ep
, asc_dvc_varp
->cfg
->isa_dma_speed
);
13547 ep
->start_motor
= asc_dvc_varp
->start_motor
;
13548 ep
->cntl
= asc_dvc_varp
->dvc_cntl
;
13549 ep
->no_scam
= asc_dvc_varp
->no_scam
;
13550 ep
->max_total_qng
= asc_dvc_varp
->max_total_qng
;
13551 ASC_EEP_SET_CHIP_ID(ep
, asc_dvc_varp
->cfg
->chip_scsi_id
);
13552 /* 'max_tag_qng' is set to the same value for every device. */
13553 ep
->max_tag_qng
= asc_dvc_varp
->cfg
->max_tag_qng
[0];
13554 ep
->adapter_info
[0] = asc_dvc_varp
->cfg
->adapter_info
[0];
13555 ep
->adapter_info
[1] = asc_dvc_varp
->cfg
->adapter_info
[1];
13556 ep
->adapter_info
[2] = asc_dvc_varp
->cfg
->adapter_info
[2];
13557 ep
->adapter_info
[3] = asc_dvc_varp
->cfg
->adapter_info
[3];
13558 ep
->adapter_info
[4] = asc_dvc_varp
->cfg
->adapter_info
[4];
13559 ep
->adapter_info
[5] = asc_dvc_varp
->cfg
->adapter_info
[5];
13562 * Modify board configuration.
13564 ASC_DBG(2, "AscInitSetConfig()\n");
13565 ret
= AscInitSetConfig(pdev
, shost
) ? -ENODEV
: 0;
13567 goto err_free_proc
;
13569 ADVEEP_3550_CONFIG
*ep_3550
;
13570 ADVEEP_38C0800_CONFIG
*ep_38C0800
;
13571 ADVEEP_38C1600_CONFIG
*ep_38C1600
;
13574 * Save Wide EEP Configuration Information.
13576 if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC3550
) {
13577 ep_3550
= &boardp
->eep_config
.adv_3550_eep
;
13579 ep_3550
->adapter_scsi_id
= adv_dvc_varp
->chip_scsi_id
;
13580 ep_3550
->max_host_qng
= adv_dvc_varp
->max_host_qng
;
13581 ep_3550
->max_dvc_qng
= adv_dvc_varp
->max_dvc_qng
;
13582 ep_3550
->termination
= adv_dvc_varp
->cfg
->termination
;
13583 ep_3550
->disc_enable
= adv_dvc_varp
->cfg
->disc_enable
;
13584 ep_3550
->bios_ctrl
= adv_dvc_varp
->bios_ctrl
;
13585 ep_3550
->wdtr_able
= adv_dvc_varp
->wdtr_able
;
13586 ep_3550
->sdtr_able
= adv_dvc_varp
->sdtr_able
;
13587 ep_3550
->ultra_able
= adv_dvc_varp
->ultra_able
;
13588 ep_3550
->tagqng_able
= adv_dvc_varp
->tagqng_able
;
13589 ep_3550
->start_motor
= adv_dvc_varp
->start_motor
;
13590 ep_3550
->scsi_reset_delay
=
13591 adv_dvc_varp
->scsi_reset_wait
;
13592 ep_3550
->serial_number_word1
=
13593 adv_dvc_varp
->cfg
->serial1
;
13594 ep_3550
->serial_number_word2
=
13595 adv_dvc_varp
->cfg
->serial2
;
13596 ep_3550
->serial_number_word3
=
13597 adv_dvc_varp
->cfg
->serial3
;
13598 } else if (adv_dvc_varp
->chip_type
== ADV_CHIP_ASC38C0800
) {
13599 ep_38C0800
= &boardp
->eep_config
.adv_38C0800_eep
;
13601 ep_38C0800
->adapter_scsi_id
=
13602 adv_dvc_varp
->chip_scsi_id
;
13603 ep_38C0800
->max_host_qng
= adv_dvc_varp
->max_host_qng
;
13604 ep_38C0800
->max_dvc_qng
= adv_dvc_varp
->max_dvc_qng
;
13605 ep_38C0800
->termination_lvd
=
13606 adv_dvc_varp
->cfg
->termination
;
13607 ep_38C0800
->disc_enable
=
13608 adv_dvc_varp
->cfg
->disc_enable
;
13609 ep_38C0800
->bios_ctrl
= adv_dvc_varp
->bios_ctrl
;
13610 ep_38C0800
->wdtr_able
= adv_dvc_varp
->wdtr_able
;
13611 ep_38C0800
->tagqng_able
= adv_dvc_varp
->tagqng_able
;
13612 ep_38C0800
->sdtr_speed1
= adv_dvc_varp
->sdtr_speed1
;
13613 ep_38C0800
->sdtr_speed2
= adv_dvc_varp
->sdtr_speed2
;
13614 ep_38C0800
->sdtr_speed3
= adv_dvc_varp
->sdtr_speed3
;
13615 ep_38C0800
->sdtr_speed4
= adv_dvc_varp
->sdtr_speed4
;
13616 ep_38C0800
->tagqng_able
= adv_dvc_varp
->tagqng_able
;
13617 ep_38C0800
->start_motor
= adv_dvc_varp
->start_motor
;
13618 ep_38C0800
->scsi_reset_delay
=
13619 adv_dvc_varp
->scsi_reset_wait
;
13620 ep_38C0800
->serial_number_word1
=
13621 adv_dvc_varp
->cfg
->serial1
;
13622 ep_38C0800
->serial_number_word2
=
13623 adv_dvc_varp
->cfg
->serial2
;
13624 ep_38C0800
->serial_number_word3
=
13625 adv_dvc_varp
->cfg
->serial3
;
13627 ep_38C1600
= &boardp
->eep_config
.adv_38C1600_eep
;
13629 ep_38C1600
->adapter_scsi_id
=
13630 adv_dvc_varp
->chip_scsi_id
;
13631 ep_38C1600
->max_host_qng
= adv_dvc_varp
->max_host_qng
;
13632 ep_38C1600
->max_dvc_qng
= adv_dvc_varp
->max_dvc_qng
;
13633 ep_38C1600
->termination_lvd
=
13634 adv_dvc_varp
->cfg
->termination
;
13635 ep_38C1600
->disc_enable
=
13636 adv_dvc_varp
->cfg
->disc_enable
;
13637 ep_38C1600
->bios_ctrl
= adv_dvc_varp
->bios_ctrl
;
13638 ep_38C1600
->wdtr_able
= adv_dvc_varp
->wdtr_able
;
13639 ep_38C1600
->tagqng_able
= adv_dvc_varp
->tagqng_able
;
13640 ep_38C1600
->sdtr_speed1
= adv_dvc_varp
->sdtr_speed1
;
13641 ep_38C1600
->sdtr_speed2
= adv_dvc_varp
->sdtr_speed2
;
13642 ep_38C1600
->sdtr_speed3
= adv_dvc_varp
->sdtr_speed3
;
13643 ep_38C1600
->sdtr_speed4
= adv_dvc_varp
->sdtr_speed4
;
13644 ep_38C1600
->tagqng_able
= adv_dvc_varp
->tagqng_able
;
13645 ep_38C1600
->start_motor
= adv_dvc_varp
->start_motor
;
13646 ep_38C1600
->scsi_reset_delay
=
13647 adv_dvc_varp
->scsi_reset_wait
;
13648 ep_38C1600
->serial_number_word1
=
13649 adv_dvc_varp
->cfg
->serial1
;
13650 ep_38C1600
->serial_number_word2
=
13651 adv_dvc_varp
->cfg
->serial2
;
13652 ep_38C1600
->serial_number_word3
=
13653 adv_dvc_varp
->cfg
->serial3
;
13657 * Set the adapter's target id bit in the 'init_tidmask' field.
13659 boardp
->init_tidmask
|=
13660 ADV_TID_TO_TIDMASK(adv_dvc_varp
->chip_scsi_id
);
13664 * Channels are numbered beginning with 0. For AdvanSys one host
13665 * structure supports one channel. Multi-channel boards have a
13666 * separate host structure for each channel.
13668 shost
->max_channel
= 0;
13669 if (ASC_NARROW_BOARD(boardp
)) {
13670 shost
->max_id
= ASC_MAX_TID
+ 1;
13671 shost
->max_lun
= ASC_MAX_LUN
+ 1;
13672 shost
->max_cmd_len
= ASC_MAX_CDB_LEN
;
13674 shost
->io_port
= asc_dvc_varp
->iop_base
;
13675 boardp
->asc_n_io_port
= ASC_IOADR_GAP
;
13676 shost
->this_id
= asc_dvc_varp
->cfg
->chip_scsi_id
;
13678 /* Set maximum number of queues the adapter can handle. */
13679 shost
->can_queue
= asc_dvc_varp
->max_total_qng
;
13681 shost
->max_id
= ADV_MAX_TID
+ 1;
13682 shost
->max_lun
= ADV_MAX_LUN
+ 1;
13683 shost
->max_cmd_len
= ADV_MAX_CDB_LEN
;
13686 * Save the I/O Port address and length even though
13687 * I/O ports are not used to access Wide boards.
13688 * Instead the Wide boards are accessed with
13689 * PCI Memory Mapped I/O.
13691 shost
->io_port
= iop
;
13693 shost
->this_id
= adv_dvc_varp
->chip_scsi_id
;
13695 /* Set maximum number of queues the adapter can handle. */
13696 shost
->can_queue
= adv_dvc_varp
->max_host_qng
;
13700 * Following v1.3.89, 'cmd_per_lun' is no longer needed
13701 * and should be set to zero.
13703 * But because of a bug introduced in v1.3.89 if the driver is
13704 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
13705 * SCSI function 'allocate_device' will panic. To allow the driver
13706 * to work as a module in these kernels set 'cmd_per_lun' to 1.
13708 * Note: This is wrong. cmd_per_lun should be set to the depth
13709 * you want on untagged devices always.
13712 shost
->cmd_per_lun
= 1;
13714 shost->cmd_per_lun = 0;
13718 * Set the maximum number of scatter-gather elements the
13719 * adapter can handle.
13721 if (ASC_NARROW_BOARD(boardp
)) {
13723 * Allow two commands with 'sg_tablesize' scatter-gather
13724 * elements to be executed simultaneously. This value is
13725 * the theoretical hardware limit. It may be decreased
13728 shost
->sg_tablesize
=
13729 (((asc_dvc_varp
->max_total_qng
- 2) / 2) *
13730 ASC_SG_LIST_PER_Q
) + 1;
13732 shost
->sg_tablesize
= ADV_MAX_SG_LIST
;
13736 * The value of 'sg_tablesize' can not exceed the SCSI
13737 * mid-level driver definition of SG_ALL. SG_ALL also
13738 * must not be exceeded, because it is used to define the
13739 * size of the scatter-gather table in 'struct asc_sg_head'.
13741 if (shost
->sg_tablesize
> SG_ALL
) {
13742 shost
->sg_tablesize
= SG_ALL
;
13745 ASC_DBG(1, "sg_tablesize: %d\n", shost
->sg_tablesize
);
13747 /* BIOS start address. */
13748 if (ASC_NARROW_BOARD(boardp
)) {
13749 shost
->base
= AscGetChipBiosAddress(asc_dvc_varp
->iop_base
,
13750 asc_dvc_varp
->bus_type
);
13753 * Fill-in BIOS board variables. The Wide BIOS saves
13754 * information in LRAM that is used by the driver.
13756 AdvReadWordLram(adv_dvc_varp
->iop_base
,
13757 BIOS_SIGNATURE
, boardp
->bios_signature
);
13758 AdvReadWordLram(adv_dvc_varp
->iop_base
,
13759 BIOS_VERSION
, boardp
->bios_version
);
13760 AdvReadWordLram(adv_dvc_varp
->iop_base
,
13761 BIOS_CODESEG
, boardp
->bios_codeseg
);
13762 AdvReadWordLram(adv_dvc_varp
->iop_base
,
13763 BIOS_CODELEN
, boardp
->bios_codelen
);
13765 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
13766 boardp
->bios_signature
, boardp
->bios_version
);
13768 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
13769 boardp
->bios_codeseg
, boardp
->bios_codelen
);
13772 * If the BIOS saved a valid signature, then fill in
13773 * the BIOS code segment base address.
13775 if (boardp
->bios_signature
== 0x55AA) {
13777 * Convert x86 realmode code segment to a linear
13778 * address by shifting left 4.
13780 shost
->base
= ((ulong
)boardp
->bios_codeseg
<< 4);
13787 * Register Board Resources - I/O Port, DMA, IRQ
13790 /* Register DMA Channel for Narrow boards. */
13791 shost
->dma_channel
= NO_ISA_DMA
; /* Default to no ISA DMA. */
13793 if (ASC_NARROW_BOARD(boardp
)) {
13794 /* Register DMA channel for ISA bus. */
13795 if (asc_dvc_varp
->bus_type
& ASC_IS_ISA
) {
13796 shost
->dma_channel
= asc_dvc_varp
->cfg
->isa_dma_channel
;
13797 ret
= request_dma(shost
->dma_channel
, DRV_NAME
);
13799 shost_printk(KERN_ERR
, shost
, "request_dma() "
13801 shost
->dma_channel
, ret
);
13802 goto err_free_proc
;
13804 AscEnableIsaDma(shost
->dma_channel
);
13807 #endif /* CONFIG_ISA */
13809 /* Register IRQ Number. */
13810 ASC_DBG(2, "request_irq(%d, %p)\n", boardp
->irq
, shost
);
13812 ret
= request_irq(boardp
->irq
, advansys_interrupt
, share_irq
,
13816 if (ret
== -EBUSY
) {
13817 shost_printk(KERN_ERR
, shost
, "request_irq(): IRQ 0x%x "
13818 "already in use\n", boardp
->irq
);
13819 } else if (ret
== -EINVAL
) {
13820 shost_printk(KERN_ERR
, shost
, "request_irq(): IRQ 0x%x "
13821 "not valid\n", boardp
->irq
);
13823 shost_printk(KERN_ERR
, shost
, "request_irq(): IRQ 0x%x "
13824 "failed with %d\n", boardp
->irq
, ret
);
13830 * Initialize board RISC chip and enable interrupts.
13832 if (ASC_NARROW_BOARD(boardp
)) {
13833 ASC_DBG(2, "AscInitAsc1000Driver()\n");
13834 warn_code
= AscInitAsc1000Driver(asc_dvc_varp
);
13836 if (warn_code
|| asc_dvc_varp
->err_code
) {
13837 shost_printk(KERN_ERR
, shost
, "error: init_state 0x%x, "
13838 "warn 0x%x, error 0x%x\n",
13839 asc_dvc_varp
->init_state
, warn_code
,
13840 asc_dvc_varp
->err_code
);
13841 if (asc_dvc_varp
->err_code
)
13845 if (advansys_wide_init_chip(shost
))
13850 goto err_free_wide_mem
;
13852 ASC_DBG_PRT_SCSI_HOST(2, shost
);
13854 ret
= scsi_add_host(shost
, boardp
->dev
);
13856 goto err_free_wide_mem
;
13858 scsi_scan_host(shost
);
13862 advansys_wide_free_mem(boardp
);
13863 free_irq(boardp
->irq
, shost
);
13865 if (shost
->dma_channel
!= NO_ISA_DMA
)
13866 free_dma(shost
->dma_channel
);
13868 kfree(boardp
->prtbuf
);
13870 if (boardp
->ioremap_addr
)
13871 iounmap(boardp
->ioremap_addr
);
13877 * advansys_release()
13879 * Release resources allocated for a single AdvanSys adapter.
13881 static int advansys_release(struct Scsi_Host
*shost
)
13883 struct asc_board
*boardp
= shost_priv(shost
);
13884 ASC_DBG(1, "begin\n");
13885 scsi_remove_host(shost
);
13886 free_irq(boardp
->irq
, shost
);
13887 if (shost
->dma_channel
!= NO_ISA_DMA
) {
13888 ASC_DBG(1, "free_dma()\n");
13889 free_dma(shost
->dma_channel
);
13891 if (!ASC_NARROW_BOARD(boardp
)) {
13892 iounmap(boardp
->ioremap_addr
);
13893 advansys_wide_free_mem(boardp
);
13895 kfree(boardp
->prtbuf
);
13896 scsi_host_put(shost
);
13897 ASC_DBG(1, "end\n");
13901 #define ASC_IOADR_TABLE_MAX_IX 11
13903 static PortAddr _asc_def_iop_base
[ASC_IOADR_TABLE_MAX_IX
] __devinitdata
= {
13904 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
13905 0x0210, 0x0230, 0x0250, 0x0330
13909 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
13915 static unsigned int __devinit
advansys_isa_irq_no(PortAddr iop_base
)
13917 unsigned short cfg_lsw
= AscGetChipCfgLsw(iop_base
);
13918 unsigned int chip_irq
= ((cfg_lsw
>> 2) & 0x03) + 10;
13919 if (chip_irq
== 13)
13924 static int __devinit
advansys_isa_probe(struct device
*dev
, unsigned int id
)
13927 PortAddr iop_base
= _asc_def_iop_base
[id
];
13928 struct Scsi_Host
*shost
;
13929 struct asc_board
*board
;
13931 if (!request_region(iop_base
, ASC_IOADR_GAP
, DRV_NAME
)) {
13932 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base
);
13935 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base
);
13936 if (!AscFindSignature(iop_base
))
13937 goto release_region
;
13938 if (!(AscGetChipVersion(iop_base
, ASC_IS_ISA
) & ASC_CHIP_VER_ISA_BIT
))
13939 goto release_region
;
13942 shost
= scsi_host_alloc(&advansys_template
, sizeof(*board
));
13944 goto release_region
;
13946 board
= shost_priv(shost
);
13947 board
->irq
= advansys_isa_irq_no(iop_base
);
13950 err
= advansys_board_found(shost
, iop_base
, ASC_IS_ISA
);
13954 dev_set_drvdata(dev
, shost
);
13958 scsi_host_put(shost
);
13960 release_region(iop_base
, ASC_IOADR_GAP
);
13964 static int __devexit
advansys_isa_remove(struct device
*dev
, unsigned int id
)
13966 int ioport
= _asc_def_iop_base
[id
];
13967 advansys_release(dev_get_drvdata(dev
));
13968 release_region(ioport
, ASC_IOADR_GAP
);
13972 static struct isa_driver advansys_isa_driver
= {
13973 .probe
= advansys_isa_probe
,
13974 .remove
= __devexit_p(advansys_isa_remove
),
13976 .owner
= THIS_MODULE
,
13982 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
13992 static unsigned int __devinit
advansys_vlb_irq_no(PortAddr iop_base
)
13994 unsigned short cfg_lsw
= AscGetChipCfgLsw(iop_base
);
13995 unsigned int chip_irq
= ((cfg_lsw
>> 2) & 0x07) + 9;
13996 if ((chip_irq
< 10) || (chip_irq
== 13) || (chip_irq
> 15))
14001 static int __devinit
advansys_vlb_probe(struct device
*dev
, unsigned int id
)
14004 PortAddr iop_base
= _asc_def_iop_base
[id
];
14005 struct Scsi_Host
*shost
;
14006 struct asc_board
*board
;
14008 if (!request_region(iop_base
, ASC_IOADR_GAP
, DRV_NAME
)) {
14009 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base
);
14012 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base
);
14013 if (!AscFindSignature(iop_base
))
14014 goto release_region
;
14016 * I don't think this condition can actually happen, but the old
14017 * driver did it, and the chances of finding a VLB setup in 2007
14018 * to do testing with is slight to none.
14020 if (AscGetChipVersion(iop_base
, ASC_IS_VL
) > ASC_CHIP_MAX_VER_VL
)
14021 goto release_region
;
14024 shost
= scsi_host_alloc(&advansys_template
, sizeof(*board
));
14026 goto release_region
;
14028 board
= shost_priv(shost
);
14029 board
->irq
= advansys_vlb_irq_no(iop_base
);
14032 err
= advansys_board_found(shost
, iop_base
, ASC_IS_VL
);
14036 dev_set_drvdata(dev
, shost
);
14040 scsi_host_put(shost
);
14042 release_region(iop_base
, ASC_IOADR_GAP
);
14046 static struct isa_driver advansys_vlb_driver
= {
14047 .probe
= advansys_vlb_probe
,
14048 .remove
= __devexit_p(advansys_isa_remove
),
14050 .owner
= THIS_MODULE
,
14051 .name
= "advansys_vlb",
14055 static struct eisa_device_id advansys_eisa_table
[] __devinitdata
= {
14061 MODULE_DEVICE_TABLE(eisa
, advansys_eisa_table
);
14064 * EISA is a little more tricky than PCI; each EISA device may have two
14065 * channels, and this driver is written to make each channel its own Scsi_Host
14067 struct eisa_scsi_data
{
14068 struct Scsi_Host
*host
[2];
14072 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
14082 static unsigned int __devinit
advansys_eisa_irq_no(struct eisa_device
*edev
)
14084 unsigned short cfg_lsw
= inw(edev
->base_addr
+ 0xc86);
14085 unsigned int chip_irq
= ((cfg_lsw
>> 8) & 0x07) + 10;
14086 if ((chip_irq
== 13) || (chip_irq
> 15))
14091 static int __devinit
advansys_eisa_probe(struct device
*dev
)
14093 int i
, ioport
, irq
= 0;
14095 struct eisa_device
*edev
= to_eisa_device(dev
);
14096 struct eisa_scsi_data
*data
;
14099 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
14102 ioport
= edev
->base_addr
+ 0xc30;
14105 for (i
= 0; i
< 2; i
++, ioport
+= 0x20) {
14106 struct asc_board
*board
;
14107 struct Scsi_Host
*shost
;
14108 if (!request_region(ioport
, ASC_IOADR_GAP
, DRV_NAME
)) {
14109 printk(KERN_WARNING
"Region %x-%x busy\n", ioport
,
14110 ioport
+ ASC_IOADR_GAP
- 1);
14113 if (!AscFindSignature(ioport
)) {
14114 release_region(ioport
, ASC_IOADR_GAP
);
14119 * I don't know why we need to do this for EISA chips, but
14120 * not for any others. It looks to be equivalent to
14121 * AscGetChipCfgMsw, but I may have overlooked something,
14122 * so I'm not converting it until I get an EISA board to
14128 irq
= advansys_eisa_irq_no(edev
);
14131 shost
= scsi_host_alloc(&advansys_template
, sizeof(*board
));
14133 goto release_region
;
14135 board
= shost_priv(shost
);
14139 err
= advansys_board_found(shost
, ioport
, ASC_IS_EISA
);
14141 data
->host
[i
] = shost
;
14145 scsi_host_put(shost
);
14147 release_region(ioport
, ASC_IOADR_GAP
);
14153 dev_set_drvdata(dev
, data
);
14157 kfree(data
->host
[0]);
14158 kfree(data
->host
[1]);
14164 static __devexit
int advansys_eisa_remove(struct device
*dev
)
14167 struct eisa_scsi_data
*data
= dev_get_drvdata(dev
);
14169 for (i
= 0; i
< 2; i
++) {
14171 struct Scsi_Host
*shost
= data
->host
[i
];
14174 ioport
= shost
->io_port
;
14175 advansys_release(shost
);
14176 release_region(ioport
, ASC_IOADR_GAP
);
14183 static struct eisa_driver advansys_eisa_driver
= {
14184 .id_table
= advansys_eisa_table
,
14187 .probe
= advansys_eisa_probe
,
14188 .remove
= __devexit_p(advansys_eisa_remove
),
14192 /* PCI Devices supported by this driver */
14193 static struct pci_device_id advansys_pci_tbl
[] __devinitdata
= {
14194 {PCI_VENDOR_ID_ASP
, PCI_DEVICE_ID_ASP_1200A
,
14195 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
14196 {PCI_VENDOR_ID_ASP
, PCI_DEVICE_ID_ASP_ABP940
,
14197 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
14198 {PCI_VENDOR_ID_ASP
, PCI_DEVICE_ID_ASP_ABP940U
,
14199 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
14200 {PCI_VENDOR_ID_ASP
, PCI_DEVICE_ID_ASP_ABP940UW
,
14201 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
14202 {PCI_VENDOR_ID_ASP
, PCI_DEVICE_ID_38C0800_REV1
,
14203 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
14204 {PCI_VENDOR_ID_ASP
, PCI_DEVICE_ID_38C1600_REV1
,
14205 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
14209 MODULE_DEVICE_TABLE(pci
, advansys_pci_tbl
);
14211 static void __devinit
advansys_set_latency(struct pci_dev
*pdev
)
14213 if ((pdev
->device
== PCI_DEVICE_ID_ASP_1200A
) ||
14214 (pdev
->device
== PCI_DEVICE_ID_ASP_ABP940
)) {
14215 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0);
14218 pci_read_config_byte(pdev
, PCI_LATENCY_TIMER
, &latency
);
14219 if (latency
< 0x20)
14220 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0x20);
14224 static int __devinit
14225 advansys_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
14228 struct Scsi_Host
*shost
;
14229 struct asc_board
*board
;
14231 err
= pci_enable_device(pdev
);
14234 err
= pci_request_regions(pdev
, DRV_NAME
);
14236 goto disable_device
;
14237 pci_set_master(pdev
);
14238 advansys_set_latency(pdev
);
14241 if (pci_resource_len(pdev
, 0) == 0)
14242 goto release_region
;
14244 ioport
= pci_resource_start(pdev
, 0);
14247 shost
= scsi_host_alloc(&advansys_template
, sizeof(*board
));
14249 goto release_region
;
14251 board
= shost_priv(shost
);
14252 board
->irq
= pdev
->irq
;
14253 board
->dev
= &pdev
->dev
;
14255 if (pdev
->device
== PCI_DEVICE_ID_ASP_ABP940UW
||
14256 pdev
->device
== PCI_DEVICE_ID_38C0800_REV1
||
14257 pdev
->device
== PCI_DEVICE_ID_38C1600_REV1
) {
14258 board
->flags
|= ASC_IS_WIDE_BOARD
;
14261 err
= advansys_board_found(shost
, ioport
, ASC_IS_PCI
);
14265 pci_set_drvdata(pdev
, shost
);
14269 scsi_host_put(shost
);
14271 pci_release_regions(pdev
);
14273 pci_disable_device(pdev
);
14278 static void __devexit
advansys_pci_remove(struct pci_dev
*pdev
)
14280 advansys_release(pci_get_drvdata(pdev
));
14281 pci_release_regions(pdev
);
14282 pci_disable_device(pdev
);
14285 static struct pci_driver advansys_pci_driver
= {
14287 .id_table
= advansys_pci_tbl
,
14288 .probe
= advansys_pci_probe
,
14289 .remove
= __devexit_p(advansys_pci_remove
),
14292 static int __init
advansys_init(void)
14296 error
= isa_register_driver(&advansys_isa_driver
,
14297 ASC_IOADR_TABLE_MAX_IX
);
14301 error
= isa_register_driver(&advansys_vlb_driver
,
14302 ASC_IOADR_TABLE_MAX_IX
);
14304 goto unregister_isa
;
14306 error
= eisa_driver_register(&advansys_eisa_driver
);
14308 goto unregister_vlb
;
14310 error
= pci_register_driver(&advansys_pci_driver
);
14312 goto unregister_eisa
;
14317 eisa_driver_unregister(&advansys_eisa_driver
);
14319 isa_unregister_driver(&advansys_vlb_driver
);
14321 isa_unregister_driver(&advansys_isa_driver
);
14326 static void __exit
advansys_exit(void)
14328 pci_unregister_driver(&advansys_pci_driver
);
14329 eisa_driver_unregister(&advansys_eisa_driver
);
14330 isa_unregister_driver(&advansys_vlb_driver
);
14331 isa_unregister_driver(&advansys_isa_driver
);
14334 module_init(advansys_init
);
14335 module_exit(advansys_exit
);
14337 MODULE_LICENSE("GPL");