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20fc0846e0bec26b2c824892797a08f8f7ccb4c2
[deliverable/linux.git] / drivers / scsi / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include <asm/io.h>
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "1.3"
52
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_CMD_SLOT_SZ = 32 * 32,
60 AHCI_RX_FIS_SZ = 256,
61 AHCI_CMD_TBL_HDR = 0x80,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
65 AHCI_RX_FIS_SZ,
66 AHCI_IRQ_ON_SG = (1 << 31),
67 AHCI_CMD_ATAPI = (1 << 5),
68 AHCI_CMD_WRITE = (1 << 6),
69 AHCI_CMD_PREFETCH = (1 << 7),
70 AHCI_CMD_RESET = (1 << 8),
71 AHCI_CMD_CLR_BUSY = (1 << 10),
72
73 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
74
75 board_ahci = 0,
76
77 /* global controller registers */
78 HOST_CAP = 0x00, /* host capabilities */
79 HOST_CTL = 0x04, /* global host control */
80 HOST_IRQ_STAT = 0x08, /* interrupt status */
81 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
82 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
83
84 /* HOST_CTL bits */
85 HOST_RESET = (1 << 0), /* reset controller; self-clear */
86 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
87 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
88
89 /* HOST_CAP bits */
90 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
91 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
92
93 /* registers for each SATA port */
94 PORT_LST_ADDR = 0x00, /* command list DMA addr */
95 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
96 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
97 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
98 PORT_IRQ_STAT = 0x10, /* interrupt status */
99 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
100 PORT_CMD = 0x18, /* port command */
101 PORT_TFDATA = 0x20, /* taskfile data */
102 PORT_SIG = 0x24, /* device TF signature */
103 PORT_CMD_ISSUE = 0x38, /* command issue */
104 PORT_SCR = 0x28, /* SATA phy register block */
105 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
106 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
107 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
108 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
109
110 /* PORT_IRQ_{STAT,MASK} bits */
111 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
112 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
113 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
114 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
115 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
116 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
117 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
118 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
119
120 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
121 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
122 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
123 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
124 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
125 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
126 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
127 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
128 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
129
130 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
131 PORT_IRQ_HBUS_ERR |
132 PORT_IRQ_HBUS_DATA_ERR |
133 PORT_IRQ_IF_ERR,
134 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
135 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
136 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
137 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
138 PORT_IRQ_D2H_REG_FIS,
139
140 /* PORT_CMD bits */
141 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
142 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
143 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
144 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
145 PORT_CMD_CLO = (1 << 3), /* Command list override */
146 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
147 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
148 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
149
150 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
151 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
152 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
153
154 /* hpriv->flags bits */
155 AHCI_FLAG_MSI = (1 << 0),
156 };
157
158 struct ahci_cmd_hdr {
159 u32 opts;
160 u32 status;
161 u32 tbl_addr;
162 u32 tbl_addr_hi;
163 u32 reserved[4];
164 };
165
166 struct ahci_sg {
167 u32 addr;
168 u32 addr_hi;
169 u32 reserved;
170 u32 flags_size;
171 };
172
173 struct ahci_host_priv {
174 unsigned long flags;
175 u32 cap; /* cache of HOST_CAP register */
176 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
177 };
178
179 struct ahci_port_priv {
180 struct ahci_cmd_hdr *cmd_slot;
181 dma_addr_t cmd_slot_dma;
182 void *cmd_tbl;
183 dma_addr_t cmd_tbl_dma;
184 struct ahci_sg *cmd_tbl_sg;
185 void *rx_fis;
186 dma_addr_t rx_fis_dma;
187 };
188
189 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
190 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
191 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
192 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
193 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
194 static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes);
195 static void ahci_irq_clear(struct ata_port *ap);
196 static void ahci_eng_timeout(struct ata_port *ap);
197 static int ahci_port_start(struct ata_port *ap);
198 static void ahci_port_stop(struct ata_port *ap);
199 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
200 static void ahci_qc_prep(struct ata_queued_cmd *qc);
201 static u8 ahci_check_status(struct ata_port *ap);
202 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
203 static void ahci_remove_one (struct pci_dev *pdev);
204
205 static struct scsi_host_template ahci_sht = {
206 .module = THIS_MODULE,
207 .name = DRV_NAME,
208 .ioctl = ata_scsi_ioctl,
209 .queuecommand = ata_scsi_queuecmd,
210 .can_queue = ATA_DEF_QUEUE,
211 .this_id = ATA_SHT_THIS_ID,
212 .sg_tablesize = AHCI_MAX_SG,
213 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
214 .emulated = ATA_SHT_EMULATED,
215 .use_clustering = AHCI_USE_CLUSTERING,
216 .proc_name = DRV_NAME,
217 .dma_boundary = AHCI_DMA_BOUNDARY,
218 .slave_configure = ata_scsi_slave_config,
219 .bios_param = ata_std_bios_param,
220 };
221
222 static const struct ata_port_operations ahci_ops = {
223 .port_disable = ata_port_disable,
224
225 .check_status = ahci_check_status,
226 .check_altstatus = ahci_check_status,
227 .dev_select = ata_noop_dev_select,
228
229 .tf_read = ahci_tf_read,
230
231 .probe_reset = ahci_probe_reset,
232
233 .qc_prep = ahci_qc_prep,
234 .qc_issue = ahci_qc_issue,
235
236 .eng_timeout = ahci_eng_timeout,
237
238 .irq_handler = ahci_interrupt,
239 .irq_clear = ahci_irq_clear,
240
241 .scr_read = ahci_scr_read,
242 .scr_write = ahci_scr_write,
243
244 .port_start = ahci_port_start,
245 .port_stop = ahci_port_stop,
246 };
247
248 static const struct ata_port_info ahci_port_info[] = {
249 /* board_ahci */
250 {
251 .sht = &ahci_sht,
252 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
253 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
254 .pio_mask = 0x1f, /* pio0-4 */
255 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
256 .port_ops = &ahci_ops,
257 },
258 };
259
260 static const struct pci_device_id ahci_pci_tbl[] = {
261 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
262 board_ahci }, /* ICH6 */
263 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
264 board_ahci }, /* ICH6M */
265 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
266 board_ahci }, /* ICH7 */
267 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
268 board_ahci }, /* ICH7M */
269 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
270 board_ahci }, /* ICH7R */
271 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
272 board_ahci }, /* ULi M5288 */
273 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
274 board_ahci }, /* ESB2 */
275 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
276 board_ahci }, /* ESB2 */
277 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
278 board_ahci }, /* ESB2 */
279 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
280 board_ahci }, /* ICH7-M DH */
281 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
282 board_ahci }, /* ICH8 */
283 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
284 board_ahci }, /* ICH8 */
285 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
286 board_ahci }, /* ICH8 */
287 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
288 board_ahci }, /* ICH8M */
289 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
290 board_ahci }, /* ICH8M */
291 { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
292 board_ahci }, /* JMicron JMB360 */
293 { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
294 board_ahci }, /* JMicron JMB363 */
295 { PCI_VENDOR_ID_ATI, 0x4380, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
296 board_ahci }, /* ATI SB600 non-raid */
297 { PCI_VENDOR_ID_ATI, 0x4381, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
298 board_ahci }, /* ATI SB600 raid */
299 { } /* terminate list */
300 };
301
302
303 static struct pci_driver ahci_pci_driver = {
304 .name = DRV_NAME,
305 .id_table = ahci_pci_tbl,
306 .probe = ahci_init_one,
307 .remove = ahci_remove_one,
308 };
309
310
311 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
312 {
313 return base + 0x100 + (port * 0x80);
314 }
315
316 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
317 {
318 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
319 }
320
321 static int ahci_port_start(struct ata_port *ap)
322 {
323 struct device *dev = ap->host_set->dev;
324 struct ahci_host_priv *hpriv = ap->host_set->private_data;
325 struct ahci_port_priv *pp;
326 void __iomem *mmio = ap->host_set->mmio_base;
327 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
328 void *mem;
329 dma_addr_t mem_dma;
330 int rc;
331
332 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
333 if (!pp)
334 return -ENOMEM;
335 memset(pp, 0, sizeof(*pp));
336
337 rc = ata_pad_alloc(ap, dev);
338 if (rc) {
339 kfree(pp);
340 return rc;
341 }
342
343 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
344 if (!mem) {
345 ata_pad_free(ap, dev);
346 kfree(pp);
347 return -ENOMEM;
348 }
349 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
350
351 /*
352 * First item in chunk of DMA memory: 32-slot command table,
353 * 32 bytes each in size
354 */
355 pp->cmd_slot = mem;
356 pp->cmd_slot_dma = mem_dma;
357
358 mem += AHCI_CMD_SLOT_SZ;
359 mem_dma += AHCI_CMD_SLOT_SZ;
360
361 /*
362 * Second item: Received-FIS area
363 */
364 pp->rx_fis = mem;
365 pp->rx_fis_dma = mem_dma;
366
367 mem += AHCI_RX_FIS_SZ;
368 mem_dma += AHCI_RX_FIS_SZ;
369
370 /*
371 * Third item: data area for storing a single command
372 * and its scatter-gather table
373 */
374 pp->cmd_tbl = mem;
375 pp->cmd_tbl_dma = mem_dma;
376
377 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
378
379 ap->private_data = pp;
380
381 if (hpriv->cap & HOST_CAP_64)
382 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
383 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
384 readl(port_mmio + PORT_LST_ADDR); /* flush */
385
386 if (hpriv->cap & HOST_CAP_64)
387 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
388 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
389 readl(port_mmio + PORT_FIS_ADDR); /* flush */
390
391 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
392 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
393 PORT_CMD_START, port_mmio + PORT_CMD);
394 readl(port_mmio + PORT_CMD); /* flush */
395
396 return 0;
397 }
398
399
400 static void ahci_port_stop(struct ata_port *ap)
401 {
402 struct device *dev = ap->host_set->dev;
403 struct ahci_port_priv *pp = ap->private_data;
404 void __iomem *mmio = ap->host_set->mmio_base;
405 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
406 u32 tmp;
407
408 tmp = readl(port_mmio + PORT_CMD);
409 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
410 writel(tmp, port_mmio + PORT_CMD);
411 readl(port_mmio + PORT_CMD); /* flush */
412
413 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
414 * this is slightly incorrect.
415 */
416 msleep(500);
417
418 ap->private_data = NULL;
419 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
420 pp->cmd_slot, pp->cmd_slot_dma);
421 ata_pad_free(ap, dev);
422 kfree(pp);
423 }
424
425 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
426 {
427 unsigned int sc_reg;
428
429 switch (sc_reg_in) {
430 case SCR_STATUS: sc_reg = 0; break;
431 case SCR_CONTROL: sc_reg = 1; break;
432 case SCR_ERROR: sc_reg = 2; break;
433 case SCR_ACTIVE: sc_reg = 3; break;
434 default:
435 return 0xffffffffU;
436 }
437
438 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
439 }
440
441
442 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
443 u32 val)
444 {
445 unsigned int sc_reg;
446
447 switch (sc_reg_in) {
448 case SCR_STATUS: sc_reg = 0; break;
449 case SCR_CONTROL: sc_reg = 1; break;
450 case SCR_ERROR: sc_reg = 2; break;
451 case SCR_ACTIVE: sc_reg = 3; break;
452 default:
453 return;
454 }
455
456 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
457 }
458
459 static int ahci_stop_engine(struct ata_port *ap)
460 {
461 void __iomem *mmio = ap->host_set->mmio_base;
462 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
463 int work;
464 u32 tmp;
465
466 tmp = readl(port_mmio + PORT_CMD);
467 tmp &= ~PORT_CMD_START;
468 writel(tmp, port_mmio + PORT_CMD);
469
470 /* wait for engine to stop. TODO: this could be
471 * as long as 500 msec
472 */
473 work = 1000;
474 while (work-- > 0) {
475 tmp = readl(port_mmio + PORT_CMD);
476 if ((tmp & PORT_CMD_LIST_ON) == 0)
477 return 0;
478 udelay(10);
479 }
480
481 return -EIO;
482 }
483
484 static void ahci_start_engine(struct ata_port *ap)
485 {
486 void __iomem *mmio = ap->host_set->mmio_base;
487 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
488 u32 tmp;
489
490 tmp = readl(port_mmio + PORT_CMD);
491 tmp |= PORT_CMD_START;
492 writel(tmp, port_mmio + PORT_CMD);
493 readl(port_mmio + PORT_CMD); /* flush */
494 }
495
496 static unsigned int ahci_dev_classify(struct ata_port *ap)
497 {
498 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
499 struct ata_taskfile tf;
500 u32 tmp;
501
502 tmp = readl(port_mmio + PORT_SIG);
503 tf.lbah = (tmp >> 24) & 0xff;
504 tf.lbam = (tmp >> 16) & 0xff;
505 tf.lbal = (tmp >> 8) & 0xff;
506 tf.nsect = (tmp) & 0xff;
507
508 return ata_dev_classify(&tf);
509 }
510
511 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, u32 opts)
512 {
513 pp->cmd_slot[0].opts = cpu_to_le32(opts);
514 pp->cmd_slot[0].status = 0;
515 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
516 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
517 }
518
519 static int ahci_poll_register(void __iomem *reg, u32 mask, u32 val,
520 unsigned long interval_msec,
521 unsigned long timeout_msec)
522 {
523 unsigned long timeout;
524 u32 tmp;
525
526 timeout = jiffies + (timeout_msec * HZ) / 1000;
527 do {
528 tmp = readl(reg);
529 if ((tmp & mask) == val)
530 return 0;
531 msleep(interval_msec);
532 } while (time_before(jiffies, timeout));
533
534 return -1;
535 }
536
537 static int ahci_softreset(struct ata_port *ap, int verbose, unsigned int *class)
538 {
539 struct ahci_host_priv *hpriv = ap->host_set->private_data;
540 struct ahci_port_priv *pp = ap->private_data;
541 void __iomem *mmio = ap->host_set->mmio_base;
542 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
543 const u32 cmd_fis_len = 5; /* five dwords */
544 const char *reason = NULL;
545 struct ata_taskfile tf;
546 u8 *fis;
547 int rc;
548
549 DPRINTK("ENTER\n");
550
551 if (!sata_dev_present(ap)) {
552 DPRINTK("PHY reports no device\n");
553 *class = ATA_DEV_NONE;
554 return 0;
555 }
556
557 /* prepare for SRST (AHCI-1.1 10.4.1) */
558 rc = ahci_stop_engine(ap);
559 if (rc) {
560 reason = "failed to stop engine";
561 goto fail_restart;
562 }
563
564 /* check BUSY/DRQ, perform Command List Override if necessary */
565 ahci_tf_read(ap, &tf);
566 if (tf.command & (ATA_BUSY | ATA_DRQ)) {
567 u32 tmp;
568
569 if (!(hpriv->cap & HOST_CAP_CLO)) {
570 rc = -EIO;
571 reason = "port busy but no CLO";
572 goto fail_restart;
573 }
574
575 tmp = readl(port_mmio + PORT_CMD);
576 tmp |= PORT_CMD_CLO;
577 writel(tmp, port_mmio + PORT_CMD);
578 readl(port_mmio + PORT_CMD); /* flush */
579
580 if (ahci_poll_register(port_mmio + PORT_CMD, PORT_CMD_CLO, 0x0,
581 1, 500)) {
582 rc = -EIO;
583 reason = "CLO failed";
584 goto fail_restart;
585 }
586 }
587
588 /* restart engine */
589 ahci_start_engine(ap);
590
591 ata_tf_init(ap, &tf, 0);
592 fis = pp->cmd_tbl;
593
594 /* issue the first D2H Register FIS */
595 ahci_fill_cmd_slot(pp, cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
596
597 tf.ctl |= ATA_SRST;
598 ata_tf_to_fis(&tf, fis, 0);
599 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
600
601 writel(1, port_mmio + PORT_CMD_ISSUE);
602 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
603
604 if (ahci_poll_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x0, 1, 500)) {
605 rc = -EIO;
606 reason = "1st FIS failed";
607 goto fail;
608 }
609
610 /* spec says at least 5us, but be generous and sleep for 1ms */
611 msleep(1);
612
613 /* issue the second D2H Register FIS */
614 ahci_fill_cmd_slot(pp, cmd_fis_len);
615
616 tf.ctl &= ~ATA_SRST;
617 ata_tf_to_fis(&tf, fis, 0);
618 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
619
620 writel(1, port_mmio + PORT_CMD_ISSUE);
621 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
622
623 /* spec mandates ">= 2ms" before checking status.
624 * We wait 150ms, because that was the magic delay used for
625 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
626 * between when the ATA command register is written, and then
627 * status is checked. Because waiting for "a while" before
628 * checking status is fine, post SRST, we perform this magic
629 * delay here as well.
630 */
631 msleep(150);
632
633 *class = ATA_DEV_NONE;
634 if (sata_dev_present(ap)) {
635 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
636 rc = -EIO;
637 reason = "device not ready";
638 goto fail;
639 }
640 *class = ahci_dev_classify(ap);
641 }
642
643 DPRINTK("EXIT, class=%u\n", *class);
644 return 0;
645
646 fail_restart:
647 ahci_start_engine(ap);
648 fail:
649 if (verbose)
650 printk(KERN_ERR "ata%u: softreset failed (%s)\n",
651 ap->id, reason);
652 else
653 DPRINTK("EXIT, rc=%d reason=\"%s\"\n", rc, reason);
654 return rc;
655 }
656
657 static int ahci_hardreset(struct ata_port *ap, int verbose, unsigned int *class)
658 {
659 int rc;
660
661 DPRINTK("ENTER\n");
662
663 ahci_stop_engine(ap);
664 rc = sata_std_hardreset(ap, verbose, class);
665 ahci_start_engine(ap);
666
667 if (rc == 0)
668 *class = ahci_dev_classify(ap);
669 if (*class == ATA_DEV_UNKNOWN)
670 *class = ATA_DEV_NONE;
671
672 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
673 return rc;
674 }
675
676 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
677 {
678 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
679 u32 new_tmp, tmp;
680
681 ata_std_postreset(ap, class);
682
683 /* Make sure port's ATAPI bit is set appropriately */
684 new_tmp = tmp = readl(port_mmio + PORT_CMD);
685 if (*class == ATA_DEV_ATAPI)
686 new_tmp |= PORT_CMD_ATAPI;
687 else
688 new_tmp &= ~PORT_CMD_ATAPI;
689 if (new_tmp != tmp) {
690 writel(new_tmp, port_mmio + PORT_CMD);
691 readl(port_mmio + PORT_CMD); /* flush */
692 }
693 }
694
695 static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes)
696 {
697 return ata_drive_probe_reset(ap, ata_std_probeinit,
698 ahci_softreset, ahci_hardreset,
699 ahci_postreset, classes);
700 }
701
702 static u8 ahci_check_status(struct ata_port *ap)
703 {
704 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
705
706 return readl(mmio + PORT_TFDATA) & 0xFF;
707 }
708
709 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
710 {
711 struct ahci_port_priv *pp = ap->private_data;
712 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
713
714 ata_tf_from_fis(d2h_fis, tf);
715 }
716
717 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
718 {
719 struct ahci_port_priv *pp = qc->ap->private_data;
720 struct scatterlist *sg;
721 struct ahci_sg *ahci_sg;
722 unsigned int n_sg = 0;
723
724 VPRINTK("ENTER\n");
725
726 /*
727 * Next, the S/G list.
728 */
729 ahci_sg = pp->cmd_tbl_sg;
730 ata_for_each_sg(sg, qc) {
731 dma_addr_t addr = sg_dma_address(sg);
732 u32 sg_len = sg_dma_len(sg);
733
734 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
735 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
736 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
737
738 ahci_sg++;
739 n_sg++;
740 }
741
742 return n_sg;
743 }
744
745 static void ahci_qc_prep(struct ata_queued_cmd *qc)
746 {
747 struct ata_port *ap = qc->ap;
748 struct ahci_port_priv *pp = ap->private_data;
749 int is_atapi = is_atapi_taskfile(&qc->tf);
750 u32 opts;
751 const u32 cmd_fis_len = 5; /* five dwords */
752 unsigned int n_elem;
753
754 /*
755 * Fill in command table information. First, the header,
756 * a SATA Register - Host to Device command FIS.
757 */
758 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
759 if (is_atapi) {
760 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
761 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb,
762 qc->dev->cdb_len);
763 }
764
765 n_elem = 0;
766 if (qc->flags & ATA_QCFLAG_DMAMAP)
767 n_elem = ahci_fill_sg(qc);
768
769 /*
770 * Fill in command slot information.
771 */
772 opts = cmd_fis_len | n_elem << 16;
773 if (qc->tf.flags & ATA_TFLAG_WRITE)
774 opts |= AHCI_CMD_WRITE;
775 if (is_atapi)
776 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
777
778 ahci_fill_cmd_slot(pp, opts);
779 }
780
781 static void ahci_restart_port(struct ata_port *ap, u32 irq_stat)
782 {
783 void __iomem *mmio = ap->host_set->mmio_base;
784 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
785 u32 tmp;
786
787 if ((ap->device[0].class != ATA_DEV_ATAPI) ||
788 ((irq_stat & PORT_IRQ_TF_ERR) == 0))
789 printk(KERN_WARNING "ata%u: port reset, "
790 "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n",
791 ap->id,
792 irq_stat,
793 readl(mmio + HOST_IRQ_STAT),
794 readl(port_mmio + PORT_IRQ_STAT),
795 readl(port_mmio + PORT_CMD),
796 readl(port_mmio + PORT_TFDATA),
797 readl(port_mmio + PORT_SCR_STAT),
798 readl(port_mmio + PORT_SCR_ERR));
799
800 /* stop DMA */
801 ahci_stop_engine(ap);
802
803 /* clear SATA phy error, if any */
804 tmp = readl(port_mmio + PORT_SCR_ERR);
805 writel(tmp, port_mmio + PORT_SCR_ERR);
806
807 /* if DRQ/BSY is set, device needs to be reset.
808 * if so, issue COMRESET
809 */
810 tmp = readl(port_mmio + PORT_TFDATA);
811 if (tmp & (ATA_BUSY | ATA_DRQ)) {
812 writel(0x301, port_mmio + PORT_SCR_CTL);
813 readl(port_mmio + PORT_SCR_CTL); /* flush */
814 udelay(10);
815 writel(0x300, port_mmio + PORT_SCR_CTL);
816 readl(port_mmio + PORT_SCR_CTL); /* flush */
817 }
818
819 /* re-start DMA */
820 ahci_start_engine(ap);
821 }
822
823 static void ahci_eng_timeout(struct ata_port *ap)
824 {
825 struct ata_host_set *host_set = ap->host_set;
826 void __iomem *mmio = host_set->mmio_base;
827 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
828 struct ata_queued_cmd *qc;
829 unsigned long flags;
830
831 printk(KERN_WARNING "ata%u: handling error/timeout\n", ap->id);
832
833 spin_lock_irqsave(&host_set->lock, flags);
834
835 ahci_restart_port(ap, readl(port_mmio + PORT_IRQ_STAT));
836 qc = ata_qc_from_tag(ap, ap->active_tag);
837 qc->err_mask |= AC_ERR_TIMEOUT;
838
839 spin_unlock_irqrestore(&host_set->lock, flags);
840
841 ata_eh_qc_complete(qc);
842 }
843
844 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
845 {
846 void __iomem *mmio = ap->host_set->mmio_base;
847 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
848 u32 status, serr, ci;
849
850 serr = readl(port_mmio + PORT_SCR_ERR);
851 writel(serr, port_mmio + PORT_SCR_ERR);
852
853 status = readl(port_mmio + PORT_IRQ_STAT);
854 writel(status, port_mmio + PORT_IRQ_STAT);
855
856 ci = readl(port_mmio + PORT_CMD_ISSUE);
857 if (likely((ci & 0x1) == 0)) {
858 if (qc) {
859 WARN_ON(qc->err_mask);
860 ata_qc_complete(qc);
861 qc = NULL;
862 }
863 }
864
865 if (status & PORT_IRQ_FATAL) {
866 unsigned int err_mask;
867 if (status & PORT_IRQ_TF_ERR)
868 err_mask = AC_ERR_DEV;
869 else if (status & PORT_IRQ_IF_ERR)
870 err_mask = AC_ERR_ATA_BUS;
871 else
872 err_mask = AC_ERR_HOST_BUS;
873
874 /* command processing has stopped due to error; restart */
875 ahci_restart_port(ap, status);
876
877 if (qc) {
878 qc->err_mask |= err_mask;
879 ata_qc_complete(qc);
880 }
881 }
882
883 return 1;
884 }
885
886 static void ahci_irq_clear(struct ata_port *ap)
887 {
888 /* TODO */
889 }
890
891 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
892 {
893 struct ata_host_set *host_set = dev_instance;
894 struct ahci_host_priv *hpriv;
895 unsigned int i, handled = 0;
896 void __iomem *mmio;
897 u32 irq_stat, irq_ack = 0;
898
899 VPRINTK("ENTER\n");
900
901 hpriv = host_set->private_data;
902 mmio = host_set->mmio_base;
903
904 /* sigh. 0xffffffff is a valid return from h/w */
905 irq_stat = readl(mmio + HOST_IRQ_STAT);
906 irq_stat &= hpriv->port_map;
907 if (!irq_stat)
908 return IRQ_NONE;
909
910 spin_lock(&host_set->lock);
911
912 for (i = 0; i < host_set->n_ports; i++) {
913 struct ata_port *ap;
914
915 if (!(irq_stat & (1 << i)))
916 continue;
917
918 ap = host_set->ports[i];
919 if (ap) {
920 struct ata_queued_cmd *qc;
921 qc = ata_qc_from_tag(ap, ap->active_tag);
922 if (!ahci_host_intr(ap, qc))
923 if (ata_ratelimit())
924 dev_printk(KERN_WARNING, host_set->dev,
925 "unhandled interrupt on port %u\n",
926 i);
927
928 VPRINTK("port %u\n", i);
929 } else {
930 VPRINTK("port %u (no irq)\n", i);
931 if (ata_ratelimit())
932 dev_printk(KERN_WARNING, host_set->dev,
933 "interrupt on disabled port %u\n", i);
934 }
935
936 irq_ack |= (1 << i);
937 }
938
939 if (irq_ack) {
940 writel(irq_ack, mmio + HOST_IRQ_STAT);
941 handled = 1;
942 }
943
944 spin_unlock(&host_set->lock);
945
946 VPRINTK("EXIT\n");
947
948 return IRQ_RETVAL(handled);
949 }
950
951 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
952 {
953 struct ata_port *ap = qc->ap;
954 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
955
956 writel(1, port_mmio + PORT_CMD_ISSUE);
957 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
958
959 return 0;
960 }
961
962 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
963 unsigned int port_idx)
964 {
965 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
966 base = ahci_port_base_ul(base, port_idx);
967 VPRINTK("base now==0x%lx\n", base);
968
969 port->cmd_addr = base;
970 port->scr_addr = base + PORT_SCR;
971
972 VPRINTK("EXIT\n");
973 }
974
975 static int ahci_host_init(struct ata_probe_ent *probe_ent)
976 {
977 struct ahci_host_priv *hpriv = probe_ent->private_data;
978 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
979 void __iomem *mmio = probe_ent->mmio_base;
980 u32 tmp, cap_save;
981 unsigned int i, j, using_dac;
982 int rc;
983 void __iomem *port_mmio;
984
985 cap_save = readl(mmio + HOST_CAP);
986 cap_save &= ( (1<<28) | (1<<17) );
987 cap_save |= (1 << 27);
988
989 /* global controller reset */
990 tmp = readl(mmio + HOST_CTL);
991 if ((tmp & HOST_RESET) == 0) {
992 writel(tmp | HOST_RESET, mmio + HOST_CTL);
993 readl(mmio + HOST_CTL); /* flush */
994 }
995
996 /* reset must complete within 1 second, or
997 * the hardware should be considered fried.
998 */
999 ssleep(1);
1000
1001 tmp = readl(mmio + HOST_CTL);
1002 if (tmp & HOST_RESET) {
1003 dev_printk(KERN_ERR, &pdev->dev,
1004 "controller reset failed (0x%x)\n", tmp);
1005 return -EIO;
1006 }
1007
1008 writel(HOST_AHCI_EN, mmio + HOST_CTL);
1009 (void) readl(mmio + HOST_CTL); /* flush */
1010 writel(cap_save, mmio + HOST_CAP);
1011 writel(0xf, mmio + HOST_PORTS_IMPL);
1012 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
1013
1014 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1015 u16 tmp16;
1016
1017 pci_read_config_word(pdev, 0x92, &tmp16);
1018 tmp16 |= 0xf;
1019 pci_write_config_word(pdev, 0x92, tmp16);
1020 }
1021
1022 hpriv->cap = readl(mmio + HOST_CAP);
1023 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1024 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1025
1026 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1027 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1028
1029 using_dac = hpriv->cap & HOST_CAP_64;
1030 if (using_dac &&
1031 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1032 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1033 if (rc) {
1034 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1035 if (rc) {
1036 dev_printk(KERN_ERR, &pdev->dev,
1037 "64-bit DMA enable failed\n");
1038 return rc;
1039 }
1040 }
1041 } else {
1042 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1043 if (rc) {
1044 dev_printk(KERN_ERR, &pdev->dev,
1045 "32-bit DMA enable failed\n");
1046 return rc;
1047 }
1048 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1049 if (rc) {
1050 dev_printk(KERN_ERR, &pdev->dev,
1051 "32-bit consistent DMA enable failed\n");
1052 return rc;
1053 }
1054 }
1055
1056 for (i = 0; i < probe_ent->n_ports; i++) {
1057 #if 0 /* BIOSen initialize this incorrectly */
1058 if (!(hpriv->port_map & (1 << i)))
1059 continue;
1060 #endif
1061
1062 port_mmio = ahci_port_base(mmio, i);
1063 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
1064
1065 ahci_setup_port(&probe_ent->port[i],
1066 (unsigned long) mmio, i);
1067
1068 /* make sure port is not active */
1069 tmp = readl(port_mmio + PORT_CMD);
1070 VPRINTK("PORT_CMD 0x%x\n", tmp);
1071 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1072 PORT_CMD_FIS_RX | PORT_CMD_START)) {
1073 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1074 PORT_CMD_FIS_RX | PORT_CMD_START);
1075 writel(tmp, port_mmio + PORT_CMD);
1076 readl(port_mmio + PORT_CMD); /* flush */
1077
1078 /* spec says 500 msecs for each bit, so
1079 * this is slightly incorrect.
1080 */
1081 msleep(500);
1082 }
1083
1084 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
1085
1086 j = 0;
1087 while (j < 100) {
1088 msleep(10);
1089 tmp = readl(port_mmio + PORT_SCR_STAT);
1090 if ((tmp & 0xf) == 0x3)
1091 break;
1092 j++;
1093 }
1094
1095 tmp = readl(port_mmio + PORT_SCR_ERR);
1096 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1097 writel(tmp, port_mmio + PORT_SCR_ERR);
1098
1099 /* ack any pending irq events for this port */
1100 tmp = readl(port_mmio + PORT_IRQ_STAT);
1101 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1102 if (tmp)
1103 writel(tmp, port_mmio + PORT_IRQ_STAT);
1104
1105 writel(1 << i, mmio + HOST_IRQ_STAT);
1106
1107 /* set irq mask (enables interrupts) */
1108 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1109 }
1110
1111 tmp = readl(mmio + HOST_CTL);
1112 VPRINTK("HOST_CTL 0x%x\n", tmp);
1113 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1114 tmp = readl(mmio + HOST_CTL);
1115 VPRINTK("HOST_CTL 0x%x\n", tmp);
1116
1117 pci_set_master(pdev);
1118
1119 return 0;
1120 }
1121
1122 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1123 {
1124 struct ahci_host_priv *hpriv = probe_ent->private_data;
1125 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1126 void __iomem *mmio = probe_ent->mmio_base;
1127 u32 vers, cap, impl, speed;
1128 const char *speed_s;
1129 u16 cc;
1130 const char *scc_s;
1131
1132 vers = readl(mmio + HOST_VERSION);
1133 cap = hpriv->cap;
1134 impl = hpriv->port_map;
1135
1136 speed = (cap >> 20) & 0xf;
1137 if (speed == 1)
1138 speed_s = "1.5";
1139 else if (speed == 2)
1140 speed_s = "3";
1141 else
1142 speed_s = "?";
1143
1144 pci_read_config_word(pdev, 0x0a, &cc);
1145 if (cc == 0x0101)
1146 scc_s = "IDE";
1147 else if (cc == 0x0106)
1148 scc_s = "SATA";
1149 else if (cc == 0x0104)
1150 scc_s = "RAID";
1151 else
1152 scc_s = "unknown";
1153
1154 dev_printk(KERN_INFO, &pdev->dev,
1155 "AHCI %02x%02x.%02x%02x "
1156 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1157 ,
1158
1159 (vers >> 24) & 0xff,
1160 (vers >> 16) & 0xff,
1161 (vers >> 8) & 0xff,
1162 vers & 0xff,
1163
1164 ((cap >> 8) & 0x1f) + 1,
1165 (cap & 0x1f) + 1,
1166 speed_s,
1167 impl,
1168 scc_s);
1169
1170 dev_printk(KERN_INFO, &pdev->dev,
1171 "flags: "
1172 "%s%s%s%s%s%s"
1173 "%s%s%s%s%s%s%s\n"
1174 ,
1175
1176 cap & (1 << 31) ? "64bit " : "",
1177 cap & (1 << 30) ? "ncq " : "",
1178 cap & (1 << 28) ? "ilck " : "",
1179 cap & (1 << 27) ? "stag " : "",
1180 cap & (1 << 26) ? "pm " : "",
1181 cap & (1 << 25) ? "led " : "",
1182
1183 cap & (1 << 24) ? "clo " : "",
1184 cap & (1 << 19) ? "nz " : "",
1185 cap & (1 << 18) ? "only " : "",
1186 cap & (1 << 17) ? "pmp " : "",
1187 cap & (1 << 15) ? "pio " : "",
1188 cap & (1 << 14) ? "slum " : "",
1189 cap & (1 << 13) ? "part " : ""
1190 );
1191 }
1192
1193 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1194 {
1195 static int printed_version;
1196 struct ata_probe_ent *probe_ent = NULL;
1197 struct ahci_host_priv *hpriv;
1198 unsigned long base;
1199 void __iomem *mmio_base;
1200 unsigned int board_idx = (unsigned int) ent->driver_data;
1201 int have_msi, pci_dev_busy = 0;
1202 int rc;
1203
1204 VPRINTK("ENTER\n");
1205
1206 if (!printed_version++)
1207 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1208
1209 rc = pci_enable_device(pdev);
1210 if (rc)
1211 return rc;
1212
1213 rc = pci_request_regions(pdev, DRV_NAME);
1214 if (rc) {
1215 pci_dev_busy = 1;
1216 goto err_out;
1217 }
1218
1219 if (pci_enable_msi(pdev) == 0)
1220 have_msi = 1;
1221 else {
1222 pci_intx(pdev, 1);
1223 have_msi = 0;
1224 }
1225
1226 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1227 if (probe_ent == NULL) {
1228 rc = -ENOMEM;
1229 goto err_out_msi;
1230 }
1231
1232 memset(probe_ent, 0, sizeof(*probe_ent));
1233 probe_ent->dev = pci_dev_to_dev(pdev);
1234 INIT_LIST_HEAD(&probe_ent->node);
1235
1236 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1237 if (mmio_base == NULL) {
1238 rc = -ENOMEM;
1239 goto err_out_free_ent;
1240 }
1241 base = (unsigned long) mmio_base;
1242
1243 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1244 if (!hpriv) {
1245 rc = -ENOMEM;
1246 goto err_out_iounmap;
1247 }
1248 memset(hpriv, 0, sizeof(*hpriv));
1249
1250 probe_ent->sht = ahci_port_info[board_idx].sht;
1251 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1252 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1253 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1254 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1255
1256 probe_ent->irq = pdev->irq;
1257 probe_ent->irq_flags = SA_SHIRQ;
1258 probe_ent->mmio_base = mmio_base;
1259 probe_ent->private_data = hpriv;
1260
1261 if (have_msi)
1262 hpriv->flags |= AHCI_FLAG_MSI;
1263
1264 /* JMicron-specific fixup: make sure we're in AHCI mode */
1265 if (pdev->vendor == 0x197b)
1266 pci_write_config_byte(pdev, 0x41, 0xa1);
1267
1268 /* initialize adapter */
1269 rc = ahci_host_init(probe_ent);
1270 if (rc)
1271 goto err_out_hpriv;
1272
1273 ahci_print_info(probe_ent);
1274
1275 /* FIXME: check ata_device_add return value */
1276 ata_device_add(probe_ent);
1277 kfree(probe_ent);
1278
1279 return 0;
1280
1281 err_out_hpriv:
1282 kfree(hpriv);
1283 err_out_iounmap:
1284 pci_iounmap(pdev, mmio_base);
1285 err_out_free_ent:
1286 kfree(probe_ent);
1287 err_out_msi:
1288 if (have_msi)
1289 pci_disable_msi(pdev);
1290 else
1291 pci_intx(pdev, 0);
1292 pci_release_regions(pdev);
1293 err_out:
1294 if (!pci_dev_busy)
1295 pci_disable_device(pdev);
1296 return rc;
1297 }
1298
1299 static void ahci_remove_one (struct pci_dev *pdev)
1300 {
1301 struct device *dev = pci_dev_to_dev(pdev);
1302 struct ata_host_set *host_set = dev_get_drvdata(dev);
1303 struct ahci_host_priv *hpriv = host_set->private_data;
1304 struct ata_port *ap;
1305 unsigned int i;
1306 int have_msi;
1307
1308 for (i = 0; i < host_set->n_ports; i++) {
1309 ap = host_set->ports[i];
1310
1311 scsi_remove_host(ap->host);
1312 }
1313
1314 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1315 free_irq(host_set->irq, host_set);
1316
1317 for (i = 0; i < host_set->n_ports; i++) {
1318 ap = host_set->ports[i];
1319
1320 ata_scsi_release(ap->host);
1321 scsi_host_put(ap->host);
1322 }
1323
1324 kfree(hpriv);
1325 pci_iounmap(pdev, host_set->mmio_base);
1326 kfree(host_set);
1327
1328 if (have_msi)
1329 pci_disable_msi(pdev);
1330 else
1331 pci_intx(pdev, 0);
1332 pci_release_regions(pdev);
1333 pci_disable_device(pdev);
1334 dev_set_drvdata(dev, NULL);
1335 }
1336
1337 static int __init ahci_init(void)
1338 {
1339 return pci_module_init(&ahci_pci_driver);
1340 }
1341
1342 static void __exit ahci_exit(void)
1343 {
1344 pci_unregister_driver(&ahci_pci_driver);
1345 }
1346
1347
1348 MODULE_AUTHOR("Jeff Garzik");
1349 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1350 MODULE_LICENSE("GPL");
1351 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1352 MODULE_VERSION(DRV_VERSION);
1353
1354 module_init(ahci_init);
1355 module_exit(ahci_exit);
Linux kernel - Deliverables
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