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[deliverable/linux.git] / drivers / scsi / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include "scsi.h"
45 #include <scsi/scsi_host.h>
46 #include <linux/libata.h>
47 #include <asm/io.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "1.01"
51
52
53 enum {
54 AHCI_PCI_BAR = 5,
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 0,
58 AHCI_CMD_SLOT_SZ = 32 * 32,
59 AHCI_RX_FIS_SZ = 256,
60 AHCI_CMD_TBL_HDR = 0x80,
61 AHCI_CMD_TBL_CDB = 0x40,
62 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
63 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
64 AHCI_RX_FIS_SZ,
65 AHCI_IRQ_ON_SG = (1 << 31),
66 AHCI_CMD_ATAPI = (1 << 5),
67 AHCI_CMD_WRITE = (1 << 6),
68
69 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
70
71 board_ahci = 0,
72
73 /* global controller registers */
74 HOST_CAP = 0x00, /* host capabilities */
75 HOST_CTL = 0x04, /* global host control */
76 HOST_IRQ_STAT = 0x08, /* interrupt status */
77 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
78 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
79
80 /* HOST_CTL bits */
81 HOST_RESET = (1 << 0), /* reset controller; self-clear */
82 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
83 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
84
85 /* HOST_CAP bits */
86 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
87
88 /* registers for each SATA port */
89 PORT_LST_ADDR = 0x00, /* command list DMA addr */
90 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
91 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
92 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
93 PORT_IRQ_STAT = 0x10, /* interrupt status */
94 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
95 PORT_CMD = 0x18, /* port command */
96 PORT_TFDATA = 0x20, /* taskfile data */
97 PORT_SIG = 0x24, /* device TF signature */
98 PORT_CMD_ISSUE = 0x38, /* command issue */
99 PORT_SCR = 0x28, /* SATA phy register block */
100 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
101 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
102 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
103 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
104
105 /* PORT_IRQ_{STAT,MASK} bits */
106 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
107 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
108 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
109 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
110 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
111 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
112 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
113 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
114
115 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
116 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
117 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
118 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
119 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
120 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
121 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
122 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
123 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
124
125 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
126 PORT_IRQ_HBUS_ERR |
127 PORT_IRQ_HBUS_DATA_ERR |
128 PORT_IRQ_IF_ERR,
129 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
130 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
131 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
132 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
133 PORT_IRQ_D2H_REG_FIS,
134
135 /* PORT_CMD bits */
136 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
137 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
138 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
139 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
140 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
141 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
142
143 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
144 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
145 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
146
147 /* hpriv->flags bits */
148 AHCI_FLAG_MSI = (1 << 0),
149 };
150
151 struct ahci_cmd_hdr {
152 u32 opts;
153 u32 status;
154 u32 tbl_addr;
155 u32 tbl_addr_hi;
156 u32 reserved[4];
157 };
158
159 struct ahci_sg {
160 u32 addr;
161 u32 addr_hi;
162 u32 reserved;
163 u32 flags_size;
164 };
165
166 struct ahci_host_priv {
167 unsigned long flags;
168 u32 cap; /* cache of HOST_CAP register */
169 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
170 };
171
172 struct ahci_port_priv {
173 struct ahci_cmd_hdr *cmd_slot;
174 dma_addr_t cmd_slot_dma;
175 void *cmd_tbl;
176 dma_addr_t cmd_tbl_dma;
177 struct ahci_sg *cmd_tbl_sg;
178 void *rx_fis;
179 dma_addr_t rx_fis_dma;
180 };
181
182 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
183 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
184 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
185 static int ahci_qc_issue(struct ata_queued_cmd *qc);
186 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
187 static void ahci_phy_reset(struct ata_port *ap);
188 static void ahci_irq_clear(struct ata_port *ap);
189 static void ahci_eng_timeout(struct ata_port *ap);
190 static int ahci_port_start(struct ata_port *ap);
191 static void ahci_port_stop(struct ata_port *ap);
192 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
193 static void ahci_qc_prep(struct ata_queued_cmd *qc);
194 static u8 ahci_check_status(struct ata_port *ap);
195 static u8 ahci_check_err(struct ata_port *ap);
196 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
197 static void ahci_remove_one (struct pci_dev *pdev);
198
199 static Scsi_Host_Template ahci_sht = {
200 .module = THIS_MODULE,
201 .name = DRV_NAME,
202 .ioctl = ata_scsi_ioctl,
203 .queuecommand = ata_scsi_queuecmd,
204 .eh_strategy_handler = ata_scsi_error,
205 .can_queue = ATA_DEF_QUEUE,
206 .this_id = ATA_SHT_THIS_ID,
207 .sg_tablesize = AHCI_MAX_SG,
208 .max_sectors = ATA_MAX_SECTORS,
209 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
210 .emulated = ATA_SHT_EMULATED,
211 .use_clustering = AHCI_USE_CLUSTERING,
212 .proc_name = DRV_NAME,
213 .dma_boundary = AHCI_DMA_BOUNDARY,
214 .slave_configure = ata_scsi_slave_config,
215 .bios_param = ata_std_bios_param,
216 .ordered_flush = 1,
217 };
218
219 static struct ata_port_operations ahci_ops = {
220 .port_disable = ata_port_disable,
221
222 .check_status = ahci_check_status,
223 .check_altstatus = ahci_check_status,
224 .check_err = ahci_check_err,
225 .dev_select = ata_noop_dev_select,
226
227 .tf_read = ahci_tf_read,
228
229 .phy_reset = ahci_phy_reset,
230
231 .qc_prep = ahci_qc_prep,
232 .qc_issue = ahci_qc_issue,
233
234 .eng_timeout = ahci_eng_timeout,
235
236 .irq_handler = ahci_interrupt,
237 .irq_clear = ahci_irq_clear,
238
239 .scr_read = ahci_scr_read,
240 .scr_write = ahci_scr_write,
241
242 .port_start = ahci_port_start,
243 .port_stop = ahci_port_stop,
244 };
245
246 static struct ata_port_info ahci_port_info[] = {
247 /* board_ahci */
248 {
249 .sht = &ahci_sht,
250 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
251 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
252 ATA_FLAG_PIO_DMA,
253 .pio_mask = 0x1f, /* pio0-4 */
254 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
255 .port_ops = &ahci_ops,
256 },
257 };
258
259 static struct pci_device_id ahci_pci_tbl[] = {
260 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
261 board_ahci }, /* ICH6 */
262 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 board_ahci }, /* ICH6M */
264 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 board_ahci }, /* ICH7 */
266 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
267 board_ahci }, /* ICH7M */
268 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
269 board_ahci }, /* ICH7R */
270 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
271 board_ahci }, /* ULi M5288 */
272 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
273 board_ahci }, /* ESB2 */
274 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
275 board_ahci }, /* ESB2 */
276 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
277 board_ahci }, /* ESB2 */
278 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
279 board_ahci }, /* ICH7-M DH */
280 { } /* terminate list */
281 };
282
283
284 static struct pci_driver ahci_pci_driver = {
285 .name = DRV_NAME,
286 .id_table = ahci_pci_tbl,
287 .probe = ahci_init_one,
288 .remove = ahci_remove_one,
289 };
290
291
292 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
293 {
294 return base + 0x100 + (port * 0x80);
295 }
296
297 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
298 {
299 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
300 }
301
302 static int ahci_port_start(struct ata_port *ap)
303 {
304 struct device *dev = ap->host_set->dev;
305 struct ahci_host_priv *hpriv = ap->host_set->private_data;
306 struct ahci_port_priv *pp;
307 void __iomem *mmio = ap->host_set->mmio_base;
308 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
309 void *mem;
310 dma_addr_t mem_dma;
311
312 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
313 if (!pp)
314 return -ENOMEM;
315 memset(pp, 0, sizeof(*pp));
316
317 ap->pad = dma_alloc_coherent(dev, ATA_DMA_PAD_BUF_SZ, &ap->pad_dma, GFP_KERNEL);
318 if (!ap->pad) {
319 kfree(pp);
320 return -ENOMEM;
321 }
322
323 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
324 if (!mem) {
325 dma_free_coherent(dev, ATA_DMA_PAD_BUF_SZ, ap->pad, ap->pad_dma);
326 kfree(pp);
327 return -ENOMEM;
328 }
329 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
330
331 /*
332 * First item in chunk of DMA memory: 32-slot command table,
333 * 32 bytes each in size
334 */
335 pp->cmd_slot = mem;
336 pp->cmd_slot_dma = mem_dma;
337
338 mem += AHCI_CMD_SLOT_SZ;
339 mem_dma += AHCI_CMD_SLOT_SZ;
340
341 /*
342 * Second item: Received-FIS area
343 */
344 pp->rx_fis = mem;
345 pp->rx_fis_dma = mem_dma;
346
347 mem += AHCI_RX_FIS_SZ;
348 mem_dma += AHCI_RX_FIS_SZ;
349
350 /*
351 * Third item: data area for storing a single command
352 * and its scatter-gather table
353 */
354 pp->cmd_tbl = mem;
355 pp->cmd_tbl_dma = mem_dma;
356
357 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
358
359 ap->private_data = pp;
360
361 if (hpriv->cap & HOST_CAP_64)
362 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
363 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
364 readl(port_mmio + PORT_LST_ADDR); /* flush */
365
366 if (hpriv->cap & HOST_CAP_64)
367 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
368 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
369 readl(port_mmio + PORT_FIS_ADDR); /* flush */
370
371 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
372 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
373 PORT_CMD_START, port_mmio + PORT_CMD);
374 readl(port_mmio + PORT_CMD); /* flush */
375
376 return 0;
377 }
378
379
380 static void ahci_port_stop(struct ata_port *ap)
381 {
382 struct device *dev = ap->host_set->dev;
383 struct ahci_port_priv *pp = ap->private_data;
384 void __iomem *mmio = ap->host_set->mmio_base;
385 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
386 u32 tmp;
387
388 tmp = readl(port_mmio + PORT_CMD);
389 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
390 writel(tmp, port_mmio + PORT_CMD);
391 readl(port_mmio + PORT_CMD); /* flush */
392
393 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
394 * this is slightly incorrect.
395 */
396 msleep(500);
397
398 ap->private_data = NULL;
399 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
400 pp->cmd_slot, pp->cmd_slot_dma);
401 dma_free_coherent(dev, ATA_DMA_PAD_BUF_SZ, ap->pad, ap->pad_dma);
402 kfree(pp);
403 }
404
405 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
406 {
407 unsigned int sc_reg;
408
409 switch (sc_reg_in) {
410 case SCR_STATUS: sc_reg = 0; break;
411 case SCR_CONTROL: sc_reg = 1; break;
412 case SCR_ERROR: sc_reg = 2; break;
413 case SCR_ACTIVE: sc_reg = 3; break;
414 default:
415 return 0xffffffffU;
416 }
417
418 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
419 }
420
421
422 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
423 u32 val)
424 {
425 unsigned int sc_reg;
426
427 switch (sc_reg_in) {
428 case SCR_STATUS: sc_reg = 0; break;
429 case SCR_CONTROL: sc_reg = 1; break;
430 case SCR_ERROR: sc_reg = 2; break;
431 case SCR_ACTIVE: sc_reg = 3; break;
432 default:
433 return;
434 }
435
436 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
437 }
438
439 static void ahci_phy_reset(struct ata_port *ap)
440 {
441 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
442 struct ata_taskfile tf;
443 struct ata_device *dev = &ap->device[0];
444 u32 tmp;
445
446 __sata_phy_reset(ap);
447
448 if (ap->flags & ATA_FLAG_PORT_DISABLED)
449 return;
450
451 tmp = readl(port_mmio + PORT_SIG);
452 tf.lbah = (tmp >> 24) & 0xff;
453 tf.lbam = (tmp >> 16) & 0xff;
454 tf.lbal = (tmp >> 8) & 0xff;
455 tf.nsect = (tmp) & 0xff;
456
457 dev->class = ata_dev_classify(&tf);
458 if (!ata_dev_present(dev))
459 ata_port_disable(ap);
460 }
461
462 static u8 ahci_check_status(struct ata_port *ap)
463 {
464 void *mmio = (void *) ap->ioaddr.cmd_addr;
465
466 return readl(mmio + PORT_TFDATA) & 0xFF;
467 }
468
469 static u8 ahci_check_err(struct ata_port *ap)
470 {
471 void *mmio = (void *) ap->ioaddr.cmd_addr;
472
473 return (readl(mmio + PORT_TFDATA) >> 8) & 0xFF;
474 }
475
476 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
477 {
478 struct ahci_port_priv *pp = ap->private_data;
479 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
480
481 ata_tf_from_fis(d2h_fis, tf);
482 }
483
484 static void ahci_fill_sg(struct ata_queued_cmd *qc)
485 {
486 struct ahci_port_priv *pp = qc->ap->private_data;
487 struct scatterlist *sg;
488 struct ahci_sg *ahci_sg;
489
490 VPRINTK("ENTER\n");
491
492 /*
493 * Next, the S/G list.
494 */
495 ahci_sg = pp->cmd_tbl_sg;
496 ata_for_each_sg(sg, qc) {
497 dma_addr_t addr = sg_dma_address(sg);
498 u32 sg_len = sg_dma_len(sg);
499
500 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
501 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
502 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
503 ahci_sg++;
504 }
505 }
506
507 static void ahci_qc_prep(struct ata_queued_cmd *qc)
508 {
509 struct ata_port *ap = qc->ap;
510 struct ahci_port_priv *pp = ap->private_data;
511 u32 opts;
512 const u32 cmd_fis_len = 5; /* five dwords */
513
514 /*
515 * Fill in command slot information (currently only one slot,
516 * slot 0, is currently since we don't do queueing)
517 */
518
519 opts = (qc->n_elem << 16) | cmd_fis_len;
520 if (qc->tf.flags & ATA_TFLAG_WRITE)
521 opts |= AHCI_CMD_WRITE;
522 if (is_atapi_taskfile(&qc->tf))
523 opts |= AHCI_CMD_ATAPI;
524
525 pp->cmd_slot[0].opts = cpu_to_le32(opts);
526 pp->cmd_slot[0].status = 0;
527 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
528 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
529
530 /*
531 * Fill in command table information. First, the header,
532 * a SATA Register - Host to Device command FIS.
533 */
534 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
535 if (opts & AHCI_CMD_ATAPI) {
536 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
537 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
538 }
539
540 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
541 return;
542
543 ahci_fill_sg(qc);
544 }
545
546 static void ahci_intr_error(struct ata_port *ap, u32 irq_stat)
547 {
548 void __iomem *mmio = ap->host_set->mmio_base;
549 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
550 u32 tmp;
551 int work;
552
553 /* stop DMA */
554 tmp = readl(port_mmio + PORT_CMD);
555 tmp &= ~PORT_CMD_START;
556 writel(tmp, port_mmio + PORT_CMD);
557
558 /* wait for engine to stop. TODO: this could be
559 * as long as 500 msec
560 */
561 work = 1000;
562 while (work-- > 0) {
563 tmp = readl(port_mmio + PORT_CMD);
564 if ((tmp & PORT_CMD_LIST_ON) == 0)
565 break;
566 udelay(10);
567 }
568
569 /* clear SATA phy error, if any */
570 tmp = readl(port_mmio + PORT_SCR_ERR);
571 writel(tmp, port_mmio + PORT_SCR_ERR);
572
573 /* if DRQ/BSY is set, device needs to be reset.
574 * if so, issue COMRESET
575 */
576 tmp = readl(port_mmio + PORT_TFDATA);
577 if (tmp & (ATA_BUSY | ATA_DRQ)) {
578 writel(0x301, port_mmio + PORT_SCR_CTL);
579 readl(port_mmio + PORT_SCR_CTL); /* flush */
580 udelay(10);
581 writel(0x300, port_mmio + PORT_SCR_CTL);
582 readl(port_mmio + PORT_SCR_CTL); /* flush */
583 }
584
585 /* re-start DMA */
586 tmp = readl(port_mmio + PORT_CMD);
587 tmp |= PORT_CMD_START;
588 writel(tmp, port_mmio + PORT_CMD);
589 readl(port_mmio + PORT_CMD); /* flush */
590
591 printk(KERN_WARNING "ata%u: error occurred, port reset\n", ap->id);
592 }
593
594 static void ahci_eng_timeout(struct ata_port *ap)
595 {
596 struct ata_host_set *host_set = ap->host_set;
597 void __iomem *mmio = host_set->mmio_base;
598 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
599 struct ata_queued_cmd *qc;
600 unsigned long flags;
601
602 DPRINTK("ENTER\n");
603
604 spin_lock_irqsave(&host_set->lock, flags);
605
606 ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT));
607
608 qc = ata_qc_from_tag(ap, ap->active_tag);
609 if (!qc) {
610 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
611 ap->id);
612 } else {
613 /* hack alert! We cannot use the supplied completion
614 * function from inside the ->eh_strategy_handler() thread.
615 * libata is the only user of ->eh_strategy_handler() in
616 * any kernel, so the default scsi_done() assumes it is
617 * not being called from the SCSI EH.
618 */
619 qc->scsidone = scsi_finish_command;
620 ata_qc_complete(qc, ATA_ERR);
621 }
622
623 spin_unlock_irqrestore(&host_set->lock, flags);
624 }
625
626 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
627 {
628 void __iomem *mmio = ap->host_set->mmio_base;
629 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
630 u32 status, serr, ci;
631
632 serr = readl(port_mmio + PORT_SCR_ERR);
633 writel(serr, port_mmio + PORT_SCR_ERR);
634
635 status = readl(port_mmio + PORT_IRQ_STAT);
636 writel(status, port_mmio + PORT_IRQ_STAT);
637
638 ci = readl(port_mmio + PORT_CMD_ISSUE);
639 if (likely((ci & 0x1) == 0)) {
640 if (qc) {
641 ata_qc_complete(qc, 0);
642 qc = NULL;
643 }
644 }
645
646 if (status & PORT_IRQ_FATAL) {
647 ahci_intr_error(ap, status);
648 if (qc)
649 ata_qc_complete(qc, ATA_ERR);
650 }
651
652 return 1;
653 }
654
655 static void ahci_irq_clear(struct ata_port *ap)
656 {
657 /* TODO */
658 }
659
660 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
661 {
662 struct ata_host_set *host_set = dev_instance;
663 struct ahci_host_priv *hpriv;
664 unsigned int i, handled = 0;
665 void __iomem *mmio;
666 u32 irq_stat, irq_ack = 0;
667
668 VPRINTK("ENTER\n");
669
670 hpriv = host_set->private_data;
671 mmio = host_set->mmio_base;
672
673 /* sigh. 0xffffffff is a valid return from h/w */
674 irq_stat = readl(mmio + HOST_IRQ_STAT);
675 irq_stat &= hpriv->port_map;
676 if (!irq_stat)
677 return IRQ_NONE;
678
679 spin_lock(&host_set->lock);
680
681 for (i = 0; i < host_set->n_ports; i++) {
682 struct ata_port *ap;
683
684 if (!(irq_stat & (1 << i)))
685 continue;
686
687 ap = host_set->ports[i];
688 if (ap) {
689 struct ata_queued_cmd *qc;
690 qc = ata_qc_from_tag(ap, ap->active_tag);
691 if (!ahci_host_intr(ap, qc))
692 if (ata_ratelimit()) {
693 struct pci_dev *pdev =
694 to_pci_dev(ap->host_set->dev);
695 printk(KERN_WARNING
696 "ahci(%s): unhandled interrupt on port %u\n",
697 pci_name(pdev), i);
698 }
699
700 VPRINTK("port %u\n", i);
701 } else {
702 VPRINTK("port %u (no irq)\n", i);
703 if (ata_ratelimit()) {
704 struct pci_dev *pdev =
705 to_pci_dev(ap->host_set->dev);
706 printk(KERN_WARNING
707 "ahci(%s): interrupt on disabled port %u\n",
708 pci_name(pdev), i);
709 }
710 }
711
712 irq_ack |= (1 << i);
713 }
714
715 if (irq_ack) {
716 writel(irq_ack, mmio + HOST_IRQ_STAT);
717 handled = 1;
718 }
719
720 spin_unlock(&host_set->lock);
721
722 VPRINTK("EXIT\n");
723
724 return IRQ_RETVAL(handled);
725 }
726
727 static int ahci_qc_issue(struct ata_queued_cmd *qc)
728 {
729 struct ata_port *ap = qc->ap;
730 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
731
732 writel(1, port_mmio + PORT_CMD_ISSUE);
733 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
734
735 return 0;
736 }
737
738 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
739 unsigned int port_idx)
740 {
741 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
742 base = ahci_port_base_ul(base, port_idx);
743 VPRINTK("base now==0x%lx\n", base);
744
745 port->cmd_addr = base;
746 port->scr_addr = base + PORT_SCR;
747
748 VPRINTK("EXIT\n");
749 }
750
751 static int ahci_host_init(struct ata_probe_ent *probe_ent)
752 {
753 struct ahci_host_priv *hpriv = probe_ent->private_data;
754 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
755 void __iomem *mmio = probe_ent->mmio_base;
756 u32 tmp, cap_save;
757 u16 tmp16;
758 unsigned int i, j, using_dac;
759 int rc;
760 void __iomem *port_mmio;
761
762 cap_save = readl(mmio + HOST_CAP);
763 cap_save &= ( (1<<28) | (1<<17) );
764 cap_save |= (1 << 27);
765
766 /* global controller reset */
767 tmp = readl(mmio + HOST_CTL);
768 if ((tmp & HOST_RESET) == 0) {
769 writel(tmp | HOST_RESET, mmio + HOST_CTL);
770 readl(mmio + HOST_CTL); /* flush */
771 }
772
773 /* reset must complete within 1 second, or
774 * the hardware should be considered fried.
775 */
776 ssleep(1);
777
778 tmp = readl(mmio + HOST_CTL);
779 if (tmp & HOST_RESET) {
780 printk(KERN_ERR DRV_NAME "(%s): controller reset failed (0x%x)\n",
781 pci_name(pdev), tmp);
782 return -EIO;
783 }
784
785 writel(HOST_AHCI_EN, mmio + HOST_CTL);
786 (void) readl(mmio + HOST_CTL); /* flush */
787 writel(cap_save, mmio + HOST_CAP);
788 writel(0xf, mmio + HOST_PORTS_IMPL);
789 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
790
791 pci_read_config_word(pdev, 0x92, &tmp16);
792 tmp16 |= 0xf;
793 pci_write_config_word(pdev, 0x92, tmp16);
794
795 hpriv->cap = readl(mmio + HOST_CAP);
796 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
797 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
798
799 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
800 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
801
802 using_dac = hpriv->cap & HOST_CAP_64;
803 if (using_dac &&
804 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
805 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
806 if (rc) {
807 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
808 if (rc) {
809 printk(KERN_ERR DRV_NAME "(%s): 64-bit DMA enable failed\n",
810 pci_name(pdev));
811 return rc;
812 }
813 }
814 } else {
815 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
816 if (rc) {
817 printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",
818 pci_name(pdev));
819 return rc;
820 }
821 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
822 if (rc) {
823 printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",
824 pci_name(pdev));
825 return rc;
826 }
827 }
828
829 for (i = 0; i < probe_ent->n_ports; i++) {
830 #if 0 /* BIOSen initialize this incorrectly */
831 if (!(hpriv->port_map & (1 << i)))
832 continue;
833 #endif
834
835 port_mmio = ahci_port_base(mmio, i);
836 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
837
838 ahci_setup_port(&probe_ent->port[i],
839 (unsigned long) mmio, i);
840
841 /* make sure port is not active */
842 tmp = readl(port_mmio + PORT_CMD);
843 VPRINTK("PORT_CMD 0x%x\n", tmp);
844 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
845 PORT_CMD_FIS_RX | PORT_CMD_START)) {
846 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
847 PORT_CMD_FIS_RX | PORT_CMD_START);
848 writel(tmp, port_mmio + PORT_CMD);
849 readl(port_mmio + PORT_CMD); /* flush */
850
851 /* spec says 500 msecs for each bit, so
852 * this is slightly incorrect.
853 */
854 msleep(500);
855 }
856
857 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
858
859 j = 0;
860 while (j < 100) {
861 msleep(10);
862 tmp = readl(port_mmio + PORT_SCR_STAT);
863 if ((tmp & 0xf) == 0x3)
864 break;
865 j++;
866 }
867
868 tmp = readl(port_mmio + PORT_SCR_ERR);
869 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
870 writel(tmp, port_mmio + PORT_SCR_ERR);
871
872 /* ack any pending irq events for this port */
873 tmp = readl(port_mmio + PORT_IRQ_STAT);
874 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
875 if (tmp)
876 writel(tmp, port_mmio + PORT_IRQ_STAT);
877
878 writel(1 << i, mmio + HOST_IRQ_STAT);
879
880 /* set irq mask (enables interrupts) */
881 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
882 }
883
884 tmp = readl(mmio + HOST_CTL);
885 VPRINTK("HOST_CTL 0x%x\n", tmp);
886 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
887 tmp = readl(mmio + HOST_CTL);
888 VPRINTK("HOST_CTL 0x%x\n", tmp);
889
890 pci_set_master(pdev);
891
892 return 0;
893 }
894
895 static void ahci_print_info(struct ata_probe_ent *probe_ent)
896 {
897 struct ahci_host_priv *hpriv = probe_ent->private_data;
898 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
899 void __iomem *mmio = probe_ent->mmio_base;
900 u32 vers, cap, impl, speed;
901 const char *speed_s;
902 u16 cc;
903 const char *scc_s;
904
905 vers = readl(mmio + HOST_VERSION);
906 cap = hpriv->cap;
907 impl = hpriv->port_map;
908
909 speed = (cap >> 20) & 0xf;
910 if (speed == 1)
911 speed_s = "1.5";
912 else if (speed == 2)
913 speed_s = "3";
914 else
915 speed_s = "?";
916
917 pci_read_config_word(pdev, 0x0a, &cc);
918 if (cc == 0x0101)
919 scc_s = "IDE";
920 else if (cc == 0x0106)
921 scc_s = "SATA";
922 else if (cc == 0x0104)
923 scc_s = "RAID";
924 else
925 scc_s = "unknown";
926
927 printk(KERN_INFO DRV_NAME "(%s) AHCI %02x%02x.%02x%02x "
928 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
929 ,
930 pci_name(pdev),
931
932 (vers >> 24) & 0xff,
933 (vers >> 16) & 0xff,
934 (vers >> 8) & 0xff,
935 vers & 0xff,
936
937 ((cap >> 8) & 0x1f) + 1,
938 (cap & 0x1f) + 1,
939 speed_s,
940 impl,
941 scc_s);
942
943 printk(KERN_INFO DRV_NAME "(%s) flags: "
944 "%s%s%s%s%s%s"
945 "%s%s%s%s%s%s%s\n"
946 ,
947 pci_name(pdev),
948
949 cap & (1 << 31) ? "64bit " : "",
950 cap & (1 << 30) ? "ncq " : "",
951 cap & (1 << 28) ? "ilck " : "",
952 cap & (1 << 27) ? "stag " : "",
953 cap & (1 << 26) ? "pm " : "",
954 cap & (1 << 25) ? "led " : "",
955
956 cap & (1 << 24) ? "clo " : "",
957 cap & (1 << 19) ? "nz " : "",
958 cap & (1 << 18) ? "only " : "",
959 cap & (1 << 17) ? "pmp " : "",
960 cap & (1 << 15) ? "pio " : "",
961 cap & (1 << 14) ? "slum " : "",
962 cap & (1 << 13) ? "part " : ""
963 );
964 }
965
966 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
967 {
968 static int printed_version;
969 struct ata_probe_ent *probe_ent = NULL;
970 struct ahci_host_priv *hpriv;
971 unsigned long base;
972 void __iomem *mmio_base;
973 unsigned int board_idx = (unsigned int) ent->driver_data;
974 int have_msi, pci_dev_busy = 0;
975 int rc;
976
977 VPRINTK("ENTER\n");
978
979 if (!printed_version++)
980 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
981
982 rc = pci_enable_device(pdev);
983 if (rc)
984 return rc;
985
986 rc = pci_request_regions(pdev, DRV_NAME);
987 if (rc) {
988 pci_dev_busy = 1;
989 goto err_out;
990 }
991
992 if (pci_enable_msi(pdev) == 0)
993 have_msi = 1;
994 else {
995 pci_intx(pdev, 1);
996 have_msi = 0;
997 }
998
999 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1000 if (probe_ent == NULL) {
1001 rc = -ENOMEM;
1002 goto err_out_msi;
1003 }
1004
1005 memset(probe_ent, 0, sizeof(*probe_ent));
1006 probe_ent->dev = pci_dev_to_dev(pdev);
1007 INIT_LIST_HEAD(&probe_ent->node);
1008
1009 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1010 if (mmio_base == NULL) {
1011 rc = -ENOMEM;
1012 goto err_out_free_ent;
1013 }
1014 base = (unsigned long) mmio_base;
1015
1016 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1017 if (!hpriv) {
1018 rc = -ENOMEM;
1019 goto err_out_iounmap;
1020 }
1021 memset(hpriv, 0, sizeof(*hpriv));
1022
1023 probe_ent->sht = ahci_port_info[board_idx].sht;
1024 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1025 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1026 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1027 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1028
1029 probe_ent->irq = pdev->irq;
1030 probe_ent->irq_flags = SA_SHIRQ;
1031 probe_ent->mmio_base = mmio_base;
1032 probe_ent->private_data = hpriv;
1033
1034 if (have_msi)
1035 hpriv->flags |= AHCI_FLAG_MSI;
1036
1037 /* initialize adapter */
1038 rc = ahci_host_init(probe_ent);
1039 if (rc)
1040 goto err_out_hpriv;
1041
1042 ahci_print_info(probe_ent);
1043
1044 /* FIXME: check ata_device_add return value */
1045 ata_device_add(probe_ent);
1046 kfree(probe_ent);
1047
1048 return 0;
1049
1050 err_out_hpriv:
1051 kfree(hpriv);
1052 err_out_iounmap:
1053 pci_iounmap(pdev, mmio_base);
1054 err_out_free_ent:
1055 kfree(probe_ent);
1056 err_out_msi:
1057 if (have_msi)
1058 pci_disable_msi(pdev);
1059 else
1060 pci_intx(pdev, 0);
1061 pci_release_regions(pdev);
1062 err_out:
1063 if (!pci_dev_busy)
1064 pci_disable_device(pdev);
1065 return rc;
1066 }
1067
1068 static void ahci_remove_one (struct pci_dev *pdev)
1069 {
1070 struct device *dev = pci_dev_to_dev(pdev);
1071 struct ata_host_set *host_set = dev_get_drvdata(dev);
1072 struct ahci_host_priv *hpriv = host_set->private_data;
1073 struct ata_port *ap;
1074 unsigned int i;
1075 int have_msi;
1076
1077 for (i = 0; i < host_set->n_ports; i++) {
1078 ap = host_set->ports[i];
1079
1080 scsi_remove_host(ap->host);
1081 }
1082
1083 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1084 free_irq(host_set->irq, host_set);
1085
1086 for (i = 0; i < host_set->n_ports; i++) {
1087 ap = host_set->ports[i];
1088
1089 ata_scsi_release(ap->host);
1090 scsi_host_put(ap->host);
1091 }
1092
1093 kfree(hpriv);
1094 pci_iounmap(pdev, host_set->mmio_base);
1095 kfree(host_set);
1096
1097 if (have_msi)
1098 pci_disable_msi(pdev);
1099 else
1100 pci_intx(pdev, 0);
1101 pci_release_regions(pdev);
1102 pci_disable_device(pdev);
1103 dev_set_drvdata(dev, NULL);
1104 }
1105
1106 static int __init ahci_init(void)
1107 {
1108 return pci_module_init(&ahci_pci_driver);
1109 }
1110
1111 static void __exit ahci_exit(void)
1112 {
1113 pci_unregister_driver(&ahci_pci_driver);
1114 }
1115
1116
1117 MODULE_AUTHOR("Jeff Garzik");
1118 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1119 MODULE_LICENSE("GPL");
1120 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1121 MODULE_VERSION(DRV_VERSION);
1122
1123 module_init(ahci_init);
1124 module_exit(ahci_exit);
Linux kernel - Deliverables
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