2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "1.3"
56 AHCI_MAX_SG
= 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY
= 0xffffffff,
58 AHCI_USE_CLUSTERING
= 0,
59 AHCI_CMD_SLOT_SZ
= 32 * 32,
61 AHCI_CMD_TBL_HDR
= 0x80,
62 AHCI_CMD_TBL_CDB
= 0x40,
63 AHCI_CMD_TBL_SZ
= AHCI_CMD_TBL_HDR
+ (AHCI_MAX_SG
* 16),
64 AHCI_PORT_PRIV_DMA_SZ
= AHCI_CMD_SLOT_SZ
+ AHCI_CMD_TBL_SZ
+
66 AHCI_IRQ_ON_SG
= (1 << 31),
67 AHCI_CMD_ATAPI
= (1 << 5),
68 AHCI_CMD_WRITE
= (1 << 6),
69 AHCI_CMD_PREFETCH
= (1 << 7),
70 AHCI_CMD_RESET
= (1 << 8),
71 AHCI_CMD_CLR_BUSY
= (1 << 10),
73 RX_FIS_D2H_REG
= 0x40, /* offset of D2H Register FIS data */
77 /* global controller registers */
78 HOST_CAP
= 0x00, /* host capabilities */
79 HOST_CTL
= 0x04, /* global host control */
80 HOST_IRQ_STAT
= 0x08, /* interrupt status */
81 HOST_PORTS_IMPL
= 0x0c, /* bitmap of implemented ports */
82 HOST_VERSION
= 0x10, /* AHCI spec. version compliancy */
85 HOST_RESET
= (1 << 0), /* reset controller; self-clear */
86 HOST_IRQ_EN
= (1 << 1), /* global IRQ enable */
87 HOST_AHCI_EN
= (1 << 31), /* AHCI enabled */
90 HOST_CAP_64
= (1 << 31), /* PCI DAC (64-bit DMA) support */
91 HOST_CAP_CLO
= (1 << 24), /* Command List Override support */
93 /* registers for each SATA port */
94 PORT_LST_ADDR
= 0x00, /* command list DMA addr */
95 PORT_LST_ADDR_HI
= 0x04, /* command list DMA addr hi */
96 PORT_FIS_ADDR
= 0x08, /* FIS rx buf addr */
97 PORT_FIS_ADDR_HI
= 0x0c, /* FIS rx buf addr hi */
98 PORT_IRQ_STAT
= 0x10, /* interrupt status */
99 PORT_IRQ_MASK
= 0x14, /* interrupt enable/disable mask */
100 PORT_CMD
= 0x18, /* port command */
101 PORT_TFDATA
= 0x20, /* taskfile data */
102 PORT_SIG
= 0x24, /* device TF signature */
103 PORT_CMD_ISSUE
= 0x38, /* command issue */
104 PORT_SCR
= 0x28, /* SATA phy register block */
105 PORT_SCR_STAT
= 0x28, /* SATA phy register: SStatus */
106 PORT_SCR_CTL
= 0x2c, /* SATA phy register: SControl */
107 PORT_SCR_ERR
= 0x30, /* SATA phy register: SError */
108 PORT_SCR_ACT
= 0x34, /* SATA phy register: SActive */
110 /* PORT_IRQ_{STAT,MASK} bits */
111 PORT_IRQ_COLD_PRES
= (1 << 31), /* cold presence detect */
112 PORT_IRQ_TF_ERR
= (1 << 30), /* task file error */
113 PORT_IRQ_HBUS_ERR
= (1 << 29), /* host bus fatal error */
114 PORT_IRQ_HBUS_DATA_ERR
= (1 << 28), /* host bus data error */
115 PORT_IRQ_IF_ERR
= (1 << 27), /* interface fatal error */
116 PORT_IRQ_IF_NONFATAL
= (1 << 26), /* interface non-fatal error */
117 PORT_IRQ_OVERFLOW
= (1 << 24), /* xfer exhausted available S/G */
118 PORT_IRQ_BAD_PMP
= (1 << 23), /* incorrect port multiplier */
120 PORT_IRQ_PHYRDY
= (1 << 22), /* PhyRdy changed */
121 PORT_IRQ_DEV_ILCK
= (1 << 7), /* device interlock */
122 PORT_IRQ_CONNECT
= (1 << 6), /* port connect change status */
123 PORT_IRQ_SG_DONE
= (1 << 5), /* descriptor processed */
124 PORT_IRQ_UNK_FIS
= (1 << 4), /* unknown FIS rx'd */
125 PORT_IRQ_SDB_FIS
= (1 << 3), /* Set Device Bits FIS rx'd */
126 PORT_IRQ_DMAS_FIS
= (1 << 2), /* DMA Setup FIS rx'd */
127 PORT_IRQ_PIOS_FIS
= (1 << 1), /* PIO Setup FIS rx'd */
128 PORT_IRQ_D2H_REG_FIS
= (1 << 0), /* D2H Register FIS rx'd */
130 PORT_IRQ_FATAL
= PORT_IRQ_TF_ERR
|
132 PORT_IRQ_HBUS_DATA_ERR
|
134 DEF_PORT_IRQ
= PORT_IRQ_FATAL
| PORT_IRQ_PHYRDY
|
135 PORT_IRQ_CONNECT
| PORT_IRQ_SG_DONE
|
136 PORT_IRQ_UNK_FIS
| PORT_IRQ_SDB_FIS
|
137 PORT_IRQ_DMAS_FIS
| PORT_IRQ_PIOS_FIS
|
138 PORT_IRQ_D2H_REG_FIS
,
141 PORT_CMD_ATAPI
= (1 << 24), /* Device is ATAPI */
142 PORT_CMD_LIST_ON
= (1 << 15), /* cmd list DMA engine running */
143 PORT_CMD_FIS_ON
= (1 << 14), /* FIS DMA engine running */
144 PORT_CMD_FIS_RX
= (1 << 4), /* Enable FIS receive DMA engine */
145 PORT_CMD_CLO
= (1 << 3), /* Command list override */
146 PORT_CMD_POWER_ON
= (1 << 2), /* Power up device */
147 PORT_CMD_SPIN_UP
= (1 << 1), /* Spin up device */
148 PORT_CMD_START
= (1 << 0), /* Enable port DMA engine */
150 PORT_CMD_ICC_ACTIVE
= (0x1 << 28), /* Put i/f in active state */
151 PORT_CMD_ICC_PARTIAL
= (0x2 << 28), /* Put i/f in partial state */
152 PORT_CMD_ICC_SLUMBER
= (0x6 << 28), /* Put i/f in slumber state */
154 /* hpriv->flags bits */
155 AHCI_FLAG_MSI
= (1 << 0),
158 struct ahci_cmd_hdr
{
173 struct ahci_host_priv
{
175 u32 cap
; /* cache of HOST_CAP register */
176 u32 port_map
; /* cache of HOST_PORTS_IMPL reg */
179 struct ahci_port_priv
{
180 struct ahci_cmd_hdr
*cmd_slot
;
181 dma_addr_t cmd_slot_dma
;
183 dma_addr_t cmd_tbl_dma
;
184 struct ahci_sg
*cmd_tbl_sg
;
186 dma_addr_t rx_fis_dma
;
189 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
190 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
191 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
192 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
);
193 static irqreturn_t
ahci_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
);
194 static int ahci_probe_reset(struct ata_port
*ap
, unsigned int *classes
);
195 static void ahci_irq_clear(struct ata_port
*ap
);
196 static void ahci_eng_timeout(struct ata_port
*ap
);
197 static int ahci_port_start(struct ata_port
*ap
);
198 static void ahci_port_stop(struct ata_port
*ap
);
199 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
);
200 static void ahci_qc_prep(struct ata_queued_cmd
*qc
);
201 static u8
ahci_check_status(struct ata_port
*ap
);
202 static inline int ahci_host_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
);
203 static void ahci_remove_one (struct pci_dev
*pdev
);
205 static struct scsi_host_template ahci_sht
= {
206 .module
= THIS_MODULE
,
208 .ioctl
= ata_scsi_ioctl
,
209 .queuecommand
= ata_scsi_queuecmd
,
210 .eh_strategy_handler
= ata_scsi_error
,
211 .can_queue
= ATA_DEF_QUEUE
,
212 .this_id
= ATA_SHT_THIS_ID
,
213 .sg_tablesize
= AHCI_MAX_SG
,
214 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
215 .emulated
= ATA_SHT_EMULATED
,
216 .use_clustering
= AHCI_USE_CLUSTERING
,
217 .proc_name
= DRV_NAME
,
218 .dma_boundary
= AHCI_DMA_BOUNDARY
,
219 .slave_configure
= ata_scsi_slave_config
,
220 .bios_param
= ata_std_bios_param
,
223 static const struct ata_port_operations ahci_ops
= {
224 .port_disable
= ata_port_disable
,
226 .check_status
= ahci_check_status
,
227 .check_altstatus
= ahci_check_status
,
228 .dev_select
= ata_noop_dev_select
,
230 .tf_read
= ahci_tf_read
,
232 .probe_reset
= ahci_probe_reset
,
234 .qc_prep
= ahci_qc_prep
,
235 .qc_issue
= ahci_qc_issue
,
237 .eng_timeout
= ahci_eng_timeout
,
239 .irq_handler
= ahci_interrupt
,
240 .irq_clear
= ahci_irq_clear
,
242 .scr_read
= ahci_scr_read
,
243 .scr_write
= ahci_scr_write
,
245 .port_start
= ahci_port_start
,
246 .port_stop
= ahci_port_stop
,
249 static const struct ata_port_info ahci_port_info
[] = {
253 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
254 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
,
255 .pio_mask
= 0x1f, /* pio0-4 */
256 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
257 .port_ops
= &ahci_ops
,
261 static const struct pci_device_id ahci_pci_tbl
[] = {
262 { PCI_VENDOR_ID_INTEL
, 0x2652, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
263 board_ahci
}, /* ICH6 */
264 { PCI_VENDOR_ID_INTEL
, 0x2653, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
265 board_ahci
}, /* ICH6M */
266 { PCI_VENDOR_ID_INTEL
, 0x27c1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
267 board_ahci
}, /* ICH7 */
268 { PCI_VENDOR_ID_INTEL
, 0x27c5, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
269 board_ahci
}, /* ICH7M */
270 { PCI_VENDOR_ID_INTEL
, 0x27c3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
271 board_ahci
}, /* ICH7R */
272 { PCI_VENDOR_ID_AL
, 0x5288, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
273 board_ahci
}, /* ULi M5288 */
274 { PCI_VENDOR_ID_INTEL
, 0x2681, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
275 board_ahci
}, /* ESB2 */
276 { PCI_VENDOR_ID_INTEL
, 0x2682, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
277 board_ahci
}, /* ESB2 */
278 { PCI_VENDOR_ID_INTEL
, 0x2683, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
279 board_ahci
}, /* ESB2 */
280 { PCI_VENDOR_ID_INTEL
, 0x27c6, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
281 board_ahci
}, /* ICH7-M DH */
282 { PCI_VENDOR_ID_INTEL
, 0x2821, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
283 board_ahci
}, /* ICH8 */
284 { PCI_VENDOR_ID_INTEL
, 0x2822, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
285 board_ahci
}, /* ICH8 */
286 { PCI_VENDOR_ID_INTEL
, 0x2824, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
287 board_ahci
}, /* ICH8 */
288 { PCI_VENDOR_ID_INTEL
, 0x2829, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
289 board_ahci
}, /* ICH8M */
290 { PCI_VENDOR_ID_INTEL
, 0x282a, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
291 board_ahci
}, /* ICH8M */
292 { 0x197b, 0x2360, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
293 board_ahci
}, /* JMicron JMB360 */
294 { 0x197b, 0x2363, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
295 board_ahci
}, /* JMicron JMB363 */
296 { PCI_VENDOR_ID_ATI
, 0x4380, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
297 board_ahci
}, /* ATI SB600 non-raid */
298 { PCI_VENDOR_ID_ATI
, 0x4381, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
299 board_ahci
}, /* ATI SB600 raid */
300 { } /* terminate list */
304 static struct pci_driver ahci_pci_driver
= {
306 .id_table
= ahci_pci_tbl
,
307 .probe
= ahci_init_one
,
308 .remove
= ahci_remove_one
,
312 static inline unsigned long ahci_port_base_ul (unsigned long base
, unsigned int port
)
314 return base
+ 0x100 + (port
* 0x80);
317 static inline void __iomem
*ahci_port_base (void __iomem
*base
, unsigned int port
)
319 return (void __iomem
*) ahci_port_base_ul((unsigned long)base
, port
);
322 static int ahci_port_start(struct ata_port
*ap
)
324 struct device
*dev
= ap
->host_set
->dev
;
325 struct ahci_host_priv
*hpriv
= ap
->host_set
->private_data
;
326 struct ahci_port_priv
*pp
;
327 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
328 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
333 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
336 memset(pp
, 0, sizeof(*pp
));
338 rc
= ata_pad_alloc(ap
, dev
);
344 mem
= dma_alloc_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
, &mem_dma
, GFP_KERNEL
);
346 ata_pad_free(ap
, dev
);
350 memset(mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
353 * First item in chunk of DMA memory: 32-slot command table,
354 * 32 bytes each in size
357 pp
->cmd_slot_dma
= mem_dma
;
359 mem
+= AHCI_CMD_SLOT_SZ
;
360 mem_dma
+= AHCI_CMD_SLOT_SZ
;
363 * Second item: Received-FIS area
366 pp
->rx_fis_dma
= mem_dma
;
368 mem
+= AHCI_RX_FIS_SZ
;
369 mem_dma
+= AHCI_RX_FIS_SZ
;
372 * Third item: data area for storing a single command
373 * and its scatter-gather table
376 pp
->cmd_tbl_dma
= mem_dma
;
378 pp
->cmd_tbl_sg
= mem
+ AHCI_CMD_TBL_HDR
;
380 ap
->private_data
= pp
;
382 if (hpriv
->cap
& HOST_CAP_64
)
383 writel((pp
->cmd_slot_dma
>> 16) >> 16, port_mmio
+ PORT_LST_ADDR_HI
);
384 writel(pp
->cmd_slot_dma
& 0xffffffff, port_mmio
+ PORT_LST_ADDR
);
385 readl(port_mmio
+ PORT_LST_ADDR
); /* flush */
387 if (hpriv
->cap
& HOST_CAP_64
)
388 writel((pp
->rx_fis_dma
>> 16) >> 16, port_mmio
+ PORT_FIS_ADDR_HI
);
389 writel(pp
->rx_fis_dma
& 0xffffffff, port_mmio
+ PORT_FIS_ADDR
);
390 readl(port_mmio
+ PORT_FIS_ADDR
); /* flush */
392 writel(PORT_CMD_ICC_ACTIVE
| PORT_CMD_FIS_RX
|
393 PORT_CMD_POWER_ON
| PORT_CMD_SPIN_UP
|
394 PORT_CMD_START
, port_mmio
+ PORT_CMD
);
395 readl(port_mmio
+ PORT_CMD
); /* flush */
401 static void ahci_port_stop(struct ata_port
*ap
)
403 struct device
*dev
= ap
->host_set
->dev
;
404 struct ahci_port_priv
*pp
= ap
->private_data
;
405 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
406 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
409 tmp
= readl(port_mmio
+ PORT_CMD
);
410 tmp
&= ~(PORT_CMD_START
| PORT_CMD_FIS_RX
);
411 writel(tmp
, port_mmio
+ PORT_CMD
);
412 readl(port_mmio
+ PORT_CMD
); /* flush */
414 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
415 * this is slightly incorrect.
419 ap
->private_data
= NULL
;
420 dma_free_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
,
421 pp
->cmd_slot
, pp
->cmd_slot_dma
);
422 ata_pad_free(ap
, dev
);
426 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg_in
)
431 case SCR_STATUS
: sc_reg
= 0; break;
432 case SCR_CONTROL
: sc_reg
= 1; break;
433 case SCR_ERROR
: sc_reg
= 2; break;
434 case SCR_ACTIVE
: sc_reg
= 3; break;
439 return readl((void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
443 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg_in
,
449 case SCR_STATUS
: sc_reg
= 0; break;
450 case SCR_CONTROL
: sc_reg
= 1; break;
451 case SCR_ERROR
: sc_reg
= 2; break;
452 case SCR_ACTIVE
: sc_reg
= 3; break;
457 writel(val
, (void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
460 static int ahci_stop_engine(struct ata_port
*ap
)
462 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
463 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
467 tmp
= readl(port_mmio
+ PORT_CMD
);
468 tmp
&= ~PORT_CMD_START
;
469 writel(tmp
, port_mmio
+ PORT_CMD
);
471 /* wait for engine to stop. TODO: this could be
472 * as long as 500 msec
476 tmp
= readl(port_mmio
+ PORT_CMD
);
477 if ((tmp
& PORT_CMD_LIST_ON
) == 0)
485 static void ahci_start_engine(struct ata_port
*ap
)
487 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
488 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
491 tmp
= readl(port_mmio
+ PORT_CMD
);
492 tmp
|= PORT_CMD_START
;
493 writel(tmp
, port_mmio
+ PORT_CMD
);
494 readl(port_mmio
+ PORT_CMD
); /* flush */
497 static unsigned int ahci_dev_classify(struct ata_port
*ap
)
499 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
500 struct ata_taskfile tf
;
503 tmp
= readl(port_mmio
+ PORT_SIG
);
504 tf
.lbah
= (tmp
>> 24) & 0xff;
505 tf
.lbam
= (tmp
>> 16) & 0xff;
506 tf
.lbal
= (tmp
>> 8) & 0xff;
507 tf
.nsect
= (tmp
) & 0xff;
509 return ata_dev_classify(&tf
);
512 static void ahci_fill_cmd_slot(struct ahci_port_priv
*pp
, u32 opts
)
514 pp
->cmd_slot
[0].opts
= cpu_to_le32(opts
);
515 pp
->cmd_slot
[0].status
= 0;
516 pp
->cmd_slot
[0].tbl_addr
= cpu_to_le32(pp
->cmd_tbl_dma
& 0xffffffff);
517 pp
->cmd_slot
[0].tbl_addr_hi
= cpu_to_le32((pp
->cmd_tbl_dma
>> 16) >> 16);
520 static int ahci_poll_register(void __iomem
*reg
, u32 mask
, u32 val
,
521 unsigned long interval_msec
,
522 unsigned long timeout_msec
)
524 unsigned long timeout
;
527 timeout
= jiffies
+ (timeout_msec
* HZ
) / 1000;
530 if ((tmp
& mask
) == val
)
532 msleep(interval_msec
);
533 } while (time_before(jiffies
, timeout
));
538 static int ahci_softreset(struct ata_port
*ap
, int verbose
, unsigned int *class)
540 struct ahci_host_priv
*hpriv
= ap
->host_set
->private_data
;
541 struct ahci_port_priv
*pp
= ap
->private_data
;
542 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
543 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
544 const u32 cmd_fis_len
= 5; /* five dwords */
545 const char *reason
= NULL
;
546 struct ata_taskfile tf
;
552 /* prepare for SRST (AHCI-1.1 10.4.1) */
553 rc
= ahci_stop_engine(ap
);
555 reason
= "failed to stop engine";
559 /* check BUSY/DRQ, perform Command List Override if necessary */
560 ahci_tf_read(ap
, &tf
);
561 if (tf
.command
& (ATA_BUSY
| ATA_DRQ
)) {
564 if (!(hpriv
->cap
& HOST_CAP_CLO
)) {
566 reason
= "port busy but no CLO";
570 tmp
= readl(port_mmio
+ PORT_CMD
);
572 writel(tmp
, port_mmio
+ PORT_CMD
);
573 readl(port_mmio
+ PORT_CMD
); /* flush */
575 if (ahci_poll_register(port_mmio
+ PORT_CMD
, PORT_CMD_CLO
, 0x0,
578 reason
= "CLO failed";
584 ahci_start_engine(ap
);
586 ata_tf_init(ap
, &tf
, 0);
589 /* issue the first D2H Register FIS */
590 ahci_fill_cmd_slot(pp
, cmd_fis_len
| AHCI_CMD_RESET
| AHCI_CMD_CLR_BUSY
);
593 ata_tf_to_fis(&tf
, fis
, 0);
594 fis
[1] &= ~(1 << 7); /* turn off Command FIS bit */
596 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
597 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
599 if (ahci_poll_register(port_mmio
+ PORT_CMD_ISSUE
, 0x1, 0x0, 1, 500)) {
601 reason
= "1st FIS failed";
605 /* spec says at least 5us, but be generous and sleep for 1ms */
608 /* issue the second D2H Register FIS */
609 ahci_fill_cmd_slot(pp
, cmd_fis_len
);
612 ata_tf_to_fis(&tf
, fis
, 0);
613 fis
[1] &= ~(1 << 7); /* turn off Command FIS bit */
615 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
616 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
618 /* spec mandates ">= 2ms" before checking status.
619 * We wait 150ms, because that was the magic delay used for
620 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
621 * between when the ATA command register is written, and then
622 * status is checked. Because waiting for "a while" before
623 * checking status is fine, post SRST, we perform this magic
624 * delay here as well.
628 *class = ATA_DEV_NONE
;
629 if (sata_dev_present(ap
)) {
630 if (ata_busy_sleep(ap
, ATA_TMOUT_BOOT_QUICK
, ATA_TMOUT_BOOT
)) {
632 reason
= "device not ready";
635 *class = ahci_dev_classify(ap
);
638 DPRINTK("EXIT, class=%u\n", *class);
642 ahci_start_engine(ap
);
645 printk(KERN_ERR
"ata%u: softreset failed (%s)\n",
648 DPRINTK("EXIT, rc=%d reason=\"%s\"\n", rc
, reason
);
652 static int ahci_hardreset(struct ata_port
*ap
, int verbose
, unsigned int *class)
658 ahci_stop_engine(ap
);
659 rc
= sata_std_hardreset(ap
, verbose
, class);
660 ahci_start_engine(ap
);
663 *class = ahci_dev_classify(ap
);
664 if (*class == ATA_DEV_UNKNOWN
)
665 *class = ATA_DEV_NONE
;
667 DPRINTK("EXIT, rc=%d, class=%u\n", rc
, *class);
671 static void ahci_postreset(struct ata_port
*ap
, unsigned int *class)
673 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
676 ata_std_postreset(ap
, class);
678 /* Make sure port's ATAPI bit is set appropriately */
679 new_tmp
= tmp
= readl(port_mmio
+ PORT_CMD
);
680 if (*class == ATA_DEV_ATAPI
)
681 new_tmp
|= PORT_CMD_ATAPI
;
683 new_tmp
&= ~PORT_CMD_ATAPI
;
684 if (new_tmp
!= tmp
) {
685 writel(new_tmp
, port_mmio
+ PORT_CMD
);
686 readl(port_mmio
+ PORT_CMD
); /* flush */
690 static int ahci_probe_reset(struct ata_port
*ap
, unsigned int *classes
)
692 return ata_drive_probe_reset(ap
, ata_std_probeinit
,
693 ahci_softreset
, ahci_hardreset
,
694 ahci_postreset
, classes
);
697 static u8
ahci_check_status(struct ata_port
*ap
)
699 void __iomem
*mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
701 return readl(mmio
+ PORT_TFDATA
) & 0xFF;
704 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
706 struct ahci_port_priv
*pp
= ap
->private_data
;
707 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
709 ata_tf_from_fis(d2h_fis
, tf
);
712 static unsigned int ahci_fill_sg(struct ata_queued_cmd
*qc
)
714 struct ahci_port_priv
*pp
= qc
->ap
->private_data
;
715 struct scatterlist
*sg
;
716 struct ahci_sg
*ahci_sg
;
717 unsigned int n_sg
= 0;
722 * Next, the S/G list.
724 ahci_sg
= pp
->cmd_tbl_sg
;
725 ata_for_each_sg(sg
, qc
) {
726 dma_addr_t addr
= sg_dma_address(sg
);
727 u32 sg_len
= sg_dma_len(sg
);
729 ahci_sg
->addr
= cpu_to_le32(addr
& 0xffffffff);
730 ahci_sg
->addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
731 ahci_sg
->flags_size
= cpu_to_le32(sg_len
- 1);
740 static void ahci_qc_prep(struct ata_queued_cmd
*qc
)
742 struct ata_port
*ap
= qc
->ap
;
743 struct ahci_port_priv
*pp
= ap
->private_data
;
744 int is_atapi
= is_atapi_taskfile(&qc
->tf
);
746 const u32 cmd_fis_len
= 5; /* five dwords */
750 * Fill in command table information. First, the header,
751 * a SATA Register - Host to Device command FIS.
753 ata_tf_to_fis(&qc
->tf
, pp
->cmd_tbl
, 0);
755 memset(pp
->cmd_tbl
+ AHCI_CMD_TBL_CDB
, 0, 32);
756 memcpy(pp
->cmd_tbl
+ AHCI_CMD_TBL_CDB
, qc
->cdb
,
761 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
762 n_elem
= ahci_fill_sg(qc
);
765 * Fill in command slot information.
767 opts
= cmd_fis_len
| n_elem
<< 16;
768 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
769 opts
|= AHCI_CMD_WRITE
;
771 opts
|= AHCI_CMD_ATAPI
| AHCI_CMD_PREFETCH
;
773 ahci_fill_cmd_slot(pp
, opts
);
776 static void ahci_restart_port(struct ata_port
*ap
, u32 irq_stat
)
778 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
779 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
782 if ((ap
->device
[0].class != ATA_DEV_ATAPI
) ||
783 ((irq_stat
& PORT_IRQ_TF_ERR
) == 0))
784 printk(KERN_WARNING
"ata%u: port reset, "
785 "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n",
788 readl(mmio
+ HOST_IRQ_STAT
),
789 readl(port_mmio
+ PORT_IRQ_STAT
),
790 readl(port_mmio
+ PORT_CMD
),
791 readl(port_mmio
+ PORT_TFDATA
),
792 readl(port_mmio
+ PORT_SCR_STAT
),
793 readl(port_mmio
+ PORT_SCR_ERR
));
796 ahci_stop_engine(ap
);
798 /* clear SATA phy error, if any */
799 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
800 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
802 /* if DRQ/BSY is set, device needs to be reset.
803 * if so, issue COMRESET
805 tmp
= readl(port_mmio
+ PORT_TFDATA
);
806 if (tmp
& (ATA_BUSY
| ATA_DRQ
)) {
807 writel(0x301, port_mmio
+ PORT_SCR_CTL
);
808 readl(port_mmio
+ PORT_SCR_CTL
); /* flush */
810 writel(0x300, port_mmio
+ PORT_SCR_CTL
);
811 readl(port_mmio
+ PORT_SCR_CTL
); /* flush */
815 ahci_start_engine(ap
);
818 static void ahci_eng_timeout(struct ata_port
*ap
)
820 struct ata_host_set
*host_set
= ap
->host_set
;
821 void __iomem
*mmio
= host_set
->mmio_base
;
822 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
823 struct ata_queued_cmd
*qc
;
826 printk(KERN_WARNING
"ata%u: handling error/timeout\n", ap
->id
);
828 spin_lock_irqsave(&host_set
->lock
, flags
);
830 ahci_restart_port(ap
, readl(port_mmio
+ PORT_IRQ_STAT
));
831 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
832 qc
->err_mask
|= AC_ERR_TIMEOUT
;
834 spin_unlock_irqrestore(&host_set
->lock
, flags
);
836 ata_eh_qc_complete(qc
);
839 static inline int ahci_host_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
)
841 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
842 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
843 u32 status
, serr
, ci
;
845 serr
= readl(port_mmio
+ PORT_SCR_ERR
);
846 writel(serr
, port_mmio
+ PORT_SCR_ERR
);
848 status
= readl(port_mmio
+ PORT_IRQ_STAT
);
849 writel(status
, port_mmio
+ PORT_IRQ_STAT
);
851 ci
= readl(port_mmio
+ PORT_CMD_ISSUE
);
852 if (likely((ci
& 0x1) == 0)) {
854 WARN_ON(qc
->err_mask
);
860 if (status
& PORT_IRQ_FATAL
) {
861 unsigned int err_mask
;
862 if (status
& PORT_IRQ_TF_ERR
)
863 err_mask
= AC_ERR_DEV
;
864 else if (status
& PORT_IRQ_IF_ERR
)
865 err_mask
= AC_ERR_ATA_BUS
;
867 err_mask
= AC_ERR_HOST_BUS
;
869 /* command processing has stopped due to error; restart */
870 ahci_restart_port(ap
, status
);
873 qc
->err_mask
|= err_mask
;
881 static void ahci_irq_clear(struct ata_port
*ap
)
886 static irqreturn_t
ahci_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
)
888 struct ata_host_set
*host_set
= dev_instance
;
889 struct ahci_host_priv
*hpriv
;
890 unsigned int i
, handled
= 0;
892 u32 irq_stat
, irq_ack
= 0;
896 hpriv
= host_set
->private_data
;
897 mmio
= host_set
->mmio_base
;
899 /* sigh. 0xffffffff is a valid return from h/w */
900 irq_stat
= readl(mmio
+ HOST_IRQ_STAT
);
901 irq_stat
&= hpriv
->port_map
;
905 spin_lock(&host_set
->lock
);
907 for (i
= 0; i
< host_set
->n_ports
; i
++) {
910 if (!(irq_stat
& (1 << i
)))
913 ap
= host_set
->ports
[i
];
915 struct ata_queued_cmd
*qc
;
916 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
917 if (!ahci_host_intr(ap
, qc
))
919 dev_printk(KERN_WARNING
, host_set
->dev
,
920 "unhandled interrupt on port %u\n",
923 VPRINTK("port %u\n", i
);
925 VPRINTK("port %u (no irq)\n", i
);
927 dev_printk(KERN_WARNING
, host_set
->dev
,
928 "interrupt on disabled port %u\n", i
);
935 writel(irq_ack
, mmio
+ HOST_IRQ_STAT
);
939 spin_unlock(&host_set
->lock
);
943 return IRQ_RETVAL(handled
);
946 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
)
948 struct ata_port
*ap
= qc
->ap
;
949 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
951 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
952 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
957 static void ahci_setup_port(struct ata_ioports
*port
, unsigned long base
,
958 unsigned int port_idx
)
960 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base
, port_idx
);
961 base
= ahci_port_base_ul(base
, port_idx
);
962 VPRINTK("base now==0x%lx\n", base
);
964 port
->cmd_addr
= base
;
965 port
->scr_addr
= base
+ PORT_SCR
;
970 static int ahci_host_init(struct ata_probe_ent
*probe_ent
)
972 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
973 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
974 void __iomem
*mmio
= probe_ent
->mmio_base
;
976 unsigned int i
, j
, using_dac
;
978 void __iomem
*port_mmio
;
980 cap_save
= readl(mmio
+ HOST_CAP
);
981 cap_save
&= ( (1<<28) | (1<<17) );
982 cap_save
|= (1 << 27);
984 /* global controller reset */
985 tmp
= readl(mmio
+ HOST_CTL
);
986 if ((tmp
& HOST_RESET
) == 0) {
987 writel(tmp
| HOST_RESET
, mmio
+ HOST_CTL
);
988 readl(mmio
+ HOST_CTL
); /* flush */
991 /* reset must complete within 1 second, or
992 * the hardware should be considered fried.
996 tmp
= readl(mmio
+ HOST_CTL
);
997 if (tmp
& HOST_RESET
) {
998 dev_printk(KERN_ERR
, &pdev
->dev
,
999 "controller reset failed (0x%x)\n", tmp
);
1003 writel(HOST_AHCI_EN
, mmio
+ HOST_CTL
);
1004 (void) readl(mmio
+ HOST_CTL
); /* flush */
1005 writel(cap_save
, mmio
+ HOST_CAP
);
1006 writel(0xf, mmio
+ HOST_PORTS_IMPL
);
1007 (void) readl(mmio
+ HOST_PORTS_IMPL
); /* flush */
1009 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
) {
1012 pci_read_config_word(pdev
, 0x92, &tmp16
);
1014 pci_write_config_word(pdev
, 0x92, tmp16
);
1017 hpriv
->cap
= readl(mmio
+ HOST_CAP
);
1018 hpriv
->port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
1019 probe_ent
->n_ports
= (hpriv
->cap
& 0x1f) + 1;
1021 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1022 hpriv
->cap
, hpriv
->port_map
, probe_ent
->n_ports
);
1024 using_dac
= hpriv
->cap
& HOST_CAP_64
;
1026 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
1027 rc
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
1029 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
1031 dev_printk(KERN_ERR
, &pdev
->dev
,
1032 "64-bit DMA enable failed\n");
1037 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
1039 dev_printk(KERN_ERR
, &pdev
->dev
,
1040 "32-bit DMA enable failed\n");
1043 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
1045 dev_printk(KERN_ERR
, &pdev
->dev
,
1046 "32-bit consistent DMA enable failed\n");
1051 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
1052 #if 0 /* BIOSen initialize this incorrectly */
1053 if (!(hpriv
->port_map
& (1 << i
)))
1057 port_mmio
= ahci_port_base(mmio
, i
);
1058 VPRINTK("mmio %p port_mmio %p\n", mmio
, port_mmio
);
1060 ahci_setup_port(&probe_ent
->port
[i
],
1061 (unsigned long) mmio
, i
);
1063 /* make sure port is not active */
1064 tmp
= readl(port_mmio
+ PORT_CMD
);
1065 VPRINTK("PORT_CMD 0x%x\n", tmp
);
1066 if (tmp
& (PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
1067 PORT_CMD_FIS_RX
| PORT_CMD_START
)) {
1068 tmp
&= ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
1069 PORT_CMD_FIS_RX
| PORT_CMD_START
);
1070 writel(tmp
, port_mmio
+ PORT_CMD
);
1071 readl(port_mmio
+ PORT_CMD
); /* flush */
1073 /* spec says 500 msecs for each bit, so
1074 * this is slightly incorrect.
1079 writel(PORT_CMD_SPIN_UP
, port_mmio
+ PORT_CMD
);
1084 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
1085 if ((tmp
& 0xf) == 0x3)
1090 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
1091 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp
);
1092 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
1094 /* ack any pending irq events for this port */
1095 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
1096 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp
);
1098 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
1100 writel(1 << i
, mmio
+ HOST_IRQ_STAT
);
1102 /* set irq mask (enables interrupts) */
1103 writel(DEF_PORT_IRQ
, port_mmio
+ PORT_IRQ_MASK
);
1106 tmp
= readl(mmio
+ HOST_CTL
);
1107 VPRINTK("HOST_CTL 0x%x\n", tmp
);
1108 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
1109 tmp
= readl(mmio
+ HOST_CTL
);
1110 VPRINTK("HOST_CTL 0x%x\n", tmp
);
1112 pci_set_master(pdev
);
1117 static void ahci_print_info(struct ata_probe_ent
*probe_ent
)
1119 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
1120 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
1121 void __iomem
*mmio
= probe_ent
->mmio_base
;
1122 u32 vers
, cap
, impl
, speed
;
1123 const char *speed_s
;
1127 vers
= readl(mmio
+ HOST_VERSION
);
1129 impl
= hpriv
->port_map
;
1131 speed
= (cap
>> 20) & 0xf;
1134 else if (speed
== 2)
1139 pci_read_config_word(pdev
, 0x0a, &cc
);
1142 else if (cc
== 0x0106)
1144 else if (cc
== 0x0104)
1149 dev_printk(KERN_INFO
, &pdev
->dev
,
1150 "AHCI %02x%02x.%02x%02x "
1151 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1154 (vers
>> 24) & 0xff,
1155 (vers
>> 16) & 0xff,
1159 ((cap
>> 8) & 0x1f) + 1,
1165 dev_printk(KERN_INFO
, &pdev
->dev
,
1171 cap
& (1 << 31) ? "64bit " : "",
1172 cap
& (1 << 30) ? "ncq " : "",
1173 cap
& (1 << 28) ? "ilck " : "",
1174 cap
& (1 << 27) ? "stag " : "",
1175 cap
& (1 << 26) ? "pm " : "",
1176 cap
& (1 << 25) ? "led " : "",
1178 cap
& (1 << 24) ? "clo " : "",
1179 cap
& (1 << 19) ? "nz " : "",
1180 cap
& (1 << 18) ? "only " : "",
1181 cap
& (1 << 17) ? "pmp " : "",
1182 cap
& (1 << 15) ? "pio " : "",
1183 cap
& (1 << 14) ? "slum " : "",
1184 cap
& (1 << 13) ? "part " : ""
1188 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1190 static int printed_version
;
1191 struct ata_probe_ent
*probe_ent
= NULL
;
1192 struct ahci_host_priv
*hpriv
;
1194 void __iomem
*mmio_base
;
1195 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
1196 int have_msi
, pci_dev_busy
= 0;
1201 if (!printed_version
++)
1202 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
1204 rc
= pci_enable_device(pdev
);
1208 rc
= pci_request_regions(pdev
, DRV_NAME
);
1214 if (pci_enable_msi(pdev
) == 0)
1221 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
1222 if (probe_ent
== NULL
) {
1227 memset(probe_ent
, 0, sizeof(*probe_ent
));
1228 probe_ent
->dev
= pci_dev_to_dev(pdev
);
1229 INIT_LIST_HEAD(&probe_ent
->node
);
1231 mmio_base
= pci_iomap(pdev
, AHCI_PCI_BAR
, 0);
1232 if (mmio_base
== NULL
) {
1234 goto err_out_free_ent
;
1236 base
= (unsigned long) mmio_base
;
1238 hpriv
= kmalloc(sizeof(*hpriv
), GFP_KERNEL
);
1241 goto err_out_iounmap
;
1243 memset(hpriv
, 0, sizeof(*hpriv
));
1245 probe_ent
->sht
= ahci_port_info
[board_idx
].sht
;
1246 probe_ent
->host_flags
= ahci_port_info
[board_idx
].host_flags
;
1247 probe_ent
->pio_mask
= ahci_port_info
[board_idx
].pio_mask
;
1248 probe_ent
->udma_mask
= ahci_port_info
[board_idx
].udma_mask
;
1249 probe_ent
->port_ops
= ahci_port_info
[board_idx
].port_ops
;
1251 probe_ent
->irq
= pdev
->irq
;
1252 probe_ent
->irq_flags
= SA_SHIRQ
;
1253 probe_ent
->mmio_base
= mmio_base
;
1254 probe_ent
->private_data
= hpriv
;
1257 hpriv
->flags
|= AHCI_FLAG_MSI
;
1259 /* JMicron-specific fixup: make sure we're in AHCI mode */
1260 if (pdev
->vendor
== 0x197b)
1261 pci_write_config_byte(pdev
, 0x41, 0xa1);
1263 /* initialize adapter */
1264 rc
= ahci_host_init(probe_ent
);
1268 ahci_print_info(probe_ent
);
1270 /* FIXME: check ata_device_add return value */
1271 ata_device_add(probe_ent
);
1279 pci_iounmap(pdev
, mmio_base
);
1284 pci_disable_msi(pdev
);
1287 pci_release_regions(pdev
);
1290 pci_disable_device(pdev
);
1294 static void ahci_remove_one (struct pci_dev
*pdev
)
1296 struct device
*dev
= pci_dev_to_dev(pdev
);
1297 struct ata_host_set
*host_set
= dev_get_drvdata(dev
);
1298 struct ahci_host_priv
*hpriv
= host_set
->private_data
;
1299 struct ata_port
*ap
;
1303 for (i
= 0; i
< host_set
->n_ports
; i
++) {
1304 ap
= host_set
->ports
[i
];
1306 scsi_remove_host(ap
->host
);
1309 have_msi
= hpriv
->flags
& AHCI_FLAG_MSI
;
1310 free_irq(host_set
->irq
, host_set
);
1312 for (i
= 0; i
< host_set
->n_ports
; i
++) {
1313 ap
= host_set
->ports
[i
];
1315 ata_scsi_release(ap
->host
);
1316 scsi_host_put(ap
->host
);
1320 pci_iounmap(pdev
, host_set
->mmio_base
);
1324 pci_disable_msi(pdev
);
1327 pci_release_regions(pdev
);
1328 pci_disable_device(pdev
);
1329 dev_set_drvdata(dev
, NULL
);
1332 static int __init
ahci_init(void)
1334 return pci_module_init(&ahci_pci_driver
);
1337 static void __exit
ahci_exit(void)
1339 pci_unregister_driver(&ahci_pci_driver
);
1343 MODULE_AUTHOR("Jeff Garzik");
1344 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1345 MODULE_LICENSE("GPL");
1346 MODULE_DEVICE_TABLE(pci
, ahci_pci_tbl
);
1347 MODULE_VERSION(DRV_VERSION
);
1349 module_init(ahci_init
);
1350 module_exit(ahci_exit
);