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[PATCH] ahci: convert to new EH
[deliverable/linux.git] / drivers / scsi / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include <asm/io.h>
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "1.3"
52
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_CMD_SLOT_SZ = 32 * 32,
60 AHCI_RX_FIS_SZ = 256,
61 AHCI_CMD_TBL_HDR = 0x80,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
65 AHCI_RX_FIS_SZ,
66 AHCI_IRQ_ON_SG = (1 << 31),
67 AHCI_CMD_ATAPI = (1 << 5),
68 AHCI_CMD_WRITE = (1 << 6),
69 AHCI_CMD_PREFETCH = (1 << 7),
70 AHCI_CMD_RESET = (1 << 8),
71 AHCI_CMD_CLR_BUSY = (1 << 10),
72
73 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
74 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
75
76 board_ahci = 0,
77 board_ahci_vt8251 = 1,
78
79 /* global controller registers */
80 HOST_CAP = 0x00, /* host capabilities */
81 HOST_CTL = 0x04, /* global host control */
82 HOST_IRQ_STAT = 0x08, /* interrupt status */
83 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
84 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
85
86 /* HOST_CTL bits */
87 HOST_RESET = (1 << 0), /* reset controller; self-clear */
88 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
89 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
90
91 /* HOST_CAP bits */
92 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
93 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
94
95 /* registers for each SATA port */
96 PORT_LST_ADDR = 0x00, /* command list DMA addr */
97 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
98 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
99 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
100 PORT_IRQ_STAT = 0x10, /* interrupt status */
101 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
102 PORT_CMD = 0x18, /* port command */
103 PORT_TFDATA = 0x20, /* taskfile data */
104 PORT_SIG = 0x24, /* device TF signature */
105 PORT_CMD_ISSUE = 0x38, /* command issue */
106 PORT_SCR = 0x28, /* SATA phy register block */
107 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
108 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
109 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
110 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
111
112 /* PORT_IRQ_{STAT,MASK} bits */
113 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
114 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
115 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
116 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
117 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
118 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
119 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
120 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
121
122 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
123 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
124 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
125 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
126 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
127 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
128 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
129 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
130 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
131
132 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
133 PORT_IRQ_IF_ERR |
134 PORT_IRQ_CONNECT |
135 PORT_IRQ_UNK_FIS,
136 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
137 PORT_IRQ_TF_ERR |
138 PORT_IRQ_HBUS_DATA_ERR,
139 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
140 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
141 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
142
143 /* PORT_CMD bits */
144 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
145 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
146 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
147 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
148 PORT_CMD_CLO = (1 << 3), /* Command list override */
149 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
150 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
151 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
152
153 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
154 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
155 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
156
157 /* hpriv->flags bits */
158 AHCI_FLAG_MSI = (1 << 0),
159
160 /* ap->flags bits */
161 AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24),
162 };
163
164 struct ahci_cmd_hdr {
165 u32 opts;
166 u32 status;
167 u32 tbl_addr;
168 u32 tbl_addr_hi;
169 u32 reserved[4];
170 };
171
172 struct ahci_sg {
173 u32 addr;
174 u32 addr_hi;
175 u32 reserved;
176 u32 flags_size;
177 };
178
179 struct ahci_host_priv {
180 unsigned long flags;
181 u32 cap; /* cache of HOST_CAP register */
182 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
183 };
184
185 struct ahci_port_priv {
186 struct ahci_cmd_hdr *cmd_slot;
187 dma_addr_t cmd_slot_dma;
188 void *cmd_tbl;
189 dma_addr_t cmd_tbl_dma;
190 struct ahci_sg *cmd_tbl_sg;
191 void *rx_fis;
192 dma_addr_t rx_fis_dma;
193 };
194
195 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
196 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
197 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
198 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
199 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
200 static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes);
201 static void ahci_irq_clear(struct ata_port *ap);
202 static int ahci_port_start(struct ata_port *ap);
203 static void ahci_port_stop(struct ata_port *ap);
204 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
205 static void ahci_qc_prep(struct ata_queued_cmd *qc);
206 static u8 ahci_check_status(struct ata_port *ap);
207 static void ahci_freeze(struct ata_port *ap);
208 static void ahci_thaw(struct ata_port *ap);
209 static void ahci_error_handler(struct ata_port *ap);
210 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
211 static void ahci_remove_one (struct pci_dev *pdev);
212
213 static struct scsi_host_template ahci_sht = {
214 .module = THIS_MODULE,
215 .name = DRV_NAME,
216 .ioctl = ata_scsi_ioctl,
217 .queuecommand = ata_scsi_queuecmd,
218 .can_queue = ATA_DEF_QUEUE,
219 .this_id = ATA_SHT_THIS_ID,
220 .sg_tablesize = AHCI_MAX_SG,
221 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
222 .emulated = ATA_SHT_EMULATED,
223 .use_clustering = AHCI_USE_CLUSTERING,
224 .proc_name = DRV_NAME,
225 .dma_boundary = AHCI_DMA_BOUNDARY,
226 .slave_configure = ata_scsi_slave_config,
227 .bios_param = ata_std_bios_param,
228 };
229
230 static const struct ata_port_operations ahci_ops = {
231 .port_disable = ata_port_disable,
232
233 .check_status = ahci_check_status,
234 .check_altstatus = ahci_check_status,
235 .dev_select = ata_noop_dev_select,
236
237 .tf_read = ahci_tf_read,
238
239 .probe_reset = ahci_probe_reset,
240
241 .qc_prep = ahci_qc_prep,
242 .qc_issue = ahci_qc_issue,
243
244 .irq_handler = ahci_interrupt,
245 .irq_clear = ahci_irq_clear,
246
247 .scr_read = ahci_scr_read,
248 .scr_write = ahci_scr_write,
249
250 .freeze = ahci_freeze,
251 .thaw = ahci_thaw,
252
253 .error_handler = ahci_error_handler,
254 .post_internal_cmd = ahci_post_internal_cmd,
255
256 .port_start = ahci_port_start,
257 .port_stop = ahci_port_stop,
258 };
259
260 static const struct ata_port_info ahci_port_info[] = {
261 /* board_ahci */
262 {
263 .sht = &ahci_sht,
264 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
265 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
266 .pio_mask = 0x1f, /* pio0-4 */
267 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
268 .port_ops = &ahci_ops,
269 },
270 /* board_ahci_vt8251 */
271 {
272 .sht = &ahci_sht,
273 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
274 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
275 AHCI_FLAG_RESET_NEEDS_CLO,
276 .pio_mask = 0x1f, /* pio0-4 */
277 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
278 .port_ops = &ahci_ops,
279 },
280 };
281
282 static const struct pci_device_id ahci_pci_tbl[] = {
283 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
284 board_ahci }, /* ICH6 */
285 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
286 board_ahci }, /* ICH6M */
287 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
288 board_ahci }, /* ICH7 */
289 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
290 board_ahci }, /* ICH7M */
291 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
292 board_ahci }, /* ICH7R */
293 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
294 board_ahci }, /* ULi M5288 */
295 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
296 board_ahci }, /* ESB2 */
297 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
298 board_ahci }, /* ESB2 */
299 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
300 board_ahci }, /* ESB2 */
301 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
302 board_ahci }, /* ICH7-M DH */
303 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
304 board_ahci }, /* ICH8 */
305 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
306 board_ahci }, /* ICH8 */
307 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
308 board_ahci }, /* ICH8 */
309 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
310 board_ahci }, /* ICH8M */
311 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
312 board_ahci }, /* ICH8M */
313 { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
314 board_ahci }, /* JMicron JMB360 */
315 { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
316 board_ahci }, /* JMicron JMB363 */
317 { PCI_VENDOR_ID_ATI, 0x4380, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
318 board_ahci }, /* ATI SB600 non-raid */
319 { PCI_VENDOR_ID_ATI, 0x4381, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
320 board_ahci }, /* ATI SB600 raid */
321 { PCI_VENDOR_ID_VIA, 0x3349, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
322 board_ahci_vt8251 }, /* VIA VT8251 */
323 { } /* terminate list */
324 };
325
326
327 static struct pci_driver ahci_pci_driver = {
328 .name = DRV_NAME,
329 .id_table = ahci_pci_tbl,
330 .probe = ahci_init_one,
331 .remove = ahci_remove_one,
332 };
333
334
335 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
336 {
337 return base + 0x100 + (port * 0x80);
338 }
339
340 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
341 {
342 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
343 }
344
345 static int ahci_port_start(struct ata_port *ap)
346 {
347 struct device *dev = ap->host_set->dev;
348 struct ahci_host_priv *hpriv = ap->host_set->private_data;
349 struct ahci_port_priv *pp;
350 void __iomem *mmio = ap->host_set->mmio_base;
351 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
352 void *mem;
353 dma_addr_t mem_dma;
354 int rc;
355
356 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
357 if (!pp)
358 return -ENOMEM;
359 memset(pp, 0, sizeof(*pp));
360
361 rc = ata_pad_alloc(ap, dev);
362 if (rc) {
363 kfree(pp);
364 return rc;
365 }
366
367 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
368 if (!mem) {
369 ata_pad_free(ap, dev);
370 kfree(pp);
371 return -ENOMEM;
372 }
373 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
374
375 /*
376 * First item in chunk of DMA memory: 32-slot command table,
377 * 32 bytes each in size
378 */
379 pp->cmd_slot = mem;
380 pp->cmd_slot_dma = mem_dma;
381
382 mem += AHCI_CMD_SLOT_SZ;
383 mem_dma += AHCI_CMD_SLOT_SZ;
384
385 /*
386 * Second item: Received-FIS area
387 */
388 pp->rx_fis = mem;
389 pp->rx_fis_dma = mem_dma;
390
391 mem += AHCI_RX_FIS_SZ;
392 mem_dma += AHCI_RX_FIS_SZ;
393
394 /*
395 * Third item: data area for storing a single command
396 * and its scatter-gather table
397 */
398 pp->cmd_tbl = mem;
399 pp->cmd_tbl_dma = mem_dma;
400
401 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
402
403 ap->private_data = pp;
404
405 if (hpriv->cap & HOST_CAP_64)
406 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
407 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
408 readl(port_mmio + PORT_LST_ADDR); /* flush */
409
410 if (hpriv->cap & HOST_CAP_64)
411 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
412 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
413 readl(port_mmio + PORT_FIS_ADDR); /* flush */
414
415 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
416 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
417 PORT_CMD_START, port_mmio + PORT_CMD);
418 readl(port_mmio + PORT_CMD); /* flush */
419
420 return 0;
421 }
422
423
424 static void ahci_port_stop(struct ata_port *ap)
425 {
426 struct device *dev = ap->host_set->dev;
427 struct ahci_port_priv *pp = ap->private_data;
428 void __iomem *mmio = ap->host_set->mmio_base;
429 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
430 u32 tmp;
431
432 tmp = readl(port_mmio + PORT_CMD);
433 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
434 writel(tmp, port_mmio + PORT_CMD);
435 readl(port_mmio + PORT_CMD); /* flush */
436
437 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
438 * this is slightly incorrect.
439 */
440 msleep(500);
441
442 ap->private_data = NULL;
443 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
444 pp->cmd_slot, pp->cmd_slot_dma);
445 ata_pad_free(ap, dev);
446 kfree(pp);
447 }
448
449 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
450 {
451 unsigned int sc_reg;
452
453 switch (sc_reg_in) {
454 case SCR_STATUS: sc_reg = 0; break;
455 case SCR_CONTROL: sc_reg = 1; break;
456 case SCR_ERROR: sc_reg = 2; break;
457 case SCR_ACTIVE: sc_reg = 3; break;
458 default:
459 return 0xffffffffU;
460 }
461
462 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
463 }
464
465
466 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
467 u32 val)
468 {
469 unsigned int sc_reg;
470
471 switch (sc_reg_in) {
472 case SCR_STATUS: sc_reg = 0; break;
473 case SCR_CONTROL: sc_reg = 1; break;
474 case SCR_ERROR: sc_reg = 2; break;
475 case SCR_ACTIVE: sc_reg = 3; break;
476 default:
477 return;
478 }
479
480 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
481 }
482
483 static int ahci_stop_engine(struct ata_port *ap)
484 {
485 void __iomem *mmio = ap->host_set->mmio_base;
486 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
487 int work;
488 u32 tmp;
489
490 tmp = readl(port_mmio + PORT_CMD);
491 tmp &= ~PORT_CMD_START;
492 writel(tmp, port_mmio + PORT_CMD);
493
494 /* wait for engine to stop. TODO: this could be
495 * as long as 500 msec
496 */
497 work = 1000;
498 while (work-- > 0) {
499 tmp = readl(port_mmio + PORT_CMD);
500 if ((tmp & PORT_CMD_LIST_ON) == 0)
501 return 0;
502 udelay(10);
503 }
504
505 return -EIO;
506 }
507
508 static void ahci_start_engine(struct ata_port *ap)
509 {
510 void __iomem *mmio = ap->host_set->mmio_base;
511 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
512 u32 tmp;
513
514 tmp = readl(port_mmio + PORT_CMD);
515 tmp |= PORT_CMD_START;
516 writel(tmp, port_mmio + PORT_CMD);
517 readl(port_mmio + PORT_CMD); /* flush */
518 }
519
520 static unsigned int ahci_dev_classify(struct ata_port *ap)
521 {
522 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
523 struct ata_taskfile tf;
524 u32 tmp;
525
526 tmp = readl(port_mmio + PORT_SIG);
527 tf.lbah = (tmp >> 24) & 0xff;
528 tf.lbam = (tmp >> 16) & 0xff;
529 tf.lbal = (tmp >> 8) & 0xff;
530 tf.nsect = (tmp) & 0xff;
531
532 return ata_dev_classify(&tf);
533 }
534
535 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, u32 opts)
536 {
537 pp->cmd_slot[0].opts = cpu_to_le32(opts);
538 pp->cmd_slot[0].status = 0;
539 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
540 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
541 }
542
543 static int ahci_clo(struct ata_port *ap)
544 {
545 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
546 struct ahci_host_priv *hpriv = ap->host_set->private_data;
547 u32 tmp;
548
549 if (!(hpriv->cap & HOST_CAP_CLO))
550 return -EOPNOTSUPP;
551
552 tmp = readl(port_mmio + PORT_CMD);
553 tmp |= PORT_CMD_CLO;
554 writel(tmp, port_mmio + PORT_CMD);
555
556 tmp = ata_wait_register(port_mmio + PORT_CMD,
557 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
558 if (tmp & PORT_CMD_CLO)
559 return -EIO;
560
561 return 0;
562 }
563
564 static int ahci_softreset(struct ata_port *ap, unsigned int *class)
565 {
566 struct ahci_port_priv *pp = ap->private_data;
567 void __iomem *mmio = ap->host_set->mmio_base;
568 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
569 const u32 cmd_fis_len = 5; /* five dwords */
570 const char *reason = NULL;
571 struct ata_taskfile tf;
572 u32 tmp;
573 u8 *fis;
574 int rc;
575
576 DPRINTK("ENTER\n");
577
578 if (ata_port_offline(ap)) {
579 DPRINTK("PHY reports no device\n");
580 *class = ATA_DEV_NONE;
581 return 0;
582 }
583
584 /* prepare for SRST (AHCI-1.1 10.4.1) */
585 rc = ahci_stop_engine(ap);
586 if (rc) {
587 reason = "failed to stop engine";
588 goto fail_restart;
589 }
590
591 /* check BUSY/DRQ, perform Command List Override if necessary */
592 ahci_tf_read(ap, &tf);
593 if (tf.command & (ATA_BUSY | ATA_DRQ)) {
594 rc = ahci_clo(ap);
595
596 if (rc == -EOPNOTSUPP) {
597 reason = "port busy but CLO unavailable";
598 goto fail_restart;
599 } else if (rc) {
600 reason = "port busy but CLO failed";
601 goto fail_restart;
602 }
603 }
604
605 /* restart engine */
606 ahci_start_engine(ap);
607
608 ata_tf_init(ap->device, &tf);
609 fis = pp->cmd_tbl;
610
611 /* issue the first D2H Register FIS */
612 ahci_fill_cmd_slot(pp, cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
613
614 tf.ctl |= ATA_SRST;
615 ata_tf_to_fis(&tf, fis, 0);
616 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
617
618 writel(1, port_mmio + PORT_CMD_ISSUE);
619
620 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
621 if (tmp & 0x1) {
622 rc = -EIO;
623 reason = "1st FIS failed";
624 goto fail;
625 }
626
627 /* spec says at least 5us, but be generous and sleep for 1ms */
628 msleep(1);
629
630 /* issue the second D2H Register FIS */
631 ahci_fill_cmd_slot(pp, cmd_fis_len);
632
633 tf.ctl &= ~ATA_SRST;
634 ata_tf_to_fis(&tf, fis, 0);
635 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
636
637 writel(1, port_mmio + PORT_CMD_ISSUE);
638 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
639
640 /* spec mandates ">= 2ms" before checking status.
641 * We wait 150ms, because that was the magic delay used for
642 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
643 * between when the ATA command register is written, and then
644 * status is checked. Because waiting for "a while" before
645 * checking status is fine, post SRST, we perform this magic
646 * delay here as well.
647 */
648 msleep(150);
649
650 *class = ATA_DEV_NONE;
651 if (ata_port_online(ap)) {
652 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
653 rc = -EIO;
654 reason = "device not ready";
655 goto fail;
656 }
657 *class = ahci_dev_classify(ap);
658 }
659
660 DPRINTK("EXIT, class=%u\n", *class);
661 return 0;
662
663 fail_restart:
664 ahci_start_engine(ap);
665 fail:
666 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
667 return rc;
668 }
669
670 static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
671 {
672 int rc;
673
674 DPRINTK("ENTER\n");
675
676 ahci_stop_engine(ap);
677 rc = sata_std_hardreset(ap, class);
678 ahci_start_engine(ap);
679
680 if (rc == 0 && ata_port_online(ap))
681 *class = ahci_dev_classify(ap);
682 if (*class == ATA_DEV_UNKNOWN)
683 *class = ATA_DEV_NONE;
684
685 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
686 return rc;
687 }
688
689 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
690 {
691 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
692 u32 new_tmp, tmp;
693
694 ata_std_postreset(ap, class);
695
696 /* Make sure port's ATAPI bit is set appropriately */
697 new_tmp = tmp = readl(port_mmio + PORT_CMD);
698 if (*class == ATA_DEV_ATAPI)
699 new_tmp |= PORT_CMD_ATAPI;
700 else
701 new_tmp &= ~PORT_CMD_ATAPI;
702 if (new_tmp != tmp) {
703 writel(new_tmp, port_mmio + PORT_CMD);
704 readl(port_mmio + PORT_CMD); /* flush */
705 }
706 }
707
708 static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes)
709 {
710 if ((ap->flags & AHCI_FLAG_RESET_NEEDS_CLO) &&
711 (ata_busy_wait(ap, ATA_BUSY, 1000) & ATA_BUSY)) {
712 /* ATA_BUSY hasn't cleared, so send a CLO */
713 ahci_clo(ap);
714 }
715
716 return ata_drive_probe_reset(ap, ata_std_probeinit,
717 ahci_softreset, ahci_hardreset,
718 ahci_postreset, classes);
719 }
720
721 static u8 ahci_check_status(struct ata_port *ap)
722 {
723 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
724
725 return readl(mmio + PORT_TFDATA) & 0xFF;
726 }
727
728 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
729 {
730 struct ahci_port_priv *pp = ap->private_data;
731 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
732
733 ata_tf_from_fis(d2h_fis, tf);
734 }
735
736 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
737 {
738 struct ahci_port_priv *pp = qc->ap->private_data;
739 struct scatterlist *sg;
740 struct ahci_sg *ahci_sg;
741 unsigned int n_sg = 0;
742
743 VPRINTK("ENTER\n");
744
745 /*
746 * Next, the S/G list.
747 */
748 ahci_sg = pp->cmd_tbl_sg;
749 ata_for_each_sg(sg, qc) {
750 dma_addr_t addr = sg_dma_address(sg);
751 u32 sg_len = sg_dma_len(sg);
752
753 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
754 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
755 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
756
757 ahci_sg++;
758 n_sg++;
759 }
760
761 return n_sg;
762 }
763
764 static void ahci_qc_prep(struct ata_queued_cmd *qc)
765 {
766 struct ata_port *ap = qc->ap;
767 struct ahci_port_priv *pp = ap->private_data;
768 int is_atapi = is_atapi_taskfile(&qc->tf);
769 u32 opts;
770 const u32 cmd_fis_len = 5; /* five dwords */
771 unsigned int n_elem;
772
773 /*
774 * Fill in command table information. First, the header,
775 * a SATA Register - Host to Device command FIS.
776 */
777 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
778 if (is_atapi) {
779 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
780 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb,
781 qc->dev->cdb_len);
782 }
783
784 n_elem = 0;
785 if (qc->flags & ATA_QCFLAG_DMAMAP)
786 n_elem = ahci_fill_sg(qc);
787
788 /*
789 * Fill in command slot information.
790 */
791 opts = cmd_fis_len | n_elem << 16;
792 if (qc->tf.flags & ATA_TFLAG_WRITE)
793 opts |= AHCI_CMD_WRITE;
794 if (is_atapi)
795 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
796
797 ahci_fill_cmd_slot(pp, opts);
798 }
799
800 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
801 {
802 struct ahci_port_priv *pp = ap->private_data;
803 struct ata_eh_info *ehi = &ap->eh_info;
804 unsigned int err_mask = 0, action = 0;
805 struct ata_queued_cmd *qc;
806 u32 serror;
807
808 ata_ehi_clear_desc(ehi);
809
810 /* AHCI needs SError cleared; otherwise, it might lock up */
811 serror = ahci_scr_read(ap, SCR_ERROR);
812 ahci_scr_write(ap, SCR_ERROR, serror);
813
814 /* analyze @irq_stat */
815 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
816
817 if (irq_stat & PORT_IRQ_TF_ERR)
818 err_mask |= AC_ERR_DEV;
819
820 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
821 err_mask |= AC_ERR_HOST_BUS;
822 action |= ATA_EH_SOFTRESET;
823 }
824
825 if (irq_stat & PORT_IRQ_IF_ERR) {
826 err_mask |= AC_ERR_ATA_BUS;
827 action |= ATA_EH_SOFTRESET;
828 ata_ehi_push_desc(ehi, ", interface fatal error");
829 }
830
831 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
832 err_mask |= AC_ERR_ATA_BUS;
833 action |= ATA_EH_SOFTRESET;
834 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
835 "connection status changed" : "PHY RDY changed");
836 }
837
838 if (irq_stat & PORT_IRQ_UNK_FIS) {
839 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
840
841 err_mask |= AC_ERR_HSM;
842 action |= ATA_EH_SOFTRESET;
843 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
844 unk[0], unk[1], unk[2], unk[3]);
845 }
846
847 /* okay, let's hand over to EH */
848 ehi->serror |= serror;
849 ehi->action |= action;
850
851 qc = ata_qc_from_tag(ap, ap->active_tag);
852 if (qc)
853 qc->err_mask |= err_mask;
854 else
855 ehi->err_mask |= err_mask;
856
857 if (irq_stat & PORT_IRQ_FREEZE)
858 ata_port_freeze(ap);
859 else
860 ata_port_abort(ap);
861 }
862
863 static void ahci_host_intr(struct ata_port *ap)
864 {
865 void __iomem *mmio = ap->host_set->mmio_base;
866 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
867 struct ata_queued_cmd *qc;
868 u32 status, ci;
869
870 status = readl(port_mmio + PORT_IRQ_STAT);
871 writel(status, port_mmio + PORT_IRQ_STAT);
872
873 if (unlikely(status & PORT_IRQ_ERROR)) {
874 ahci_error_intr(ap, status);
875 return;
876 }
877
878 if ((qc = ata_qc_from_tag(ap, ap->active_tag))) {
879 ci = readl(port_mmio + PORT_CMD_ISSUE);
880 if ((ci & 0x1) == 0) {
881 ata_qc_complete(qc);
882 return;
883 }
884 }
885
886 /* spurious interrupt */
887 if (ata_ratelimit())
888 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
889 "(irq_stat 0x%x active_tag %d)\n",
890 status, ap->active_tag);
891 }
892
893 static void ahci_irq_clear(struct ata_port *ap)
894 {
895 /* TODO */
896 }
897
898 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
899 {
900 struct ata_host_set *host_set = dev_instance;
901 struct ahci_host_priv *hpriv;
902 unsigned int i, handled = 0;
903 void __iomem *mmio;
904 u32 irq_stat, irq_ack = 0;
905
906 VPRINTK("ENTER\n");
907
908 hpriv = host_set->private_data;
909 mmio = host_set->mmio_base;
910
911 /* sigh. 0xffffffff is a valid return from h/w */
912 irq_stat = readl(mmio + HOST_IRQ_STAT);
913 irq_stat &= hpriv->port_map;
914 if (!irq_stat)
915 return IRQ_NONE;
916
917 spin_lock(&host_set->lock);
918
919 for (i = 0; i < host_set->n_ports; i++) {
920 struct ata_port *ap;
921
922 if (!(irq_stat & (1 << i)))
923 continue;
924
925 ap = host_set->ports[i];
926 if (ap) {
927 ahci_host_intr(ap);
928 VPRINTK("port %u\n", i);
929 } else {
930 VPRINTK("port %u (no irq)\n", i);
931 if (ata_ratelimit())
932 dev_printk(KERN_WARNING, host_set->dev,
933 "interrupt on disabled port %u\n", i);
934 }
935
936 irq_ack |= (1 << i);
937 }
938
939 if (irq_ack) {
940 writel(irq_ack, mmio + HOST_IRQ_STAT);
941 handled = 1;
942 }
943
944 spin_unlock(&host_set->lock);
945
946 VPRINTK("EXIT\n");
947
948 return IRQ_RETVAL(handled);
949 }
950
951 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
952 {
953 struct ata_port *ap = qc->ap;
954 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
955
956 writel(1, port_mmio + PORT_CMD_ISSUE);
957 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
958
959 return 0;
960 }
961
962 static void ahci_freeze(struct ata_port *ap)
963 {
964 void __iomem *mmio = ap->host_set->mmio_base;
965 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
966
967 /* turn IRQ off */
968 writel(0, port_mmio + PORT_IRQ_MASK);
969 }
970
971 static void ahci_thaw(struct ata_port *ap)
972 {
973 void __iomem *mmio = ap->host_set->mmio_base;
974 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
975 u32 tmp;
976
977 /* clear IRQ */
978 tmp = readl(port_mmio + PORT_IRQ_STAT);
979 writel(tmp, port_mmio + PORT_IRQ_STAT);
980 writel(1 << ap->id, mmio + HOST_IRQ_STAT);
981
982 /* turn IRQ back on */
983 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
984 }
985
986 static void ahci_error_handler(struct ata_port *ap)
987 {
988 if (!(ap->flags & ATA_FLAG_FROZEN)) {
989 /* restart engine */
990 ahci_stop_engine(ap);
991 ahci_start_engine(ap);
992 }
993
994 /* perform recovery */
995 ata_do_eh(ap, ahci_softreset, ahci_hardreset, ahci_postreset);
996 }
997
998 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
999 {
1000 struct ata_port *ap = qc->ap;
1001
1002 if (qc->flags & ATA_QCFLAG_FAILED)
1003 qc->err_mask |= AC_ERR_OTHER;
1004
1005 if (qc->err_mask) {
1006 /* make DMA engine forget about the failed command */
1007 ahci_stop_engine(ap);
1008 ahci_start_engine(ap);
1009 }
1010 }
1011
1012 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1013 unsigned int port_idx)
1014 {
1015 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1016 base = ahci_port_base_ul(base, port_idx);
1017 VPRINTK("base now==0x%lx\n", base);
1018
1019 port->cmd_addr = base;
1020 port->scr_addr = base + PORT_SCR;
1021
1022 VPRINTK("EXIT\n");
1023 }
1024
1025 static int ahci_host_init(struct ata_probe_ent *probe_ent)
1026 {
1027 struct ahci_host_priv *hpriv = probe_ent->private_data;
1028 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1029 void __iomem *mmio = probe_ent->mmio_base;
1030 u32 tmp, cap_save;
1031 unsigned int i, j, using_dac;
1032 int rc;
1033 void __iomem *port_mmio;
1034
1035 cap_save = readl(mmio + HOST_CAP);
1036 cap_save &= ( (1<<28) | (1<<17) );
1037 cap_save |= (1 << 27);
1038
1039 /* global controller reset */
1040 tmp = readl(mmio + HOST_CTL);
1041 if ((tmp & HOST_RESET) == 0) {
1042 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1043 readl(mmio + HOST_CTL); /* flush */
1044 }
1045
1046 /* reset must complete within 1 second, or
1047 * the hardware should be considered fried.
1048 */
1049 ssleep(1);
1050
1051 tmp = readl(mmio + HOST_CTL);
1052 if (tmp & HOST_RESET) {
1053 dev_printk(KERN_ERR, &pdev->dev,
1054 "controller reset failed (0x%x)\n", tmp);
1055 return -EIO;
1056 }
1057
1058 writel(HOST_AHCI_EN, mmio + HOST_CTL);
1059 (void) readl(mmio + HOST_CTL); /* flush */
1060 writel(cap_save, mmio + HOST_CAP);
1061 writel(0xf, mmio + HOST_PORTS_IMPL);
1062 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
1063
1064 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1065 u16 tmp16;
1066
1067 pci_read_config_word(pdev, 0x92, &tmp16);
1068 tmp16 |= 0xf;
1069 pci_write_config_word(pdev, 0x92, tmp16);
1070 }
1071
1072 hpriv->cap = readl(mmio + HOST_CAP);
1073 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1074 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1075
1076 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1077 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1078
1079 using_dac = hpriv->cap & HOST_CAP_64;
1080 if (using_dac &&
1081 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1082 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1083 if (rc) {
1084 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1085 if (rc) {
1086 dev_printk(KERN_ERR, &pdev->dev,
1087 "64-bit DMA enable failed\n");
1088 return rc;
1089 }
1090 }
1091 } else {
1092 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1093 if (rc) {
1094 dev_printk(KERN_ERR, &pdev->dev,
1095 "32-bit DMA enable failed\n");
1096 return rc;
1097 }
1098 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1099 if (rc) {
1100 dev_printk(KERN_ERR, &pdev->dev,
1101 "32-bit consistent DMA enable failed\n");
1102 return rc;
1103 }
1104 }
1105
1106 for (i = 0; i < probe_ent->n_ports; i++) {
1107 #if 0 /* BIOSen initialize this incorrectly */
1108 if (!(hpriv->port_map & (1 << i)))
1109 continue;
1110 #endif
1111
1112 port_mmio = ahci_port_base(mmio, i);
1113 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
1114
1115 ahci_setup_port(&probe_ent->port[i],
1116 (unsigned long) mmio, i);
1117
1118 /* make sure port is not active */
1119 tmp = readl(port_mmio + PORT_CMD);
1120 VPRINTK("PORT_CMD 0x%x\n", tmp);
1121 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1122 PORT_CMD_FIS_RX | PORT_CMD_START)) {
1123 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1124 PORT_CMD_FIS_RX | PORT_CMD_START);
1125 writel(tmp, port_mmio + PORT_CMD);
1126 readl(port_mmio + PORT_CMD); /* flush */
1127
1128 /* spec says 500 msecs for each bit, so
1129 * this is slightly incorrect.
1130 */
1131 msleep(500);
1132 }
1133
1134 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
1135
1136 j = 0;
1137 while (j < 100) {
1138 msleep(10);
1139 tmp = readl(port_mmio + PORT_SCR_STAT);
1140 if ((tmp & 0xf) == 0x3)
1141 break;
1142 j++;
1143 }
1144
1145 tmp = readl(port_mmio + PORT_SCR_ERR);
1146 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1147 writel(tmp, port_mmio + PORT_SCR_ERR);
1148
1149 /* ack any pending irq events for this port */
1150 tmp = readl(port_mmio + PORT_IRQ_STAT);
1151 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1152 if (tmp)
1153 writel(tmp, port_mmio + PORT_IRQ_STAT);
1154
1155 writel(1 << i, mmio + HOST_IRQ_STAT);
1156 }
1157
1158 tmp = readl(mmio + HOST_CTL);
1159 VPRINTK("HOST_CTL 0x%x\n", tmp);
1160 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1161 tmp = readl(mmio + HOST_CTL);
1162 VPRINTK("HOST_CTL 0x%x\n", tmp);
1163
1164 pci_set_master(pdev);
1165
1166 return 0;
1167 }
1168
1169 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1170 {
1171 struct ahci_host_priv *hpriv = probe_ent->private_data;
1172 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1173 void __iomem *mmio = probe_ent->mmio_base;
1174 u32 vers, cap, impl, speed;
1175 const char *speed_s;
1176 u16 cc;
1177 const char *scc_s;
1178
1179 vers = readl(mmio + HOST_VERSION);
1180 cap = hpriv->cap;
1181 impl = hpriv->port_map;
1182
1183 speed = (cap >> 20) & 0xf;
1184 if (speed == 1)
1185 speed_s = "1.5";
1186 else if (speed == 2)
1187 speed_s = "3";
1188 else
1189 speed_s = "?";
1190
1191 pci_read_config_word(pdev, 0x0a, &cc);
1192 if (cc == 0x0101)
1193 scc_s = "IDE";
1194 else if (cc == 0x0106)
1195 scc_s = "SATA";
1196 else if (cc == 0x0104)
1197 scc_s = "RAID";
1198 else
1199 scc_s = "unknown";
1200
1201 dev_printk(KERN_INFO, &pdev->dev,
1202 "AHCI %02x%02x.%02x%02x "
1203 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1204 ,
1205
1206 (vers >> 24) & 0xff,
1207 (vers >> 16) & 0xff,
1208 (vers >> 8) & 0xff,
1209 vers & 0xff,
1210
1211 ((cap >> 8) & 0x1f) + 1,
1212 (cap & 0x1f) + 1,
1213 speed_s,
1214 impl,
1215 scc_s);
1216
1217 dev_printk(KERN_INFO, &pdev->dev,
1218 "flags: "
1219 "%s%s%s%s%s%s"
1220 "%s%s%s%s%s%s%s\n"
1221 ,
1222
1223 cap & (1 << 31) ? "64bit " : "",
1224 cap & (1 << 30) ? "ncq " : "",
1225 cap & (1 << 28) ? "ilck " : "",
1226 cap & (1 << 27) ? "stag " : "",
1227 cap & (1 << 26) ? "pm " : "",
1228 cap & (1 << 25) ? "led " : "",
1229
1230 cap & (1 << 24) ? "clo " : "",
1231 cap & (1 << 19) ? "nz " : "",
1232 cap & (1 << 18) ? "only " : "",
1233 cap & (1 << 17) ? "pmp " : "",
1234 cap & (1 << 15) ? "pio " : "",
1235 cap & (1 << 14) ? "slum " : "",
1236 cap & (1 << 13) ? "part " : ""
1237 );
1238 }
1239
1240 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1241 {
1242 static int printed_version;
1243 struct ata_probe_ent *probe_ent = NULL;
1244 struct ahci_host_priv *hpriv;
1245 unsigned long base;
1246 void __iomem *mmio_base;
1247 unsigned int board_idx = (unsigned int) ent->driver_data;
1248 int have_msi, pci_dev_busy = 0;
1249 int rc;
1250
1251 VPRINTK("ENTER\n");
1252
1253 if (!printed_version++)
1254 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1255
1256 rc = pci_enable_device(pdev);
1257 if (rc)
1258 return rc;
1259
1260 rc = pci_request_regions(pdev, DRV_NAME);
1261 if (rc) {
1262 pci_dev_busy = 1;
1263 goto err_out;
1264 }
1265
1266 if (pci_enable_msi(pdev) == 0)
1267 have_msi = 1;
1268 else {
1269 pci_intx(pdev, 1);
1270 have_msi = 0;
1271 }
1272
1273 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1274 if (probe_ent == NULL) {
1275 rc = -ENOMEM;
1276 goto err_out_msi;
1277 }
1278
1279 memset(probe_ent, 0, sizeof(*probe_ent));
1280 probe_ent->dev = pci_dev_to_dev(pdev);
1281 INIT_LIST_HEAD(&probe_ent->node);
1282
1283 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1284 if (mmio_base == NULL) {
1285 rc = -ENOMEM;
1286 goto err_out_free_ent;
1287 }
1288 base = (unsigned long) mmio_base;
1289
1290 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1291 if (!hpriv) {
1292 rc = -ENOMEM;
1293 goto err_out_iounmap;
1294 }
1295 memset(hpriv, 0, sizeof(*hpriv));
1296
1297 probe_ent->sht = ahci_port_info[board_idx].sht;
1298 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1299 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1300 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1301 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1302
1303 probe_ent->irq = pdev->irq;
1304 probe_ent->irq_flags = SA_SHIRQ;
1305 probe_ent->mmio_base = mmio_base;
1306 probe_ent->private_data = hpriv;
1307
1308 if (have_msi)
1309 hpriv->flags |= AHCI_FLAG_MSI;
1310
1311 /* JMicron-specific fixup: make sure we're in AHCI mode */
1312 if (pdev->vendor == 0x197b)
1313 pci_write_config_byte(pdev, 0x41, 0xa1);
1314
1315 /* initialize adapter */
1316 rc = ahci_host_init(probe_ent);
1317 if (rc)
1318 goto err_out_hpriv;
1319
1320 ahci_print_info(probe_ent);
1321
1322 /* FIXME: check ata_device_add return value */
1323 ata_device_add(probe_ent);
1324 kfree(probe_ent);
1325
1326 return 0;
1327
1328 err_out_hpriv:
1329 kfree(hpriv);
1330 err_out_iounmap:
1331 pci_iounmap(pdev, mmio_base);
1332 err_out_free_ent:
1333 kfree(probe_ent);
1334 err_out_msi:
1335 if (have_msi)
1336 pci_disable_msi(pdev);
1337 else
1338 pci_intx(pdev, 0);
1339 pci_release_regions(pdev);
1340 err_out:
1341 if (!pci_dev_busy)
1342 pci_disable_device(pdev);
1343 return rc;
1344 }
1345
1346 static void ahci_remove_one (struct pci_dev *pdev)
1347 {
1348 struct device *dev = pci_dev_to_dev(pdev);
1349 struct ata_host_set *host_set = dev_get_drvdata(dev);
1350 struct ahci_host_priv *hpriv = host_set->private_data;
1351 struct ata_port *ap;
1352 unsigned int i;
1353 int have_msi;
1354
1355 for (i = 0; i < host_set->n_ports; i++) {
1356 ap = host_set->ports[i];
1357
1358 scsi_remove_host(ap->host);
1359 }
1360
1361 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1362 free_irq(host_set->irq, host_set);
1363
1364 for (i = 0; i < host_set->n_ports; i++) {
1365 ap = host_set->ports[i];
1366
1367 ata_scsi_release(ap->host);
1368 scsi_host_put(ap->host);
1369 }
1370
1371 kfree(hpriv);
1372 pci_iounmap(pdev, host_set->mmio_base);
1373 kfree(host_set);
1374
1375 if (have_msi)
1376 pci_disable_msi(pdev);
1377 else
1378 pci_intx(pdev, 0);
1379 pci_release_regions(pdev);
1380 pci_disable_device(pdev);
1381 dev_set_drvdata(dev, NULL);
1382 }
1383
1384 static int __init ahci_init(void)
1385 {
1386 return pci_module_init(&ahci_pci_driver);
1387 }
1388
1389 static void __exit ahci_exit(void)
1390 {
1391 pci_unregister_driver(&ahci_pci_driver);
1392 }
1393
1394
1395 MODULE_AUTHOR("Jeff Garzik");
1396 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1397 MODULE_LICENSE("GPL");
1398 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1399 MODULE_VERSION(DRV_VERSION);
1400
1401 module_init(ahci_init);
1402 module_exit(ahci_exit);
Linux kernel - Deliverables
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