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[PATCH] libata-hp-prep: add prereset() method and implement ata_std_prereset()
[deliverable/linux.git] / drivers / scsi / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include <asm/io.h>
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "1.3"
52
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_MAX_CMDS = 32,
60 AHCI_CMD_SZ = 32,
61 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
62 AHCI_RX_FIS_SZ = 256,
63 AHCI_CMD_TBL_CDB = 0x40,
64 AHCI_CMD_TBL_HDR_SZ = 0x80,
65 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
66 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
67 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
68 AHCI_RX_FIS_SZ,
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
72 AHCI_CMD_PREFETCH = (1 << 7),
73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
75
76 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
78
79 board_ahci = 0,
80 board_ahci_vt8251 = 1,
81
82 /* global controller registers */
83 HOST_CAP = 0x00, /* host capabilities */
84 HOST_CTL = 0x04, /* global host control */
85 HOST_IRQ_STAT = 0x08, /* interrupt status */
86 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
87 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
88
89 /* HOST_CTL bits */
90 HOST_RESET = (1 << 0), /* reset controller; self-clear */
91 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
92 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
93
94 /* HOST_CAP bits */
95 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
96 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
97 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
98
99 /* registers for each SATA port */
100 PORT_LST_ADDR = 0x00, /* command list DMA addr */
101 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
102 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
103 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
104 PORT_IRQ_STAT = 0x10, /* interrupt status */
105 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
106 PORT_CMD = 0x18, /* port command */
107 PORT_TFDATA = 0x20, /* taskfile data */
108 PORT_SIG = 0x24, /* device TF signature */
109 PORT_CMD_ISSUE = 0x38, /* command issue */
110 PORT_SCR = 0x28, /* SATA phy register block */
111 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
112 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
113 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
114 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
115
116 /* PORT_IRQ_{STAT,MASK} bits */
117 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
118 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
119 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
120 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
121 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
122 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
123 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
124 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
125
126 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
127 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
128 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
129 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
130 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
131 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
132 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
133 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
134 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
135
136 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
137 PORT_IRQ_IF_ERR |
138 PORT_IRQ_CONNECT |
139 PORT_IRQ_UNK_FIS,
140 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
141 PORT_IRQ_TF_ERR |
142 PORT_IRQ_HBUS_DATA_ERR,
143 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
144 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
145 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
146
147 /* PORT_CMD bits */
148 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
149 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
150 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
151 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
152 PORT_CMD_CLO = (1 << 3), /* Command list override */
153 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
154 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
155 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
156
157 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
158 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
159 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
160
161 /* hpriv->flags bits */
162 AHCI_FLAG_MSI = (1 << 0),
163
164 /* ap->flags bits */
165 AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24),
166 };
167
168 struct ahci_cmd_hdr {
169 u32 opts;
170 u32 status;
171 u32 tbl_addr;
172 u32 tbl_addr_hi;
173 u32 reserved[4];
174 };
175
176 struct ahci_sg {
177 u32 addr;
178 u32 addr_hi;
179 u32 reserved;
180 u32 flags_size;
181 };
182
183 struct ahci_host_priv {
184 unsigned long flags;
185 u32 cap; /* cache of HOST_CAP register */
186 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
187 };
188
189 struct ahci_port_priv {
190 struct ahci_cmd_hdr *cmd_slot;
191 dma_addr_t cmd_slot_dma;
192 void *cmd_tbl;
193 dma_addr_t cmd_tbl_dma;
194 void *rx_fis;
195 dma_addr_t rx_fis_dma;
196 };
197
198 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
199 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
200 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
201 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
202 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
203 static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes);
204 static void ahci_irq_clear(struct ata_port *ap);
205 static int ahci_port_start(struct ata_port *ap);
206 static void ahci_port_stop(struct ata_port *ap);
207 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
208 static void ahci_qc_prep(struct ata_queued_cmd *qc);
209 static u8 ahci_check_status(struct ata_port *ap);
210 static void ahci_freeze(struct ata_port *ap);
211 static void ahci_thaw(struct ata_port *ap);
212 static void ahci_error_handler(struct ata_port *ap);
213 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
214 static void ahci_remove_one (struct pci_dev *pdev);
215
216 static struct scsi_host_template ahci_sht = {
217 .module = THIS_MODULE,
218 .name = DRV_NAME,
219 .ioctl = ata_scsi_ioctl,
220 .queuecommand = ata_scsi_queuecmd,
221 .change_queue_depth = ata_scsi_change_queue_depth,
222 .can_queue = AHCI_MAX_CMDS - 1,
223 .this_id = ATA_SHT_THIS_ID,
224 .sg_tablesize = AHCI_MAX_SG,
225 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
226 .emulated = ATA_SHT_EMULATED,
227 .use_clustering = AHCI_USE_CLUSTERING,
228 .proc_name = DRV_NAME,
229 .dma_boundary = AHCI_DMA_BOUNDARY,
230 .slave_configure = ata_scsi_slave_config,
231 .bios_param = ata_std_bios_param,
232 };
233
234 static const struct ata_port_operations ahci_ops = {
235 .port_disable = ata_port_disable,
236
237 .check_status = ahci_check_status,
238 .check_altstatus = ahci_check_status,
239 .dev_select = ata_noop_dev_select,
240
241 .tf_read = ahci_tf_read,
242
243 .probe_reset = ahci_probe_reset,
244
245 .qc_prep = ahci_qc_prep,
246 .qc_issue = ahci_qc_issue,
247
248 .irq_handler = ahci_interrupt,
249 .irq_clear = ahci_irq_clear,
250
251 .scr_read = ahci_scr_read,
252 .scr_write = ahci_scr_write,
253
254 .freeze = ahci_freeze,
255 .thaw = ahci_thaw,
256
257 .error_handler = ahci_error_handler,
258 .post_internal_cmd = ahci_post_internal_cmd,
259
260 .port_start = ahci_port_start,
261 .port_stop = ahci_port_stop,
262 };
263
264 static const struct ata_port_info ahci_port_info[] = {
265 /* board_ahci */
266 {
267 .sht = &ahci_sht,
268 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
269 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
270 .pio_mask = 0x1f, /* pio0-4 */
271 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
272 .port_ops = &ahci_ops,
273 },
274 /* board_ahci_vt8251 */
275 {
276 .sht = &ahci_sht,
277 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
278 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
279 AHCI_FLAG_RESET_NEEDS_CLO,
280 .pio_mask = 0x1f, /* pio0-4 */
281 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
282 .port_ops = &ahci_ops,
283 },
284 };
285
286 static const struct pci_device_id ahci_pci_tbl[] = {
287 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
288 board_ahci }, /* ICH6 */
289 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
290 board_ahci }, /* ICH6M */
291 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
292 board_ahci }, /* ICH7 */
293 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
294 board_ahci }, /* ICH7M */
295 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
296 board_ahci }, /* ICH7R */
297 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
298 board_ahci }, /* ULi M5288 */
299 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
300 board_ahci }, /* ESB2 */
301 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
302 board_ahci }, /* ESB2 */
303 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
304 board_ahci }, /* ESB2 */
305 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
306 board_ahci }, /* ICH7-M DH */
307 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
308 board_ahci }, /* ICH8 */
309 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
310 board_ahci }, /* ICH8 */
311 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
312 board_ahci }, /* ICH8 */
313 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
314 board_ahci }, /* ICH8M */
315 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
316 board_ahci }, /* ICH8M */
317 { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
318 board_ahci }, /* JMicron JMB360 */
319 { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
320 board_ahci }, /* JMicron JMB363 */
321 { PCI_VENDOR_ID_ATI, 0x4380, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
322 board_ahci }, /* ATI SB600 non-raid */
323 { PCI_VENDOR_ID_ATI, 0x4381, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
324 board_ahci }, /* ATI SB600 raid */
325 { PCI_VENDOR_ID_VIA, 0x3349, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
326 board_ahci_vt8251 }, /* VIA VT8251 */
327 { } /* terminate list */
328 };
329
330
331 static struct pci_driver ahci_pci_driver = {
332 .name = DRV_NAME,
333 .id_table = ahci_pci_tbl,
334 .probe = ahci_init_one,
335 .remove = ahci_remove_one,
336 };
337
338
339 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
340 {
341 return base + 0x100 + (port * 0x80);
342 }
343
344 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
345 {
346 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
347 }
348
349 static int ahci_port_start(struct ata_port *ap)
350 {
351 struct device *dev = ap->host_set->dev;
352 struct ahci_host_priv *hpriv = ap->host_set->private_data;
353 struct ahci_port_priv *pp;
354 void __iomem *mmio = ap->host_set->mmio_base;
355 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
356 void *mem;
357 dma_addr_t mem_dma;
358 int rc;
359
360 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
361 if (!pp)
362 return -ENOMEM;
363 memset(pp, 0, sizeof(*pp));
364
365 rc = ata_pad_alloc(ap, dev);
366 if (rc) {
367 kfree(pp);
368 return rc;
369 }
370
371 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
372 if (!mem) {
373 ata_pad_free(ap, dev);
374 kfree(pp);
375 return -ENOMEM;
376 }
377 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
378
379 /*
380 * First item in chunk of DMA memory: 32-slot command table,
381 * 32 bytes each in size
382 */
383 pp->cmd_slot = mem;
384 pp->cmd_slot_dma = mem_dma;
385
386 mem += AHCI_CMD_SLOT_SZ;
387 mem_dma += AHCI_CMD_SLOT_SZ;
388
389 /*
390 * Second item: Received-FIS area
391 */
392 pp->rx_fis = mem;
393 pp->rx_fis_dma = mem_dma;
394
395 mem += AHCI_RX_FIS_SZ;
396 mem_dma += AHCI_RX_FIS_SZ;
397
398 /*
399 * Third item: data area for storing a single command
400 * and its scatter-gather table
401 */
402 pp->cmd_tbl = mem;
403 pp->cmd_tbl_dma = mem_dma;
404
405 ap->private_data = pp;
406
407 if (hpriv->cap & HOST_CAP_64)
408 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
409 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
410 readl(port_mmio + PORT_LST_ADDR); /* flush */
411
412 if (hpriv->cap & HOST_CAP_64)
413 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
414 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
415 readl(port_mmio + PORT_FIS_ADDR); /* flush */
416
417 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
418 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
419 PORT_CMD_START, port_mmio + PORT_CMD);
420 readl(port_mmio + PORT_CMD); /* flush */
421
422 return 0;
423 }
424
425
426 static void ahci_port_stop(struct ata_port *ap)
427 {
428 struct device *dev = ap->host_set->dev;
429 struct ahci_port_priv *pp = ap->private_data;
430 void __iomem *mmio = ap->host_set->mmio_base;
431 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
432 u32 tmp;
433
434 tmp = readl(port_mmio + PORT_CMD);
435 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
436 writel(tmp, port_mmio + PORT_CMD);
437 readl(port_mmio + PORT_CMD); /* flush */
438
439 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
440 * this is slightly incorrect.
441 */
442 msleep(500);
443
444 ap->private_data = NULL;
445 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
446 pp->cmd_slot, pp->cmd_slot_dma);
447 ata_pad_free(ap, dev);
448 kfree(pp);
449 }
450
451 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
452 {
453 unsigned int sc_reg;
454
455 switch (sc_reg_in) {
456 case SCR_STATUS: sc_reg = 0; break;
457 case SCR_CONTROL: sc_reg = 1; break;
458 case SCR_ERROR: sc_reg = 2; break;
459 case SCR_ACTIVE: sc_reg = 3; break;
460 default:
461 return 0xffffffffU;
462 }
463
464 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
465 }
466
467
468 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
469 u32 val)
470 {
471 unsigned int sc_reg;
472
473 switch (sc_reg_in) {
474 case SCR_STATUS: sc_reg = 0; break;
475 case SCR_CONTROL: sc_reg = 1; break;
476 case SCR_ERROR: sc_reg = 2; break;
477 case SCR_ACTIVE: sc_reg = 3; break;
478 default:
479 return;
480 }
481
482 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
483 }
484
485 static int ahci_stop_engine(struct ata_port *ap)
486 {
487 void __iomem *mmio = ap->host_set->mmio_base;
488 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
489 int work;
490 u32 tmp;
491
492 tmp = readl(port_mmio + PORT_CMD);
493 tmp &= ~PORT_CMD_START;
494 writel(tmp, port_mmio + PORT_CMD);
495
496 /* wait for engine to stop. TODO: this could be
497 * as long as 500 msec
498 */
499 work = 1000;
500 while (work-- > 0) {
501 tmp = readl(port_mmio + PORT_CMD);
502 if ((tmp & PORT_CMD_LIST_ON) == 0)
503 return 0;
504 udelay(10);
505 }
506
507 return -EIO;
508 }
509
510 static void ahci_start_engine(struct ata_port *ap)
511 {
512 void __iomem *mmio = ap->host_set->mmio_base;
513 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
514 u32 tmp;
515
516 tmp = readl(port_mmio + PORT_CMD);
517 tmp |= PORT_CMD_START;
518 writel(tmp, port_mmio + PORT_CMD);
519 readl(port_mmio + PORT_CMD); /* flush */
520 }
521
522 static unsigned int ahci_dev_classify(struct ata_port *ap)
523 {
524 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
525 struct ata_taskfile tf;
526 u32 tmp;
527
528 tmp = readl(port_mmio + PORT_SIG);
529 tf.lbah = (tmp >> 24) & 0xff;
530 tf.lbam = (tmp >> 16) & 0xff;
531 tf.lbal = (tmp >> 8) & 0xff;
532 tf.nsect = (tmp) & 0xff;
533
534 return ata_dev_classify(&tf);
535 }
536
537 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
538 u32 opts)
539 {
540 dma_addr_t cmd_tbl_dma;
541
542 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
543
544 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
545 pp->cmd_slot[tag].status = 0;
546 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
547 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
548 }
549
550 static int ahci_clo(struct ata_port *ap)
551 {
552 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
553 struct ahci_host_priv *hpriv = ap->host_set->private_data;
554 u32 tmp;
555
556 if (!(hpriv->cap & HOST_CAP_CLO))
557 return -EOPNOTSUPP;
558
559 tmp = readl(port_mmio + PORT_CMD);
560 tmp |= PORT_CMD_CLO;
561 writel(tmp, port_mmio + PORT_CMD);
562
563 tmp = ata_wait_register(port_mmio + PORT_CMD,
564 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
565 if (tmp & PORT_CMD_CLO)
566 return -EIO;
567
568 return 0;
569 }
570
571 static int ahci_softreset(struct ata_port *ap, unsigned int *class)
572 {
573 struct ahci_port_priv *pp = ap->private_data;
574 void __iomem *mmio = ap->host_set->mmio_base;
575 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
576 const u32 cmd_fis_len = 5; /* five dwords */
577 const char *reason = NULL;
578 struct ata_taskfile tf;
579 u32 tmp;
580 u8 *fis;
581 int rc;
582
583 DPRINTK("ENTER\n");
584
585 if (ata_port_offline(ap)) {
586 DPRINTK("PHY reports no device\n");
587 *class = ATA_DEV_NONE;
588 return 0;
589 }
590
591 /* prepare for SRST (AHCI-1.1 10.4.1) */
592 rc = ahci_stop_engine(ap);
593 if (rc) {
594 reason = "failed to stop engine";
595 goto fail_restart;
596 }
597
598 /* check BUSY/DRQ, perform Command List Override if necessary */
599 ahci_tf_read(ap, &tf);
600 if (tf.command & (ATA_BUSY | ATA_DRQ)) {
601 rc = ahci_clo(ap);
602
603 if (rc == -EOPNOTSUPP) {
604 reason = "port busy but CLO unavailable";
605 goto fail_restart;
606 } else if (rc) {
607 reason = "port busy but CLO failed";
608 goto fail_restart;
609 }
610 }
611
612 /* restart engine */
613 ahci_start_engine(ap);
614
615 ata_tf_init(ap->device, &tf);
616 fis = pp->cmd_tbl;
617
618 /* issue the first D2H Register FIS */
619 ahci_fill_cmd_slot(pp, 0,
620 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
621
622 tf.ctl |= ATA_SRST;
623 ata_tf_to_fis(&tf, fis, 0);
624 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
625
626 writel(1, port_mmio + PORT_CMD_ISSUE);
627
628 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
629 if (tmp & 0x1) {
630 rc = -EIO;
631 reason = "1st FIS failed";
632 goto fail;
633 }
634
635 /* spec says at least 5us, but be generous and sleep for 1ms */
636 msleep(1);
637
638 /* issue the second D2H Register FIS */
639 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
640
641 tf.ctl &= ~ATA_SRST;
642 ata_tf_to_fis(&tf, fis, 0);
643 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
644
645 writel(1, port_mmio + PORT_CMD_ISSUE);
646 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
647
648 /* spec mandates ">= 2ms" before checking status.
649 * We wait 150ms, because that was the magic delay used for
650 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
651 * between when the ATA command register is written, and then
652 * status is checked. Because waiting for "a while" before
653 * checking status is fine, post SRST, we perform this magic
654 * delay here as well.
655 */
656 msleep(150);
657
658 *class = ATA_DEV_NONE;
659 if (ata_port_online(ap)) {
660 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
661 rc = -EIO;
662 reason = "device not ready";
663 goto fail;
664 }
665 *class = ahci_dev_classify(ap);
666 }
667
668 DPRINTK("EXIT, class=%u\n", *class);
669 return 0;
670
671 fail_restart:
672 ahci_start_engine(ap);
673 fail:
674 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
675 return rc;
676 }
677
678 static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
679 {
680 int rc;
681
682 DPRINTK("ENTER\n");
683
684 ahci_stop_engine(ap);
685 rc = sata_std_hardreset(ap, class);
686 ahci_start_engine(ap);
687
688 if (rc == 0 && ata_port_online(ap))
689 *class = ahci_dev_classify(ap);
690 if (*class == ATA_DEV_UNKNOWN)
691 *class = ATA_DEV_NONE;
692
693 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
694 return rc;
695 }
696
697 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
698 {
699 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
700 u32 new_tmp, tmp;
701
702 ata_std_postreset(ap, class);
703
704 /* Make sure port's ATAPI bit is set appropriately */
705 new_tmp = tmp = readl(port_mmio + PORT_CMD);
706 if (*class == ATA_DEV_ATAPI)
707 new_tmp |= PORT_CMD_ATAPI;
708 else
709 new_tmp &= ~PORT_CMD_ATAPI;
710 if (new_tmp != tmp) {
711 writel(new_tmp, port_mmio + PORT_CMD);
712 readl(port_mmio + PORT_CMD); /* flush */
713 }
714 }
715
716 static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes)
717 {
718 if ((ap->flags & AHCI_FLAG_RESET_NEEDS_CLO) &&
719 (ata_busy_wait(ap, ATA_BUSY, 1000) & ATA_BUSY)) {
720 /* ATA_BUSY hasn't cleared, so send a CLO */
721 ahci_clo(ap);
722 }
723
724 return ata_drive_probe_reset(ap, ata_std_probeinit,
725 ahci_softreset, ahci_hardreset,
726 ahci_postreset, classes);
727 }
728
729 static u8 ahci_check_status(struct ata_port *ap)
730 {
731 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
732
733 return readl(mmio + PORT_TFDATA) & 0xFF;
734 }
735
736 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
737 {
738 struct ahci_port_priv *pp = ap->private_data;
739 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
740
741 ata_tf_from_fis(d2h_fis, tf);
742 }
743
744 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
745 {
746 struct scatterlist *sg;
747 struct ahci_sg *ahci_sg;
748 unsigned int n_sg = 0;
749
750 VPRINTK("ENTER\n");
751
752 /*
753 * Next, the S/G list.
754 */
755 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
756 ata_for_each_sg(sg, qc) {
757 dma_addr_t addr = sg_dma_address(sg);
758 u32 sg_len = sg_dma_len(sg);
759
760 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
761 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
762 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
763
764 ahci_sg++;
765 n_sg++;
766 }
767
768 return n_sg;
769 }
770
771 static void ahci_qc_prep(struct ata_queued_cmd *qc)
772 {
773 struct ata_port *ap = qc->ap;
774 struct ahci_port_priv *pp = ap->private_data;
775 int is_atapi = is_atapi_taskfile(&qc->tf);
776 void *cmd_tbl;
777 u32 opts;
778 const u32 cmd_fis_len = 5; /* five dwords */
779 unsigned int n_elem;
780
781 /*
782 * Fill in command table information. First, the header,
783 * a SATA Register - Host to Device command FIS.
784 */
785 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
786
787 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
788 if (is_atapi) {
789 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
790 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
791 }
792
793 n_elem = 0;
794 if (qc->flags & ATA_QCFLAG_DMAMAP)
795 n_elem = ahci_fill_sg(qc, cmd_tbl);
796
797 /*
798 * Fill in command slot information.
799 */
800 opts = cmd_fis_len | n_elem << 16;
801 if (qc->tf.flags & ATA_TFLAG_WRITE)
802 opts |= AHCI_CMD_WRITE;
803 if (is_atapi)
804 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
805
806 ahci_fill_cmd_slot(pp, qc->tag, opts);
807 }
808
809 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
810 {
811 struct ahci_port_priv *pp = ap->private_data;
812 struct ata_eh_info *ehi = &ap->eh_info;
813 unsigned int err_mask = 0, action = 0;
814 struct ata_queued_cmd *qc;
815 u32 serror;
816
817 ata_ehi_clear_desc(ehi);
818
819 /* AHCI needs SError cleared; otherwise, it might lock up */
820 serror = ahci_scr_read(ap, SCR_ERROR);
821 ahci_scr_write(ap, SCR_ERROR, serror);
822
823 /* analyze @irq_stat */
824 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
825
826 if (irq_stat & PORT_IRQ_TF_ERR)
827 err_mask |= AC_ERR_DEV;
828
829 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
830 err_mask |= AC_ERR_HOST_BUS;
831 action |= ATA_EH_SOFTRESET;
832 }
833
834 if (irq_stat & PORT_IRQ_IF_ERR) {
835 err_mask |= AC_ERR_ATA_BUS;
836 action |= ATA_EH_SOFTRESET;
837 ata_ehi_push_desc(ehi, ", interface fatal error");
838 }
839
840 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
841 err_mask |= AC_ERR_ATA_BUS;
842 action |= ATA_EH_SOFTRESET;
843 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
844 "connection status changed" : "PHY RDY changed");
845 }
846
847 if (irq_stat & PORT_IRQ_UNK_FIS) {
848 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
849
850 err_mask |= AC_ERR_HSM;
851 action |= ATA_EH_SOFTRESET;
852 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
853 unk[0], unk[1], unk[2], unk[3]);
854 }
855
856 /* okay, let's hand over to EH */
857 ehi->serror |= serror;
858 ehi->action |= action;
859
860 qc = ata_qc_from_tag(ap, ap->active_tag);
861 if (qc)
862 qc->err_mask |= err_mask;
863 else
864 ehi->err_mask |= err_mask;
865
866 if (irq_stat & PORT_IRQ_FREEZE)
867 ata_port_freeze(ap);
868 else
869 ata_port_abort(ap);
870 }
871
872 static void ahci_host_intr(struct ata_port *ap)
873 {
874 void __iomem *mmio = ap->host_set->mmio_base;
875 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
876 struct ata_eh_info *ehi = &ap->eh_info;
877 u32 status, qc_active;
878 int rc;
879
880 status = readl(port_mmio + PORT_IRQ_STAT);
881 writel(status, port_mmio + PORT_IRQ_STAT);
882
883 if (unlikely(status & PORT_IRQ_ERROR)) {
884 ahci_error_intr(ap, status);
885 return;
886 }
887
888 if (ap->sactive)
889 qc_active = readl(port_mmio + PORT_SCR_ACT);
890 else
891 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
892
893 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
894 if (rc > 0)
895 return;
896 if (rc < 0) {
897 ehi->err_mask |= AC_ERR_HSM;
898 ehi->action |= ATA_EH_SOFTRESET;
899 ata_port_freeze(ap);
900 return;
901 }
902
903 /* hmmm... a spurious interupt */
904
905 /* some devices send D2H reg with I bit set during NCQ command phase */
906 if (ap->sactive && status & PORT_IRQ_D2H_REG_FIS)
907 return;
908
909 /* ignore interim PIO setup fis interrupts */
910 if (ata_tag_valid(ap->active_tag)) {
911 struct ata_queued_cmd *qc =
912 ata_qc_from_tag(ap, ap->active_tag);
913
914 if (qc && qc->tf.protocol == ATA_PROT_PIO &&
915 (status & PORT_IRQ_PIOS_FIS))
916 return;
917 }
918
919 if (ata_ratelimit())
920 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
921 "(irq_stat 0x%x active_tag %d sactive 0x%x)\n",
922 status, ap->active_tag, ap->sactive);
923 }
924
925 static void ahci_irq_clear(struct ata_port *ap)
926 {
927 /* TODO */
928 }
929
930 static irqreturn_t ahci_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
931 {
932 struct ata_host_set *host_set = dev_instance;
933 struct ahci_host_priv *hpriv;
934 unsigned int i, handled = 0;
935 void __iomem *mmio;
936 u32 irq_stat, irq_ack = 0;
937
938 VPRINTK("ENTER\n");
939
940 hpriv = host_set->private_data;
941 mmio = host_set->mmio_base;
942
943 /* sigh. 0xffffffff is a valid return from h/w */
944 irq_stat = readl(mmio + HOST_IRQ_STAT);
945 irq_stat &= hpriv->port_map;
946 if (!irq_stat)
947 return IRQ_NONE;
948
949 spin_lock(&host_set->lock);
950
951 for (i = 0; i < host_set->n_ports; i++) {
952 struct ata_port *ap;
953
954 if (!(irq_stat & (1 << i)))
955 continue;
956
957 ap = host_set->ports[i];
958 if (ap) {
959 ahci_host_intr(ap);
960 VPRINTK("port %u\n", i);
961 } else {
962 VPRINTK("port %u (no irq)\n", i);
963 if (ata_ratelimit())
964 dev_printk(KERN_WARNING, host_set->dev,
965 "interrupt on disabled port %u\n", i);
966 }
967
968 irq_ack |= (1 << i);
969 }
970
971 if (irq_ack) {
972 writel(irq_ack, mmio + HOST_IRQ_STAT);
973 handled = 1;
974 }
975
976 spin_unlock(&host_set->lock);
977
978 VPRINTK("EXIT\n");
979
980 return IRQ_RETVAL(handled);
981 }
982
983 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
984 {
985 struct ata_port *ap = qc->ap;
986 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
987
988 if (qc->tf.protocol == ATA_PROT_NCQ)
989 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
990 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
991 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
992
993 return 0;
994 }
995
996 static void ahci_freeze(struct ata_port *ap)
997 {
998 void __iomem *mmio = ap->host_set->mmio_base;
999 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1000
1001 /* turn IRQ off */
1002 writel(0, port_mmio + PORT_IRQ_MASK);
1003 }
1004
1005 static void ahci_thaw(struct ata_port *ap)
1006 {
1007 void __iomem *mmio = ap->host_set->mmio_base;
1008 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1009 u32 tmp;
1010
1011 /* clear IRQ */
1012 tmp = readl(port_mmio + PORT_IRQ_STAT);
1013 writel(tmp, port_mmio + PORT_IRQ_STAT);
1014 writel(1 << ap->id, mmio + HOST_IRQ_STAT);
1015
1016 /* turn IRQ back on */
1017 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1018 }
1019
1020 static void ahci_error_handler(struct ata_port *ap)
1021 {
1022 if (!(ap->flags & ATA_FLAG_FROZEN)) {
1023 /* restart engine */
1024 ahci_stop_engine(ap);
1025 ahci_start_engine(ap);
1026 }
1027
1028 /* perform recovery */
1029 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1030 ahci_postreset);
1031 }
1032
1033 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1034 {
1035 struct ata_port *ap = qc->ap;
1036
1037 if (qc->flags & ATA_QCFLAG_FAILED)
1038 qc->err_mask |= AC_ERR_OTHER;
1039
1040 if (qc->err_mask) {
1041 /* make DMA engine forget about the failed command */
1042 ahci_stop_engine(ap);
1043 ahci_start_engine(ap);
1044 }
1045 }
1046
1047 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1048 unsigned int port_idx)
1049 {
1050 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1051 base = ahci_port_base_ul(base, port_idx);
1052 VPRINTK("base now==0x%lx\n", base);
1053
1054 port->cmd_addr = base;
1055 port->scr_addr = base + PORT_SCR;
1056
1057 VPRINTK("EXIT\n");
1058 }
1059
1060 static int ahci_host_init(struct ata_probe_ent *probe_ent)
1061 {
1062 struct ahci_host_priv *hpriv = probe_ent->private_data;
1063 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1064 void __iomem *mmio = probe_ent->mmio_base;
1065 u32 tmp, cap_save;
1066 unsigned int i, j, using_dac;
1067 int rc;
1068 void __iomem *port_mmio;
1069
1070 cap_save = readl(mmio + HOST_CAP);
1071 cap_save &= ( (1<<28) | (1<<17) );
1072 cap_save |= (1 << 27);
1073
1074 /* global controller reset */
1075 tmp = readl(mmio + HOST_CTL);
1076 if ((tmp & HOST_RESET) == 0) {
1077 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1078 readl(mmio + HOST_CTL); /* flush */
1079 }
1080
1081 /* reset must complete within 1 second, or
1082 * the hardware should be considered fried.
1083 */
1084 ssleep(1);
1085
1086 tmp = readl(mmio + HOST_CTL);
1087 if (tmp & HOST_RESET) {
1088 dev_printk(KERN_ERR, &pdev->dev,
1089 "controller reset failed (0x%x)\n", tmp);
1090 return -EIO;
1091 }
1092
1093 writel(HOST_AHCI_EN, mmio + HOST_CTL);
1094 (void) readl(mmio + HOST_CTL); /* flush */
1095 writel(cap_save, mmio + HOST_CAP);
1096 writel(0xf, mmio + HOST_PORTS_IMPL);
1097 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
1098
1099 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1100 u16 tmp16;
1101
1102 pci_read_config_word(pdev, 0x92, &tmp16);
1103 tmp16 |= 0xf;
1104 pci_write_config_word(pdev, 0x92, tmp16);
1105 }
1106
1107 hpriv->cap = readl(mmio + HOST_CAP);
1108 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1109 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1110
1111 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1112 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1113
1114 using_dac = hpriv->cap & HOST_CAP_64;
1115 if (using_dac &&
1116 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1117 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1118 if (rc) {
1119 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1120 if (rc) {
1121 dev_printk(KERN_ERR, &pdev->dev,
1122 "64-bit DMA enable failed\n");
1123 return rc;
1124 }
1125 }
1126 } else {
1127 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1128 if (rc) {
1129 dev_printk(KERN_ERR, &pdev->dev,
1130 "32-bit DMA enable failed\n");
1131 return rc;
1132 }
1133 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1134 if (rc) {
1135 dev_printk(KERN_ERR, &pdev->dev,
1136 "32-bit consistent DMA enable failed\n");
1137 return rc;
1138 }
1139 }
1140
1141 for (i = 0; i < probe_ent->n_ports; i++) {
1142 #if 0 /* BIOSen initialize this incorrectly */
1143 if (!(hpriv->port_map & (1 << i)))
1144 continue;
1145 #endif
1146
1147 port_mmio = ahci_port_base(mmio, i);
1148 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
1149
1150 ahci_setup_port(&probe_ent->port[i],
1151 (unsigned long) mmio, i);
1152
1153 /* make sure port is not active */
1154 tmp = readl(port_mmio + PORT_CMD);
1155 VPRINTK("PORT_CMD 0x%x\n", tmp);
1156 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1157 PORT_CMD_FIS_RX | PORT_CMD_START)) {
1158 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1159 PORT_CMD_FIS_RX | PORT_CMD_START);
1160 writel(tmp, port_mmio + PORT_CMD);
1161 readl(port_mmio + PORT_CMD); /* flush */
1162
1163 /* spec says 500 msecs for each bit, so
1164 * this is slightly incorrect.
1165 */
1166 msleep(500);
1167 }
1168
1169 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
1170
1171 j = 0;
1172 while (j < 100) {
1173 msleep(10);
1174 tmp = readl(port_mmio + PORT_SCR_STAT);
1175 if ((tmp & 0xf) == 0x3)
1176 break;
1177 j++;
1178 }
1179
1180 tmp = readl(port_mmio + PORT_SCR_ERR);
1181 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1182 writel(tmp, port_mmio + PORT_SCR_ERR);
1183
1184 /* ack any pending irq events for this port */
1185 tmp = readl(port_mmio + PORT_IRQ_STAT);
1186 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1187 if (tmp)
1188 writel(tmp, port_mmio + PORT_IRQ_STAT);
1189
1190 writel(1 << i, mmio + HOST_IRQ_STAT);
1191 }
1192
1193 tmp = readl(mmio + HOST_CTL);
1194 VPRINTK("HOST_CTL 0x%x\n", tmp);
1195 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1196 tmp = readl(mmio + HOST_CTL);
1197 VPRINTK("HOST_CTL 0x%x\n", tmp);
1198
1199 pci_set_master(pdev);
1200
1201 return 0;
1202 }
1203
1204 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1205 {
1206 struct ahci_host_priv *hpriv = probe_ent->private_data;
1207 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1208 void __iomem *mmio = probe_ent->mmio_base;
1209 u32 vers, cap, impl, speed;
1210 const char *speed_s;
1211 u16 cc;
1212 const char *scc_s;
1213
1214 vers = readl(mmio + HOST_VERSION);
1215 cap = hpriv->cap;
1216 impl = hpriv->port_map;
1217
1218 speed = (cap >> 20) & 0xf;
1219 if (speed == 1)
1220 speed_s = "1.5";
1221 else if (speed == 2)
1222 speed_s = "3";
1223 else
1224 speed_s = "?";
1225
1226 pci_read_config_word(pdev, 0x0a, &cc);
1227 if (cc == 0x0101)
1228 scc_s = "IDE";
1229 else if (cc == 0x0106)
1230 scc_s = "SATA";
1231 else if (cc == 0x0104)
1232 scc_s = "RAID";
1233 else
1234 scc_s = "unknown";
1235
1236 dev_printk(KERN_INFO, &pdev->dev,
1237 "AHCI %02x%02x.%02x%02x "
1238 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1239 ,
1240
1241 (vers >> 24) & 0xff,
1242 (vers >> 16) & 0xff,
1243 (vers >> 8) & 0xff,
1244 vers & 0xff,
1245
1246 ((cap >> 8) & 0x1f) + 1,
1247 (cap & 0x1f) + 1,
1248 speed_s,
1249 impl,
1250 scc_s);
1251
1252 dev_printk(KERN_INFO, &pdev->dev,
1253 "flags: "
1254 "%s%s%s%s%s%s"
1255 "%s%s%s%s%s%s%s\n"
1256 ,
1257
1258 cap & (1 << 31) ? "64bit " : "",
1259 cap & (1 << 30) ? "ncq " : "",
1260 cap & (1 << 28) ? "ilck " : "",
1261 cap & (1 << 27) ? "stag " : "",
1262 cap & (1 << 26) ? "pm " : "",
1263 cap & (1 << 25) ? "led " : "",
1264
1265 cap & (1 << 24) ? "clo " : "",
1266 cap & (1 << 19) ? "nz " : "",
1267 cap & (1 << 18) ? "only " : "",
1268 cap & (1 << 17) ? "pmp " : "",
1269 cap & (1 << 15) ? "pio " : "",
1270 cap & (1 << 14) ? "slum " : "",
1271 cap & (1 << 13) ? "part " : ""
1272 );
1273 }
1274
1275 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1276 {
1277 static int printed_version;
1278 struct ata_probe_ent *probe_ent = NULL;
1279 struct ahci_host_priv *hpriv;
1280 unsigned long base;
1281 void __iomem *mmio_base;
1282 unsigned int board_idx = (unsigned int) ent->driver_data;
1283 int have_msi, pci_dev_busy = 0;
1284 int rc;
1285
1286 VPRINTK("ENTER\n");
1287
1288 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1289
1290 if (!printed_version++)
1291 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1292
1293 rc = pci_enable_device(pdev);
1294 if (rc)
1295 return rc;
1296
1297 rc = pci_request_regions(pdev, DRV_NAME);
1298 if (rc) {
1299 pci_dev_busy = 1;
1300 goto err_out;
1301 }
1302
1303 if (pci_enable_msi(pdev) == 0)
1304 have_msi = 1;
1305 else {
1306 pci_intx(pdev, 1);
1307 have_msi = 0;
1308 }
1309
1310 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1311 if (probe_ent == NULL) {
1312 rc = -ENOMEM;
1313 goto err_out_msi;
1314 }
1315
1316 memset(probe_ent, 0, sizeof(*probe_ent));
1317 probe_ent->dev = pci_dev_to_dev(pdev);
1318 INIT_LIST_HEAD(&probe_ent->node);
1319
1320 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1321 if (mmio_base == NULL) {
1322 rc = -ENOMEM;
1323 goto err_out_free_ent;
1324 }
1325 base = (unsigned long) mmio_base;
1326
1327 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1328 if (!hpriv) {
1329 rc = -ENOMEM;
1330 goto err_out_iounmap;
1331 }
1332 memset(hpriv, 0, sizeof(*hpriv));
1333
1334 probe_ent->sht = ahci_port_info[board_idx].sht;
1335 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1336 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1337 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1338 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1339
1340 probe_ent->irq = pdev->irq;
1341 probe_ent->irq_flags = SA_SHIRQ;
1342 probe_ent->mmio_base = mmio_base;
1343 probe_ent->private_data = hpriv;
1344
1345 if (have_msi)
1346 hpriv->flags |= AHCI_FLAG_MSI;
1347
1348 /* JMicron-specific fixup: make sure we're in AHCI mode */
1349 if (pdev->vendor == 0x197b)
1350 pci_write_config_byte(pdev, 0x41, 0xa1);
1351
1352 /* initialize adapter */
1353 rc = ahci_host_init(probe_ent);
1354 if (rc)
1355 goto err_out_hpriv;
1356
1357 if (hpriv->cap & HOST_CAP_NCQ)
1358 probe_ent->host_flags |= ATA_FLAG_NCQ;
1359
1360 ahci_print_info(probe_ent);
1361
1362 /* FIXME: check ata_device_add return value */
1363 ata_device_add(probe_ent);
1364 kfree(probe_ent);
1365
1366 return 0;
1367
1368 err_out_hpriv:
1369 kfree(hpriv);
1370 err_out_iounmap:
1371 pci_iounmap(pdev, mmio_base);
1372 err_out_free_ent:
1373 kfree(probe_ent);
1374 err_out_msi:
1375 if (have_msi)
1376 pci_disable_msi(pdev);
1377 else
1378 pci_intx(pdev, 0);
1379 pci_release_regions(pdev);
1380 err_out:
1381 if (!pci_dev_busy)
1382 pci_disable_device(pdev);
1383 return rc;
1384 }
1385
1386 static void ahci_remove_one (struct pci_dev *pdev)
1387 {
1388 struct device *dev = pci_dev_to_dev(pdev);
1389 struct ata_host_set *host_set = dev_get_drvdata(dev);
1390 struct ahci_host_priv *hpriv = host_set->private_data;
1391 struct ata_port *ap;
1392 unsigned int i;
1393 int have_msi;
1394
1395 for (i = 0; i < host_set->n_ports; i++) {
1396 ap = host_set->ports[i];
1397
1398 scsi_remove_host(ap->host);
1399 }
1400
1401 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1402 free_irq(host_set->irq, host_set);
1403
1404 for (i = 0; i < host_set->n_ports; i++) {
1405 ap = host_set->ports[i];
1406
1407 ata_scsi_release(ap->host);
1408 scsi_host_put(ap->host);
1409 }
1410
1411 kfree(hpriv);
1412 pci_iounmap(pdev, host_set->mmio_base);
1413 kfree(host_set);
1414
1415 if (have_msi)
1416 pci_disable_msi(pdev);
1417 else
1418 pci_intx(pdev, 0);
1419 pci_release_regions(pdev);
1420 pci_disable_device(pdev);
1421 dev_set_drvdata(dev, NULL);
1422 }
1423
1424 static int __init ahci_init(void)
1425 {
1426 return pci_module_init(&ahci_pci_driver);
1427 }
1428
1429 static void __exit ahci_exit(void)
1430 {
1431 pci_unregister_driver(&ahci_pci_driver);
1432 }
1433
1434
1435 MODULE_AUTHOR("Jeff Garzik");
1436 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1437 MODULE_LICENSE("GPL");
1438 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1439 MODULE_VERSION(DRV_VERSION);
1440
1441 module_init(ahci_init);
1442 module_exit(ahci_exit);
Linux kernel - Deliverables
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