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[PATCH] ata_piix: convert to new EH
[deliverable/linux.git] / drivers / scsi / ata_piix.c
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "1.10"
97
98 enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
102 PIIX_SCC = 0x0A, /* sub-class code register */
103
104 PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */
105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108 PIIX_FLAG_COMBINED = (1 << 29), /* combined mode possible */
109 /* ICH6/7 use different scheme for map value */
110 PIIX_FLAG_COMBINED_ICH6 = PIIX_FLAG_COMBINED | (1 << 30),
111
112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
114 */
115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
121 /* controller IDs */
122 piix4_pata = 0,
123 ich5_pata = 1,
124 ich5_sata = 2,
125 esb_sata = 3,
126 ich6_sata = 4,
127 ich6_sata_ahci = 5,
128 ich6m_sata_ahci = 6,
129
130 /* constants for mapping table */
131 P0 = 0, /* port 0 */
132 P1 = 1, /* port 1 */
133 P2 = 2, /* port 2 */
134 P3 = 3, /* port 3 */
135 IDE = -1, /* IDE */
136 NA = -2, /* not avaliable */
137 RV = -3, /* reserved */
138
139 PIIX_AHCI_DEVICE = 6,
140 };
141
142 struct piix_map_db {
143 const u32 mask;
144 const int map[][4];
145 };
146
147 static int piix_init_one (struct pci_dev *pdev,
148 const struct pci_device_id *ent);
149
150 static int piix_pata_probe_reset(struct ata_port *ap, unsigned int *classes);
151 static int piix_sata_probe_reset(struct ata_port *ap, unsigned int *classes);
152 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
153 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
154
155 static unsigned int in_module_init = 1;
156
157 static const struct pci_device_id piix_pci_tbl[] = {
158 #ifdef ATA_ENABLE_PATA
159 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
160 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
161 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
162 #endif
163
164 /* NOTE: The following PCI ids must be kept in sync with the
165 * list in drivers/pci/quirks.c.
166 */
167
168 /* 82801EB (ICH5) */
169 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
170 /* 82801EB (ICH5) */
171 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
172 /* 6300ESB (ICH5 variant with broken PCS present bits) */
173 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
174 /* 6300ESB pretending RAID */
175 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
176 /* 82801FB/FW (ICH6/ICH6W) */
177 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
178 /* 82801FR/FRW (ICH6R/ICH6RW) */
179 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
180 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
181 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
182 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
183 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
184 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
185 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
186 /* Enterprise Southbridge 2 (where's the datasheet?) */
187 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
188 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
189 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
190 /* SATA Controller 2 IDE (ICH8, ditto) */
191 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
192 /* Mobile SATA Controller IDE (ICH8M, ditto) */
193 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
194
195 { } /* terminate list */
196 };
197
198 static struct pci_driver piix_pci_driver = {
199 .name = DRV_NAME,
200 .id_table = piix_pci_tbl,
201 .probe = piix_init_one,
202 .remove = ata_pci_remove_one,
203 .suspend = ata_pci_device_suspend,
204 .resume = ata_pci_device_resume,
205 };
206
207 static struct scsi_host_template piix_sht = {
208 .module = THIS_MODULE,
209 .name = DRV_NAME,
210 .ioctl = ata_scsi_ioctl,
211 .queuecommand = ata_scsi_queuecmd,
212 .can_queue = ATA_DEF_QUEUE,
213 .this_id = ATA_SHT_THIS_ID,
214 .sg_tablesize = LIBATA_MAX_PRD,
215 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
216 .emulated = ATA_SHT_EMULATED,
217 .use_clustering = ATA_SHT_USE_CLUSTERING,
218 .proc_name = DRV_NAME,
219 .dma_boundary = ATA_DMA_BOUNDARY,
220 .slave_configure = ata_scsi_slave_config,
221 .bios_param = ata_std_bios_param,
222 .resume = ata_scsi_device_resume,
223 .suspend = ata_scsi_device_suspend,
224 };
225
226 static const struct ata_port_operations piix_pata_ops = {
227 .port_disable = ata_port_disable,
228 .set_piomode = piix_set_piomode,
229 .set_dmamode = piix_set_dmamode,
230
231 .tf_load = ata_tf_load,
232 .tf_read = ata_tf_read,
233 .check_status = ata_check_status,
234 .exec_command = ata_exec_command,
235 .dev_select = ata_std_dev_select,
236
237 .probe_reset = piix_pata_probe_reset,
238
239 .bmdma_setup = ata_bmdma_setup,
240 .bmdma_start = ata_bmdma_start,
241 .bmdma_stop = ata_bmdma_stop,
242 .bmdma_status = ata_bmdma_status,
243 .qc_prep = ata_qc_prep,
244 .qc_issue = ata_qc_issue_prot,
245
246 .freeze = ata_bmdma_freeze,
247 .thaw = ata_bmdma_thaw,
248 .error_handler = ata_bmdma_error_handler,
249 .post_internal_cmd = ata_bmdma_post_internal_cmd,
250
251 .irq_handler = ata_interrupt,
252 .irq_clear = ata_bmdma_irq_clear,
253
254 .port_start = ata_port_start,
255 .port_stop = ata_port_stop,
256 .host_stop = ata_host_stop,
257 };
258
259 static const struct ata_port_operations piix_sata_ops = {
260 .port_disable = ata_port_disable,
261
262 .tf_load = ata_tf_load,
263 .tf_read = ata_tf_read,
264 .check_status = ata_check_status,
265 .exec_command = ata_exec_command,
266 .dev_select = ata_std_dev_select,
267
268 .probe_reset = piix_sata_probe_reset,
269
270 .bmdma_setup = ata_bmdma_setup,
271 .bmdma_start = ata_bmdma_start,
272 .bmdma_stop = ata_bmdma_stop,
273 .bmdma_status = ata_bmdma_status,
274 .qc_prep = ata_qc_prep,
275 .qc_issue = ata_qc_issue_prot,
276
277 .freeze = ata_bmdma_freeze,
278 .thaw = ata_bmdma_thaw,
279 .error_handler = ata_bmdma_error_handler,
280 .post_internal_cmd = ata_bmdma_post_internal_cmd,
281
282 .irq_handler = ata_interrupt,
283 .irq_clear = ata_bmdma_irq_clear,
284
285 .port_start = ata_port_start,
286 .port_stop = ata_port_stop,
287 .host_stop = ata_host_stop,
288 };
289
290 static struct piix_map_db ich5_map_db = {
291 .mask = 0x7,
292 .map = {
293 /* PM PS SM SS MAP */
294 { P0, NA, P1, NA }, /* 000b */
295 { P1, NA, P0, NA }, /* 001b */
296 { RV, RV, RV, RV },
297 { RV, RV, RV, RV },
298 { P0, P1, IDE, IDE }, /* 100b */
299 { P1, P0, IDE, IDE }, /* 101b */
300 { IDE, IDE, P0, P1 }, /* 110b */
301 { IDE, IDE, P1, P0 }, /* 111b */
302 },
303 };
304
305 static struct piix_map_db ich6_map_db = {
306 .mask = 0x3,
307 .map = {
308 /* PM PS SM SS MAP */
309 { P0, P2, P1, P3 }, /* 00b */
310 { IDE, IDE, P1, P3 }, /* 01b */
311 { P0, P2, IDE, IDE }, /* 10b */
312 { RV, RV, RV, RV },
313 },
314 };
315
316 static struct piix_map_db ich6m_map_db = {
317 .mask = 0x3,
318 .map = {
319 /* PM PS SM SS MAP */
320 { P0, P2, RV, RV }, /* 00b */
321 { RV, RV, RV, RV },
322 { P0, P2, IDE, IDE }, /* 10b */
323 { RV, RV, RV, RV },
324 },
325 };
326
327 static struct ata_port_info piix_port_info[] = {
328 /* piix4_pata */
329 {
330 .sht = &piix_sht,
331 .host_flags = ATA_FLAG_SLAVE_POSS,
332 .pio_mask = 0x1f, /* pio0-4 */
333 #if 0
334 .mwdma_mask = 0x06, /* mwdma1-2 */
335 #else
336 .mwdma_mask = 0x00, /* mwdma broken */
337 #endif
338 .udma_mask = ATA_UDMA_MASK_40C,
339 .port_ops = &piix_pata_ops,
340 },
341
342 /* ich5_pata */
343 {
344 .sht = &piix_sht,
345 .host_flags = ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
346 .pio_mask = 0x1f, /* pio0-4 */
347 #if 0
348 .mwdma_mask = 0x06, /* mwdma1-2 */
349 #else
350 .mwdma_mask = 0x00, /* mwdma broken */
351 #endif
352 .udma_mask = 0x3f, /* udma0-5 */
353 .port_ops = &piix_pata_ops,
354 },
355
356 /* ich5_sata */
357 {
358 .sht = &piix_sht,
359 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
360 PIIX_FLAG_CHECKINTR,
361 .pio_mask = 0x1f, /* pio0-4 */
362 .mwdma_mask = 0x07, /* mwdma0-2 */
363 .udma_mask = 0x7f, /* udma0-6 */
364 .port_ops = &piix_sata_ops,
365 .private_data = &ich5_map_db,
366 },
367
368 /* i6300esb_sata */
369 {
370 .sht = &piix_sht,
371 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
372 PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGNORE_PCS,
373 .pio_mask = 0x1f, /* pio0-4 */
374 .mwdma_mask = 0x07, /* mwdma0-2 */
375 .udma_mask = 0x7f, /* udma0-6 */
376 .port_ops = &piix_sata_ops,
377 .private_data = &ich5_map_db,
378 },
379
380 /* ich6_sata */
381 {
382 .sht = &piix_sht,
383 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
384 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR,
385 .pio_mask = 0x1f, /* pio0-4 */
386 .mwdma_mask = 0x07, /* mwdma0-2 */
387 .udma_mask = 0x7f, /* udma0-6 */
388 .port_ops = &piix_sata_ops,
389 .private_data = &ich6_map_db,
390 },
391
392 /* ich6_sata_ahci */
393 {
394 .sht = &piix_sht,
395 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
396 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
397 PIIX_FLAG_AHCI,
398 .pio_mask = 0x1f, /* pio0-4 */
399 .mwdma_mask = 0x07, /* mwdma0-2 */
400 .udma_mask = 0x7f, /* udma0-6 */
401 .port_ops = &piix_sata_ops,
402 .private_data = &ich6_map_db,
403 },
404
405 /* ich6m_sata_ahci */
406 {
407 .sht = &piix_sht,
408 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
409 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
410 PIIX_FLAG_AHCI,
411 .pio_mask = 0x1f, /* pio0-4 */
412 .mwdma_mask = 0x07, /* mwdma0-2 */
413 .udma_mask = 0x7f, /* udma0-6 */
414 .port_ops = &piix_sata_ops,
415 .private_data = &ich6m_map_db,
416 },
417 };
418
419 static struct pci_bits piix_enable_bits[] = {
420 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
421 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
422 };
423
424 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
425 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
426 MODULE_LICENSE("GPL");
427 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
428 MODULE_VERSION(DRV_VERSION);
429
430 /**
431 * piix_pata_cbl_detect - Probe host controller cable detect info
432 * @ap: Port for which cable detect info is desired
433 *
434 * Read 80c cable indicator from ATA PCI device's PCI config
435 * register. This register is normally set by firmware (BIOS).
436 *
437 * LOCKING:
438 * None (inherited from caller).
439 */
440 static void piix_pata_cbl_detect(struct ata_port *ap)
441 {
442 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
443 u8 tmp, mask;
444
445 /* no 80c support in host controller? */
446 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
447 goto cbl40;
448
449 /* check BIOS cable detect results */
450 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
451 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
452 if ((tmp & mask) == 0)
453 goto cbl40;
454
455 ap->cbl = ATA_CBL_PATA80;
456 return;
457
458 cbl40:
459 ap->cbl = ATA_CBL_PATA40;
460 ap->udma_mask &= ATA_UDMA_MASK_40C;
461 }
462
463 /**
464 * piix_pata_probeinit - probeinit for PATA host controller
465 * @ap: Target port
466 *
467 * Probeinit including cable detection.
468 *
469 * LOCKING:
470 * None (inherited from caller).
471 */
472 static void piix_pata_probeinit(struct ata_port *ap)
473 {
474 piix_pata_cbl_detect(ap);
475 ata_std_probeinit(ap);
476 }
477
478 /**
479 * piix_pata_probe_reset - Perform reset on PATA port and classify
480 * @ap: Port to reset
481 * @classes: Resulting classes of attached devices
482 *
483 * Reset PATA phy and classify attached devices.
484 *
485 * LOCKING:
486 * None (inherited from caller).
487 */
488 static int piix_pata_probe_reset(struct ata_port *ap, unsigned int *classes)
489 {
490 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
491
492 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
493 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
494 return 0;
495 }
496
497 return ata_drive_probe_reset(ap, piix_pata_probeinit,
498 ata_std_softreset, NULL,
499 ata_std_postreset, classes);
500 }
501
502 /**
503 * piix_sata_probe - Probe PCI device for present SATA devices
504 * @ap: Port associated with the PCI device we wish to probe
505 *
506 * Reads and configures SATA PCI device's PCI config register
507 * Port Configuration and Status (PCS) to determine port and
508 * device availability.
509 *
510 * LOCKING:
511 * None (inherited from caller).
512 *
513 * RETURNS:
514 * Mask of avaliable devices on the port.
515 */
516 static unsigned int piix_sata_probe (struct ata_port *ap)
517 {
518 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
519 const unsigned int *map = ap->host_set->private_data;
520 int base = 2 * ap->hard_port_no;
521 unsigned int present_mask = 0;
522 int port, i;
523 u8 pcs;
524
525 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
526 DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base);
527
528 /* enable all ports on this ap and wait for them to settle */
529 for (i = 0; i < 2; i++) {
530 port = map[base + i];
531 if (port >= 0)
532 pcs |= 1 << port;
533 }
534
535 pci_write_config_byte(pdev, ICH5_PCS, pcs);
536 msleep(100);
537
538 /* let's see which devices are present */
539 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
540
541 for (i = 0; i < 2; i++) {
542 port = map[base + i];
543 if (port < 0)
544 continue;
545 if (ap->flags & PIIX_FLAG_IGNORE_PCS || pcs & 1 << (4 + port))
546 present_mask |= 1 << i;
547 else
548 pcs &= ~(1 << port);
549 }
550
551 /* disable offline ports on non-AHCI controllers */
552 if (!(ap->flags & PIIX_FLAG_AHCI))
553 pci_write_config_byte(pdev, ICH5_PCS, pcs);
554
555 DPRINTK("ata%u: LEAVE, pcs=0x%x present_mask=0x%x\n",
556 ap->id, pcs, present_mask);
557
558 return present_mask;
559 }
560
561 /**
562 * piix_sata_probe_reset - Perform reset on SATA port and classify
563 * @ap: Port to reset
564 * @classes: Resulting classes of attached devices
565 *
566 * Reset SATA phy and classify attached devices.
567 *
568 * LOCKING:
569 * None (inherited from caller).
570 */
571 static int piix_sata_probe_reset(struct ata_port *ap, unsigned int *classes)
572 {
573 if (!piix_sata_probe(ap)) {
574 ata_port_printk(ap, KERN_INFO, "SATA port has no device.\n");
575 return 0;
576 }
577
578 return ata_drive_probe_reset(ap, ata_std_probeinit,
579 ata_std_softreset, NULL,
580 ata_std_postreset, classes);
581 }
582
583 /**
584 * piix_set_piomode - Initialize host controller PATA PIO timings
585 * @ap: Port whose timings we are configuring
586 * @adev: um
587 *
588 * Set PIO mode for device, in host controller PCI config space.
589 *
590 * LOCKING:
591 * None (inherited from caller).
592 */
593
594 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
595 {
596 unsigned int pio = adev->pio_mode - XFER_PIO_0;
597 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
598 unsigned int is_slave = (adev->devno != 0);
599 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
600 unsigned int slave_port = 0x44;
601 u16 master_data;
602 u8 slave_data;
603
604 static const /* ISP RTC */
605 u8 timings[][2] = { { 0, 0 },
606 { 0, 0 },
607 { 1, 0 },
608 { 2, 1 },
609 { 2, 3 }, };
610
611 pci_read_config_word(dev, master_port, &master_data);
612 if (is_slave) {
613 master_data |= 0x4000;
614 /* enable PPE, IE and TIME */
615 master_data |= 0x0070;
616 pci_read_config_byte(dev, slave_port, &slave_data);
617 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
618 slave_data |=
619 (timings[pio][0] << 2) |
620 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
621 } else {
622 master_data &= 0xccf8;
623 /* enable PPE, IE and TIME */
624 master_data |= 0x0007;
625 master_data |=
626 (timings[pio][0] << 12) |
627 (timings[pio][1] << 8);
628 }
629 pci_write_config_word(dev, master_port, master_data);
630 if (is_slave)
631 pci_write_config_byte(dev, slave_port, slave_data);
632 }
633
634 /**
635 * piix_set_dmamode - Initialize host controller PATA PIO timings
636 * @ap: Port whose timings we are configuring
637 * @adev: um
638 * @udma: udma mode, 0 - 6
639 *
640 * Set UDMA mode for device, in host controller PCI config space.
641 *
642 * LOCKING:
643 * None (inherited from caller).
644 */
645
646 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
647 {
648 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
649 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
650 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
651 u8 speed = udma;
652 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
653 int a_speed = 3 << (drive_dn * 4);
654 int u_flag = 1 << drive_dn;
655 int v_flag = 0x01 << drive_dn;
656 int w_flag = 0x10 << drive_dn;
657 int u_speed = 0;
658 int sitre;
659 u16 reg4042, reg4a;
660 u8 reg48, reg54, reg55;
661
662 pci_read_config_word(dev, maslave, &reg4042);
663 DPRINTK("reg4042 = 0x%04x\n", reg4042);
664 sitre = (reg4042 & 0x4000) ? 1 : 0;
665 pci_read_config_byte(dev, 0x48, &reg48);
666 pci_read_config_word(dev, 0x4a, &reg4a);
667 pci_read_config_byte(dev, 0x54, &reg54);
668 pci_read_config_byte(dev, 0x55, &reg55);
669
670 switch(speed) {
671 case XFER_UDMA_4:
672 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
673 case XFER_UDMA_6:
674 case XFER_UDMA_5:
675 case XFER_UDMA_3:
676 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
677 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
678 case XFER_MW_DMA_2:
679 case XFER_MW_DMA_1: break;
680 default:
681 BUG();
682 return;
683 }
684
685 if (speed >= XFER_UDMA_0) {
686 if (!(reg48 & u_flag))
687 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
688 if (speed == XFER_UDMA_5) {
689 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
690 } else {
691 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
692 }
693 if ((reg4a & a_speed) != u_speed)
694 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
695 if (speed > XFER_UDMA_2) {
696 if (!(reg54 & v_flag))
697 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
698 } else
699 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
700 } else {
701 if (reg48 & u_flag)
702 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
703 if (reg4a & a_speed)
704 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
705 if (reg54 & v_flag)
706 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
707 if (reg55 & w_flag)
708 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
709 }
710 }
711
712 #define AHCI_PCI_BAR 5
713 #define AHCI_GLOBAL_CTL 0x04
714 #define AHCI_ENABLE (1 << 31)
715 static int piix_disable_ahci(struct pci_dev *pdev)
716 {
717 void __iomem *mmio;
718 u32 tmp;
719 int rc = 0;
720
721 /* BUG: pci_enable_device has not yet been called. This
722 * works because this device is usually set up by BIOS.
723 */
724
725 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
726 !pci_resource_len(pdev, AHCI_PCI_BAR))
727 return 0;
728
729 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
730 if (!mmio)
731 return -ENOMEM;
732
733 tmp = readl(mmio + AHCI_GLOBAL_CTL);
734 if (tmp & AHCI_ENABLE) {
735 tmp &= ~AHCI_ENABLE;
736 writel(tmp, mmio + AHCI_GLOBAL_CTL);
737
738 tmp = readl(mmio + AHCI_GLOBAL_CTL);
739 if (tmp & AHCI_ENABLE)
740 rc = -EIO;
741 }
742
743 pci_iounmap(pdev, mmio);
744 return rc;
745 }
746
747 /**
748 * piix_check_450nx_errata - Check for problem 450NX setup
749 * @ata_dev: the PCI device to check
750 *
751 * Check for the present of 450NX errata #19 and errata #25. If
752 * they are found return an error code so we can turn off DMA
753 */
754
755 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
756 {
757 struct pci_dev *pdev = NULL;
758 u16 cfg;
759 u8 rev;
760 int no_piix_dma = 0;
761
762 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
763 {
764 /* Look for 450NX PXB. Check for problem configurations
765 A PCI quirk checks bit 6 already */
766 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
767 pci_read_config_word(pdev, 0x41, &cfg);
768 /* Only on the original revision: IDE DMA can hang */
769 if(rev == 0x00)
770 no_piix_dma = 1;
771 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
772 else if(cfg & (1<<14) && rev < 5)
773 no_piix_dma = 2;
774 }
775 if(no_piix_dma)
776 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
777 if(no_piix_dma == 2)
778 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
779 return no_piix_dma;
780 }
781
782 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
783 struct ata_port_info *pinfo)
784 {
785 struct piix_map_db *map_db = pinfo[0].private_data;
786 const unsigned int *map;
787 int i, invalid_map = 0;
788 u8 map_value;
789
790 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
791
792 map = map_db->map[map_value & map_db->mask];
793
794 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
795 for (i = 0; i < 4; i++) {
796 switch (map[i]) {
797 case RV:
798 invalid_map = 1;
799 printk(" XX");
800 break;
801
802 case NA:
803 printk(" --");
804 break;
805
806 case IDE:
807 WARN_ON((i & 1) || map[i + 1] != IDE);
808 pinfo[i / 2] = piix_port_info[ich5_pata];
809 i++;
810 printk(" IDE IDE");
811 break;
812
813 default:
814 printk(" P%d", map[i]);
815 if (i & 1)
816 pinfo[i / 2].host_flags |= ATA_FLAG_SLAVE_POSS;
817 break;
818 }
819 }
820 printk(" ]\n");
821
822 if (invalid_map)
823 dev_printk(KERN_ERR, &pdev->dev,
824 "invalid MAP value %u\n", map_value);
825
826 pinfo[0].private_data = (void *)map;
827 pinfo[1].private_data = (void *)map;
828 }
829
830 /**
831 * piix_init_one - Register PIIX ATA PCI device with kernel services
832 * @pdev: PCI device to register
833 * @ent: Entry in piix_pci_tbl matching with @pdev
834 *
835 * Called from kernel PCI layer. We probe for combined mode (sigh),
836 * and then hand over control to libata, for it to do the rest.
837 *
838 * LOCKING:
839 * Inherited from PCI layer (may sleep).
840 *
841 * RETURNS:
842 * Zero on success, or -ERRNO value.
843 */
844
845 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
846 {
847 static int printed_version;
848 struct ata_port_info port_info[2];
849 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
850 unsigned long host_flags;
851
852 if (!printed_version++)
853 dev_printk(KERN_DEBUG, &pdev->dev,
854 "version " DRV_VERSION "\n");
855
856 /* no hotplugging support (FIXME) */
857 if (!in_module_init)
858 return -ENODEV;
859
860 port_info[0] = piix_port_info[ent->driver_data];
861 port_info[1] = piix_port_info[ent->driver_data];
862
863 host_flags = port_info[0].host_flags;
864
865 if (host_flags & PIIX_FLAG_AHCI) {
866 u8 tmp;
867 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
868 if (tmp == PIIX_AHCI_DEVICE) {
869 int rc = piix_disable_ahci(pdev);
870 if (rc)
871 return rc;
872 }
873 }
874
875 /* Initialize SATA map */
876 if (host_flags & ATA_FLAG_SATA)
877 piix_init_sata_map(pdev, port_info);
878
879 /* On ICH5, some BIOSen disable the interrupt using the
880 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
881 * On ICH6, this bit has the same effect, but only when
882 * MSI is disabled (and it is disabled, as we don't use
883 * message-signalled interrupts currently).
884 */
885 if (host_flags & PIIX_FLAG_CHECKINTR)
886 pci_intx(pdev, 1);
887
888 if (piix_check_450nx_errata(pdev)) {
889 /* This writes into the master table but it does not
890 really matter for this errata as we will apply it to
891 all the PIIX devices on the board */
892 port_info[0].mwdma_mask = 0;
893 port_info[0].udma_mask = 0;
894 port_info[1].mwdma_mask = 0;
895 port_info[1].udma_mask = 0;
896 }
897 return ata_pci_init_one(pdev, ppinfo, 2);
898 }
899
900 static int __init piix_init(void)
901 {
902 int rc;
903
904 DPRINTK("pci_module_init\n");
905 rc = pci_module_init(&piix_pci_driver);
906 if (rc)
907 return rc;
908
909 in_module_init = 0;
910
911 DPRINTK("done\n");
912 return 0;
913 }
914
915 static void __exit piix_exit(void)
916 {
917 pci_unregister_driver(&piix_pci_driver);
918 }
919
920 module_init(piix_init);
921 module_exit(piix_exit);
922
Linux kernel - Deliverables
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