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atp870u: Untangle tmpcip
[deliverable/linux.git] / drivers / scsi / atp870u.c
1 /*
2 * Copyright (C) 1997 Wu Ching Chen
3 * 2.1.x update (C) 1998 Krzysztof G. Baranowski
4 * 2.5.x update (C) 2002 Red Hat
5 * 2.6.x update (C) 2004 Red Hat
6 *
7 * Marcelo Tosatti <marcelo@conectiva.com.br> : SMP fixes
8 *
9 * Wu Ching Chen : NULL pointer fixes 2000/06/02
10 * support atp876 chip
11 * enable 32 bit fifo transfer
12 * support cdrom & remove device run ultra speed
13 * fix disconnect bug 2000/12/21
14 * support atp880 chip lvd u160 2001/05/15
15 * fix prd table bug 2001/09/12 (7.1)
16 *
17 * atp885 support add by ACARD Hao Ping Lian 2005/01/05
18 */
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/string.h>
25 #include <linux/ioport.h>
26 #include <linux/delay.h>
27 #include <linux/proc_fs.h>
28 #include <linux/spinlock.h>
29 #include <linux/pci.h>
30 #include <linux/blkdev.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/slab.h>
33 #include <asm/io.h>
34
35 #include <scsi/scsi.h>
36 #include <scsi/scsi_cmnd.h>
37 #include <scsi/scsi_device.h>
38 #include <scsi/scsi_host.h>
39
40 #include "atp870u.h"
41
42 static struct scsi_host_template atp870u_template;
43 static void send_s870(struct atp_unit *dev,unsigned char c);
44 static void is885(struct atp_unit *dev, unsigned int wkport,unsigned char c);
45 static void tscam_885(void);
46
47 static irqreturn_t atp870u_intr_handle(int irq, void *dev_id)
48 {
49 unsigned long flags;
50 unsigned short int id;
51 unsigned char i, j, c, target_id, lun,cmdp;
52 unsigned char *prd;
53 struct scsi_cmnd *workreq;
54 unsigned long adrcnt, k;
55 #ifdef ED_DBGP
56 unsigned long l;
57 #endif
58 int errstus;
59 struct Scsi_Host *host = dev_id;
60 struct atp_unit *dev = (struct atp_unit *)&host->hostdata;
61
62 for (c = 0; c < 2; c++) {
63 j = inb(dev->ioport[c] + 0x1f);
64 if ((j & 0x80) != 0)
65 {
66 goto ch_sel;
67 }
68 dev->in_int[c] = 0;
69 }
70 return IRQ_NONE;
71 ch_sel:
72 #ifdef ED_DBGP
73 printk("atp870u_intr_handle enter\n");
74 #endif
75 dev->in_int[c] = 1;
76 cmdp = inb(dev->ioport[c] + 0x10);
77 if (dev->working[c] != 0) {
78 if (dev->dev_id == ATP885_DEVID) {
79 if ((inb(dev->ioport[c] + 0x16) & 0x80) == 0)
80 outb((inb(dev->ioport[c] + 0x16) | 0x80), dev->ioport[c] + 0x16);
81 }
82 if ((inb(dev->pciport[c]) & 0x08) != 0)
83 {
84 for (k=0; k < 1000; k++) {
85 if ((inb(dev->pciport[c] + 2) & 0x08) == 0) {
86 goto stop_dma;
87 }
88 if ((inb(dev->pciport[c] + 2) & 0x01) == 0) {
89 goto stop_dma;
90 }
91 }
92 }
93 stop_dma:
94 outb(0x00, dev->pciport[c]);
95
96 i = inb(dev->ioport[c] + 0x17);
97
98 if (dev->dev_id == ATP885_DEVID)
99 outb(0x06, dev->pciport[c] + 2);
100
101 target_id = inb(dev->ioport[c] + 0x15);
102
103 /*
104 * Remap wide devices onto id numbers
105 */
106
107 if ((target_id & 0x40) != 0) {
108 target_id = (target_id & 0x07) | 0x08;
109 } else {
110 target_id &= 0x07;
111 }
112
113 if ((j & 0x40) != 0) {
114 if (dev->last_cmd[c] == 0xff) {
115 dev->last_cmd[c] = target_id;
116 }
117 dev->last_cmd[c] |= 0x40;
118 }
119 if (dev->dev_id == ATP885_DEVID)
120 dev->r1f[c][target_id] |= j;
121 #ifdef ED_DBGP
122 printk("atp870u_intr_handle status = %x\n",i);
123 #endif
124 if (i == 0x85) {
125 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
126 dev->last_cmd[c] = 0xff;
127 }
128 if (dev->dev_id == ATP885_DEVID) {
129 adrcnt = 0;
130 ((unsigned char *) &adrcnt)[2] = inb(dev->ioport[c] + 0x12);
131 ((unsigned char *) &adrcnt)[1] = inb(dev->ioport[c] + 0x13);
132 ((unsigned char *) &adrcnt)[0] = inb(dev->ioport[c] + 0x14);
133 if (dev->id[c][target_id].last_len != adrcnt)
134 {
135 k = dev->id[c][target_id].last_len;
136 k -= adrcnt;
137 dev->id[c][target_id].tran_len = k;
138 dev->id[c][target_id].last_len = adrcnt;
139 }
140 #ifdef ED_DBGP
141 printk("dev->id[c][target_id].last_len = %d dev->id[c][target_id].tran_len = %d\n",dev->id[c][target_id].last_len,dev->id[c][target_id].tran_len);
142 #endif
143 }
144
145 /*
146 * Flip wide
147 */
148 if (dev->wide_id[c] != 0) {
149 outb(0x01, dev->ioport[c] + 0x1b);
150 while ((inb(dev->ioport[c] + 0x1b) & 0x01) != 0x01) {
151 outb(0x01, dev->ioport[c] + 0x1b);
152 }
153 }
154 /*
155 * Issue more commands
156 */
157 spin_lock_irqsave(dev->host->host_lock, flags);
158 if (((dev->quhd[c] != dev->quend[c]) || (dev->last_cmd[c] != 0xff)) &&
159 (dev->in_snd[c] == 0)) {
160 #ifdef ED_DBGP
161 printk("Call sent_s870\n");
162 #endif
163 send_s870(dev,c);
164 }
165 spin_unlock_irqrestore(dev->host->host_lock, flags);
166 /*
167 * Done
168 */
169 dev->in_int[c] = 0;
170 #ifdef ED_DBGP
171 printk("Status 0x85 return\n");
172 #endif
173 goto handled;
174 }
175
176 if (i == 0x40) {
177 dev->last_cmd[c] |= 0x40;
178 dev->in_int[c] = 0;
179 goto handled;
180 }
181
182 if (i == 0x21) {
183 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
184 dev->last_cmd[c] = 0xff;
185 }
186 adrcnt = 0;
187 ((unsigned char *) &adrcnt)[2] = inb(dev->ioport[c] + 0x12);
188 ((unsigned char *) &adrcnt)[1] = inb(dev->ioport[c] + 0x13);
189 ((unsigned char *) &adrcnt)[0] = inb(dev->ioport[c] + 0x14);
190 k = dev->id[c][target_id].last_len;
191 k -= adrcnt;
192 dev->id[c][target_id].tran_len = k;
193 dev->id[c][target_id].last_len = adrcnt;
194 outb(0x41, dev->ioport[c] + 0x10);
195 outb(0x08, dev->ioport[c] + 0x18);
196 dev->in_int[c] = 0;
197 goto handled;
198 }
199
200 if (dev->dev_id == ATP885_DEVID) {
201 if ((i == 0x4c) || (i == 0x4d) || (i == 0x8c) || (i == 0x8d)) {
202 if ((i == 0x4c) || (i == 0x8c))
203 i=0x48;
204 else
205 i=0x49;
206 }
207
208 }
209 if ((i == 0x80) || (i == 0x8f)) {
210 #ifdef ED_DBGP
211 printk(KERN_DEBUG "Device reselect\n");
212 #endif
213 lun = 0;
214 if (cmdp == 0x44 || i==0x80) {
215 lun = inb(dev->ioport[c] + 0x1d) & 0x07;
216 } else {
217 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
218 dev->last_cmd[c] = 0xff;
219 }
220 if (cmdp == 0x41) {
221 #ifdef ED_DBGP
222 printk("cmdp = 0x41\n");
223 #endif
224 adrcnt = 0;
225 ((unsigned char *) &adrcnt)[2] = inb(dev->ioport[c] + 0x12);
226 ((unsigned char *) &adrcnt)[1] = inb(dev->ioport[c] + 0x13);
227 ((unsigned char *) &adrcnt)[0] = inb(dev->ioport[c] + 0x14);
228 k = dev->id[c][target_id].last_len;
229 k -= adrcnt;
230 dev->id[c][target_id].tran_len = k;
231 dev->id[c][target_id].last_len = adrcnt;
232 outb(0x08, dev->ioport[c] + 0x18);
233 dev->in_int[c] = 0;
234 goto handled;
235 } else {
236 #ifdef ED_DBGP
237 printk("cmdp != 0x41\n");
238 #endif
239 outb(0x46, dev->ioport[c] + 0x10);
240 dev->id[c][target_id].dirct = 0x00;
241 outb(0x00, dev->ioport[c] + 0x12);
242 outb(0x00, dev->ioport[c] + 0x13);
243 outb(0x00, dev->ioport[c] + 0x14);
244 outb(0x08, dev->ioport[c] + 0x18);
245 dev->in_int[c] = 0;
246 goto handled;
247 }
248 }
249 if (dev->last_cmd[c] != 0xff) {
250 dev->last_cmd[c] |= 0x40;
251 }
252 if (dev->dev_id == ATP885_DEVID) {
253 j = inb(dev->baseport + 0x29) & 0xfe;
254 outb(j, dev->baseport + 0x29);
255 } else
256 outb(0x45, dev->ioport[c] + 0x10);
257
258 target_id = inb(dev->ioport[c] + 0x16);
259 /*
260 * Remap wide identifiers
261 */
262 if ((target_id & 0x10) != 0) {
263 target_id = (target_id & 0x07) | 0x08;
264 } else {
265 target_id &= 0x07;
266 }
267 if (dev->dev_id == ATP885_DEVID)
268 outb(0x45, dev->ioport[c] + 0x10);
269 workreq = dev->id[c][target_id].curr_req;
270 #ifdef ED_DBGP
271 scmd_printk(KERN_DEBUG, workreq, "CDB");
272 for (l = 0; l < workreq->cmd_len; l++)
273 printk(KERN_DEBUG " %x",workreq->cmnd[l]);
274 printk("\n");
275 #endif
276
277 outb(lun, dev->ioport[c] + 0x0f);
278 outb(dev->id[c][target_id].devsp, dev->ioport[c] + 0x11);
279 adrcnt = dev->id[c][target_id].tran_len;
280 k = dev->id[c][target_id].last_len;
281
282 outb(((unsigned char *) &k)[2], dev->ioport[c] + 0x12);
283 outb(((unsigned char *) &k)[1], dev->ioport[c] + 0x13);
284 outb(((unsigned char *) &k)[0], dev->ioport[c] + 0x14);
285 #ifdef ED_DBGP
286 printk("k %x, k[0] 0x%x k[1] 0x%x k[2] 0x%x\n", k, inb(dev->ioport[c] + 0x14), inb(dev->ioport[c] + 0x13), inb(dev->ioport[c] + 0x12));
287 #endif
288 /* Remap wide */
289 j = target_id;
290 if (target_id > 7) {
291 j = (j & 0x07) | 0x40;
292 }
293 /* Add direction */
294 j |= dev->id[c][target_id].dirct;
295 outb(j, dev->ioport[c] + 0x15);
296 outb(0x80, dev->ioport[c] + 0x16);
297
298 /* enable 32 bit fifo transfer */
299 if (dev->dev_id == ATP885_DEVID) {
300 i=inb(dev->pciport[c] + 1) & 0xf3;
301 //j=workreq->cmnd[0];
302 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
303 i |= 0x0c;
304 }
305 outb(i, dev->pciport[c] + 1);
306 } else if ((dev->dev_id == ATP880_DEVID1) ||
307 (dev->dev_id == ATP880_DEVID2) ) {
308 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
309 outb((unsigned char) ((inb(dev->ioport[c] - 0x05) & 0x3f) | 0xc0), dev->ioport[c] - 0x05);///minus 0x05???
310 } else {
311 outb((unsigned char) (inb(dev->ioport[c] - 0x05) & 0x3f), dev->ioport[c] - 0x05);///minus 0x05???
312 }
313 } else {
314 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
315 outb((unsigned char) ((inb(dev->ioport[c] + 0x3a) & 0xf3) | 0x08), dev->ioport[c] + 0x3a);
316 } else {
317 outb((unsigned char) (inb(dev->ioport[c] + 0x3a) & 0xf3), dev->ioport[c] + 0x3a);
318 }
319 }
320 j = 0;
321 id = 1;
322 id = id << target_id;
323 /*
324 * Is this a wide device
325 */
326 if ((id & dev->wide_id[c]) != 0) {
327 j |= 0x01;
328 }
329 outb(j, dev->ioport[c] + 0x1b);
330 while ((inb(dev->ioport[c] + 0x1b) & 0x01) != j) {
331 outb(j,dev->ioport[c] + 0x1b);
332 }
333 if (dev->id[c][target_id].last_len == 0) {
334 outb(0x08, dev->ioport[c] + 0x18);
335 dev->in_int[c] = 0;
336 #ifdef ED_DBGP
337 printk("dev->id[c][target_id].last_len = 0\n");
338 #endif
339 goto handled;
340 }
341 #ifdef ED_DBGP
342 printk("target_id = %d adrcnt = %d\n",target_id,adrcnt);
343 #endif
344 prd = dev->id[c][target_id].prd_pos;
345 while (adrcnt != 0) {
346 id = ((unsigned short int *)prd)[2];
347 if (id == 0) {
348 k = 0x10000;
349 } else {
350 k = id;
351 }
352 if (k > adrcnt) {
353 ((unsigned short int *)prd)[2] = (unsigned short int)
354 (k - adrcnt);
355 ((unsigned long *)prd)[0] += adrcnt;
356 adrcnt = 0;
357 dev->id[c][target_id].prd_pos = prd;
358 } else {
359 adrcnt -= k;
360 dev->id[c][target_id].prdaddr += 0x08;
361 prd += 0x08;
362 if (adrcnt == 0) {
363 dev->id[c][target_id].prd_pos = prd;
364 }
365 }
366 }
367 outl(dev->id[c][target_id].prdaddr, dev->pciport[c] + 0x04);
368 #ifdef ED_DBGP
369 printk("dev->id[%d][%d].prdaddr 0x%8x\n", c, target_id, dev->id[c][target_id].prdaddr);
370 #endif
371 if (dev->dev_id != ATP885_DEVID) {
372 outb(0x06, dev->pciport[c] + 2);
373 outb(0x00, dev->pciport[c] + 2);
374 }
375 /*
376 * Check transfer direction
377 */
378 if (dev->id[c][target_id].dirct != 0) {
379 outb(0x08, dev->ioport[c] + 0x18);
380 outb(0x01, dev->pciport[c]);
381 dev->in_int[c] = 0;
382 #ifdef ED_DBGP
383 printk("status 0x80 return dirct != 0\n");
384 #endif
385 goto handled;
386 }
387 outb(0x08, dev->ioport[c] + 0x18);
388 outb(0x09, dev->pciport[c]);
389 dev->in_int[c] = 0;
390 #ifdef ED_DBGP
391 printk("status 0x80 return dirct = 0\n");
392 #endif
393 goto handled;
394 }
395
396 /*
397 * Current scsi request on this target
398 */
399
400 workreq = dev->id[c][target_id].curr_req;
401
402 if (i == 0x42) {
403 if ((dev->last_cmd[c] & 0xf0) != 0x40)
404 {
405 dev->last_cmd[c] = 0xff;
406 }
407 errstus = 0x02;
408 workreq->result = errstus;
409 goto go_42;
410 }
411 if (i == 0x16) {
412 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
413 dev->last_cmd[c] = 0xff;
414 }
415 errstus = 0;
416 errstus = inb(dev->ioport[c] + 0x0f);
417 if (((dev->r1f[c][target_id] & 0x10) != 0)&&(dev->dev_id==ATP885_DEVID)) {
418 printk(KERN_WARNING "AEC67162 CRC ERROR !\n");
419 errstus = 0x02;
420 }
421 workreq->result = errstus;
422 go_42:
423 if (dev->dev_id == ATP885_DEVID) {
424 j = inb(dev->baseport + 0x29) | 0x01;
425 outb(j, dev->baseport + 0x29);
426 }
427 /*
428 * Complete the command
429 */
430 scsi_dma_unmap(workreq);
431
432 spin_lock_irqsave(dev->host->host_lock, flags);
433 (*workreq->scsi_done) (workreq);
434 #ifdef ED_DBGP
435 printk("workreq->scsi_done\n");
436 #endif
437 /*
438 * Clear it off the queue
439 */
440 dev->id[c][target_id].curr_req = NULL;
441 dev->working[c]--;
442 spin_unlock_irqrestore(dev->host->host_lock, flags);
443 /*
444 * Take it back wide
445 */
446 if (dev->wide_id[c] != 0) {
447 outb(0x01, dev->ioport[c] + 0x1b);
448 while ((inb(dev->ioport[c] + 0x1b) & 0x01) != 0x01) {
449 outb(0x01, dev->ioport[c] + 0x1b);
450 }
451 }
452 /*
453 * If there is stuff to send and nothing going then send it
454 */
455 spin_lock_irqsave(dev->host->host_lock, flags);
456 if (((dev->last_cmd[c] != 0xff) || (dev->quhd[c] != dev->quend[c])) &&
457 (dev->in_snd[c] == 0)) {
458 #ifdef ED_DBGP
459 printk("Call sent_s870(scsi_done)\n");
460 #endif
461 send_s870(dev,c);
462 }
463 spin_unlock_irqrestore(dev->host->host_lock, flags);
464 dev->in_int[c] = 0;
465 goto handled;
466 }
467 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
468 dev->last_cmd[c] = 0xff;
469 }
470 if (i == 0x4f) {
471 i = 0x89;
472 }
473 i &= 0x0f;
474 if (i == 0x09) {
475 outl(dev->id[c][target_id].prdaddr, dev->pciport[c] + 4);
476 outb(0x06, dev->pciport[c] + 2);
477 outb(0x00, dev->pciport[c] + 2);
478 outb(0x41, dev->ioport[c] + 0x10);
479 if (dev->dev_id == ATP885_DEVID) {
480 k = dev->id[c][target_id].last_len;
481 outb((unsigned char) (((unsigned char *) (&k))[2]), dev->ioport[c] + 0x12);
482 outb((unsigned char) (((unsigned char *) (&k))[1]), dev->ioport[c] + 0x13);
483 outb((unsigned char) (((unsigned char *) (&k))[0]), dev->ioport[c] + 0x14);
484 dev->id[c][target_id].dirct = 0x00;
485 } else {
486 dev->id[c][target_id].dirct = 0x00;
487 }
488 outb(0x08, dev->ioport[c] + 0x18);
489 outb(0x09, dev->pciport[c]);
490 dev->in_int[c] = 0;
491 goto handled;
492 }
493 if (i == 0x08) {
494 outl(dev->id[c][target_id].prdaddr, dev->pciport[c] + 4);
495 outb(0x06, dev->pciport[c] + 2);
496 outb(0x00, dev->pciport[c] + 2);
497 outb(0x41, dev->ioport[c] + 0x10);
498 if (dev->dev_id == ATP885_DEVID) {
499 k = dev->id[c][target_id].last_len;
500 outb((unsigned char) (((unsigned char *) (&k))[2]), dev->ioport[c] + 0x12);
501 outb((unsigned char) (((unsigned char *) (&k))[1]), dev->ioport[c] + 0x13);
502 outb((unsigned char) (((unsigned char *) (&k))[0]), dev->ioport[c] + 0x14);
503 }
504 outb((unsigned char) (inb(dev->ioport[c] + 0x15) | 0x20), dev->ioport[c] + 0x15);
505 dev->id[c][target_id].dirct = 0x20;
506 outb(0x08, dev->ioport[c] + 0x18);
507 outb(0x01, dev->pciport[c]);
508 dev->in_int[c] = 0;
509 goto handled;
510 }
511 if (i == 0x0a) {
512 outb(0x30, dev->ioport[c] + 0x10);
513 } else {
514 outb(0x46, dev->ioport[c] + 0x10);
515 }
516 dev->id[c][target_id].dirct = 0x00;
517 outb(0x00, dev->ioport[c] + 0x12);
518 outb(0x00, dev->ioport[c] + 0x13);
519 outb(0x00, dev->ioport[c] + 0x14);
520 outb(0x08, dev->ioport[c] + 0x18);
521 dev->in_int[c] = 0;
522 goto handled;
523 } else {
524 // inb(dev->ioport[c] + 0x17);
525 // dev->working[c] = 0;
526 dev->in_int[c] = 0;
527 goto handled;
528 }
529
530 handled:
531 #ifdef ED_DBGP
532 printk("atp870u_intr_handle exit\n");
533 #endif
534 return IRQ_HANDLED;
535 }
536 /**
537 * atp870u_queuecommand - Queue SCSI command
538 * @req_p: request block
539 * @done: completion function
540 *
541 * Queue a command to the ATP queue. Called with the host lock held.
542 */
543 static int atp870u_queuecommand_lck(struct scsi_cmnd *req_p,
544 void (*done) (struct scsi_cmnd *))
545 {
546 unsigned char c;
547 unsigned int m;
548 struct atp_unit *dev;
549 struct Scsi_Host *host;
550
551 c = scmd_channel(req_p);
552 req_p->sense_buffer[0]=0;
553 scsi_set_resid(req_p, 0);
554 if (scmd_channel(req_p) > 1) {
555 req_p->result = 0x00040000;
556 done(req_p);
557 #ifdef ED_DBGP
558 printk("atp870u_queuecommand : req_p->device->channel > 1\n");
559 #endif
560 return 0;
561 }
562
563 host = req_p->device->host;
564 dev = (struct atp_unit *)&host->hostdata;
565
566
567
568 m = 1;
569 m = m << scmd_id(req_p);
570
571 /*
572 * Fake a timeout for missing targets
573 */
574
575 if ((m & dev->active_id[c]) == 0) {
576 req_p->result = 0x00040000;
577 done(req_p);
578 return 0;
579 }
580
581 if (done) {
582 req_p->scsi_done = done;
583 } else {
584 #ifdef ED_DBGP
585 printk( "atp870u_queuecommand: done can't be NULL\n");
586 #endif
587 req_p->result = 0;
588 done(req_p);
589 return 0;
590 }
591
592 /*
593 * Count new command
594 */
595 dev->quend[c]++;
596 if (dev->quend[c] >= qcnt) {
597 dev->quend[c] = 0;
598 }
599
600 /*
601 * Check queue state
602 */
603 if (dev->quhd[c] == dev->quend[c]) {
604 if (dev->quend[c] == 0) {
605 dev->quend[c] = qcnt;
606 }
607 #ifdef ED_DBGP
608 printk("atp870u_queuecommand : dev->quhd[c] == dev->quend[c]\n");
609 #endif
610 dev->quend[c]--;
611 req_p->result = 0x00020000;
612 done(req_p);
613 return 0;
614 }
615 dev->quereq[c][dev->quend[c]] = req_p;
616 #ifdef ED_DBGP
617 printk("dev->ioport[c] = %x inb(dev->ioport[c] + 0x1c) = %x dev->in_int[%d] = %d dev->in_snd[%d] = %d\n",dev->ioport[c],inb(dev->ioport[c] + 0x1c),c,dev->in_int[c],c,dev->in_snd[c]);
618 #endif
619 if ((inb(dev->ioport[c] + 0x1c) == 0) && (dev->in_int[c] == 0) && (dev->in_snd[c] == 0)) {
620 #ifdef ED_DBGP
621 printk("Call sent_s870(atp870u_queuecommand)\n");
622 #endif
623 send_s870(dev,c);
624 }
625 #ifdef ED_DBGP
626 printk("atp870u_queuecommand : exit\n");
627 #endif
628 return 0;
629 }
630
631 static DEF_SCSI_QCMD(atp870u_queuecommand)
632
633 /**
634 * send_s870 - send a command to the controller
635 * @host: host
636 *
637 * On entry there is work queued to be done. We move some of that work to the
638 * controller itself.
639 *
640 * Caller holds the host lock.
641 */
642 static void send_s870(struct atp_unit *dev,unsigned char c)
643 {
644 struct scsi_cmnd *workreq;
645 unsigned int i;//,k;
646 unsigned char j, target_id;
647 unsigned char *prd;
648 unsigned short int tmpcip, w;
649 unsigned long l, bttl = 0;
650 unsigned long sg_count;
651
652 if (dev->in_snd[c] != 0) {
653 #ifdef ED_DBGP
654 printk("cmnd in_snd\n");
655 #endif
656 return;
657 }
658 #ifdef ED_DBGP
659 printk("Sent_s870 enter\n");
660 #endif
661 dev->in_snd[c] = 1;
662 if ((dev->last_cmd[c] != 0xff) && ((dev->last_cmd[c] & 0x40) != 0)) {
663 dev->last_cmd[c] &= 0x0f;
664 workreq = dev->id[c][dev->last_cmd[c]].curr_req;
665 if (workreq != NULL) { /* check NULL pointer */
666 goto cmd_subp;
667 }
668 dev->last_cmd[c] = 0xff;
669 if (dev->quhd[c] == dev->quend[c]) {
670 dev->in_snd[c] = 0;
671 return ;
672 }
673 }
674 if ((dev->last_cmd[c] != 0xff) && (dev->working[c] != 0)) {
675 dev->in_snd[c] = 0;
676 return ;
677 }
678 dev->working[c]++;
679 j = dev->quhd[c];
680 dev->quhd[c]++;
681 if (dev->quhd[c] >= qcnt) {
682 dev->quhd[c] = 0;
683 }
684 workreq = dev->quereq[c][dev->quhd[c]];
685 if (dev->id[c][scmd_id(workreq)].curr_req == NULL) {
686 dev->id[c][scmd_id(workreq)].curr_req = workreq;
687 dev->last_cmd[c] = scmd_id(workreq);
688 goto cmd_subp;
689 }
690 dev->quhd[c] = j;
691 dev->working[c]--;
692 dev->in_snd[c] = 0;
693 return;
694 cmd_subp:
695 if ((inb(dev->ioport[c] + 0x1f) & 0xb0) != 0) {
696 goto abortsnd;
697 }
698 if (inb(dev->ioport[c] + 0x1c) == 0) {
699 goto oktosend;
700 }
701 abortsnd:
702 #ifdef ED_DBGP
703 printk("Abort to Send\n");
704 #endif
705 dev->last_cmd[c] |= 0x40;
706 dev->in_snd[c] = 0;
707 return;
708 oktosend:
709 #ifdef ED_DBGP
710 printk("OK to Send\n");
711 scmd_printk(KERN_DEBUG, workreq, "CDB");
712 for(i=0;i<workreq->cmd_len;i++) {
713 printk(" %x",workreq->cmnd[i]);
714 }
715 printk("\n");
716 #endif
717 l = scsi_bufflen(workreq);
718
719 if (dev->dev_id == ATP885_DEVID) {
720 j = inb(dev->baseport + 0x29) & 0xfe;
721 outb(j, dev->baseport + 0x29);
722 dev->r1f[c][scmd_id(workreq)] = 0;
723 }
724
725 if (workreq->cmnd[0] == READ_CAPACITY) {
726 if (l > 8)
727 l = 8;
728 }
729 if (workreq->cmnd[0] == 0x00) {
730 l = 0;
731 }
732
733 j = 0;
734 target_id = scmd_id(workreq);
735
736 /*
737 * Wide ?
738 */
739 w = 1;
740 w = w << target_id;
741 if ((w & dev->wide_id[c]) != 0) {
742 j |= 0x01;
743 }
744 outb(j, dev->ioport[c] + 0x1b);
745 while ((inb(dev->ioport[c] + 0x1b) & 0x01) != j) {
746 outb(j,dev->ioport[c] + 0x1b);
747 #ifdef ED_DBGP
748 printk("send_s870 while loop 1\n");
749 #endif
750 }
751 /*
752 * Write the command
753 */
754
755 outb(workreq->cmd_len, dev->ioport[c] + 0x00);
756 outb(0x2c, dev->ioport[c] + 0x01);
757 if (dev->dev_id == ATP885_DEVID) {
758 outb(0x7f, dev->ioport[c] + 0x02);
759 } else {
760 outb(0xcf, dev->ioport[c] + 0x02);
761 }
762 for (i = 0; i < workreq->cmd_len; i++) {
763 outb(workreq->cmnd[i], dev->ioport[c] + 0x03 + i);
764 }
765 outb(workreq->device->lun, dev->ioport[c] + 0x0f);
766 /*
767 * Write the target
768 */
769 outb(dev->id[c][target_id].devsp, dev->ioport[c] + 0x11);
770 #ifdef ED_DBGP
771 printk("dev->id[%d][%d].devsp = %2x\n",c,target_id,dev->id[c][target_id].devsp);
772 #endif
773
774 sg_count = scsi_dma_map(workreq);
775 /*
776 * Write transfer size
777 */
778 outb((unsigned char) (((unsigned char *) (&l))[2]), dev->ioport[c] + 0x12);
779 outb((unsigned char) (((unsigned char *) (&l))[1]), dev->ioport[c] + 0x13);
780 outb((unsigned char) (((unsigned char *) (&l))[0]), dev->ioport[c] + 0x14);
781 j = target_id;
782 dev->id[c][j].last_len = l;
783 dev->id[c][j].tran_len = 0;
784 #ifdef ED_DBGP
785 printk("dev->id[%2d][%2d].last_len = %d\n",c,j,dev->id[c][j].last_len);
786 #endif
787 /*
788 * Flip the wide bits
789 */
790 if ((j & 0x08) != 0) {
791 j = (j & 0x07) | 0x40;
792 }
793 /*
794 * Check transfer direction
795 */
796 if (workreq->sc_data_direction == DMA_TO_DEVICE) {
797 outb((unsigned char) (j | 0x20), dev->ioport[c] + 0x15);
798 } else {
799 outb(j, dev->ioport[c] + 0x15);
800 }
801 outb((unsigned char) (inb(dev->ioport[c] + 0x16) | 0x80), dev->ioport[c] + 0x16);
802 outb(0x80, dev->ioport[c] + 0x16);
803 dev->id[c][target_id].dirct = 0;
804 if (l == 0) {
805 if (inb(dev->ioport[c] + 0x1c) == 0) {
806 #ifdef ED_DBGP
807 printk("change SCSI_CMD_REG 0x08\n");
808 #endif
809 outb(0x08, dev->ioport[c] + 0x18);
810 } else {
811 dev->last_cmd[c] |= 0x40;
812 }
813 dev->in_snd[c] = 0;
814 return;
815 }
816 tmpcip = dev->pciport[c];
817 prd = dev->id[c][target_id].prd_table;
818 dev->id[c][target_id].prd_pos = prd;
819
820 /*
821 * Now write the request list. Either as scatter/gather or as
822 * a linear chain.
823 */
824
825 if (l) {
826 struct scatterlist *sgpnt;
827 i = 0;
828 scsi_for_each_sg(workreq, sgpnt, sg_count, j) {
829 bttl = sg_dma_address(sgpnt);
830 l=sg_dma_len(sgpnt);
831 #ifdef ED_DBGP
832 printk("1. bttl %x, l %x\n",bttl, l);
833 #endif
834 while (l > 0x10000) {
835 (((u16 *) (prd))[i + 3]) = 0x0000;
836 (((u16 *) (prd))[i + 2]) = 0x0000;
837 (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl);
838 l -= 0x10000;
839 bttl += 0x10000;
840 i += 0x04;
841 }
842 (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl);
843 (((u16 *) (prd))[i + 2]) = cpu_to_le16(l);
844 (((u16 *) (prd))[i + 3]) = 0;
845 i += 0x04;
846 }
847 (((u16 *) (prd))[i - 1]) = cpu_to_le16(0x8000);
848 #ifdef ED_DBGP
849 printk("prd %4x %4x %4x %4x\n",(((unsigned short int *)prd)[0]),(((unsigned short int *)prd)[1]),(((unsigned short int *)prd)[2]),(((unsigned short int *)prd)[3]));
850 printk("2. bttl %x, l %x\n",bttl, l);
851 #endif
852 }
853 tmpcip += 4;
854 #ifdef ED_DBGP
855 printk("send_s870: prdaddr_2 0x%8x tmpcip %x target_id %d\n", dev->id[c][target_id].prdaddr,tmpcip,target_id);
856 #endif
857 dev->id[c][target_id].prdaddr = dev->id[c][target_id].prd_bus;
858 outl(dev->id[c][target_id].prdaddr, tmpcip);
859 tmpcip = tmpcip - 2;
860 outb(0x06, tmpcip);
861 outb(0x00, tmpcip);
862 if (dev->dev_id == ATP885_DEVID) {
863 tmpcip--;
864 j=inb(tmpcip) & 0xf3;
865 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) ||
866 (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
867 j |= 0x0c;
868 }
869 outb(j,tmpcip);
870 tmpcip--;
871 } else if ((dev->dev_id == ATP880_DEVID1) ||
872 (dev->dev_id == ATP880_DEVID2)) {
873 tmpcip =tmpcip -2;
874 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
875 outb((unsigned char) ((inb(dev->ioport[c] - 0x05) & 0x3f) | 0xc0), dev->ioport[c] - 0x05);
876 } else {
877 outb((unsigned char) (inb(dev->ioport[c] - 0x05) & 0x3f), dev->ioport[c] - 0x05);
878 }
879 } else {
880 tmpcip =tmpcip -2;
881 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
882 outb((inb(dev->ioport[c] + 0x3a) & 0xf3) | 0x08, dev->ioport[c] + 0x3a);
883 } else {
884 outb(inb(dev->ioport[c] + 0x3a) & 0xf3, dev->ioport[c] + 0x3a);
885 }
886 }
887
888 if(workreq->sc_data_direction == DMA_TO_DEVICE) {
889 dev->id[c][target_id].dirct = 0x20;
890 if (inb(dev->ioport[c] + 0x1c) == 0) {
891 outb(0x08, dev->ioport[c] + 0x18);
892 outb(0x01, tmpcip);
893 #ifdef ED_DBGP
894 printk( "start DMA(to target)\n");
895 #endif
896 } else {
897 dev->last_cmd[c] |= 0x40;
898 }
899 dev->in_snd[c] = 0;
900 return;
901 }
902 if (inb(dev->ioport[c] + 0x1c) == 0) {
903 outb(0x08, dev->ioport[c] + 0x18);
904 outb(0x09, tmpcip);
905 #ifdef ED_DBGP
906 printk( "start DMA(to host)\n");
907 #endif
908 } else {
909 dev->last_cmd[c] |= 0x40;
910 }
911 dev->in_snd[c] = 0;
912 return;
913
914 }
915
916 static unsigned char fun_scam(struct atp_unit *dev, unsigned short int *val)
917 {
918 unsigned short int i, k;
919 unsigned char j;
920
921 outw(*val, dev->ioport[0] + 0x1c);
922 FUN_D7:
923 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */
924 k = inw(dev->ioport[0] + 0x1c);
925 j = (unsigned char) (k >> 8);
926 if ((k & 0x8000) != 0) { /* DB7 all release? */
927 goto FUN_D7;
928 }
929 }
930 *val |= 0x4000; /* assert DB6 */
931 outw(*val, dev->ioport[0] + 0x1c);
932 *val &= 0xdfff; /* assert DB5 */
933 outw(*val, dev->ioport[0] + 0x1c);
934 FUN_D5:
935 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */
936 if ((inw(dev->ioport[0] + 0x1c) & 0x2000) != 0) { /* DB5 all release? */
937 goto FUN_D5;
938 }
939 }
940 *val |= 0x8000; /* no DB4-0, assert DB7 */
941 *val &= 0xe0ff;
942 outw(*val, dev->ioport[0] + 0x1c);
943 *val &= 0xbfff; /* release DB6 */
944 outw(*val, dev->ioport[0] + 0x1c);
945 FUN_D6:
946 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */
947 if ((inw(dev->ioport[0] + 0x1c) & 0x4000) != 0) { /* DB6 all release? */
948 goto FUN_D6;
949 }
950 }
951
952 return j;
953 }
954
955 static void tscam(struct Scsi_Host *host)
956 {
957
958 unsigned char i, j, k;
959 unsigned long n;
960 unsigned short int m, assignid_map, val;
961 unsigned char mbuf[33], quintet[2];
962 struct atp_unit *dev = (struct atp_unit *)&host->hostdata;
963 static unsigned char g2q_tab[8] = {
964 0x38, 0x31, 0x32, 0x2b, 0x34, 0x2d, 0x2e, 0x27
965 };
966
967 /* I can't believe we need this before we've even done anything. Remove it
968 * and see if anyone bitches.
969 for (i = 0; i < 0x10; i++) {
970 udelay(0xffff);
971 }
972 */
973
974 outb(0x08, dev->ioport[0] + 1);
975 outb(0x7f, dev->ioport[0] + 2);
976 outb(0x20, dev->ioport[0] + 0x11);
977
978 if ((dev->scam_on & 0x40) == 0) {
979 return;
980 }
981 m = 1;
982 m <<= dev->host_id[0];
983 j = 16;
984 if (dev->chip_ver < 4) {
985 m |= 0xff00;
986 j = 8;
987 }
988 assignid_map = m;
989 outb(0x02, dev->ioport[0] + 0x02); /* 2*2=4ms,3EH 2/32*3E=3.9ms */
990 outb(0, dev->ioport[0] + 0x03);
991 outb(0, dev->ioport[0] + 0x04);
992 outb(0, dev->ioport[0] + 0x05);
993 outb(0, dev->ioport[0] + 0x06);
994 outb(0, dev->ioport[0] + 0x07);
995 outb(0, dev->ioport[0] + 0x08);
996
997 for (i = 0; i < j; i++) {
998 m = 1;
999 m = m << i;
1000 if ((m & assignid_map) != 0) {
1001 continue;
1002 }
1003 outb(0, dev->ioport[0] + 0x0f);
1004 outb(0, dev->ioport[0] + 0x12);
1005 outb(0, dev->ioport[0] + 0x13);
1006 outb(0, dev->ioport[0] + 0x14);
1007 if (i > 7) {
1008 k = (i & 0x07) | 0x40;
1009 } else {
1010 k = i;
1011 }
1012 outb(k, dev->ioport[0] + 0x15);
1013 if (dev->chip_ver == 4) {
1014 outb(0x01, dev->ioport[0] + 0x1b);
1015 } else {
1016 outb(0x00, dev->ioport[0] + 0x1b);
1017 }
1018 wait_rdyok:
1019 outb(0x09, dev->ioport[0] + 0x18);
1020
1021 while ((inb(dev->ioport[0] + 0x1f) & 0x80) == 0x00)
1022 cpu_relax();
1023 k = inb(dev->ioport[0] + 0x17);
1024 if (k != 0x16) {
1025 if ((k == 0x85) || (k == 0x42)) {
1026 continue;
1027 }
1028 outb(0x41, dev->ioport[0] + 0x10);
1029 goto wait_rdyok;
1030 }
1031 assignid_map |= m;
1032
1033 }
1034 outb(0x7f, dev->ioport[0] + 0x02);
1035 outb(0x02, dev->ioport[0] + 0x1b);
1036
1037 outb(0, 0x80);
1038
1039 val = 0x0080; /* bsy */
1040 outw(val, dev->ioport[0] + 0x1c);
1041 val |= 0x0040; /* sel */
1042 outw(val, dev->ioport[0] + 0x1c);
1043 val |= 0x0004; /* msg */
1044 outw(val, dev->ioport[0] + 0x1c);
1045 inb(0x80); /* 2 deskew delay(45ns*2=90ns) */
1046 val &= 0x007f; /* no bsy */
1047 outw(val, dev->ioport[0] + 0x1c);
1048 mdelay(128);
1049 val &= 0x00fb; /* after 1ms no msg */
1050 outw(val, dev->ioport[0] + 0x1c);
1051 wait_nomsg:
1052 if ((inb(dev->ioport[0] + 0x1c) & 0x04) != 0) {
1053 goto wait_nomsg;
1054 }
1055 outb(1, 0x80);
1056 udelay(100);
1057 for (n = 0; n < 0x30000; n++) {
1058 if ((inb(dev->ioport[0] + 0x1c) & 0x80) != 0) { /* bsy ? */
1059 goto wait_io;
1060 }
1061 }
1062 goto TCM_SYNC;
1063 wait_io:
1064 for (n = 0; n < 0x30000; n++) {
1065 if ((inb(dev->ioport[0] + 0x1c) & 0x81) == 0x0081) {
1066 goto wait_io1;
1067 }
1068 }
1069 goto TCM_SYNC;
1070 wait_io1:
1071 inb(0x80);
1072 val |= 0x8003; /* io,cd,db7 */
1073 outw(val, dev->ioport[0] + 0x1c);
1074 inb(0x80);
1075 val &= 0x00bf; /* no sel */
1076 outw(val, dev->ioport[0] + 0x1c);
1077 outb(2, 0x80);
1078 TCM_SYNC:
1079 /*
1080 * The funny division into multiple delays is to accomodate
1081 * arches like ARM where udelay() multiplies its argument by
1082 * a large number to initialize a loop counter. To avoid
1083 * overflow, the maximum supported udelay is 2000 microseconds.
1084 *
1085 * XXX it would be more polite to find a way to use msleep()
1086 */
1087 mdelay(2);
1088 udelay(48);
1089 if ((inb(dev->ioport[0] + 0x1c) & 0x80) == 0x00) { /* bsy ? */
1090 outw(0, dev->ioport[0] + 0x1c);
1091 outb(0, dev->ioport[0] + 0x1b);
1092 outb(0, dev->ioport[0] + 0x15);
1093 outb(0x09, dev->ioport[0] + 0x18);
1094 while ((inb(dev->ioport[0] + 0x1f) & 0x80) == 0)
1095 cpu_relax();
1096 inb(dev->ioport[0] + 0x17);
1097 return;
1098 }
1099 val &= 0x00ff; /* synchronization */
1100 val |= 0x3f00;
1101 fun_scam(dev, &val);
1102 outb(3, 0x80);
1103 val &= 0x00ff; /* isolation */
1104 val |= 0x2000;
1105 fun_scam(dev, &val);
1106 outb(4, 0x80);
1107 i = 8;
1108 j = 0;
1109 TCM_ID:
1110 if ((inw(dev->ioport[0] + 0x1c) & 0x2000) == 0) {
1111 goto TCM_ID;
1112 }
1113 outb(5, 0x80);
1114 val &= 0x00ff; /* get ID_STRING */
1115 val |= 0x2000;
1116 k = fun_scam(dev, &val);
1117 if ((k & 0x03) == 0) {
1118 goto TCM_5;
1119 }
1120 mbuf[j] <<= 0x01;
1121 mbuf[j] &= 0xfe;
1122 if ((k & 0x02) != 0) {
1123 mbuf[j] |= 0x01;
1124 }
1125 i--;
1126 if (i > 0) {
1127 goto TCM_ID;
1128 }
1129 j++;
1130 i = 8;
1131 goto TCM_ID;
1132
1133 TCM_5: /* isolation complete.. */
1134 /* mbuf[32]=0;
1135 printk(" \n%x %x %x %s\n ",assignid_map,mbuf[0],mbuf[1],&mbuf[2]); */
1136 i = 15;
1137 j = mbuf[0];
1138 if ((j & 0x20) != 0) { /* bit5=1:ID up to 7 */
1139 i = 7;
1140 }
1141 if ((j & 0x06) == 0) { /* IDvalid? */
1142 goto G2Q5;
1143 }
1144 k = mbuf[1];
1145 small_id:
1146 m = 1;
1147 m <<= k;
1148 if ((m & assignid_map) == 0) {
1149 goto G2Q_QUIN;
1150 }
1151 if (k > 0) {
1152 k--;
1153 goto small_id;
1154 }
1155 G2Q5: /* srch from max acceptable ID# */
1156 k = i; /* max acceptable ID# */
1157 G2Q_LP:
1158 m = 1;
1159 m <<= k;
1160 if ((m & assignid_map) == 0) {
1161 goto G2Q_QUIN;
1162 }
1163 if (k > 0) {
1164 k--;
1165 goto G2Q_LP;
1166 }
1167 G2Q_QUIN: /* k=binID#, */
1168 assignid_map |= m;
1169 if (k < 8) {
1170 quintet[0] = 0x38; /* 1st dft ID<8 */
1171 } else {
1172 quintet[0] = 0x31; /* 1st ID>=8 */
1173 }
1174 k &= 0x07;
1175 quintet[1] = g2q_tab[k];
1176
1177 val &= 0x00ff; /* AssignID 1stQuintet,AH=001xxxxx */
1178 m = quintet[0] << 8;
1179 val |= m;
1180 fun_scam(dev, &val);
1181 val &= 0x00ff; /* AssignID 2ndQuintet,AH=001xxxxx */
1182 m = quintet[1] << 8;
1183 val |= m;
1184 fun_scam(dev, &val);
1185
1186 goto TCM_SYNC;
1187
1188 }
1189
1190 static void is870(struct atp_unit *dev, unsigned int wkport)
1191 {
1192 unsigned char i, j, k, rmb, n;
1193 unsigned short int m;
1194 static unsigned char mbuf[512];
1195 static unsigned char satn[9] = { 0, 0, 0, 0, 0, 0, 0, 6, 6 };
1196 static unsigned char inqd[9] = { 0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6 };
1197 static unsigned char synn[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
1198 static unsigned char synu[6] = { 0x80, 1, 3, 1, 0x0c, 0x0e };
1199 static unsigned char synw[6] = { 0x80, 1, 3, 1, 0x0c, 0x07 };
1200 static unsigned char wide[6] = { 0x80, 1, 2, 3, 1, 0 };
1201
1202 outb((unsigned char) (inb(wkport + 0x3a) | 0x10), wkport + 0x3a);
1203
1204 for (i = 0; i < 16; i++) {
1205 if ((dev->chip_ver != 4) && (i > 7)) {
1206 break;
1207 }
1208 m = 1;
1209 m = m << i;
1210 if ((m & dev->active_id[0]) != 0) {
1211 continue;
1212 }
1213 if (i == dev->host_id[0]) {
1214 printk(KERN_INFO " ID: %2d Host Adapter\n", dev->host_id[0]);
1215 continue;
1216 }
1217 if (dev->chip_ver == 4) {
1218 outb(0x01, wkport + 0x1b);
1219 } else {
1220 outb(0x00, wkport + 0x1b);
1221 }
1222 outb(0x08, wkport + 1);
1223 outb(0x7f, wkport + 2);
1224 outb(satn[0], wkport + 3);
1225 outb(satn[1], wkport + 4);
1226 outb(satn[2], wkport + 5);
1227 outb(satn[3], wkport + 6);
1228 outb(satn[4], wkport + 7);
1229 outb(satn[5], wkport + 8);
1230 outb(0, wkport + 0x0f);
1231 outb(dev->id[0][i].devsp, wkport + 0x11);
1232 outb(0, wkport + 0x12);
1233 outb(satn[6], wkport + 0x13);
1234 outb(satn[7], wkport + 0x14);
1235 j = i;
1236 if ((j & 0x08) != 0) {
1237 j = (j & 0x07) | 0x40;
1238 }
1239 outb(j, wkport + 0x15);
1240 outb(satn[8], wkport + 0x18);
1241
1242 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1243 cpu_relax();
1244
1245 if (inb(wkport + 0x17) != 0x11 && inb(wkport + 0x17) != 0x8e)
1246 continue;
1247
1248 while (inb(wkport + 0x17) != 0x8e)
1249 cpu_relax();
1250
1251 dev->active_id[0] |= m;
1252
1253 outb(0x30, wkport + 0x10);
1254 outb(0x00, wkport + 0x04);
1255
1256 phase_cmd:
1257 outb(0x08, wkport + 0x18);
1258 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1259 cpu_relax();
1260 j = inb(wkport + 0x17);
1261 if (j != 0x16) {
1262 outb(0x41, wkport + 0x10);
1263 goto phase_cmd;
1264 }
1265 sel_ok:
1266 outb(inqd[0], wkport + 3);
1267 outb(inqd[1], wkport + 4);
1268 outb(inqd[2], wkport + 5);
1269 outb(inqd[3], wkport + 6);
1270 outb(inqd[4], wkport + 7);
1271 outb(inqd[5], wkport + 8);
1272 outb(0, wkport + 0x0f);
1273 outb(dev->id[0][i].devsp, wkport + 0x11);
1274 outb(0, wkport + 0x12);
1275 outb(inqd[6], wkport + 0x13);
1276 outb(inqd[7], wkport + 0x14);
1277 outb(inqd[8], wkport + 0x18);
1278
1279 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1280 cpu_relax();
1281
1282 if (inb(wkport + 0x17) != 0x11 && inb(wkport + 0x17) != 0x8e)
1283 continue;
1284
1285 while (inb(wkport + 0x17) != 0x8e)
1286 cpu_relax();
1287
1288 if (dev->chip_ver == 4)
1289 outb(0x00, wkport + 0x1b);
1290
1291 outb(0x08, wkport + 0x18);
1292 j = 0;
1293 rd_inq_data:
1294 k = inb(wkport + 0x1f);
1295 if ((k & 0x01) != 0) {
1296 mbuf[j++] = inb(wkport + 0x19);
1297 goto rd_inq_data;
1298 }
1299 if ((k & 0x80) == 0) {
1300 goto rd_inq_data;
1301 }
1302 j = inb(wkport + 0x17);
1303 if (j == 0x16) {
1304 goto inq_ok;
1305 }
1306 outb(0x46, wkport + 0x10);
1307 outb(0, wkport + 0x12);
1308 outb(0, wkport + 0x13);
1309 outb(0, wkport + 0x14);
1310 outb(0x08, wkport + 0x18);
1311
1312 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1313 cpu_relax();
1314
1315 if (inb(wkport + 0x17) != 0x16) {
1316 goto sel_ok;
1317 }
1318 inq_ok:
1319 mbuf[36] = 0;
1320 printk(KERN_INFO " ID: %2d %s\n", i, &mbuf[8]);
1321 dev->id[0][i].devtype = mbuf[0];
1322 rmb = mbuf[1];
1323 n = mbuf[7];
1324 if (dev->chip_ver != 4) {
1325 goto not_wide;
1326 }
1327 if ((mbuf[7] & 0x60) == 0) {
1328 goto not_wide;
1329 }
1330 if ((dev->global_map[0] & 0x20) == 0) {
1331 goto not_wide;
1332 }
1333 outb(0x01, wkport + 0x1b);
1334 outb(satn[0], wkport + 3);
1335 outb(satn[1], wkport + 4);
1336 outb(satn[2], wkport + 5);
1337 outb(satn[3], wkport + 6);
1338 outb(satn[4], wkport + 7);
1339 outb(satn[5], wkport + 8);
1340 outb(0, wkport + 0x0f);
1341 outb(dev->id[0][i].devsp, wkport + 0x11);
1342 outb(0, wkport + 0x12);
1343 outb(satn[6], wkport + 0x13);
1344 outb(satn[7], wkport + 0x14);
1345 outb(satn[8], wkport + 0x18);
1346
1347 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1348 cpu_relax();
1349
1350 if (inb(wkport + 0x17) != 0x11 && inb(wkport + 0x17) != 0x8e)
1351 continue;
1352
1353 while (inb(wkport + 0x17) != 0x8e)
1354 cpu_relax();
1355
1356 try_wide:
1357 j = 0;
1358 outb(0x05, wkport + 0x14);
1359 outb(0x20, wkport + 0x18);
1360
1361 while ((inb(wkport + 0x1f) & 0x80) == 0) {
1362 if ((inb(wkport + 0x1f) & 0x01) != 0)
1363 outb(wide[j++], wkport + 0x19);
1364 }
1365
1366 while ((inb(wkport + 0x17) & 0x80) == 0x00)
1367 cpu_relax();
1368
1369 j = inb(wkport + 0x17) & 0x0f;
1370 if (j == 0x0f) {
1371 goto widep_in;
1372 }
1373 if (j == 0x0a) {
1374 goto widep_cmd;
1375 }
1376 if (j == 0x0e) {
1377 goto try_wide;
1378 }
1379 continue;
1380 widep_out:
1381 outb(0x20, wkport + 0x18);
1382 while ((inb(wkport + 0x1f) & 0x80) == 0) {
1383 if ((inb(wkport + 0x1f) & 0x01) != 0)
1384 outb(0, wkport + 0x19);
1385 }
1386 j = inb(wkport + 0x17) & 0x0f;
1387 if (j == 0x0f) {
1388 goto widep_in;
1389 }
1390 if (j == 0x0a) {
1391 goto widep_cmd;
1392 }
1393 if (j == 0x0e) {
1394 goto widep_out;
1395 }
1396 continue;
1397 widep_in:
1398 outb(0xff, wkport + 0x14);
1399 outb(0x20, wkport + 0x18);
1400 k = 0;
1401 widep_in1:
1402 j = inb(wkport + 0x1f);
1403 if ((j & 0x01) != 0) {
1404 mbuf[k++] = inb(wkport + 0x19);
1405 goto widep_in1;
1406 }
1407 if ((j & 0x80) == 0x00) {
1408 goto widep_in1;
1409 }
1410 j = inb(wkport + 0x17) & 0x0f;
1411 if (j == 0x0f) {
1412 goto widep_in;
1413 }
1414 if (j == 0x0a) {
1415 goto widep_cmd;
1416 }
1417 if (j == 0x0e) {
1418 goto widep_out;
1419 }
1420 continue;
1421 widep_cmd:
1422 outb(0x30, wkport + 0x10);
1423 outb(0x00, wkport + 0x14);
1424 outb(0x08, wkport + 0x18);
1425
1426 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1427 cpu_relax();
1428
1429 j = inb(wkport + 0x17);
1430 if (j != 0x16) {
1431 if (j == 0x4e) {
1432 goto widep_out;
1433 }
1434 continue;
1435 }
1436 if (mbuf[0] != 0x01) {
1437 goto not_wide;
1438 }
1439 if (mbuf[1] != 0x02) {
1440 goto not_wide;
1441 }
1442 if (mbuf[2] != 0x03) {
1443 goto not_wide;
1444 }
1445 if (mbuf[3] != 0x01) {
1446 goto not_wide;
1447 }
1448 m = 1;
1449 m = m << i;
1450 dev->wide_id[0] |= m;
1451 not_wide:
1452 if ((dev->id[0][i].devtype == 0x00) || (dev->id[0][i].devtype == 0x07) || ((dev->id[0][i].devtype == 0x05) && ((n & 0x10) != 0))) {
1453 goto set_sync;
1454 }
1455 continue;
1456 set_sync:
1457 j = 0;
1458 if ((m & dev->wide_id[0]) != 0) {
1459 j |= 0x01;
1460 }
1461 outb(j, wkport + 0x1b);
1462 outb(satn[0], wkport + 3);
1463 outb(satn[1], wkport + 4);
1464 outb(satn[2], wkport + 5);
1465 outb(satn[3], wkport + 6);
1466 outb(satn[4], wkport + 7);
1467 outb(satn[5], wkport + 8);
1468 outb(0, wkport + 0x0f);
1469 outb(dev->id[0][i].devsp, wkport + 0x11);
1470 outb(0, wkport + 0x12);
1471 outb(satn[6], wkport + 0x13);
1472 outb(satn[7], wkport + 0x14);
1473 outb(satn[8], wkport + 0x18);
1474
1475 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1476 cpu_relax();
1477
1478 if (inb(wkport + 0x17) != 0x11 && inb(wkport + 0x17) != 0x8e)
1479 continue;
1480
1481 while (inb(wkport + 0x17) != 0x8e)
1482 cpu_relax();
1483
1484 try_sync:
1485 j = 0;
1486 outb(0x06, wkport + 0x14);
1487 outb(0x20, wkport + 0x18);
1488
1489 while ((inb(wkport + 0x1f) & 0x80) == 0) {
1490 if ((inb(wkport + 0x1f) & 0x01) != 0) {
1491 if ((m & dev->wide_id[0]) != 0) {
1492 outb(synw[j++], wkport + 0x19);
1493 } else {
1494 if ((m & dev->ultra_map[0]) != 0) {
1495 outb(synu[j++], wkport + 0x19);
1496 } else {
1497 outb(synn[j++], wkport + 0x19);
1498 }
1499 }
1500 }
1501 }
1502
1503 while ((inb(wkport + 0x17) & 0x80) == 0x00)
1504 cpu_relax();
1505
1506 j = inb(wkport + 0x17) & 0x0f;
1507 if (j == 0x0f) {
1508 goto phase_ins;
1509 }
1510 if (j == 0x0a) {
1511 goto phase_cmds;
1512 }
1513 if (j == 0x0e) {
1514 goto try_sync;
1515 }
1516 continue;
1517 phase_outs:
1518 outb(0x20, wkport + 0x18);
1519 while ((inb(wkport + 0x1f) & 0x80) == 0x00) {
1520 if ((inb(wkport + 0x1f) & 0x01) != 0x00)
1521 outb(0x00, wkport + 0x19);
1522 }
1523 j = inb(wkport + 0x17);
1524 if (j == 0x85) {
1525 goto tar_dcons;
1526 }
1527 j &= 0x0f;
1528 if (j == 0x0f) {
1529 goto phase_ins;
1530 }
1531 if (j == 0x0a) {
1532 goto phase_cmds;
1533 }
1534 if (j == 0x0e) {
1535 goto phase_outs;
1536 }
1537 continue;
1538 phase_ins:
1539 outb(0xff, wkport + 0x14);
1540 outb(0x20, wkport + 0x18);
1541 k = 0;
1542 phase_ins1:
1543 j = inb(wkport + 0x1f);
1544 if ((j & 0x01) != 0x00) {
1545 mbuf[k++] = inb(wkport + 0x19);
1546 goto phase_ins1;
1547 }
1548 if ((j & 0x80) == 0x00) {
1549 goto phase_ins1;
1550 }
1551
1552 while ((inb(wkport + 0x17) & 0x80) == 0x00)
1553 cpu_relax();
1554
1555 j = inb(wkport + 0x17);
1556 if (j == 0x85) {
1557 goto tar_dcons;
1558 }
1559 j &= 0x0f;
1560 if (j == 0x0f) {
1561 goto phase_ins;
1562 }
1563 if (j == 0x0a) {
1564 goto phase_cmds;
1565 }
1566 if (j == 0x0e) {
1567 goto phase_outs;
1568 }
1569 continue;
1570 phase_cmds:
1571 outb(0x30, wkport + 0x10);
1572 tar_dcons:
1573 outb(0x00, wkport + 0x14);
1574 outb(0x08, wkport + 0x18);
1575
1576 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1577 cpu_relax();
1578
1579 j = inb(wkport + 0x17);
1580 if (j != 0x16) {
1581 continue;
1582 }
1583 if (mbuf[0] != 0x01) {
1584 continue;
1585 }
1586 if (mbuf[1] != 0x03) {
1587 continue;
1588 }
1589 if (mbuf[4] == 0x00) {
1590 continue;
1591 }
1592 if (mbuf[3] > 0x64) {
1593 continue;
1594 }
1595 if (mbuf[4] > 0x0c) {
1596 mbuf[4] = 0x0c;
1597 }
1598 dev->id[0][i].devsp = mbuf[4];
1599 if ((mbuf[3] < 0x0d) && (rmb == 0)) {
1600 j = 0xa0;
1601 goto set_syn_ok;
1602 }
1603 if (mbuf[3] < 0x1a) {
1604 j = 0x20;
1605 goto set_syn_ok;
1606 }
1607 if (mbuf[3] < 0x33) {
1608 j = 0x40;
1609 goto set_syn_ok;
1610 }
1611 if (mbuf[3] < 0x4c) {
1612 j = 0x50;
1613 goto set_syn_ok;
1614 }
1615 j = 0x60;
1616 set_syn_ok:
1617 dev->id[0][i].devsp = (dev->id[0][i].devsp & 0x0f) | j;
1618 }
1619 outb((unsigned char) (inb(wkport + 0x3a) & 0xef), wkport + 0x3a);
1620 }
1621
1622 static void is880(struct atp_unit *dev, unsigned int wkport)
1623 {
1624 unsigned char i, j, k, rmb, n, lvdmode;
1625 unsigned short int m;
1626 static unsigned char mbuf[512];
1627 static unsigned char satn[9] = { 0, 0, 0, 0, 0, 0, 0, 6, 6 };
1628 static unsigned char inqd[9] = { 0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6 };
1629 static unsigned char synn[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
1630 unsigned char synu[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e };
1631 static unsigned char synw[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
1632 unsigned char synuw[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e };
1633 static unsigned char wide[6] = { 0x80, 1, 2, 3, 1, 0 };
1634 static unsigned char u3[9] = { 0x80, 1, 6, 4, 0x09, 00, 0x0e, 0x01, 0x02 };
1635
1636 lvdmode = inb(wkport + 0x3f) & 0x40;
1637
1638 for (i = 0; i < 16; i++) {
1639 m = 1;
1640 m = m << i;
1641 if ((m & dev->active_id[0]) != 0) {
1642 continue;
1643 }
1644 if (i == dev->host_id[0]) {
1645 printk(KERN_INFO " ID: %2d Host Adapter\n", dev->host_id[0]);
1646 continue;
1647 }
1648 outb(0x01, wkport + 0x5b);
1649 outb(0x08, wkport + 0x41);
1650 outb(0x7f, wkport + 0x42);
1651 outb(satn[0], wkport + 0x43);
1652 outb(satn[1], wkport + 0x44);
1653 outb(satn[2], wkport + 0x45);
1654 outb(satn[3], wkport + 0x46);
1655 outb(satn[4], wkport + 0x47);
1656 outb(satn[5], wkport + 0x48);
1657 outb(0, wkport + 0x4f);
1658 outb(dev->id[0][i].devsp, wkport + 0x51);
1659 outb(0, wkport + 0x52);
1660 outb(satn[6], wkport + 0x53);
1661 outb(satn[7], wkport + 0x54);
1662 j = i;
1663 if ((j & 0x08) != 0) {
1664 j = (j & 0x07) | 0x40;
1665 }
1666 outb(j, wkport + 0x55);
1667 outb(satn[8], wkport + 0x58);
1668
1669 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
1670 cpu_relax();
1671
1672 if (inb(wkport + 0x57) != 0x11 && inb(wkport + 0x57) != 0x8e)
1673 continue;
1674
1675 while (inb(wkport + 0x57) != 0x8e)
1676 cpu_relax();
1677
1678 dev->active_id[0] |= m;
1679
1680 outb(0x30, wkport + 0x50);
1681 outb(0x00, wkport + 0x54);
1682
1683 phase_cmd:
1684 outb(0x08, wkport + 0x58);
1685
1686 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
1687 cpu_relax();
1688
1689 j = inb(wkport + 0x57);
1690 if (j != 0x16) {
1691 outb(0x41, wkport + 0x50);
1692 goto phase_cmd;
1693 }
1694 sel_ok:
1695 outb(inqd[0], wkport + 0x43);
1696 outb(inqd[1], wkport + 0x44);
1697 outb(inqd[2], wkport + 0x45);
1698 outb(inqd[3], wkport + 0x46);
1699 outb(inqd[4], wkport + 0x47);
1700 outb(inqd[5], wkport + 0x48);
1701 outb(0, wkport + 0x4f);
1702 outb(dev->id[0][i].devsp, wkport + 0x51);
1703 outb(0, wkport + 0x52);
1704 outb(inqd[6], wkport + 0x53);
1705 outb(inqd[7], wkport + 0x54);
1706 outb(inqd[8], wkport + 0x58);
1707
1708 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
1709 cpu_relax();
1710
1711 if (inb(wkport + 0x57) != 0x11 && inb(wkport + 0x57) != 0x8e)
1712 continue;
1713
1714 while (inb(wkport + 0x57) != 0x8e)
1715 cpu_relax();
1716
1717 outb(0x00, wkport + 0x5b);
1718 outb(0x08, wkport + 0x58);
1719 j = 0;
1720 rd_inq_data:
1721 k = inb(wkport + 0x5f);
1722 if ((k & 0x01) != 0) {
1723 mbuf[j++] = inb(wkport + 0x59);
1724 goto rd_inq_data;
1725 }
1726 if ((k & 0x80) == 0) {
1727 goto rd_inq_data;
1728 }
1729 j = inb(wkport + 0x57);
1730 if (j == 0x16) {
1731 goto inq_ok;
1732 }
1733 outb(0x46, wkport + 0x50);
1734 outb(0, wkport + 0x52);
1735 outb(0, wkport + 0x53);
1736 outb(0, wkport + 0x54);
1737 outb(0x08, wkport + 0x58);
1738 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
1739 cpu_relax();
1740
1741 if (inb(wkport + 0x57) != 0x16)
1742 goto sel_ok;
1743
1744 inq_ok:
1745 mbuf[36] = 0;
1746 printk(KERN_INFO " ID: %2d %s\n", i, &mbuf[8]);
1747 dev->id[0][i].devtype = mbuf[0];
1748 rmb = mbuf[1];
1749 n = mbuf[7];
1750 if ((mbuf[7] & 0x60) == 0) {
1751 goto not_wide;
1752 }
1753 if ((i < 8) && ((dev->global_map[0] & 0x20) == 0)) {
1754 goto not_wide;
1755 }
1756 if (lvdmode == 0) {
1757 goto chg_wide;
1758 }
1759 if (dev->sp[0][i] != 0x04) // force u2
1760 {
1761 goto chg_wide;
1762 }
1763
1764 outb(0x01, wkport + 0x5b);
1765 outb(satn[0], wkport + 0x43);
1766 outb(satn[1], wkport + 0x44);
1767 outb(satn[2], wkport + 0x45);
1768 outb(satn[3], wkport + 0x46);
1769 outb(satn[4], wkport + 0x47);
1770 outb(satn[5], wkport + 0x48);
1771 outb(0, wkport + 0x4f);
1772 outb(dev->id[0][i].devsp, wkport + 0x51);
1773 outb(0, wkport + 0x52);
1774 outb(satn[6], wkport + 0x53);
1775 outb(satn[7], wkport + 0x54);
1776 outb(satn[8], wkport + 0x58);
1777
1778 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
1779 cpu_relax();
1780
1781 if (inb(wkport + 0x57) != 0x11 && inb(wkport + 0x57) != 0x8e)
1782 continue;
1783
1784 while (inb(wkport + 0x57) != 0x8e)
1785 cpu_relax();
1786
1787 try_u3:
1788 j = 0;
1789 outb(0x09, wkport + 0x54);
1790 outb(0x20, wkport + 0x58);
1791
1792 while ((inb(wkport + 0x5f) & 0x80) == 0) {
1793 if ((inb(wkport + 0x5f) & 0x01) != 0)
1794 outb(u3[j++], wkport + 0x59);
1795 }
1796
1797 while ((inb(wkport + 0x57) & 0x80) == 0x00)
1798 cpu_relax();
1799
1800 j = inb(wkport + 0x57) & 0x0f;
1801 if (j == 0x0f) {
1802 goto u3p_in;
1803 }
1804 if (j == 0x0a) {
1805 goto u3p_cmd;
1806 }
1807 if (j == 0x0e) {
1808 goto try_u3;
1809 }
1810 continue;
1811 u3p_out:
1812 outb(0x20, wkport + 0x58);
1813 while ((inb(wkport + 0x5f) & 0x80) == 0) {
1814 if ((inb(wkport + 0x5f) & 0x01) != 0)
1815 outb(0, wkport + 0x59);
1816 }
1817 j = inb(wkport + 0x57) & 0x0f;
1818 if (j == 0x0f) {
1819 goto u3p_in;
1820 }
1821 if (j == 0x0a) {
1822 goto u3p_cmd;
1823 }
1824 if (j == 0x0e) {
1825 goto u3p_out;
1826 }
1827 continue;
1828 u3p_in:
1829 outb(0x09, wkport + 0x54);
1830 outb(0x20, wkport + 0x58);
1831 k = 0;
1832 u3p_in1:
1833 j = inb(wkport + 0x5f);
1834 if ((j & 0x01) != 0) {
1835 mbuf[k++] = inb(wkport + 0x59);
1836 goto u3p_in1;
1837 }
1838 if ((j & 0x80) == 0x00) {
1839 goto u3p_in1;
1840 }
1841 j = inb(wkport + 0x57) & 0x0f;
1842 if (j == 0x0f) {
1843 goto u3p_in;
1844 }
1845 if (j == 0x0a) {
1846 goto u3p_cmd;
1847 }
1848 if (j == 0x0e) {
1849 goto u3p_out;
1850 }
1851 continue;
1852 u3p_cmd:
1853 outb(0x30, wkport + 0x50);
1854 outb(0x00, wkport + 0x54);
1855 outb(0x08, wkport + 0x58);
1856
1857 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
1858 cpu_relax();
1859
1860 j = inb(wkport + 0x57);
1861 if (j != 0x16) {
1862 if (j == 0x4e) {
1863 goto u3p_out;
1864 }
1865 continue;
1866 }
1867 if (mbuf[0] != 0x01) {
1868 goto chg_wide;
1869 }
1870 if (mbuf[1] != 0x06) {
1871 goto chg_wide;
1872 }
1873 if (mbuf[2] != 0x04) {
1874 goto chg_wide;
1875 }
1876 if (mbuf[3] == 0x09) {
1877 m = 1;
1878 m = m << i;
1879 dev->wide_id[0] |= m;
1880 dev->id[0][i].devsp = 0xce;
1881 continue;
1882 }
1883 chg_wide:
1884 outb(0x01, wkport + 0x5b);
1885 outb(satn[0], wkport + 0x43);
1886 outb(satn[1], wkport + 0x44);
1887 outb(satn[2], wkport + 0x45);
1888 outb(satn[3], wkport + 0x46);
1889 outb(satn[4], wkport + 0x47);
1890 outb(satn[5], wkport + 0x48);
1891 outb(0, wkport + 0x4f);
1892 outb(dev->id[0][i].devsp, wkport + 0x51);
1893 outb(0, wkport + 0x52);
1894 outb(satn[6], wkport + 0x53);
1895 outb(satn[7], wkport + 0x54);
1896 outb(satn[8], wkport + 0x58);
1897
1898 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
1899 cpu_relax();
1900
1901 if (inb(wkport + 0x57) != 0x11 && inb(wkport + 0x57) != 0x8e)
1902 continue;
1903
1904 while (inb(wkport + 0x57) != 0x8e)
1905 cpu_relax();
1906
1907 try_wide:
1908 j = 0;
1909 outb(0x05, wkport + 0x54);
1910 outb(0x20, wkport + 0x58);
1911
1912 while ((inb(wkport + 0x5f) & 0x80) == 0) {
1913 if ((inb(wkport + 0x5f) & 0x01) != 0)
1914 outb(wide[j++], wkport + 0x59);
1915 }
1916 while ((inb(wkport + 0x57) & 0x80) == 0x00)
1917 cpu_relax();
1918
1919 j = inb(wkport + 0x57) & 0x0f;
1920 if (j == 0x0f) {
1921 goto widep_in;
1922 }
1923 if (j == 0x0a) {
1924 goto widep_cmd;
1925 }
1926 if (j == 0x0e) {
1927 goto try_wide;
1928 }
1929 continue;
1930 widep_out:
1931 outb(0x20, wkport + 0x58);
1932 while ((inb(wkport + 0x5f) & 0x80) == 0) {
1933 if ((inb(wkport + 0x5f) & 0x01) != 0)
1934 outb(0, wkport + 0x59);
1935 }
1936 j = inb(wkport + 0x57) & 0x0f;
1937 if (j == 0x0f) {
1938 goto widep_in;
1939 }
1940 if (j == 0x0a) {
1941 goto widep_cmd;
1942 }
1943 if (j == 0x0e) {
1944 goto widep_out;
1945 }
1946 continue;
1947 widep_in:
1948 outb(0xff, wkport + 0x54);
1949 outb(0x20, wkport + 0x58);
1950 k = 0;
1951 widep_in1:
1952 j = inb(wkport + 0x5f);
1953 if ((j & 0x01) != 0) {
1954 mbuf[k++] = inb(wkport + 0x59);
1955 goto widep_in1;
1956 }
1957 if ((j & 0x80) == 0x00) {
1958 goto widep_in1;
1959 }
1960 j = inb(wkport + 0x57) & 0x0f;
1961 if (j == 0x0f) {
1962 goto widep_in;
1963 }
1964 if (j == 0x0a) {
1965 goto widep_cmd;
1966 }
1967 if (j == 0x0e) {
1968 goto widep_out;
1969 }
1970 continue;
1971 widep_cmd:
1972 outb(0x30, wkport + 0x50);
1973 outb(0x00, wkport + 0x54);
1974 outb(0x08, wkport + 0x58);
1975
1976 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
1977 cpu_relax();
1978
1979 j = inb(wkport + 0x57);
1980 if (j != 0x16) {
1981 if (j == 0x4e) {
1982 goto widep_out;
1983 }
1984 continue;
1985 }
1986 if (mbuf[0] != 0x01) {
1987 goto not_wide;
1988 }
1989 if (mbuf[1] != 0x02) {
1990 goto not_wide;
1991 }
1992 if (mbuf[2] != 0x03) {
1993 goto not_wide;
1994 }
1995 if (mbuf[3] != 0x01) {
1996 goto not_wide;
1997 }
1998 m = 1;
1999 m = m << i;
2000 dev->wide_id[0] |= m;
2001 not_wide:
2002 if ((dev->id[0][i].devtype == 0x00) || (dev->id[0][i].devtype == 0x07) || ((dev->id[0][i].devtype == 0x05) && ((n & 0x10) != 0))) {
2003 m = 1;
2004 m = m << i;
2005 if ((dev->async[0] & m) != 0) {
2006 goto set_sync;
2007 }
2008 }
2009 continue;
2010 set_sync:
2011 if (dev->sp[0][i] == 0x02) {
2012 synu[4] = 0x0c;
2013 synuw[4] = 0x0c;
2014 } else {
2015 if (dev->sp[0][i] >= 0x03) {
2016 synu[4] = 0x0a;
2017 synuw[4] = 0x0a;
2018 }
2019 }
2020 j = 0;
2021 if ((m & dev->wide_id[0]) != 0) {
2022 j |= 0x01;
2023 }
2024 outb(j, wkport + 0x5b);
2025 outb(satn[0], wkport + 0x43);
2026 outb(satn[1], wkport + 0x44);
2027 outb(satn[2], wkport + 0x45);
2028 outb(satn[3], wkport + 0x46);
2029 outb(satn[4], wkport + 0x47);
2030 outb(satn[5], wkport + 0x48);
2031 outb(0, wkport + 0x4f);
2032 outb(dev->id[0][i].devsp, wkport + 0x51);
2033 outb(0, wkport + 0x52);
2034 outb(satn[6], wkport + 0x53);
2035 outb(satn[7], wkport + 0x54);
2036 outb(satn[8], wkport + 0x58);
2037
2038 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
2039 cpu_relax();
2040
2041 if ((inb(wkport + 0x57) != 0x11) && (inb(wkport + 0x57) != 0x8e)) {
2042 continue;
2043 }
2044 while (inb(wkport + 0x57) != 0x8e)
2045 cpu_relax();
2046
2047 try_sync:
2048 j = 0;
2049 outb(0x06, wkport + 0x54);
2050 outb(0x20, wkport + 0x58);
2051
2052 while ((inb(wkport + 0x5f) & 0x80) == 0) {
2053 if ((inb(wkport + 0x5f) & 0x01) != 0) {
2054 if ((m & dev->wide_id[0]) != 0) {
2055 if ((m & dev->ultra_map[0]) != 0) {
2056 outb(synuw[j++], wkport + 0x59);
2057 } else {
2058 outb(synw[j++], wkport + 0x59);
2059 }
2060 } else {
2061 if ((m & dev->ultra_map[0]) != 0) {
2062 outb(synu[j++], wkport + 0x59);
2063 } else {
2064 outb(synn[j++], wkport + 0x59);
2065 }
2066 }
2067 }
2068 }
2069
2070 while ((inb(wkport + 0x57) & 0x80) == 0x00)
2071 cpu_relax();
2072
2073 j = inb(wkport + 0x57) & 0x0f;
2074 if (j == 0x0f) {
2075 goto phase_ins;
2076 }
2077 if (j == 0x0a) {
2078 goto phase_cmds;
2079 }
2080 if (j == 0x0e) {
2081 goto try_sync;
2082 }
2083 continue;
2084 phase_outs:
2085 outb(0x20, wkport + 0x58);
2086 while ((inb(wkport + 0x5f) & 0x80) == 0x00) {
2087 if ((inb(wkport + 0x5f) & 0x01) != 0x00)
2088 outb(0x00, wkport + 0x59);
2089 }
2090 j = inb(wkport + 0x57);
2091 if (j == 0x85) {
2092 goto tar_dcons;
2093 }
2094 j &= 0x0f;
2095 if (j == 0x0f) {
2096 goto phase_ins;
2097 }
2098 if (j == 0x0a) {
2099 goto phase_cmds;
2100 }
2101 if (j == 0x0e) {
2102 goto phase_outs;
2103 }
2104 continue;
2105 phase_ins:
2106 outb(0x06, wkport + 0x54);
2107 outb(0x20, wkport + 0x58);
2108 k = 0;
2109 phase_ins1:
2110 j = inb(wkport + 0x5f);
2111 if ((j & 0x01) != 0x00) {
2112 mbuf[k++] = inb(wkport + 0x59);
2113 goto phase_ins1;
2114 }
2115 if ((j & 0x80) == 0x00) {
2116 goto phase_ins1;
2117 }
2118
2119 while ((inb(wkport + 0x57) & 0x80) == 0x00)
2120 cpu_relax();
2121
2122 j = inb(wkport + 0x57);
2123 if (j == 0x85) {
2124 goto tar_dcons;
2125 }
2126 j &= 0x0f;
2127 if (j == 0x0f) {
2128 goto phase_ins;
2129 }
2130 if (j == 0x0a) {
2131 goto phase_cmds;
2132 }
2133 if (j == 0x0e) {
2134 goto phase_outs;
2135 }
2136 continue;
2137 phase_cmds:
2138 outb(0x30, wkport + 0x50);
2139 tar_dcons:
2140 outb(0x00, wkport + 0x54);
2141 outb(0x08, wkport + 0x58);
2142
2143 while ((inb(wkport + 0x5f) & 0x80) == 0x00)
2144 cpu_relax();
2145
2146 j = inb(wkport + 0x57);
2147 if (j != 0x16) {
2148 continue;
2149 }
2150 if (mbuf[0] != 0x01) {
2151 continue;
2152 }
2153 if (mbuf[1] != 0x03) {
2154 continue;
2155 }
2156 if (mbuf[4] == 0x00) {
2157 continue;
2158 }
2159 if (mbuf[3] > 0x64) {
2160 continue;
2161 }
2162 if (mbuf[4] > 0x0e) {
2163 mbuf[4] = 0x0e;
2164 }
2165 dev->id[0][i].devsp = mbuf[4];
2166 if (mbuf[3] < 0x0c) {
2167 j = 0xb0;
2168 goto set_syn_ok;
2169 }
2170 if ((mbuf[3] < 0x0d) && (rmb == 0)) {
2171 j = 0xa0;
2172 goto set_syn_ok;
2173 }
2174 if (mbuf[3] < 0x1a) {
2175 j = 0x20;
2176 goto set_syn_ok;
2177 }
2178 if (mbuf[3] < 0x33) {
2179 j = 0x40;
2180 goto set_syn_ok;
2181 }
2182 if (mbuf[3] < 0x4c) {
2183 j = 0x50;
2184 goto set_syn_ok;
2185 }
2186 j = 0x60;
2187 set_syn_ok:
2188 dev->id[0][i].devsp = (dev->id[0][i].devsp & 0x0f) | j;
2189 }
2190 }
2191
2192 static void atp870u_free_tables(struct Scsi_Host *host)
2193 {
2194 struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata;
2195 int j, k;
2196 for (j=0; j < 2; j++) {
2197 for (k = 0; k < 16; k++) {
2198 if (!atp_dev->id[j][k].prd_table)
2199 continue;
2200 pci_free_consistent(atp_dev->pdev, 1024, atp_dev->id[j][k].prd_table, atp_dev->id[j][k].prd_bus);
2201 atp_dev->id[j][k].prd_table = NULL;
2202 }
2203 }
2204 }
2205
2206 static int atp870u_init_tables(struct Scsi_Host *host)
2207 {
2208 struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata;
2209 int c,k;
2210 for(c=0;c < 2;c++) {
2211 for(k=0;k<16;k++) {
2212 atp_dev->id[c][k].prd_table = pci_alloc_consistent(atp_dev->pdev, 1024, &(atp_dev->id[c][k].prd_bus));
2213 if (!atp_dev->id[c][k].prd_table) {
2214 printk("atp870u_init_tables fail\n");
2215 atp870u_free_tables(host);
2216 return -ENOMEM;
2217 }
2218 atp_dev->id[c][k].prdaddr = atp_dev->id[c][k].prd_bus;
2219 atp_dev->id[c][k].devsp=0x20;
2220 atp_dev->id[c][k].devtype = 0x7f;
2221 atp_dev->id[c][k].curr_req = NULL;
2222 }
2223
2224 atp_dev->active_id[c] = 0;
2225 atp_dev->wide_id[c] = 0;
2226 atp_dev->host_id[c] = 0x07;
2227 atp_dev->quhd[c] = 0;
2228 atp_dev->quend[c] = 0;
2229 atp_dev->last_cmd[c] = 0xff;
2230 atp_dev->in_snd[c] = 0;
2231 atp_dev->in_int[c] = 0;
2232
2233 for (k = 0; k < qcnt; k++) {
2234 atp_dev->quereq[c][k] = NULL;
2235 }
2236 for (k = 0; k < 16; k++) {
2237 atp_dev->id[c][k].curr_req = NULL;
2238 atp_dev->sp[c][k] = 0x04;
2239 }
2240 }
2241 return 0;
2242 }
2243
2244 /* return non-zero on detection */
2245 static int atp870u_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2246 {
2247 unsigned char k, m, c;
2248 unsigned long flags;
2249 unsigned int base_io, error,n;
2250 unsigned char host_id;
2251 struct Scsi_Host *shpnt = NULL;
2252 struct atp_unit *atpdev, *p;
2253 unsigned char setupdata[2][16];
2254 int count = 0;
2255
2256 atpdev = kzalloc(sizeof(*atpdev), GFP_KERNEL);
2257 if (!atpdev)
2258 return -ENOMEM;
2259
2260 if (pci_enable_device(pdev))
2261 goto err_eio;
2262
2263 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2264 printk(KERN_INFO "atp870u: use 32bit DMA mask.\n");
2265 } else {
2266 printk(KERN_ERR "atp870u: DMA mask required but not available.\n");
2267 goto err_eio;
2268 }
2269
2270 /*
2271 * It's probably easier to weed out some revisions like
2272 * this than via the PCI device table
2273 */
2274 if (ent->device == PCI_DEVICE_ID_ARTOP_AEC7610) {
2275 atpdev->chip_ver = pdev->revision;
2276 if (atpdev->chip_ver < 2)
2277 goto err_eio;
2278 }
2279
2280 switch (ent->device) {
2281 case PCI_DEVICE_ID_ARTOP_AEC7612UW:
2282 case PCI_DEVICE_ID_ARTOP_AEC7612SUW:
2283 case ATP880_DEVID1:
2284 case ATP880_DEVID2:
2285 case ATP885_DEVID:
2286 atpdev->chip_ver = 0x04;
2287 default:
2288 break;
2289 }
2290 base_io = pci_resource_start(pdev, 0);
2291 base_io &= 0xfffffff8;
2292
2293 if ((ent->device == ATP880_DEVID1)||(ent->device == ATP880_DEVID2)) {
2294 atpdev->chip_ver = pdev->revision;
2295 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);//JCC082803
2296
2297 host_id = inb(base_io + 0x39);
2298 host_id >>= 0x04;
2299
2300 printk(KERN_INFO " ACARD AEC-67160 PCI Ultra3 LVD Host Adapter: %d"
2301 " IO:%x, IRQ:%d.\n", count, base_io, pdev->irq);
2302 atpdev->ioport[0] = base_io + 0x40;
2303 atpdev->pciport[0] = base_io + 0x28;
2304 atpdev->dev_id = ent->device;
2305 atpdev->host_id[0] = host_id;
2306
2307 atpdev->scam_on = inb(base_io + 0x22);
2308 atpdev->global_map[0] = inb(base_io + 0x35);
2309 atpdev->ultra_map[0] = inw(base_io + 0x3c);
2310
2311 n = 0x3f09;
2312 next_fblk_880:
2313 if (n >= 0x4000)
2314 goto flash_ok_880;
2315
2316 m = 0;
2317 outw(n, base_io + 0x34);
2318 n += 0x0002;
2319 if (inb(base_io + 0x30) == 0xff)
2320 goto flash_ok_880;
2321
2322 atpdev->sp[0][m++] = inb(base_io + 0x30);
2323 atpdev->sp[0][m++] = inb(base_io + 0x31);
2324 atpdev->sp[0][m++] = inb(base_io + 0x32);
2325 atpdev->sp[0][m++] = inb(base_io + 0x33);
2326 outw(n, base_io + 0x34);
2327 n += 0x0002;
2328 atpdev->sp[0][m++] = inb(base_io + 0x30);
2329 atpdev->sp[0][m++] = inb(base_io + 0x31);
2330 atpdev->sp[0][m++] = inb(base_io + 0x32);
2331 atpdev->sp[0][m++] = inb(base_io + 0x33);
2332 outw(n, base_io + 0x34);
2333 n += 0x0002;
2334 atpdev->sp[0][m++] = inb(base_io + 0x30);
2335 atpdev->sp[0][m++] = inb(base_io + 0x31);
2336 atpdev->sp[0][m++] = inb(base_io + 0x32);
2337 atpdev->sp[0][m++] = inb(base_io + 0x33);
2338 outw(n, base_io + 0x34);
2339 n += 0x0002;
2340 atpdev->sp[0][m++] = inb(base_io + 0x30);
2341 atpdev->sp[0][m++] = inb(base_io + 0x31);
2342 atpdev->sp[0][m++] = inb(base_io + 0x32);
2343 atpdev->sp[0][m++] = inb(base_io + 0x33);
2344 n += 0x0018;
2345 goto next_fblk_880;
2346 flash_ok_880:
2347 outw(0, base_io + 0x34);
2348 atpdev->ultra_map[0] = 0;
2349 atpdev->async[0] = 0;
2350 for (k = 0; k < 16; k++) {
2351 n = 1;
2352 n = n << k;
2353 if (atpdev->sp[0][k] > 1) {
2354 atpdev->ultra_map[0] |= n;
2355 } else {
2356 if (atpdev->sp[0][k] == 0)
2357 atpdev->async[0] |= n;
2358 }
2359 }
2360 atpdev->async[0] = ~(atpdev->async[0]);
2361 outb(atpdev->global_map[0], base_io + 0x35);
2362
2363 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
2364 if (!shpnt)
2365 goto err_nomem;
2366
2367 p = (struct atp_unit *)&shpnt->hostdata;
2368
2369 atpdev->host = shpnt;
2370 atpdev->pdev = pdev;
2371 pci_set_drvdata(pdev, p);
2372 memcpy(p, atpdev, sizeof(*atpdev));
2373 if (atp870u_init_tables(shpnt) < 0) {
2374 printk(KERN_ERR "Unable to allocate tables for Acard controller\n");
2375 goto unregister;
2376 }
2377
2378 if (request_irq(pdev->irq, atp870u_intr_handle, IRQF_SHARED, "atp880i", shpnt)) {
2379 printk(KERN_ERR "Unable to allocate IRQ%d for Acard controller.\n", pdev->irq);
2380 goto free_tables;
2381 }
2382
2383 spin_lock_irqsave(shpnt->host_lock, flags);
2384 k = inb(base_io + 0x38) & 0x80;
2385 outb(k, base_io + 0x38);
2386 outb(0x20, base_io + 0x3b);
2387 mdelay(32);
2388 outb(0, base_io + 0x3b);
2389 mdelay(32);
2390 inb(base_io + 0x5b);
2391 inb(base_io + 0x57);
2392 outb((host_id | 0x08), base_io + 0x40);
2393 outb(0, base_io + 0x58);
2394 while ((inb(base_io + 0x5f) & 0x80) == 0)
2395 mdelay(1);
2396 inb(base_io + 0x57);
2397 outb(8, base_io + 0x41);
2398 outb(0x7f, base_io + 0x42);
2399 outb(0x20, base_io + 0x51);
2400
2401 tscam(shpnt);
2402 is880(p, base_io);
2403 outb(0xb0, base_io + 0x38);
2404 shpnt->max_id = 16;
2405 shpnt->this_id = host_id;
2406 shpnt->unique_id = base_io;
2407 shpnt->io_port = base_io;
2408 shpnt->n_io_port = 0x60; /* Number of bytes of I/O space used */
2409 shpnt->irq = pdev->irq;
2410 } else if (ent->device == ATP885_DEVID) {
2411 printk(KERN_INFO " ACARD AEC-67162 PCI Ultra3 LVD Host Adapter: IO:%x, IRQ:%d.\n"
2412 , base_io, pdev->irq);
2413
2414 atpdev->pdev = pdev;
2415 atpdev->dev_id = ent->device;
2416 atpdev->baseport = base_io;
2417 atpdev->ioport[0] = base_io + 0x80;
2418 atpdev->ioport[1] = base_io + 0xc0;
2419 atpdev->pciport[0] = base_io + 0x40;
2420 atpdev->pciport[1] = base_io + 0x50;
2421
2422 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
2423 if (!shpnt)
2424 goto err_nomem;
2425
2426 p = (struct atp_unit *)&shpnt->hostdata;
2427
2428 atpdev->host = shpnt;
2429 atpdev->pdev = pdev;
2430 pci_set_drvdata(pdev, p);
2431 memcpy(p, atpdev, sizeof(struct atp_unit));
2432 if (atp870u_init_tables(shpnt) < 0)
2433 goto unregister;
2434
2435 #ifdef ED_DBGP
2436 printk("request_irq() shpnt %p hostdata %p\n", shpnt, p);
2437 #endif
2438 if (request_irq(pdev->irq, atp870u_intr_handle, IRQF_SHARED, "atp870u", shpnt)) {
2439 printk(KERN_ERR "Unable to allocate IRQ for Acard controller.\n");
2440 goto free_tables;
2441 }
2442
2443 spin_lock_irqsave(shpnt->host_lock, flags);
2444
2445 c=inb(base_io + 0x29);
2446 outb((c | 0x04),base_io + 0x29);
2447
2448 n=0x1f80;
2449 next_fblk_885:
2450 if (n >= 0x2000) {
2451 goto flash_ok_885;
2452 }
2453 outw(n,base_io + 0x3c);
2454 if (inl(base_io + 0x38) == 0xffffffff) {
2455 goto flash_ok_885;
2456 }
2457 for (m=0; m < 2; m++) {
2458 p->global_map[m]= 0;
2459 for (k=0; k < 4; k++) {
2460 outw(n++,base_io + 0x3c);
2461 ((unsigned long *)&setupdata[m][0])[k]=inl(base_io + 0x38);
2462 }
2463 for (k=0; k < 4; k++) {
2464 outw(n++,base_io + 0x3c);
2465 ((unsigned long *)&p->sp[m][0])[k]=inl(base_io + 0x38);
2466 }
2467 n += 8;
2468 }
2469 goto next_fblk_885;
2470 flash_ok_885:
2471 #ifdef ED_DBGP
2472 printk( "Flash Read OK\n");
2473 #endif
2474 c=inb(base_io + 0x29);
2475 outb((c & 0xfb),base_io + 0x29);
2476 for (c=0;c < 2;c++) {
2477 p->ultra_map[c]=0;
2478 p->async[c] = 0;
2479 for (k=0; k < 16; k++) {
2480 n=1;
2481 n = n << k;
2482 if (p->sp[c][k] > 1) {
2483 p->ultra_map[c] |= n;
2484 } else {
2485 if (p->sp[c][k] == 0) {
2486 p->async[c] |= n;
2487 }
2488 }
2489 }
2490 p->async[c] = ~(p->async[c]);
2491
2492 if (p->global_map[c] == 0) {
2493 k=setupdata[c][1];
2494 if ((k & 0x40) != 0)
2495 p->global_map[c] |= 0x20;
2496 k &= 0x07;
2497 p->global_map[c] |= k;
2498 if ((setupdata[c][2] & 0x04) != 0)
2499 p->global_map[c] |= 0x08;
2500 p->host_id[c] = setupdata[c][0] & 0x07;
2501 }
2502 }
2503
2504 k = inb(base_io + 0x28) & 0x8f;
2505 k |= 0x10;
2506 outb(k, base_io + 0x28);
2507 outb(0x80, base_io + 0x41);
2508 outb(0x80, base_io + 0x51);
2509 mdelay(100);
2510 outb(0, base_io + 0x41);
2511 outb(0, base_io + 0x51);
2512 mdelay(1000);
2513 inb(base_io + 0x9b);
2514 inb(base_io + 0x97);
2515 inb(base_io + 0xdb);
2516 inb(base_io + 0xd7);
2517 k=p->host_id[0];
2518 if (k > 7)
2519 k = (k & 0x07) | 0x40;
2520 k |= 0x08;
2521 outb(k, base_io + 0x80);
2522 outb(0, base_io + 0x98);
2523
2524 while ((inb(base_io + 0x9f) & 0x80) == 0)
2525 cpu_relax();
2526
2527 inb(base_io + 0x97);
2528 outb(8, base_io + 0x81);
2529 outb(0x7f, base_io + 0x82);
2530 outb(0x20, base_io + 0x91);
2531
2532 k=p->host_id[1];
2533 if (k > 7)
2534 k = (k & 0x07) | 0x40;
2535 k |= 0x08;
2536 outb(k, base_io + 0xc0);
2537 outb(0, base_io + 0xd8);
2538
2539 while ((inb(base_io + 0xdf) & 0x80) == 0)
2540 cpu_relax();
2541
2542 inb(base_io + 0xd7);
2543 outb(8, base_io + 0xc1);
2544 outb(0x7f, base_io + 0xc2);
2545 outb(0x20, base_io + 0xd1);
2546
2547 tscam_885();
2548 printk(KERN_INFO " Scanning Channel A SCSI Device ...\n");
2549 is885(p, base_io + 0x80, 0);
2550 printk(KERN_INFO " Scanning Channel B SCSI Device ...\n");
2551 is885(p, base_io + 0xc0, 1);
2552
2553 k = inb(base_io + 0x28) & 0xcf;
2554 k |= 0xc0;
2555 outb(k, base_io + 0x28);
2556 k = inb(base_io + 0x1f) | 0x80;
2557 outb(k, base_io + 0x1f);
2558 k = inb(base_io + 0x29) | 0x01;
2559 outb(k, base_io + 0x29);
2560 #ifdef ED_DBGP
2561 //printk("atp885: atp_host[0] 0x%p\n", atp_host[0]);
2562 #endif
2563 shpnt->max_id = 16;
2564 shpnt->max_lun = (p->global_map[0] & 0x07) + 1;
2565 shpnt->max_channel = 1;
2566 shpnt->this_id = p->host_id[0];
2567 shpnt->unique_id = base_io;
2568 shpnt->io_port = base_io;
2569 shpnt->n_io_port = 0xff; /* Number of bytes of I/O space used */
2570 shpnt->irq = pdev->irq;
2571
2572 } else {
2573 error = pci_read_config_byte(pdev, 0x49, &host_id);
2574
2575 printk(KERN_INFO " ACARD AEC-671X PCI Ultra/W SCSI-2/3 Host Adapter: %d "
2576 "IO:%x, IRQ:%d.\n", count, base_io, pdev->irq);
2577
2578 atpdev->ioport[0] = base_io;
2579 atpdev->pciport[0] = base_io + 0x20;
2580 atpdev->dev_id = ent->device;
2581 host_id &= 0x07;
2582 atpdev->host_id[0] = host_id;
2583 atpdev->scam_on = inb(base_io + 0x22);
2584 atpdev->global_map[0] = inb(base_io + 0x2d);
2585 atpdev->ultra_map[0] = inw(base_io + 0x2e);
2586
2587 if (atpdev->ultra_map[0] == 0) {
2588 atpdev->scam_on = 0x00;
2589 atpdev->global_map[0] = 0x20;
2590 atpdev->ultra_map[0] = 0xffff;
2591 }
2592
2593 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
2594 if (!shpnt)
2595 goto err_nomem;
2596
2597 p = (struct atp_unit *)&shpnt->hostdata;
2598
2599 atpdev->host = shpnt;
2600 atpdev->pdev = pdev;
2601 pci_set_drvdata(pdev, p);
2602 memcpy(p, atpdev, sizeof(*atpdev));
2603 if (atp870u_init_tables(shpnt) < 0)
2604 goto unregister;
2605
2606 if (request_irq(pdev->irq, atp870u_intr_handle, IRQF_SHARED, "atp870i", shpnt)) {
2607 printk(KERN_ERR "Unable to allocate IRQ%d for Acard controller.\n", pdev->irq);
2608 goto free_tables;
2609 }
2610
2611 spin_lock_irqsave(shpnt->host_lock, flags);
2612 if (atpdev->chip_ver > 0x07) { /* check if atp876 chip then enable terminator */
2613 outb(0x00, base_io + 0x3e);
2614 }
2615
2616 k = (inb(base_io + 0x3a) & 0xf3) | 0x10;
2617 outb(k, base_io + 0x3a);
2618 outb((k & 0xdf), base_io + 0x3a);
2619 mdelay(32);
2620 outb(k, base_io + 0x3a);
2621 mdelay(32);
2622 outb((host_id | 0x08), base_io + 0);
2623 outb(0, base_io + 0x18);
2624 while ((inb(base_io + 0x1f) & 0x80) == 0)
2625 mdelay(1);
2626
2627 inb(base_io + 0x17);
2628 outb(8, base_io + 1);
2629 outb(0x7f, base_io + 2);
2630 outb(0x20, base_io + 0x11);
2631
2632 tscam(shpnt);
2633 is870(p, base_io);
2634 outb((inb(base_io + 0x3a) & 0xef), base_io + 0x3a);
2635 outb((inb(base_io + 0x3b) | 0x20), base_io + 0x3b);
2636 if (atpdev->chip_ver == 4)
2637 shpnt->max_id = 16;
2638 else
2639 shpnt->max_id = 8;
2640 shpnt->this_id = host_id;
2641 shpnt->unique_id = base_io;
2642 shpnt->io_port = base_io;
2643 shpnt->n_io_port = 0x40; /* Number of bytes of I/O space used */
2644 shpnt->irq = pdev->irq;
2645 }
2646 spin_unlock_irqrestore(shpnt->host_lock, flags);
2647 if(ent->device==ATP885_DEVID) {
2648 if(!request_region(base_io, 0xff, "atp870u")) /* Register the IO ports that we use */
2649 goto request_io_fail;
2650 } else if((ent->device==ATP880_DEVID1)||(ent->device==ATP880_DEVID2)) {
2651 if(!request_region(base_io, 0x60, "atp870u")) /* Register the IO ports that we use */
2652 goto request_io_fail;
2653 } else {
2654 if(!request_region(base_io, 0x40, "atp870u")) /* Register the IO ports that we use */
2655 goto request_io_fail;
2656 }
2657 count++;
2658 if (scsi_add_host(shpnt, &pdev->dev))
2659 goto scsi_add_fail;
2660 scsi_scan_host(shpnt);
2661 #ifdef ED_DBGP
2662 printk("atp870u_prob : exit\n");
2663 #endif
2664 return 0;
2665
2666 scsi_add_fail:
2667 printk("atp870u_prob:scsi_add_fail\n");
2668 if(ent->device==ATP885_DEVID) {
2669 release_region(base_io, 0xff);
2670 } else if((ent->device==ATP880_DEVID1)||(ent->device==ATP880_DEVID2)) {
2671 release_region(base_io, 0x60);
2672 } else {
2673 release_region(base_io, 0x40);
2674 }
2675 request_io_fail:
2676 printk("atp870u_prob:request_io_fail\n");
2677 free_irq(pdev->irq, shpnt);
2678 free_tables:
2679 printk("atp870u_prob:free_table\n");
2680 atp870u_free_tables(shpnt);
2681 unregister:
2682 printk("atp870u_prob:unregister\n");
2683 scsi_host_put(shpnt);
2684 return -1;
2685 err_eio:
2686 kfree(atpdev);
2687 return -EIO;
2688 err_nomem:
2689 kfree(atpdev);
2690 return -ENOMEM;
2691 }
2692
2693 /* The abort command does not leave the device in a clean state where
2694 it is available to be used again. Until this gets worked out, we will
2695 leave it commented out. */
2696
2697 static int atp870u_abort(struct scsi_cmnd * SCpnt)
2698 {
2699 unsigned char j, k, c;
2700 struct scsi_cmnd *workrequ;
2701 struct atp_unit *dev;
2702 struct Scsi_Host *host;
2703 host = SCpnt->device->host;
2704
2705 dev = (struct atp_unit *)&host->hostdata;
2706 c = scmd_channel(SCpnt);
2707 printk(" atp870u: abort Channel = %x \n", c);
2708 printk("working=%x last_cmd=%x ", dev->working[c], dev->last_cmd[c]);
2709 printk(" quhdu=%x quendu=%x ", dev->quhd[c], dev->quend[c]);
2710 for (j = 0; j < 0x18; j++) {
2711 printk(" r%2x=%2x", j, inb(dev->ioport[c] + j));
2712 }
2713 printk(" r1c=%2x", inb(dev->ioport[c] + 0x1c));
2714 printk(" r1f=%2x in_snd=%2x ", inb(dev->ioport[c] + 0x1f), dev->in_snd[c]);
2715 printk(" d00=%2x", inb(dev->pciport[c]));
2716 printk(" d02=%2x", inb(dev->pciport[c] + 0x02));
2717 for(j=0;j<16;j++) {
2718 if (dev->id[c][j].curr_req != NULL) {
2719 workrequ = dev->id[c][j].curr_req;
2720 printk("\n que cdb= ");
2721 for (k=0; k < workrequ->cmd_len; k++) {
2722 printk(" %2x ",workrequ->cmnd[k]);
2723 }
2724 printk(" last_lenu= %x ",(unsigned int)dev->id[c][j].last_len);
2725 }
2726 }
2727 return SUCCESS;
2728 }
2729
2730 static const char *atp870u_info(struct Scsi_Host *notused)
2731 {
2732 static char buffer[128];
2733
2734 strcpy(buffer, "ACARD AEC-6710/6712/67160 PCI Ultra/W/LVD SCSI-3 Adapter Driver V2.6+ac ");
2735
2736 return buffer;
2737 }
2738
2739 static int atp870u_show_info(struct seq_file *m, struct Scsi_Host *HBAptr)
2740 {
2741 seq_puts(m, "ACARD AEC-671X Driver Version: 2.6+ac\n\n"
2742 "Adapter Configuration:\n");
2743 seq_printf(m, " Base IO: %#.4lx\n", HBAptr->io_port);
2744 seq_printf(m, " IRQ: %d\n", HBAptr->irq);
2745 return 0;
2746 }
2747
2748
2749 static int atp870u_biosparam(struct scsi_device *disk, struct block_device *dev,
2750 sector_t capacity, int *ip)
2751 {
2752 int heads, sectors, cylinders;
2753
2754 heads = 64;
2755 sectors = 32;
2756 cylinders = (unsigned long)capacity / (heads * sectors);
2757 if (cylinders > 1024) {
2758 heads = 255;
2759 sectors = 63;
2760 cylinders = (unsigned long)capacity / (heads * sectors);
2761 }
2762 ip[0] = heads;
2763 ip[1] = sectors;
2764 ip[2] = cylinders;
2765
2766 return 0;
2767 }
2768
2769 static void atp870u_remove (struct pci_dev *pdev)
2770 {
2771 struct atp_unit *devext = pci_get_drvdata(pdev);
2772 struct Scsi_Host *pshost = devext->host;
2773
2774
2775 scsi_remove_host(pshost);
2776 printk(KERN_INFO "free_irq : %d\n",pshost->irq);
2777 free_irq(pshost->irq, pshost);
2778 release_region(pshost->io_port, pshost->n_io_port);
2779 printk(KERN_INFO "atp870u_free_tables : %p\n",pshost);
2780 atp870u_free_tables(pshost);
2781 printk(KERN_INFO "scsi_host_put : %p\n",pshost);
2782 scsi_host_put(pshost);
2783 }
2784 MODULE_LICENSE("GPL");
2785
2786 static struct scsi_host_template atp870u_template = {
2787 .module = THIS_MODULE,
2788 .name = "atp870u" /* name */,
2789 .proc_name = "atp870u",
2790 .show_info = atp870u_show_info,
2791 .info = atp870u_info /* info */,
2792 .queuecommand = atp870u_queuecommand /* queuecommand */,
2793 .eh_abort_handler = atp870u_abort /* abort */,
2794 .bios_param = atp870u_biosparam /* biosparm */,
2795 .can_queue = qcnt /* can_queue */,
2796 .this_id = 7 /* SCSI ID */,
2797 .sg_tablesize = ATP870U_SCATTER /*SG_ALL*/ /*SG_NONE*/,
2798 .use_clustering = ENABLE_CLUSTERING,
2799 .max_sectors = ATP870U_MAX_SECTORS,
2800 };
2801
2802 static struct pci_device_id atp870u_id_table[] = {
2803 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP885_DEVID) },
2804 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID1) },
2805 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID2) },
2806 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7610) },
2807 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612UW) },
2808 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612U) },
2809 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612S) },
2810 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612D) },
2811 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612SUW) },
2812 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_8060) },
2813 { 0, },
2814 };
2815
2816 MODULE_DEVICE_TABLE(pci, atp870u_id_table);
2817
2818 static struct pci_driver atp870u_driver = {
2819 .id_table = atp870u_id_table,
2820 .name = "atp870u",
2821 .probe = atp870u_probe,
2822 .remove = atp870u_remove,
2823 };
2824
2825 static int __init atp870u_init(void)
2826 {
2827 #ifdef ED_DBGP
2828 printk("atp870u_init: Entry\n");
2829 #endif
2830 return pci_register_driver(&atp870u_driver);
2831 }
2832
2833 static void __exit atp870u_exit(void)
2834 {
2835 #ifdef ED_DBGP
2836 printk("atp870u_exit: Entry\n");
2837 #endif
2838 pci_unregister_driver(&atp870u_driver);
2839 }
2840
2841 static void tscam_885(void)
2842 {
2843 unsigned char i;
2844
2845 for (i = 0; i < 0x2; i++) {
2846 mdelay(300);
2847 }
2848 return;
2849 }
2850
2851
2852
2853 static void is885(struct atp_unit *dev, unsigned int wkport,unsigned char c)
2854 {
2855 unsigned char i, j, k, rmb, n, lvdmode;
2856 unsigned short int m;
2857 static unsigned char mbuf[512];
2858 static unsigned char satn[9] = {0, 0, 0, 0, 0, 0, 0, 6, 6};
2859 static unsigned char inqd[9] = {0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6};
2860 static unsigned char synn[6] = {0x80, 1, 3, 1, 0x19, 0x0e};
2861 unsigned char synu[6] = {0x80, 1, 3, 1, 0x0a, 0x0e};
2862 static unsigned char synw[6] = {0x80, 1, 3, 1, 0x19, 0x0e};
2863 unsigned char synuw[6] = {0x80, 1, 3, 1, 0x0a, 0x0e};
2864 static unsigned char wide[6] = {0x80, 1, 2, 3, 1, 0};
2865 static unsigned char u3[9] = { 0x80,1,6,4,0x09,00,0x0e,0x01,0x02 };
2866
2867 lvdmode=inb(wkport + 0x1b) >> 7;
2868
2869 for (i = 0; i < 16; i++) {
2870 m = 1;
2871 m = m << i;
2872 if ((m & dev->active_id[c]) != 0) {
2873 continue;
2874 }
2875 if (i == dev->host_id[c]) {
2876 printk(KERN_INFO " ID: %2d Host Adapter\n", dev->host_id[c]);
2877 continue;
2878 }
2879 outb(0x01, wkport + 0x1b);
2880 outb(0x08, wkport + 0x01);
2881 outb(0x7f, wkport + 0x02);
2882 outb(satn[0], wkport + 0x03);
2883 outb(satn[1], wkport + 0x04);
2884 outb(satn[2], wkport + 0x05);
2885 outb(satn[3], wkport + 0x06);
2886 outb(satn[4], wkport + 0x07);
2887 outb(satn[5], wkport + 0x08);
2888 outb(0, wkport + 0x0f);
2889 outb(dev->id[c][i].devsp, wkport + 0x11);
2890
2891 outb(0, wkport + 0x12);
2892 outb(satn[6], wkport + 0x13);
2893 outb(satn[7], wkport + 0x14);
2894 j = i;
2895 if ((j & 0x08) != 0) {
2896 j = (j & 0x07) | 0x40;
2897 }
2898 outb(j, wkport + 0x15);
2899 outb(satn[8], wkport + 0x18);
2900
2901 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
2902 cpu_relax();
2903 if ((inb(wkport + 0x17) != 0x11) && (inb(wkport + 0x17) != 0x8e)) {
2904 continue;
2905 }
2906 while (inb(wkport + 0x17) != 0x8e)
2907 cpu_relax();
2908 dev->active_id[c] |= m;
2909
2910 outb(0x30, wkport + 0x10);
2911 outb(0x00, wkport + 0x14);
2912
2913 phase_cmd:
2914 outb(0x08, wkport + 0x18);
2915 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
2916 cpu_relax();
2917 j = inb(wkport + 0x17);
2918 if (j != 0x16) {
2919 outb(0x41, wkport + 0x10);
2920 goto phase_cmd;
2921 }
2922 sel_ok:
2923 outb(inqd[0], wkport + 0x03);
2924 outb(inqd[1], wkport + 0x04);
2925 outb(inqd[2], wkport + 0x05);
2926 outb(inqd[3], wkport + 0x06);
2927 outb(inqd[4], wkport + 0x07);
2928 outb(inqd[5], wkport + 0x08);
2929 outb(0, wkport + 0x0f);
2930 outb(dev->id[c][i].devsp, wkport + 0x11);
2931 outb(0, wkport + 0x12);
2932 outb(inqd[6], wkport + 0x13);
2933 outb(inqd[7], wkport + 0x14);
2934 outb(inqd[8], wkport + 0x18);
2935 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
2936 cpu_relax();
2937 if ((inb(wkport + 0x17) != 0x11) && (inb(wkport + 0x17) != 0x8e)) {
2938 continue;
2939 }
2940 while (inb(wkport + 0x17) != 0x8e)
2941 cpu_relax();
2942 outb(0x00, wkport + 0x1b);
2943 outb(0x08, wkport + 0x18);
2944 j = 0;
2945 rd_inq_data:
2946 k = inb(wkport + 0x1f);
2947 if ((k & 0x01) != 0) {
2948 mbuf[j++] = inb(wkport + 0x19);
2949 goto rd_inq_data;
2950 }
2951 if ((k & 0x80) == 0) {
2952 goto rd_inq_data;
2953 }
2954 j = inb(wkport + 0x17);
2955 if (j == 0x16) {
2956 goto inq_ok;
2957 }
2958 outb(0x46, wkport + 0x10);
2959 outb(0, wkport + 0x12);
2960 outb(0, wkport + 0x13);
2961 outb(0, wkport + 0x14);
2962 outb(0x08, wkport + 0x18);
2963 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
2964 cpu_relax();
2965 if (inb(wkport + 0x17) != 0x16) {
2966 goto sel_ok;
2967 }
2968 inq_ok:
2969 mbuf[36] = 0;
2970 printk( KERN_INFO" ID: %2d %s\n", i, &mbuf[8]);
2971 dev->id[c][i].devtype = mbuf[0];
2972 rmb = mbuf[1];
2973 n = mbuf[7];
2974 if ((mbuf[7] & 0x60) == 0) {
2975 goto not_wide;
2976 }
2977 if ((i < 8) && ((dev->global_map[c] & 0x20) == 0)) {
2978 goto not_wide;
2979 }
2980 if (lvdmode == 0) {
2981 goto chg_wide;
2982 }
2983 if (dev->sp[c][i] != 0x04) { // force u2
2984 goto chg_wide;
2985 }
2986
2987 outb(0x01, wkport + 0x1b);
2988 outb(satn[0], wkport + 0x03);
2989 outb(satn[1], wkport + 0x04);
2990 outb(satn[2], wkport + 0x05);
2991 outb(satn[3], wkport + 0x06);
2992 outb(satn[4], wkport + 0x07);
2993 outb(satn[5], wkport + 0x08);
2994 outb(0, wkport + 0x0f);
2995 outb(dev->id[c][i].devsp, wkport + 0x11);
2996 outb(0, wkport + 0x12);
2997 outb(satn[6], wkport + 0x13);
2998 outb(satn[7], wkport + 0x14);
2999 outb(satn[8], wkport + 0x18);
3000
3001 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
3002 cpu_relax();
3003 if ((inb(wkport + 0x17) != 0x11) && (inb(wkport + 0x17) != 0x8e)) {
3004 continue;
3005 }
3006 while (inb(wkport + 0x17) != 0x8e)
3007 cpu_relax();
3008 try_u3:
3009 j = 0;
3010 outb(0x09, wkport + 0x14);
3011 outb(0x20, wkport + 0x18);
3012
3013 while ((inb(wkport + 0x1f) & 0x80) == 0) {
3014 if ((inb(wkport + 0x1f) & 0x01) != 0)
3015 outb(u3[j++], wkport + 0x19);
3016 cpu_relax();
3017 }
3018 while ((inb(wkport + 0x17) & 0x80) == 0x00)
3019 cpu_relax();
3020 j = inb(wkport + 0x17) & 0x0f;
3021 if (j == 0x0f) {
3022 goto u3p_in;
3023 }
3024 if (j == 0x0a) {
3025 goto u3p_cmd;
3026 }
3027 if (j == 0x0e) {
3028 goto try_u3;
3029 }
3030 continue;
3031 u3p_out:
3032 outb(0x20, wkport + 0x18);
3033 while ((inb(wkport + 0x1f) & 0x80) == 0) {
3034 if ((inb(wkport + 0x1f) & 0x01) != 0)
3035 outb(0, wkport + 0x19);
3036 cpu_relax();
3037 }
3038 j = inb(wkport + 0x17) & 0x0f;
3039 if (j == 0x0f) {
3040 goto u3p_in;
3041 }
3042 if (j == 0x0a) {
3043 goto u3p_cmd;
3044 }
3045 if (j == 0x0e) {
3046 goto u3p_out;
3047 }
3048 continue;
3049 u3p_in:
3050 outb(0x09, wkport + 0x14);
3051 outb(0x20, wkport + 0x18);
3052 k = 0;
3053 u3p_in1:
3054 j = inb(wkport + 0x1f);
3055 if ((j & 0x01) != 0) {
3056 mbuf[k++] = inb(wkport + 0x19);
3057 goto u3p_in1;
3058 }
3059 if ((j & 0x80) == 0x00) {
3060 goto u3p_in1;
3061 }
3062 j = inb(wkport + 0x17) & 0x0f;
3063 if (j == 0x0f) {
3064 goto u3p_in;
3065 }
3066 if (j == 0x0a) {
3067 goto u3p_cmd;
3068 }
3069 if (j == 0x0e) {
3070 goto u3p_out;
3071 }
3072 continue;
3073 u3p_cmd:
3074 outb(0x30, wkport + 0x10);
3075 outb(0x00, wkport + 0x14);
3076 outb(0x08, wkport + 0x18);
3077 while ((inb(wkport + 0x1f) & 0x80) == 0x00);
3078 j = inb(wkport + 0x17);
3079 if (j != 0x16) {
3080 if (j == 0x4e) {
3081 goto u3p_out;
3082 }
3083 continue;
3084 }
3085 if (mbuf[0] != 0x01) {
3086 goto chg_wide;
3087 }
3088 if (mbuf[1] != 0x06) {
3089 goto chg_wide;
3090 }
3091 if (mbuf[2] != 0x04) {
3092 goto chg_wide;
3093 }
3094 if (mbuf[3] == 0x09) {
3095 m = 1;
3096 m = m << i;
3097 dev->wide_id[c] |= m;
3098 dev->id[c][i].devsp = 0xce;
3099 #ifdef ED_DBGP
3100 printk("dev->id[%2d][%2d].devsp = %2x\n",c,i,dev->id[c][i].devsp);
3101 #endif
3102 continue;
3103 }
3104 chg_wide:
3105 outb(0x01, wkport + 0x1b);
3106 outb(satn[0], wkport + 0x03);
3107 outb(satn[1], wkport + 0x04);
3108 outb(satn[2], wkport + 0x05);
3109 outb(satn[3], wkport + 0x06);
3110 outb(satn[4], wkport + 0x07);
3111 outb(satn[5], wkport + 0x08);
3112 outb(0, wkport + 0x0f);
3113 outb(dev->id[c][i].devsp, wkport + 0x11);
3114 outb(0, wkport + 0x12);
3115 outb(satn[6], wkport + 0x13);
3116 outb(satn[7], wkport + 0x14);
3117 outb(satn[8], wkport + 0x18);
3118
3119 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
3120 cpu_relax();
3121 if ((inb(wkport + 0x17) != 0x11) && (inb(wkport + 0x17) != 0x8e)) {
3122 continue;
3123 }
3124 while (inb(wkport + 0x17) != 0x8e)
3125 cpu_relax();
3126 try_wide:
3127 j = 0;
3128 outb(0x05, wkport + 0x14);
3129 outb(0x20, wkport + 0x18);
3130
3131 while ((inb(wkport + 0x1f) & 0x80) == 0) {
3132 if ((inb(wkport + 0x1f) & 0x01) != 0)
3133 outb(wide[j++], wkport + 0x19);
3134 cpu_relax();
3135 }
3136 while ((inb(wkport + 0x17) & 0x80) == 0x00)
3137 cpu_relax();
3138 j = inb(wkport + 0x17) & 0x0f;
3139 if (j == 0x0f) {
3140 goto widep_in;
3141 }
3142 if (j == 0x0a) {
3143 goto widep_cmd;
3144 }
3145 if (j == 0x0e) {
3146 goto try_wide;
3147 }
3148 continue;
3149 widep_out:
3150 outb(0x20, wkport + 0x18);
3151 while ((inb(wkport + 0x1f) & 0x80) == 0) {
3152 if ((inb(wkport + 0x1f) & 0x01) != 0)
3153 outb(0, wkport + 0x19);
3154 cpu_relax();
3155 }
3156 j = inb(wkport + 0x17) & 0x0f;
3157 if (j == 0x0f) {
3158 goto widep_in;
3159 }
3160 if (j == 0x0a) {
3161 goto widep_cmd;
3162 }
3163 if (j == 0x0e) {
3164 goto widep_out;
3165 }
3166 continue;
3167 widep_in:
3168 outb(0xff, wkport + 0x14);
3169 outb(0x20, wkport + 0x18);
3170 k = 0;
3171 widep_in1:
3172 j = inb(wkport + 0x1f);
3173 if ((j & 0x01) != 0) {
3174 mbuf[k++] = inb(wkport + 0x19);
3175 goto widep_in1;
3176 }
3177 if ((j & 0x80) == 0x00) {
3178 goto widep_in1;
3179 }
3180 j = inb(wkport + 0x17) & 0x0f;
3181 if (j == 0x0f) {
3182 goto widep_in;
3183 }
3184 if (j == 0x0a) {
3185 goto widep_cmd;
3186 }
3187 if (j == 0x0e) {
3188 goto widep_out;
3189 }
3190 continue;
3191 widep_cmd:
3192 outb(0x30, wkport + 0x10);
3193 outb(0x00, wkport + 0x14);
3194 outb(0x08, wkport + 0x18);
3195 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
3196 cpu_relax();
3197 j = inb(wkport + 0x17);
3198 if (j != 0x16) {
3199 if (j == 0x4e) {
3200 goto widep_out;
3201 }
3202 continue;
3203 }
3204 if (mbuf[0] != 0x01) {
3205 goto not_wide;
3206 }
3207 if (mbuf[1] != 0x02) {
3208 goto not_wide;
3209 }
3210 if (mbuf[2] != 0x03) {
3211 goto not_wide;
3212 }
3213 if (mbuf[3] != 0x01) {
3214 goto not_wide;
3215 }
3216 m = 1;
3217 m = m << i;
3218 dev->wide_id[c] |= m;
3219 not_wide:
3220 if ((dev->id[c][i].devtype == 0x00) || (dev->id[c][i].devtype == 0x07) ||
3221 ((dev->id[c][i].devtype == 0x05) && ((n & 0x10) != 0))) {
3222 m = 1;
3223 m = m << i;
3224 if ((dev->async[c] & m) != 0) {
3225 goto set_sync;
3226 }
3227 }
3228 continue;
3229 set_sync:
3230 if (dev->sp[c][i] == 0x02) {
3231 synu[4]=0x0c;
3232 synuw[4]=0x0c;
3233 } else {
3234 if (dev->sp[c][i] >= 0x03) {
3235 synu[4]=0x0a;
3236 synuw[4]=0x0a;
3237 }
3238 }
3239 j = 0;
3240 if ((m & dev->wide_id[c]) != 0) {
3241 j |= 0x01;
3242 }
3243 outb(j, wkport + 0x1b);
3244 outb(satn[0], wkport + 0x03);
3245 outb(satn[1], wkport + 0x04);
3246 outb(satn[2], wkport + 0x05);
3247 outb(satn[3], wkport + 0x06);
3248 outb(satn[4], wkport + 0x07);
3249 outb(satn[5], wkport + 0x08);
3250 outb(0, wkport + 0x0f);
3251 outb(dev->id[c][i].devsp, wkport + 0x11);
3252 outb(0, wkport + 0x12);
3253 outb(satn[6], wkport + 0x13);
3254 outb(satn[7], wkport + 0x14);
3255 outb(satn[8], wkport + 0x18);
3256
3257 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
3258 cpu_relax();
3259 if ((inb(wkport + 0x17) != 0x11) && (inb(wkport + 0x17) != 0x8e)) {
3260 continue;
3261 }
3262 while (inb(wkport + 0x17) != 0x8e)
3263 cpu_relax();
3264 try_sync:
3265 j = 0;
3266 outb(0x06, wkport + 0x14);
3267 outb(0x20, wkport + 0x18);
3268
3269 while ((inb(wkport + 0x1f) & 0x80) == 0) {
3270 if ((inb(wkport + 0x1f) & 0x01) != 0) {
3271 if ((m & dev->wide_id[c]) != 0) {
3272 if ((m & dev->ultra_map[c]) != 0) {
3273 outb(synuw[j++], wkport + 0x19);
3274 } else {
3275 outb(synw[j++], wkport + 0x19);
3276 }
3277 } else {
3278 if ((m & dev->ultra_map[c]) != 0) {
3279 outb(synu[j++], wkport + 0x19);
3280 } else {
3281 outb(synn[j++], wkport + 0x19);
3282 }
3283 }
3284 }
3285 }
3286 while ((inb(wkport + 0x17) & 0x80) == 0x00)
3287 cpu_relax();
3288 j = inb(wkport + 0x17) & 0x0f;
3289 if (j == 0x0f) {
3290 goto phase_ins;
3291 }
3292 if (j == 0x0a) {
3293 goto phase_cmds;
3294 }
3295 if (j == 0x0e) {
3296 goto try_sync;
3297 }
3298 continue;
3299 phase_outs:
3300 outb(0x20, wkport + 0x18);
3301 while ((inb(wkport + 0x1f) & 0x80) == 0x00) {
3302 if ((inb(wkport + 0x1f) & 0x01) != 0x00)
3303 outb(0x00, wkport + 0x19);
3304 cpu_relax();
3305 }
3306 j = inb(wkport + 0x17);
3307 if (j == 0x85) {
3308 goto tar_dcons;
3309 }
3310 j &= 0x0f;
3311 if (j == 0x0f) {
3312 goto phase_ins;
3313 }
3314 if (j == 0x0a) {
3315 goto phase_cmds;
3316 }
3317 if (j == 0x0e) {
3318 goto phase_outs;
3319 }
3320 continue;
3321 phase_ins:
3322 outb(0x06, wkport + 0x14);
3323 outb(0x20, wkport + 0x18);
3324 k = 0;
3325 phase_ins1:
3326 j = inb(wkport + 0x1f);
3327 if ((j & 0x01) != 0x00) {
3328 mbuf[k++] = inb(wkport + 0x19);
3329 goto phase_ins1;
3330 }
3331 if ((j & 0x80) == 0x00) {
3332 goto phase_ins1;
3333 }
3334 while ((inb(wkport + 0x17) & 0x80) == 0x00);
3335 j = inb(wkport + 0x17);
3336 if (j == 0x85) {
3337 goto tar_dcons;
3338 }
3339 j &= 0x0f;
3340 if (j == 0x0f) {
3341 goto phase_ins;
3342 }
3343 if (j == 0x0a) {
3344 goto phase_cmds;
3345 }
3346 if (j == 0x0e) {
3347 goto phase_outs;
3348 }
3349 continue;
3350 phase_cmds:
3351 outb(0x30, wkport + 0x10);
3352 tar_dcons:
3353 outb(0x00, wkport + 0x14);
3354 outb(0x08, wkport + 0x18);
3355 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
3356 cpu_relax();
3357 j = inb(wkport + 0x17);
3358 if (j != 0x16) {
3359 continue;
3360 }
3361 if (mbuf[0] != 0x01) {
3362 continue;
3363 }
3364 if (mbuf[1] != 0x03) {
3365 continue;
3366 }
3367 if (mbuf[4] == 0x00) {
3368 continue;
3369 }
3370 if (mbuf[3] > 0x64) {
3371 continue;
3372 }
3373 if (mbuf[4] > 0x0e) {
3374 mbuf[4] = 0x0e;
3375 }
3376 dev->id[c][i].devsp = mbuf[4];
3377 if (mbuf[3] < 0x0c){
3378 j = 0xb0;
3379 goto set_syn_ok;
3380 }
3381 if ((mbuf[3] < 0x0d) && (rmb == 0)) {
3382 j = 0xa0;
3383 goto set_syn_ok;
3384 }
3385 if (mbuf[3] < 0x1a) {
3386 j = 0x20;
3387 goto set_syn_ok;
3388 }
3389 if (mbuf[3] < 0x33) {
3390 j = 0x40;
3391 goto set_syn_ok;
3392 }
3393 if (mbuf[3] < 0x4c) {
3394 j = 0x50;
3395 goto set_syn_ok;
3396 }
3397 j = 0x60;
3398 set_syn_ok:
3399 dev->id[c][i].devsp = (dev->id[c][i].devsp & 0x0f) | j;
3400 #ifdef ED_DBGP
3401 printk("dev->id[%2d][%2d].devsp = %2x\n",c,i,dev->id[c][i].devsp);
3402 #endif
3403 }
3404 outb(0x80, wkport + 0x16);
3405 }
3406
3407 module_init(atp870u_init);
3408 module_exit(atp870u_exit);
3409
Linux kernel - Deliverables
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