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atp870u: Add channel parameter to is870() and is880()
[deliverable/linux.git] / drivers / scsi / atp870u.c
1 /*
2 * Copyright (C) 1997 Wu Ching Chen
3 * 2.1.x update (C) 1998 Krzysztof G. Baranowski
4 * 2.5.x update (C) 2002 Red Hat
5 * 2.6.x update (C) 2004 Red Hat
6 *
7 * Marcelo Tosatti <marcelo@conectiva.com.br> : SMP fixes
8 *
9 * Wu Ching Chen : NULL pointer fixes 2000/06/02
10 * support atp876 chip
11 * enable 32 bit fifo transfer
12 * support cdrom & remove device run ultra speed
13 * fix disconnect bug 2000/12/21
14 * support atp880 chip lvd u160 2001/05/15
15 * fix prd table bug 2001/09/12 (7.1)
16 *
17 * atp885 support add by ACARD Hao Ping Lian 2005/01/05
18 */
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/string.h>
25 #include <linux/ioport.h>
26 #include <linux/delay.h>
27 #include <linux/proc_fs.h>
28 #include <linux/spinlock.h>
29 #include <linux/pci.h>
30 #include <linux/blkdev.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/slab.h>
33 #include <asm/io.h>
34
35 #include <scsi/scsi.h>
36 #include <scsi/scsi_cmnd.h>
37 #include <scsi/scsi_device.h>
38 #include <scsi/scsi_host.h>
39
40 #include "atp870u.h"
41
42 static struct scsi_host_template atp870u_template;
43 static void send_s870(struct atp_unit *dev,unsigned char c);
44 static void is885(struct atp_unit *dev, unsigned char c);
45 static void tscam_885(void);
46
47 static inline void atp_writeb_base(struct atp_unit *atp, u8 reg, u8 val)
48 {
49 outb(val, atp->baseport + reg);
50 }
51
52 static inline void atp_writeb_io(struct atp_unit *atp, u8 channel, u8 reg, u8 val)
53 {
54 outb(val, atp->ioport[channel] + reg);
55 }
56
57 static inline void atp_writew_io(struct atp_unit *atp, u8 channel, u8 reg, u16 val)
58 {
59 outw(val, atp->ioport[channel] + reg);
60 }
61
62 static inline void atp_writeb_pci(struct atp_unit *atp, u8 channel, u8 reg, u8 val)
63 {
64 outb(val, atp->pciport[channel] + reg);
65 }
66
67 static inline void atp_writel_pci(struct atp_unit *atp, u8 channel, u8 reg, u32 val)
68 {
69 outl(val, atp->pciport[channel] + reg);
70 }
71
72 static inline u8 atp_readb_base(struct atp_unit *atp, u8 reg)
73 {
74 return inb(atp->baseport + reg);
75 }
76
77 static inline u8 atp_readb_io(struct atp_unit *atp, u8 channel, u8 reg)
78 {
79 return inb(atp->ioport[channel] + reg);
80 }
81
82 static inline u16 atp_readw_io(struct atp_unit *atp, u8 channel, u8 reg)
83 {
84 return inw(atp->ioport[channel] + reg);
85 }
86
87 static inline u8 atp_readb_pci(struct atp_unit *atp, u8 channel, u8 reg)
88 {
89 return inb(atp->pciport[channel] + reg);
90 }
91
92 static irqreturn_t atp870u_intr_handle(int irq, void *dev_id)
93 {
94 unsigned long flags;
95 unsigned short int id;
96 unsigned char i, j, c, target_id, lun,cmdp;
97 unsigned char *prd;
98 struct scsi_cmnd *workreq;
99 unsigned long adrcnt, k;
100 #ifdef ED_DBGP
101 unsigned long l;
102 #endif
103 struct Scsi_Host *host = dev_id;
104 struct atp_unit *dev = (struct atp_unit *)&host->hostdata;
105
106 for (c = 0; c < 2; c++) {
107 j = atp_readb_io(dev, c, 0x1f);
108 if ((j & 0x80) != 0)
109 break;
110 dev->in_int[c] = 0;
111 }
112 if ((j & 0x80) == 0)
113 return IRQ_NONE;
114 #ifdef ED_DBGP
115 printk("atp870u_intr_handle enter\n");
116 #endif
117 dev->in_int[c] = 1;
118 cmdp = atp_readb_io(dev, c, 0x10);
119 if (dev->working[c] != 0) {
120 if (dev->dev_id == ATP885_DEVID) {
121 if ((atp_readb_io(dev, c, 0x16) & 0x80) == 0)
122 atp_writeb_io(dev, c, 0x16, (atp_readb_io(dev, c, 0x16) | 0x80));
123 }
124 if ((atp_readb_pci(dev, c, 0x00) & 0x08) != 0)
125 {
126 for (k=0; k < 1000; k++) {
127 if ((atp_readb_pci(dev, c, 2) & 0x08) == 0)
128 break;
129 if ((atp_readb_pci(dev, c, 2) & 0x01) == 0)
130 break;
131 }
132 }
133 atp_writeb_pci(dev, c, 0, 0x00);
134
135 i = atp_readb_io(dev, c, 0x17);
136
137 if (dev->dev_id == ATP885_DEVID)
138 atp_writeb_pci(dev, c, 2, 0x06);
139
140 target_id = atp_readb_io(dev, c, 0x15);
141
142 /*
143 * Remap wide devices onto id numbers
144 */
145
146 if ((target_id & 0x40) != 0) {
147 target_id = (target_id & 0x07) | 0x08;
148 } else {
149 target_id &= 0x07;
150 }
151
152 if ((j & 0x40) != 0) {
153 if (dev->last_cmd[c] == 0xff) {
154 dev->last_cmd[c] = target_id;
155 }
156 dev->last_cmd[c] |= 0x40;
157 }
158 if (dev->dev_id == ATP885_DEVID)
159 dev->r1f[c][target_id] |= j;
160 #ifdef ED_DBGP
161 printk("atp870u_intr_handle status = %x\n",i);
162 #endif
163 if (i == 0x85) {
164 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
165 dev->last_cmd[c] = 0xff;
166 }
167 if (dev->dev_id == ATP885_DEVID) {
168 adrcnt = 0;
169 ((unsigned char *) &adrcnt)[2] = atp_readb_io(dev, c, 0x12);
170 ((unsigned char *) &adrcnt)[1] = atp_readb_io(dev, c, 0x13);
171 ((unsigned char *) &adrcnt)[0] = atp_readb_io(dev, c, 0x14);
172 if (dev->id[c][target_id].last_len != adrcnt)
173 {
174 k = dev->id[c][target_id].last_len;
175 k -= adrcnt;
176 dev->id[c][target_id].tran_len = k;
177 dev->id[c][target_id].last_len = adrcnt;
178 }
179 #ifdef ED_DBGP
180 printk("dev->id[c][target_id].last_len = %d dev->id[c][target_id].tran_len = %d\n",dev->id[c][target_id].last_len,dev->id[c][target_id].tran_len);
181 #endif
182 }
183
184 /*
185 * Flip wide
186 */
187 if (dev->wide_id[c] != 0) {
188 atp_writeb_io(dev, c, 0x1b, 0x01);
189 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != 0x01)
190 atp_writeb_io(dev, c, 0x1b, 0x01);
191 }
192 /*
193 * Issue more commands
194 */
195 spin_lock_irqsave(dev->host->host_lock, flags);
196 if (((dev->quhd[c] != dev->quend[c]) || (dev->last_cmd[c] != 0xff)) &&
197 (dev->in_snd[c] == 0)) {
198 #ifdef ED_DBGP
199 printk("Call sent_s870\n");
200 #endif
201 send_s870(dev,c);
202 }
203 spin_unlock_irqrestore(dev->host->host_lock, flags);
204 /*
205 * Done
206 */
207 dev->in_int[c] = 0;
208 #ifdef ED_DBGP
209 printk("Status 0x85 return\n");
210 #endif
211 return IRQ_HANDLED;
212 }
213
214 if (i == 0x40) {
215 dev->last_cmd[c] |= 0x40;
216 dev->in_int[c] = 0;
217 return IRQ_HANDLED;
218 }
219
220 if (i == 0x21) {
221 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
222 dev->last_cmd[c] = 0xff;
223 }
224 adrcnt = 0;
225 ((unsigned char *) &adrcnt)[2] = atp_readb_io(dev, c, 0x12);
226 ((unsigned char *) &adrcnt)[1] = atp_readb_io(dev, c, 0x13);
227 ((unsigned char *) &adrcnt)[0] = atp_readb_io(dev, c, 0x14);
228 k = dev->id[c][target_id].last_len;
229 k -= adrcnt;
230 dev->id[c][target_id].tran_len = k;
231 dev->id[c][target_id].last_len = adrcnt;
232 atp_writeb_io(dev, c, 0x10, 0x41);
233 atp_writeb_io(dev, c, 0x18, 0x08);
234 dev->in_int[c] = 0;
235 return IRQ_HANDLED;
236 }
237
238 if (dev->dev_id == ATP885_DEVID) {
239 if ((i == 0x4c) || (i == 0x4d) || (i == 0x8c) || (i == 0x8d)) {
240 if ((i == 0x4c) || (i == 0x8c))
241 i=0x48;
242 else
243 i=0x49;
244 }
245
246 }
247 if ((i == 0x80) || (i == 0x8f)) {
248 #ifdef ED_DBGP
249 printk(KERN_DEBUG "Device reselect\n");
250 #endif
251 lun = 0;
252 if (cmdp == 0x44 || i == 0x80)
253 lun = atp_readb_io(dev, c, 0x1d) & 0x07;
254 else {
255 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
256 dev->last_cmd[c] = 0xff;
257 }
258 if (cmdp == 0x41) {
259 #ifdef ED_DBGP
260 printk("cmdp = 0x41\n");
261 #endif
262 adrcnt = 0;
263 ((unsigned char *) &adrcnt)[2] = atp_readb_io(dev, c, 0x12);
264 ((unsigned char *) &adrcnt)[1] = atp_readb_io(dev, c, 0x13);
265 ((unsigned char *) &adrcnt)[0] = atp_readb_io(dev, c, 0x14);
266 k = dev->id[c][target_id].last_len;
267 k -= adrcnt;
268 dev->id[c][target_id].tran_len = k;
269 dev->id[c][target_id].last_len = adrcnt;
270 atp_writeb_io(dev, c, 0x18, 0x08);
271 dev->in_int[c] = 0;
272 return IRQ_HANDLED;
273 } else {
274 #ifdef ED_DBGP
275 printk("cmdp != 0x41\n");
276 #endif
277 atp_writeb_io(dev, c, 0x10, 0x46);
278 dev->id[c][target_id].dirct = 0x00;
279 atp_writeb_io(dev, c, 0x12, 0x00);
280 atp_writeb_io(dev, c, 0x13, 0x00);
281 atp_writeb_io(dev, c, 0x14, 0x00);
282 atp_writeb_io(dev, c, 0x18, 0x08);
283 dev->in_int[c] = 0;
284 return IRQ_HANDLED;
285 }
286 }
287 if (dev->last_cmd[c] != 0xff) {
288 dev->last_cmd[c] |= 0x40;
289 }
290 if (dev->dev_id == ATP885_DEVID) {
291 j = atp_readb_base(dev, 0x29) & 0xfe;
292 atp_writeb_base(dev, 0x29, j);
293 } else
294 atp_writeb_io(dev, c, 0x10, 0x45);
295
296 target_id = atp_readb_io(dev, c, 0x16);
297 /*
298 * Remap wide identifiers
299 */
300 if ((target_id & 0x10) != 0) {
301 target_id = (target_id & 0x07) | 0x08;
302 } else {
303 target_id &= 0x07;
304 }
305 if (dev->dev_id == ATP885_DEVID)
306 atp_writeb_io(dev, c, 0x10, 0x45);
307 workreq = dev->id[c][target_id].curr_req;
308 #ifdef ED_DBGP
309 scmd_printk(KERN_DEBUG, workreq, "CDB");
310 for (l = 0; l < workreq->cmd_len; l++)
311 printk(KERN_DEBUG " %x",workreq->cmnd[l]);
312 printk("\n");
313 #endif
314
315 atp_writeb_io(dev, c, 0x0f, lun);
316 atp_writeb_io(dev, c, 0x11, dev->id[c][target_id].devsp);
317 adrcnt = dev->id[c][target_id].tran_len;
318 k = dev->id[c][target_id].last_len;
319
320 atp_writeb_io(dev, c, 0x12, ((unsigned char *) &k)[2]);
321 atp_writeb_io(dev, c, 0x13, ((unsigned char *) &k)[1]);
322 atp_writeb_io(dev, c, 0x14, ((unsigned char *) &k)[0]);
323 #ifdef ED_DBGP
324 printk("k %x, k[0] 0x%x k[1] 0x%x k[2] 0x%x\n", k, atp_readb_io(dev, c, 0x14), atp_readb_io(dev, c, 0x13), atp_readb_io(dev, c, 0x12));
325 #endif
326 /* Remap wide */
327 j = target_id;
328 if (target_id > 7) {
329 j = (j & 0x07) | 0x40;
330 }
331 /* Add direction */
332 j |= dev->id[c][target_id].dirct;
333 atp_writeb_io(dev, c, 0x15, j);
334 atp_writeb_io(dev, c, 0x16, 0x80);
335
336 /* enable 32 bit fifo transfer */
337 if (dev->dev_id == ATP885_DEVID) {
338 i = atp_readb_pci(dev, c, 1) & 0xf3;
339 //j=workreq->cmnd[0];
340 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
341 i |= 0x0c;
342 }
343 atp_writeb_pci(dev, c, 1, i);
344 } else if ((dev->dev_id == ATP880_DEVID1) ||
345 (dev->dev_id == ATP880_DEVID2) ) {
346 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a))
347 atp_writeb_base(dev, 0x3b, (atp_readb_base(dev, 0x3b) & 0x3f) | 0xc0);
348 else
349 atp_writeb_base(dev, 0x3b, atp_readb_base(dev, 0x3b) & 0x3f);
350 } else {
351 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a))
352 atp_writeb_io(dev, c, 0x3a, (atp_readb_io(dev, c, 0x3a) & 0xf3) | 0x08);
353 else
354 atp_writeb_io(dev, c, 0x3a, atp_readb_io(dev, c, 0x3a) & 0xf3);
355 }
356 j = 0;
357 id = 1;
358 id = id << target_id;
359 /*
360 * Is this a wide device
361 */
362 if ((id & dev->wide_id[c]) != 0) {
363 j |= 0x01;
364 }
365 atp_writeb_io(dev, c, 0x1b, j);
366 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != j)
367 atp_writeb_io(dev, c, 0x1b, j);
368 if (dev->id[c][target_id].last_len == 0) {
369 atp_writeb_io(dev, c, 0x18, 0x08);
370 dev->in_int[c] = 0;
371 #ifdef ED_DBGP
372 printk("dev->id[c][target_id].last_len = 0\n");
373 #endif
374 return IRQ_HANDLED;
375 }
376 #ifdef ED_DBGP
377 printk("target_id = %d adrcnt = %d\n",target_id,adrcnt);
378 #endif
379 prd = dev->id[c][target_id].prd_pos;
380 while (adrcnt != 0) {
381 id = ((unsigned short int *)prd)[2];
382 if (id == 0) {
383 k = 0x10000;
384 } else {
385 k = id;
386 }
387 if (k > adrcnt) {
388 ((unsigned short int *)prd)[2] = (unsigned short int)
389 (k - adrcnt);
390 ((unsigned long *)prd)[0] += adrcnt;
391 adrcnt = 0;
392 dev->id[c][target_id].prd_pos = prd;
393 } else {
394 adrcnt -= k;
395 dev->id[c][target_id].prdaddr += 0x08;
396 prd += 0x08;
397 if (adrcnt == 0) {
398 dev->id[c][target_id].prd_pos = prd;
399 }
400 }
401 }
402 atp_writel_pci(dev, c, 0x04, dev->id[c][target_id].prdaddr);
403 #ifdef ED_DBGP
404 printk("dev->id[%d][%d].prdaddr 0x%8x\n", c, target_id, dev->id[c][target_id].prdaddr);
405 #endif
406 if (dev->dev_id != ATP885_DEVID) {
407 atp_writeb_pci(dev, c, 2, 0x06);
408 atp_writeb_pci(dev, c, 2, 0x00);
409 }
410 /*
411 * Check transfer direction
412 */
413 if (dev->id[c][target_id].dirct != 0) {
414 atp_writeb_io(dev, c, 0x18, 0x08);
415 atp_writeb_pci(dev, c, 0, 0x01);
416 dev->in_int[c] = 0;
417 #ifdef ED_DBGP
418 printk("status 0x80 return dirct != 0\n");
419 #endif
420 return IRQ_HANDLED;
421 }
422 atp_writeb_io(dev, c, 0x18, 0x08);
423 atp_writeb_pci(dev, c, 0, 0x09);
424 dev->in_int[c] = 0;
425 #ifdef ED_DBGP
426 printk("status 0x80 return dirct = 0\n");
427 #endif
428 return IRQ_HANDLED;
429 }
430
431 /*
432 * Current scsi request on this target
433 */
434
435 workreq = dev->id[c][target_id].curr_req;
436
437 if (i == 0x42 || i == 0x16) {
438 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
439 dev->last_cmd[c] = 0xff;
440 }
441 if (i == 0x16) {
442 workreq->result = atp_readb_io(dev, c, 0x0f);
443 if (((dev->r1f[c][target_id] & 0x10) != 0)&&(dev->dev_id==ATP885_DEVID)) {
444 printk(KERN_WARNING "AEC67162 CRC ERROR !\n");
445 workreq->result = 0x02;
446 }
447 } else
448 workreq->result = 0x02;
449
450 if (dev->dev_id == ATP885_DEVID) {
451 j = atp_readb_base(dev, 0x29) | 0x01;
452 atp_writeb_base(dev, 0x29, j);
453 }
454 /*
455 * Complete the command
456 */
457 scsi_dma_unmap(workreq);
458
459 spin_lock_irqsave(dev->host->host_lock, flags);
460 (*workreq->scsi_done) (workreq);
461 #ifdef ED_DBGP
462 printk("workreq->scsi_done\n");
463 #endif
464 /*
465 * Clear it off the queue
466 */
467 dev->id[c][target_id].curr_req = NULL;
468 dev->working[c]--;
469 spin_unlock_irqrestore(dev->host->host_lock, flags);
470 /*
471 * Take it back wide
472 */
473 if (dev->wide_id[c] != 0) {
474 atp_writeb_io(dev, c, 0x1b, 0x01);
475 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != 0x01)
476 atp_writeb_io(dev, c, 0x1b, 0x01);
477 }
478 /*
479 * If there is stuff to send and nothing going then send it
480 */
481 spin_lock_irqsave(dev->host->host_lock, flags);
482 if (((dev->last_cmd[c] != 0xff) || (dev->quhd[c] != dev->quend[c])) &&
483 (dev->in_snd[c] == 0)) {
484 #ifdef ED_DBGP
485 printk("Call sent_s870(scsi_done)\n");
486 #endif
487 send_s870(dev,c);
488 }
489 spin_unlock_irqrestore(dev->host->host_lock, flags);
490 dev->in_int[c] = 0;
491 return IRQ_HANDLED;
492 }
493 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
494 dev->last_cmd[c] = 0xff;
495 }
496 if (i == 0x4f) {
497 i = 0x89;
498 }
499 i &= 0x0f;
500 if (i == 0x09) {
501 atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr);
502 atp_writeb_pci(dev, c, 2, 0x06);
503 atp_writeb_pci(dev, c, 2, 0x00);
504 atp_writeb_io(dev, c, 0x10, 0x41);
505 if (dev->dev_id == ATP885_DEVID) {
506 k = dev->id[c][target_id].last_len;
507 atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&k))[2]);
508 atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&k))[1]);
509 atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&k))[0]);
510 dev->id[c][target_id].dirct = 0x00;
511 } else {
512 dev->id[c][target_id].dirct = 0x00;
513 }
514 atp_writeb_io(dev, c, 0x18, 0x08);
515 atp_writeb_pci(dev, c, 0, 0x09);
516 dev->in_int[c] = 0;
517 return IRQ_HANDLED;
518 }
519 if (i == 0x08) {
520 atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr);
521 atp_writeb_pci(dev, c, 2, 0x06);
522 atp_writeb_pci(dev, c, 2, 0x00);
523 atp_writeb_io(dev, c, 0x10, 0x41);
524 if (dev->dev_id == ATP885_DEVID) {
525 k = dev->id[c][target_id].last_len;
526 atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&k))[2]);
527 atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&k))[1]);
528 atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&k))[0]);
529 }
530 atp_writeb_io(dev, c, 0x15, atp_readb_io(dev, c, 0x15) | 0x20);
531 dev->id[c][target_id].dirct = 0x20;
532 atp_writeb_io(dev, c, 0x18, 0x08);
533 atp_writeb_pci(dev, c, 0, 0x01);
534 dev->in_int[c] = 0;
535 return IRQ_HANDLED;
536 }
537 if (i == 0x0a)
538 atp_writeb_io(dev, c, 0x10, 0x30);
539 else
540 atp_writeb_io(dev, c, 0x10, 0x46);
541 dev->id[c][target_id].dirct = 0x00;
542 atp_writeb_io(dev, c, 0x12, 0x00);
543 atp_writeb_io(dev, c, 0x13, 0x00);
544 atp_writeb_io(dev, c, 0x14, 0x00);
545 atp_writeb_io(dev, c, 0x18, 0x08);
546 }
547 dev->in_int[c] = 0;
548
549 return IRQ_HANDLED;
550 }
551 /**
552 * atp870u_queuecommand - Queue SCSI command
553 * @req_p: request block
554 * @done: completion function
555 *
556 * Queue a command to the ATP queue. Called with the host lock held.
557 */
558 static int atp870u_queuecommand_lck(struct scsi_cmnd *req_p,
559 void (*done) (struct scsi_cmnd *))
560 {
561 unsigned char c;
562 unsigned int m;
563 struct atp_unit *dev;
564 struct Scsi_Host *host;
565
566 c = scmd_channel(req_p);
567 req_p->sense_buffer[0]=0;
568 scsi_set_resid(req_p, 0);
569 if (scmd_channel(req_p) > 1) {
570 req_p->result = 0x00040000;
571 done(req_p);
572 #ifdef ED_DBGP
573 printk("atp870u_queuecommand : req_p->device->channel > 1\n");
574 #endif
575 return 0;
576 }
577
578 host = req_p->device->host;
579 dev = (struct atp_unit *)&host->hostdata;
580
581
582
583 m = 1;
584 m = m << scmd_id(req_p);
585
586 /*
587 * Fake a timeout for missing targets
588 */
589
590 if ((m & dev->active_id[c]) == 0) {
591 req_p->result = 0x00040000;
592 done(req_p);
593 return 0;
594 }
595
596 if (done) {
597 req_p->scsi_done = done;
598 } else {
599 #ifdef ED_DBGP
600 printk( "atp870u_queuecommand: done can't be NULL\n");
601 #endif
602 req_p->result = 0;
603 done(req_p);
604 return 0;
605 }
606
607 /*
608 * Count new command
609 */
610 dev->quend[c]++;
611 if (dev->quend[c] >= qcnt) {
612 dev->quend[c] = 0;
613 }
614
615 /*
616 * Check queue state
617 */
618 if (dev->quhd[c] == dev->quend[c]) {
619 if (dev->quend[c] == 0) {
620 dev->quend[c] = qcnt;
621 }
622 #ifdef ED_DBGP
623 printk("atp870u_queuecommand : dev->quhd[c] == dev->quend[c]\n");
624 #endif
625 dev->quend[c]--;
626 req_p->result = 0x00020000;
627 done(req_p);
628 return 0;
629 }
630 dev->quereq[c][dev->quend[c]] = req_p;
631 #ifdef ED_DBGP
632 printk("dev->ioport[c] = %x atp_readb_io(dev, c, 0x1c) = %x dev->in_int[%d] = %d dev->in_snd[%d] = %d\n",dev->ioport[c],atp_readb_io(dev, c, 0x1c),c,dev->in_int[c],c,dev->in_snd[c]);
633 #endif
634 if ((atp_readb_io(dev, c, 0x1c) == 0) && (dev->in_int[c] == 0) && (dev->in_snd[c] == 0)) {
635 #ifdef ED_DBGP
636 printk("Call sent_s870(atp870u_queuecommand)\n");
637 #endif
638 send_s870(dev,c);
639 }
640 #ifdef ED_DBGP
641 printk("atp870u_queuecommand : exit\n");
642 #endif
643 return 0;
644 }
645
646 static DEF_SCSI_QCMD(atp870u_queuecommand)
647
648 /**
649 * send_s870 - send a command to the controller
650 * @host: host
651 *
652 * On entry there is work queued to be done. We move some of that work to the
653 * controller itself.
654 *
655 * Caller holds the host lock.
656 */
657 static void send_s870(struct atp_unit *dev,unsigned char c)
658 {
659 struct scsi_cmnd *workreq = NULL;
660 unsigned int i;//,k;
661 unsigned char j, target_id;
662 unsigned char *prd;
663 unsigned short int w;
664 unsigned long l, bttl = 0;
665 unsigned long sg_count;
666
667 if (dev->in_snd[c] != 0) {
668 #ifdef ED_DBGP
669 printk("cmnd in_snd\n");
670 #endif
671 return;
672 }
673 #ifdef ED_DBGP
674 printk("Sent_s870 enter\n");
675 #endif
676 dev->in_snd[c] = 1;
677 if ((dev->last_cmd[c] != 0xff) && ((dev->last_cmd[c] & 0x40) != 0)) {
678 dev->last_cmd[c] &= 0x0f;
679 workreq = dev->id[c][dev->last_cmd[c]].curr_req;
680 if (!workreq) {
681 dev->last_cmd[c] = 0xff;
682 if (dev->quhd[c] == dev->quend[c]) {
683 dev->in_snd[c] = 0;
684 return;
685 }
686 }
687 }
688 if (!workreq) {
689 if ((dev->last_cmd[c] != 0xff) && (dev->working[c] != 0)) {
690 dev->in_snd[c] = 0;
691 return;
692 }
693 dev->working[c]++;
694 j = dev->quhd[c];
695 dev->quhd[c]++;
696 if (dev->quhd[c] >= qcnt)
697 dev->quhd[c] = 0;
698 workreq = dev->quereq[c][dev->quhd[c]];
699 if (dev->id[c][scmd_id(workreq)].curr_req != NULL) {
700 dev->quhd[c] = j;
701 dev->working[c]--;
702 dev->in_snd[c] = 0;
703 return;
704 }
705 dev->id[c][scmd_id(workreq)].curr_req = workreq;
706 dev->last_cmd[c] = scmd_id(workreq);
707 }
708 if ((atp_readb_io(dev, c, 0x1f) & 0xb0) != 0 || atp_readb_io(dev, c, 0x1c) != 0) {
709 #ifdef ED_DBGP
710 printk("Abort to Send\n");
711 #endif
712 dev->last_cmd[c] |= 0x40;
713 dev->in_snd[c] = 0;
714 return;
715 }
716 #ifdef ED_DBGP
717 printk("OK to Send\n");
718 scmd_printk(KERN_DEBUG, workreq, "CDB");
719 for(i=0;i<workreq->cmd_len;i++) {
720 printk(" %x",workreq->cmnd[i]);
721 }
722 printk("\n");
723 #endif
724 l = scsi_bufflen(workreq);
725
726 if (dev->dev_id == ATP885_DEVID) {
727 j = atp_readb_base(dev, 0x29) & 0xfe;
728 atp_writeb_base(dev, 0x29, j);
729 dev->r1f[c][scmd_id(workreq)] = 0;
730 }
731
732 if (workreq->cmnd[0] == READ_CAPACITY) {
733 if (l > 8)
734 l = 8;
735 }
736 if (workreq->cmnd[0] == 0x00) {
737 l = 0;
738 }
739
740 j = 0;
741 target_id = scmd_id(workreq);
742
743 /*
744 * Wide ?
745 */
746 w = 1;
747 w = w << target_id;
748 if ((w & dev->wide_id[c]) != 0) {
749 j |= 0x01;
750 }
751 atp_writeb_io(dev, c, 0x1b, j);
752 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != j) {
753 atp_writeb_pci(dev, c, 0x1b, j);
754 #ifdef ED_DBGP
755 printk("send_s870 while loop 1\n");
756 #endif
757 }
758 /*
759 * Write the command
760 */
761
762 atp_writeb_io(dev, c, 0x00, workreq->cmd_len);
763 atp_writeb_io(dev, c, 0x01, 0x2c);
764 if (dev->dev_id == ATP885_DEVID)
765 atp_writeb_io(dev, c, 0x02, 0x7f);
766 else
767 atp_writeb_io(dev, c, 0x02, 0xcf);
768 for (i = 0; i < workreq->cmd_len; i++)
769 atp_writeb_io(dev, c, 0x03 + i, workreq->cmnd[i]);
770 atp_writeb_io(dev, c, 0x0f, workreq->device->lun);
771 /*
772 * Write the target
773 */
774 atp_writeb_io(dev, c, 0x11, dev->id[c][target_id].devsp);
775 #ifdef ED_DBGP
776 printk("dev->id[%d][%d].devsp = %2x\n",c,target_id,dev->id[c][target_id].devsp);
777 #endif
778
779 sg_count = scsi_dma_map(workreq);
780 /*
781 * Write transfer size
782 */
783 atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&l))[2]);
784 atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&l))[1]);
785 atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&l))[0]);
786 j = target_id;
787 dev->id[c][j].last_len = l;
788 dev->id[c][j].tran_len = 0;
789 #ifdef ED_DBGP
790 printk("dev->id[%2d][%2d].last_len = %d\n",c,j,dev->id[c][j].last_len);
791 #endif
792 /*
793 * Flip the wide bits
794 */
795 if ((j & 0x08) != 0) {
796 j = (j & 0x07) | 0x40;
797 }
798 /*
799 * Check transfer direction
800 */
801 if (workreq->sc_data_direction == DMA_TO_DEVICE)
802 atp_writeb_io(dev, c, 0x15, j | 0x20);
803 else
804 atp_writeb_io(dev, c, 0x15, j);
805 atp_writeb_io(dev, c, 0x16, atp_readb_io(dev, c, 0x16) | 0x80);
806 atp_writeb_io(dev, c, 0x16, 0x80);
807 dev->id[c][target_id].dirct = 0;
808 if (l == 0) {
809 if (atp_readb_io(dev, c, 0x1c) == 0) {
810 #ifdef ED_DBGP
811 printk("change SCSI_CMD_REG 0x08\n");
812 #endif
813 atp_writeb_io(dev, c, 0x18, 0x08);
814 } else
815 dev->last_cmd[c] |= 0x40;
816 dev->in_snd[c] = 0;
817 return;
818 }
819 prd = dev->id[c][target_id].prd_table;
820 dev->id[c][target_id].prd_pos = prd;
821
822 /*
823 * Now write the request list. Either as scatter/gather or as
824 * a linear chain.
825 */
826
827 if (l) {
828 struct scatterlist *sgpnt;
829 i = 0;
830 scsi_for_each_sg(workreq, sgpnt, sg_count, j) {
831 bttl = sg_dma_address(sgpnt);
832 l=sg_dma_len(sgpnt);
833 #ifdef ED_DBGP
834 printk("1. bttl %x, l %x\n",bttl, l);
835 #endif
836 while (l > 0x10000) {
837 (((u16 *) (prd))[i + 3]) = 0x0000;
838 (((u16 *) (prd))[i + 2]) = 0x0000;
839 (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl);
840 l -= 0x10000;
841 bttl += 0x10000;
842 i += 0x04;
843 }
844 (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl);
845 (((u16 *) (prd))[i + 2]) = cpu_to_le16(l);
846 (((u16 *) (prd))[i + 3]) = 0;
847 i += 0x04;
848 }
849 (((u16 *) (prd))[i - 1]) = cpu_to_le16(0x8000);
850 #ifdef ED_DBGP
851 printk("prd %4x %4x %4x %4x\n",(((unsigned short int *)prd)[0]),(((unsigned short int *)prd)[1]),(((unsigned short int *)prd)[2]),(((unsigned short int *)prd)[3]));
852 printk("2. bttl %x, l %x\n",bttl, l);
853 #endif
854 }
855 #ifdef ED_DBGP
856 printk("send_s870: prdaddr_2 0x%8x target_id %d\n", dev->id[c][target_id].prdaddr,target_id);
857 #endif
858 dev->id[c][target_id].prdaddr = dev->id[c][target_id].prd_bus;
859 atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr);
860 atp_writeb_pci(dev, c, 2, 0x06);
861 atp_writeb_pci(dev, c, 2, 0x00);
862 if (dev->dev_id == ATP885_DEVID) {
863 j = atp_readb_pci(dev, c, 1) & 0xf3;
864 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) ||
865 (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
866 j |= 0x0c;
867 }
868 atp_writeb_pci(dev, c, 1, j);
869 } else if ((dev->dev_id == ATP880_DEVID1) ||
870 (dev->dev_id == ATP880_DEVID2)) {
871 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a))
872 atp_writeb_base(dev, 0x3b, (atp_readb_base(dev, 0x3b) & 0x3f) | 0xc0);
873 else
874 atp_writeb_base(dev, 0x3b, atp_readb_base(dev, 0x3b) & 0x3f);
875 } else {
876 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a))
877 atp_writeb_io(dev, c, 0x3a, (atp_readb_io(dev, c, 0x3a) & 0xf3) | 0x08);
878 else
879 atp_writeb_io(dev, c, 0x3a, atp_readb_io(dev, c, 0x3a) & 0xf3);
880 }
881
882 if(workreq->sc_data_direction == DMA_TO_DEVICE) {
883 dev->id[c][target_id].dirct = 0x20;
884 if (atp_readb_io(dev, c, 0x1c) == 0) {
885 atp_writeb_io(dev, c, 0x18, 0x08);
886 atp_writeb_pci(dev, c, 0, 0x01);
887 #ifdef ED_DBGP
888 printk( "start DMA(to target)\n");
889 #endif
890 } else {
891 dev->last_cmd[c] |= 0x40;
892 }
893 dev->in_snd[c] = 0;
894 return;
895 }
896 if (atp_readb_io(dev, c, 0x1c) == 0) {
897 atp_writeb_io(dev, c, 0x18, 0x08);
898 atp_writeb_pci(dev, c, 0, 0x09);
899 #ifdef ED_DBGP
900 printk( "start DMA(to host)\n");
901 #endif
902 } else {
903 dev->last_cmd[c] |= 0x40;
904 }
905 dev->in_snd[c] = 0;
906 return;
907
908 }
909
910 static unsigned char fun_scam(struct atp_unit *dev, unsigned short int *val)
911 {
912 unsigned short int i, k;
913 unsigned char j;
914
915 atp_writew_io(dev, 0, 0x1c, *val);
916 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */
917 k = atp_readw_io(dev, 0, 0x1c);
918 j = (unsigned char) (k >> 8);
919 if ((k & 0x8000) != 0) /* DB7 all release? */
920 i = 0;
921 }
922 *val |= 0x4000; /* assert DB6 */
923 atp_writew_io(dev, 0, 0x1c, *val);
924 *val &= 0xdfff; /* assert DB5 */
925 atp_writew_io(dev, 0, 0x1c, *val);
926 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */
927 if ((atp_readw_io(dev, 0, 0x1c) & 0x2000) != 0) /* DB5 all release? */
928 i = 0;
929 }
930 *val |= 0x8000; /* no DB4-0, assert DB7 */
931 *val &= 0xe0ff;
932 atp_writew_io(dev, 0, 0x1c, *val);
933 *val &= 0xbfff; /* release DB6 */
934 atp_writew_io(dev, 0, 0x1c, *val);
935 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */
936 if ((atp_readw_io(dev, 0, 0x1c) & 0x4000) != 0) /* DB6 all release? */
937 i = 0;
938 }
939
940 return j;
941 }
942
943 static void tscam(struct Scsi_Host *host)
944 {
945
946 unsigned char i, j, k;
947 unsigned long n;
948 unsigned short int m, assignid_map, val;
949 unsigned char mbuf[33], quintet[2];
950 struct atp_unit *dev = (struct atp_unit *)&host->hostdata;
951 static unsigned char g2q_tab[8] = {
952 0x38, 0x31, 0x32, 0x2b, 0x34, 0x2d, 0x2e, 0x27
953 };
954
955 /* I can't believe we need this before we've even done anything. Remove it
956 * and see if anyone bitches.
957 for (i = 0; i < 0x10; i++) {
958 udelay(0xffff);
959 }
960 */
961
962 atp_writeb_io(dev, 0, 1, 0x08);
963 atp_writeb_io(dev, 0, 2, 0x7f);
964 atp_writeb_io(dev, 0, 0x11, 0x20);
965
966 if ((dev->scam_on & 0x40) == 0) {
967 return;
968 }
969 m = 1;
970 m <<= dev->host_id[0];
971 j = 16;
972 if (dev->chip_ver < 4) {
973 m |= 0xff00;
974 j = 8;
975 }
976 assignid_map = m;
977 atp_writeb_io(dev, 0, 0x02, 0x02); /* 2*2=4ms,3EH 2/32*3E=3.9ms */
978 atp_writeb_io(dev, 0, 0x03, 0);
979 atp_writeb_io(dev, 0, 0x04, 0);
980 atp_writeb_io(dev, 0, 0x05, 0);
981 atp_writeb_io(dev, 0, 0x06, 0);
982 atp_writeb_io(dev, 0, 0x07, 0);
983 atp_writeb_io(dev, 0, 0x08, 0);
984
985 for (i = 0; i < j; i++) {
986 m = 1;
987 m = m << i;
988 if ((m & assignid_map) != 0) {
989 continue;
990 }
991 atp_writeb_io(dev, 0, 0x0f, 0);
992 atp_writeb_io(dev, 0, 0x12, 0);
993 atp_writeb_io(dev, 0, 0x13, 0);
994 atp_writeb_io(dev, 0, 0x14, 0);
995 if (i > 7) {
996 k = (i & 0x07) | 0x40;
997 } else {
998 k = i;
999 }
1000 atp_writeb_io(dev, 0, 0x15, k);
1001 if (dev->chip_ver == 4)
1002 atp_writeb_io(dev, 0, 0x1b, 0x01);
1003 else
1004 atp_writeb_io(dev, 0, 0x1b, 0x00);
1005 do {
1006 atp_writeb_io(dev, 0, 0x18, 0x09);
1007
1008 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1009 cpu_relax();
1010 k = atp_readb_io(dev, 0, 0x17);
1011 if ((k == 0x85) || (k == 0x42))
1012 break;
1013 if (k != 0x16)
1014 atp_writeb_io(dev, 0, 0x10, 0x41);
1015 } while (k != 0x16);
1016 if ((k == 0x85) || (k == 0x42))
1017 continue;
1018 assignid_map |= m;
1019
1020 }
1021 atp_writeb_io(dev, 0, 0x02, 0x7f);
1022 atp_writeb_io(dev, 0, 0x1b, 0x02);
1023
1024 outb(0, 0x80);
1025
1026 val = 0x0080; /* bsy */
1027 atp_writew_io(dev, 0, 0x1c, val);
1028 val |= 0x0040; /* sel */
1029 atp_writew_io(dev, 0, 0x1c, val);
1030 val |= 0x0004; /* msg */
1031 atp_writew_io(dev, 0, 0x1c, val);
1032 inb(0x80); /* 2 deskew delay(45ns*2=90ns) */
1033 val &= 0x007f; /* no bsy */
1034 atp_writew_io(dev, 0, 0x1c, val);
1035 mdelay(128);
1036 val &= 0x00fb; /* after 1ms no msg */
1037 atp_writew_io(dev, 0, 0x1c, val);
1038 while ((atp_readb_io(dev, 0, 0x1c) & 0x04) != 0)
1039 ;
1040 outb(1, 0x80);
1041 udelay(100);
1042 for (n = 0; n < 0x30000; n++)
1043 if ((atp_readb_io(dev, 0, 0x1c) & 0x80) != 0) /* bsy ? */
1044 break;
1045 if (n < 0x30000)
1046 for (n = 0; n < 0x30000; n++)
1047 if ((atp_readb_io(dev, 0, 0x1c) & 0x81) == 0x0081) {
1048 inb(0x80);
1049 val |= 0x8003; /* io,cd,db7 */
1050 atp_writew_io(dev, 0, 0x1c, val);
1051 inb(0x80);
1052 val &= 0x00bf; /* no sel */
1053 atp_writew_io(dev, 0, 0x1c, val);
1054 outb(2, 0x80);
1055 break;
1056 }
1057 while (1) {
1058 /*
1059 * The funny division into multiple delays is to accomodate
1060 * arches like ARM where udelay() multiplies its argument by
1061 * a large number to initialize a loop counter. To avoid
1062 * overflow, the maximum supported udelay is 2000 microseconds.
1063 *
1064 * XXX it would be more polite to find a way to use msleep()
1065 */
1066 mdelay(2);
1067 udelay(48);
1068 if ((atp_readb_io(dev, 0, 0x1c) & 0x80) == 0x00) { /* bsy ? */
1069 atp_writew_io(dev, 0, 0x1c, 0);
1070 atp_writeb_io(dev, 0, 0x1b, 0);
1071 atp_writeb_io(dev, 0, 0x15, 0);
1072 atp_writeb_io(dev, 0, 0x18, 0x09);
1073 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0)
1074 cpu_relax();
1075 atp_readb_io(dev, 0, 0x17);
1076 return;
1077 }
1078 val &= 0x00ff; /* synchronization */
1079 val |= 0x3f00;
1080 fun_scam(dev, &val);
1081 outb(3, 0x80);
1082 val &= 0x00ff; /* isolation */
1083 val |= 0x2000;
1084 fun_scam(dev, &val);
1085 outb(4, 0x80);
1086 i = 8;
1087 j = 0;
1088
1089 while (1) {
1090 if ((atp_readw_io(dev, 0, 0x1c) & 0x2000) == 0)
1091 continue;
1092 outb(5, 0x80);
1093 val &= 0x00ff; /* get ID_STRING */
1094 val |= 0x2000;
1095 k = fun_scam(dev, &val);
1096 if ((k & 0x03) == 0)
1097 break;
1098 mbuf[j] <<= 0x01;
1099 mbuf[j] &= 0xfe;
1100 if ((k & 0x02) != 0)
1101 mbuf[j] |= 0x01;
1102 i--;
1103 if (i > 0)
1104 continue;
1105 j++;
1106 i = 8;
1107 }
1108
1109 /* isolation complete.. */
1110 /* mbuf[32]=0;
1111 printk(" \n%x %x %x %s\n ",assignid_map,mbuf[0],mbuf[1],&mbuf[2]); */
1112 i = 15;
1113 j = mbuf[0];
1114 if ((j & 0x20) != 0) { /* bit5=1:ID up to 7 */
1115 i = 7;
1116 }
1117 if ((j & 0x06) != 0) { /* IDvalid? */
1118 k = mbuf[1];
1119 while (1) {
1120 m = 1;
1121 m <<= k;
1122 if ((m & assignid_map) == 0)
1123 break;
1124 if (k > 0)
1125 k--;
1126 else
1127 break;
1128 }
1129 }
1130 if ((m & assignid_map) != 0) { /* srch from max acceptable ID# */
1131 k = i; /* max acceptable ID# */
1132 while (1) {
1133 m = 1;
1134 m <<= k;
1135 if ((m & assignid_map) == 0)
1136 break;
1137 if (k > 0)
1138 k--;
1139 else
1140 break;
1141 }
1142 }
1143 /* k=binID#, */
1144 assignid_map |= m;
1145 if (k < 8) {
1146 quintet[0] = 0x38; /* 1st dft ID<8 */
1147 } else {
1148 quintet[0] = 0x31; /* 1st ID>=8 */
1149 }
1150 k &= 0x07;
1151 quintet[1] = g2q_tab[k];
1152
1153 val &= 0x00ff; /* AssignID 1stQuintet,AH=001xxxxx */
1154 m = quintet[0] << 8;
1155 val |= m;
1156 fun_scam(dev, &val);
1157 val &= 0x00ff; /* AssignID 2ndQuintet,AH=001xxxxx */
1158 m = quintet[1] << 8;
1159 val |= m;
1160 fun_scam(dev, &val);
1161
1162 }
1163 }
1164
1165 static void is870(struct atp_unit *dev, unsigned char c)
1166 {
1167 unsigned char i, j, k, rmb, n;
1168 unsigned short int m;
1169 static unsigned char mbuf[512];
1170 static unsigned char satn[9] = { 0, 0, 0, 0, 0, 0, 0, 6, 6 };
1171 static unsigned char inqd[9] = { 0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6 };
1172 static unsigned char synn[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
1173 static unsigned char synu[6] = { 0x80, 1, 3, 1, 0x0c, 0x0e };
1174 static unsigned char synw[6] = { 0x80, 1, 3, 1, 0x0c, 0x07 };
1175 static unsigned char wide[6] = { 0x80, 1, 2, 3, 1, 0 };
1176
1177 atp_writeb_io(dev, c, 0x3a, atp_readb_io(dev, c, 0x3a) | 0x10);
1178
1179 for (i = 0; i < 16; i++) {
1180 if ((dev->chip_ver != 4) && (i > 7)) {
1181 break;
1182 }
1183 m = 1;
1184 m = m << i;
1185 if ((m & dev->active_id[c]) != 0) {
1186 continue;
1187 }
1188 if (i == dev->host_id[c]) {
1189 printk(KERN_INFO " ID: %2d Host Adapter\n", dev->host_id[c]);
1190 continue;
1191 }
1192 if (dev->chip_ver == 4) {
1193 atp_writeb_io(dev, c, 0x1b, 0x01);
1194 } else {
1195 atp_writeb_io(dev, c, 0x1b, 0x00);
1196 }
1197 atp_writeb_io(dev, c, 1, 0x08);
1198 atp_writeb_io(dev, c, 2, 0x7f);
1199 atp_writeb_io(dev, c, 3, satn[0]);
1200 atp_writeb_io(dev, c, 4, satn[1]);
1201 atp_writeb_io(dev, c, 5, satn[2]);
1202 atp_writeb_io(dev, c, 6, satn[3]);
1203 atp_writeb_io(dev, c, 7, satn[4]);
1204 atp_writeb_io(dev, c, 8, satn[5]);
1205 atp_writeb_io(dev, c, 0x0f, 0);
1206 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
1207 atp_writeb_io(dev, c, 0x12, 0);
1208 atp_writeb_io(dev, c, 0x13, satn[6]);
1209 atp_writeb_io(dev, c, 0x14, satn[7]);
1210 j = i;
1211 if ((j & 0x08) != 0) {
1212 j = (j & 0x07) | 0x40;
1213 }
1214 atp_writeb_io(dev, c, 0x15, j);
1215 atp_writeb_io(dev, c, 0x18, satn[8]);
1216
1217 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
1218 cpu_relax();
1219
1220 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
1221 continue;
1222
1223 while (atp_readb_io(dev, c, 0x17) != 0x8e)
1224 cpu_relax();
1225
1226 dev->active_id[c] |= m;
1227
1228 atp_writeb_io(dev, c, 0x10, 0x30);
1229 atp_writeb_io(dev, c, 0x04, 0x00);
1230
1231 phase_cmd:
1232 atp_writeb_io(dev, c, 0x18, 0x08);
1233
1234 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
1235 cpu_relax();
1236
1237 j = atp_readb_io(dev, c, 0x17);
1238 if (j != 0x16) {
1239 atp_writeb_io(dev, c, 0x10, 0x41);
1240 goto phase_cmd;
1241 }
1242 sel_ok:
1243 atp_writeb_io(dev, c, 3, inqd[0]);
1244 atp_writeb_io(dev, c, 4, inqd[1]);
1245 atp_writeb_io(dev, c, 5, inqd[2]);
1246 atp_writeb_io(dev, c, 6, inqd[3]);
1247 atp_writeb_io(dev, c, 7, inqd[4]);
1248 atp_writeb_io(dev, c, 8, inqd[5]);
1249 atp_writeb_io(dev, c, 0x0f, 0);
1250 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
1251 atp_writeb_io(dev, c, 0x12, 0);
1252 atp_writeb_io(dev, c, 0x13, inqd[6]);
1253 atp_writeb_io(dev, c, 0x14, inqd[7]);
1254 atp_writeb_io(dev, c, 0x18, inqd[8]);
1255
1256 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
1257 cpu_relax();
1258
1259 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
1260 continue;
1261
1262 while (atp_readb_io(dev, c, 0x17) != 0x8e)
1263 cpu_relax();
1264
1265 if (dev->chip_ver == 4)
1266 atp_writeb_io(dev, c, 0x1b, 0x00);
1267
1268 atp_writeb_io(dev, c, 0x18, 0x08);
1269 j = 0;
1270 rd_inq_data:
1271 k = atp_readb_io(dev, c, 0x1f);
1272 if ((k & 0x01) != 0) {
1273 mbuf[j++] = atp_readb_io(dev, c, 0x19);
1274 goto rd_inq_data;
1275 }
1276 if ((k & 0x80) == 0) {
1277 goto rd_inq_data;
1278 }
1279 j = atp_readb_io(dev, c, 0x17);
1280 if (j == 0x16) {
1281 goto inq_ok;
1282 }
1283 atp_writeb_io(dev, c, 0x10, 0x46);
1284 atp_writeb_io(dev, c, 0x12, 0);
1285 atp_writeb_io(dev, c, 0x13, 0);
1286 atp_writeb_io(dev, c, 0x14, 0);
1287 atp_writeb_io(dev, c, 0x18, 0x08);
1288
1289 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
1290 cpu_relax();
1291
1292 if (atp_readb_io(dev, c, 0x17) != 0x16)
1293 goto sel_ok;
1294
1295 inq_ok:
1296 mbuf[36] = 0;
1297 printk(KERN_INFO " ID: %2d %s\n", i, &mbuf[8]);
1298 dev->id[c][i].devtype = mbuf[0];
1299 rmb = mbuf[1];
1300 n = mbuf[7];
1301 if (dev->chip_ver != 4) {
1302 goto not_wide;
1303 }
1304 if ((mbuf[7] & 0x60) == 0) {
1305 goto not_wide;
1306 }
1307 if ((dev->global_map[c] & 0x20) == 0) {
1308 goto not_wide;
1309 }
1310 atp_writeb_io(dev, c, 0x1b, 0x01);
1311 atp_writeb_io(dev, c, 3, satn[0]);
1312 atp_writeb_io(dev, c, 4, satn[1]);
1313 atp_writeb_io(dev, c, 5, satn[2]);
1314 atp_writeb_io(dev, c, 6, satn[3]);
1315 atp_writeb_io(dev, c, 7, satn[4]);
1316 atp_writeb_io(dev, c, 8, satn[5]);
1317 atp_writeb_io(dev, c, 0x0f, 0);
1318 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
1319 atp_writeb_io(dev, c, 0x12, 0);
1320 atp_writeb_io(dev, c, 0x13, satn[6]);
1321 atp_writeb_io(dev, c, 0x14, satn[7]);
1322 atp_writeb_io(dev, c, 0x18, satn[8]);
1323
1324 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
1325 cpu_relax();
1326
1327 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
1328 continue;
1329
1330 while (atp_readb_io(dev, c, 0x17) != 0x8e)
1331 cpu_relax();
1332
1333 try_wide:
1334 j = 0;
1335 atp_writeb_io(dev, c, 0x14, 0x05);
1336 atp_writeb_io(dev, c, 0x18, 0x20);
1337
1338 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
1339 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0)
1340 atp_writeb_io(dev, c, 0x19, wide[j++]);
1341 }
1342
1343 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00)
1344 cpu_relax();
1345
1346 j = atp_readb_io(dev, c, 0x17) & 0x0f;
1347 if (j == 0x0f) {
1348 goto widep_in;
1349 }
1350 if (j == 0x0a) {
1351 goto widep_cmd;
1352 }
1353 if (j == 0x0e) {
1354 goto try_wide;
1355 }
1356 continue;
1357 widep_out:
1358 atp_writeb_io(dev, c, 0x18, 0x20);
1359 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
1360 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0)
1361 atp_writeb_io(dev, c, 0x19, 0);
1362 }
1363 j = atp_readb_io(dev, c, 0x17) & 0x0f;
1364 if (j == 0x0f) {
1365 goto widep_in;
1366 }
1367 if (j == 0x0a) {
1368 goto widep_cmd;
1369 }
1370 if (j == 0x0e) {
1371 goto widep_out;
1372 }
1373 continue;
1374 widep_in:
1375 atp_writeb_io(dev, c, 0x14, 0xff);
1376 atp_writeb_io(dev, c, 0x18, 0x20);
1377 k = 0;
1378 widep_in1:
1379 j = atp_readb_io(dev, c, 0x1f);
1380 if ((j & 0x01) != 0) {
1381 mbuf[k++] = atp_readb_io(dev, c, 0x19);
1382 goto widep_in1;
1383 }
1384 if ((j & 0x80) == 0x00) {
1385 goto widep_in1;
1386 }
1387 j = atp_readb_io(dev, c, 0x17) & 0x0f;
1388 if (j == 0x0f) {
1389 goto widep_in;
1390 }
1391 if (j == 0x0a) {
1392 goto widep_cmd;
1393 }
1394 if (j == 0x0e) {
1395 goto widep_out;
1396 }
1397 continue;
1398 widep_cmd:
1399 atp_writeb_io(dev, c, 0x10, 0x30);
1400 atp_writeb_io(dev, c, 0x14, 0x00);
1401 atp_writeb_io(dev, c, 0x18, 0x08);
1402
1403 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
1404 cpu_relax();
1405
1406 j = atp_readb_io(dev, c, 0x17);
1407 if (j != 0x16) {
1408 if (j == 0x4e) {
1409 goto widep_out;
1410 }
1411 continue;
1412 }
1413 if (mbuf[0] != 0x01) {
1414 goto not_wide;
1415 }
1416 if (mbuf[1] != 0x02) {
1417 goto not_wide;
1418 }
1419 if (mbuf[2] != 0x03) {
1420 goto not_wide;
1421 }
1422 if (mbuf[3] != 0x01) {
1423 goto not_wide;
1424 }
1425 m = 1;
1426 m = m << i;
1427 dev->wide_id[c] |= m;
1428 not_wide:
1429 if ((dev->id[c][i].devtype == 0x00) || (dev->id[c][i].devtype == 0x07) || ((dev->id[c][i].devtype == 0x05) && ((n & 0x10) != 0))) {
1430 goto set_sync;
1431 }
1432 continue;
1433 set_sync:
1434 j = 0;
1435 if ((m & dev->wide_id[c]) != 0) {
1436 j |= 0x01;
1437 }
1438 atp_writeb_io(dev, c, 0x1b, j);
1439 atp_writeb_io(dev, c, 3, satn[0]);
1440 atp_writeb_io(dev, c, 4, satn[1]);
1441 atp_writeb_io(dev, c, 5, satn[2]);
1442 atp_writeb_io(dev, c, 6, satn[3]);
1443 atp_writeb_io(dev, c, 7, satn[4]);
1444 atp_writeb_io(dev, c, 8, satn[5]);
1445 atp_writeb_io(dev, c, 0x0f, 0);
1446 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
1447 atp_writeb_io(dev, c, 0x12, 0);
1448 atp_writeb_io(dev, c, 0x13, satn[6]);
1449 atp_writeb_io(dev, c, 0x14, satn[7]);
1450 atp_writeb_io(dev, c, 0x18, satn[8]);
1451
1452 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
1453 cpu_relax();
1454
1455 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
1456 continue;
1457
1458 while (atp_readb_io(dev, c, 0x17) != 0x8e)
1459 cpu_relax();
1460
1461 try_sync:
1462 j = 0;
1463 atp_writeb_io(dev, c, 0x14, 0x06);
1464 atp_writeb_io(dev, c, 0x18, 0x20);
1465
1466 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
1467 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) {
1468 if ((m & dev->wide_id[c]) != 0) {
1469 atp_writeb_io(dev, c, 0x19, synw[j++]);
1470 } else {
1471 if ((m & dev->ultra_map[c]) != 0) {
1472 atp_writeb_io(dev, c, 0x19, synu[j++]);
1473 } else {
1474 atp_writeb_io(dev, c, 0x19, synn[j++]);
1475 }
1476 }
1477 }
1478 }
1479
1480 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00)
1481 cpu_relax();
1482
1483 j = atp_readb_io(dev, c, 0x17) & 0x0f;
1484 if (j == 0x0f) {
1485 goto phase_ins;
1486 }
1487 if (j == 0x0a) {
1488 goto phase_cmds;
1489 }
1490 if (j == 0x0e) {
1491 goto try_sync;
1492 }
1493 continue;
1494 phase_outs:
1495 atp_writeb_io(dev, c, 0x18, 0x20);
1496 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) {
1497 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0x00)
1498 atp_writeb_io(dev, c, 0x19, 0x00);
1499 }
1500 j = atp_readb_io(dev, c, 0x17);
1501 if (j == 0x85) {
1502 goto tar_dcons;
1503 }
1504 j &= 0x0f;
1505 if (j == 0x0f) {
1506 goto phase_ins;
1507 }
1508 if (j == 0x0a) {
1509 goto phase_cmds;
1510 }
1511 if (j == 0x0e) {
1512 goto phase_outs;
1513 }
1514 continue;
1515 phase_ins:
1516 atp_writeb_io(dev, c, 0x14, 0xff);
1517 atp_writeb_io(dev, c, 0x18, 0x20);
1518 k = 0;
1519 phase_ins1:
1520 j = atp_readb_io(dev, c, 0x1f);
1521 if ((j & 0x01) != 0x00) {
1522 mbuf[k++] = atp_readb_io(dev, c, 0x19);
1523 goto phase_ins1;
1524 }
1525 if ((j & 0x80) == 0x00) {
1526 goto phase_ins1;
1527 }
1528
1529 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00)
1530 cpu_relax();
1531
1532 j = atp_readb_io(dev, c, 0x17);
1533 if (j == 0x85) {
1534 goto tar_dcons;
1535 }
1536 j &= 0x0f;
1537 if (j == 0x0f) {
1538 goto phase_ins;
1539 }
1540 if (j == 0x0a) {
1541 goto phase_cmds;
1542 }
1543 if (j == 0x0e) {
1544 goto phase_outs;
1545 }
1546 continue;
1547 phase_cmds:
1548 atp_writeb_io(dev, c, 0x10, 0x30);
1549 tar_dcons:
1550 atp_writeb_io(dev, c, 0x14, 0x00);
1551 atp_writeb_io(dev, c, 0x18, 0x08);
1552
1553 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
1554 cpu_relax();
1555
1556 j = atp_readb_io(dev, c, 0x17);
1557 if (j != 0x16) {
1558 continue;
1559 }
1560 if (mbuf[0] != 0x01) {
1561 continue;
1562 }
1563 if (mbuf[1] != 0x03) {
1564 continue;
1565 }
1566 if (mbuf[4] == 0x00) {
1567 continue;
1568 }
1569 if (mbuf[3] > 0x64) {
1570 continue;
1571 }
1572 if (mbuf[4] > 0x0c) {
1573 mbuf[4] = 0x0c;
1574 }
1575 dev->id[c][i].devsp = mbuf[4];
1576 if ((mbuf[3] < 0x0d) && (rmb == 0)) {
1577 j = 0xa0;
1578 goto set_syn_ok;
1579 }
1580 if (mbuf[3] < 0x1a) {
1581 j = 0x20;
1582 goto set_syn_ok;
1583 }
1584 if (mbuf[3] < 0x33) {
1585 j = 0x40;
1586 goto set_syn_ok;
1587 }
1588 if (mbuf[3] < 0x4c) {
1589 j = 0x50;
1590 goto set_syn_ok;
1591 }
1592 j = 0x60;
1593 set_syn_ok:
1594 dev->id[c][i].devsp = (dev->id[c][i].devsp & 0x0f) | j;
1595 }
1596 atp_writeb_io(dev, c, 0x3a, atp_readb_io(dev, c, 0x3a) & 0xef);
1597 }
1598
1599 static void is880(struct atp_unit *dev, unsigned char c)
1600 {
1601 unsigned char i, j, k, rmb, n, lvdmode;
1602 unsigned short int m;
1603 static unsigned char mbuf[512];
1604 static unsigned char satn[9] = { 0, 0, 0, 0, 0, 0, 0, 6, 6 };
1605 static unsigned char inqd[9] = { 0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6 };
1606 static unsigned char synn[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
1607 unsigned char synu[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e };
1608 static unsigned char synw[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
1609 unsigned char synuw[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e };
1610 static unsigned char wide[6] = { 0x80, 1, 2, 3, 1, 0 };
1611 static unsigned char u3[9] = { 0x80, 1, 6, 4, 0x09, 00, 0x0e, 0x01, 0x02 };
1612
1613 lvdmode = atp_readb_base(dev, 0x3f) & 0x40;
1614
1615 for (i = 0; i < 16; i++) {
1616 m = 1;
1617 m = m << i;
1618 if ((m & dev->active_id[c]) != 0) {
1619 continue;
1620 }
1621 if (i == dev->host_id[c]) {
1622 printk(KERN_INFO " ID: %2d Host Adapter\n", dev->host_id[c]);
1623 continue;
1624 }
1625 atp_writeb_io(dev, c, 0x1b, 0x01);
1626 atp_writeb_io(dev, c, 1, 0x08);
1627 atp_writeb_io(dev, c, 2, 0x7f);
1628 atp_writeb_io(dev, c, 3, satn[0]);
1629 atp_writeb_io(dev, c, 4, satn[1]);
1630 atp_writeb_io(dev, c, 5, satn[2]);
1631 atp_writeb_io(dev, c, 6, satn[3]);
1632 atp_writeb_io(dev, c, 7, satn[4]);
1633 atp_writeb_io(dev, c, 8, satn[5]);
1634 atp_writeb_io(dev, c, 0x0f, 0);
1635 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
1636 atp_writeb_io(dev, c, 0x12, 0);
1637 atp_writeb_io(dev, c, 0x13, satn[6]);
1638 atp_writeb_io(dev, c, 0x14, satn[7]);
1639 j = i;
1640 if ((j & 0x08) != 0) {
1641 j = (j & 0x07) | 0x40;
1642 }
1643 atp_writeb_io(dev, c, 0x15, j);
1644 atp_writeb_io(dev, c, 0x18, satn[8]);
1645
1646 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
1647 cpu_relax();
1648
1649 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
1650 continue;
1651
1652 while (atp_readb_io(dev, c, 0x17) != 0x8e)
1653 cpu_relax();
1654
1655 dev->active_id[c] |= m;
1656
1657 atp_writeb_io(dev, c, 0x10, 0x30);
1658 atp_writeb_io(dev, c, 0x14, 0x00);
1659
1660 phase_cmd:
1661 atp_writeb_io(dev, c, 0x18, 0x08);
1662
1663 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
1664 cpu_relax();
1665
1666 j = atp_readb_io(dev, c, 0x17);
1667 if (j != 0x16) {
1668 atp_writeb_io(dev, c, 0x10, 0x41);
1669 goto phase_cmd;
1670 }
1671 sel_ok:
1672 atp_writeb_io(dev, c, 3, inqd[0]);
1673 atp_writeb_io(dev, c, 4, inqd[1]);
1674 atp_writeb_io(dev, c, 5, inqd[2]);
1675 atp_writeb_io(dev, c, 6, inqd[3]);
1676 atp_writeb_io(dev, c, 7, inqd[4]);
1677 atp_writeb_io(dev, c, 8, inqd[5]);
1678 atp_writeb_io(dev, c, 0x0f, 0);
1679 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
1680 atp_writeb_io(dev, c, 0x12, 0);
1681 atp_writeb_io(dev, c, 0x13, inqd[6]);
1682 atp_writeb_io(dev, c, 0x14, inqd[7]);
1683 atp_writeb_io(dev, c, 0x18, inqd[8]);
1684
1685 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
1686 cpu_relax();
1687
1688 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
1689 continue;
1690
1691 while (atp_readb_io(dev, c, 0x17) != 0x8e)
1692 cpu_relax();
1693
1694 atp_writeb_io(dev, c, 0x1b, 0x00);
1695 atp_writeb_io(dev, c, 0x18, 0x08);
1696 j = 0;
1697 rd_inq_data:
1698 k = atp_readb_io(dev, c, 0x1f);
1699 if ((k & 0x01) != 0) {
1700 mbuf[j++] = atp_readb_io(dev, c, 0x19);
1701 goto rd_inq_data;
1702 }
1703 if ((k & 0x80) == 0) {
1704 goto rd_inq_data;
1705 }
1706 j = atp_readb_io(dev, c, 0x17);
1707 if (j == 0x16) {
1708 goto inq_ok;
1709 }
1710 atp_writeb_io(dev, c, 0x10, 0x46);
1711 atp_writeb_io(dev, c, 0x12, 0);
1712 atp_writeb_io(dev, c, 0x13, 0);
1713 atp_writeb_io(dev, c, 0x14, 0);
1714 atp_writeb_io(dev, c, 0x18, 0x08);
1715
1716 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
1717 cpu_relax();
1718
1719 if (atp_readb_io(dev, c, 0x17) != 0x16)
1720 goto sel_ok;
1721
1722 inq_ok:
1723 mbuf[36] = 0;
1724 printk(KERN_INFO " ID: %2d %s\n", i, &mbuf[8]);
1725 dev->id[c][i].devtype = mbuf[0];
1726 rmb = mbuf[1];
1727 n = mbuf[7];
1728 if ((mbuf[7] & 0x60) == 0) {
1729 goto not_wide;
1730 }
1731 if ((i < 8) && ((dev->global_map[c] & 0x20) == 0)) {
1732 goto not_wide;
1733 }
1734 if (lvdmode == 0) {
1735 goto chg_wide;
1736 }
1737 if (dev->sp[c][i] != 0x04) // force u2
1738 {
1739 goto chg_wide;
1740 }
1741
1742 atp_writeb_io(dev, c, 0x1b, 0x01);
1743 atp_writeb_io(dev, c, 3, satn[0]);
1744 atp_writeb_io(dev, c, 4, satn[1]);
1745 atp_writeb_io(dev, c, 5, satn[2]);
1746 atp_writeb_io(dev, c, 6, satn[3]);
1747 atp_writeb_io(dev, c, 7, satn[4]);
1748 atp_writeb_io(dev, c, 8, satn[5]);
1749 atp_writeb_io(dev, c, 0x0f, 0);
1750 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
1751 atp_writeb_io(dev, c, 0x12, 0);
1752 atp_writeb_io(dev, c, 0x13, satn[6]);
1753 atp_writeb_io(dev, c, 0x14, satn[7]);
1754 atp_writeb_io(dev, c, 0x18, satn[8]);
1755
1756 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
1757 cpu_relax();
1758
1759 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
1760 continue;
1761
1762 while (atp_readb_io(dev, c, 0x17) != 0x8e)
1763 cpu_relax();
1764
1765 try_u3:
1766 j = 0;
1767 atp_writeb_io(dev, c, 0x14, 0x09);
1768 atp_writeb_io(dev, c, 0x18, 0x20);
1769
1770 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
1771 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0)
1772 atp_writeb_io(dev, c, 0x19, u3[j++]);
1773 }
1774
1775 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00)
1776 cpu_relax();
1777
1778 j = atp_readb_io(dev, c, 0x17) & 0x0f;
1779 if (j == 0x0f) {
1780 goto u3p_in;
1781 }
1782 if (j == 0x0a) {
1783 goto u3p_cmd;
1784 }
1785 if (j == 0x0e) {
1786 goto try_u3;
1787 }
1788 continue;
1789 u3p_out:
1790 atp_writeb_io(dev, c, 0x18, 0x20);
1791 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
1792 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0)
1793 atp_writeb_io(dev, c, 0x19, 0);
1794 }
1795 j = atp_readb_io(dev, c, 0x17) & 0x0f;
1796 if (j == 0x0f) {
1797 goto u3p_in;
1798 }
1799 if (j == 0x0a) {
1800 goto u3p_cmd;
1801 }
1802 if (j == 0x0e) {
1803 goto u3p_out;
1804 }
1805 continue;
1806 u3p_in:
1807 atp_writeb_io(dev, c, 0x14, 0x09);
1808 atp_writeb_io(dev, c, 0x18, 0x20);
1809 k = 0;
1810 u3p_in1:
1811 j = atp_readb_io(dev, c, 0x1f);
1812 if ((j & 0x01) != 0) {
1813 mbuf[k++] = atp_readb_io(dev, c, 0x19);
1814 goto u3p_in1;
1815 }
1816 if ((j & 0x80) == 0x00) {
1817 goto u3p_in1;
1818 }
1819 j = atp_readb_io(dev, c, 0x17) & 0x0f;
1820 if (j == 0x0f) {
1821 goto u3p_in;
1822 }
1823 if (j == 0x0a) {
1824 goto u3p_cmd;
1825 }
1826 if (j == 0x0e) {
1827 goto u3p_out;
1828 }
1829 continue;
1830 u3p_cmd:
1831 atp_writeb_io(dev, c, 0x10, 0x30);
1832 atp_writeb_io(dev, c, 0x14, 0x00);
1833 atp_writeb_io(dev, c, 0x18, 0x08);
1834
1835 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
1836 cpu_relax();
1837
1838 j = atp_readb_io(dev, c, 0x17);
1839 if (j != 0x16) {
1840 if (j == 0x4e) {
1841 goto u3p_out;
1842 }
1843 continue;
1844 }
1845 if (mbuf[0] != 0x01) {
1846 goto chg_wide;
1847 }
1848 if (mbuf[1] != 0x06) {
1849 goto chg_wide;
1850 }
1851 if (mbuf[2] != 0x04) {
1852 goto chg_wide;
1853 }
1854 if (mbuf[3] == 0x09) {
1855 m = 1;
1856 m = m << i;
1857 dev->wide_id[c] |= m;
1858 dev->id[c][i].devsp = 0xce;
1859 continue;
1860 }
1861 chg_wide:
1862 atp_writeb_io(dev, c, 0x1b, 0x01);
1863 atp_writeb_io(dev, c, 3, satn[0]);
1864 atp_writeb_io(dev, c, 4, satn[1]);
1865 atp_writeb_io(dev, c, 5, satn[2]);
1866 atp_writeb_io(dev, c, 6, satn[3]);
1867 atp_writeb_io(dev, c, 7, satn[4]);
1868 atp_writeb_io(dev, c, 8, satn[5]);
1869 atp_writeb_io(dev, c, 0x0f, 0);
1870 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
1871 atp_writeb_io(dev, c, 0x12, 0);
1872 atp_writeb_io(dev, c, 0x13, satn[6]);
1873 atp_writeb_io(dev, c, 0x14, satn[7]);
1874 atp_writeb_io(dev, c, 0x18, satn[8]);
1875
1876 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
1877 cpu_relax();
1878
1879 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
1880 continue;
1881
1882 while (atp_readb_io(dev, c, 0x17) != 0x8e)
1883 cpu_relax();
1884
1885 try_wide:
1886 j = 0;
1887 atp_writeb_io(dev, c, 0x14, 0x05);
1888 atp_writeb_io(dev, c, 0x18, 0x20);
1889
1890 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
1891 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0)
1892 atp_writeb_io(dev, c, 0x19, wide[j++]);
1893 }
1894
1895 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00)
1896 cpu_relax();
1897
1898 j = atp_readb_io(dev, c, 0x17) & 0x0f;
1899 if (j == 0x0f) {
1900 goto widep_in;
1901 }
1902 if (j == 0x0a) {
1903 goto widep_cmd;
1904 }
1905 if (j == 0x0e) {
1906 goto try_wide;
1907 }
1908 continue;
1909 widep_out:
1910 atp_writeb_io(dev, c, 0x18, 0x20);
1911 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
1912 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0)
1913 atp_writeb_io(dev, c, 0x19, 0);
1914 }
1915 j = atp_readb_io(dev, c, 0x17) & 0x0f;
1916 if (j == 0x0f) {
1917 goto widep_in;
1918 }
1919 if (j == 0x0a) {
1920 goto widep_cmd;
1921 }
1922 if (j == 0x0e) {
1923 goto widep_out;
1924 }
1925 continue;
1926 widep_in:
1927 atp_writeb_io(dev, c, 0x14, 0xff);
1928 atp_writeb_io(dev, c, 0x18, 0x20);
1929 k = 0;
1930 widep_in1:
1931 j = atp_readb_io(dev, c, 0x1f);
1932 if ((j & 0x01) != 0) {
1933 mbuf[k++] = atp_readb_io(dev, c, 0x19);
1934 goto widep_in1;
1935 }
1936 if ((j & 0x80) == 0x00) {
1937 goto widep_in1;
1938 }
1939 j = atp_readb_io(dev, c, 0x17) & 0x0f;
1940 if (j == 0x0f) {
1941 goto widep_in;
1942 }
1943 if (j == 0x0a) {
1944 goto widep_cmd;
1945 }
1946 if (j == 0x0e) {
1947 goto widep_out;
1948 }
1949 continue;
1950 widep_cmd:
1951 atp_writeb_io(dev, c, 0x10, 0x30);
1952 atp_writeb_io(dev, c, 0x14, 0x00);
1953 atp_writeb_io(dev, c, 0x18, 0x08);
1954
1955 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
1956 cpu_relax();
1957
1958 j = atp_readb_io(dev, c, 0x17);
1959 if (j != 0x16) {
1960 if (j == 0x4e) {
1961 goto widep_out;
1962 }
1963 continue;
1964 }
1965 if (mbuf[0] != 0x01) {
1966 goto not_wide;
1967 }
1968 if (mbuf[1] != 0x02) {
1969 goto not_wide;
1970 }
1971 if (mbuf[2] != 0x03) {
1972 goto not_wide;
1973 }
1974 if (mbuf[3] != 0x01) {
1975 goto not_wide;
1976 }
1977 m = 1;
1978 m = m << i;
1979 dev->wide_id[c] |= m;
1980 not_wide:
1981 if ((dev->id[c][i].devtype == 0x00) || (dev->id[c][i].devtype == 0x07) || ((dev->id[c][i].devtype == 0x05) && ((n & 0x10) != 0))) {
1982 m = 1;
1983 m = m << i;
1984 if ((dev->async[c] & m) != 0) {
1985 goto set_sync;
1986 }
1987 }
1988 continue;
1989 set_sync:
1990 if (dev->sp[c][i] == 0x02) {
1991 synu[4] = 0x0c;
1992 synuw[4] = 0x0c;
1993 } else {
1994 if (dev->sp[c][i] >= 0x03) {
1995 synu[4] = 0x0a;
1996 synuw[4] = 0x0a;
1997 }
1998 }
1999 j = 0;
2000 if ((m & dev->wide_id[c]) != 0) {
2001 j |= 0x01;
2002 }
2003 atp_writeb_io(dev, c, 0x1b, j);
2004 atp_writeb_io(dev, c, 3, satn[0]);
2005 atp_writeb_io(dev, c, 4, satn[1]);
2006 atp_writeb_io(dev, c, 5, satn[2]);
2007 atp_writeb_io(dev, c, 6, satn[3]);
2008 atp_writeb_io(dev, c, 7, satn[4]);
2009 atp_writeb_io(dev, c, 8, satn[5]);
2010 atp_writeb_io(dev, c, 0x0f, 0);
2011 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
2012 atp_writeb_io(dev, c, 0x12, 0);
2013 atp_writeb_io(dev, c, 0x13, satn[6]);
2014 atp_writeb_io(dev, c, 0x14, satn[7]);
2015 atp_writeb_io(dev, c, 0x18, satn[8]);
2016
2017 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
2018 cpu_relax();
2019
2020 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
2021 continue;
2022
2023 while (atp_readb_io(dev, c, 0x17) != 0x8e)
2024 cpu_relax();
2025
2026 try_sync:
2027 j = 0;
2028 atp_writeb_io(dev, c, 0x14, 0x06);
2029 atp_writeb_io(dev, c, 0x18, 0x20);
2030
2031 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
2032 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) {
2033 if ((m & dev->wide_id[c]) != 0) {
2034 if ((m & dev->ultra_map[c]) != 0) {
2035 atp_writeb_io(dev, c, 0x19, synuw[j++]);
2036 } else {
2037 atp_writeb_io(dev, c, 0x19, synw[j++]);
2038 }
2039 } else {
2040 if ((m & dev->ultra_map[c]) != 0) {
2041 atp_writeb_io(dev, c, 0x19, synu[j++]);
2042 } else {
2043 atp_writeb_io(dev, c, 0x19, synn[j++]);
2044 }
2045 }
2046 }
2047 }
2048
2049 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00)
2050 cpu_relax();
2051
2052 j = atp_readb_io(dev, c, 0x17) & 0x0f;
2053 if (j == 0x0f) {
2054 goto phase_ins;
2055 }
2056 if (j == 0x0a) {
2057 goto phase_cmds;
2058 }
2059 if (j == 0x0e) {
2060 goto try_sync;
2061 }
2062 continue;
2063 phase_outs:
2064 atp_writeb_io(dev, c, 0x18, 0x20);
2065 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) {
2066 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0x00)
2067 atp_writeb_io(dev, c, 0x19, 0x00);
2068 }
2069 j = atp_readb_io(dev, c, 0x17);
2070 if (j == 0x85) {
2071 goto tar_dcons;
2072 }
2073 j &= 0x0f;
2074 if (j == 0x0f) {
2075 goto phase_ins;
2076 }
2077 if (j == 0x0a) {
2078 goto phase_cmds;
2079 }
2080 if (j == 0x0e) {
2081 goto phase_outs;
2082 }
2083 continue;
2084 phase_ins:
2085 atp_writeb_io(dev, c, 0x14, 0x06);
2086 atp_writeb_io(dev, c, 0x18, 0x20);
2087 k = 0;
2088 phase_ins1:
2089 j = atp_readb_io(dev, c, 0x1f);
2090 if ((j & 0x01) != 0x00) {
2091 mbuf[k++] = atp_readb_io(dev, c, 0x19);
2092 goto phase_ins1;
2093 }
2094 if ((j & 0x80) == 0x00) {
2095 goto phase_ins1;
2096 }
2097
2098 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00)
2099 cpu_relax();
2100
2101 j = atp_readb_io(dev, c, 0x17);
2102 if (j == 0x85) {
2103 goto tar_dcons;
2104 }
2105 j &= 0x0f;
2106 if (j == 0x0f) {
2107 goto phase_ins;
2108 }
2109 if (j == 0x0a) {
2110 goto phase_cmds;
2111 }
2112 if (j == 0x0e) {
2113 goto phase_outs;
2114 }
2115 continue;
2116 phase_cmds:
2117 atp_writeb_io(dev, c, 0x10, 0x30);
2118 tar_dcons:
2119 atp_writeb_io(dev, c, 0x14, 0x00);
2120 atp_writeb_io(dev, c, 0x18, 0x08);
2121
2122 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
2123 cpu_relax();
2124
2125 j = atp_readb_io(dev, c, 0x17);
2126 if (j != 0x16) {
2127 continue;
2128 }
2129 if (mbuf[0] != 0x01) {
2130 continue;
2131 }
2132 if (mbuf[1] != 0x03) {
2133 continue;
2134 }
2135 if (mbuf[4] == 0x00) {
2136 continue;
2137 }
2138 if (mbuf[3] > 0x64) {
2139 continue;
2140 }
2141 if (mbuf[4] > 0x0e) {
2142 mbuf[4] = 0x0e;
2143 }
2144 dev->id[c][i].devsp = mbuf[4];
2145 if (mbuf[3] < 0x0c) {
2146 j = 0xb0;
2147 goto set_syn_ok;
2148 }
2149 if ((mbuf[3] < 0x0d) && (rmb == 0)) {
2150 j = 0xa0;
2151 goto set_syn_ok;
2152 }
2153 if (mbuf[3] < 0x1a) {
2154 j = 0x20;
2155 goto set_syn_ok;
2156 }
2157 if (mbuf[3] < 0x33) {
2158 j = 0x40;
2159 goto set_syn_ok;
2160 }
2161 if (mbuf[3] < 0x4c) {
2162 j = 0x50;
2163 goto set_syn_ok;
2164 }
2165 j = 0x60;
2166 set_syn_ok:
2167 dev->id[c][i].devsp = (dev->id[c][i].devsp & 0x0f) | j;
2168 }
2169 }
2170
2171 static void atp870u_free_tables(struct Scsi_Host *host)
2172 {
2173 struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata;
2174 int j, k;
2175 for (j=0; j < 2; j++) {
2176 for (k = 0; k < 16; k++) {
2177 if (!atp_dev->id[j][k].prd_table)
2178 continue;
2179 pci_free_consistent(atp_dev->pdev, 1024, atp_dev->id[j][k].prd_table, atp_dev->id[j][k].prd_bus);
2180 atp_dev->id[j][k].prd_table = NULL;
2181 }
2182 }
2183 }
2184
2185 static int atp870u_init_tables(struct Scsi_Host *host)
2186 {
2187 struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata;
2188 int c,k;
2189 for(c=0;c < 2;c++) {
2190 for(k=0;k<16;k++) {
2191 atp_dev->id[c][k].prd_table = pci_alloc_consistent(atp_dev->pdev, 1024, &(atp_dev->id[c][k].prd_bus));
2192 if (!atp_dev->id[c][k].prd_table) {
2193 printk("atp870u_init_tables fail\n");
2194 atp870u_free_tables(host);
2195 return -ENOMEM;
2196 }
2197 atp_dev->id[c][k].prdaddr = atp_dev->id[c][k].prd_bus;
2198 atp_dev->id[c][k].devsp=0x20;
2199 atp_dev->id[c][k].devtype = 0x7f;
2200 atp_dev->id[c][k].curr_req = NULL;
2201 }
2202
2203 atp_dev->active_id[c] = 0;
2204 atp_dev->wide_id[c] = 0;
2205 atp_dev->host_id[c] = 0x07;
2206 atp_dev->quhd[c] = 0;
2207 atp_dev->quend[c] = 0;
2208 atp_dev->last_cmd[c] = 0xff;
2209 atp_dev->in_snd[c] = 0;
2210 atp_dev->in_int[c] = 0;
2211
2212 for (k = 0; k < qcnt; k++) {
2213 atp_dev->quereq[c][k] = NULL;
2214 }
2215 for (k = 0; k < 16; k++) {
2216 atp_dev->id[c][k].curr_req = NULL;
2217 atp_dev->sp[c][k] = 0x04;
2218 }
2219 }
2220 return 0;
2221 }
2222
2223 /* return non-zero on detection */
2224 static int atp870u_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2225 {
2226 unsigned char k, m, c;
2227 unsigned long flags;
2228 unsigned int base_io, error,n;
2229 unsigned char host_id;
2230 struct Scsi_Host *shpnt = NULL;
2231 struct atp_unit *atpdev, *p;
2232 unsigned char setupdata[2][16];
2233 int count = 0;
2234
2235 atpdev = kzalloc(sizeof(*atpdev), GFP_KERNEL);
2236 if (!atpdev)
2237 return -ENOMEM;
2238
2239 if (pci_enable_device(pdev))
2240 goto err_eio;
2241
2242 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2243 printk(KERN_INFO "atp870u: use 32bit DMA mask.\n");
2244 } else {
2245 printk(KERN_ERR "atp870u: DMA mask required but not available.\n");
2246 goto err_eio;
2247 }
2248
2249 /*
2250 * It's probably easier to weed out some revisions like
2251 * this than via the PCI device table
2252 */
2253 if (ent->device == PCI_DEVICE_ID_ARTOP_AEC7610) {
2254 atpdev->chip_ver = pdev->revision;
2255 if (atpdev->chip_ver < 2)
2256 goto err_eio;
2257 }
2258
2259 switch (ent->device) {
2260 case PCI_DEVICE_ID_ARTOP_AEC7612UW:
2261 case PCI_DEVICE_ID_ARTOP_AEC7612SUW:
2262 case ATP880_DEVID1:
2263 case ATP880_DEVID2:
2264 case ATP885_DEVID:
2265 atpdev->chip_ver = 0x04;
2266 default:
2267 break;
2268 }
2269 base_io = pci_resource_start(pdev, 0);
2270 base_io &= 0xfffffff8;
2271 atpdev->baseport = base_io;
2272
2273 if ((ent->device == ATP880_DEVID1)||(ent->device == ATP880_DEVID2)) {
2274 atpdev->chip_ver = pdev->revision;
2275 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);//JCC082803
2276
2277 host_id = inb(base_io + 0x39);
2278 host_id >>= 0x04;
2279
2280 printk(KERN_INFO " ACARD AEC-67160 PCI Ultra3 LVD Host Adapter: %d"
2281 " IO:%x, IRQ:%d.\n", count, base_io, pdev->irq);
2282 atpdev->ioport[0] = base_io + 0x40;
2283 atpdev->pciport[0] = base_io + 0x28;
2284 atpdev->dev_id = ent->device;
2285 atpdev->host_id[0] = host_id;
2286
2287 atpdev->scam_on = inb(base_io + 0x22);
2288 atpdev->global_map[0] = inb(base_io + 0x35);
2289 atpdev->ultra_map[0] = inw(base_io + 0x3c);
2290
2291 n = 0x3f09;
2292 next_fblk_880:
2293 if (n >= 0x4000)
2294 goto flash_ok_880;
2295
2296 m = 0;
2297 outw(n, base_io + 0x34);
2298 n += 0x0002;
2299 if (inb(base_io + 0x30) == 0xff)
2300 goto flash_ok_880;
2301
2302 atpdev->sp[0][m++] = inb(base_io + 0x30);
2303 atpdev->sp[0][m++] = inb(base_io + 0x31);
2304 atpdev->sp[0][m++] = inb(base_io + 0x32);
2305 atpdev->sp[0][m++] = inb(base_io + 0x33);
2306 outw(n, base_io + 0x34);
2307 n += 0x0002;
2308 atpdev->sp[0][m++] = inb(base_io + 0x30);
2309 atpdev->sp[0][m++] = inb(base_io + 0x31);
2310 atpdev->sp[0][m++] = inb(base_io + 0x32);
2311 atpdev->sp[0][m++] = inb(base_io + 0x33);
2312 outw(n, base_io + 0x34);
2313 n += 0x0002;
2314 atpdev->sp[0][m++] = inb(base_io + 0x30);
2315 atpdev->sp[0][m++] = inb(base_io + 0x31);
2316 atpdev->sp[0][m++] = inb(base_io + 0x32);
2317 atpdev->sp[0][m++] = inb(base_io + 0x33);
2318 outw(n, base_io + 0x34);
2319 n += 0x0002;
2320 atpdev->sp[0][m++] = inb(base_io + 0x30);
2321 atpdev->sp[0][m++] = inb(base_io + 0x31);
2322 atpdev->sp[0][m++] = inb(base_io + 0x32);
2323 atpdev->sp[0][m++] = inb(base_io + 0x33);
2324 n += 0x0018;
2325 goto next_fblk_880;
2326 flash_ok_880:
2327 outw(0, base_io + 0x34);
2328 atpdev->ultra_map[0] = 0;
2329 atpdev->async[0] = 0;
2330 for (k = 0; k < 16; k++) {
2331 n = 1;
2332 n = n << k;
2333 if (atpdev->sp[0][k] > 1) {
2334 atpdev->ultra_map[0] |= n;
2335 } else {
2336 if (atpdev->sp[0][k] == 0)
2337 atpdev->async[0] |= n;
2338 }
2339 }
2340 atpdev->async[0] = ~(atpdev->async[0]);
2341 outb(atpdev->global_map[0], base_io + 0x35);
2342
2343 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
2344 if (!shpnt)
2345 goto err_nomem;
2346
2347 p = (struct atp_unit *)&shpnt->hostdata;
2348
2349 atpdev->host = shpnt;
2350 atpdev->pdev = pdev;
2351 pci_set_drvdata(pdev, p);
2352 memcpy(p, atpdev, sizeof(*atpdev));
2353 if (atp870u_init_tables(shpnt) < 0) {
2354 printk(KERN_ERR "Unable to allocate tables for Acard controller\n");
2355 goto unregister;
2356 }
2357
2358 if (request_irq(pdev->irq, atp870u_intr_handle, IRQF_SHARED, "atp880i", shpnt)) {
2359 printk(KERN_ERR "Unable to allocate IRQ%d for Acard controller.\n", pdev->irq);
2360 goto free_tables;
2361 }
2362
2363 spin_lock_irqsave(shpnt->host_lock, flags);
2364 k = inb(base_io + 0x38) & 0x80;
2365 outb(k, base_io + 0x38);
2366 outb(0x20, base_io + 0x3b);
2367 mdelay(32);
2368 outb(0, base_io + 0x3b);
2369 mdelay(32);
2370 inb(base_io + 0x5b);
2371 inb(base_io + 0x57);
2372 outb((host_id | 0x08), base_io + 0x40);
2373 outb(0, base_io + 0x58);
2374 while ((inb(base_io + 0x5f) & 0x80) == 0)
2375 mdelay(1);
2376 inb(base_io + 0x57);
2377 outb(8, base_io + 0x41);
2378 outb(0x7f, base_io + 0x42);
2379 outb(0x20, base_io + 0x51);
2380
2381 tscam(shpnt);
2382 is880(p, 0);
2383 outb(0xb0, base_io + 0x38);
2384 shpnt->max_id = 16;
2385 shpnt->this_id = host_id;
2386 shpnt->unique_id = base_io;
2387 shpnt->io_port = base_io;
2388 shpnt->n_io_port = 0x60; /* Number of bytes of I/O space used */
2389 shpnt->irq = pdev->irq;
2390 } else if (ent->device == ATP885_DEVID) {
2391 printk(KERN_INFO " ACARD AEC-67162 PCI Ultra3 LVD Host Adapter: IO:%x, IRQ:%d.\n"
2392 , base_io, pdev->irq);
2393
2394 atpdev->pdev = pdev;
2395 atpdev->dev_id = ent->device;
2396 atpdev->ioport[0] = base_io + 0x80;
2397 atpdev->ioport[1] = base_io + 0xc0;
2398 atpdev->pciport[0] = base_io + 0x40;
2399 atpdev->pciport[1] = base_io + 0x50;
2400
2401 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
2402 if (!shpnt)
2403 goto err_nomem;
2404
2405 p = (struct atp_unit *)&shpnt->hostdata;
2406
2407 atpdev->host = shpnt;
2408 atpdev->pdev = pdev;
2409 pci_set_drvdata(pdev, p);
2410 memcpy(p, atpdev, sizeof(struct atp_unit));
2411 if (atp870u_init_tables(shpnt) < 0)
2412 goto unregister;
2413
2414 #ifdef ED_DBGP
2415 printk("request_irq() shpnt %p hostdata %p\n", shpnt, p);
2416 #endif
2417 if (request_irq(pdev->irq, atp870u_intr_handle, IRQF_SHARED, "atp870u", shpnt)) {
2418 printk(KERN_ERR "Unable to allocate IRQ for Acard controller.\n");
2419 goto free_tables;
2420 }
2421
2422 spin_lock_irqsave(shpnt->host_lock, flags);
2423
2424 c=inb(base_io + 0x29);
2425 outb((c | 0x04),base_io + 0x29);
2426
2427 n=0x1f80;
2428 next_fblk_885:
2429 if (n >= 0x2000) {
2430 goto flash_ok_885;
2431 }
2432 outw(n,base_io + 0x3c);
2433 if (inl(base_io + 0x38) == 0xffffffff) {
2434 goto flash_ok_885;
2435 }
2436 for (m=0; m < 2; m++) {
2437 p->global_map[m]= 0;
2438 for (k=0; k < 4; k++) {
2439 outw(n++,base_io + 0x3c);
2440 ((unsigned long *)&setupdata[m][0])[k]=inl(base_io + 0x38);
2441 }
2442 for (k=0; k < 4; k++) {
2443 outw(n++,base_io + 0x3c);
2444 ((unsigned long *)&p->sp[m][0])[k]=inl(base_io + 0x38);
2445 }
2446 n += 8;
2447 }
2448 goto next_fblk_885;
2449 flash_ok_885:
2450 #ifdef ED_DBGP
2451 printk( "Flash Read OK\n");
2452 #endif
2453 c=inb(base_io + 0x29);
2454 outb((c & 0xfb),base_io + 0x29);
2455 for (c=0;c < 2;c++) {
2456 p->ultra_map[c]=0;
2457 p->async[c] = 0;
2458 for (k=0; k < 16; k++) {
2459 n=1;
2460 n = n << k;
2461 if (p->sp[c][k] > 1) {
2462 p->ultra_map[c] |= n;
2463 } else {
2464 if (p->sp[c][k] == 0) {
2465 p->async[c] |= n;
2466 }
2467 }
2468 }
2469 p->async[c] = ~(p->async[c]);
2470
2471 if (p->global_map[c] == 0) {
2472 k=setupdata[c][1];
2473 if ((k & 0x40) != 0)
2474 p->global_map[c] |= 0x20;
2475 k &= 0x07;
2476 p->global_map[c] |= k;
2477 if ((setupdata[c][2] & 0x04) != 0)
2478 p->global_map[c] |= 0x08;
2479 p->host_id[c] = setupdata[c][0] & 0x07;
2480 }
2481 }
2482
2483 k = inb(base_io + 0x28) & 0x8f;
2484 k |= 0x10;
2485 outb(k, base_io + 0x28);
2486 outb(0x80, base_io + 0x41);
2487 outb(0x80, base_io + 0x51);
2488 mdelay(100);
2489 outb(0, base_io + 0x41);
2490 outb(0, base_io + 0x51);
2491 mdelay(1000);
2492 inb(base_io + 0x9b);
2493 inb(base_io + 0x97);
2494 inb(base_io + 0xdb);
2495 inb(base_io + 0xd7);
2496 k=p->host_id[0];
2497 if (k > 7)
2498 k = (k & 0x07) | 0x40;
2499 k |= 0x08;
2500 outb(k, base_io + 0x80);
2501 outb(0, base_io + 0x98);
2502
2503 while ((inb(base_io + 0x9f) & 0x80) == 0)
2504 cpu_relax();
2505
2506 inb(base_io + 0x97);
2507 outb(8, base_io + 0x81);
2508 outb(0x7f, base_io + 0x82);
2509 outb(0x20, base_io + 0x91);
2510
2511 k=p->host_id[1];
2512 if (k > 7)
2513 k = (k & 0x07) | 0x40;
2514 k |= 0x08;
2515 outb(k, base_io + 0xc0);
2516 outb(0, base_io + 0xd8);
2517
2518 while ((inb(base_io + 0xdf) & 0x80) == 0)
2519 cpu_relax();
2520
2521 inb(base_io + 0xd7);
2522 outb(8, base_io + 0xc1);
2523 outb(0x7f, base_io + 0xc2);
2524 outb(0x20, base_io + 0xd1);
2525
2526 tscam_885();
2527 printk(KERN_INFO " Scanning Channel A SCSI Device ...\n");
2528 is885(p, 0);
2529 printk(KERN_INFO " Scanning Channel B SCSI Device ...\n");
2530 is885(p, 1);
2531
2532 k = inb(base_io + 0x28) & 0xcf;
2533 k |= 0xc0;
2534 outb(k, base_io + 0x28);
2535 k = inb(base_io + 0x1f) | 0x80;
2536 outb(k, base_io + 0x1f);
2537 k = inb(base_io + 0x29) | 0x01;
2538 outb(k, base_io + 0x29);
2539 #ifdef ED_DBGP
2540 //printk("atp885: atp_host[0] 0x%p\n", atp_host[0]);
2541 #endif
2542 shpnt->max_id = 16;
2543 shpnt->max_lun = (p->global_map[0] & 0x07) + 1;
2544 shpnt->max_channel = 1;
2545 shpnt->this_id = p->host_id[0];
2546 shpnt->unique_id = base_io;
2547 shpnt->io_port = base_io;
2548 shpnt->n_io_port = 0xff; /* Number of bytes of I/O space used */
2549 shpnt->irq = pdev->irq;
2550
2551 } else {
2552 error = pci_read_config_byte(pdev, 0x49, &host_id);
2553
2554 printk(KERN_INFO " ACARD AEC-671X PCI Ultra/W SCSI-2/3 Host Adapter: %d "
2555 "IO:%x, IRQ:%d.\n", count, base_io, pdev->irq);
2556
2557 atpdev->ioport[0] = base_io;
2558 atpdev->pciport[0] = base_io + 0x20;
2559 atpdev->dev_id = ent->device;
2560 host_id &= 0x07;
2561 atpdev->host_id[0] = host_id;
2562 atpdev->scam_on = inb(base_io + 0x22);
2563 atpdev->global_map[0] = inb(base_io + 0x2d);
2564 atpdev->ultra_map[0] = inw(base_io + 0x2e);
2565
2566 if (atpdev->ultra_map[0] == 0) {
2567 atpdev->scam_on = 0x00;
2568 atpdev->global_map[0] = 0x20;
2569 atpdev->ultra_map[0] = 0xffff;
2570 }
2571
2572 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
2573 if (!shpnt)
2574 goto err_nomem;
2575
2576 p = (struct atp_unit *)&shpnt->hostdata;
2577
2578 atpdev->host = shpnt;
2579 atpdev->pdev = pdev;
2580 pci_set_drvdata(pdev, p);
2581 memcpy(p, atpdev, sizeof(*atpdev));
2582 if (atp870u_init_tables(shpnt) < 0)
2583 goto unregister;
2584
2585 if (request_irq(pdev->irq, atp870u_intr_handle, IRQF_SHARED, "atp870i", shpnt)) {
2586 printk(KERN_ERR "Unable to allocate IRQ%d for Acard controller.\n", pdev->irq);
2587 goto free_tables;
2588 }
2589
2590 spin_lock_irqsave(shpnt->host_lock, flags);
2591 if (atpdev->chip_ver > 0x07) { /* check if atp876 chip then enable terminator */
2592 outb(0x00, base_io + 0x3e);
2593 }
2594
2595 k = (inb(base_io + 0x3a) & 0xf3) | 0x10;
2596 outb(k, base_io + 0x3a);
2597 outb((k & 0xdf), base_io + 0x3a);
2598 mdelay(32);
2599 outb(k, base_io + 0x3a);
2600 mdelay(32);
2601 outb((host_id | 0x08), base_io + 0);
2602 outb(0, base_io + 0x18);
2603 while ((inb(base_io + 0x1f) & 0x80) == 0)
2604 mdelay(1);
2605
2606 inb(base_io + 0x17);
2607 outb(8, base_io + 1);
2608 outb(0x7f, base_io + 2);
2609 outb(0x20, base_io + 0x11);
2610
2611 tscam(shpnt);
2612 is870(p, 0);
2613 outb((inb(base_io + 0x3a) & 0xef), base_io + 0x3a);
2614 outb((inb(base_io + 0x3b) | 0x20), base_io + 0x3b);
2615 if (atpdev->chip_ver == 4)
2616 shpnt->max_id = 16;
2617 else
2618 shpnt->max_id = 8;
2619 shpnt->this_id = host_id;
2620 shpnt->unique_id = base_io;
2621 shpnt->io_port = base_io;
2622 shpnt->n_io_port = 0x40; /* Number of bytes of I/O space used */
2623 shpnt->irq = pdev->irq;
2624 }
2625 spin_unlock_irqrestore(shpnt->host_lock, flags);
2626 if(ent->device==ATP885_DEVID) {
2627 if(!request_region(base_io, 0xff, "atp870u")) /* Register the IO ports that we use */
2628 goto request_io_fail;
2629 } else if((ent->device==ATP880_DEVID1)||(ent->device==ATP880_DEVID2)) {
2630 if(!request_region(base_io, 0x60, "atp870u")) /* Register the IO ports that we use */
2631 goto request_io_fail;
2632 } else {
2633 if(!request_region(base_io, 0x40, "atp870u")) /* Register the IO ports that we use */
2634 goto request_io_fail;
2635 }
2636 count++;
2637 if (scsi_add_host(shpnt, &pdev->dev))
2638 goto scsi_add_fail;
2639 scsi_scan_host(shpnt);
2640 #ifdef ED_DBGP
2641 printk("atp870u_prob : exit\n");
2642 #endif
2643 return 0;
2644
2645 scsi_add_fail:
2646 printk("atp870u_prob:scsi_add_fail\n");
2647 if(ent->device==ATP885_DEVID) {
2648 release_region(base_io, 0xff);
2649 } else if((ent->device==ATP880_DEVID1)||(ent->device==ATP880_DEVID2)) {
2650 release_region(base_io, 0x60);
2651 } else {
2652 release_region(base_io, 0x40);
2653 }
2654 request_io_fail:
2655 printk("atp870u_prob:request_io_fail\n");
2656 free_irq(pdev->irq, shpnt);
2657 free_tables:
2658 printk("atp870u_prob:free_table\n");
2659 atp870u_free_tables(shpnt);
2660 unregister:
2661 printk("atp870u_prob:unregister\n");
2662 scsi_host_put(shpnt);
2663 return -1;
2664 err_eio:
2665 kfree(atpdev);
2666 return -EIO;
2667 err_nomem:
2668 kfree(atpdev);
2669 return -ENOMEM;
2670 }
2671
2672 /* The abort command does not leave the device in a clean state where
2673 it is available to be used again. Until this gets worked out, we will
2674 leave it commented out. */
2675
2676 static int atp870u_abort(struct scsi_cmnd * SCpnt)
2677 {
2678 unsigned char j, k, c;
2679 struct scsi_cmnd *workrequ;
2680 struct atp_unit *dev;
2681 struct Scsi_Host *host;
2682 host = SCpnt->device->host;
2683
2684 dev = (struct atp_unit *)&host->hostdata;
2685 c = scmd_channel(SCpnt);
2686 printk(" atp870u: abort Channel = %x \n", c);
2687 printk("working=%x last_cmd=%x ", dev->working[c], dev->last_cmd[c]);
2688 printk(" quhdu=%x quendu=%x ", dev->quhd[c], dev->quend[c]);
2689 for (j = 0; j < 0x18; j++) {
2690 printk(" r%2x=%2x", j, atp_readb_io(dev, c, j));
2691 }
2692 printk(" r1c=%2x", atp_readb_io(dev, c, 0x1c));
2693 printk(" r1f=%2x in_snd=%2x ", atp_readb_io(dev, c, 0x1f), dev->in_snd[c]);
2694 printk(" d00=%2x", atp_readb_pci(dev, c, 0x00));
2695 printk(" d02=%2x", atp_readb_pci(dev, c, 0x02));
2696 for(j=0;j<16;j++) {
2697 if (dev->id[c][j].curr_req != NULL) {
2698 workrequ = dev->id[c][j].curr_req;
2699 printk("\n que cdb= ");
2700 for (k=0; k < workrequ->cmd_len; k++) {
2701 printk(" %2x ",workrequ->cmnd[k]);
2702 }
2703 printk(" last_lenu= %x ",(unsigned int)dev->id[c][j].last_len);
2704 }
2705 }
2706 return SUCCESS;
2707 }
2708
2709 static const char *atp870u_info(struct Scsi_Host *notused)
2710 {
2711 static char buffer[128];
2712
2713 strcpy(buffer, "ACARD AEC-6710/6712/67160 PCI Ultra/W/LVD SCSI-3 Adapter Driver V2.6+ac ");
2714
2715 return buffer;
2716 }
2717
2718 static int atp870u_show_info(struct seq_file *m, struct Scsi_Host *HBAptr)
2719 {
2720 seq_puts(m, "ACARD AEC-671X Driver Version: 2.6+ac\n\n"
2721 "Adapter Configuration:\n");
2722 seq_printf(m, " Base IO: %#.4lx\n", HBAptr->io_port);
2723 seq_printf(m, " IRQ: %d\n", HBAptr->irq);
2724 return 0;
2725 }
2726
2727
2728 static int atp870u_biosparam(struct scsi_device *disk, struct block_device *dev,
2729 sector_t capacity, int *ip)
2730 {
2731 int heads, sectors, cylinders;
2732
2733 heads = 64;
2734 sectors = 32;
2735 cylinders = (unsigned long)capacity / (heads * sectors);
2736 if (cylinders > 1024) {
2737 heads = 255;
2738 sectors = 63;
2739 cylinders = (unsigned long)capacity / (heads * sectors);
2740 }
2741 ip[0] = heads;
2742 ip[1] = sectors;
2743 ip[2] = cylinders;
2744
2745 return 0;
2746 }
2747
2748 static void atp870u_remove (struct pci_dev *pdev)
2749 {
2750 struct atp_unit *devext = pci_get_drvdata(pdev);
2751 struct Scsi_Host *pshost = devext->host;
2752
2753
2754 scsi_remove_host(pshost);
2755 printk(KERN_INFO "free_irq : %d\n",pshost->irq);
2756 free_irq(pshost->irq, pshost);
2757 release_region(pshost->io_port, pshost->n_io_port);
2758 printk(KERN_INFO "atp870u_free_tables : %p\n",pshost);
2759 atp870u_free_tables(pshost);
2760 printk(KERN_INFO "scsi_host_put : %p\n",pshost);
2761 scsi_host_put(pshost);
2762 }
2763 MODULE_LICENSE("GPL");
2764
2765 static struct scsi_host_template atp870u_template = {
2766 .module = THIS_MODULE,
2767 .name = "atp870u" /* name */,
2768 .proc_name = "atp870u",
2769 .show_info = atp870u_show_info,
2770 .info = atp870u_info /* info */,
2771 .queuecommand = atp870u_queuecommand /* queuecommand */,
2772 .eh_abort_handler = atp870u_abort /* abort */,
2773 .bios_param = atp870u_biosparam /* biosparm */,
2774 .can_queue = qcnt /* can_queue */,
2775 .this_id = 7 /* SCSI ID */,
2776 .sg_tablesize = ATP870U_SCATTER /*SG_ALL*/ /*SG_NONE*/,
2777 .use_clustering = ENABLE_CLUSTERING,
2778 .max_sectors = ATP870U_MAX_SECTORS,
2779 };
2780
2781 static struct pci_device_id atp870u_id_table[] = {
2782 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP885_DEVID) },
2783 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID1) },
2784 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID2) },
2785 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7610) },
2786 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612UW) },
2787 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612U) },
2788 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612S) },
2789 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612D) },
2790 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612SUW) },
2791 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_8060) },
2792 { 0, },
2793 };
2794
2795 MODULE_DEVICE_TABLE(pci, atp870u_id_table);
2796
2797 static struct pci_driver atp870u_driver = {
2798 .id_table = atp870u_id_table,
2799 .name = "atp870u",
2800 .probe = atp870u_probe,
2801 .remove = atp870u_remove,
2802 };
2803
2804 static int __init atp870u_init(void)
2805 {
2806 #ifdef ED_DBGP
2807 printk("atp870u_init: Entry\n");
2808 #endif
2809 return pci_register_driver(&atp870u_driver);
2810 }
2811
2812 static void __exit atp870u_exit(void)
2813 {
2814 #ifdef ED_DBGP
2815 printk("atp870u_exit: Entry\n");
2816 #endif
2817 pci_unregister_driver(&atp870u_driver);
2818 }
2819
2820 static void tscam_885(void)
2821 {
2822 unsigned char i;
2823
2824 for (i = 0; i < 0x2; i++) {
2825 mdelay(300);
2826 }
2827 return;
2828 }
2829
2830
2831
2832 static void is885(struct atp_unit *dev, unsigned char c)
2833 {
2834 unsigned char i, j, k, rmb, n, lvdmode;
2835 unsigned short int m;
2836 static unsigned char mbuf[512];
2837 static unsigned char satn[9] = { 0, 0, 0, 0, 0, 0, 0, 6, 6 };
2838 static unsigned char inqd[9] = { 0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6 };
2839 static unsigned char synn[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
2840 unsigned char synu[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e };
2841 static unsigned char synw[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
2842 unsigned char synuw[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e };
2843 static unsigned char wide[6] = { 0x80, 1, 2, 3, 1, 0 };
2844 static unsigned char u3[9] = { 0x80, 1, 6, 4, 0x09, 00, 0x0e, 0x01, 0x02 };
2845
2846 lvdmode = atp_readb_io(dev, c, 0x1b) >> 7;
2847
2848 for (i = 0; i < 16; i++) {
2849 m = 1;
2850 m = m << i;
2851 if ((m & dev->active_id[c]) != 0) {
2852 continue;
2853 }
2854 if (i == dev->host_id[c]) {
2855 printk(KERN_INFO " ID: %2d Host Adapter\n", dev->host_id[c]);
2856 continue;
2857 }
2858 atp_writeb_io(dev, c, 0x1b, 0x01);
2859 atp_writeb_io(dev, c, 1, 0x08);
2860 atp_writeb_io(dev, c, 2, 0x7f);
2861 atp_writeb_io(dev, c, 3, satn[0]);
2862 atp_writeb_io(dev, c, 4, satn[1]);
2863 atp_writeb_io(dev, c, 5, satn[2]);
2864 atp_writeb_io(dev, c, 6, satn[3]);
2865 atp_writeb_io(dev, c, 7, satn[4]);
2866 atp_writeb_io(dev, c, 8, satn[5]);
2867 atp_writeb_io(dev, c, 0x0f, 0);
2868 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
2869 atp_writeb_io(dev, c, 0x12, 0);
2870 atp_writeb_io(dev, c, 0x13, satn[6]);
2871 atp_writeb_io(dev, c, 0x14, satn[7]);
2872 j = i;
2873 if ((j & 0x08) != 0) {
2874 j = (j & 0x07) | 0x40;
2875 }
2876 atp_writeb_io(dev, c, 0x15, j);
2877 atp_writeb_io(dev, c, 0x18, satn[8]);
2878
2879 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
2880 cpu_relax();
2881
2882 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
2883 continue;
2884
2885 while (atp_readb_io(dev, c, 0x17) != 0x8e)
2886 cpu_relax();
2887
2888 dev->active_id[c] |= m;
2889
2890 atp_writeb_io(dev, c, 0x10, 0x30);
2891 atp_writeb_io(dev, c, 0x14, 0x00);
2892
2893 phase_cmd:
2894 atp_writeb_io(dev, c, 0x18, 0x08);
2895
2896 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
2897 cpu_relax();
2898
2899 j = atp_readb_io(dev, c, 0x17);
2900 if (j != 0x16) {
2901 atp_writeb_io(dev, c, 0x10, 0x41);
2902 goto phase_cmd;
2903 }
2904 sel_ok:
2905 atp_writeb_io(dev, c, 3, inqd[0]);
2906 atp_writeb_io(dev, c, 4, inqd[1]);
2907 atp_writeb_io(dev, c, 5, inqd[2]);
2908 atp_writeb_io(dev, c, 6, inqd[3]);
2909 atp_writeb_io(dev, c, 7, inqd[4]);
2910 atp_writeb_io(dev, c, 8, inqd[5]);
2911 atp_writeb_io(dev, c, 0x0f, 0);
2912 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
2913 atp_writeb_io(dev, c, 0x12, 0);
2914 atp_writeb_io(dev, c, 0x13, inqd[6]);
2915 atp_writeb_io(dev, c, 0x14, inqd[7]);
2916 atp_writeb_io(dev, c, 0x18, inqd[8]);
2917
2918 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
2919 cpu_relax();
2920
2921 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
2922 continue;
2923
2924 while (atp_readb_io(dev, c, 0x17) != 0x8e)
2925 cpu_relax();
2926
2927 atp_writeb_io(dev, c, 0x1b, 0x00);
2928 atp_writeb_io(dev, c, 0x18, 0x08);
2929 j = 0;
2930 rd_inq_data:
2931 k = atp_readb_io(dev, c, 0x1f);
2932 if ((k & 0x01) != 0) {
2933 mbuf[j++] = atp_readb_io(dev, c, 0x19);
2934 goto rd_inq_data;
2935 }
2936 if ((k & 0x80) == 0) {
2937 goto rd_inq_data;
2938 }
2939 j = atp_readb_io(dev, c, 0x17);
2940 if (j == 0x16) {
2941 goto inq_ok;
2942 }
2943 atp_writeb_io(dev, c, 0x10, 0x46);
2944 atp_writeb_io(dev, c, 0x12, 0);
2945 atp_writeb_io(dev, c, 0x13, 0);
2946 atp_writeb_io(dev, c, 0x14, 0);
2947 atp_writeb_io(dev, c, 0x18, 0x08);
2948
2949 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
2950 cpu_relax();
2951
2952 if (atp_readb_io(dev, c, 0x17) != 0x16)
2953 goto sel_ok;
2954
2955 inq_ok:
2956 mbuf[36] = 0;
2957 printk(KERN_INFO " ID: %2d %s\n", i, &mbuf[8]);
2958 dev->id[c][i].devtype = mbuf[0];
2959 rmb = mbuf[1];
2960 n = mbuf[7];
2961 if ((mbuf[7] & 0x60) == 0) {
2962 goto not_wide;
2963 }
2964 if ((i < 8) && ((dev->global_map[c] & 0x20) == 0)) {
2965 goto not_wide;
2966 }
2967 if (lvdmode == 0) {
2968 goto chg_wide;
2969 }
2970 if (dev->sp[c][i] != 0x04) // force u2
2971 {
2972 goto chg_wide;
2973 }
2974
2975 atp_writeb_io(dev, c, 0x1b, 0x01);
2976 atp_writeb_io(dev, c, 3, satn[0]);
2977 atp_writeb_io(dev, c, 4, satn[1]);
2978 atp_writeb_io(dev, c, 5, satn[2]);
2979 atp_writeb_io(dev, c, 6, satn[3]);
2980 atp_writeb_io(dev, c, 7, satn[4]);
2981 atp_writeb_io(dev, c, 8, satn[5]);
2982 atp_writeb_io(dev, c, 0x0f, 0);
2983 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
2984 atp_writeb_io(dev, c, 0x12, 0);
2985 atp_writeb_io(dev, c, 0x13, satn[6]);
2986 atp_writeb_io(dev, c, 0x14, satn[7]);
2987 atp_writeb_io(dev, c, 0x18, satn[8]);
2988
2989 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
2990 cpu_relax();
2991
2992 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
2993 continue;
2994
2995 while (atp_readb_io(dev, c, 0x17) != 0x8e)
2996 cpu_relax();
2997
2998 try_u3:
2999 j = 0;
3000 atp_writeb_io(dev, c, 0x14, 0x09);
3001 atp_writeb_io(dev, c, 0x18, 0x20);
3002
3003 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
3004 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0)
3005 atp_writeb_io(dev, c, 0x19, u3[j++]);
3006 cpu_relax();
3007 }
3008
3009 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00)
3010 cpu_relax();
3011
3012 j = atp_readb_io(dev, c, 0x17) & 0x0f;
3013 if (j == 0x0f) {
3014 goto u3p_in;
3015 }
3016 if (j == 0x0a) {
3017 goto u3p_cmd;
3018 }
3019 if (j == 0x0e) {
3020 goto try_u3;
3021 }
3022 continue;
3023 u3p_out:
3024 atp_writeb_io(dev, c, 0x18, 0x20);
3025 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
3026 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0)
3027 atp_writeb_io(dev, c, 0x19, 0);
3028 cpu_relax();
3029 }
3030 j = atp_readb_io(dev, c, 0x17) & 0x0f;
3031 if (j == 0x0f) {
3032 goto u3p_in;
3033 }
3034 if (j == 0x0a) {
3035 goto u3p_cmd;
3036 }
3037 if (j == 0x0e) {
3038 goto u3p_out;
3039 }
3040 continue;
3041 u3p_in:
3042 atp_writeb_io(dev, c, 0x14, 0x09);
3043 atp_writeb_io(dev, c, 0x18, 0x20);
3044 k = 0;
3045 u3p_in1:
3046 j = atp_readb_io(dev, c, 0x1f);
3047 if ((j & 0x01) != 0) {
3048 mbuf[k++] = atp_readb_io(dev, c, 0x19);
3049 goto u3p_in1;
3050 }
3051 if ((j & 0x80) == 0x00) {
3052 goto u3p_in1;
3053 }
3054 j = atp_readb_io(dev, c, 0x17) & 0x0f;
3055 if (j == 0x0f) {
3056 goto u3p_in;
3057 }
3058 if (j == 0x0a) {
3059 goto u3p_cmd;
3060 }
3061 if (j == 0x0e) {
3062 goto u3p_out;
3063 }
3064 continue;
3065 u3p_cmd:
3066 atp_writeb_io(dev, c, 0x10, 0x30);
3067 atp_writeb_io(dev, c, 0x14, 0x00);
3068 atp_writeb_io(dev, c, 0x18, 0x08);
3069
3070 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00);
3071
3072 j = atp_readb_io(dev, c, 0x17);
3073 if (j != 0x16) {
3074 if (j == 0x4e) {
3075 goto u3p_out;
3076 }
3077 continue;
3078 }
3079 if (mbuf[0] != 0x01) {
3080 goto chg_wide;
3081 }
3082 if (mbuf[1] != 0x06) {
3083 goto chg_wide;
3084 }
3085 if (mbuf[2] != 0x04) {
3086 goto chg_wide;
3087 }
3088 if (mbuf[3] == 0x09) {
3089 m = 1;
3090 m = m << i;
3091 dev->wide_id[c] |= m;
3092 dev->id[c][i].devsp = 0xce;
3093 #ifdef ED_DBGP
3094 printk("dev->id[%2d][%2d].devsp = %2x\n",c,i,dev->id[c][i].devsp);
3095 #endif
3096 continue;
3097 }
3098 chg_wide:
3099 atp_writeb_io(dev, c, 0x1b, 0x01);
3100 atp_writeb_io(dev, c, 3, satn[0]);
3101 atp_writeb_io(dev, c, 4, satn[1]);
3102 atp_writeb_io(dev, c, 5, satn[2]);
3103 atp_writeb_io(dev, c, 6, satn[3]);
3104 atp_writeb_io(dev, c, 7, satn[4]);
3105 atp_writeb_io(dev, c, 8, satn[5]);
3106 atp_writeb_io(dev, c, 0x0f, 0);
3107 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
3108 atp_writeb_io(dev, c, 0x12, 0);
3109 atp_writeb_io(dev, c, 0x13, satn[6]);
3110 atp_writeb_io(dev, c, 0x14, satn[7]);
3111 atp_writeb_io(dev, c, 0x18, satn[8]);
3112
3113 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
3114 cpu_relax();
3115
3116 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
3117 continue;
3118
3119 while (atp_readb_io(dev, c, 0x17) != 0x8e)
3120 cpu_relax();
3121
3122 try_wide:
3123 j = 0;
3124 atp_writeb_io(dev, c, 0x14, 0x05);
3125 atp_writeb_io(dev, c, 0x18, 0x20);
3126
3127 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
3128 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0)
3129 atp_writeb_io(dev, c, 0x19, wide[j++]);
3130 cpu_relax();
3131 }
3132
3133 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00)
3134 cpu_relax();
3135
3136 j = atp_readb_io(dev, c, 0x17) & 0x0f;
3137 if (j == 0x0f) {
3138 goto widep_in;
3139 }
3140 if (j == 0x0a) {
3141 goto widep_cmd;
3142 }
3143 if (j == 0x0e) {
3144 goto try_wide;
3145 }
3146 continue;
3147 widep_out:
3148 atp_writeb_io(dev, c, 0x18, 0x20);
3149 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
3150 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0)
3151 atp_writeb_io(dev, c, 0x19, 0);
3152 cpu_relax();
3153 }
3154 j = atp_readb_io(dev, c, 0x17) & 0x0f;
3155 if (j == 0x0f) {
3156 goto widep_in;
3157 }
3158 if (j == 0x0a) {
3159 goto widep_cmd;
3160 }
3161 if (j == 0x0e) {
3162 goto widep_out;
3163 }
3164 continue;
3165 widep_in:
3166 atp_writeb_io(dev, c, 0x14, 0xff);
3167 atp_writeb_io(dev, c, 0x18, 0x20);
3168 k = 0;
3169 widep_in1:
3170 j = atp_readb_io(dev, c, 0x1f);
3171 if ((j & 0x01) != 0) {
3172 mbuf[k++] = atp_readb_io(dev, c, 0x19);
3173 goto widep_in1;
3174 }
3175 if ((j & 0x80) == 0x00) {
3176 goto widep_in1;
3177 }
3178 j = atp_readb_io(dev, c, 0x17) & 0x0f;
3179 if (j == 0x0f) {
3180 goto widep_in;
3181 }
3182 if (j == 0x0a) {
3183 goto widep_cmd;
3184 }
3185 if (j == 0x0e) {
3186 goto widep_out;
3187 }
3188 continue;
3189 widep_cmd:
3190 atp_writeb_io(dev, c, 0x10, 0x30);
3191 atp_writeb_io(dev, c, 0x14, 0x00);
3192 atp_writeb_io(dev, c, 0x18, 0x08);
3193
3194 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
3195 cpu_relax();
3196
3197 j = atp_readb_io(dev, c, 0x17);
3198 if (j != 0x16) {
3199 if (j == 0x4e) {
3200 goto widep_out;
3201 }
3202 continue;
3203 }
3204 if (mbuf[0] != 0x01) {
3205 goto not_wide;
3206 }
3207 if (mbuf[1] != 0x02) {
3208 goto not_wide;
3209 }
3210 if (mbuf[2] != 0x03) {
3211 goto not_wide;
3212 }
3213 if (mbuf[3] != 0x01) {
3214 goto not_wide;
3215 }
3216 m = 1;
3217 m = m << i;
3218 dev->wide_id[c] |= m;
3219 not_wide:
3220 if ((dev->id[c][i].devtype == 0x00) || (dev->id[c][i].devtype == 0x07) || ((dev->id[c][i].devtype == 0x05) && ((n & 0x10) != 0))) {
3221 m = 1;
3222 m = m << i;
3223 if ((dev->async[c] & m) != 0) {
3224 goto set_sync;
3225 }
3226 }
3227 continue;
3228 set_sync:
3229 if (dev->sp[c][i] == 0x02) {
3230 synu[4] = 0x0c;
3231 synuw[4] = 0x0c;
3232 } else {
3233 if (dev->sp[c][i] >= 0x03) {
3234 synu[4] = 0x0a;
3235 synuw[4] = 0x0a;
3236 }
3237 }
3238 j = 0;
3239 if ((m & dev->wide_id[c]) != 0) {
3240 j |= 0x01;
3241 }
3242 atp_writeb_io(dev, c, 0x1b, j);
3243 atp_writeb_io(dev, c, 3, satn[0]);
3244 atp_writeb_io(dev, c, 4, satn[1]);
3245 atp_writeb_io(dev, c, 5, satn[2]);
3246 atp_writeb_io(dev, c, 6, satn[3]);
3247 atp_writeb_io(dev, c, 7, satn[4]);
3248 atp_writeb_io(dev, c, 8, satn[5]);
3249 atp_writeb_io(dev, c, 0x0f, 0);
3250 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
3251 atp_writeb_io(dev, c, 0x12, 0);
3252 atp_writeb_io(dev, c, 0x13, satn[6]);
3253 atp_writeb_io(dev, c, 0x14, satn[7]);
3254 atp_writeb_io(dev, c, 0x18, satn[8]);
3255
3256 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
3257 cpu_relax();
3258
3259 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
3260 continue;
3261
3262 while (atp_readb_io(dev, c, 0x17) != 0x8e)
3263 cpu_relax();
3264
3265 try_sync:
3266 j = 0;
3267 atp_writeb_io(dev, c, 0x14, 0x06);
3268 atp_writeb_io(dev, c, 0x18, 0x20);
3269
3270 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
3271 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) {
3272 if ((m & dev->wide_id[c]) != 0) {
3273 if ((m & dev->ultra_map[c]) != 0) {
3274 atp_writeb_io(dev, c, 0x19, synuw[j++]);
3275 } else {
3276 atp_writeb_io(dev, c, 0x19, synw[j++]);
3277 }
3278 } else {
3279 if ((m & dev->ultra_map[c]) != 0) {
3280 atp_writeb_io(dev, c, 0x19, synu[j++]);
3281 } else {
3282 atp_writeb_io(dev, c, 0x19, synn[j++]);
3283 }
3284 }
3285 }
3286 }
3287
3288 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00)
3289 cpu_relax();
3290
3291 j = atp_readb_io(dev, c, 0x17) & 0x0f;
3292 if (j == 0x0f) {
3293 goto phase_ins;
3294 }
3295 if (j == 0x0a) {
3296 goto phase_cmds;
3297 }
3298 if (j == 0x0e) {
3299 goto try_sync;
3300 }
3301 continue;
3302 phase_outs:
3303 atp_writeb_io(dev, c, 0x18, 0x20);
3304 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) {
3305 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0x00)
3306 atp_writeb_io(dev, c, 0x19, 0x00);
3307 cpu_relax();
3308 }
3309 j = atp_readb_io(dev, c, 0x17);
3310 if (j == 0x85) {
3311 goto tar_dcons;
3312 }
3313 j &= 0x0f;
3314 if (j == 0x0f) {
3315 goto phase_ins;
3316 }
3317 if (j == 0x0a) {
3318 goto phase_cmds;
3319 }
3320 if (j == 0x0e) {
3321 goto phase_outs;
3322 }
3323 continue;
3324 phase_ins:
3325 atp_writeb_io(dev, c, 0x14, 0x06);
3326 atp_writeb_io(dev, c, 0x18, 0x20);
3327 k = 0;
3328 phase_ins1:
3329 j = atp_readb_io(dev, c, 0x1f);
3330 if ((j & 0x01) != 0x00) {
3331 mbuf[k++] = atp_readb_io(dev, c, 0x19);
3332 goto phase_ins1;
3333 }
3334 if ((j & 0x80) == 0x00) {
3335 goto phase_ins1;
3336 }
3337
3338 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00);
3339
3340 j = atp_readb_io(dev, c, 0x17);
3341 if (j == 0x85) {
3342 goto tar_dcons;
3343 }
3344 j &= 0x0f;
3345 if (j == 0x0f) {
3346 goto phase_ins;
3347 }
3348 if (j == 0x0a) {
3349 goto phase_cmds;
3350 }
3351 if (j == 0x0e) {
3352 goto phase_outs;
3353 }
3354 continue;
3355 phase_cmds:
3356 atp_writeb_io(dev, c, 0x10, 0x30);
3357 tar_dcons:
3358 atp_writeb_io(dev, c, 0x14, 0x00);
3359 atp_writeb_io(dev, c, 0x18, 0x08);
3360
3361 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
3362 cpu_relax();
3363
3364 j = atp_readb_io(dev, c, 0x17);
3365 if (j != 0x16) {
3366 continue;
3367 }
3368 if (mbuf[0] != 0x01) {
3369 continue;
3370 }
3371 if (mbuf[1] != 0x03) {
3372 continue;
3373 }
3374 if (mbuf[4] == 0x00) {
3375 continue;
3376 }
3377 if (mbuf[3] > 0x64) {
3378 continue;
3379 }
3380 if (mbuf[4] > 0x0e) {
3381 mbuf[4] = 0x0e;
3382 }
3383 dev->id[c][i].devsp = mbuf[4];
3384 if (mbuf[3] < 0x0c) {
3385 j = 0xb0;
3386 goto set_syn_ok;
3387 }
3388 if ((mbuf[3] < 0x0d) && (rmb == 0)) {
3389 j = 0xa0;
3390 goto set_syn_ok;
3391 }
3392 if (mbuf[3] < 0x1a) {
3393 j = 0x20;
3394 goto set_syn_ok;
3395 }
3396 if (mbuf[3] < 0x33) {
3397 j = 0x40;
3398 goto set_syn_ok;
3399 }
3400 if (mbuf[3] < 0x4c) {
3401 j = 0x50;
3402 goto set_syn_ok;
3403 }
3404 j = 0x60;
3405 set_syn_ok:
3406 dev->id[c][i].devsp = (dev->id[c][i].devsp & 0x0f) | j;
3407 #ifdef ED_DBGP
3408 printk("dev->id[%2d][%2d].devsp = %2x\n",c,i,dev->id[c][i].devsp);
3409 #endif
3410 }
3411 atp_writeb_io(dev, c, 0x16, 0x80);
3412 }
3413
3414 module_init(atp870u_init);
3415 module_exit(atp870u_exit);
3416
Linux kernel - Deliverables
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