drivers/scsi/be2iscsi/be_main.h

   1 /**
   2  * Copyright (C) 2005 - 2015 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Written by: Jayamohan Kallickal (jayamohan.kallickal@avagotech.com)
  11  *
  12  * Contact Information:
  13  * linux-drivers@avagotech.com
  14  *
  15  * Emulex
  16  * 3333 Susan Street
  17  * Costa Mesa, CA 92626
  18  */
  19
  20 #ifndef _BEISCSI_MAIN_
  21 #define _BEISCSI_MAIN_
  22
  23 #include <linux/kernel.h>
  24 #include <linux/pci.h>
  25 #include <linux/if_ether.h>
  26 #include <linux/in.h>
  27 #include <linux/ctype.h>
  28 #include <linux/module.h>
  29 #include <linux/aer.h>
  30 #include <scsi/scsi.h>
  31 #include <scsi/scsi_cmnd.h>
  32 #include <scsi/scsi_device.h>
  33 #include <scsi/scsi_host.h>
  34 #include <scsi/iscsi_proto.h>
  35 #include <scsi/libiscsi.h>
  36 #include <scsi/scsi_transport_iscsi.h>
  37
  38 #define DRV_NAME                "be2iscsi"
  39 #define BUILD_STR               "11.0.0.0"
  40 #define BE_NAME                 "Emulex OneConnect" \
  41                                 "Open-iSCSI Driver version" BUILD_STR
  42 #define DRV_DESC                BE_NAME " " "Driver"
  43
  44 #define BE_VENDOR_ID            0x19A2
  45 #define ELX_VENDOR_ID           0x10DF
  46 /* DEVICE ID's for BE2 */
  47 #define BE_DEVICE_ID1           0x212
  48 #define OC_DEVICE_ID1           0x702
  49 #define OC_DEVICE_ID2           0x703
  50
  51 /* DEVICE ID's for BE3 */
  52 #define BE_DEVICE_ID2           0x222
  53 #define OC_DEVICE_ID3           0x712
  54
  55 /* DEVICE ID for SKH */
  56 #define OC_SKH_ID1              0x722
  57
  58 #define BE2_IO_DEPTH            1024
  59 #define BE2_MAX_SESSIONS        256
  60 #define BE2_CMDS_PER_CXN        128
  61 #define BE2_TMFS                16
  62 #define BE2_NOPOUT_REQ          16
  63 #define BE2_SGE                 32
  64 #define BE2_DEFPDU_HDR_SZ       64
  65 #define BE2_DEFPDU_DATA_SZ      8192
  66 #define BE2_MAX_NUM_CQ_PROC     512
  67
  68 #define MAX_CPUS                64
  69 #define BEISCSI_MAX_NUM_CPUS    7
  70
  71 #define BEISCSI_VER_STRLEN 32
  72
  73 #define BEISCSI_SGLIST_ELEMENTS 30
  74
  75 #define BEISCSI_CMD_PER_LUN     128 /* scsi_host->cmd_per_lun */
  76 #define BEISCSI_MAX_SECTORS     1024 /* scsi_host->max_sectors */
  77 #define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */
  78
  79 #define BEISCSI_MAX_CMD_LEN     16      /* scsi_host->max_cmd_len */
  80 #define BEISCSI_NUM_MAX_LUN     256     /* scsi_host->max_lun */
  81 #define BEISCSI_NUM_DEVICES_SUPPORTED   0x01
  82 #define BEISCSI_MAX_FRAGS_INIT  192
  83 #define BE_NUM_MSIX_ENTRIES     1
  84
  85 #define MPU_EP_CONTROL          0
  86 #define MPU_EP_SEMAPHORE        0xac
  87 #define BE2_SOFT_RESET          0x5c
  88 #define BE2_PCI_ONLINE0         0xb0
  89 #define BE2_PCI_ONLINE1         0xb4
  90 #define BE2_SET_RESET           0x80
  91 #define BE2_MPU_IRAM_ONLINE     0x00000080
  92
  93 #define BE_SENSE_INFO_SIZE              258
  94 #define BE_ISCSI_PDU_HEADER_SIZE        64
  95 #define BE_MIN_MEM_SIZE                 16384
  96 #define MAX_CMD_SZ                      65536
  97 #define IIOC_SCSI_DATA                  0x05    /* Write Operation */
  98
  99 #define INVALID_SESS_HANDLE     0xFFFFFFFF
 100
 101 /**
 102  * Adapter States
 103  **/
 104 #define BE_ADAPTER_LINK_UP      0x001
 105 #define BE_ADAPTER_LINK_DOWN    0x002
 106 #define BE_ADAPTER_PCI_ERR      0x004
 107 #define BE_ADAPTER_CHECK_BOOT   0x008
 108
 109
 110 #define BEISCSI_CLEAN_UNLOAD    0x01
 111 #define BEISCSI_EEH_UNLOAD      0x02
 112
 113 #define BE_GET_BOOT_RETRIES     45
 114 #define BE_GET_BOOT_TO          20
 115 /**
 116  * hardware needs the async PDU buffers to be posted in multiples of 8
 117  * So have atleast 8 of them by default
 118  */
 119
 120 #define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num)    \
 121         (phwi->phwi_ctxt->pasync_ctx[ulp_num])
 122
 123 /********* Memory BAR register ************/
 124 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET      0xfc
 125 /**
 126  * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
 127  * Disable" may still globally block interrupts in addition to individual
 128  * interrupt masks; a mechanism for the device driver to block all interrupts
 129  * atomically without having to arbitrate for the PCI Interrupt Disable bit
 130  * with the OS.
 131  */
 132 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK      (1 << 29)       /* bit 29 */
 133
 134 /********* ISR0 Register offset **********/
 135 #define CEV_ISR0_OFFSET                         0xC18
 136 #define CEV_ISR_SIZE                            4
 137
 138 /**
 139  * Macros for reading/writing a protection domain or CSR registers
 140  * in BladeEngine.
 141  */
 142
 143 #define DB_TXULP0_OFFSET 0x40
 144 #define DB_RXULP0_OFFSET 0xA0
 145 /********* Event Q door bell *************/
 146 #define DB_EQ_OFFSET                    DB_CQ_OFFSET
 147 #define DB_EQ_RING_ID_LOW_MASK          0x1FF   /* bits 0 - 8 */
 148 /* Clear the interrupt for this eq */
 149 #define DB_EQ_CLR_SHIFT                 (9)     /* bit 9 */
 150 /* Must be 1 */
 151 #define DB_EQ_EVNT_SHIFT                (10)    /* bit 10 */
 152 /* Higher Order EQ_ID bit */
 153 #define DB_EQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
 154 #define DB_EQ_HIGH_SET_SHIFT    11
 155 #define DB_EQ_HIGH_FEILD_SHIFT  9
 156 /* Number of event entries processed */
 157 #define DB_EQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 158 /* Rearm bit */
 159 #define DB_EQ_REARM_SHIFT               (29)    /* bit 29 */
 160
 161 /********* Compl Q door bell *************/
 162 #define DB_CQ_OFFSET                    0x120
 163 #define DB_CQ_RING_ID_LOW_MASK          0x3FF   /* bits 0 - 9 */
 164 /* Higher Order CQ_ID bit */
 165 #define DB_CQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
 166 #define DB_CQ_HIGH_SET_SHIFT    11
 167 #define DB_CQ_HIGH_FEILD_SHIFT  10
 168
 169 /* Number of event entries processed */
 170 #define DB_CQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 171 /* Rearm bit */
 172 #define DB_CQ_REARM_SHIFT               (29)    /* bit 29 */
 173
 174 #define GET_HWI_CONTROLLER_WS(pc)       (pc->phwi_ctrlr)
 175 #define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
 176                 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
 177 #define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
 178                 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)
 179
 180 #define PAGES_REQUIRED(x) \
 181         ((x < PAGE_SIZE) ? 1 :  ((x + PAGE_SIZE - 1) / PAGE_SIZE))
 182
 183 #define BEISCSI_MSI_NAME 20 /* size of msi_name string */
 184
 185 #define MEM_DESCR_OFFSET 8
 186 #define BEISCSI_DEFQ_HDR 1
 187 #define BEISCSI_DEFQ_DATA 0
 188 enum be_mem_enum {
 189         HWI_MEM_ADDN_CONTEXT,
 190         HWI_MEM_WRB,
 191         HWI_MEM_WRBH,
 192         HWI_MEM_SGLH,
 193         HWI_MEM_SGE,
 194         HWI_MEM_TEMPLATE_HDR_ULP0,
 195         HWI_MEM_ASYNC_HEADER_BUF_ULP0,  /* 6 */
 196         HWI_MEM_ASYNC_DATA_BUF_ULP0,
 197         HWI_MEM_ASYNC_HEADER_RING_ULP0,
 198         HWI_MEM_ASYNC_DATA_RING_ULP0,
 199         HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
 200         HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */
 201         HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
 202         HWI_MEM_TEMPLATE_HDR_ULP1,
 203         HWI_MEM_ASYNC_HEADER_BUF_ULP1,  /* 14 */
 204         HWI_MEM_ASYNC_DATA_BUF_ULP1,
 205         HWI_MEM_ASYNC_HEADER_RING_ULP1,
 206         HWI_MEM_ASYNC_DATA_RING_ULP1,
 207         HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
 208         HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */
 209         HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
 210         ISCSI_MEM_GLOBAL_HEADER,
 211         SE_MEM_MAX
 212 };
 213
 214 struct be_bus_address32 {
 215         unsigned int address_lo;
 216         unsigned int address_hi;
 217 };
 218
 219 struct be_bus_address64 {
 220         unsigned long long address;
 221 };
 222
 223 struct be_bus_address {
 224         union {
 225                 struct be_bus_address32 a32;
 226                 struct be_bus_address64 a64;
 227         } u;
 228 };
 229
 230 struct mem_array {
 231         struct be_bus_address bus_address;      /* Bus address of location */
 232         void *virtual_address;          /* virtual address to the location */
 233         unsigned int size;              /* Size required by memory block */
 234 };
 235
 236 struct be_mem_descriptor {
 237         unsigned int index;     /* Index of this memory parameter */
 238         unsigned int category;  /* type indicates cached/non-cached */
 239         unsigned int num_elements;      /* number of elements in this
 240                                          * descriptor
 241                                          */
 242         unsigned int alignment_mask;    /* Alignment mask for this block */
 243         unsigned int size_in_bytes;     /* Size required by memory block */
 244         struct mem_array *mem_array;
 245 };
 246
 247 struct sgl_handle {
 248         unsigned int sgl_index;
 249         unsigned int type;
 250         unsigned int cid;
 251         struct iscsi_task *task;
 252         struct iscsi_sge *pfrag;
 253 };
 254
 255 struct hba_parameters {
 256         unsigned int ios_per_ctrl;
 257         unsigned int cxns_per_ctrl;
 258         unsigned int asyncpdus_per_ctrl;
 259         unsigned int icds_per_ctrl;
 260         unsigned int num_sge_per_io;
 261         unsigned int defpdu_hdr_sz;
 262         unsigned int defpdu_data_sz;
 263         unsigned int num_cq_entries;
 264         unsigned int num_eq_entries;
 265         unsigned int wrbs_per_cxn;
 266         unsigned int crashmode;
 267         unsigned int hba_num;
 268
 269         unsigned int mgmt_ws_sz;
 270         unsigned int hwi_ws_sz;
 271
 272         unsigned int eto;
 273         unsigned int ldto;
 274
 275         unsigned int dbg_flags;
 276         unsigned int num_cxn;
 277
 278         unsigned int eq_timer;
 279         /**
 280          * These are calculated from other params. They're here
 281          * for debug purposes
 282          */
 283         unsigned int num_mcc_pages;
 284         unsigned int num_mcc_cq_pages;
 285         unsigned int num_cq_pages;
 286         unsigned int num_eq_pages;
 287
 288         unsigned int num_async_pdu_buf_pages;
 289         unsigned int num_async_pdu_buf_sgl_pages;
 290         unsigned int num_async_pdu_buf_cq_pages;
 291
 292         unsigned int num_async_pdu_hdr_pages;
 293         unsigned int num_async_pdu_hdr_sgl_pages;
 294         unsigned int num_async_pdu_hdr_cq_pages;
 295
 296         unsigned int num_sge;
 297 };
 298
 299 struct invalidate_command_table {
 300         unsigned short icd;
 301         unsigned short cid;
 302 } __packed;
 303
 304 #define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
 305         (phwi_ctrlr->wrb_context[cri].ulp_num)
 306 struct hwi_wrb_context {
 307         spinlock_t wrb_lock;
 308         struct list_head wrb_handle_list;
 309         struct list_head wrb_handle_drvr_list;
 310         struct wrb_handle **pwrb_handle_base;
 311         struct wrb_handle **pwrb_handle_basestd;
 312         struct iscsi_wrb *plast_wrb;
 313         unsigned short alloc_index;
 314         unsigned short free_index;
 315         unsigned short wrb_handles_available;
 316         unsigned short cid;
 317         uint8_t ulp_num;        /* ULP to which CID binded */
 318         uint16_t register_set;
 319         uint16_t doorbell_format;
 320         uint32_t doorbell_offset;
 321 };
 322
 323 struct ulp_cid_info {
 324         unsigned short *cid_array;
 325         unsigned short avlbl_cids;
 326         unsigned short cid_alloc;
 327         unsigned short cid_free;
 328 };
 329
 330 #include "be.h"
 331 #define chip_be2(phba)      (phba->generation == BE_GEN2)
 332 #define chip_be3_r(phba)    (phba->generation == BE_GEN3)
 333 #define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
 334
 335 #define BEISCSI_ULP0    0
 336 #define BEISCSI_ULP1    1
 337 #define BEISCSI_ULP_COUNT   2
 338 #define BEISCSI_ULP0_LOADED 0x01
 339 #define BEISCSI_ULP1_LOADED 0x02
 340
 341 #define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) \
 342         (((struct ulp_cid_info *)phba->cid_array_info[ulp_num])->avlbl_cids)
 343 #define BEISCSI_ULP0_AVLBL_CID(phba) \
 344         BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP0)
 345 #define BEISCSI_ULP1_AVLBL_CID(phba) \
 346         BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP1)
 347
 348 struct beiscsi_hba {
 349         struct hba_parameters params;
 350         struct hwi_controller *phwi_ctrlr;
 351         unsigned int mem_req[SE_MEM_MAX];
 352         /* PCI BAR mapped addresses */
 353         u8 __iomem *csr_va;     /* CSR */
 354         u8 __iomem *db_va;      /* Door  Bell  */
 355         u8 __iomem *pci_va;     /* PCI Config */
 356         struct be_bus_address csr_pa;   /* CSR */
 357         struct be_bus_address db_pa;    /* CSR */
 358         struct be_bus_address pci_pa;   /* CSR */
 359         /* PCI representation of our HBA */
 360         struct pci_dev *pcidev;
 361         unsigned short asic_revision;
 362         unsigned int num_cpus;
 363         unsigned int nxt_cqid;
 364         struct msix_entry msix_entries[MAX_CPUS];
 365         char *msi_name[MAX_CPUS];
 366         bool msix_enabled;
 367         struct be_mem_descriptor *init_mem;
 368
 369         unsigned short io_sgl_alloc_index;
 370         unsigned short io_sgl_free_index;
 371         unsigned short io_sgl_hndl_avbl;
 372         struct sgl_handle **io_sgl_hndl_base;
 373         struct sgl_handle **sgl_hndl_array;
 374
 375         unsigned short eh_sgl_alloc_index;
 376         unsigned short eh_sgl_free_index;
 377         unsigned short eh_sgl_hndl_avbl;
 378         struct sgl_handle **eh_sgl_hndl_base;
 379         spinlock_t io_sgl_lock;
 380         spinlock_t mgmt_sgl_lock;
 381         spinlock_t isr_lock;
 382         spinlock_t async_pdu_lock;
 383         unsigned int age;
 384         struct list_head hba_queue;
 385 #define BE_MAX_SESSION 2048
 386 #define BE_SET_CID_TO_CRI(cri_index, cid) \
 387                           (phba->cid_to_cri_map[cid] = cri_index)
 388 #define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
 389         unsigned short cid_to_cri_map[BE_MAX_SESSION];
 390         struct ulp_cid_info *cid_array_info[BEISCSI_ULP_COUNT];
 391         struct iscsi_endpoint **ep_array;
 392         struct beiscsi_conn **conn_table;
 393         struct iscsi_boot_kset *boot_kset;
 394         struct Scsi_Host *shost;
 395         struct iscsi_iface *ipv4_iface;
 396         struct iscsi_iface *ipv6_iface;
 397         struct {
 398                 /**
 399                  * group together since they are used most frequently
 400                  * for cid to cri conversion
 401                  */
 402 #define BEISCSI_PHYS_PORT_MAX   4
 403                 unsigned int phys_port;
 404                 /* valid values of phys_port id are 0, 1, 2, 3 */
 405                 unsigned int eqid_count;
 406                 unsigned int cqid_count;
 407                 unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT];
 408 #define BEISCSI_GET_CID_COUNT(phba, ulp_num) \
 409                 (phba->fw_config.iscsi_cid_count[ulp_num])
 410                 unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT];
 411                 unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT];
 412                 unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT];
 413                 unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT];
 414                 unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT];
 415
 416                 unsigned short iscsi_features;
 417                 uint16_t dual_ulp_aware;
 418                 unsigned long ulp_supported;
 419         } fw_config;
 420
 421         unsigned int state;
 422         u8 optic_state;
 423         int get_boot;
 424         bool fw_timeout;
 425         bool ue_detected;
 426         struct delayed_work beiscsi_hw_check_task;
 427
 428         bool mac_addr_set;
 429         u8 mac_address[ETH_ALEN];
 430         u8 port_name;
 431         u8 port_speed;
 432         char fw_ver_str[BEISCSI_VER_STRLEN];
 433         char wq_name[20];
 434         struct workqueue_struct *wq;    /* The actuak work queue */
 435         struct be_ctrl_info ctrl;
 436         unsigned int generation;
 437         unsigned int interface_handle;
 438         struct mgmt_session_info boot_sess;
 439         struct invalidate_command_table inv_tbl[128];
 440
 441         struct be_aic_obj aic_obj[MAX_CPUS];
 442         unsigned int attr_log_enable;
 443         int (*iotask_fn)(struct iscsi_task *,
 444                         struct scatterlist *sg,
 445                         uint32_t num_sg, uint32_t xferlen,
 446                         uint32_t writedir);
 447 };
 448
 449 struct beiscsi_session {
 450         struct pci_pool *bhs_pool;
 451 };
 452
 453 /**
 454  * struct beiscsi_conn - iscsi connection structure
 455  */
 456 struct beiscsi_conn {
 457         struct iscsi_conn *conn;
 458         struct beiscsi_hba *phba;
 459         u32 exp_statsn;
 460         u32 doorbell_offset;
 461         u32 beiscsi_conn_cid;
 462         struct beiscsi_endpoint *ep;
 463         unsigned short login_in_progress;
 464         struct wrb_handle *plogin_wrb_handle;
 465         struct sgl_handle *plogin_sgl_handle;
 466         struct beiscsi_session *beiscsi_sess;
 467         struct iscsi_task *task;
 468 };
 469
 470 /* This structure is used by the chip */
 471 struct pdu_data_out {
 472         u32 dw[12];
 473 };
 474 /**
 475  * Pseudo amap definition in which each bit of the actual structure is defined
 476  * as a byte: used to calculate offset/shift/mask of each field
 477  */
 478 struct amap_pdu_data_out {
 479         u8 opcode[6];           /* opcode */
 480         u8 rsvd0[2];            /* should be 0 */
 481         u8 rsvd1[7];
 482         u8 final_bit;           /* F bit */
 483         u8 rsvd2[16];
 484         u8 ahs_length[8];       /* no AHS */
 485         u8 data_len_hi[8];
 486         u8 data_len_lo[16];     /* DataSegmentLength */
 487         u8 lun[64];
 488         u8 itt[32];             /* ITT; initiator task tag */
 489         u8 ttt[32];             /* TTT; valid for R2T or 0xffffffff */
 490         u8 rsvd3[32];
 491         u8 exp_stat_sn[32];
 492         u8 rsvd4[32];
 493         u8 data_sn[32];
 494         u8 buffer_offset[32];
 495         u8 rsvd5[32];
 496 };
 497
 498 struct be_cmd_bhs {
 499         struct iscsi_scsi_req iscsi_hdr;
 500         unsigned char pad1[16];
 501         struct pdu_data_out iscsi_data_pdu;
 502         unsigned char pad2[BE_SENSE_INFO_SIZE -
 503                         sizeof(struct pdu_data_out)];
 504 };
 505
 506 struct beiscsi_io_task {
 507         struct wrb_handle *pwrb_handle;
 508         struct sgl_handle *psgl_handle;
 509         struct beiscsi_conn *conn;
 510         struct scsi_cmnd *scsi_cmnd;
 511         struct hwi_wrb_context *pwrb_context;
 512         unsigned int cmd_sn;
 513         unsigned int flags;
 514         unsigned short cid;
 515         unsigned short header_len;
 516         itt_t libiscsi_itt;
 517         struct be_cmd_bhs *cmd_bhs;
 518         struct be_bus_address bhs_pa;
 519         unsigned short bhs_len;
 520         dma_addr_t mtask_addr;
 521         uint32_t mtask_data_count;
 522         uint8_t wrb_type;
 523 };
 524
 525 struct be_nonio_bhs {
 526         struct iscsi_hdr iscsi_hdr;
 527         unsigned char pad1[16];
 528         struct pdu_data_out iscsi_data_pdu;
 529         unsigned char pad2[BE_SENSE_INFO_SIZE -
 530                         sizeof(struct pdu_data_out)];
 531 };
 532
 533 struct be_status_bhs {
 534         struct iscsi_scsi_req iscsi_hdr;
 535         unsigned char pad1[16];
 536         /**
 537          * The plus 2 below is to hold the sense info length that gets
 538          * DMA'ed by RxULP
 539          */
 540         unsigned char sense_info[BE_SENSE_INFO_SIZE];
 541 };
 542
 543 struct iscsi_sge {
 544         u32 dw[4];
 545 };
 546
 547 /**
 548  * Pseudo amap definition in which each bit of the actual structure is defined
 549  * as a byte: used to calculate offset/shift/mask of each field
 550  */
 551 struct amap_iscsi_sge {
 552         u8 addr_hi[32];
 553         u8 addr_lo[32];
 554         u8 sge_offset[22];      /* DWORD 2 */
 555         u8 rsvd0[9];            /* DWORD 2 */
 556         u8 last_sge;            /* DWORD 2 */
 557         u8 len[17];             /* DWORD 3 */
 558         u8 rsvd1[15];           /* DWORD 3 */
 559 };
 560
 561 struct beiscsi_offload_params {
 562         u32 dw[6];
 563 };
 564
 565 #define OFFLD_PARAMS_ERL        0x00000003
 566 #define OFFLD_PARAMS_DDE        0x00000004
 567 #define OFFLD_PARAMS_HDE        0x00000008
 568 #define OFFLD_PARAMS_IR2T       0x00000010
 569 #define OFFLD_PARAMS_IMD        0x00000020
 570 #define OFFLD_PARAMS_DATA_SEQ_INORDER   0x00000040
 571 #define OFFLD_PARAMS_PDU_SEQ_INORDER    0x00000080
 572 #define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
 573
 574 /**
 575  * Pseudo amap definition in which each bit of the actual structure is defined
 576  * as a byte: used to calculate offset/shift/mask of each field
 577  */
 578 struct amap_beiscsi_offload_params {
 579         u8 max_burst_length[32];
 580         u8 max_send_data_segment_length[32];
 581         u8 first_burst_length[32];
 582         u8 erl[2];
 583         u8 dde[1];
 584         u8 hde[1];
 585         u8 ir2t[1];
 586         u8 imd[1];
 587         u8 data_seq_inorder[1];
 588         u8 pdu_seq_inorder[1];
 589         u8 max_r2t[16];
 590         u8 pad[8];
 591         u8 exp_statsn[32];
 592         u8 max_recv_data_segment_length[32];
 593 };
 594
 595 /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
 596                 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
 597
 598 struct async_pdu_handle {
 599         struct list_head link;
 600         struct be_bus_address pa;
 601         void *pbuffer;
 602         unsigned int consumed;
 603         unsigned char index;
 604         unsigned char is_header;
 605         unsigned short cri;
 606         unsigned long buffer_len;
 607 };
 608
 609 struct hwi_async_entry {
 610         struct {
 611                 unsigned char hdr_received;
 612                 unsigned char hdr_len;
 613                 unsigned short bytes_received;
 614                 unsigned int bytes_needed;
 615                 struct list_head list;
 616         } wait_queue;
 617
 618         struct list_head header_busy_list;
 619         struct list_head data_busy_list;
 620 };
 621
 622 struct hwi_async_pdu_context {
 623         struct {
 624                 struct be_bus_address pa_base;
 625                 void *va_base;
 626                 void *ring_base;
 627                 struct async_pdu_handle *handle_base;
 628
 629                 unsigned int host_write_ptr;
 630                 unsigned int ep_read_ptr;
 631                 unsigned int writables;
 632
 633                 unsigned int free_entries;
 634                 unsigned int busy_entries;
 635
 636                 struct list_head free_list;
 637         } async_header;
 638
 639         struct {
 640                 struct be_bus_address pa_base;
 641                 void *va_base;
 642                 void *ring_base;
 643                 struct async_pdu_handle *handle_base;
 644
 645                 unsigned int host_write_ptr;
 646                 unsigned int ep_read_ptr;
 647                 unsigned int writables;
 648
 649                 unsigned int free_entries;
 650                 unsigned int busy_entries;
 651                 struct list_head free_list;
 652         } async_data;
 653
 654         unsigned int buffer_size;
 655         unsigned int num_entries;
 656 #define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid])
 657         unsigned short cid_to_async_cri_map[BE_MAX_SESSION];
 658         /**
 659          * This is a varying size list! Do not add anything
 660          * after this entry!!
 661          */
 662         struct hwi_async_entry *async_entry;
 663 };
 664
 665 #define PDUCQE_CODE_MASK        0x0000003F
 666 #define PDUCQE_DPL_MASK         0xFFFF0000
 667 #define PDUCQE_INDEX_MASK       0x0000FFFF
 668
 669 struct i_t_dpdu_cqe {
 670         u32 dw[4];
 671 } __packed;
 672
 673 /**
 674  * Pseudo amap definition in which each bit of the actual structure is defined
 675  * as a byte: used to calculate offset/shift/mask of each field
 676  */
 677 struct amap_i_t_dpdu_cqe {
 678         u8 db_addr_hi[32];
 679         u8 db_addr_lo[32];
 680         u8 code[6];
 681         u8 cid[10];
 682         u8 dpl[16];
 683         u8 index[16];
 684         u8 num_cons[10];
 685         u8 rsvd0[4];
 686         u8 final;
 687         u8 valid;
 688 } __packed;
 689
 690 struct amap_i_t_dpdu_cqe_v2 {
 691         u8 db_addr_hi[32];  /* DWORD 0 */
 692         u8 db_addr_lo[32];  /* DWORD 1 */
 693         u8 code[6]; /* DWORD 2 */
 694         u8 num_cons; /* DWORD 2*/
 695         u8 rsvd0[8]; /* DWORD 2 */
 696         u8 dpl[17]; /* DWORD 2 */
 697         u8 index[16]; /* DWORD 3 */
 698         u8 cid[13]; /* DWORD 3 */
 699         u8 rsvd1; /* DWORD 3 */
 700         u8 final; /* DWORD 3 */
 701         u8 valid; /* DWORD 3 */
 702 } __packed;
 703
 704 #define CQE_VALID_MASK  0x80000000
 705 #define CQE_CODE_MASK   0x0000003F
 706 #define CQE_CID_MASK    0x0000FFC0
 707
 708 #define EQE_VALID_MASK          0x00000001
 709 #define EQE_MAJORCODE_MASK      0x0000000E
 710 #define EQE_RESID_MASK          0xFFFF0000
 711
 712 struct be_eq_entry {
 713         u32 dw[1];
 714 } __packed;
 715
 716 /**
 717  * Pseudo amap definition in which each bit of the actual structure is defined
 718  * as a byte: used to calculate offset/shift/mask of each field
 719  */
 720 struct amap_eq_entry {
 721         u8 valid;               /* DWORD 0 */
 722         u8 major_code[3];       /* DWORD 0 */
 723         u8 minor_code[12];      /* DWORD 0 */
 724         u8 resource_id[16];     /* DWORD 0 */
 725
 726 } __packed;
 727
 728 struct cq_db {
 729         u32 dw[1];
 730 } __packed;
 731
 732 /**
 733  * Pseudo amap definition in which each bit of the actual structure is defined
 734  * as a byte: used to calculate offset/shift/mask of each field
 735  */
 736 struct amap_cq_db {
 737         u8 qid[10];
 738         u8 event[1];
 739         u8 rsvd0[5];
 740         u8 num_popped[13];
 741         u8 rearm[1];
 742         u8 rsvd1[2];
 743 } __packed;
 744
 745 void beiscsi_process_eq(struct beiscsi_hba *phba);
 746
 747 struct iscsi_wrb {
 748         u32 dw[16];
 749 } __packed;
 750
 751 #define WRB_TYPE_MASK 0xF0000000
 752 #define SKH_WRB_TYPE_OFFSET 27
 753 #define BE_WRB_TYPE_OFFSET  28
 754
 755 #define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
 756                 (pwrb->dw[0] |= (wrb_type << type_offset))
 757
 758 /**
 759  * Pseudo amap definition in which each bit of the actual structure is defined
 760  * as a byte: used to calculate offset/shift/mask of each field
 761  */
 762 struct amap_iscsi_wrb {
 763         u8 lun[14];             /* DWORD 0 */
 764         u8 lt;                  /* DWORD 0 */
 765         u8 invld;               /* DWORD 0 */
 766         u8 wrb_idx[8];          /* DWORD 0 */
 767         u8 dsp;                 /* DWORD 0 */
 768         u8 dmsg;                /* DWORD 0 */
 769         u8 undr_run;            /* DWORD 0 */
 770         u8 over_run;            /* DWORD 0 */
 771         u8 type[4];             /* DWORD 0 */
 772         u8 ptr2nextwrb[8];      /* DWORD 1 */
 773         u8 r2t_exp_dtl[24];     /* DWORD 1 */
 774         u8 sgl_icd_idx[12];     /* DWORD 2 */
 775         u8 rsvd0[20];           /* DWORD 2 */
 776         u8 exp_data_sn[32];     /* DWORD 3 */
 777         u8 iscsi_bhs_addr_hi[32];       /* DWORD 4 */
 778         u8 iscsi_bhs_addr_lo[32];       /* DWORD 5 */
 779         u8 cmdsn_itt[32];       /* DWORD 6 */
 780         u8 dif_ref_tag[32];     /* DWORD 7 */
 781         u8 sge0_addr_hi[32];    /* DWORD 8 */
 782         u8 sge0_addr_lo[32];    /* DWORD 9  */
 783         u8 sge0_offset[22];     /* DWORD 10 */
 784         u8 pbs;                 /* DWORD 10 */
 785         u8 dif_mode[2];         /* DWORD 10 */
 786         u8 rsvd1[6];            /* DWORD 10 */
 787         u8 sge0_last;           /* DWORD 10 */
 788         u8 sge0_len[17];        /* DWORD 11 */
 789         u8 dif_meta_tag[14];    /* DWORD 11 */
 790         u8 sge0_in_ddr;         /* DWORD 11 */
 791         u8 sge1_addr_hi[32];    /* DWORD 12 */
 792         u8 sge1_addr_lo[32];    /* DWORD 13 */
 793         u8 sge1_r2t_offset[22]; /* DWORD 14 */
 794         u8 rsvd2[9];            /* DWORD 14 */
 795         u8 sge1_last;           /* DWORD 14 */
 796         u8 sge1_len[17];        /* DWORD 15 */
 797         u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
 798         u8 rsvd3[2];            /* DWORD 15 */
 799         u8 sge1_in_ddr;         /* DWORD 15 */
 800
 801 } __packed;
 802
 803 struct amap_iscsi_wrb_v2 {
 804         u8 r2t_exp_dtl[25]; /* DWORD 0 */
 805         u8 rsvd0[2];    /* DWORD 0*/
 806         u8 type[5];     /* DWORD 0 */
 807         u8 ptr2nextwrb[8];  /* DWORD 1 */
 808         u8 wrb_idx[8];      /* DWORD 1 */
 809         u8 lun[16];     /* DWORD 1 */
 810         u8 sgl_idx[16]; /* DWORD 2 */
 811         u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
 812         u8 exp_data_sn[32]; /* DWORD 3 */
 813         u8 iscsi_bhs_addr_hi[32];   /* DWORD 4 */
 814         u8 iscsi_bhs_addr_lo[32];   /* DWORD 5 */
 815         u8 cq_id[16];   /* DWORD 6 */
 816         u8 rsvd1[16];   /* DWORD 6 */
 817         u8 cmdsn_itt[32];   /* DWORD 7 */
 818         u8 sge0_addr_hi[32];    /* DWORD 8 */
 819         u8 sge0_addr_lo[32];    /* DWORD 9 */
 820         u8 sge0_offset[24]; /* DWORD 10 */
 821         u8 rsvd2[7];    /* DWORD 10 */
 822         u8 sge0_last;   /* DWORD 10 */
 823         u8 sge0_len[17];    /* DWORD 11 */
 824         u8 rsvd3[7];    /* DWORD 11 */
 825         u8 diff_enbl;   /* DWORD 11 */
 826         u8 u_run;       /* DWORD 11 */
 827         u8 o_run;       /* DWORD 11 */
 828         u8 invalid;     /* DWORD 11 */
 829         u8 dsp;         /* DWORD 11 */
 830         u8 dmsg;        /* DWORD 11 */
 831         u8 rsvd4;       /* DWORD 11 */
 832         u8 lt;          /* DWORD 11 */
 833         u8 sge1_addr_hi[32];    /* DWORD 12 */
 834         u8 sge1_addr_lo[32];    /* DWORD 13 */
 835         u8 sge1_r2t_offset[24]; /* DWORD 14 */
 836         u8 rsvd5[7];    /* DWORD 14 */
 837         u8 sge1_last;   /* DWORD 14 */
 838         u8 sge1_len[17];    /* DWORD 15 */
 839         u8 rsvd6[15];   /* DWORD 15 */
 840 } __packed;
 841
 842
 843 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
 844                                      struct hwi_wrb_context **pcontext);
 845 void
 846 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
 847
 848 void beiscsi_process_all_cqs(struct work_struct *work);
 849 void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
 850                                      struct iscsi_task *task);
 851
 852 void hwi_ring_cq_db(struct beiscsi_hba *phba,
 853                      unsigned int id, unsigned int num_processed,
 854                      unsigned char rearm);
 855
 856 unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget);
 857 void beiscsi_process_mcc_cq(struct beiscsi_hba *phba);
 858
 859 static inline bool beiscsi_error(struct beiscsi_hba *phba)
 860 {
 861         return phba->ue_detected || phba->fw_timeout;
 862 }
 863
 864 struct pdu_nop_out {
 865         u32 dw[12];
 866 };
 867
 868 /**
 869  * Pseudo amap definition in which each bit of the actual structure is defined
 870  * as a byte: used to calculate offset/shift/mask of each field
 871  */
 872 struct amap_pdu_nop_out {
 873         u8 opcode[6];           /* opcode 0x00 */
 874         u8 i_bit;               /* I Bit */
 875         u8 x_bit;               /* reserved; should be 0 */
 876         u8 fp_bit_filler1[7];
 877         u8 f_bit;               /* always 1 */
 878         u8 reserved1[16];
 879         u8 ahs_length[8];       /* no AHS */
 880         u8 data_len_hi[8];
 881         u8 data_len_lo[16];     /* DataSegmentLength */
 882         u8 lun[64];
 883         u8 itt[32];             /* initiator id for ping or 0xffffffff */
 884         u8 ttt[32];             /* target id for ping or 0xffffffff */
 885         u8 cmd_sn[32];
 886         u8 exp_stat_sn[32];
 887         u8 reserved5[128];
 888 };
 889
 890 #define PDUBASE_OPCODE_MASK     0x0000003F
 891 #define PDUBASE_DATALENHI_MASK  0x0000FF00
 892 #define PDUBASE_DATALENLO_MASK  0xFFFF0000
 893
 894 struct pdu_base {
 895         u32 dw[16];
 896 } __packed;
 897
 898 /**
 899  * Pseudo amap definition in which each bit of the actual structure is defined
 900  * as a byte: used to calculate offset/shift/mask of each field
 901  */
 902 struct amap_pdu_base {
 903         u8 opcode[6];
 904         u8 i_bit;               /* immediate bit */
 905         u8 x_bit;               /* reserved, always 0 */
 906         u8 reserved1[24];       /* opcode-specific fields */
 907         u8 ahs_length[8];       /* length units is 4 byte words */
 908         u8 data_len_hi[8];
 909         u8 data_len_lo[16];     /* DatasegmentLength */
 910         u8 lun[64];             /* lun or opcode-specific fields */
 911         u8 itt[32];             /* initiator task tag */
 912         u8 reserved4[224];
 913 };
 914
 915 struct iscsi_target_context_update_wrb {
 916         u32 dw[16];
 917 } __packed;
 918
 919 /**
 920  * Pseudo amap definition in which each bit of the actual structure is defined
 921  * as a byte: used to calculate offset/shift/mask of each field
 922  */
 923 #define BE_TGT_CTX_UPDT_CMD 0x07
 924 struct amap_iscsi_target_context_update_wrb {
 925         u8 lun[14];             /* DWORD 0 */
 926         u8 lt;                  /* DWORD 0 */
 927         u8 invld;               /* DWORD 0 */
 928         u8 wrb_idx[8];          /* DWORD 0 */
 929         u8 dsp;                 /* DWORD 0 */
 930         u8 dmsg;                /* DWORD 0 */
 931         u8 undr_run;            /* DWORD 0 */
 932         u8 over_run;            /* DWORD 0 */
 933         u8 type[4];             /* DWORD 0 */
 934         u8 ptr2nextwrb[8];      /* DWORD 1 */
 935         u8 max_burst_length[19];        /* DWORD 1 */
 936         u8 rsvd0[5];            /* DWORD 1 */
 937         u8 rsvd1[15];           /* DWORD 2 */
 938         u8 max_send_data_segment_length[17];    /* DWORD 2 */
 939         u8 first_burst_length[14];      /* DWORD 3 */
 940         u8 rsvd2[2];            /* DWORD 3 */
 941         u8 tx_wrbindex_drv_msg[8];      /* DWORD 3 */
 942         u8 rsvd3[5];            /* DWORD 3 */
 943         u8 session_state[3];    /* DWORD 3 */
 944         u8 rsvd4[16];           /* DWORD 4 */
 945         u8 tx_jumbo;            /* DWORD 4 */
 946         u8 hde;                 /* DWORD 4 */
 947         u8 dde;                 /* DWORD 4 */
 948         u8 erl[2];              /* DWORD 4 */
 949         u8 domain_id[5];                /* DWORD 4 */
 950         u8 mode;                /* DWORD 4 */
 951         u8 imd;                 /* DWORD 4 */
 952         u8 ir2t;                /* DWORD 4 */
 953         u8 notpredblq[2];       /* DWORD 4 */
 954         u8 compltonack;         /* DWORD 4 */
 955         u8 stat_sn[32];         /* DWORD 5 */
 956         u8 pad_buffer_addr_hi[32];      /* DWORD 6 */
 957         u8 pad_buffer_addr_lo[32];      /* DWORD 7 */
 958         u8 pad_addr_hi[32];     /* DWORD 8 */
 959         u8 pad_addr_lo[32];     /* DWORD 9 */
 960         u8 rsvd5[32];           /* DWORD 10 */
 961         u8 rsvd6[32];           /* DWORD 11 */
 962         u8 rsvd7[32];           /* DWORD 12 */
 963         u8 rsvd8[32];           /* DWORD 13 */
 964         u8 rsvd9[32];           /* DWORD 14 */
 965         u8 rsvd10[32];          /* DWORD 15 */
 966
 967 } __packed;
 968
 969 #define BEISCSI_MAX_RECV_DATASEG_LEN    (64 * 1024)
 970 #define BEISCSI_MAX_CXNS    1
 971 struct amap_iscsi_target_context_update_wrb_v2 {
 972         u8 max_burst_length[24];    /* DWORD 0 */
 973         u8 rsvd0[3];    /* DWORD 0 */
 974         u8 type[5];     /* DWORD 0 */
 975         u8 ptr2nextwrb[8];  /* DWORD 1 */
 976         u8 wrb_idx[8];      /* DWORD 1 */
 977         u8 rsvd1[16];       /* DWORD 1 */
 978         u8 max_send_data_segment_length[24];    /* DWORD 2 */
 979         u8 rsvd2[8];    /* DWORD 2 */
 980         u8 first_burst_length[24]; /* DWORD 3 */
 981         u8 rsvd3[8]; /* DOWRD 3 */
 982         u8 max_r2t[16]; /* DWORD 4 */
 983         u8 rsvd4;       /* DWORD 4 */
 984         u8 hde;         /* DWORD 4 */
 985         u8 dde;         /* DWORD 4 */
 986         u8 erl[2];      /* DWORD 4 */
 987         u8 rsvd5[6];    /* DWORD 4 */
 988         u8 imd;         /* DWORD 4 */
 989         u8 ir2t;        /* DWORD 4 */
 990         u8 rsvd6[3];    /* DWORD 4 */
 991         u8 stat_sn[32];     /* DWORD 5 */
 992         u8 rsvd7[32];   /* DWORD 6 */
 993         u8 rsvd8[32];   /* DWORD 7 */
 994         u8 max_recv_dataseg_len[24];    /* DWORD 8 */
 995         u8 rsvd9[8]; /* DWORD 8 */
 996         u8 rsvd10[32];   /* DWORD 9 */
 997         u8 rsvd11[32];   /* DWORD 10 */
 998         u8 max_cxns[16]; /* DWORD 11 */
 999         u8 rsvd12[11]; /* DWORD  11*/
1000         u8 invld; /* DWORD 11 */
1001         u8 rsvd13;/* DWORD 11*/
1002         u8 dmsg; /* DWORD 11 */
1003         u8 data_seq_inorder; /* DWORD 11 */
1004         u8 pdu_seq_inorder; /* DWORD 11 */
1005         u8 rsvd14[32]; /*DWORD 12 */
1006         u8 rsvd15[32]; /* DWORD 13 */
1007         u8 rsvd16[32]; /* DWORD 14 */
1008         u8 rsvd17[32]; /* DWORD 15 */
1009 } __packed;
1010
1011
1012 struct be_ring {
1013         u32 pages;              /* queue size in pages */
1014         u32 id;                 /* queue id assigned by beklib */
1015         u32 num;                /* number of elements in queue */
1016         u32 cidx;               /* consumer index */
1017         u32 pidx;               /* producer index -- not used by most rings */
1018         u32 item_size;          /* size in bytes of one object */
1019         u8 ulp_num;     /* ULP to which CID binded */
1020         u16 register_set;
1021         u16 doorbell_format;
1022         u32 doorbell_offset;
1023
1024         void *va;               /* The virtual address of the ring.  This
1025                                  * should be last to allow 32 & 64 bit debugger
1026                                  * extensions to work.
1027                                  */
1028 };
1029
1030 struct hwi_controller {
1031         struct list_head io_sgl_list;
1032         struct list_head eh_sgl_list;
1033         struct sgl_handle *psgl_handle_base;
1034         unsigned int wrb_mem_index;
1035
1036         struct hwi_wrb_context *wrb_context;
1037         struct mcc_wrb *pmcc_wrb_base;
1038         struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
1039         struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
1040         struct hwi_context_memory *phwi_ctxt;
1041 };
1042
1043 enum hwh_type_enum {
1044         HWH_TYPE_IO = 1,
1045         HWH_TYPE_LOGOUT = 2,
1046         HWH_TYPE_TMF = 3,
1047         HWH_TYPE_NOP = 4,
1048         HWH_TYPE_IO_RD = 5,
1049         HWH_TYPE_LOGIN = 11,
1050         HWH_TYPE_INVALID = 0xFFFFFFFF
1051 };
1052
1053 struct wrb_handle {
1054         enum hwh_type_enum type;
1055         unsigned short wrb_index;
1056
1057         struct iscsi_task *pio_handle;
1058         struct iscsi_wrb *pwrb;
1059 };
1060
1061 struct hwi_context_memory {
1062         /* Adaptive interrupt coalescing (AIC) info */
1063         u16 min_eqd;            /* in usecs */
1064         u16 max_eqd;            /* in usecs */
1065         u16 cur_eqd;            /* in usecs */
1066         struct be_eq_obj be_eq[MAX_CPUS];
1067         struct be_queue_info be_cq[MAX_CPUS - 1];
1068
1069         struct be_queue_info *be_wrbq;
1070         struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT];
1071         struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT];
1072         struct hwi_async_pdu_context *pasync_ctx[BEISCSI_ULP_COUNT];
1073 };
1074
1075 /* Logging related definitions */
1076 #define BEISCSI_LOG_INIT        0x0001  /* Initialization events */
1077 #define BEISCSI_LOG_MBOX        0x0002  /* Mailbox Events */
1078 #define BEISCSI_LOG_MISC        0x0004  /* Miscllaneous Events */
1079 #define BEISCSI_LOG_EH          0x0008  /* Error Handler */
1080 #define BEISCSI_LOG_IO          0x0010  /* IO Code Path */
1081 #define BEISCSI_LOG_CONFIG      0x0020  /* CONFIG Code Path */
1082 #define BEISCSI_LOG_ISCSI       0x0040  /* SCSI/iSCSI Protocol related Logs */
1083
1084 #define __beiscsi_log(phba, level, fmt, arg...) \
1085         shost_printk(level, phba->shost, fmt, __LINE__, ##arg)
1086
1087 #define beiscsi_log(phba, level, mask, fmt, arg...) \
1088 do { \
1089         uint32_t log_value = phba->attr_log_enable; \
1090                 if (((mask) & log_value) || (level[1] <= '3')) \
1091                         __beiscsi_log(phba, level, fmt, ##arg); \
1092 } while (0);
1093
1094 #endif