2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
24 #include <scsi/scsicam.h>
31 struct access_method
{
32 void (*submit_command
)(struct ctlr_info
*h
,
33 struct CommandList
*c
);
34 void (*set_intr_mask
)(struct ctlr_info
*h
, unsigned long val
);
35 unsigned long (*fifo_full
)(struct ctlr_info
*h
);
36 bool (*intr_pending
)(struct ctlr_info
*h
);
37 unsigned long (*command_completed
)(struct ctlr_info
*h
);
40 struct hpsa_scsi_dev_t
{
42 int bus
, target
, lun
; /* as presented to the OS */
43 unsigned char scsi3addr
[8]; /* as presented to the HW */
44 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
45 unsigned char device_id
[16]; /* from inquiry pg. 0x83 */
46 unsigned char vendor
[8]; /* bytes 8-15 of inquiry data */
47 unsigned char model
[16]; /* bytes 16-31 of inquiry data */
48 unsigned char raid_level
; /* from inquiry page 0xC1 */
59 int nr_cmds
; /* Number of commands allowed on this controller */
60 struct CfgTable __iomem
*cfgtable
;
61 int interrupts_enabled
;
64 int commands_outstanding
;
65 int max_outstanding
; /* Debug */
66 int usage_count
; /* number of opens all all minor devices */
67 # define PERF_MODE_INT 0
68 # define DOORBELL_INT 1
69 # define SIMPLE_MODE_INT 2
70 # define MEMQ_MODE_INT 3
72 unsigned int msix_vector
;
73 unsigned int msi_vector
;
74 int intr_mode
; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
75 struct access_method access
;
77 /* queue and queue Info */
78 struct list_head reqQ
;
79 struct list_head cmpQ
;
81 unsigned int maxQsinceinit
;
85 u8 max_cmd_sg_entries
;
87 struct SGDescriptor
**cmd_sg_list
;
89 /* pointers to command and error info pool */
90 struct CommandList
*cmd_pool
;
91 dma_addr_t cmd_pool_dhandle
;
92 struct ErrorInfo
*errinfo_pool
;
93 dma_addr_t errinfo_pool_dhandle
;
94 unsigned long *cmd_pool_bits
;
99 wait_queue_head_t scan_wait_queue
;
101 struct Scsi_Host
*scsi_host
;
102 spinlock_t devlock
; /* to protect hba[ctlr]->dev[]; */
103 int ndevices
; /* number of used elements in .dev[] array. */
104 struct hpsa_scsi_dev_t
*dev
[HPSA_MAX_DEVICES
];
106 * Performant mode tables.
110 struct TransTable_struct
*transtable
;
111 unsigned long transMethod
;
114 * Performant mode completion buffer
117 dma_addr_t reply_pool_dhandle
;
118 u64
*reply_pool_head
;
119 size_t reply_pool_size
;
120 unsigned char reply_pool_wraparound
;
121 u32
*blockFetchTable
;
122 unsigned char *hba_inquiry_data
;
123 u64 last_intr_timestamp
;
125 u64 last_heartbeat_timestamp
;
127 struct list_head lockup_list
;
129 #define HPSA_ABORT_MSG 0
130 #define HPSA_DEVICE_RESET_MSG 1
131 #define HPSA_RESET_TYPE_CONTROLLER 0x00
132 #define HPSA_RESET_TYPE_BUS 0x01
133 #define HPSA_RESET_TYPE_TARGET 0x03
134 #define HPSA_RESET_TYPE_LUN 0x04
135 #define HPSA_MSG_SEND_RETRY_LIMIT 10
136 #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
138 /* Maximum time in seconds driver will wait for command completions
139 * when polling before giving up.
141 #define HPSA_MAX_POLL_TIME_SECS (20)
143 /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
144 * how many times to retry TEST UNIT READY on a device
145 * while waiting for it to become ready before giving up.
146 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
147 * between sending TURs while waiting for a device
150 #define HPSA_TUR_RETRY_LIMIT (20)
151 #define HPSA_MAX_WAIT_INTERVAL_SECS (30)
153 /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
154 * to become ready, in seconds, before giving up on it.
155 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
156 * between polling the board to see if it is ready, in
157 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
158 * HPSA_BOARD_READY_ITERATIONS are derived from those.
160 #define HPSA_BOARD_READY_WAIT_SECS (120)
161 #define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
162 #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
163 #define HPSA_BOARD_READY_POLL_INTERVAL \
164 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
165 #define HPSA_BOARD_READY_ITERATIONS \
166 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
167 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
168 #define HPSA_BOARD_NOT_READY_ITERATIONS \
169 ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
170 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
171 #define HPSA_POST_RESET_PAUSE_MSECS (3000)
172 #define HPSA_POST_RESET_NOOP_RETRIES (12)
174 /* Defining the diffent access_menthods */
176 * Memory mapped FIFO interface (SMART 53xx cards)
178 #define SA5_DOORBELL 0x20
179 #define SA5_REQUEST_PORT_OFFSET 0x40
180 #define SA5_REPLY_INTR_MASK_OFFSET 0x34
181 #define SA5_REPLY_PORT_OFFSET 0x44
182 #define SA5_INTR_STATUS 0x30
183 #define SA5_SCRATCHPAD_OFFSET 0xB0
185 #define SA5_CTCFG_OFFSET 0xB4
186 #define SA5_CTMEM_OFFSET 0xB8
188 #define SA5_INTR_OFF 0x08
189 #define SA5B_INTR_OFF 0x04
190 #define SA5_INTR_PENDING 0x08
191 #define SA5B_INTR_PENDING 0x04
192 #define FIFO_EMPTY 0xffffffff
193 #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
195 #define HPSA_ERROR_BIT 0x02
197 /* Performant mode flags */
198 #define SA5_PERF_INTR_PENDING 0x04
199 #define SA5_PERF_INTR_OFF 0x05
200 #define SA5_OUTDB_STATUS_PERF_BIT 0x01
201 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
202 #define SA5_OUTDB_CLEAR 0xA0
203 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
204 #define SA5_OUTDB_STATUS 0x9C
207 #define HPSA_INTR_ON 1
208 #define HPSA_INTR_OFF 0
210 Send the command to the hardware
212 static void SA5_submit_command(struct ctlr_info
*h
,
213 struct CommandList
*c
)
215 dev_dbg(&h
->pdev
->dev
, "Sending %x, tag = %x\n", c
->busaddr
,
216 c
->Header
.Tag
.lower
);
217 writel(c
->busaddr
, h
->vaddr
+ SA5_REQUEST_PORT_OFFSET
);
218 (void) readl(h
->vaddr
+ SA5_SCRATCHPAD_OFFSET
);
219 h
->commands_outstanding
++;
220 if (h
->commands_outstanding
> h
->max_outstanding
)
221 h
->max_outstanding
= h
->commands_outstanding
;
225 * This card is the opposite of the other cards.
226 * 0 turns interrupts on...
227 * 0x08 turns them off...
229 static void SA5_intr_mask(struct ctlr_info
*h
, unsigned long val
)
231 if (val
) { /* Turn interrupts on */
232 h
->interrupts_enabled
= 1;
233 writel(0, h
->vaddr
+ SA5_REPLY_INTR_MASK_OFFSET
);
234 (void) readl(h
->vaddr
+ SA5_REPLY_INTR_MASK_OFFSET
);
235 } else { /* Turn them off */
236 h
->interrupts_enabled
= 0;
238 h
->vaddr
+ SA5_REPLY_INTR_MASK_OFFSET
);
239 (void) readl(h
->vaddr
+ SA5_REPLY_INTR_MASK_OFFSET
);
243 static void SA5_performant_intr_mask(struct ctlr_info
*h
, unsigned long val
)
245 if (val
) { /* turn on interrupts */
246 h
->interrupts_enabled
= 1;
247 writel(0, h
->vaddr
+ SA5_REPLY_INTR_MASK_OFFSET
);
248 (void) readl(h
->vaddr
+ SA5_REPLY_INTR_MASK_OFFSET
);
250 h
->interrupts_enabled
= 0;
251 writel(SA5_PERF_INTR_OFF
,
252 h
->vaddr
+ SA5_REPLY_INTR_MASK_OFFSET
);
253 (void) readl(h
->vaddr
+ SA5_REPLY_INTR_MASK_OFFSET
);
257 static unsigned long SA5_performant_completed(struct ctlr_info
*h
)
259 unsigned long register_value
= FIFO_EMPTY
;
261 /* flush the controller write of the reply queue by reading
262 * outbound doorbell status register.
264 register_value
= readl(h
->vaddr
+ SA5_OUTDB_STATUS
);
265 /* msi auto clears the interrupt pending bit. */
266 if (!(h
->msi_vector
|| h
->msix_vector
)) {
267 writel(SA5_OUTDB_CLEAR_PERF_BIT
, h
->vaddr
+ SA5_OUTDB_CLEAR
);
268 /* Do a read in order to flush the write to the controller
271 register_value
= readl(h
->vaddr
+ SA5_OUTDB_STATUS
);
274 if ((*(h
->reply_pool_head
) & 1) == (h
->reply_pool_wraparound
)) {
275 register_value
= *(h
->reply_pool_head
);
276 (h
->reply_pool_head
)++;
277 h
->commands_outstanding
--;
279 register_value
= FIFO_EMPTY
;
281 /* Check for wraparound */
282 if (h
->reply_pool_head
== (h
->reply_pool
+ h
->max_commands
)) {
283 h
->reply_pool_head
= h
->reply_pool
;
284 h
->reply_pool_wraparound
^= 1;
287 return register_value
;
291 * Returns true if fifo is full.
294 static unsigned long SA5_fifo_full(struct ctlr_info
*h
)
296 if (h
->commands_outstanding
>= h
->max_commands
)
303 * returns value read from hardware.
304 * returns FIFO_EMPTY if there is nothing to read
306 static unsigned long SA5_completed(struct ctlr_info
*h
)
308 unsigned long register_value
309 = readl(h
->vaddr
+ SA5_REPLY_PORT_OFFSET
);
311 if (register_value
!= FIFO_EMPTY
)
312 h
->commands_outstanding
--;
315 if (register_value
!= FIFO_EMPTY
)
316 dev_dbg(&h
->pdev
->dev
, "Read %lx back from board\n",
319 dev_dbg(&h
->pdev
->dev
, "FIFO Empty read\n");
322 return register_value
;
325 * Returns true if an interrupt is pending..
327 static bool SA5_intr_pending(struct ctlr_info
*h
)
329 unsigned long register_value
=
330 readl(h
->vaddr
+ SA5_INTR_STATUS
);
331 dev_dbg(&h
->pdev
->dev
, "intr_pending %lx\n", register_value
);
332 return register_value
& SA5_INTR_PENDING
;
335 static bool SA5_performant_intr_pending(struct ctlr_info
*h
)
337 unsigned long register_value
= readl(h
->vaddr
+ SA5_INTR_STATUS
);
342 if (h
->msi_vector
|| h
->msix_vector
)
345 /* Read outbound doorbell to flush */
346 register_value
= readl(h
->vaddr
+ SA5_OUTDB_STATUS
);
347 return register_value
& SA5_OUTDB_STATUS_PERF_BIT
;
350 static struct access_method SA5_access
= {
358 static struct access_method SA5_performant_access
= {
360 SA5_performant_intr_mask
,
362 SA5_performant_intr_pending
,
363 SA5_performant_completed
,
369 struct access_method
*access
;