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clk: renesas: cpg-mssr: Use always-on governor for Clock Domain
[deliverable/linux.git] / drivers / scsi / hpsa.h
1 /*
2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2016 Microsemi Corporation
4 * Copyright 2014-2015 PMC-Sierra, Inc.
5 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
14 * NON INFRINGEMENT. See the GNU General Public License for more details.
15 *
16 * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
17 *
18 */
19 #ifndef HPSA_H
20 #define HPSA_H
21
22 #include <scsi/scsicam.h>
23
24 #define IO_OK 0
25 #define IO_ERROR 1
26
27 struct ctlr_info;
28
29 struct access_method {
30 void (*submit_command)(struct ctlr_info *h,
31 struct CommandList *c);
32 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
33 bool (*intr_pending)(struct ctlr_info *h);
34 unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
35 };
36
37 /* for SAS hosts and SAS expanders */
38 struct hpsa_sas_node {
39 struct device *parent_dev;
40 struct list_head port_list_head;
41 };
42
43 struct hpsa_sas_port {
44 struct list_head port_list_entry;
45 u64 sas_address;
46 struct sas_port *port;
47 int next_phy_index;
48 struct list_head phy_list_head;
49 struct hpsa_sas_node *parent_node;
50 struct sas_rphy *rphy;
51 };
52
53 struct hpsa_sas_phy {
54 struct list_head phy_list_entry;
55 struct sas_phy *phy;
56 struct hpsa_sas_port *parent_port;
57 bool added_to_port;
58 };
59
60 struct hpsa_scsi_dev_t {
61 unsigned int devtype;
62 int bus, target, lun; /* as presented to the OS */
63 unsigned char scsi3addr[8]; /* as presented to the HW */
64 u8 physical_device : 1;
65 u8 expose_device;
66 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
67 unsigned char device_id[16]; /* from inquiry pg. 0x83 */
68 u64 sas_address;
69 unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
70 unsigned char model[16]; /* bytes 16-31 of inquiry data */
71 unsigned char raid_level; /* from inquiry page 0xC1 */
72 unsigned char volume_offline; /* discovered via TUR or VPD */
73 u16 queue_depth; /* max queue_depth for this device */
74 atomic_t reset_cmds_out; /* Count of commands to-be affected */
75 atomic_t ioaccel_cmds_out; /* Only used for physical devices
76 * counts commands sent to physical
77 * device via "ioaccel" path.
78 */
79 u32 ioaccel_handle;
80 u8 active_path_index;
81 u8 path_map;
82 u8 bay;
83 u8 box[8];
84 u16 phys_connector[8];
85 int offload_config; /* I/O accel RAID offload configured */
86 int offload_enabled; /* I/O accel RAID offload enabled */
87 int offload_to_be_enabled;
88 int hba_ioaccel_enabled;
89 int offload_to_mirror; /* Send next I/O accelerator RAID
90 * offload request to mirror drive
91 */
92 struct raid_map_data raid_map; /* I/O accelerator RAID map */
93
94 /*
95 * Pointers from logical drive map indices to the phys drives that
96 * make those logical drives. Note, multiple logical drives may
97 * share physical drives. You can have for instance 5 physical
98 * drives with 3 logical drives each using those same 5 physical
99 * disks. We need these pointers for counting i/o's out to physical
100 * devices in order to honor physical device queue depth limits.
101 */
102 struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES];
103 int nphysical_disks;
104 int supports_aborts;
105 struct hpsa_sas_port *sas_port;
106 int external; /* 1-from external array 0-not <0-unknown */
107 };
108
109 struct reply_queue_buffer {
110 u64 *head;
111 size_t size;
112 u8 wraparound;
113 u32 current_entry;
114 dma_addr_t busaddr;
115 };
116
117 #pragma pack(1)
118 struct bmic_controller_parameters {
119 u8 led_flags;
120 u8 enable_command_list_verification;
121 u8 backed_out_write_drives;
122 u16 stripes_for_parity;
123 u8 parity_distribution_mode_flags;
124 u16 max_driver_requests;
125 u16 elevator_trend_count;
126 u8 disable_elevator;
127 u8 force_scan_complete;
128 u8 scsi_transfer_mode;
129 u8 force_narrow;
130 u8 rebuild_priority;
131 u8 expand_priority;
132 u8 host_sdb_asic_fix;
133 u8 pdpi_burst_from_host_disabled;
134 char software_name[64];
135 char hardware_name[32];
136 u8 bridge_revision;
137 u8 snapshot_priority;
138 u32 os_specific;
139 u8 post_prompt_timeout;
140 u8 automatic_drive_slamming;
141 u8 reserved1;
142 u8 nvram_flags;
143 u8 cache_nvram_flags;
144 u8 drive_config_flags;
145 u16 reserved2;
146 u8 temp_warning_level;
147 u8 temp_shutdown_level;
148 u8 temp_condition_reset;
149 u8 max_coalesce_commands;
150 u32 max_coalesce_delay;
151 u8 orca_password[4];
152 u8 access_id[16];
153 u8 reserved[356];
154 };
155 #pragma pack()
156
157 struct ctlr_info {
158 int ctlr;
159 char devname[8];
160 char *product_name;
161 struct pci_dev *pdev;
162 u32 board_id;
163 u64 sas_address;
164 void __iomem *vaddr;
165 unsigned long paddr;
166 int nr_cmds; /* Number of commands allowed on this controller */
167 #define HPSA_CMDS_RESERVED_FOR_ABORTS 2
168 #define HPSA_CMDS_RESERVED_FOR_DRIVER 1
169 struct CfgTable __iomem *cfgtable;
170 int interrupts_enabled;
171 int max_commands;
172 atomic_t commands_outstanding;
173 # define PERF_MODE_INT 0
174 # define DOORBELL_INT 1
175 # define SIMPLE_MODE_INT 2
176 # define MEMQ_MODE_INT 3
177 unsigned int intr[MAX_REPLY_QUEUES];
178 unsigned int msix_vector;
179 unsigned int msi_vector;
180 int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
181 struct access_method access;
182
183 /* queue and queue Info */
184 unsigned int Qdepth;
185 unsigned int maxSG;
186 spinlock_t lock;
187 int maxsgentries;
188 u8 max_cmd_sg_entries;
189 int chainsize;
190 struct SGDescriptor **cmd_sg_list;
191 struct ioaccel2_sg_element **ioaccel2_cmd_sg_list;
192
193 /* pointers to command and error info pool */
194 struct CommandList *cmd_pool;
195 dma_addr_t cmd_pool_dhandle;
196 struct io_accel1_cmd *ioaccel_cmd_pool;
197 dma_addr_t ioaccel_cmd_pool_dhandle;
198 struct io_accel2_cmd *ioaccel2_cmd_pool;
199 dma_addr_t ioaccel2_cmd_pool_dhandle;
200 struct ErrorInfo *errinfo_pool;
201 dma_addr_t errinfo_pool_dhandle;
202 unsigned long *cmd_pool_bits;
203 int scan_finished;
204 spinlock_t scan_lock;
205 wait_queue_head_t scan_wait_queue;
206
207 struct Scsi_Host *scsi_host;
208 spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
209 int ndevices; /* number of used elements in .dev[] array. */
210 struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
211 /*
212 * Performant mode tables.
213 */
214 u32 trans_support;
215 u32 trans_offset;
216 struct TransTable_struct __iomem *transtable;
217 unsigned long transMethod;
218
219 /* cap concurrent passthrus at some reasonable maximum */
220 #define HPSA_MAX_CONCURRENT_PASSTHRUS (10)
221 atomic_t passthru_cmds_avail;
222
223 /*
224 * Performant mode completion buffers
225 */
226 size_t reply_queue_size;
227 struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES];
228 u8 nreply_queues;
229 u32 *blockFetchTable;
230 u32 *ioaccel1_blockFetchTable;
231 u32 *ioaccel2_blockFetchTable;
232 u32 __iomem *ioaccel2_bft2_regs;
233 unsigned char *hba_inquiry_data;
234 u32 driver_support;
235 u32 fw_support;
236 int ioaccel_support;
237 int ioaccel_maxsg;
238 u64 last_intr_timestamp;
239 u32 last_heartbeat;
240 u64 last_heartbeat_timestamp;
241 u32 heartbeat_sample_interval;
242 atomic_t firmware_flash_in_progress;
243 u32 __percpu *lockup_detected;
244 struct delayed_work monitor_ctlr_work;
245 struct delayed_work rescan_ctlr_work;
246 int remove_in_progress;
247 /* Address of h->q[x] is passed to intr handler to know which queue */
248 u8 q[MAX_REPLY_QUEUES];
249 char intrname[MAX_REPLY_QUEUES][16]; /* "hpsa0-msix00" names */
250 u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
251 #define HPSATMF_BITS_SUPPORTED (1 << 0)
252 #define HPSATMF_PHYS_LUN_RESET (1 << 1)
253 #define HPSATMF_PHYS_NEX_RESET (1 << 2)
254 #define HPSATMF_PHYS_TASK_ABORT (1 << 3)
255 #define HPSATMF_PHYS_TSET_ABORT (1 << 4)
256 #define HPSATMF_PHYS_CLEAR_ACA (1 << 5)
257 #define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
258 #define HPSATMF_PHYS_QRY_TASK (1 << 7)
259 #define HPSATMF_PHYS_QRY_TSET (1 << 8)
260 #define HPSATMF_PHYS_QRY_ASYNC (1 << 9)
261 #define HPSATMF_IOACCEL_ENABLED (1 << 15)
262 #define HPSATMF_MASK_SUPPORTED (1 << 16)
263 #define HPSATMF_LOG_LUN_RESET (1 << 17)
264 #define HPSATMF_LOG_NEX_RESET (1 << 18)
265 #define HPSATMF_LOG_TASK_ABORT (1 << 19)
266 #define HPSATMF_LOG_TSET_ABORT (1 << 20)
267 #define HPSATMF_LOG_CLEAR_ACA (1 << 21)
268 #define HPSATMF_LOG_CLEAR_TSET (1 << 22)
269 #define HPSATMF_LOG_QRY_TASK (1 << 23)
270 #define HPSATMF_LOG_QRY_TSET (1 << 24)
271 #define HPSATMF_LOG_QRY_ASYNC (1 << 25)
272 u32 events;
273 #define CTLR_STATE_CHANGE_EVENT (1 << 0)
274 #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1)
275 #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4)
276 #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5)
277 #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6)
278 #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30)
279 #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31)
280
281 #define RESCAN_REQUIRED_EVENT_BITS \
282 (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \
283 CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \
284 CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \
285 CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \
286 CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
287 spinlock_t offline_device_lock;
288 struct list_head offline_device_list;
289 int acciopath_status;
290 int drv_req_rescan;
291 int raid_offload_debug;
292 int discovery_polling;
293 struct ReportLUNdata *lastlogicals;
294 int needs_abort_tags_swizzled;
295 struct workqueue_struct *resubmit_wq;
296 struct workqueue_struct *rescan_ctlr_wq;
297 atomic_t abort_cmds_available;
298 wait_queue_head_t abort_cmd_wait_queue;
299 wait_queue_head_t event_sync_wait_queue;
300 struct mutex reset_mutex;
301 u8 reset_in_progress;
302 struct hpsa_sas_node *sas_host;
303 };
304
305 struct offline_device_entry {
306 unsigned char scsi3addr[8];
307 struct list_head offline_list;
308 };
309
310 #define HPSA_ABORT_MSG 0
311 #define HPSA_DEVICE_RESET_MSG 1
312 #define HPSA_RESET_TYPE_CONTROLLER 0x00
313 #define HPSA_RESET_TYPE_BUS 0x01
314 #define HPSA_RESET_TYPE_TARGET 0x03
315 #define HPSA_RESET_TYPE_LUN 0x04
316 #define HPSA_PHYS_TARGET_RESET 0x99 /* not defined by cciss spec */
317 #define HPSA_MSG_SEND_RETRY_LIMIT 10
318 #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
319
320 /* Maximum time in seconds driver will wait for command completions
321 * when polling before giving up.
322 */
323 #define HPSA_MAX_POLL_TIME_SECS (20)
324
325 /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
326 * how many times to retry TEST UNIT READY on a device
327 * while waiting for it to become ready before giving up.
328 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
329 * between sending TURs while waiting for a device
330 * to become ready.
331 */
332 #define HPSA_TUR_RETRY_LIMIT (20)
333 #define HPSA_MAX_WAIT_INTERVAL_SECS (30)
334
335 /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
336 * to become ready, in seconds, before giving up on it.
337 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
338 * between polling the board to see if it is ready, in
339 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
340 * HPSA_BOARD_READY_ITERATIONS are derived from those.
341 */
342 #define HPSA_BOARD_READY_WAIT_SECS (120)
343 #define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
344 #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
345 #define HPSA_BOARD_READY_POLL_INTERVAL \
346 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
347 #define HPSA_BOARD_READY_ITERATIONS \
348 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
349 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
350 #define HPSA_BOARD_NOT_READY_ITERATIONS \
351 ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
352 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
353 #define HPSA_POST_RESET_PAUSE_MSECS (3000)
354 #define HPSA_POST_RESET_NOOP_RETRIES (12)
355
356 /* Defining the diffent access_menthods */
357 /*
358 * Memory mapped FIFO interface (SMART 53xx cards)
359 */
360 #define SA5_DOORBELL 0x20
361 #define SA5_REQUEST_PORT_OFFSET 0x40
362 #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0
363 #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4
364 #define SA5_REPLY_INTR_MASK_OFFSET 0x34
365 #define SA5_REPLY_PORT_OFFSET 0x44
366 #define SA5_INTR_STATUS 0x30
367 #define SA5_SCRATCHPAD_OFFSET 0xB0
368
369 #define SA5_CTCFG_OFFSET 0xB4
370 #define SA5_CTMEM_OFFSET 0xB8
371
372 #define SA5_INTR_OFF 0x08
373 #define SA5B_INTR_OFF 0x04
374 #define SA5_INTR_PENDING 0x08
375 #define SA5B_INTR_PENDING 0x04
376 #define FIFO_EMPTY 0xffffffff
377 #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
378
379 #define HPSA_ERROR_BIT 0x02
380
381 /* Performant mode flags */
382 #define SA5_PERF_INTR_PENDING 0x04
383 #define SA5_PERF_INTR_OFF 0x05
384 #define SA5_OUTDB_STATUS_PERF_BIT 0x01
385 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
386 #define SA5_OUTDB_CLEAR 0xA0
387 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
388 #define SA5_OUTDB_STATUS 0x9C
389
390
391 #define HPSA_INTR_ON 1
392 #define HPSA_INTR_OFF 0
393
394 /*
395 * Inbound Post Queue offsets for IO Accelerator Mode 2
396 */
397 #define IOACCEL2_INBOUND_POSTQ_32 0x48
398 #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0
399 #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4
400
401 #define HPSA_PHYSICAL_DEVICE_BUS 0
402 #define HPSA_RAID_VOLUME_BUS 1
403 #define HPSA_EXTERNAL_RAID_VOLUME_BUS 2
404 #define HPSA_HBA_BUS 0
405
406 /*
407 Send the command to the hardware
408 */
409 static void SA5_submit_command(struct ctlr_info *h,
410 struct CommandList *c)
411 {
412 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
413 (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
414 }
415
416 static void SA5_submit_command_no_read(struct ctlr_info *h,
417 struct CommandList *c)
418 {
419 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
420 }
421
422 static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
423 struct CommandList *c)
424 {
425 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
426 }
427
428 /*
429 * This card is the opposite of the other cards.
430 * 0 turns interrupts on...
431 * 0x08 turns them off...
432 */
433 static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
434 {
435 if (val) { /* Turn interrupts on */
436 h->interrupts_enabled = 1;
437 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
438 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
439 } else { /* Turn them off */
440 h->interrupts_enabled = 0;
441 writel(SA5_INTR_OFF,
442 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
443 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
444 }
445 }
446
447 static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
448 {
449 if (val) { /* turn on interrupts */
450 h->interrupts_enabled = 1;
451 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
452 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
453 } else {
454 h->interrupts_enabled = 0;
455 writel(SA5_PERF_INTR_OFF,
456 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
457 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
458 }
459 }
460
461 static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
462 {
463 struct reply_queue_buffer *rq = &h->reply_queue[q];
464 unsigned long register_value = FIFO_EMPTY;
465
466 /* msi auto clears the interrupt pending bit. */
467 if (unlikely(!(h->msi_vector || h->msix_vector))) {
468 /* flush the controller write of the reply queue by reading
469 * outbound doorbell status register.
470 */
471 (void) readl(h->vaddr + SA5_OUTDB_STATUS);
472 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
473 /* Do a read in order to flush the write to the controller
474 * (as per spec.)
475 */
476 (void) readl(h->vaddr + SA5_OUTDB_STATUS);
477 }
478
479 if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) {
480 register_value = rq->head[rq->current_entry];
481 rq->current_entry++;
482 atomic_dec(&h->commands_outstanding);
483 } else {
484 register_value = FIFO_EMPTY;
485 }
486 /* Check for wraparound */
487 if (rq->current_entry == h->max_commands) {
488 rq->current_entry = 0;
489 rq->wraparound ^= 1;
490 }
491 return register_value;
492 }
493
494 /*
495 * returns value read from hardware.
496 * returns FIFO_EMPTY if there is nothing to read
497 */
498 static unsigned long SA5_completed(struct ctlr_info *h,
499 __attribute__((unused)) u8 q)
500 {
501 unsigned long register_value
502 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
503
504 if (register_value != FIFO_EMPTY)
505 atomic_dec(&h->commands_outstanding);
506
507 #ifdef HPSA_DEBUG
508 if (register_value != FIFO_EMPTY)
509 dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
510 register_value);
511 else
512 dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
513 #endif
514
515 return register_value;
516 }
517 /*
518 * Returns true if an interrupt is pending..
519 */
520 static bool SA5_intr_pending(struct ctlr_info *h)
521 {
522 unsigned long register_value =
523 readl(h->vaddr + SA5_INTR_STATUS);
524 return register_value & SA5_INTR_PENDING;
525 }
526
527 static bool SA5_performant_intr_pending(struct ctlr_info *h)
528 {
529 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
530
531 if (!register_value)
532 return false;
533
534 /* Read outbound doorbell to flush */
535 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
536 return register_value & SA5_OUTDB_STATUS_PERF_BIT;
537 }
538
539 #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100
540
541 static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
542 {
543 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
544
545 return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
546 true : false;
547 }
548
549 #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
550 #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
551 #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
552 #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL
553
554 static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
555 {
556 u64 register_value;
557 struct reply_queue_buffer *rq = &h->reply_queue[q];
558
559 BUG_ON(q >= h->nreply_queues);
560
561 register_value = rq->head[rq->current_entry];
562 if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
563 rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
564 if (++rq->current_entry == rq->size)
565 rq->current_entry = 0;
566 /*
567 * @todo
568 *
569 * Don't really need to write the new index after each command,
570 * but with current driver design this is easiest.
571 */
572 wmb();
573 writel((q << 24) | rq->current_entry, h->vaddr +
574 IOACCEL_MODE1_CONSUMER_INDEX);
575 atomic_dec(&h->commands_outstanding);
576 }
577 return (unsigned long) register_value;
578 }
579
580 static struct access_method SA5_access = {
581 SA5_submit_command,
582 SA5_intr_mask,
583 SA5_intr_pending,
584 SA5_completed,
585 };
586
587 static struct access_method SA5_ioaccel_mode1_access = {
588 SA5_submit_command,
589 SA5_performant_intr_mask,
590 SA5_ioaccel_mode1_intr_pending,
591 SA5_ioaccel_mode1_completed,
592 };
593
594 static struct access_method SA5_ioaccel_mode2_access = {
595 SA5_submit_command_ioaccel2,
596 SA5_performant_intr_mask,
597 SA5_performant_intr_pending,
598 SA5_performant_completed,
599 };
600
601 static struct access_method SA5_performant_access = {
602 SA5_submit_command,
603 SA5_performant_intr_mask,
604 SA5_performant_intr_pending,
605 SA5_performant_completed,
606 };
607
608 static struct access_method SA5_performant_access_no_read = {
609 SA5_submit_command_no_read,
610 SA5_performant_intr_mask,
611 SA5_performant_intr_pending,
612 SA5_performant_completed,
613 };
614
615 struct board_type {
616 u32 board_id;
617 char *product_name;
618 struct access_method *access;
619 };
620
621 #endif /* HPSA_H */
622
Linux kernel - Deliverables
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