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[SCSI] ipr: Add support for MSI-X and distributed completion
[deliverable/linux.git] / drivers / scsi / ipr.h
1 /*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
24 */
25
26 #ifndef _IPR_H
27 #define _IPR_H
28
29 #include <asm/unaligned.h>
30 #include <linux/types.h>
31 #include <linux/completion.h>
32 #include <linux/libata.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <scsi/scsi.h>
36 #include <scsi/scsi_cmnd.h>
37
38 /*
39 * Literals
40 */
41 #define IPR_DRIVER_VERSION "2.5.4"
42 #define IPR_DRIVER_DATE "(July 11, 2012)"
43
44 /*
45 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
46 * ops per device for devices not running tagged command queuing.
47 * This can be adjusted at runtime through sysfs device attributes.
48 */
49 #define IPR_MAX_CMD_PER_LUN 6
50 #define IPR_MAX_CMD_PER_ATA_LUN 1
51
52 /*
53 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
54 * ops the mid-layer can send to the adapter.
55 */
56 #define IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds)
57
58 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
59
60 #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
61 #define PCI_DEVICE_ID_IBM_CROCODILE 0x034A
62
63 #define IPR_SUBS_DEV_ID_2780 0x0264
64 #define IPR_SUBS_DEV_ID_5702 0x0266
65 #define IPR_SUBS_DEV_ID_5703 0x0278
66 #define IPR_SUBS_DEV_ID_572E 0x028D
67 #define IPR_SUBS_DEV_ID_573E 0x02D3
68 #define IPR_SUBS_DEV_ID_573D 0x02D4
69 #define IPR_SUBS_DEV_ID_571A 0x02C0
70 #define IPR_SUBS_DEV_ID_571B 0x02BE
71 #define IPR_SUBS_DEV_ID_571E 0x02BF
72 #define IPR_SUBS_DEV_ID_571F 0x02D5
73 #define IPR_SUBS_DEV_ID_572A 0x02C1
74 #define IPR_SUBS_DEV_ID_572B 0x02C2
75 #define IPR_SUBS_DEV_ID_572F 0x02C3
76 #define IPR_SUBS_DEV_ID_574E 0x030A
77 #define IPR_SUBS_DEV_ID_575B 0x030D
78 #define IPR_SUBS_DEV_ID_575C 0x0338
79 #define IPR_SUBS_DEV_ID_57B3 0x033A
80 #define IPR_SUBS_DEV_ID_57B7 0x0360
81 #define IPR_SUBS_DEV_ID_57B8 0x02C2
82
83 #define IPR_SUBS_DEV_ID_57B4 0x033B
84 #define IPR_SUBS_DEV_ID_57B2 0x035F
85 #define IPR_SUBS_DEV_ID_57C0 0x0352
86 #define IPR_SUBS_DEV_ID_57C3 0x0353
87 #define IPR_SUBS_DEV_ID_57C4 0x0354
88 #define IPR_SUBS_DEV_ID_57C6 0x0357
89 #define IPR_SUBS_DEV_ID_57CC 0x035C
90
91 #define IPR_SUBS_DEV_ID_57B5 0x033C
92 #define IPR_SUBS_DEV_ID_57CE 0x035E
93 #define IPR_SUBS_DEV_ID_57B1 0x0355
94
95 #define IPR_SUBS_DEV_ID_574D 0x0356
96 #define IPR_SUBS_DEV_ID_57C8 0x035D
97
98 #define IPR_SUBS_DEV_ID_57D5 0x03FB
99 #define IPR_SUBS_DEV_ID_57D6 0x03FC
100 #define IPR_SUBS_DEV_ID_57D7 0x03FF
101 #define IPR_SUBS_DEV_ID_57D8 0x03FE
102 #define IPR_NAME "ipr"
103
104 /*
105 * Return codes
106 */
107 #define IPR_RC_JOB_CONTINUE 1
108 #define IPR_RC_JOB_RETURN 2
109
110 /*
111 * IOASCs
112 */
113 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
114 #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
115 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000
116 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
117 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
118 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
119 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00
120 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
121 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
122 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
123 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
124 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
125 #define IPR_IOASC_BUS_WAS_RESET 0x06290000
126 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
127 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
128
129 #define IPR_FIRST_DRIVER_IOASC 0x10000000
130 #define IPR_IOASC_IOA_WAS_RESET 0x10000001
131 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
132
133 /* Driver data flags */
134 #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
135 #define IPR_USE_PCI_WARM_RESET 0x00000002
136
137 #define IPR_DEFAULT_MAX_ERROR_DUMP 984
138 #define IPR_NUM_LOG_HCAMS 2
139 #define IPR_NUM_CFG_CHG_HCAMS 2
140 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
141
142 #define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
143 #define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
144
145 #define IPR_MAX_NUM_TARGETS_PER_BUS 256
146 #define IPR_MAX_NUM_LUNS_PER_TARGET 256
147 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
148 #define IPR_VSET_BUS 0xff
149 #define IPR_IOA_BUS 0xff
150 #define IPR_IOA_TARGET 0xff
151 #define IPR_IOA_LUN 0xff
152 #define IPR_MAX_NUM_BUSES 16
153 #define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
154
155 #define IPR_NUM_RESET_RELOAD_RETRIES 3
156
157 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
158 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
159 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
160
161 #define IPR_MAX_COMMANDS 100
162 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
163 IPR_NUM_INTERNAL_CMD_BLKS)
164
165 #define IPR_MAX_PHYSICAL_DEVS 192
166 #define IPR_DEFAULT_SIS64_DEVS 1024
167 #define IPR_MAX_SIS64_DEVS 4096
168
169 #define IPR_MAX_SGLIST 64
170 #define IPR_IOA_MAX_SECTORS 32767
171 #define IPR_VSET_MAX_SECTORS 512
172 #define IPR_MAX_CDB_LEN 16
173 #define IPR_MAX_HRRQ_RETRIES 3
174
175 #define IPR_DEFAULT_BUS_WIDTH 16
176 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
177 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
178 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
179 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
180
181 #define IPR_IOA_RES_HANDLE 0xffffffff
182 #define IPR_INVALID_RES_HANDLE 0
183 #define IPR_IOA_RES_ADDR 0x00ffffff
184
185 /*
186 * Adapter Commands
187 */
188 #define IPR_QUERY_RSRC_STATE 0xC2
189 #define IPR_RESET_DEVICE 0xC3
190 #define IPR_RESET_TYPE_SELECT 0x80
191 #define IPR_LUN_RESET 0x40
192 #define IPR_TARGET_RESET 0x20
193 #define IPR_BUS_RESET 0x10
194 #define IPR_ATA_PHY_RESET 0x80
195 #define IPR_ID_HOST_RR_Q 0xC4
196 #define IPR_QUERY_IOA_CONFIG 0xC5
197 #define IPR_CANCEL_ALL_REQUESTS 0xCE
198 #define IPR_HOST_CONTROLLED_ASYNC 0xCF
199 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
200 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
201 #define IPR_SET_SUPPORTED_DEVICES 0xFB
202 #define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
203 #define IPR_IOA_SHUTDOWN 0xF7
204 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
205
206 /*
207 * Timeouts
208 */
209 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
210 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
211 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
212 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
213 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
214 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
215 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
216 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
217 #define IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ)
218 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
219 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
220 #define IPR_OPERATIONAL_TIMEOUT (5 * 60)
221 #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
222 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
223 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
224 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
225 #define IPR_PCI_RESET_TIMEOUT (HZ / 2)
226 #define IPR_SIS32_DUMP_TIMEOUT (15 * HZ)
227 #define IPR_SIS64_DUMP_TIMEOUT (40 * HZ)
228 #define IPR_DUMP_DELAY_SECONDS 4
229 #define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ)
230
231 /*
232 * SCSI Literals
233 */
234 #define IPR_VENDOR_ID_LEN 8
235 #define IPR_PROD_ID_LEN 16
236 #define IPR_SERIAL_NUM_LEN 8
237
238 /*
239 * Hardware literals
240 */
241 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
242 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
243 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
244 #define IPR_GET_FMT2_BAR_SEL(mbx) \
245 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
246 #define IPR_SDT_FMT2_BAR0_SEL 0x0
247 #define IPR_SDT_FMT2_BAR1_SEL 0x1
248 #define IPR_SDT_FMT2_BAR2_SEL 0x2
249 #define IPR_SDT_FMT2_BAR3_SEL 0x3
250 #define IPR_SDT_FMT2_BAR4_SEL 0x4
251 #define IPR_SDT_FMT2_BAR5_SEL 0x5
252 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
253 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
254 #define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
255 #define IPR_DOORBELL 0x82800000
256 #define IPR_RUNTIME_RESET 0x40000000
257
258 #define IPR_IPL_INIT_MIN_STAGE_TIME 5
259 #define IPR_IPL_INIT_DEFAULT_STAGE_TIME 15
260 #define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
261 #define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
262 #define IPR_IPL_INIT_STAGE_MASK 0xff000000
263 #define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
264 #define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
265
266 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
267 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
268 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
269 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
270 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
271 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
272 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
273 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
274 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
275 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
276 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
277
278 #define IPR_PCII_ERROR_INTERRUPTS \
279 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
280 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
281
282 #define IPR_PCII_OPER_INTERRUPTS \
283 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
284
285 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
286 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
287 #define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
288
289 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
290 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
291
292 /*
293 * Dump literals
294 */
295 #define IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
296 #define IPR_FMT3_MAX_IOA_DUMP_SIZE (32 * 1024 * 1024)
297 #define IPR_FMT2_NUM_SDT_ENTRIES 511
298 #define IPR_FMT3_NUM_SDT_ENTRIES 0xFFF
299 #define IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
300 #define IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
301
302 /*
303 * Misc literals
304 */
305 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
306 #define IPR_MAX_MSIX_VECTORS 0x5
307 #define IPR_MAX_HRRQ_NUM 0x10
308 #define IPR_INIT_HRRQ 0x0
309
310 /*
311 * Adapter interface types
312 */
313
314 struct ipr_res_addr {
315 u8 reserved;
316 u8 bus;
317 u8 target;
318 u8 lun;
319 #define IPR_GET_PHYS_LOC(res_addr) \
320 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
321 }__attribute__((packed, aligned (4)));
322
323 struct ipr_std_inq_vpids {
324 u8 vendor_id[IPR_VENDOR_ID_LEN];
325 u8 product_id[IPR_PROD_ID_LEN];
326 }__attribute__((packed));
327
328 struct ipr_vpd {
329 struct ipr_std_inq_vpids vpids;
330 u8 sn[IPR_SERIAL_NUM_LEN];
331 }__attribute__((packed));
332
333 struct ipr_ext_vpd {
334 struct ipr_vpd vpd;
335 __be32 wwid[2];
336 }__attribute__((packed));
337
338 struct ipr_ext_vpd64 {
339 struct ipr_vpd vpd;
340 __be32 wwid[4];
341 }__attribute__((packed));
342
343 struct ipr_std_inq_data {
344 u8 peri_qual_dev_type;
345 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
346 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
347
348 u8 removeable_medium_rsvd;
349 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
350
351 #define IPR_IS_DASD_DEVICE(std_inq) \
352 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
353 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
354
355 #define IPR_IS_SES_DEVICE(std_inq) \
356 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
357
358 u8 version;
359 u8 aen_naca_fmt;
360 u8 additional_len;
361 u8 sccs_rsvd;
362 u8 bq_enc_multi;
363 u8 sync_cmdq_flags;
364
365 struct ipr_std_inq_vpids vpids;
366
367 u8 ros_rsvd_ram_rsvd[4];
368
369 u8 serial_num[IPR_SERIAL_NUM_LEN];
370 }__attribute__ ((packed));
371
372 #define IPR_RES_TYPE_AF_DASD 0x00
373 #define IPR_RES_TYPE_GENERIC_SCSI 0x01
374 #define IPR_RES_TYPE_VOLUME_SET 0x02
375 #define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
376 #define IPR_RES_TYPE_GENERIC_ATA 0x04
377 #define IPR_RES_TYPE_ARRAY 0x05
378 #define IPR_RES_TYPE_IOAFP 0xff
379
380 struct ipr_config_table_entry {
381 u8 proto;
382 #define IPR_PROTO_SATA 0x02
383 #define IPR_PROTO_SATA_ATAPI 0x03
384 #define IPR_PROTO_SAS_STP 0x06
385 #define IPR_PROTO_SAS_STP_ATAPI 0x07
386 u8 array_id;
387 u8 flags;
388 #define IPR_IS_IOA_RESOURCE 0x80
389 u8 rsvd_subtype;
390
391 #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
392 #define IPR_QUEUE_FROZEN_MODEL 0
393 #define IPR_QUEUE_NACA_MODEL 1
394
395 struct ipr_res_addr res_addr;
396 __be32 res_handle;
397 __be32 lun_wwn[2];
398 struct ipr_std_inq_data std_inq_data;
399 }__attribute__ ((packed, aligned (4)));
400
401 struct ipr_config_table_entry64 {
402 u8 res_type;
403 u8 proto;
404 u8 vset_num;
405 u8 array_id;
406 __be16 flags;
407 __be16 res_flags;
408 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
409 __be32 res_handle;
410 u8 dev_id_type;
411 u8 reserved[3];
412 __be64 dev_id;
413 __be64 lun;
414 __be64 lun_wwn[2];
415 #define IPR_MAX_RES_PATH_LENGTH 48
416 __be64 res_path;
417 struct ipr_std_inq_data std_inq_data;
418 u8 reserved2[4];
419 __be64 reserved3[2];
420 u8 reserved4[8];
421 }__attribute__ ((packed, aligned (8)));
422
423 struct ipr_config_table_hdr {
424 u8 num_entries;
425 u8 flags;
426 #define IPR_UCODE_DOWNLOAD_REQ 0x10
427 __be16 reserved;
428 }__attribute__((packed, aligned (4)));
429
430 struct ipr_config_table_hdr64 {
431 __be16 num_entries;
432 __be16 reserved;
433 u8 flags;
434 u8 reserved2[11];
435 }__attribute__((packed, aligned (4)));
436
437 struct ipr_config_table {
438 struct ipr_config_table_hdr hdr;
439 struct ipr_config_table_entry dev[0];
440 }__attribute__((packed, aligned (4)));
441
442 struct ipr_config_table64 {
443 struct ipr_config_table_hdr64 hdr64;
444 struct ipr_config_table_entry64 dev[0];
445 }__attribute__((packed, aligned (8)));
446
447 struct ipr_config_table_entry_wrapper {
448 union {
449 struct ipr_config_table_entry *cfgte;
450 struct ipr_config_table_entry64 *cfgte64;
451 } u;
452 };
453
454 struct ipr_hostrcb_cfg_ch_not {
455 union {
456 struct ipr_config_table_entry cfgte;
457 struct ipr_config_table_entry64 cfgte64;
458 } u;
459 u8 reserved[936];
460 }__attribute__((packed, aligned (4)));
461
462 struct ipr_supported_device {
463 __be16 data_length;
464 u8 reserved;
465 u8 num_records;
466 struct ipr_std_inq_vpids vpids;
467 u8 reserved2[16];
468 }__attribute__((packed, aligned (4)));
469
470 struct ipr_hrr_queue {
471 struct ipr_ioa_cfg *ioa_cfg;
472 __be32 *host_rrq;
473 dma_addr_t host_rrq_dma;
474 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
475 #define IPR_HRRQ_RESP_BIT_SET 0x00000002
476 #define IPR_HRRQ_TOGGLE_BIT 0x00000001
477 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
478 #define IPR_ID_HRRQ_SELE_ENABLE 0x02
479 volatile __be32 *hrrq_start;
480 volatile __be32 *hrrq_end;
481 volatile __be32 *hrrq_curr;
482
483 struct list_head hrrq_free_q;
484 struct list_head hrrq_pending_q;
485
486 volatile u32 toggle_bit;
487 u32 size;
488 u32 min_cmd_id;
489 u32 max_cmd_id;
490 };
491
492 #define for_each_hrrq(hrrq, ioa_cfg) \
493 for (hrrq = (ioa_cfg)->hrrq; \
494 hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++)
495
496 /* Command packet structure */
497 struct ipr_cmd_pkt {
498 u8 reserved; /* Reserved by IOA */
499 u8 hrrq_id;
500 u8 request_type;
501 #define IPR_RQTYPE_SCSICDB 0x00
502 #define IPR_RQTYPE_IOACMD 0x01
503 #define IPR_RQTYPE_HCAM 0x02
504 #define IPR_RQTYPE_ATA_PASSTHRU 0x04
505
506 u8 reserved2;
507
508 u8 flags_hi;
509 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
510 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
511 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
512 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
513 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04
514
515 u8 flags_lo;
516 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20
517 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
518 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
519 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02
520 #define IPR_FLAGS_LO_ORDERED_TASK 0x04
521 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
522 #define IPR_FLAGS_LO_ACA_TASK 0x08
523
524 u8 cdb[16];
525 __be16 timeout;
526 }__attribute__ ((packed, aligned(4)));
527
528 struct ipr_ioarcb_ata_regs { /* 22 bytes */
529 u8 flags;
530 #define IPR_ATA_FLAG_PACKET_CMD 0x80
531 #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
532 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
533 u8 reserved[3];
534
535 __be16 data;
536 u8 feature;
537 u8 nsect;
538 u8 lbal;
539 u8 lbam;
540 u8 lbah;
541 u8 device;
542 u8 command;
543 u8 reserved2[3];
544 u8 hob_feature;
545 u8 hob_nsect;
546 u8 hob_lbal;
547 u8 hob_lbam;
548 u8 hob_lbah;
549 u8 ctl;
550 }__attribute__ ((packed, aligned(4)));
551
552 struct ipr_ioadl_desc {
553 __be32 flags_and_data_len;
554 #define IPR_IOADL_FLAGS_MASK 0xff000000
555 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
556 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
557 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
558 #define IPR_IOADL_FLAGS_READ 0x48000000
559 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000
560 #define IPR_IOADL_FLAGS_WRITE 0x68000000
561 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
562 #define IPR_IOADL_FLAGS_LAST 0x01000000
563
564 __be32 address;
565 }__attribute__((packed, aligned (8)));
566
567 struct ipr_ioadl64_desc {
568 __be32 flags;
569 __be32 data_len;
570 __be64 address;
571 }__attribute__((packed, aligned (16)));
572
573 struct ipr_ata64_ioadl {
574 struct ipr_ioarcb_ata_regs regs;
575 u16 reserved[5];
576 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
577 }__attribute__((packed, aligned (16)));
578
579 struct ipr_ioarcb_add_data {
580 union {
581 struct ipr_ioarcb_ata_regs regs;
582 struct ipr_ioadl_desc ioadl[5];
583 __be32 add_cmd_parms[10];
584 } u;
585 }__attribute__ ((packed, aligned (4)));
586
587 struct ipr_ioarcb_sis64_add_addr_ecb {
588 __be64 ioasa_host_pci_addr;
589 __be64 data_ioadl_addr;
590 __be64 reserved;
591 __be32 ext_control_buf[4];
592 }__attribute__((packed, aligned (8)));
593
594 /* IOA Request Control Block 128 bytes */
595 struct ipr_ioarcb {
596 union {
597 __be32 ioarcb_host_pci_addr;
598 __be64 ioarcb_host_pci_addr64;
599 } a;
600 __be32 res_handle;
601 __be32 host_response_handle;
602 __be32 reserved1;
603 __be32 reserved2;
604 __be32 reserved3;
605
606 __be32 data_transfer_length;
607 __be32 read_data_transfer_length;
608 __be32 write_ioadl_addr;
609 __be32 ioadl_len;
610 __be32 read_ioadl_addr;
611 __be32 read_ioadl_len;
612
613 __be32 ioasa_host_pci_addr;
614 __be16 ioasa_len;
615 __be16 reserved4;
616
617 struct ipr_cmd_pkt cmd_pkt;
618
619 __be16 add_cmd_parms_offset;
620 __be16 add_cmd_parms_len;
621
622 union {
623 struct ipr_ioarcb_add_data add_data;
624 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
625 } u;
626
627 }__attribute__((packed, aligned (4)));
628
629 struct ipr_ioasa_vset {
630 __be32 failing_lba_hi;
631 __be32 failing_lba_lo;
632 __be32 reserved;
633 }__attribute__((packed, aligned (4)));
634
635 struct ipr_ioasa_af_dasd {
636 __be32 failing_lba;
637 __be32 reserved[2];
638 }__attribute__((packed, aligned (4)));
639
640 struct ipr_ioasa_gpdd {
641 u8 end_state;
642 u8 bus_phase;
643 __be16 reserved;
644 __be32 ioa_data[2];
645 }__attribute__((packed, aligned (4)));
646
647 struct ipr_ioasa_gata {
648 u8 error;
649 u8 nsect; /* Interrupt reason */
650 u8 lbal;
651 u8 lbam;
652 u8 lbah;
653 u8 device;
654 u8 status;
655 u8 alt_status; /* ATA CTL */
656 u8 hob_nsect;
657 u8 hob_lbal;
658 u8 hob_lbam;
659 u8 hob_lbah;
660 }__attribute__((packed, aligned (4)));
661
662 struct ipr_auto_sense {
663 __be16 auto_sense_len;
664 __be16 ioa_data_len;
665 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
666 };
667
668 struct ipr_ioasa_hdr {
669 __be32 ioasc;
670 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
671 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
672 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
673 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
674
675 __be16 ret_stat_len; /* Length of the returned IOASA */
676
677 __be16 avail_stat_len; /* Total Length of status available. */
678
679 __be32 residual_data_len; /* number of bytes in the host data */
680 /* buffers that were not used by the IOARCB command. */
681
682 __be32 ilid;
683 #define IPR_NO_ILID 0
684 #define IPR_DRIVER_ILID 0xffffffff
685
686 __be32 fd_ioasc;
687
688 __be32 fd_phys_locator;
689
690 __be32 fd_res_handle;
691
692 __be32 ioasc_specific; /* status code specific field */
693 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000
694 #define IPR_AUTOSENSE_VALID 0x40000000
695 #define IPR_ATA_DEVICE_WAS_RESET 0x20000000
696 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
697 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
698 #define IPR_FIELD_POINTER_MASK 0x0000ffff
699
700 }__attribute__((packed, aligned (4)));
701
702 struct ipr_ioasa {
703 struct ipr_ioasa_hdr hdr;
704
705 union {
706 struct ipr_ioasa_vset vset;
707 struct ipr_ioasa_af_dasd dasd;
708 struct ipr_ioasa_gpdd gpdd;
709 struct ipr_ioasa_gata gata;
710 } u;
711
712 struct ipr_auto_sense auto_sense;
713 }__attribute__((packed, aligned (4)));
714
715 struct ipr_ioasa64 {
716 struct ipr_ioasa_hdr hdr;
717 u8 fd_res_path[8];
718
719 union {
720 struct ipr_ioasa_vset vset;
721 struct ipr_ioasa_af_dasd dasd;
722 struct ipr_ioasa_gpdd gpdd;
723 struct ipr_ioasa_gata gata;
724 } u;
725
726 struct ipr_auto_sense auto_sense;
727 }__attribute__((packed, aligned (4)));
728
729 struct ipr_mode_parm_hdr {
730 u8 length;
731 u8 medium_type;
732 u8 device_spec_parms;
733 u8 block_desc_len;
734 }__attribute__((packed));
735
736 struct ipr_mode_pages {
737 struct ipr_mode_parm_hdr hdr;
738 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
739 }__attribute__((packed));
740
741 struct ipr_mode_page_hdr {
742 u8 ps_page_code;
743 #define IPR_MODE_PAGE_PS 0x80
744 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
745 u8 page_length;
746 }__attribute__ ((packed));
747
748 struct ipr_dev_bus_entry {
749 struct ipr_res_addr res_addr;
750 u8 flags;
751 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80
752 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40
753 #define IPR_SCSI_ATTR_QAS_MASK 0xC0
754 #define IPR_SCSI_ATTR_ENABLE_TM 0x20
755 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
756 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
757 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
758
759 u8 scsi_id;
760 u8 bus_width;
761 u8 extended_reset_delay;
762 #define IPR_EXTENDED_RESET_DELAY 7
763
764 __be32 max_xfer_rate;
765
766 u8 spinup_delay;
767 u8 reserved3;
768 __be16 reserved4;
769 }__attribute__((packed, aligned (4)));
770
771 struct ipr_mode_page28 {
772 struct ipr_mode_page_hdr hdr;
773 u8 num_entries;
774 u8 entry_length;
775 struct ipr_dev_bus_entry bus[0];
776 }__attribute__((packed));
777
778 struct ipr_mode_page24 {
779 struct ipr_mode_page_hdr hdr;
780 u8 flags;
781 #define IPR_ENABLE_DUAL_IOA_AF 0x80
782 }__attribute__((packed));
783
784 struct ipr_ioa_vpd {
785 struct ipr_std_inq_data std_inq_data;
786 u8 ascii_part_num[12];
787 u8 reserved[40];
788 u8 ascii_plant_code[4];
789 }__attribute__((packed));
790
791 struct ipr_inquiry_page3 {
792 u8 peri_qual_dev_type;
793 u8 page_code;
794 u8 reserved1;
795 u8 page_length;
796 u8 ascii_len;
797 u8 reserved2[3];
798 u8 load_id[4];
799 u8 major_release;
800 u8 card_type;
801 u8 minor_release[2];
802 u8 ptf_number[4];
803 u8 patch_number[4];
804 }__attribute__((packed));
805
806 struct ipr_inquiry_cap {
807 u8 peri_qual_dev_type;
808 u8 page_code;
809 u8 reserved1;
810 u8 page_length;
811 u8 ascii_len;
812 u8 reserved2;
813 u8 sis_version[2];
814 u8 cap;
815 #define IPR_CAP_DUAL_IOA_RAID 0x80
816 u8 reserved3[15];
817 }__attribute__((packed));
818
819 #define IPR_INQUIRY_PAGE0_ENTRIES 20
820 struct ipr_inquiry_page0 {
821 u8 peri_qual_dev_type;
822 u8 page_code;
823 u8 reserved1;
824 u8 len;
825 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
826 }__attribute__((packed));
827
828 struct ipr_hostrcb_device_data_entry {
829 struct ipr_vpd vpd;
830 struct ipr_res_addr dev_res_addr;
831 struct ipr_vpd new_vpd;
832 struct ipr_vpd ioa_last_with_dev_vpd;
833 struct ipr_vpd cfc_last_with_dev_vpd;
834 __be32 ioa_data[5];
835 }__attribute__((packed, aligned (4)));
836
837 struct ipr_hostrcb_device_data_entry_enhanced {
838 struct ipr_ext_vpd vpd;
839 u8 ccin[4];
840 struct ipr_res_addr dev_res_addr;
841 struct ipr_ext_vpd new_vpd;
842 u8 new_ccin[4];
843 struct ipr_ext_vpd ioa_last_with_dev_vpd;
844 struct ipr_ext_vpd cfc_last_with_dev_vpd;
845 }__attribute__((packed, aligned (4)));
846
847 struct ipr_hostrcb64_device_data_entry_enhanced {
848 struct ipr_ext_vpd vpd;
849 u8 ccin[4];
850 u8 res_path[8];
851 struct ipr_ext_vpd new_vpd;
852 u8 new_ccin[4];
853 struct ipr_ext_vpd ioa_last_with_dev_vpd;
854 struct ipr_ext_vpd cfc_last_with_dev_vpd;
855 }__attribute__((packed, aligned (4)));
856
857 struct ipr_hostrcb_array_data_entry {
858 struct ipr_vpd vpd;
859 struct ipr_res_addr expected_dev_res_addr;
860 struct ipr_res_addr dev_res_addr;
861 }__attribute__((packed, aligned (4)));
862
863 struct ipr_hostrcb64_array_data_entry {
864 struct ipr_ext_vpd vpd;
865 u8 ccin[4];
866 u8 expected_res_path[8];
867 u8 res_path[8];
868 }__attribute__((packed, aligned (4)));
869
870 struct ipr_hostrcb_array_data_entry_enhanced {
871 struct ipr_ext_vpd vpd;
872 u8 ccin[4];
873 struct ipr_res_addr expected_dev_res_addr;
874 struct ipr_res_addr dev_res_addr;
875 }__attribute__((packed, aligned (4)));
876
877 struct ipr_hostrcb_type_ff_error {
878 __be32 ioa_data[758];
879 }__attribute__((packed, aligned (4)));
880
881 struct ipr_hostrcb_type_01_error {
882 __be32 seek_counter;
883 __be32 read_counter;
884 u8 sense_data[32];
885 __be32 ioa_data[236];
886 }__attribute__((packed, aligned (4)));
887
888 struct ipr_hostrcb_type_02_error {
889 struct ipr_vpd ioa_vpd;
890 struct ipr_vpd cfc_vpd;
891 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
892 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
893 __be32 ioa_data[3];
894 }__attribute__((packed, aligned (4)));
895
896 struct ipr_hostrcb_type_12_error {
897 struct ipr_ext_vpd ioa_vpd;
898 struct ipr_ext_vpd cfc_vpd;
899 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
900 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
901 __be32 ioa_data[3];
902 }__attribute__((packed, aligned (4)));
903
904 struct ipr_hostrcb_type_03_error {
905 struct ipr_vpd ioa_vpd;
906 struct ipr_vpd cfc_vpd;
907 __be32 errors_detected;
908 __be32 errors_logged;
909 u8 ioa_data[12];
910 struct ipr_hostrcb_device_data_entry dev[3];
911 }__attribute__((packed, aligned (4)));
912
913 struct ipr_hostrcb_type_13_error {
914 struct ipr_ext_vpd ioa_vpd;
915 struct ipr_ext_vpd cfc_vpd;
916 __be32 errors_detected;
917 __be32 errors_logged;
918 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
919 }__attribute__((packed, aligned (4)));
920
921 struct ipr_hostrcb_type_23_error {
922 struct ipr_ext_vpd ioa_vpd;
923 struct ipr_ext_vpd cfc_vpd;
924 __be32 errors_detected;
925 __be32 errors_logged;
926 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
927 }__attribute__((packed, aligned (4)));
928
929 struct ipr_hostrcb_type_04_error {
930 struct ipr_vpd ioa_vpd;
931 struct ipr_vpd cfc_vpd;
932 u8 ioa_data[12];
933 struct ipr_hostrcb_array_data_entry array_member[10];
934 __be32 exposed_mode_adn;
935 __be32 array_id;
936 struct ipr_vpd incomp_dev_vpd;
937 __be32 ioa_data2;
938 struct ipr_hostrcb_array_data_entry array_member2[8];
939 struct ipr_res_addr last_func_vset_res_addr;
940 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
941 u8 protection_level[8];
942 }__attribute__((packed, aligned (4)));
943
944 struct ipr_hostrcb_type_14_error {
945 struct ipr_ext_vpd ioa_vpd;
946 struct ipr_ext_vpd cfc_vpd;
947 __be32 exposed_mode_adn;
948 __be32 array_id;
949 struct ipr_res_addr last_func_vset_res_addr;
950 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
951 u8 protection_level[8];
952 __be32 num_entries;
953 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
954 }__attribute__((packed, aligned (4)));
955
956 struct ipr_hostrcb_type_24_error {
957 struct ipr_ext_vpd ioa_vpd;
958 struct ipr_ext_vpd cfc_vpd;
959 u8 reserved[2];
960 u8 exposed_mode_adn;
961 #define IPR_INVALID_ARRAY_DEV_NUM 0xff
962 u8 array_id;
963 u8 last_res_path[8];
964 u8 protection_level[8];
965 struct ipr_ext_vpd64 array_vpd;
966 u8 description[16];
967 u8 reserved2[3];
968 u8 num_entries;
969 struct ipr_hostrcb64_array_data_entry array_member[32];
970 }__attribute__((packed, aligned (4)));
971
972 struct ipr_hostrcb_type_07_error {
973 u8 failure_reason[64];
974 struct ipr_vpd vpd;
975 u32 data[222];
976 }__attribute__((packed, aligned (4)));
977
978 struct ipr_hostrcb_type_17_error {
979 u8 failure_reason[64];
980 struct ipr_ext_vpd vpd;
981 u32 data[476];
982 }__attribute__((packed, aligned (4)));
983
984 struct ipr_hostrcb_config_element {
985 u8 type_status;
986 #define IPR_PATH_CFG_TYPE_MASK 0xF0
987 #define IPR_PATH_CFG_NOT_EXIST 0x00
988 #define IPR_PATH_CFG_IOA_PORT 0x10
989 #define IPR_PATH_CFG_EXP_PORT 0x20
990 #define IPR_PATH_CFG_DEVICE_PORT 0x30
991 #define IPR_PATH_CFG_DEVICE_LUN 0x40
992
993 #define IPR_PATH_CFG_STATUS_MASK 0x0F
994 #define IPR_PATH_CFG_NO_PROB 0x00
995 #define IPR_PATH_CFG_DEGRADED 0x01
996 #define IPR_PATH_CFG_FAILED 0x02
997 #define IPR_PATH_CFG_SUSPECT 0x03
998 #define IPR_PATH_NOT_DETECTED 0x04
999 #define IPR_PATH_INCORRECT_CONN 0x05
1000
1001 u8 cascaded_expander;
1002 u8 phy;
1003 u8 link_rate;
1004 #define IPR_PHY_LINK_RATE_MASK 0x0F
1005
1006 __be32 wwid[2];
1007 }__attribute__((packed, aligned (4)));
1008
1009 struct ipr_hostrcb64_config_element {
1010 __be16 length;
1011 u8 descriptor_id;
1012 #define IPR_DESCRIPTOR_MASK 0xC0
1013 #define IPR_DESCRIPTOR_SIS64 0x00
1014
1015 u8 reserved;
1016 u8 type_status;
1017
1018 u8 reserved2[2];
1019 u8 link_rate;
1020
1021 u8 res_path[8];
1022 __be32 wwid[2];
1023 }__attribute__((packed, aligned (8)));
1024
1025 struct ipr_hostrcb_fabric_desc {
1026 __be16 length;
1027 u8 ioa_port;
1028 u8 cascaded_expander;
1029 u8 phy;
1030 u8 path_state;
1031 #define IPR_PATH_ACTIVE_MASK 0xC0
1032 #define IPR_PATH_NO_INFO 0x00
1033 #define IPR_PATH_ACTIVE 0x40
1034 #define IPR_PATH_NOT_ACTIVE 0x80
1035
1036 #define IPR_PATH_STATE_MASK 0x0F
1037 #define IPR_PATH_STATE_NO_INFO 0x00
1038 #define IPR_PATH_HEALTHY 0x01
1039 #define IPR_PATH_DEGRADED 0x02
1040 #define IPR_PATH_FAILED 0x03
1041
1042 __be16 num_entries;
1043 struct ipr_hostrcb_config_element elem[1];
1044 }__attribute__((packed, aligned (4)));
1045
1046 struct ipr_hostrcb64_fabric_desc {
1047 __be16 length;
1048 u8 descriptor_id;
1049
1050 u8 reserved[2];
1051 u8 path_state;
1052
1053 u8 reserved2[2];
1054 u8 res_path[8];
1055 u8 reserved3[6];
1056 __be16 num_entries;
1057 struct ipr_hostrcb64_config_element elem[1];
1058 }__attribute__((packed, aligned (8)));
1059
1060 #define for_each_fabric_cfg(fabric, cfg) \
1061 for (cfg = (fabric)->elem; \
1062 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1063 cfg++)
1064
1065 struct ipr_hostrcb_type_20_error {
1066 u8 failure_reason[64];
1067 u8 reserved[3];
1068 u8 num_entries;
1069 struct ipr_hostrcb_fabric_desc desc[1];
1070 }__attribute__((packed, aligned (4)));
1071
1072 struct ipr_hostrcb_type_30_error {
1073 u8 failure_reason[64];
1074 u8 reserved[3];
1075 u8 num_entries;
1076 struct ipr_hostrcb64_fabric_desc desc[1];
1077 }__attribute__((packed, aligned (4)));
1078
1079 struct ipr_hostrcb_error {
1080 __be32 fd_ioasc;
1081 struct ipr_res_addr fd_res_addr;
1082 __be32 fd_res_handle;
1083 __be32 prc;
1084 union {
1085 struct ipr_hostrcb_type_ff_error type_ff_error;
1086 struct ipr_hostrcb_type_01_error type_01_error;
1087 struct ipr_hostrcb_type_02_error type_02_error;
1088 struct ipr_hostrcb_type_03_error type_03_error;
1089 struct ipr_hostrcb_type_04_error type_04_error;
1090 struct ipr_hostrcb_type_07_error type_07_error;
1091 struct ipr_hostrcb_type_12_error type_12_error;
1092 struct ipr_hostrcb_type_13_error type_13_error;
1093 struct ipr_hostrcb_type_14_error type_14_error;
1094 struct ipr_hostrcb_type_17_error type_17_error;
1095 struct ipr_hostrcb_type_20_error type_20_error;
1096 } u;
1097 }__attribute__((packed, aligned (4)));
1098
1099 struct ipr_hostrcb64_error {
1100 __be32 fd_ioasc;
1101 __be32 ioa_fw_level;
1102 __be32 fd_res_handle;
1103 __be32 prc;
1104 __be64 fd_dev_id;
1105 __be64 fd_lun;
1106 u8 fd_res_path[8];
1107 __be64 time_stamp;
1108 u8 reserved[16];
1109 union {
1110 struct ipr_hostrcb_type_ff_error type_ff_error;
1111 struct ipr_hostrcb_type_12_error type_12_error;
1112 struct ipr_hostrcb_type_17_error type_17_error;
1113 struct ipr_hostrcb_type_23_error type_23_error;
1114 struct ipr_hostrcb_type_24_error type_24_error;
1115 struct ipr_hostrcb_type_30_error type_30_error;
1116 } u;
1117 }__attribute__((packed, aligned (8)));
1118
1119 struct ipr_hostrcb_raw {
1120 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1121 }__attribute__((packed, aligned (4)));
1122
1123 struct ipr_hcam {
1124 u8 op_code;
1125 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1126 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1127
1128 u8 notify_type;
1129 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1130 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1131 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1132 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1133 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1134
1135 u8 notifications_lost;
1136 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1137 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1138
1139 u8 flags;
1140 #define IPR_HOSTRCB_INTERNAL_OPER 0x80
1141 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1142
1143 u8 overlay_id;
1144 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1145 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1146 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1147 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1148 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06
1149 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07
1150 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1151 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1152 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1153 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1154 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17
1155 #define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1156 #define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1157 #define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1158 #define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1159 #define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1160 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1161
1162 u8 reserved1[3];
1163 __be32 ilid;
1164 __be32 time_since_last_ioa_reset;
1165 __be32 reserved2;
1166 __be32 length;
1167
1168 union {
1169 struct ipr_hostrcb_error error;
1170 struct ipr_hostrcb64_error error64;
1171 struct ipr_hostrcb_cfg_ch_not ccn;
1172 struct ipr_hostrcb_raw raw;
1173 } u;
1174 }__attribute__((packed, aligned (4)));
1175
1176 struct ipr_hostrcb {
1177 struct ipr_hcam hcam;
1178 dma_addr_t hostrcb_dma;
1179 struct list_head queue;
1180 struct ipr_ioa_cfg *ioa_cfg;
1181 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1182 };
1183
1184 /* IPR smart dump table structures */
1185 struct ipr_sdt_entry {
1186 __be32 start_token;
1187 __be32 end_token;
1188 u8 reserved[4];
1189
1190 u8 flags;
1191 #define IPR_SDT_ENDIAN 0x80
1192 #define IPR_SDT_VALID_ENTRY 0x20
1193
1194 u8 resv;
1195 __be16 priority;
1196 }__attribute__((packed, aligned (4)));
1197
1198 struct ipr_sdt_header {
1199 __be32 state;
1200 __be32 num_entries;
1201 __be32 num_entries_used;
1202 __be32 dump_size;
1203 }__attribute__((packed, aligned (4)));
1204
1205 struct ipr_sdt {
1206 struct ipr_sdt_header hdr;
1207 struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
1208 }__attribute__((packed, aligned (4)));
1209
1210 struct ipr_uc_sdt {
1211 struct ipr_sdt_header hdr;
1212 struct ipr_sdt_entry entry[1];
1213 }__attribute__((packed, aligned (4)));
1214
1215 /*
1216 * Driver types
1217 */
1218 struct ipr_bus_attributes {
1219 u8 bus;
1220 u8 qas_enabled;
1221 u8 bus_width;
1222 u8 reserved;
1223 u32 max_xfer_rate;
1224 };
1225
1226 struct ipr_sata_port {
1227 struct ipr_ioa_cfg *ioa_cfg;
1228 struct ata_port *ap;
1229 struct ipr_resource_entry *res;
1230 struct ipr_ioasa_gata ioasa;
1231 };
1232
1233 struct ipr_resource_entry {
1234 u8 needs_sync_complete:1;
1235 u8 in_erp:1;
1236 u8 add_to_ml:1;
1237 u8 del_from_ml:1;
1238 u8 resetting_device:1;
1239
1240 u32 bus; /* AKA channel */
1241 u32 target; /* AKA id */
1242 u32 lun;
1243 #define IPR_ARRAY_VIRTUAL_BUS 0x1
1244 #define IPR_VSET_VIRTUAL_BUS 0x2
1245 #define IPR_IOAFP_VIRTUAL_BUS 0x3
1246
1247 #define IPR_GET_RES_PHYS_LOC(res) \
1248 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1249
1250 u8 ata_class;
1251
1252 u8 flags;
1253 __be16 res_flags;
1254
1255 u8 type;
1256
1257 u8 qmodel;
1258 struct ipr_std_inq_data std_inq_data;
1259
1260 __be32 res_handle;
1261 __be64 dev_id;
1262 __be64 lun_wwn;
1263 struct scsi_lun dev_lun;
1264 u8 res_path[8];
1265
1266 struct ipr_ioa_cfg *ioa_cfg;
1267 struct scsi_device *sdev;
1268 struct ipr_sata_port *sata_port;
1269 struct list_head queue;
1270 }; /* struct ipr_resource_entry */
1271
1272 struct ipr_resource_hdr {
1273 u16 num_entries;
1274 u16 reserved;
1275 };
1276
1277 struct ipr_misc_cbs {
1278 struct ipr_ioa_vpd ioa_vpd;
1279 struct ipr_inquiry_page0 page0_data;
1280 struct ipr_inquiry_page3 page3_data;
1281 struct ipr_inquiry_cap cap;
1282 struct ipr_mode_pages mode_pages;
1283 struct ipr_supported_device supp_dev;
1284 };
1285
1286 struct ipr_interrupt_offsets {
1287 unsigned long set_interrupt_mask_reg;
1288 unsigned long clr_interrupt_mask_reg;
1289 unsigned long clr_interrupt_mask_reg32;
1290 unsigned long sense_interrupt_mask_reg;
1291 unsigned long sense_interrupt_mask_reg32;
1292 unsigned long clr_interrupt_reg;
1293 unsigned long clr_interrupt_reg32;
1294
1295 unsigned long sense_interrupt_reg;
1296 unsigned long sense_interrupt_reg32;
1297 unsigned long ioarrin_reg;
1298 unsigned long sense_uproc_interrupt_reg;
1299 unsigned long sense_uproc_interrupt_reg32;
1300 unsigned long set_uproc_interrupt_reg;
1301 unsigned long set_uproc_interrupt_reg32;
1302 unsigned long clr_uproc_interrupt_reg;
1303 unsigned long clr_uproc_interrupt_reg32;
1304
1305 unsigned long init_feedback_reg;
1306
1307 unsigned long dump_addr_reg;
1308 unsigned long dump_data_reg;
1309
1310 #define IPR_ENDIAN_SWAP_KEY 0x00080800
1311 unsigned long endian_swap_reg;
1312 };
1313
1314 struct ipr_interrupts {
1315 void __iomem *set_interrupt_mask_reg;
1316 void __iomem *clr_interrupt_mask_reg;
1317 void __iomem *clr_interrupt_mask_reg32;
1318 void __iomem *sense_interrupt_mask_reg;
1319 void __iomem *sense_interrupt_mask_reg32;
1320 void __iomem *clr_interrupt_reg;
1321 void __iomem *clr_interrupt_reg32;
1322
1323 void __iomem *sense_interrupt_reg;
1324 void __iomem *sense_interrupt_reg32;
1325 void __iomem *ioarrin_reg;
1326 void __iomem *sense_uproc_interrupt_reg;
1327 void __iomem *sense_uproc_interrupt_reg32;
1328 void __iomem *set_uproc_interrupt_reg;
1329 void __iomem *set_uproc_interrupt_reg32;
1330 void __iomem *clr_uproc_interrupt_reg;
1331 void __iomem *clr_uproc_interrupt_reg32;
1332
1333 void __iomem *init_feedback_reg;
1334
1335 void __iomem *dump_addr_reg;
1336 void __iomem *dump_data_reg;
1337
1338 void __iomem *endian_swap_reg;
1339 };
1340
1341 struct ipr_chip_cfg_t {
1342 u32 mailbox;
1343 u16 max_cmds;
1344 u8 cache_line_size;
1345 u8 clear_isr;
1346 struct ipr_interrupt_offsets regs;
1347 };
1348
1349 struct ipr_chip_t {
1350 u16 vendor;
1351 u16 device;
1352 u16 intr_type;
1353 #define IPR_USE_LSI 0x00
1354 #define IPR_USE_MSI 0x01
1355 #define IPR_USE_MSIX 0x02
1356 u16 sis_type;
1357 #define IPR_SIS32 0x00
1358 #define IPR_SIS64 0x01
1359 u16 bist_method;
1360 #define IPR_PCI_CFG 0x00
1361 #define IPR_MMIO 0x01
1362 const struct ipr_chip_cfg_t *cfg;
1363 };
1364
1365 enum ipr_shutdown_type {
1366 IPR_SHUTDOWN_NORMAL = 0x00,
1367 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1368 IPR_SHUTDOWN_ABBREV = 0x80,
1369 IPR_SHUTDOWN_NONE = 0x100
1370 };
1371
1372 struct ipr_trace_entry {
1373 u32 time;
1374
1375 u8 op_code;
1376 u8 ata_op_code;
1377 u8 type;
1378 #define IPR_TRACE_START 0x00
1379 #define IPR_TRACE_FINISH 0xff
1380 u8 cmd_index;
1381
1382 __be32 res_handle;
1383 union {
1384 u32 ioasc;
1385 u32 add_data;
1386 u32 res_addr;
1387 } u;
1388 };
1389
1390 struct ipr_sglist {
1391 u32 order;
1392 u32 num_sg;
1393 u32 num_dma_sg;
1394 u32 buffer_len;
1395 struct scatterlist scatterlist[1];
1396 };
1397
1398 enum ipr_sdt_state {
1399 INACTIVE,
1400 WAIT_FOR_DUMP,
1401 GET_DUMP,
1402 READ_DUMP,
1403 ABORT_DUMP,
1404 DUMP_OBTAINED
1405 };
1406
1407 /* Per-controller data */
1408 struct ipr_ioa_cfg {
1409 char eye_catcher[8];
1410 #define IPR_EYECATCHER "iprcfg"
1411
1412 struct list_head queue;
1413
1414 u8 allow_interrupts:1;
1415 u8 in_reset_reload:1;
1416 u8 in_ioa_bringdown:1;
1417 u8 ioa_unit_checked:1;
1418 u8 ioa_is_dead:1;
1419 u8 dump_taken:1;
1420 u8 allow_cmds:1;
1421 u8 allow_ml_add_del:1;
1422 u8 needs_hard_reset:1;
1423 u8 dual_raid:1;
1424 u8 needs_warm_reset:1;
1425 u8 msi_received:1;
1426 u8 sis64:1;
1427 u8 dump_timeout:1;
1428 u8 cfg_locked:1;
1429 u8 clear_isr:1;
1430
1431 u8 revid;
1432
1433 /*
1434 * Bitmaps for SIS64 generated target values
1435 */
1436 unsigned long *target_ids;
1437 unsigned long *array_ids;
1438 unsigned long *vset_ids;
1439
1440 u16 type; /* CCIN of the card */
1441
1442 u8 log_level;
1443 #define IPR_MAX_LOG_LEVEL 4
1444 #define IPR_DEFAULT_LOG_LEVEL 2
1445
1446 #define IPR_NUM_TRACE_INDEX_BITS 8
1447 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1448 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1449 char trace_start[8];
1450 #define IPR_TRACE_START_LABEL "trace"
1451 struct ipr_trace_entry *trace;
1452 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1453
1454 char cfg_table_start[8];
1455 #define IPR_CFG_TBL_START "cfg"
1456 union {
1457 struct ipr_config_table *cfg_table;
1458 struct ipr_config_table64 *cfg_table64;
1459 } u;
1460 dma_addr_t cfg_table_dma;
1461 u32 cfg_table_size;
1462 u32 max_devs_supported;
1463
1464 char resource_table_label[8];
1465 #define IPR_RES_TABLE_LABEL "res_tbl"
1466 struct ipr_resource_entry *res_entries;
1467 struct list_head free_res_q;
1468 struct list_head used_res_q;
1469
1470 char ipr_hcam_label[8];
1471 #define IPR_HCAM_LABEL "hcams"
1472 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1473 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1474 struct list_head hostrcb_free_q;
1475 struct list_head hostrcb_pending_q;
1476
1477 struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM];
1478 u32 hrrq_num;
1479 u32 hrrq_index;
1480
1481 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1482
1483 unsigned int transop_timeout;
1484 const struct ipr_chip_cfg_t *chip_cfg;
1485 const struct ipr_chip_t *ipr_chip;
1486
1487 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1488 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1489 void __iomem *ioa_mailbox;
1490 struct ipr_interrupts regs;
1491
1492 u16 saved_pcix_cmd_reg;
1493 u16 reset_retries;
1494
1495 u32 errors_logged;
1496 u32 doorbell;
1497
1498 struct Scsi_Host *host;
1499 struct pci_dev *pdev;
1500 struct ipr_sglist *ucode_sglist;
1501 u8 saved_mode_page_len;
1502
1503 struct work_struct work_q;
1504
1505 wait_queue_head_t reset_wait_q;
1506 wait_queue_head_t msi_wait_q;
1507
1508 struct ipr_dump *dump;
1509 enum ipr_sdt_state sdt_state;
1510
1511 struct ipr_misc_cbs *vpd_cbs;
1512 dma_addr_t vpd_cbs_dma;
1513
1514 struct pci_pool *ipr_cmd_pool;
1515
1516 struct ipr_cmnd *reset_cmd;
1517 int (*reset) (struct ipr_cmnd *);
1518
1519 struct ata_host ata_host;
1520 char ipr_cmd_label[8];
1521 #define IPR_CMD_LABEL "ipr_cmd"
1522 u32 max_cmds;
1523 struct ipr_cmnd **ipr_cmnd_list;
1524 dma_addr_t *ipr_cmnd_list_dma;
1525
1526 u16 intr_flag;
1527 unsigned int nvectors;
1528
1529 struct {
1530 unsigned short vec;
1531 char desc[22];
1532 } vectors_info[IPR_MAX_MSIX_VECTORS];
1533
1534 }; /* struct ipr_ioa_cfg */
1535
1536 struct ipr_cmnd {
1537 struct ipr_ioarcb ioarcb;
1538 union {
1539 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1540 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1541 struct ipr_ata64_ioadl ata_ioadl;
1542 } i;
1543 union {
1544 struct ipr_ioasa ioasa;
1545 struct ipr_ioasa64 ioasa64;
1546 } s;
1547 struct list_head queue;
1548 struct scsi_cmnd *scsi_cmd;
1549 struct ata_queued_cmd *qc;
1550 struct completion completion;
1551 struct timer_list timer;
1552 void (*fast_done) (struct ipr_cmnd *);
1553 void (*done) (struct ipr_cmnd *);
1554 int (*job_step) (struct ipr_cmnd *);
1555 int (*job_step_failed) (struct ipr_cmnd *);
1556 u16 cmd_index;
1557 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1558 dma_addr_t sense_buffer_dma;
1559 unsigned short dma_use_sg;
1560 dma_addr_t dma_addr;
1561 struct ipr_cmnd *sibling;
1562 union {
1563 enum ipr_shutdown_type shutdown_type;
1564 struct ipr_hostrcb *hostrcb;
1565 unsigned long time_left;
1566 unsigned long scratch;
1567 struct ipr_resource_entry *res;
1568 struct scsi_device *sdev;
1569 } u;
1570
1571 struct ipr_hrr_queue *hrrq;
1572 struct ipr_ioa_cfg *ioa_cfg;
1573 };
1574
1575 struct ipr_ses_table_entry {
1576 char product_id[17];
1577 char compare_product_id_byte[17];
1578 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1579 };
1580
1581 struct ipr_dump_header {
1582 u32 eye_catcher;
1583 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1584 u32 len;
1585 u32 num_entries;
1586 u32 first_entry_offset;
1587 u32 status;
1588 #define IPR_DUMP_STATUS_SUCCESS 0
1589 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1590 #define IPR_DUMP_STATUS_FAILED 0xffffffff
1591 u32 os;
1592 #define IPR_DUMP_OS_LINUX 0x4C4E5558
1593 u32 driver_name;
1594 #define IPR_DUMP_DRIVER_NAME 0x49505232
1595 }__attribute__((packed, aligned (4)));
1596
1597 struct ipr_dump_entry_header {
1598 u32 eye_catcher;
1599 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1600 u32 len;
1601 u32 num_elems;
1602 u32 offset;
1603 u32 data_type;
1604 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1605 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1606 u32 id;
1607 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1608 #define IPR_DUMP_LOCATION_ID 0x4C4F4341
1609 #define IPR_DUMP_TRACE_ID 0x54524143
1610 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1611 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1612 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1613 #define IPR_DUMP_PEND_OPS 0x414F5053
1614 u32 status;
1615 }__attribute__((packed, aligned (4)));
1616
1617 struct ipr_dump_location_entry {
1618 struct ipr_dump_entry_header hdr;
1619 u8 location[20];
1620 }__attribute__((packed));
1621
1622 struct ipr_dump_trace_entry {
1623 struct ipr_dump_entry_header hdr;
1624 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1625 }__attribute__((packed, aligned (4)));
1626
1627 struct ipr_dump_version_entry {
1628 struct ipr_dump_entry_header hdr;
1629 u8 version[sizeof(IPR_DRIVER_VERSION)];
1630 };
1631
1632 struct ipr_dump_ioa_type_entry {
1633 struct ipr_dump_entry_header hdr;
1634 u32 type;
1635 u32 fw_version;
1636 };
1637
1638 struct ipr_driver_dump {
1639 struct ipr_dump_header hdr;
1640 struct ipr_dump_version_entry version_entry;
1641 struct ipr_dump_location_entry location_entry;
1642 struct ipr_dump_ioa_type_entry ioa_type_entry;
1643 struct ipr_dump_trace_entry trace_entry;
1644 }__attribute__((packed));
1645
1646 struct ipr_ioa_dump {
1647 struct ipr_dump_entry_header hdr;
1648 struct ipr_sdt sdt;
1649 __be32 **ioa_data;
1650 u32 reserved;
1651 u32 next_page_index;
1652 u32 page_offset;
1653 u32 format;
1654 }__attribute__((packed, aligned (4)));
1655
1656 struct ipr_dump {
1657 struct kref kref;
1658 struct ipr_ioa_cfg *ioa_cfg;
1659 struct ipr_driver_dump driver_dump;
1660 struct ipr_ioa_dump ioa_dump;
1661 };
1662
1663 struct ipr_error_table_t {
1664 u32 ioasc;
1665 int log_ioasa;
1666 int log_hcam;
1667 char *error;
1668 };
1669
1670 struct ipr_software_inq_lid_info {
1671 __be32 load_id;
1672 __be32 timestamp[3];
1673 }__attribute__((packed, aligned (4)));
1674
1675 struct ipr_ucode_image_header {
1676 __be32 header_length;
1677 __be32 lid_table_offset;
1678 u8 major_release;
1679 u8 card_type;
1680 u8 minor_release[2];
1681 u8 reserved[20];
1682 char eyecatcher[16];
1683 __be32 num_lids;
1684 struct ipr_software_inq_lid_info lid[1];
1685 }__attribute__((packed, aligned (4)));
1686
1687 /*
1688 * Macros
1689 */
1690 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1691
1692 #ifdef CONFIG_SCSI_IPR_TRACE
1693 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1694 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1695 #else
1696 #define ipr_create_trace_file(kobj, attr) 0
1697 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1698 #endif
1699
1700 #ifdef CONFIG_SCSI_IPR_DUMP
1701 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1702 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1703 #else
1704 #define ipr_create_dump_file(kobj, attr) 0
1705 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1706 #endif
1707
1708 /*
1709 * Error logging macros
1710 */
1711 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1712 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1713 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1714
1715 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1716 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1717 bus, target, lun, ##__VA_ARGS__)
1718
1719 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1720 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1721
1722 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1723 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1724 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1725
1726 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1727 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1728
1729 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1730 { \
1731 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1732 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1733 } else { \
1734 ipr_err(fmt": %d:%d:%d:%d\n", \
1735 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1736 (res).bus, (res).target, (res).lun); \
1737 } \
1738 }
1739
1740 #define ipr_hcam_err(hostrcb, fmt, ...) \
1741 { \
1742 if (ipr_is_device(hostrcb)) { \
1743 if ((hostrcb)->ioa_cfg->sis64) { \
1744 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1745 ipr_format_res_path(hostrcb->ioa_cfg, \
1746 hostrcb->hcam.u.error64.fd_res_path, \
1747 hostrcb->rp_buffer, \
1748 sizeof(hostrcb->rp_buffer)), \
1749 __VA_ARGS__); \
1750 } else { \
1751 ipr_ra_err((hostrcb)->ioa_cfg, \
1752 (hostrcb)->hcam.u.error.fd_res_addr, \
1753 fmt, __VA_ARGS__); \
1754 } \
1755 } else { \
1756 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1757 } \
1758 }
1759
1760 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1761 __FILE__, __func__, __LINE__)
1762
1763 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1764 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1765
1766 #define ipr_err_separator \
1767 ipr_err("----------------------------------------------------------\n")
1768
1769
1770 /*
1771 * Inlines
1772 */
1773
1774 /**
1775 * ipr_is_ioa_resource - Determine if a resource is the IOA
1776 * @res: resource entry struct
1777 *
1778 * Return value:
1779 * 1 if IOA / 0 if not IOA
1780 **/
1781 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1782 {
1783 return res->type == IPR_RES_TYPE_IOAFP;
1784 }
1785
1786 /**
1787 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1788 * @res: resource entry struct
1789 *
1790 * Return value:
1791 * 1 if AF DASD / 0 if not AF DASD
1792 **/
1793 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1794 {
1795 return res->type == IPR_RES_TYPE_AF_DASD ||
1796 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1797 }
1798
1799 /**
1800 * ipr_is_vset_device - Determine if a resource is a VSET
1801 * @res: resource entry struct
1802 *
1803 * Return value:
1804 * 1 if VSET / 0 if not VSET
1805 **/
1806 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1807 {
1808 return res->type == IPR_RES_TYPE_VOLUME_SET;
1809 }
1810
1811 /**
1812 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1813 * @res: resource entry struct
1814 *
1815 * Return value:
1816 * 1 if GSCSI / 0 if not GSCSI
1817 **/
1818 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1819 {
1820 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1821 }
1822
1823 /**
1824 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1825 * @res: resource entry struct
1826 *
1827 * Return value:
1828 * 1 if SCSI disk / 0 if not SCSI disk
1829 **/
1830 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1831 {
1832 if (ipr_is_af_dasd_device(res) ||
1833 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1834 return 1;
1835 else
1836 return 0;
1837 }
1838
1839 /**
1840 * ipr_is_gata - Determine if a resource is a generic ATA resource
1841 * @res: resource entry struct
1842 *
1843 * Return value:
1844 * 1 if GATA / 0 if not GATA
1845 **/
1846 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1847 {
1848 return res->type == IPR_RES_TYPE_GENERIC_ATA;
1849 }
1850
1851 /**
1852 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1853 * @res: resource entry struct
1854 *
1855 * Return value:
1856 * 1 if NACA queueing model / 0 if not NACA queueing model
1857 **/
1858 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1859 {
1860 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1861 return 1;
1862 return 0;
1863 }
1864
1865 /**
1866 * ipr_is_device - Determine if the hostrcb structure is related to a device
1867 * @hostrcb: host resource control blocks struct
1868 *
1869 * Return value:
1870 * 1 if AF / 0 if not AF
1871 **/
1872 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1873 {
1874 struct ipr_res_addr *res_addr;
1875 u8 *res_path;
1876
1877 if (hostrcb->ioa_cfg->sis64) {
1878 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1879 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1880 res_path[0] == 0x81) && res_path[2] != 0xFF)
1881 return 1;
1882 } else {
1883 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1884
1885 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1886 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1887 return 1;
1888 }
1889 return 0;
1890 }
1891
1892 /**
1893 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1894 * @sdt_word: SDT address
1895 *
1896 * Return value:
1897 * 1 if format 2 / 0 if not
1898 **/
1899 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1900 {
1901 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1902
1903 switch (bar_sel) {
1904 case IPR_SDT_FMT2_BAR0_SEL:
1905 case IPR_SDT_FMT2_BAR1_SEL:
1906 case IPR_SDT_FMT2_BAR2_SEL:
1907 case IPR_SDT_FMT2_BAR3_SEL:
1908 case IPR_SDT_FMT2_BAR4_SEL:
1909 case IPR_SDT_FMT2_BAR5_SEL:
1910 case IPR_SDT_FMT2_EXP_ROM_SEL:
1911 return 1;
1912 };
1913
1914 return 0;
1915 }
1916
1917 #ifndef writeq
1918 static inline void writeq(u64 val, void __iomem *addr)
1919 {
1920 writel(((u32) (val >> 32)), addr);
1921 writel(((u32) (val)), (addr + 4));
1922 }
1923 #endif
1924
1925 #endif /* _IPR_H */
Linux kernel - Deliverables
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