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[deliverable/linux.git] / drivers / scsi / ips.c
1 /*****************************************************************************/
2 /* ips.c -- driver for the Adaptec / IBM ServeRAID controller */
3 /* */
4 /* Written By: Keith Mitchell, IBM Corporation */
5 /* Jack Hammer, Adaptec, Inc. */
6 /* David Jeffery, Adaptec, Inc. */
7 /* */
8 /* Copyright (C) 2000 IBM Corporation */
9 /* Copyright (C) 2002,2003 Adaptec, Inc. */
10 /* */
11 /* This program is free software; you can redistribute it and/or modify */
12 /* it under the terms of the GNU General Public License as published by */
13 /* the Free Software Foundation; either version 2 of the License, or */
14 /* (at your option) any later version. */
15 /* */
16 /* This program is distributed in the hope that it will be useful, */
17 /* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18 /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19 /* GNU General Public License for more details. */
20 /* */
21 /* NO WARRANTY */
22 /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23 /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24 /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25 /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26 /* solely responsible for determining the appropriateness of using and */
27 /* distributing the Program and assumes all risks associated with its */
28 /* exercise of rights under this Agreement, including but not limited to */
29 /* the risks and costs of program errors, damage to or loss of data, */
30 /* programs or equipment, and unavailability or interruption of operations. */
31 /* */
32 /* DISCLAIMER OF LIABILITY */
33 /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34 /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35 /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36 /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37 /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38 /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39 /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
40 /* */
41 /* You should have received a copy of the GNU General Public License */
42 /* along with this program; if not, write to the Free Software */
43 /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
44 /* */
45 /* Bugs/Comments/Suggestions about this driver should be mailed to: */
46 /* ipslinux@adaptec.com */
47 /* */
48 /* For system support issues, contact your local IBM Customer support. */
49 /* Directions to find IBM Customer Support for each country can be found at: */
50 /* http://www.ibm.com/planetwide/ */
51 /* */
52 /*****************************************************************************/
53
54 /*****************************************************************************/
55 /* Change Log */
56 /* */
57 /* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */
58 /* 0.99.03 - Make interrupt routine handle all completed request on the */
59 /* adapter not just the first one */
60 /* - Make sure passthru commands get woken up if we run out of */
61 /* SCBs */
62 /* - Send all of the commands on the queue at once rather than */
63 /* one at a time since the card will support it. */
64 /* 0.99.04 - Fix race condition in the passthru mechanism -- this required */
65 /* the interface to the utilities to change */
66 /* - Fix error recovery code */
67 /* 0.99.05 - Fix an oops when we get certain passthru commands */
68 /* 1.00.00 - Initial Public Release */
69 /* Functionally equivalent to 0.99.05 */
70 /* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */
71 /* - Change version to 3.60 to coincide with release numbering. */
72 /* 3.60.01 - Remove bogus error check in passthru routine */
73 /* 3.60.02 - Make DCDB direction based on lookup table */
74 /* - Only allow one DCDB command to a SCSI ID at a time */
75 /* 4.00.00 - Add support for ServeRAID 4 */
76 /* 4.00.01 - Add support for First Failure Data Capture */
77 /* 4.00.02 - Fix problem with PT DCDB with no buffer */
78 /* 4.00.03 - Add alternative passthru interface */
79 /* - Add ability to flash BIOS */
80 /* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */
81 /* 4.00.05 - Remove wish_block from init routine */
82 /* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */
83 /* 2.3.18 and later */
84 /* - Sync with other changes from the 2.3 kernels */
85 /* 4.00.06 - Fix timeout with initial FFDC command */
86 /* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */
87 /* 4.10.00 - Add support for ServeRAID 4M/4L */
88 /* 4.10.13 - Fix for dynamic unload and proc file system */
89 /* 4.20.03 - Rename version to coincide with new release schedules */
90 /* Performance fixes */
91 /* Fix truncation of /proc files with cat */
92 /* Merge in changes through kernel 2.4.0test1ac21 */
93 /* 4.20.13 - Fix some failure cases / reset code */
94 /* - Hook into the reboot_notifier to flush the controller cache */
95 /* 4.50.01 - Fix problem when there is a hole in logical drive numbering */
96 /* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */
97 /* - Add IPSSEND Flash Support */
98 /* - Set Sense Data for Unknown SCSI Command */
99 /* - Use Slot Number from NVRAM Page 5 */
100 /* - Restore caller's DCDB Structure */
101 /* 4.70.12 - Corrective actions for bad controller ( during initialization )*/
102 /* 4.70.13 - Don't Send CDB's if we already know the device is not present */
103 /* - Don't release HA Lock in ips_next() until SC taken off queue */
104 /* - Unregister SCSI device in ips_release() */
105 /* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */
106 /* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */
107 /* Code Clean-Up for 2.4.x kernel */
108 /* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */
109 /* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */
110 /* - Don't Issue Internal FFDC Command if there are Active Commands */
111 /* - Close Window for getting too many IOCTL's active */
112 /* 4.80.00 - Make ia64 Safe */
113 /* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */
114 /* - Adjustments to Device Queue Depth */
115 /* 4.80.14 - Take all semaphores off stack */
116 /* - Clean Up New_IOCTL path */
117 /* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */
118 /* - 5 second delay needed after resetting an i960 adapter */
119 /* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */
120 /* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */
121 /* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */
122 /* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */
123 /* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */
124 /* 4.90.11 - Don't actually RESET unless it's physically required */
125 /* - Remove unused compile options */
126 /* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */
127 /* - Get rid on IOCTL_NEW_COMMAND code */
128 /* - Add Extended DCDB Commands for Tape Support in 5I */
129 /* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */
130 /* 5.10.15 - remove unused code (sem, macros, etc.) */
131 /* 5.30.00 - use __devexit_p() */
132 /* 6.00.00 - Add 6x Adapters and Battery Flash */
133 /* 6.10.00 - Remove 1G Addressing Limitations */
134 /* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */
135 /* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */
136 /* 7.10.xx - Add highmem_io flag in SCSI Templete for 2.4 kernels */
137 /* - Fix path/name for scsi_hosts.h include for 2.6 kernels */
138 /* - Fix sort order of 7k */
139 /* - Remove 3 unused "inline" functions */
140 /*****************************************************************************/
141
142 /*
143 * Conditional Compilation directives for this driver:
144 *
145 * IPS_DEBUG - Turn on debugging info
146 *
147 * Parameters:
148 *
149 * debug:<number> - Set debug level to <number>
150 * NOTE: only works when IPS_DEBUG compile directive is used.
151 * 1 - Normal debug messages
152 * 2 - Verbose debug messages
153 * 11 - Method trace (non interrupt)
154 * 12 - Method trace (includes interrupt)
155 *
156 * noi2o - Don't use I2O Queues (ServeRAID 4 only)
157 * nommap - Don't use memory mapped I/O
158 * ioctlsize - Initial size of the IOCTL buffer
159 */
160
161 #include <asm/io.h>
162 #include <asm/byteorder.h>
163 #include <asm/page.h>
164 #include <linux/stddef.h>
165 #include <linux/version.h>
166 #include <linux/string.h>
167 #include <linux/errno.h>
168 #include <linux/kernel.h>
169 #include <linux/ioport.h>
170 #include <linux/slab.h>
171 #include <linux/delay.h>
172 #include <linux/pci.h>
173 #include <linux/proc_fs.h>
174 #include <linux/reboot.h>
175 #include <linux/interrupt.h>
176
177 #include <linux/blkdev.h>
178 #include <linux/types.h>
179
180 #include <scsi/sg.h>
181
182 #include "scsi.h"
183
184 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,0)
185 #include "hosts.h"
186 #else
187 #include <scsi/scsi_host.h>
188 #endif
189
190 #include "ips.h"
191
192 #include <linux/module.h>
193
194 #include <linux/stat.h>
195 #include <linux/config.h>
196
197 #include <linux/spinlock.h>
198 #include <linux/init.h>
199
200 #include <linux/smp.h>
201
202 #ifdef MODULE
203 static char *ips = NULL;
204 module_param(ips, charp, 0);
205 #endif
206
207 /*
208 * DRIVER_VER
209 */
210 #define IPS_VERSION_HIGH "7.10"
211 #define IPS_VERSION_LOW ".18 "
212
213 #if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__)
214 #warning "This driver has only been tested on the x86/ia64/x86_64 platforms"
215 #endif
216
217 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,0)
218 #include <linux/blk.h>
219 #include "sd.h"
220 #define IPS_SG_ADDRESS(sg) ((sg)->address)
221 #define IPS_LOCK_SAVE(lock,flags) spin_lock_irqsave(&io_request_lock,flags)
222 #define IPS_UNLOCK_RESTORE(lock,flags) spin_unlock_irqrestore(&io_request_lock,flags)
223 #ifndef __devexit_p
224 #define __devexit_p(x) x
225 #endif
226 #else
227 #define IPS_SG_ADDRESS(sg) (page_address((sg)->page) ? \
228 page_address((sg)->page)+(sg)->offset : NULL)
229 #define IPS_LOCK_SAVE(lock,flags) do{spin_lock(lock);(void)flags;}while(0)
230 #define IPS_UNLOCK_RESTORE(lock,flags) do{spin_unlock(lock);(void)flags;}while(0)
231 #endif
232
233 #define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \
234 DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \
235 PCI_DMA_BIDIRECTIONAL : \
236 scb->scsi_cmd->sc_data_direction)
237
238 #ifdef IPS_DEBUG
239 #define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n");
240 #define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n");
241 #define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v);
242 #else
243 #define METHOD_TRACE(s, i)
244 #define DEBUG(i, s)
245 #define DEBUG_VAR(i, s, v...)
246 #endif
247
248 /*
249 * Function prototypes
250 */
251 static int ips_detect(Scsi_Host_Template *);
252 static int ips_release(struct Scsi_Host *);
253 static int ips_eh_abort(Scsi_Cmnd *);
254 static int ips_eh_reset(Scsi_Cmnd *);
255 static int ips_queue(Scsi_Cmnd *, void (*)(Scsi_Cmnd *));
256 static const char *ips_info(struct Scsi_Host *);
257 static irqreturn_t do_ipsintr(int, void *, struct pt_regs *);
258 static int ips_hainit(ips_ha_t *);
259 static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *);
260 static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int);
261 static int ips_send_cmd(ips_ha_t *, ips_scb_t *);
262 static int ips_online(ips_ha_t *, ips_scb_t *);
263 static int ips_inquiry(ips_ha_t *, ips_scb_t *);
264 static int ips_rdcap(ips_ha_t *, ips_scb_t *);
265 static int ips_msense(ips_ha_t *, ips_scb_t *);
266 static int ips_reqsen(ips_ha_t *, ips_scb_t *);
267 static int ips_deallocatescbs(ips_ha_t *, int);
268 static int ips_allocatescbs(ips_ha_t *);
269 static int ips_reset_copperhead(ips_ha_t *);
270 static int ips_reset_copperhead_memio(ips_ha_t *);
271 static int ips_reset_morpheus(ips_ha_t *);
272 static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *);
273 static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *);
274 static int ips_issue_i2o(ips_ha_t *, ips_scb_t *);
275 static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *);
276 static int ips_isintr_copperhead(ips_ha_t *);
277 static int ips_isintr_copperhead_memio(ips_ha_t *);
278 static int ips_isintr_morpheus(ips_ha_t *);
279 static int ips_wait(ips_ha_t *, int, int);
280 static int ips_write_driver_status(ips_ha_t *, int);
281 static int ips_read_adapter_status(ips_ha_t *, int);
282 static int ips_read_subsystem_parameters(ips_ha_t *, int);
283 static int ips_read_config(ips_ha_t *, int);
284 static int ips_clear_adapter(ips_ha_t *, int);
285 static int ips_readwrite_page5(ips_ha_t *, int, int);
286 static int ips_init_copperhead(ips_ha_t *);
287 static int ips_init_copperhead_memio(ips_ha_t *);
288 static int ips_init_morpheus(ips_ha_t *);
289 static int ips_isinit_copperhead(ips_ha_t *);
290 static int ips_isinit_copperhead_memio(ips_ha_t *);
291 static int ips_isinit_morpheus(ips_ha_t *);
292 static int ips_erase_bios(ips_ha_t *);
293 static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t);
294 static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t);
295 static int ips_erase_bios_memio(ips_ha_t *);
296 static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
297 static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
298 static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
299 static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
300 static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
301 static void ips_free_flash_copperhead(ips_ha_t * ha);
302 static void ips_get_bios_version(ips_ha_t *, int);
303 static void ips_identify_controller(ips_ha_t *);
304 static void ips_chkstatus(ips_ha_t *, IPS_STATUS *);
305 static void ips_enable_int_copperhead(ips_ha_t *);
306 static void ips_enable_int_copperhead_memio(ips_ha_t *);
307 static void ips_enable_int_morpheus(ips_ha_t *);
308 static int ips_intr_copperhead(ips_ha_t *);
309 static int ips_intr_morpheus(ips_ha_t *);
310 static void ips_next(ips_ha_t *, int);
311 static void ipsintr_blocking(ips_ha_t *, struct ips_scb *);
312 static void ipsintr_done(ips_ha_t *, struct ips_scb *);
313 static void ips_done(ips_ha_t *, ips_scb_t *);
314 static void ips_free(ips_ha_t *);
315 static void ips_init_scb(ips_ha_t *, ips_scb_t *);
316 static void ips_freescb(ips_ha_t *, ips_scb_t *);
317 static void ips_setup_funclist(ips_ha_t *);
318 static void ips_statinit(ips_ha_t *);
319 static void ips_statinit_memio(ips_ha_t *);
320 static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time_t);
321 static void ips_ffdc_reset(ips_ha_t *, int);
322 static void ips_ffdc_time(ips_ha_t *);
323 static uint32_t ips_statupd_copperhead(ips_ha_t *);
324 static uint32_t ips_statupd_copperhead_memio(ips_ha_t *);
325 static uint32_t ips_statupd_morpheus(ips_ha_t *);
326 static ips_scb_t *ips_getscb(ips_ha_t *);
327 static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *);
328 static void ips_putq_wait_tail(ips_wait_queue_t *, Scsi_Cmnd *);
329 static void ips_putq_copp_tail(ips_copp_queue_t *,
330 ips_copp_wait_item_t *);
331 static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *);
332 static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *);
333 static Scsi_Cmnd *ips_removeq_wait_head(ips_wait_queue_t *);
334 static Scsi_Cmnd *ips_removeq_wait(ips_wait_queue_t *, Scsi_Cmnd *);
335 static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *,
336 ips_copp_wait_item_t *);
337 static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *);
338
339 static int ips_is_passthru(Scsi_Cmnd *);
340 static int ips_make_passthru(ips_ha_t *, Scsi_Cmnd *, ips_scb_t *, int);
341 static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
342 static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *);
343 static void ips_scmd_buf_write(Scsi_Cmnd * scmd, void *data,
344 unsigned int count);
345 static void ips_scmd_buf_read(Scsi_Cmnd * scmd, void *data, unsigned int count);
346
347 static int ips_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int);
348 static int ips_host_info(ips_ha_t *, char *, off_t, int);
349 static void copy_mem_info(IPS_INFOSTR *, char *, int);
350 static int copy_info(IPS_INFOSTR *, char *, ...);
351 static int ips_get_version_info(ips_ha_t * ha, dma_addr_t, int intr);
352 static void ips_version_check(ips_ha_t * ha, int intr);
353 static int ips_abort_init(ips_ha_t * ha, int index);
354 static int ips_init_phase2(int index);
355
356 static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr);
357 static int ips_register_scsi(int index);
358
359 /*
360 * global variables
361 */
362 static const char ips_name[] = "ips";
363 static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */
364 static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */
365 static unsigned int ips_next_controller;
366 static unsigned int ips_num_controllers;
367 static unsigned int ips_released_controllers;
368 static int ips_hotplug;
369 static int ips_cmd_timeout = 60;
370 static int ips_reset_timeout = 60 * 5;
371 static int ips_force_memio = 1; /* Always use Memory Mapped I/O */
372 static int ips_force_i2o = 1; /* Always use I2O command delivery */
373 static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */
374 static int ips_cd_boot; /* Booting from Manager CD */
375 static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */
376 static dma_addr_t ips_flashbusaddr;
377 static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */
378 static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */
379 static Scsi_Host_Template ips_driver_template = {
380 .detect = ips_detect,
381 .release = ips_release,
382 .info = ips_info,
383 .queuecommand = ips_queue,
384 .eh_abort_handler = ips_eh_abort,
385 .eh_host_reset_handler = ips_eh_reset,
386 .proc_name = "ips",
387 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
388 .proc_info = ips_proc_info,
389 .slave_configure = ips_slave_configure,
390 #else
391 .proc_info = ips_proc24_info,
392 .select_queue_depths = ips_select_queue_depth,
393 #endif
394 .bios_param = ips_biosparam,
395 .this_id = -1,
396 .sg_tablesize = IPS_MAX_SG,
397 .cmd_per_lun = 3,
398 .use_clustering = ENABLE_CLUSTERING,
399 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
400 .use_new_eh_code = 1,
401 #endif
402 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
403 .highmem_io = 1,
404 #endif
405 };
406
407 static IPS_DEFINE_COMPAT_TABLE( Compatable ); /* Version Compatability Table */
408
409
410 /* This table describes all ServeRAID Adapters */
411 static struct pci_device_id ips_pci_table[] = {
412 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
413 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
414 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
415 { 0, }
416 };
417
418 MODULE_DEVICE_TABLE( pci, ips_pci_table );
419
420 static char ips_hot_plug_name[] = "ips";
421
422 static int __devinit ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent);
423 static void __devexit ips_remove_device(struct pci_dev *pci_dev);
424
425 static struct pci_driver ips_pci_driver = {
426 .name = ips_hot_plug_name,
427 .id_table = ips_pci_table,
428 .probe = ips_insert_device,
429 .remove = __devexit_p(ips_remove_device),
430 };
431
432
433 /*
434 * Necessary forward function protoypes
435 */
436 static int ips_halt(struct notifier_block *nb, ulong event, void *buf);
437
438 #define MAX_ADAPTER_NAME 15
439
440 static char ips_adapter_name[][30] = {
441 "ServeRAID",
442 "ServeRAID II",
443 "ServeRAID on motherboard",
444 "ServeRAID on motherboard",
445 "ServeRAID 3H",
446 "ServeRAID 3L",
447 "ServeRAID 4H",
448 "ServeRAID 4M",
449 "ServeRAID 4L",
450 "ServeRAID 4Mx",
451 "ServeRAID 4Lx",
452 "ServeRAID 5i",
453 "ServeRAID 5i",
454 "ServeRAID 6M",
455 "ServeRAID 6i",
456 "ServeRAID 7t",
457 "ServeRAID 7k",
458 "ServeRAID 7M"
459 };
460
461 static struct notifier_block ips_notifier = {
462 ips_halt, NULL, 0
463 };
464
465 /*
466 * Direction table
467 */
468 static char ips_command_direction[] = {
469 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT,
470 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK,
471 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
472 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
473 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT,
474 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
475 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN,
476 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
477 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK,
478 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
479 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE,
480 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
481 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT,
482 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE,
483 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK,
484 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
485 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
486 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
487 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
488 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
489 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
490 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
491 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
492 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
493 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
494 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
495 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
496 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
497 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
498 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
499 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
500 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
501 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
502 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE,
503 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT,
504 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE,
505 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN,
506 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
507 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
508 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
509 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
510 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
511 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
512 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
513 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
514 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
515 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT,
516 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
517 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
518 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
519 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK
520 };
521
522
523 /****************************************************************************/
524 /* */
525 /* Routine Name: ips_setup */
526 /* */
527 /* Routine Description: */
528 /* */
529 /* setup parameters to the driver */
530 /* */
531 /****************************************************************************/
532 static int
533 ips_setup(char *ips_str)
534 {
535
536 int i;
537 char *key;
538 char *value;
539 IPS_OPTION options[] = {
540 {"noi2o", &ips_force_i2o, 0},
541 {"nommap", &ips_force_memio, 0},
542 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE},
543 {"cdboot", &ips_cd_boot, 0},
544 {"maxcmds", &MaxLiteCmds, 32},
545 };
546
547 /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */
548 /* Search for value */
549 while ((key = strsep(&ips_str, ",."))) {
550 if (!*key)
551 continue;
552 value = strchr(key, ':');
553 if (value)
554 *value++ = '\0';
555 /*
556 * We now have key/value pairs.
557 * Update the variables
558 */
559 for (i = 0; i < (sizeof (options) / sizeof (options[0])); i++) {
560 if (strnicmp
561 (key, options[i].option_name,
562 strlen(options[i].option_name)) == 0) {
563 if (value)
564 *options[i].option_flag =
565 simple_strtoul(value, NULL, 0);
566 else
567 *options[i].option_flag =
568 options[i].option_value;
569 break;
570 }
571 }
572 }
573
574 return (1);
575 }
576
577 __setup("ips=", ips_setup);
578
579 /****************************************************************************/
580 /* */
581 /* Routine Name: ips_detect */
582 /* */
583 /* Routine Description: */
584 /* */
585 /* Detect and initialize the driver */
586 /* */
587 /* NOTE: this routine is called under the io_request_lock spinlock */
588 /* */
589 /****************************************************************************/
590 static int
591 ips_detect(Scsi_Host_Template * SHT)
592 {
593 int i;
594
595 METHOD_TRACE("ips_detect", 1);
596
597 #ifdef MODULE
598 if (ips)
599 ips_setup(ips);
600 #endif
601
602 for (i = 0; i < ips_num_controllers; i++) {
603 if (ips_register_scsi(i))
604 ips_free(ips_ha[i]);
605 ips_released_controllers++;
606 }
607 ips_hotplug = 1;
608 return (ips_num_controllers);
609 }
610
611 /****************************************************************************/
612 /* configure the function pointers to use the functions that will work */
613 /* with the found version of the adapter */
614 /****************************************************************************/
615 static void
616 ips_setup_funclist(ips_ha_t * ha)
617 {
618
619 /*
620 * Setup Functions
621 */
622 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
623 /* morpheus / marco / sebring */
624 ha->func.isintr = ips_isintr_morpheus;
625 ha->func.isinit = ips_isinit_morpheus;
626 ha->func.issue = ips_issue_i2o_memio;
627 ha->func.init = ips_init_morpheus;
628 ha->func.statupd = ips_statupd_morpheus;
629 ha->func.reset = ips_reset_morpheus;
630 ha->func.intr = ips_intr_morpheus;
631 ha->func.enableint = ips_enable_int_morpheus;
632 } else if (IPS_USE_MEMIO(ha)) {
633 /* copperhead w/MEMIO */
634 ha->func.isintr = ips_isintr_copperhead_memio;
635 ha->func.isinit = ips_isinit_copperhead_memio;
636 ha->func.init = ips_init_copperhead_memio;
637 ha->func.statupd = ips_statupd_copperhead_memio;
638 ha->func.statinit = ips_statinit_memio;
639 ha->func.reset = ips_reset_copperhead_memio;
640 ha->func.intr = ips_intr_copperhead;
641 ha->func.erasebios = ips_erase_bios_memio;
642 ha->func.programbios = ips_program_bios_memio;
643 ha->func.verifybios = ips_verify_bios_memio;
644 ha->func.enableint = ips_enable_int_copperhead_memio;
645 if (IPS_USE_I2O_DELIVER(ha))
646 ha->func.issue = ips_issue_i2o_memio;
647 else
648 ha->func.issue = ips_issue_copperhead_memio;
649 } else {
650 /* copperhead */
651 ha->func.isintr = ips_isintr_copperhead;
652 ha->func.isinit = ips_isinit_copperhead;
653 ha->func.init = ips_init_copperhead;
654 ha->func.statupd = ips_statupd_copperhead;
655 ha->func.statinit = ips_statinit;
656 ha->func.reset = ips_reset_copperhead;
657 ha->func.intr = ips_intr_copperhead;
658 ha->func.erasebios = ips_erase_bios;
659 ha->func.programbios = ips_program_bios;
660 ha->func.verifybios = ips_verify_bios;
661 ha->func.enableint = ips_enable_int_copperhead;
662
663 if (IPS_USE_I2O_DELIVER(ha))
664 ha->func.issue = ips_issue_i2o;
665 else
666 ha->func.issue = ips_issue_copperhead;
667 }
668 }
669
670 /****************************************************************************/
671 /* */
672 /* Routine Name: ips_release */
673 /* */
674 /* Routine Description: */
675 /* */
676 /* Remove a driver */
677 /* */
678 /****************************************************************************/
679 static int
680 ips_release(struct Scsi_Host *sh)
681 {
682 ips_scb_t *scb;
683 ips_ha_t *ha;
684 int i;
685
686 METHOD_TRACE("ips_release", 1);
687
688 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ;
689
690 if (i == IPS_MAX_ADAPTERS) {
691 printk(KERN_WARNING
692 "(%s) release, invalid Scsi_Host pointer.\n", ips_name);
693 BUG();
694 return (FALSE);
695 }
696
697 ha = IPS_HA(sh);
698
699 if (!ha)
700 return (FALSE);
701
702 /* flush the cache on the controller */
703 scb = &ha->scbs[ha->max_cmds - 1];
704
705 ips_init_scb(ha, scb);
706
707 scb->timeout = ips_cmd_timeout;
708 scb->cdb[0] = IPS_CMD_FLUSH;
709
710 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
711 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
712 scb->cmd.flush_cache.state = IPS_NORM_STATE;
713 scb->cmd.flush_cache.reserved = 0;
714 scb->cmd.flush_cache.reserved2 = 0;
715 scb->cmd.flush_cache.reserved3 = 0;
716 scb->cmd.flush_cache.reserved4 = 0;
717
718 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
719
720 /* send command */
721 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
722 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n");
723
724 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n");
725
726 ips_sh[i] = NULL;
727 ips_ha[i] = NULL;
728
729 /* free extra memory */
730 ips_free(ha);
731
732 /* Free I/O Region */
733 if (ha->io_addr)
734 release_region(ha->io_addr, ha->io_len);
735
736 /* free IRQ */
737 free_irq(ha->irq, ha);
738
739 IPS_REMOVE_HOST(sh);
740 scsi_host_put(sh);
741
742 ips_released_controllers++;
743
744 return (FALSE);
745 }
746
747 /****************************************************************************/
748 /* */
749 /* Routine Name: ips_halt */
750 /* */
751 /* Routine Description: */
752 /* */
753 /* Perform cleanup when the system reboots */
754 /* */
755 /****************************************************************************/
756 static int
757 ips_halt(struct notifier_block *nb, ulong event, void *buf)
758 {
759 ips_scb_t *scb;
760 ips_ha_t *ha;
761 int i;
762
763 if ((event != SYS_RESTART) && (event != SYS_HALT) &&
764 (event != SYS_POWER_OFF))
765 return (NOTIFY_DONE);
766
767 for (i = 0; i < ips_next_controller; i++) {
768 ha = (ips_ha_t *) ips_ha[i];
769
770 if (!ha)
771 continue;
772
773 if (!ha->active)
774 continue;
775
776 /* flush the cache on the controller */
777 scb = &ha->scbs[ha->max_cmds - 1];
778
779 ips_init_scb(ha, scb);
780
781 scb->timeout = ips_cmd_timeout;
782 scb->cdb[0] = IPS_CMD_FLUSH;
783
784 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
785 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
786 scb->cmd.flush_cache.state = IPS_NORM_STATE;
787 scb->cmd.flush_cache.reserved = 0;
788 scb->cmd.flush_cache.reserved2 = 0;
789 scb->cmd.flush_cache.reserved3 = 0;
790 scb->cmd.flush_cache.reserved4 = 0;
791
792 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
793
794 /* send command */
795 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
796 IPS_FAILURE)
797 IPS_PRINTK(KERN_WARNING, ha->pcidev,
798 "Incomplete Flush.\n");
799 else
800 IPS_PRINTK(KERN_WARNING, ha->pcidev,
801 "Flushing Complete.\n");
802 }
803
804 return (NOTIFY_OK);
805 }
806
807 /****************************************************************************/
808 /* */
809 /* Routine Name: ips_eh_abort */
810 /* */
811 /* Routine Description: */
812 /* */
813 /* Abort a command (using the new error code stuff) */
814 /* Note: this routine is called under the io_request_lock */
815 /****************************************************************************/
816 int
817 ips_eh_abort(Scsi_Cmnd * SC)
818 {
819 ips_ha_t *ha;
820 ips_copp_wait_item_t *item;
821 int ret;
822
823 METHOD_TRACE("ips_eh_abort", 1);
824
825 if (!SC)
826 return (FAILED);
827
828 ha = (ips_ha_t *) SC->device->host->hostdata;
829
830 if (!ha)
831 return (FAILED);
832
833 if (!ha->active)
834 return (FAILED);
835
836 /* See if the command is on the copp queue */
837 item = ha->copp_waitlist.head;
838 while ((item) && (item->scsi_cmd != SC))
839 item = item->next;
840
841 if (item) {
842 /* Found it */
843 ips_removeq_copp(&ha->copp_waitlist, item);
844 ret = (SUCCESS);
845
846 /* See if the command is on the wait queue */
847 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
848 /* command not sent yet */
849 ret = (SUCCESS);
850 } else {
851 /* command must have already been sent */
852 ret = (FAILED);
853 }
854 return ret;
855 }
856
857 /****************************************************************************/
858 /* */
859 /* Routine Name: ips_eh_reset */
860 /* */
861 /* Routine Description: */
862 /* */
863 /* Reset the controller (with new eh error code) */
864 /* */
865 /* NOTE: this routine is called under the io_request_lock spinlock */
866 /* */
867 /****************************************************************************/
868 static int
869 ips_eh_reset(Scsi_Cmnd * SC)
870 {
871 int ret;
872 int i;
873 ips_ha_t *ha;
874 ips_scb_t *scb;
875 ips_copp_wait_item_t *item;
876
877 METHOD_TRACE("ips_eh_reset", 1);
878
879 #ifdef NO_IPS_RESET
880 return (FAILED);
881 #else
882
883 if (!SC) {
884 DEBUG(1, "Reset called with NULL scsi command");
885
886 return (FAILED);
887 }
888
889 ha = (ips_ha_t *) SC->device->host->hostdata;
890
891 if (!ha) {
892 DEBUG(1, "Reset called with NULL ha struct");
893
894 return (FAILED);
895 }
896
897 if (!ha->active)
898 return (FAILED);
899
900 /* See if the command is on the copp queue */
901 item = ha->copp_waitlist.head;
902 while ((item) && (item->scsi_cmd != SC))
903 item = item->next;
904
905 if (item) {
906 /* Found it */
907 ips_removeq_copp(&ha->copp_waitlist, item);
908 return (SUCCESS);
909 }
910
911 /* See if the command is on the wait queue */
912 if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
913 /* command not sent yet */
914 return (SUCCESS);
915 }
916
917 /* An explanation for the casual observer: */
918 /* Part of the function of a RAID controller is automatic error */
919 /* detection and recovery. As such, the only problem that physically */
920 /* resetting an adapter will ever fix is when, for some reason, */
921 /* the driver is not successfully communicating with the adapter. */
922 /* Therefore, we will attempt to flush this adapter. If that succeeds, */
923 /* then there's no real purpose in a physical reset. This will complete */
924 /* much faster and avoids any problems that might be caused by a */
925 /* physical reset ( such as having to fail all the outstanding I/O's ). */
926
927 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */
928 scb = &ha->scbs[ha->max_cmds - 1];
929
930 ips_init_scb(ha, scb);
931
932 scb->timeout = ips_cmd_timeout;
933 scb->cdb[0] = IPS_CMD_FLUSH;
934
935 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
936 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
937 scb->cmd.flush_cache.state = IPS_NORM_STATE;
938 scb->cmd.flush_cache.reserved = 0;
939 scb->cmd.flush_cache.reserved2 = 0;
940 scb->cmd.flush_cache.reserved3 = 0;
941 scb->cmd.flush_cache.reserved4 = 0;
942
943 /* Attempt the flush command */
944 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
945 if (ret == IPS_SUCCESS) {
946 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
947 "Reset Request - Flushed Cache\n");
948 return (SUCCESS);
949 }
950 }
951
952 /* Either we can't communicate with the adapter or it's an IOCTL request */
953 /* from a utility. A physical reset is needed at this point. */
954
955 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */
956
957 /*
958 * command must have already been sent
959 * reset the controller
960 */
961 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n");
962 ret = (*ha->func.reset) (ha);
963
964 if (!ret) {
965 Scsi_Cmnd *scsi_cmd;
966
967 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
968 "Controller reset failed - controller now offline.\n");
969
970 /* Now fail all of the active commands */
971 DEBUG_VAR(1, "(%s%d) Failing active commands",
972 ips_name, ha->host_num);
973
974 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
975 scb->scsi_cmd->result = DID_ERROR << 16;
976 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
977 ips_freescb(ha, scb);
978 }
979
980 /* Now fail all of the pending commands */
981 DEBUG_VAR(1, "(%s%d) Failing pending commands",
982 ips_name, ha->host_num);
983
984 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
985 scsi_cmd->result = DID_ERROR;
986 scsi_cmd->scsi_done(scsi_cmd);
987 }
988
989 ha->active = FALSE;
990 return (FAILED);
991 }
992
993 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
994 Scsi_Cmnd *scsi_cmd;
995
996 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
997 "Controller reset failed - controller now offline.\n");
998
999 /* Now fail all of the active commands */
1000 DEBUG_VAR(1, "(%s%d) Failing active commands",
1001 ips_name, ha->host_num);
1002
1003 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1004 scb->scsi_cmd->result = DID_ERROR << 16;
1005 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
1006 ips_freescb(ha, scb);
1007 }
1008
1009 /* Now fail all of the pending commands */
1010 DEBUG_VAR(1, "(%s%d) Failing pending commands",
1011 ips_name, ha->host_num);
1012
1013 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
1014 scsi_cmd->result = DID_ERROR << 16;
1015 scsi_cmd->scsi_done(scsi_cmd);
1016 }
1017
1018 ha->active = FALSE;
1019 return (FAILED);
1020 }
1021
1022 /* FFDC */
1023 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
1024 struct timeval tv;
1025
1026 do_gettimeofday(&tv);
1027 ha->last_ffdc = tv.tv_sec;
1028 ha->reset_count++;
1029 ips_ffdc_reset(ha, IPS_INTR_IORL);
1030 }
1031
1032 /* Now fail all of the active commands */
1033 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
1034
1035 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1036 scb->scsi_cmd->result =
1037 (DID_RESET << 16) | (SUGGEST_RETRY << 24);
1038 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
1039 ips_freescb(ha, scb);
1040 }
1041
1042 /* Reset DCDB active command bits */
1043 for (i = 1; i < ha->nbus; i++)
1044 ha->dcdb_active[i - 1] = 0;
1045
1046 /* Reset the number of active IOCTLs */
1047 ha->num_ioctl = 0;
1048
1049 ips_next(ha, IPS_INTR_IORL);
1050
1051 return (SUCCESS);
1052 #endif /* NO_IPS_RESET */
1053
1054 }
1055
1056 /****************************************************************************/
1057 /* */
1058 /* Routine Name: ips_queue */
1059 /* */
1060 /* Routine Description: */
1061 /* */
1062 /* Send a command to the controller */
1063 /* */
1064 /* NOTE: */
1065 /* Linux obtains io_request_lock before calling this function */
1066 /* */
1067 /****************************************************************************/
1068 static int
1069 ips_queue(Scsi_Cmnd * SC, void (*done) (Scsi_Cmnd *))
1070 {
1071 ips_ha_t *ha;
1072 ips_passthru_t *pt;
1073
1074 METHOD_TRACE("ips_queue", 1);
1075
1076 ha = (ips_ha_t *) SC->device->host->hostdata;
1077
1078 if (!ha)
1079 return (1);
1080
1081 if (!ha->active)
1082 return (DID_ERROR);
1083
1084 if (ips_is_passthru(SC)) {
1085 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
1086 SC->result = DID_BUS_BUSY << 16;
1087 done(SC);
1088
1089 return (0);
1090 }
1091 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
1092 SC->result = DID_BUS_BUSY << 16;
1093 done(SC);
1094
1095 return (0);
1096 }
1097
1098 SC->scsi_done = done;
1099
1100 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)",
1101 ips_name,
1102 ha->host_num,
1103 SC->cmnd[0],
1104 SC->device->channel, SC->device->id, SC->device->lun);
1105
1106 /* Check for command to initiator IDs */
1107 if ((SC->device->channel > 0)
1108 && (SC->device->id == ha->ha_id[SC->device->channel])) {
1109 SC->result = DID_NO_CONNECT << 16;
1110 done(SC);
1111
1112 return (0);
1113 }
1114
1115 if (ips_is_passthru(SC)) {
1116
1117 ips_copp_wait_item_t *scratch;
1118
1119 /* A Reset IOCTL is only sent by the boot CD in extreme cases. */
1120 /* There can never be any system activity ( network or disk ), but check */
1121 /* anyway just as a good practice. */
1122 pt = (ips_passthru_t *) SC->request_buffer;
1123 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) &&
1124 (pt->CoppCP.cmd.reset.adapter_flag == 1)) {
1125 if (ha->scb_activelist.count != 0) {
1126 SC->result = DID_BUS_BUSY << 16;
1127 done(SC);
1128 return (0);
1129 }
1130 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */
1131 ips_eh_reset(SC);
1132 SC->result = DID_OK << 16;
1133 SC->scsi_done(SC);
1134 return (0);
1135 }
1136
1137 /* allocate space for the scribble */
1138 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC);
1139
1140 if (!scratch) {
1141 SC->result = DID_ERROR << 16;
1142 done(SC);
1143
1144 return (0);
1145 }
1146
1147 scratch->scsi_cmd = SC;
1148 scratch->next = NULL;
1149
1150 ips_putq_copp_tail(&ha->copp_waitlist, scratch);
1151 } else {
1152 ips_putq_wait_tail(&ha->scb_waitlist, SC);
1153 }
1154
1155 ips_next(ha, IPS_INTR_IORL);
1156
1157 return (0);
1158 }
1159
1160 /****************************************************************************/
1161 /* */
1162 /* Routine Name: ips_biosparam */
1163 /* */
1164 /* Routine Description: */
1165 /* */
1166 /* Set bios geometry for the controller */
1167 /* */
1168 /****************************************************************************/
1169 static int
1170 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1171 ips_biosparam(Disk * disk, kdev_t dev, int geom[])
1172 {
1173 ips_ha_t *ha = (ips_ha_t *) disk->device->host->hostdata;
1174 unsigned long capacity = disk->capacity;
1175 #else
1176 ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
1177 sector_t capacity, int geom[])
1178 {
1179 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata;
1180 #endif
1181 int heads;
1182 int sectors;
1183 int cylinders;
1184
1185 METHOD_TRACE("ips_biosparam", 1);
1186
1187 if (!ha)
1188 /* ?!?! host adater info invalid */
1189 return (0);
1190
1191 if (!ha->active)
1192 return (0);
1193
1194 if (!ips_read_adapter_status(ha, IPS_INTR_ON))
1195 /* ?!?! Enquiry command failed */
1196 return (0);
1197
1198 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
1199 heads = IPS_NORM_HEADS;
1200 sectors = IPS_NORM_SECTORS;
1201 } else {
1202 heads = IPS_COMP_HEADS;
1203 sectors = IPS_COMP_SECTORS;
1204 }
1205
1206 cylinders = (unsigned long) capacity / (heads * sectors);
1207
1208 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d",
1209 heads, sectors, cylinders);
1210
1211 geom[0] = heads;
1212 geom[1] = sectors;
1213 geom[2] = cylinders;
1214
1215 return (0);
1216 }
1217
1218 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1219
1220 /* ips_proc24_info is a wrapper around ips_proc_info *
1221 * for compatibility with the 2.4 scsi parameters */
1222 static int
1223 ips_proc24_info(char *buffer, char **start, off_t offset, int length,
1224 int hostno, int func)
1225 {
1226 int i;
1227
1228 for (i = 0; i < ips_next_controller; i++) {
1229 if (ips_sh[i] && ips_sh[i]->host_no == hostno) {
1230 return ips_proc_info(ips_sh[i], buffer, start,
1231 offset, length, func);
1232 }
1233 }
1234 return -EINVAL;
1235 }
1236
1237 /****************************************************************************/
1238 /* */
1239 /* Routine Name: ips_select_queue_depth */
1240 /* */
1241 /* Routine Description: */
1242 /* */
1243 /* Select queue depths for the devices on the contoller */
1244 /* */
1245 /****************************************************************************/
1246 static void
1247 ips_select_queue_depth(struct Scsi_Host *host, Scsi_Device * scsi_devs)
1248 {
1249 Scsi_Device *device;
1250 ips_ha_t *ha;
1251 int count = 0;
1252 int min;
1253
1254 ha = IPS_HA(host);
1255 min = ha->max_cmds / 4;
1256
1257 for (device = scsi_devs; device; device = device->next) {
1258 if (device->host == host) {
1259 if ((device->channel == 0) && (device->type == 0))
1260 count++;
1261 }
1262 }
1263
1264 for (device = scsi_devs; device; device = device->next) {
1265 if (device->host == host) {
1266 if ((device->channel == 0) && (device->type == 0)) {
1267 device->queue_depth =
1268 (ha->max_cmds - 1) / count;
1269 if (device->queue_depth < min)
1270 device->queue_depth = min;
1271 } else {
1272 device->queue_depth = 2;
1273 }
1274
1275 if (device->queue_depth < 2)
1276 device->queue_depth = 2;
1277 }
1278 }
1279 }
1280
1281 #else
1282 /****************************************************************************/
1283 /* */
1284 /* Routine Name: ips_slave_configure */
1285 /* */
1286 /* Routine Description: */
1287 /* */
1288 /* Set queue depths on devices once scan is complete */
1289 /* */
1290 /****************************************************************************/
1291 static int
1292 ips_slave_configure(Scsi_Device * SDptr)
1293 {
1294 ips_ha_t *ha;
1295 int min;
1296
1297 ha = IPS_HA(SDptr->host);
1298 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) {
1299 min = ha->max_cmds / 2;
1300 if (ha->enq->ucLogDriveCount <= 2)
1301 min = ha->max_cmds - 1;
1302 scsi_adjust_queue_depth(SDptr, MSG_ORDERED_TAG, min);
1303 }
1304 return 0;
1305 }
1306 #endif
1307
1308 /****************************************************************************/
1309 /* */
1310 /* Routine Name: do_ipsintr */
1311 /* */
1312 /* Routine Description: */
1313 /* */
1314 /* Wrapper for the interrupt handler */
1315 /* */
1316 /****************************************************************************/
1317 static irqreturn_t
1318 do_ipsintr(int irq, void *dev_id, struct pt_regs * regs)
1319 {
1320 ips_ha_t *ha;
1321 unsigned long cpu_flags;
1322 struct Scsi_Host *host;
1323 int irqstatus;
1324
1325 METHOD_TRACE("do_ipsintr", 2);
1326
1327 ha = (ips_ha_t *) dev_id;
1328 if (!ha)
1329 return IRQ_NONE;
1330 host = ips_sh[ha->host_num];
1331 /* interrupt during initialization */
1332 if (!host) {
1333 (*ha->func.intr) (ha);
1334 return IRQ_HANDLED;
1335 }
1336
1337 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
1338
1339 if (!ha->active) {
1340 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
1341 return IRQ_HANDLED;
1342 }
1343
1344 irqstatus = (*ha->func.intr) (ha);
1345
1346 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
1347
1348 /* start the next command */
1349 ips_next(ha, IPS_INTR_ON);
1350 return IRQ_RETVAL(irqstatus);
1351 }
1352
1353 /****************************************************************************/
1354 /* */
1355 /* Routine Name: ips_intr_copperhead */
1356 /* */
1357 /* Routine Description: */
1358 /* */
1359 /* Polling interrupt handler */
1360 /* */
1361 /* ASSUMES interrupts are disabled */
1362 /* */
1363 /****************************************************************************/
1364 int
1365 ips_intr_copperhead(ips_ha_t * ha)
1366 {
1367 ips_stat_t *sp;
1368 ips_scb_t *scb;
1369 IPS_STATUS cstatus;
1370 int intrstatus;
1371
1372 METHOD_TRACE("ips_intr", 2);
1373
1374 if (!ha)
1375 return 0;
1376
1377 if (!ha->active)
1378 return 0;
1379
1380 intrstatus = (*ha->func.isintr) (ha);
1381
1382 if (!intrstatus) {
1383 /*
1384 * Unexpected/Shared interrupt
1385 */
1386
1387 return 0;
1388 }
1389
1390 while (TRUE) {
1391 sp = &ha->sp;
1392
1393 intrstatus = (*ha->func.isintr) (ha);
1394
1395 if (!intrstatus)
1396 break;
1397 else
1398 cstatus.value = (*ha->func.statupd) (ha);
1399
1400 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1401 /* Spurious Interupt ? */
1402 continue;
1403 }
1404
1405 ips_chkstatus(ha, &cstatus);
1406 scb = (ips_scb_t *) sp->scb_addr;
1407
1408 /*
1409 * use the callback function to finish things up
1410 * NOTE: interrupts are OFF for this
1411 */
1412 (*scb->callback) (ha, scb);
1413 } /* end while */
1414 return 1;
1415 }
1416
1417 /****************************************************************************/
1418 /* */
1419 /* Routine Name: ips_intr_morpheus */
1420 /* */
1421 /* Routine Description: */
1422 /* */
1423 /* Polling interrupt handler */
1424 /* */
1425 /* ASSUMES interrupts are disabled */
1426 /* */
1427 /****************************************************************************/
1428 int
1429 ips_intr_morpheus(ips_ha_t * ha)
1430 {
1431 ips_stat_t *sp;
1432 ips_scb_t *scb;
1433 IPS_STATUS cstatus;
1434 int intrstatus;
1435
1436 METHOD_TRACE("ips_intr_morpheus", 2);
1437
1438 if (!ha)
1439 return 0;
1440
1441 if (!ha->active)
1442 return 0;
1443
1444 intrstatus = (*ha->func.isintr) (ha);
1445
1446 if (!intrstatus) {
1447 /*
1448 * Unexpected/Shared interrupt
1449 */
1450
1451 return 0;
1452 }
1453
1454 while (TRUE) {
1455 sp = &ha->sp;
1456
1457 intrstatus = (*ha->func.isintr) (ha);
1458
1459 if (!intrstatus)
1460 break;
1461 else
1462 cstatus.value = (*ha->func.statupd) (ha);
1463
1464 if (cstatus.value == 0xffffffff)
1465 /* No more to process */
1466 break;
1467
1468 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1469 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1470 "Spurious interrupt; no ccb.\n");
1471
1472 continue;
1473 }
1474
1475 ips_chkstatus(ha, &cstatus);
1476 scb = (ips_scb_t *) sp->scb_addr;
1477
1478 /*
1479 * use the callback function to finish things up
1480 * NOTE: interrupts are OFF for this
1481 */
1482 (*scb->callback) (ha, scb);
1483 } /* end while */
1484 return 1;
1485 }
1486
1487 /****************************************************************************/
1488 /* */
1489 /* Routine Name: ips_info */
1490 /* */
1491 /* Routine Description: */
1492 /* */
1493 /* Return info about the driver */
1494 /* */
1495 /****************************************************************************/
1496 static const char *
1497 ips_info(struct Scsi_Host *SH)
1498 {
1499 static char buffer[256];
1500 char *bp;
1501 ips_ha_t *ha;
1502
1503 METHOD_TRACE("ips_info", 1);
1504
1505 ha = IPS_HA(SH);
1506
1507 if (!ha)
1508 return (NULL);
1509
1510 bp = &buffer[0];
1511 memset(bp, 0, sizeof (buffer));
1512
1513 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ",
1514 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT);
1515
1516 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
1517 strcat(bp, " <");
1518 strcat(bp, ips_adapter_name[ha->ad_type - 1]);
1519 strcat(bp, ">");
1520 }
1521
1522 return (bp);
1523 }
1524
1525 /****************************************************************************/
1526 /* */
1527 /* Routine Name: ips_proc_info */
1528 /* */
1529 /* Routine Description: */
1530 /* */
1531 /* The passthru interface for the driver */
1532 /* */
1533 /****************************************************************************/
1534 static int
1535 ips_proc_info(struct Scsi_Host *host, char *buffer, char **start, off_t offset,
1536 int length, int func)
1537 {
1538 int i;
1539 int ret;
1540 ips_ha_t *ha = NULL;
1541
1542 METHOD_TRACE("ips_proc_info", 1);
1543
1544 /* Find our host structure */
1545 for (i = 0; i < ips_next_controller; i++) {
1546 if (ips_sh[i]) {
1547 if (ips_sh[i] == host) {
1548 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1549 break;
1550 }
1551 }
1552 }
1553
1554 if (!ha)
1555 return (-EINVAL);
1556
1557 if (func) {
1558 /* write */
1559 return (0);
1560 } else {
1561 /* read */
1562 if (start)
1563 *start = buffer;
1564
1565 ret = ips_host_info(ha, buffer, offset, length);
1566
1567 return (ret);
1568 }
1569 }
1570
1571 /*--------------------------------------------------------------------------*/
1572 /* Helper Functions */
1573 /*--------------------------------------------------------------------------*/
1574
1575 /****************************************************************************/
1576 /* */
1577 /* Routine Name: ips_is_passthru */
1578 /* */
1579 /* Routine Description: */
1580 /* */
1581 /* Determine if the specified SCSI command is really a passthru command */
1582 /* */
1583 /****************************************************************************/
1584 static int
1585 ips_is_passthru(Scsi_Cmnd * SC)
1586 {
1587 METHOD_TRACE("ips_is_passthru", 1);
1588
1589 if (!SC)
1590 return (0);
1591
1592 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) &&
1593 (SC->device->channel == 0) &&
1594 (SC->device->id == IPS_ADAPTER_ID) &&
1595 (SC->device->lun == 0) && SC->request_buffer) {
1596 if ((!SC->use_sg) && SC->request_bufflen &&
1597 (((char *) SC->request_buffer)[0] == 'C') &&
1598 (((char *) SC->request_buffer)[1] == 'O') &&
1599 (((char *) SC->request_buffer)[2] == 'P') &&
1600 (((char *) SC->request_buffer)[3] == 'P'))
1601 return 1;
1602 else if (SC->use_sg) {
1603 struct scatterlist *sg = SC->request_buffer;
1604 char *buffer = IPS_SG_ADDRESS(sg);
1605 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' &&
1606 buffer[2] == 'P' && buffer[3] == 'P')
1607 return 1;
1608 }
1609 }
1610 return 0;
1611 }
1612
1613 /****************************************************************************/
1614 /* */
1615 /* Routine Name: ips_alloc_passthru_buffer */
1616 /* */
1617 /* Routine Description: */
1618 /* allocate a buffer large enough for the ioctl data if the ioctl buffer */
1619 /* is too small or doesn't exist */
1620 /****************************************************************************/
1621 static int
1622 ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
1623 {
1624 void *bigger_buf;
1625 dma_addr_t dma_busaddr;
1626
1627 if (ha->ioctl_data && length <= ha->ioctl_len)
1628 return 0;
1629 /* there is no buffer or it's not big enough, allocate a new one */
1630 bigger_buf = pci_alloc_consistent(ha->pcidev, length, &dma_busaddr);
1631 if (bigger_buf) {
1632 /* free the old memory */
1633 pci_free_consistent(ha->pcidev, ha->ioctl_len, ha->ioctl_data,
1634 ha->ioctl_busaddr);
1635 /* use the new memory */
1636 ha->ioctl_data = (char *) bigger_buf;
1637 ha->ioctl_len = length;
1638 ha->ioctl_busaddr = dma_busaddr;
1639 } else {
1640 return -1;
1641 }
1642 return 0;
1643 }
1644
1645 /****************************************************************************/
1646 /* */
1647 /* Routine Name: ips_make_passthru */
1648 /* */
1649 /* Routine Description: */
1650 /* */
1651 /* Make a passthru command out of the info in the Scsi block */
1652 /* */
1653 /****************************************************************************/
1654 static int
1655 ips_make_passthru(ips_ha_t * ha, Scsi_Cmnd * SC, ips_scb_t * scb, int intr)
1656 {
1657 ips_passthru_t *pt;
1658 int length = 0;
1659 int ret;
1660
1661 METHOD_TRACE("ips_make_passthru", 1);
1662
1663 if (!SC->use_sg) {
1664 length = SC->request_bufflen;
1665 } else {
1666 struct scatterlist *sg = SC->request_buffer;
1667 int i;
1668 for (i = 0; i < SC->use_sg; i++)
1669 length += sg[i].length;
1670 }
1671 if (length < sizeof (ips_passthru_t)) {
1672 /* wrong size */
1673 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size",
1674 ips_name, ha->host_num);
1675 return (IPS_FAILURE);
1676 }
1677 if (ips_alloc_passthru_buffer(ha, length)) {
1678 /* allocation failure! If ha->ioctl_data exists, use it to return
1679 some error codes. Return a failed command to the scsi layer. */
1680 if (ha->ioctl_data) {
1681 pt = (ips_passthru_t *) ha->ioctl_data;
1682 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t));
1683 pt->BasicStatus = 0x0B;
1684 pt->ExtendedStatus = 0x00;
1685 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t));
1686 }
1687 return IPS_FAILURE;
1688 }
1689 ha->ioctl_datasize = length;
1690
1691 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
1692 pt = (ips_passthru_t *) ha->ioctl_data;
1693
1694 /*
1695 * Some notes about the passthru interface used
1696 *
1697 * IF the scsi op_code == 0x0d then we assume
1698 * that the data came along with/goes with the
1699 * packet we received from the sg driver. In this
1700 * case the CmdBSize field of the pt structure is
1701 * used for the size of the buffer.
1702 */
1703
1704 switch (pt->CoppCmd) {
1705 case IPS_NUMCTRLS:
1706 memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
1707 &ips_num_controllers, sizeof (int));
1708 ips_scmd_buf_write(SC, ha->ioctl_data,
1709 sizeof (ips_passthru_t) + sizeof (int));
1710 SC->result = DID_OK << 16;
1711
1712 return (IPS_SUCCESS_IMM);
1713
1714 case IPS_COPPUSRCMD:
1715 case IPS_COPPIOCCMD:
1716 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) {
1717 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) {
1718 /* wrong size */
1719 DEBUG_VAR(1,
1720 "(%s%d) Passthru structure wrong size",
1721 ips_name, ha->host_num);
1722
1723 return (IPS_FAILURE);
1724 }
1725
1726 if (ha->device_id == IPS_DEVICEID_COPPERHEAD &&
1727 pt->CoppCP.cmd.flashfw.op_code ==
1728 IPS_CMD_RW_BIOSFW) {
1729 ret = ips_flash_copperhead(ha, pt, scb);
1730 ips_scmd_buf_write(SC, ha->ioctl_data,
1731 sizeof (ips_passthru_t));
1732 return ret;
1733 }
1734 if (ips_usrcmd(ha, pt, scb))
1735 return (IPS_SUCCESS);
1736 else
1737 return (IPS_FAILURE);
1738 }
1739
1740 break;
1741
1742 } /* end switch */
1743
1744 return (IPS_FAILURE);
1745 }
1746
1747 /****************************************************************************/
1748 /* Routine Name: ips_flash_copperhead */
1749 /* Routine Description: */
1750 /* Flash the BIOS/FW on a Copperhead style controller */
1751 /****************************************************************************/
1752 static int
1753 ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1754 {
1755 int datasize;
1756
1757 /* Trombone is the only copperhead that can do packet flash, but only
1758 * for firmware. No one said it had to make sence. */
1759 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
1760 if (ips_usrcmd(ha, pt, scb))
1761 return IPS_SUCCESS;
1762 else
1763 return IPS_FAILURE;
1764 }
1765 pt->BasicStatus = 0x0B;
1766 pt->ExtendedStatus = 0;
1767 scb->scsi_cmd->result = DID_OK << 16;
1768 /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */
1769 /* avoid allocating a huge buffer per adapter ( which can fail ). */
1770 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1771 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1772 pt->BasicStatus = 0;
1773 return ips_flash_bios(ha, pt, scb);
1774 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) {
1775 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){
1776 ha->flash_data = ips_FlashData;
1777 ha->flash_busaddr = ips_flashbusaddr;
1778 ha->flash_len = PAGE_SIZE << 7;
1779 ha->flash_datasize = 0;
1780 } else if (!ha->flash_data) {
1781 datasize = pt->CoppCP.cmd.flashfw.total_packets *
1782 pt->CoppCP.cmd.flashfw.count;
1783 ha->flash_data = pci_alloc_consistent(ha->pcidev,
1784 datasize,
1785 &ha->flash_busaddr);
1786 if (!ha->flash_data){
1787 printk(KERN_WARNING "Unable to allocate a flash buffer\n");
1788 return IPS_FAILURE;
1789 }
1790 ha->flash_datasize = 0;
1791 ha->flash_len = datasize;
1792 } else
1793 return IPS_FAILURE;
1794 } else {
1795 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
1796 ha->flash_len) {
1797 ips_free_flash_copperhead(ha);
1798 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1799 "failed size sanity check\n");
1800 return IPS_FAILURE;
1801 }
1802 }
1803 if (!ha->flash_data)
1804 return IPS_FAILURE;
1805 pt->BasicStatus = 0;
1806 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
1807 pt->CoppCP.cmd.flashfw.count);
1808 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
1809 if (pt->CoppCP.cmd.flashfw.packet_num ==
1810 pt->CoppCP.cmd.flashfw.total_packets - 1) {
1811 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE)
1812 return ips_flash_bios(ha, pt, scb);
1813 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE)
1814 return ips_flash_firmware(ha, pt, scb);
1815 }
1816 return IPS_SUCCESS_IMM;
1817 }
1818
1819 /****************************************************************************/
1820 /* Routine Name: ips_flash_bios */
1821 /* Routine Description: */
1822 /* flashes the bios of a copperhead adapter */
1823 /****************************************************************************/
1824 static int
1825 ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1826 {
1827
1828 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1829 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) {
1830 if ((!ha->func.programbios) || (!ha->func.erasebios) ||
1831 (!ha->func.verifybios))
1832 goto error;
1833 if ((*ha->func.erasebios) (ha)) {
1834 DEBUG_VAR(1,
1835 "(%s%d) flash bios failed - unable to erase flash",
1836 ips_name, ha->host_num);
1837 goto error;
1838 } else
1839 if ((*ha->func.programbios) (ha,
1840 ha->flash_data +
1841 IPS_BIOS_HEADER,
1842 ha->flash_datasize -
1843 IPS_BIOS_HEADER, 0)) {
1844 DEBUG_VAR(1,
1845 "(%s%d) flash bios failed - unable to flash",
1846 ips_name, ha->host_num);
1847 goto error;
1848 } else
1849 if ((*ha->func.verifybios) (ha,
1850 ha->flash_data +
1851 IPS_BIOS_HEADER,
1852 ha->flash_datasize -
1853 IPS_BIOS_HEADER, 0)) {
1854 DEBUG_VAR(1,
1855 "(%s%d) flash bios failed - unable to verify flash",
1856 ips_name, ha->host_num);
1857 goto error;
1858 }
1859 ips_free_flash_copperhead(ha);
1860 return IPS_SUCCESS_IMM;
1861 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1862 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1863 if (!ha->func.erasebios)
1864 goto error;
1865 if ((*ha->func.erasebios) (ha)) {
1866 DEBUG_VAR(1,
1867 "(%s%d) flash bios failed - unable to erase flash",
1868 ips_name, ha->host_num);
1869 goto error;
1870 }
1871 return IPS_SUCCESS_IMM;
1872 }
1873 error:
1874 pt->BasicStatus = 0x0B;
1875 pt->ExtendedStatus = 0x00;
1876 ips_free_flash_copperhead(ha);
1877 return IPS_FAILURE;
1878 }
1879
1880 /****************************************************************************/
1881 /* */
1882 /* Routine Name: ips_fill_scb_sg_single */
1883 /* */
1884 /* Routine Description: */
1885 /* Fill in a single scb sg_list element from an address */
1886 /* return a -1 if a breakup occurred */
1887 /****************************************************************************/
1888 static int
1889 ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
1890 ips_scb_t * scb, int indx, unsigned int e_len)
1891 {
1892
1893 int ret_val = 0;
1894
1895 if ((scb->data_len + e_len) > ha->max_xfer) {
1896 e_len = ha->max_xfer - scb->data_len;
1897 scb->breakup = indx;
1898 ++scb->sg_break;
1899 ret_val = -1;
1900 } else {
1901 scb->breakup = 0;
1902 scb->sg_break = 0;
1903 }
1904 if (IPS_USE_ENH_SGLIST(ha)) {
1905 scb->sg_list.enh_list[indx].address_lo =
1906 cpu_to_le32(pci_dma_lo32(busaddr));
1907 scb->sg_list.enh_list[indx].address_hi =
1908 cpu_to_le32(pci_dma_hi32(busaddr));
1909 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len);
1910 } else {
1911 scb->sg_list.std_list[indx].address =
1912 cpu_to_le32(pci_dma_lo32(busaddr));
1913 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len);
1914 }
1915
1916 ++scb->sg_len;
1917 scb->data_len += e_len;
1918 return ret_val;
1919 }
1920
1921 /****************************************************************************/
1922 /* Routine Name: ips_flash_firmware */
1923 /* Routine Description: */
1924 /* flashes the firmware of a copperhead adapter */
1925 /****************************************************************************/
1926 static int
1927 ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1928 {
1929 IPS_SG_LIST sg_list;
1930 uint32_t cmd_busaddr;
1931
1932 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE &&
1933 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) {
1934 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND));
1935 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD;
1936 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
1937 } else {
1938 pt->BasicStatus = 0x0B;
1939 pt->ExtendedStatus = 0x00;
1940 ips_free_flash_copperhead(ha);
1941 return IPS_FAILURE;
1942 }
1943 /* Save the S/G list pointer so it doesn't get clobbered */
1944 sg_list.list = scb->sg_list.list;
1945 cmd_busaddr = scb->scb_busaddr;
1946 /* copy in the CP */
1947 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1948 /* FIX stuff that might be wrong */
1949 scb->sg_list.list = sg_list.list;
1950 scb->scb_busaddr = cmd_busaddr;
1951 scb->bus = scb->scsi_cmd->device->channel;
1952 scb->target_id = scb->scsi_cmd->device->id;
1953 scb->lun = scb->scsi_cmd->device->lun;
1954 scb->sg_len = 0;
1955 scb->data_len = 0;
1956 scb->flags = 0;
1957 scb->op_code = 0;
1958 scb->callback = ipsintr_done;
1959 scb->timeout = ips_cmd_timeout;
1960
1961 scb->data_len = ha->flash_datasize;
1962 scb->data_busaddr =
1963 pci_map_single(ha->pcidev, ha->flash_data, scb->data_len,
1964 IPS_DMA_DIR(scb));
1965 scb->flags |= IPS_SCB_MAP_SINGLE;
1966 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
1967 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr);
1968 if (pt->TimeOut)
1969 scb->timeout = pt->TimeOut;
1970 scb->scsi_cmd->result = DID_OK << 16;
1971 return IPS_SUCCESS;
1972 }
1973
1974 /****************************************************************************/
1975 /* Routine Name: ips_free_flash_copperhead */
1976 /* Routine Description: */
1977 /* release the memory resources used to hold the flash image */
1978 /****************************************************************************/
1979 static void
1980 ips_free_flash_copperhead(ips_ha_t * ha)
1981 {
1982 if (ha->flash_data == ips_FlashData)
1983 test_and_clear_bit(0, &ips_FlashDataInUse);
1984 else if (ha->flash_data)
1985 pci_free_consistent(ha->pcidev, ha->flash_len, ha->flash_data,
1986 ha->flash_busaddr);
1987 ha->flash_data = NULL;
1988 }
1989
1990 /****************************************************************************/
1991 /* */
1992 /* Routine Name: ips_usrcmd */
1993 /* */
1994 /* Routine Description: */
1995 /* */
1996 /* Process a user command and make it ready to send */
1997 /* */
1998 /****************************************************************************/
1999 static int
2000 ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
2001 {
2002 IPS_SG_LIST sg_list;
2003 uint32_t cmd_busaddr;
2004
2005 METHOD_TRACE("ips_usrcmd", 1);
2006
2007 if ((!scb) || (!pt) || (!ha))
2008 return (0);
2009
2010 /* Save the S/G list pointer so it doesn't get clobbered */
2011 sg_list.list = scb->sg_list.list;
2012 cmd_busaddr = scb->scb_busaddr;
2013 /* copy in the CP */
2014 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
2015 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE));
2016
2017 /* FIX stuff that might be wrong */
2018 scb->sg_list.list = sg_list.list;
2019 scb->scb_busaddr = cmd_busaddr;
2020 scb->bus = scb->scsi_cmd->device->channel;
2021 scb->target_id = scb->scsi_cmd->device->id;
2022 scb->lun = scb->scsi_cmd->device->lun;
2023 scb->sg_len = 0;
2024 scb->data_len = 0;
2025 scb->flags = 0;
2026 scb->op_code = 0;
2027 scb->callback = ipsintr_done;
2028 scb->timeout = ips_cmd_timeout;
2029 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
2030
2031 /* we don't support DCDB/READ/WRITE Scatter Gather */
2032 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) ||
2033 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) ||
2034 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG))
2035 return (0);
2036
2037 if (pt->CmdBSize) {
2038 scb->data_len = pt->CmdBSize;
2039 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
2040 } else {
2041 scb->data_busaddr = 0L;
2042 }
2043
2044 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
2045 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
2046 (unsigned long) &scb->
2047 dcdb -
2048 (unsigned long) scb);
2049
2050 if (pt->CmdBSize) {
2051 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
2052 scb->dcdb.buffer_pointer =
2053 cpu_to_le32(scb->data_busaddr);
2054 else
2055 scb->cmd.basic_io.sg_addr =
2056 cpu_to_le32(scb->data_busaddr);
2057 }
2058
2059 /* set timeouts */
2060 if (pt->TimeOut) {
2061 scb->timeout = pt->TimeOut;
2062
2063 if (pt->TimeOut <= 10)
2064 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
2065 else if (pt->TimeOut <= 60)
2066 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
2067 else
2068 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
2069 }
2070
2071 /* assume success */
2072 scb->scsi_cmd->result = DID_OK << 16;
2073
2074 /* success */
2075 return (1);
2076 }
2077
2078 /****************************************************************************/
2079 /* */
2080 /* Routine Name: ips_cleanup_passthru */
2081 /* */
2082 /* Routine Description: */
2083 /* */
2084 /* Cleanup after a passthru command */
2085 /* */
2086 /****************************************************************************/
2087 static void
2088 ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
2089 {
2090 ips_passthru_t *pt;
2091
2092 METHOD_TRACE("ips_cleanup_passthru", 1);
2093
2094 if ((!scb) || (!scb->scsi_cmd) || (!scb->scsi_cmd->request_buffer)) {
2095 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru",
2096 ips_name, ha->host_num);
2097
2098 return;
2099 }
2100 pt = (ips_passthru_t *) ha->ioctl_data;
2101
2102 /* Copy data back to the user */
2103 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */
2104 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE));
2105
2106 pt->BasicStatus = scb->basic_status;
2107 pt->ExtendedStatus = scb->extended_status;
2108 pt->AdapterType = ha->ad_type;
2109
2110 if (ha->device_id == IPS_DEVICEID_COPPERHEAD &&
2111 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD ||
2112 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW))
2113 ips_free_flash_copperhead(ha);
2114
2115 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
2116 }
2117
2118 /****************************************************************************/
2119 /* */
2120 /* Routine Name: ips_host_info */
2121 /* */
2122 /* Routine Description: */
2123 /* */
2124 /* The passthru interface for the driver */
2125 /* */
2126 /****************************************************************************/
2127 static int
2128 ips_host_info(ips_ha_t * ha, char *ptr, off_t offset, int len)
2129 {
2130 IPS_INFOSTR info;
2131
2132 METHOD_TRACE("ips_host_info", 1);
2133
2134 info.buffer = ptr;
2135 info.length = len;
2136 info.offset = offset;
2137 info.pos = 0;
2138 info.localpos = 0;
2139
2140 copy_info(&info, "\nIBM ServeRAID General Information:\n\n");
2141
2142 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
2143 (le16_to_cpu(ha->nvram->adapter_type) != 0))
2144 copy_info(&info, "\tController Type : %s\n",
2145 ips_adapter_name[ha->ad_type - 1]);
2146 else
2147 copy_info(&info,
2148 "\tController Type : Unknown\n");
2149
2150 if (ha->io_addr)
2151 copy_info(&info,
2152 "\tIO region : 0x%lx (%d bytes)\n",
2153 ha->io_addr, ha->io_len);
2154
2155 if (ha->mem_addr) {
2156 copy_info(&info,
2157 "\tMemory region : 0x%lx (%d bytes)\n",
2158 ha->mem_addr, ha->mem_len);
2159 copy_info(&info,
2160 "\tShared memory address : 0x%lx\n",
2161 ha->mem_ptr);
2162 }
2163
2164 copy_info(&info, "\tIRQ number : %d\n", ha->irq);
2165
2166 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */
2167 /* That keeps everything happy for "text" operations on the proc file. */
2168
2169 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
2170 if (ha->nvram->bios_low[3] == 0) {
2171 copy_info(&info,
2172 "\tBIOS Version : %c%c%c%c%c%c%c\n",
2173 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2174 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2175 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2176 ha->nvram->bios_low[2]);
2177
2178 } else {
2179 copy_info(&info,
2180 "\tBIOS Version : %c%c%c%c%c%c%c%c\n",
2181 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2182 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2183 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2184 ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
2185 }
2186
2187 }
2188
2189 if (ha->enq->CodeBlkVersion[7] == 0) {
2190 copy_info(&info,
2191 "\tFirmware Version : %c%c%c%c%c%c%c\n",
2192 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2193 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2194 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2195 ha->enq->CodeBlkVersion[6]);
2196 } else {
2197 copy_info(&info,
2198 "\tFirmware Version : %c%c%c%c%c%c%c%c\n",
2199 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2200 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2201 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2202 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
2203 }
2204
2205 if (ha->enq->BootBlkVersion[7] == 0) {
2206 copy_info(&info,
2207 "\tBoot Block Version : %c%c%c%c%c%c%c\n",
2208 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2209 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2210 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2211 ha->enq->BootBlkVersion[6]);
2212 } else {
2213 copy_info(&info,
2214 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n",
2215 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2216 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2217 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2218 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
2219 }
2220
2221 copy_info(&info, "\tDriver Version : %s%s\n",
2222 IPS_VERSION_HIGH, IPS_VERSION_LOW);
2223
2224 copy_info(&info, "\tDriver Build : %d\n",
2225 IPS_BUILD_IDENT);
2226
2227 copy_info(&info, "\tMax Physical Devices : %d\n",
2228 ha->enq->ucMaxPhysicalDevices);
2229 copy_info(&info, "\tMax Active Commands : %d\n",
2230 ha->max_cmds);
2231 copy_info(&info, "\tCurrent Queued Commands : %d\n",
2232 ha->scb_waitlist.count);
2233 copy_info(&info, "\tCurrent Active Commands : %d\n",
2234 ha->scb_activelist.count - ha->num_ioctl);
2235 copy_info(&info, "\tCurrent Queued PT Commands : %d\n",
2236 ha->copp_waitlist.count);
2237 copy_info(&info, "\tCurrent Active PT Commands : %d\n",
2238 ha->num_ioctl);
2239
2240 copy_info(&info, "\n");
2241
2242 return (info.localpos);
2243 }
2244
2245 /****************************************************************************/
2246 /* */
2247 /* Routine Name: copy_mem_info */
2248 /* */
2249 /* Routine Description: */
2250 /* */
2251 /* Copy data into an IPS_INFOSTR structure */
2252 /* */
2253 /****************************************************************************/
2254 static void
2255 copy_mem_info(IPS_INFOSTR * info, char *data, int len)
2256 {
2257 METHOD_TRACE("copy_mem_info", 1);
2258
2259 if (info->pos + len < info->offset) {
2260 info->pos += len;
2261 return;
2262 }
2263
2264 if (info->pos < info->offset) {
2265 data += (info->offset - info->pos);
2266 len -= (info->offset - info->pos);
2267 info->pos += (info->offset - info->pos);
2268 }
2269
2270 if (info->localpos + len > info->length)
2271 len = info->length - info->localpos;
2272
2273 if (len > 0) {
2274 memcpy(info->buffer + info->localpos, data, len);
2275 info->pos += len;
2276 info->localpos += len;
2277 }
2278 }
2279
2280 /****************************************************************************/
2281 /* */
2282 /* Routine Name: copy_info */
2283 /* */
2284 /* Routine Description: */
2285 /* */
2286 /* printf style wrapper for an info structure */
2287 /* */
2288 /****************************************************************************/
2289 static int
2290 copy_info(IPS_INFOSTR * info, char *fmt, ...)
2291 {
2292 va_list args;
2293 char buf[128];
2294 int len;
2295
2296 METHOD_TRACE("copy_info", 1);
2297
2298 va_start(args, fmt);
2299 len = vsprintf(buf, fmt, args);
2300 va_end(args);
2301
2302 copy_mem_info(info, buf, len);
2303
2304 return (len);
2305 }
2306
2307 /****************************************************************************/
2308 /* */
2309 /* Routine Name: ips_identify_controller */
2310 /* */
2311 /* Routine Description: */
2312 /* */
2313 /* Identify this controller */
2314 /* */
2315 /****************************************************************************/
2316 static void
2317 ips_identify_controller(ips_ha_t * ha)
2318 {
2319 METHOD_TRACE("ips_identify_controller", 1);
2320
2321 switch (ha->device_id) {
2322 case IPS_DEVICEID_COPPERHEAD:
2323 if (ha->revision_id <= IPS_REVID_SERVERAID) {
2324 ha->ad_type = IPS_ADTYPE_SERVERAID;
2325 } else if (ha->revision_id == IPS_REVID_SERVERAID2) {
2326 ha->ad_type = IPS_ADTYPE_SERVERAID2;
2327 } else if (ha->revision_id == IPS_REVID_NAVAJO) {
2328 ha->ad_type = IPS_ADTYPE_NAVAJO;
2329 } else if ((ha->revision_id == IPS_REVID_SERVERAID2)
2330 && (ha->slot_num == 0)) {
2331 ha->ad_type = IPS_ADTYPE_KIOWA;
2332 } else if ((ha->revision_id >= IPS_REVID_CLARINETP1) &&
2333 (ha->revision_id <= IPS_REVID_CLARINETP3)) {
2334 if (ha->enq->ucMaxPhysicalDevices == 15)
2335 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2336 else
2337 ha->ad_type = IPS_ADTYPE_SERVERAID3;
2338 } else if ((ha->revision_id >= IPS_REVID_TROMBONE32) &&
2339 (ha->revision_id <= IPS_REVID_TROMBONE64)) {
2340 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2341 }
2342 break;
2343
2344 case IPS_DEVICEID_MORPHEUS:
2345 switch (ha->subdevice_id) {
2346 case IPS_SUBDEVICEID_4L:
2347 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2348 break;
2349
2350 case IPS_SUBDEVICEID_4M:
2351 ha->ad_type = IPS_ADTYPE_SERVERAID4M;
2352 break;
2353
2354 case IPS_SUBDEVICEID_4MX:
2355 ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
2356 break;
2357
2358 case IPS_SUBDEVICEID_4LX:
2359 ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
2360 break;
2361
2362 case IPS_SUBDEVICEID_5I2:
2363 ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
2364 break;
2365
2366 case IPS_SUBDEVICEID_5I1:
2367 ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
2368 break;
2369 }
2370
2371 break;
2372
2373 case IPS_DEVICEID_MARCO:
2374 switch (ha->subdevice_id) {
2375 case IPS_SUBDEVICEID_6M:
2376 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2377 break;
2378 case IPS_SUBDEVICEID_6I:
2379 ha->ad_type = IPS_ADTYPE_SERVERAID6I;
2380 break;
2381 case IPS_SUBDEVICEID_7k:
2382 ha->ad_type = IPS_ADTYPE_SERVERAID7k;
2383 break;
2384 case IPS_SUBDEVICEID_7M:
2385 ha->ad_type = IPS_ADTYPE_SERVERAID7M;
2386 break;
2387 }
2388 break;
2389 }
2390 }
2391
2392 /****************************************************************************/
2393 /* */
2394 /* Routine Name: ips_get_bios_version */
2395 /* */
2396 /* Routine Description: */
2397 /* */
2398 /* Get the BIOS revision number */
2399 /* */
2400 /****************************************************************************/
2401 static void
2402 ips_get_bios_version(ips_ha_t * ha, int intr)
2403 {
2404 ips_scb_t *scb;
2405 int ret;
2406 uint8_t major;
2407 uint8_t minor;
2408 uint8_t subminor;
2409 uint8_t *buffer;
2410 char hexDigits[] =
2411 { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C',
2412 'D', 'E', 'F' };
2413
2414 METHOD_TRACE("ips_get_bios_version", 1);
2415
2416 major = 0;
2417 minor = 0;
2418
2419 strncpy(ha->bios_version, " ?", 8);
2420
2421 if (ha->device_id == IPS_DEVICEID_COPPERHEAD) {
2422 if (IPS_USE_MEMIO(ha)) {
2423 /* Memory Mapped I/O */
2424
2425 /* test 1st byte */
2426 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2427 if (ha->revision_id == IPS_REVID_TROMBONE64)
2428 udelay(25); /* 25 us */
2429
2430 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2431 return;
2432
2433 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2434 if (ha->revision_id == IPS_REVID_TROMBONE64)
2435 udelay(25); /* 25 us */
2436
2437 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2438 return;
2439
2440 /* Get Major version */
2441 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2442 if (ha->revision_id == IPS_REVID_TROMBONE64)
2443 udelay(25); /* 25 us */
2444
2445 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2446
2447 /* Get Minor version */
2448 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2449 if (ha->revision_id == IPS_REVID_TROMBONE64)
2450 udelay(25); /* 25 us */
2451 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2452
2453 /* Get SubMinor version */
2454 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2455 if (ha->revision_id == IPS_REVID_TROMBONE64)
2456 udelay(25); /* 25 us */
2457 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2458
2459 } else {
2460 /* Programmed I/O */
2461
2462 /* test 1st byte */
2463 outl(0, ha->io_addr + IPS_REG_FLAP);
2464 if (ha->revision_id == IPS_REVID_TROMBONE64)
2465 udelay(25); /* 25 us */
2466
2467 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2468 return;
2469
2470 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP);
2471 if (ha->revision_id == IPS_REVID_TROMBONE64)
2472 udelay(25); /* 25 us */
2473
2474 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2475 return;
2476
2477 /* Get Major version */
2478 outl(cpu_to_le32(0x1FF), ha->io_addr + IPS_REG_FLAP);
2479 if (ha->revision_id == IPS_REVID_TROMBONE64)
2480 udelay(25); /* 25 us */
2481
2482 major = inb(ha->io_addr + IPS_REG_FLDP);
2483
2484 /* Get Minor version */
2485 outl(cpu_to_le32(0x1FE), ha->io_addr + IPS_REG_FLAP);
2486 if (ha->revision_id == IPS_REVID_TROMBONE64)
2487 udelay(25); /* 25 us */
2488
2489 minor = inb(ha->io_addr + IPS_REG_FLDP);
2490
2491 /* Get SubMinor version */
2492 outl(cpu_to_le32(0x1FD), ha->io_addr + IPS_REG_FLAP);
2493 if (ha->revision_id == IPS_REVID_TROMBONE64)
2494 udelay(25); /* 25 us */
2495
2496 subminor = inb(ha->io_addr + IPS_REG_FLDP);
2497
2498 }
2499 } else {
2500 /* Morpheus Family - Send Command to the card */
2501
2502 buffer = ha->ioctl_data;
2503
2504 memset(buffer, 0, 0x1000);
2505
2506 scb = &ha->scbs[ha->max_cmds - 1];
2507
2508 ips_init_scb(ha, scb);
2509
2510 scb->timeout = ips_cmd_timeout;
2511 scb->cdb[0] = IPS_CMD_RW_BIOSFW;
2512
2513 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW;
2514 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2515 scb->cmd.flashfw.type = 1;
2516 scb->cmd.flashfw.direction = 0;
2517 scb->cmd.flashfw.count = cpu_to_le32(0x800);
2518 scb->cmd.flashfw.total_packets = 1;
2519 scb->cmd.flashfw.packet_num = 0;
2520 scb->data_len = 0x1000;
2521 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
2522
2523 /* issue the command */
2524 if (((ret =
2525 ips_send_wait(ha, scb, ips_cmd_timeout,
2526 intr)) == IPS_FAILURE)
2527 || (ret == IPS_SUCCESS_IMM)
2528 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
2529 /* Error occurred */
2530
2531 return;
2532 }
2533
2534 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) {
2535 major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */
2536 minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */
2537 subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */
2538 } else {
2539 return;
2540 }
2541 }
2542
2543 ha->bios_version[0] = hexDigits[(major & 0xF0) >> 4];
2544 ha->bios_version[1] = '.';
2545 ha->bios_version[2] = hexDigits[major & 0x0F];
2546 ha->bios_version[3] = hexDigits[subminor];
2547 ha->bios_version[4] = '.';
2548 ha->bios_version[5] = hexDigits[(minor & 0xF0) >> 4];
2549 ha->bios_version[6] = hexDigits[minor & 0x0F];
2550 ha->bios_version[7] = 0;
2551 }
2552
2553 /****************************************************************************/
2554 /* */
2555 /* Routine Name: ips_hainit */
2556 /* */
2557 /* Routine Description: */
2558 /* */
2559 /* Initialize the controller */
2560 /* */
2561 /* NOTE: Assumes to be called from with a lock */
2562 /* */
2563 /****************************************************************************/
2564 static int
2565 ips_hainit(ips_ha_t * ha)
2566 {
2567 int i;
2568 struct timeval tv;
2569
2570 METHOD_TRACE("ips_hainit", 1);
2571
2572 if (!ha)
2573 return (0);
2574
2575 if (ha->func.statinit)
2576 (*ha->func.statinit) (ha);
2577
2578 if (ha->func.enableint)
2579 (*ha->func.enableint) (ha);
2580
2581 /* Send FFDC */
2582 ha->reset_count = 1;
2583 do_gettimeofday(&tv);
2584 ha->last_ffdc = tv.tv_sec;
2585 ips_ffdc_reset(ha, IPS_INTR_IORL);
2586
2587 if (!ips_read_config(ha, IPS_INTR_IORL)) {
2588 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2589 "unable to read config from controller.\n");
2590
2591 return (0);
2592 }
2593 /* end if */
2594 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
2595 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2596 "unable to read controller status.\n");
2597
2598 return (0);
2599 }
2600
2601 /* Identify this controller */
2602 ips_identify_controller(ha);
2603
2604 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
2605 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2606 "unable to read subsystem parameters.\n");
2607
2608 return (0);
2609 }
2610
2611 /* write nvram user page 5 */
2612 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
2613 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2614 "unable to write driver info to controller.\n");
2615
2616 return (0);
2617 }
2618
2619 /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */
2620 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
2621 ips_clear_adapter(ha, IPS_INTR_IORL);
2622
2623 /* set limits on SID, LUN, BUS */
2624 ha->ntargets = IPS_MAX_TARGETS + 1;
2625 ha->nlun = 1;
2626 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
2627
2628 switch (ha->conf->logical_drive[0].ucStripeSize) {
2629 case 4:
2630 ha->max_xfer = 0x10000;
2631 break;
2632
2633 case 5:
2634 ha->max_xfer = 0x20000;
2635 break;
2636
2637 case 6:
2638 ha->max_xfer = 0x40000;
2639 break;
2640
2641 case 7:
2642 default:
2643 ha->max_xfer = 0x80000;
2644 break;
2645 }
2646
2647 /* setup max concurrent commands */
2648 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
2649 /* Use the new method */
2650 ha->max_cmds = ha->enq->ucConcurrentCmdCount;
2651 } else {
2652 /* use the old method */
2653 switch (ha->conf->logical_drive[0].ucStripeSize) {
2654 case 4:
2655 ha->max_cmds = 32;
2656 break;
2657
2658 case 5:
2659 ha->max_cmds = 16;
2660 break;
2661
2662 case 6:
2663 ha->max_cmds = 8;
2664 break;
2665
2666 case 7:
2667 default:
2668 ha->max_cmds = 4;
2669 break;
2670 }
2671 }
2672
2673 /* Limit the Active Commands on a Lite Adapter */
2674 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
2675 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
2676 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
2677 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
2678 ha->max_cmds = MaxLiteCmds;
2679 }
2680
2681 /* set controller IDs */
2682 ha->ha_id[0] = IPS_ADAPTER_ID;
2683 for (i = 1; i < ha->nbus; i++) {
2684 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
2685 ha->dcdb_active[i - 1] = 0;
2686 }
2687
2688 return (1);
2689 }
2690
2691 /****************************************************************************/
2692 /* */
2693 /* Routine Name: ips_next */
2694 /* */
2695 /* Routine Description: */
2696 /* */
2697 /* Take the next command off the queue and send it to the controller */
2698 /* */
2699 /****************************************************************************/
2700 static void
2701 ips_next(ips_ha_t * ha, int intr)
2702 {
2703 ips_scb_t *scb;
2704 Scsi_Cmnd *SC;
2705 Scsi_Cmnd *p;
2706 Scsi_Cmnd *q;
2707 ips_copp_wait_item_t *item;
2708 int ret;
2709 unsigned long cpu_flags = 0;
2710 struct Scsi_Host *host;
2711 METHOD_TRACE("ips_next", 1);
2712
2713 if (!ha)
2714 return;
2715 host = ips_sh[ha->host_num];
2716 /*
2717 * Block access to the queue function so
2718 * this command won't time out
2719 */
2720 if (intr == IPS_INTR_ON)
2721 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
2722
2723 if ((ha->subsys->param[3] & 0x300000)
2724 && (ha->scb_activelist.count == 0)) {
2725 struct timeval tv;
2726
2727 do_gettimeofday(&tv);
2728
2729 if (tv.tv_sec - ha->last_ffdc > IPS_SECS_8HOURS) {
2730 ha->last_ffdc = tv.tv_sec;
2731 ips_ffdc_time(ha);
2732 }
2733 }
2734
2735 /*
2736 * Send passthru commands
2737 * These have priority over normal I/O
2738 * but shouldn't affect performance too much
2739 * since we limit the number that can be active
2740 * on the card at any one time
2741 */
2742 while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
2743 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
2744
2745 item = ips_removeq_copp_head(&ha->copp_waitlist);
2746 ha->num_ioctl++;
2747 if (intr == IPS_INTR_ON)
2748 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
2749 scb->scsi_cmd = item->scsi_cmd;
2750 kfree(item);
2751
2752 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
2753
2754 if (intr == IPS_INTR_ON)
2755 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
2756 switch (ret) {
2757 case IPS_FAILURE:
2758 if (scb->scsi_cmd) {
2759 scb->scsi_cmd->result = DID_ERROR << 16;
2760 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2761 }
2762
2763 ips_freescb(ha, scb);
2764 break;
2765 case IPS_SUCCESS_IMM:
2766 if (scb->scsi_cmd) {
2767 scb->scsi_cmd->result = DID_OK << 16;
2768 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2769 }
2770
2771 ips_freescb(ha, scb);
2772 break;
2773 default:
2774 break;
2775 } /* end case */
2776
2777 if (ret != IPS_SUCCESS) {
2778 ha->num_ioctl--;
2779 continue;
2780 }
2781
2782 ret = ips_send_cmd(ha, scb);
2783
2784 if (ret == IPS_SUCCESS)
2785 ips_putq_scb_head(&ha->scb_activelist, scb);
2786 else
2787 ha->num_ioctl--;
2788
2789 switch (ret) {
2790 case IPS_FAILURE:
2791 if (scb->scsi_cmd) {
2792 scb->scsi_cmd->result = DID_ERROR << 16;
2793 }
2794
2795 ips_freescb(ha, scb);
2796 break;
2797 case IPS_SUCCESS_IMM:
2798 ips_freescb(ha, scb);
2799 break;
2800 default:
2801 break;
2802 } /* end case */
2803
2804 }
2805
2806 /*
2807 * Send "Normal" I/O commands
2808 */
2809
2810 p = ha->scb_waitlist.head;
2811 while ((p) && (scb = ips_getscb(ha))) {
2812 if ((p->device->channel > 0)
2813 && (ha->
2814 dcdb_active[p->device->channel -
2815 1] & (1 << p->device->id))) {
2816 ips_freescb(ha, scb);
2817 p = (Scsi_Cmnd *) p->host_scribble;
2818 continue;
2819 }
2820
2821 q = p;
2822 SC = ips_removeq_wait(&ha->scb_waitlist, q);
2823
2824 if (intr == IPS_INTR_ON)
2825 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags); /* Unlock HA after command is taken off queue */
2826
2827 SC->result = DID_OK;
2828 SC->host_scribble = NULL;
2829
2830 memset(SC->sense_buffer, 0, sizeof (SC->sense_buffer));
2831
2832 scb->target_id = SC->device->id;
2833 scb->lun = SC->device->lun;
2834 scb->bus = SC->device->channel;
2835 scb->scsi_cmd = SC;
2836 scb->breakup = 0;
2837 scb->data_len = 0;
2838 scb->callback = ipsintr_done;
2839 scb->timeout = ips_cmd_timeout;
2840 memset(&scb->cmd, 0, 16);
2841
2842 /* copy in the CDB */
2843 memcpy(scb->cdb, SC->cmnd, SC->cmd_len);
2844
2845 /* Now handle the data buffer */
2846 if (SC->use_sg) {
2847 struct scatterlist *sg;
2848 int i;
2849
2850 sg = SC->request_buffer;
2851 scb->sg_count = pci_map_sg(ha->pcidev, sg, SC->use_sg,
2852 SC->sc_data_direction);
2853 scb->flags |= IPS_SCB_MAP_SG;
2854 for (i = 0; i < scb->sg_count; i++) {
2855 if (ips_fill_scb_sg_single
2856 (ha, sg_dma_address(&sg[i]), scb, i,
2857 sg_dma_len(&sg[i])) < 0)
2858 break;
2859 }
2860 scb->dcdb.transfer_length = scb->data_len;
2861 } else {
2862 if (SC->request_bufflen) {
2863 scb->data_busaddr =
2864 pci_map_single(ha->pcidev,
2865 SC->request_buffer,
2866 SC->request_bufflen,
2867 SC->sc_data_direction);
2868 scb->flags |= IPS_SCB_MAP_SINGLE;
2869 ips_fill_scb_sg_single(ha, scb->data_busaddr,
2870 scb, 0,
2871 SC->request_bufflen);
2872 scb->dcdb.transfer_length = scb->data_len;
2873 } else {
2874 scb->data_busaddr = 0L;
2875 scb->sg_len = 0;
2876 scb->data_len = 0;
2877 scb->dcdb.transfer_length = 0;
2878 }
2879
2880 }
2881
2882 scb->dcdb.cmd_attribute =
2883 ips_command_direction[scb->scsi_cmd->cmnd[0]];
2884
2885 /* Allow a WRITE BUFFER Command to Have no Data */
2886 /* This is Used by Tape Flash Utilites */
2887 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) && (scb->data_len == 0))
2888 scb->dcdb.cmd_attribute = 0;
2889
2890 if (!(scb->dcdb.cmd_attribute & 0x3))
2891 scb->dcdb.transfer_length = 0;
2892
2893 if (scb->data_len >= IPS_MAX_XFER) {
2894 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
2895 scb->dcdb.transfer_length = 0;
2896 }
2897 if (intr == IPS_INTR_ON)
2898 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
2899
2900 ret = ips_send_cmd(ha, scb);
2901
2902 switch (ret) {
2903 case IPS_SUCCESS:
2904 ips_putq_scb_head(&ha->scb_activelist, scb);
2905 break;
2906 case IPS_FAILURE:
2907 if (scb->scsi_cmd) {
2908 scb->scsi_cmd->result = DID_ERROR << 16;
2909 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2910 }
2911
2912 if (scb->bus)
2913 ha->dcdb_active[scb->bus - 1] &=
2914 ~(1 << scb->target_id);
2915
2916 ips_freescb(ha, scb);
2917 break;
2918 case IPS_SUCCESS_IMM:
2919 if (scb->scsi_cmd)
2920 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2921
2922 if (scb->bus)
2923 ha->dcdb_active[scb->bus - 1] &=
2924 ~(1 << scb->target_id);
2925
2926 ips_freescb(ha, scb);
2927 break;
2928 default:
2929 break;
2930 } /* end case */
2931
2932 p = (Scsi_Cmnd *) p->host_scribble;
2933
2934 } /* end while */
2935
2936 if (intr == IPS_INTR_ON)
2937 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
2938 }
2939
2940 /****************************************************************************/
2941 /* */
2942 /* Routine Name: ips_putq_scb_head */
2943 /* */
2944 /* Routine Description: */
2945 /* */
2946 /* Add an item to the head of the queue */
2947 /* */
2948 /* ASSUMED to be called from within the HA lock */
2949 /* */
2950 /****************************************************************************/
2951 static void
2952 ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item)
2953 {
2954 METHOD_TRACE("ips_putq_scb_head", 1);
2955
2956 if (!item)
2957 return;
2958
2959 item->q_next = queue->head;
2960 queue->head = item;
2961
2962 if (!queue->tail)
2963 queue->tail = item;
2964
2965 queue->count++;
2966 }
2967
2968 /****************************************************************************/
2969 /* */
2970 /* Routine Name: ips_removeq_scb_head */
2971 /* */
2972 /* Routine Description: */
2973 /* */
2974 /* Remove the head of the queue */
2975 /* */
2976 /* ASSUMED to be called from within the HA lock */
2977 /* */
2978 /****************************************************************************/
2979 static ips_scb_t *
2980 ips_removeq_scb_head(ips_scb_queue_t * queue)
2981 {
2982 ips_scb_t *item;
2983
2984 METHOD_TRACE("ips_removeq_scb_head", 1);
2985
2986 item = queue->head;
2987
2988 if (!item) {
2989 return (NULL);
2990 }
2991
2992 queue->head = item->q_next;
2993 item->q_next = NULL;
2994
2995 if (queue->tail == item)
2996 queue->tail = NULL;
2997
2998 queue->count--;
2999
3000 return (item);
3001 }
3002
3003 /****************************************************************************/
3004 /* */
3005 /* Routine Name: ips_removeq_scb */
3006 /* */
3007 /* Routine Description: */
3008 /* */
3009 /* Remove an item from a queue */
3010 /* */
3011 /* ASSUMED to be called from within the HA lock */
3012 /* */
3013 /****************************************************************************/
3014 static ips_scb_t *
3015 ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item)
3016 {
3017 ips_scb_t *p;
3018
3019 METHOD_TRACE("ips_removeq_scb", 1);
3020
3021 if (!item)
3022 return (NULL);
3023
3024 if (item == queue->head) {
3025 return (ips_removeq_scb_head(queue));
3026 }
3027
3028 p = queue->head;
3029
3030 while ((p) && (item != p->q_next))
3031 p = p->q_next;
3032
3033 if (p) {
3034 /* found a match */
3035 p->q_next = item->q_next;
3036
3037 if (!item->q_next)
3038 queue->tail = p;
3039
3040 item->q_next = NULL;
3041 queue->count--;
3042
3043 return (item);
3044 }
3045
3046 return (NULL);
3047 }
3048
3049 /****************************************************************************/
3050 /* */
3051 /* Routine Name: ips_putq_wait_tail */
3052 /* */
3053 /* Routine Description: */
3054 /* */
3055 /* Add an item to the tail of the queue */
3056 /* */
3057 /* ASSUMED to be called from within the HA lock */
3058 /* */
3059 /****************************************************************************/
3060 static void
3061 ips_putq_wait_tail(ips_wait_queue_t * queue, Scsi_Cmnd * item)
3062 {
3063 METHOD_TRACE("ips_putq_wait_tail", 1);
3064
3065 if (!item)
3066 return;
3067
3068 item->host_scribble = NULL;
3069
3070 if (queue->tail)
3071 queue->tail->host_scribble = (char *) item;
3072
3073 queue->tail = item;
3074
3075 if (!queue->head)
3076 queue->head = item;
3077
3078 queue->count++;
3079 }
3080
3081 /****************************************************************************/
3082 /* */
3083 /* Routine Name: ips_removeq_wait_head */
3084 /* */
3085 /* Routine Description: */
3086 /* */
3087 /* Remove the head of the queue */
3088 /* */
3089 /* ASSUMED to be called from within the HA lock */
3090 /* */
3091 /****************************************************************************/
3092 static Scsi_Cmnd *
3093 ips_removeq_wait_head(ips_wait_queue_t * queue)
3094 {
3095 Scsi_Cmnd *item;
3096
3097 METHOD_TRACE("ips_removeq_wait_head", 1);
3098
3099 item = queue->head;
3100
3101 if (!item) {
3102 return (NULL);
3103 }
3104
3105 queue->head = (Scsi_Cmnd *) item->host_scribble;
3106 item->host_scribble = NULL;
3107
3108 if (queue->tail == item)
3109 queue->tail = NULL;
3110
3111 queue->count--;
3112
3113 return (item);
3114 }
3115
3116 /****************************************************************************/
3117 /* */
3118 /* Routine Name: ips_removeq_wait */
3119 /* */
3120 /* Routine Description: */
3121 /* */
3122 /* Remove an item from a queue */
3123 /* */
3124 /* ASSUMED to be called from within the HA lock */
3125 /* */
3126 /****************************************************************************/
3127 static Scsi_Cmnd *
3128 ips_removeq_wait(ips_wait_queue_t * queue, Scsi_Cmnd * item)
3129 {
3130 Scsi_Cmnd *p;
3131
3132 METHOD_TRACE("ips_removeq_wait", 1);
3133
3134 if (!item)
3135 return (NULL);
3136
3137 if (item == queue->head) {
3138 return (ips_removeq_wait_head(queue));
3139 }
3140
3141 p = queue->head;
3142
3143 while ((p) && (item != (Scsi_Cmnd *) p->host_scribble))
3144 p = (Scsi_Cmnd *) p->host_scribble;
3145
3146 if (p) {
3147 /* found a match */
3148 p->host_scribble = item->host_scribble;
3149
3150 if (!item->host_scribble)
3151 queue->tail = p;
3152
3153 item->host_scribble = NULL;
3154 queue->count--;
3155
3156 return (item);
3157 }
3158
3159 return (NULL);
3160 }
3161
3162 /****************************************************************************/
3163 /* */
3164 /* Routine Name: ips_putq_copp_tail */
3165 /* */
3166 /* Routine Description: */
3167 /* */
3168 /* Add an item to the tail of the queue */
3169 /* */
3170 /* ASSUMED to be called from within the HA lock */
3171 /* */
3172 /****************************************************************************/
3173 static void
3174 ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3175 {
3176 METHOD_TRACE("ips_putq_copp_tail", 1);
3177
3178 if (!item)
3179 return;
3180
3181 item->next = NULL;
3182
3183 if (queue->tail)
3184 queue->tail->next = item;
3185
3186 queue->tail = item;
3187
3188 if (!queue->head)
3189 queue->head = item;
3190
3191 queue->count++;
3192 }
3193
3194 /****************************************************************************/
3195 /* */
3196 /* Routine Name: ips_removeq_copp_head */
3197 /* */
3198 /* Routine Description: */
3199 /* */
3200 /* Remove the head of the queue */
3201 /* */
3202 /* ASSUMED to be called from within the HA lock */
3203 /* */
3204 /****************************************************************************/
3205 static ips_copp_wait_item_t *
3206 ips_removeq_copp_head(ips_copp_queue_t * queue)
3207 {
3208 ips_copp_wait_item_t *item;
3209
3210 METHOD_TRACE("ips_removeq_copp_head", 1);
3211
3212 item = queue->head;
3213
3214 if (!item) {
3215 return (NULL);
3216 }
3217
3218 queue->head = item->next;
3219 item->next = NULL;
3220
3221 if (queue->tail == item)
3222 queue->tail = NULL;
3223
3224 queue->count--;
3225
3226 return (item);
3227 }
3228
3229 /****************************************************************************/
3230 /* */
3231 /* Routine Name: ips_removeq_copp */
3232 /* */
3233 /* Routine Description: */
3234 /* */
3235 /* Remove an item from a queue */
3236 /* */
3237 /* ASSUMED to be called from within the HA lock */
3238 /* */
3239 /****************************************************************************/
3240 static ips_copp_wait_item_t *
3241 ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3242 {
3243 ips_copp_wait_item_t *p;
3244
3245 METHOD_TRACE("ips_removeq_copp", 1);
3246
3247 if (!item)
3248 return (NULL);
3249
3250 if (item == queue->head) {
3251 return (ips_removeq_copp_head(queue));
3252 }
3253
3254 p = queue->head;
3255
3256 while ((p) && (item != p->next))
3257 p = p->next;
3258
3259 if (p) {
3260 /* found a match */
3261 p->next = item->next;
3262
3263 if (!item->next)
3264 queue->tail = p;
3265
3266 item->next = NULL;
3267 queue->count--;
3268
3269 return (item);
3270 }
3271
3272 return (NULL);
3273 }
3274
3275 /****************************************************************************/
3276 /* */
3277 /* Routine Name: ipsintr_blocking */
3278 /* */
3279 /* Routine Description: */
3280 /* */
3281 /* Finalize an interrupt for internal commands */
3282 /* */
3283 /****************************************************************************/
3284 static void
3285 ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
3286 {
3287 METHOD_TRACE("ipsintr_blocking", 2);
3288
3289 ips_freescb(ha, scb);
3290 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) {
3291 ha->waitflag = FALSE;
3292
3293 return;
3294 }
3295 }
3296
3297 /****************************************************************************/
3298 /* */
3299 /* Routine Name: ipsintr_done */
3300 /* */
3301 /* Routine Description: */
3302 /* */
3303 /* Finalize an interrupt for non-internal commands */
3304 /* */
3305 /****************************************************************************/
3306 static void
3307 ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
3308 {
3309 METHOD_TRACE("ipsintr_done", 2);
3310
3311 if (!scb) {
3312 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3313 "Spurious interrupt; scb NULL.\n");
3314
3315 return;
3316 }
3317
3318 if (scb->scsi_cmd == NULL) {
3319 /* unexpected interrupt */
3320 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3321 "Spurious interrupt; scsi_cmd not set.\n");
3322
3323 return;
3324 }
3325
3326 ips_done(ha, scb);
3327 }
3328
3329 /****************************************************************************/
3330 /* */
3331 /* Routine Name: ips_done */
3332 /* */
3333 /* Routine Description: */
3334 /* */
3335 /* Do housekeeping on completed commands */
3336 /* ASSUMED to be called form within the request lock */
3337 /****************************************************************************/
3338 static void
3339 ips_done(ips_ha_t * ha, ips_scb_t * scb)
3340 {
3341 int ret;
3342
3343 METHOD_TRACE("ips_done", 1);
3344
3345 if (!scb)
3346 return;
3347
3348 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) {
3349 ips_cleanup_passthru(ha, scb);
3350 ha->num_ioctl--;
3351 } else {
3352 /*
3353 * Check to see if this command had too much
3354 * data and had to be broke up. If so, queue
3355 * the rest of the data and continue.
3356 */
3357 if ((scb->breakup) || (scb->sg_break)) {
3358 /* we had a data breakup */
3359 scb->data_len = 0;
3360
3361 if (scb->sg_count) {
3362 /* S/G request */
3363 struct scatterlist *sg;
3364 int ips_sg_index = 0;
3365 int sg_dma_index;
3366
3367 sg = scb->scsi_cmd->request_buffer;
3368
3369 /* Spin forward to last dma chunk */
3370 sg_dma_index = scb->breakup;
3371
3372 /* Take care of possible partial on last chunk */
3373 ips_fill_scb_sg_single(ha,
3374 sg_dma_address(&sg
3375 [sg_dma_index]),
3376 scb, ips_sg_index++,
3377 sg_dma_len(&sg
3378 [sg_dma_index]));
3379
3380 for (; sg_dma_index < scb->sg_count;
3381 sg_dma_index++) {
3382 if (ips_fill_scb_sg_single
3383 (ha,
3384 sg_dma_address(&sg[sg_dma_index]),
3385 scb, ips_sg_index++,
3386 sg_dma_len(&sg[sg_dma_index])) < 0)
3387 break;
3388
3389 }
3390
3391 } else {
3392 /* Non S/G Request */
3393 (void) ips_fill_scb_sg_single(ha,
3394 scb->
3395 data_busaddr +
3396 (scb->sg_break *
3397 ha->max_xfer),
3398 scb, 0,
3399 scb->scsi_cmd->
3400 request_bufflen -
3401 (scb->sg_break *
3402 ha->max_xfer));
3403 }
3404
3405 scb->dcdb.transfer_length = scb->data_len;
3406 scb->dcdb.cmd_attribute |=
3407 ips_command_direction[scb->scsi_cmd->cmnd[0]];
3408
3409 if (!(scb->dcdb.cmd_attribute & 0x3))
3410 scb->dcdb.transfer_length = 0;
3411
3412 if (scb->data_len >= IPS_MAX_XFER) {
3413 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
3414 scb->dcdb.transfer_length = 0;
3415 }
3416
3417 ret = ips_send_cmd(ha, scb);
3418
3419 switch (ret) {
3420 case IPS_FAILURE:
3421 if (scb->scsi_cmd) {
3422 scb->scsi_cmd->result = DID_ERROR << 16;
3423 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3424 }
3425
3426 ips_freescb(ha, scb);
3427 break;
3428 case IPS_SUCCESS_IMM:
3429 if (scb->scsi_cmd) {
3430 scb->scsi_cmd->result = DID_ERROR << 16;
3431 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3432 }
3433
3434 ips_freescb(ha, scb);
3435 break;
3436 default:
3437 break;
3438 } /* end case */
3439
3440 return;
3441 }
3442 } /* end if passthru */
3443
3444 if (scb->bus) {
3445 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
3446 }
3447
3448 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3449
3450 ips_freescb(ha, scb);
3451 }
3452
3453 /****************************************************************************/
3454 /* */
3455 /* Routine Name: ips_map_status */
3456 /* */
3457 /* Routine Description: */
3458 /* */
3459 /* Map Controller Error codes to Linux Error Codes */
3460 /* */
3461 /****************************************************************************/
3462 static int
3463 ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3464 {
3465 int errcode;
3466 int device_error;
3467 uint32_t transfer_len;
3468 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3469
3470 METHOD_TRACE("ips_map_status", 1);
3471
3472 if (scb->bus) {
3473 DEBUG_VAR(2,
3474 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x",
3475 ips_name, ha->host_num,
3476 scb->scsi_cmd->device->channel,
3477 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun,
3478 scb->basic_status, scb->extended_status,
3479 scb->extended_status ==
3480 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0,
3481 scb->extended_status ==
3482 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0,
3483 scb->extended_status ==
3484 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0);
3485 }
3486
3487 /* default driver error */
3488 errcode = DID_ERROR;
3489 device_error = 0;
3490
3491 switch (scb->basic_status & IPS_GSC_STATUS_MASK) {
3492 case IPS_CMD_TIMEOUT:
3493 errcode = DID_TIME_OUT;
3494 break;
3495
3496 case IPS_INVAL_OPCO:
3497 case IPS_INVAL_CMD_BLK:
3498 case IPS_INVAL_PARM_BLK:
3499 case IPS_LD_ERROR:
3500 case IPS_CMD_CMPLT_WERROR:
3501 break;
3502
3503 case IPS_PHYS_DRV_ERROR:
3504 switch (scb->extended_status) {
3505 case IPS_ERR_SEL_TO:
3506 if (scb->bus)
3507 errcode = DID_NO_CONNECT;
3508
3509 break;
3510
3511 case IPS_ERR_OU_RUN:
3512 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) ||
3513 (scb->cmd.dcdb.op_code ==
3514 IPS_CMD_EXTENDED_DCDB_SG)) {
3515 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3516 transfer_len = tapeDCDB->transfer_length;
3517 } else {
3518 transfer_len =
3519 (uint32_t) scb->dcdb.transfer_length;
3520 }
3521
3522 if ((scb->bus) && (transfer_len < scb->data_len)) {
3523 /* Underrun - set default to no error */
3524 errcode = DID_OK;
3525
3526 /* Restrict access to physical DASD */
3527 if ((scb->scsi_cmd->cmnd[0] == INQUIRY) &&
3528 ((((char *) scb->scsi_cmd->
3529 buffer)[0] & 0x1f) == TYPE_DISK)) {
3530 /* underflow -- no error */
3531 /* restrict access to physical DASD */
3532 errcode = DID_TIME_OUT;
3533 break;
3534 }
3535 } else
3536 errcode = DID_ERROR;
3537
3538 break;
3539
3540 case IPS_ERR_RECOVERY:
3541 /* don't fail recovered errors */
3542 if (scb->bus)
3543 errcode = DID_OK;
3544
3545 break;
3546
3547 case IPS_ERR_HOST_RESET:
3548 case IPS_ERR_DEV_RESET:
3549 errcode = DID_RESET;
3550 break;
3551
3552 case IPS_ERR_CKCOND:
3553 if (scb->bus) {
3554 if ((scb->cmd.dcdb.op_code ==
3555 IPS_CMD_EXTENDED_DCDB)
3556 || (scb->cmd.dcdb.op_code ==
3557 IPS_CMD_EXTENDED_DCDB_SG)) {
3558 tapeDCDB =
3559 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3560 memcpy(scb->scsi_cmd->sense_buffer,
3561 tapeDCDB->sense_info,
3562 sizeof (scb->scsi_cmd->
3563 sense_buffer));
3564 } else {
3565 memcpy(scb->scsi_cmd->sense_buffer,
3566 scb->dcdb.sense_info,
3567 sizeof (scb->scsi_cmd->
3568 sense_buffer));
3569 }
3570 device_error = 2; /* check condition */
3571 }
3572
3573 errcode = DID_OK;
3574
3575 break;
3576
3577 default:
3578 errcode = DID_ERROR;
3579 break;
3580
3581 } /* end switch */
3582 } /* end switch */
3583
3584 scb->scsi_cmd->result = device_error | (errcode << 16);
3585
3586 return (1);
3587 }
3588
3589 /****************************************************************************/
3590 /* */
3591 /* Routine Name: ips_send_wait */
3592 /* */
3593 /* Routine Description: */
3594 /* */
3595 /* Send a command to the controller and wait for it to return */
3596 /* */
3597 /* The FFDC Time Stamp use this function for the callback, but doesn't */
3598 /* actually need to wait. */
3599 /****************************************************************************/
3600 static int
3601 ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
3602 {
3603 int ret;
3604
3605 METHOD_TRACE("ips_send_wait", 1);
3606
3607 if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */
3608 ha->waitflag = TRUE;
3609 ha->cmd_in_progress = scb->cdb[0];
3610 }
3611 scb->callback = ipsintr_blocking;
3612 ret = ips_send_cmd(ha, scb);
3613
3614 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM))
3615 return (ret);
3616
3617 if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */
3618 ret = ips_wait(ha, timeout, intr);
3619
3620 return (ret);
3621 }
3622
3623 /****************************************************************************/
3624 /* */
3625 /* Routine Name: ips_scmd_buf_write */
3626 /* */
3627 /* Routine Description: */
3628 /* Write data to Scsi_Cmnd request_buffer at proper offsets */
3629 /****************************************************************************/
3630 static void
3631 ips_scmd_buf_write(Scsi_Cmnd * scmd, void *data, unsigned
3632 int count)
3633 {
3634 if (scmd->use_sg) {
3635 int i;
3636 unsigned int min_cnt, xfer_cnt;
3637 char *cdata = (char *) data;
3638 struct scatterlist *sg = scmd->request_buffer;
3639 for (i = 0, xfer_cnt = 0;
3640 (i < scmd->use_sg) && (xfer_cnt < count); i++) {
3641 if (!IPS_SG_ADDRESS(&sg[i]))
3642 return;
3643 min_cnt = min(count - xfer_cnt, sg[i].length);
3644 memcpy(IPS_SG_ADDRESS(&sg[i]), &cdata[xfer_cnt],
3645 min_cnt);
3646 xfer_cnt += min_cnt;
3647 }
3648
3649 } else {
3650 unsigned int min_cnt = min(count, scmd->request_bufflen);
3651 memcpy(scmd->request_buffer, data, min_cnt);
3652 }
3653 }
3654
3655 /****************************************************************************/
3656 /* */
3657 /* Routine Name: ips_scmd_buf_read */
3658 /* */
3659 /* Routine Description: */
3660 /* Copy data from a Scsi_Cmnd to a new, linear buffer */
3661 /****************************************************************************/
3662 static void
3663 ips_scmd_buf_read(Scsi_Cmnd * scmd, void *data, unsigned
3664 int count)
3665 {
3666 if (scmd->use_sg) {
3667 int i;
3668 unsigned int min_cnt, xfer_cnt;
3669 char *cdata = (char *) data;
3670 struct scatterlist *sg = scmd->request_buffer;
3671 for (i = 0, xfer_cnt = 0;
3672 (i < scmd->use_sg) && (xfer_cnt < count); i++) {
3673 if (!IPS_SG_ADDRESS(&sg[i]))
3674 return;
3675 min_cnt = min(count - xfer_cnt, sg[i].length);
3676 memcpy(&cdata[xfer_cnt], IPS_SG_ADDRESS(&sg[i]),
3677 min_cnt);
3678 xfer_cnt += min_cnt;
3679 }
3680
3681 } else {
3682 unsigned int min_cnt = min(count, scmd->request_bufflen);
3683 memcpy(data, scmd->request_buffer, min_cnt);
3684 }
3685 }
3686
3687 /****************************************************************************/
3688 /* */
3689 /* Routine Name: ips_send_cmd */
3690 /* */
3691 /* Routine Description: */
3692 /* */
3693 /* Map SCSI commands to ServeRAID commands for logical drives */
3694 /* */
3695 /****************************************************************************/
3696 static int
3697 ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3698 {
3699 int ret;
3700 char *sp;
3701 int device_error;
3702 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3703 int TimeOut;
3704
3705 METHOD_TRACE("ips_send_cmd", 1);
3706
3707 ret = IPS_SUCCESS;
3708
3709 if (!scb->scsi_cmd) {
3710 /* internal command */
3711
3712 if (scb->bus > 0) {
3713 /* Controller commands can't be issued */
3714 /* to real devices -- fail them */
3715 if ((ha->waitflag == TRUE) &&
3716 (ha->cmd_in_progress == scb->cdb[0])) {
3717 ha->waitflag = FALSE;
3718 }
3719
3720 return (1);
3721 }
3722 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) {
3723 /* command to logical bus -- interpret */
3724 ret = IPS_SUCCESS_IMM;
3725
3726 switch (scb->scsi_cmd->cmnd[0]) {
3727 case ALLOW_MEDIUM_REMOVAL:
3728 case REZERO_UNIT:
3729 case ERASE:
3730 case WRITE_FILEMARKS:
3731 case SPACE:
3732 scb->scsi_cmd->result = DID_ERROR << 16;
3733 break;
3734
3735 case START_STOP:
3736 scb->scsi_cmd->result = DID_OK << 16;
3737
3738 case TEST_UNIT_READY:
3739 case INQUIRY:
3740 if (scb->target_id == IPS_ADAPTER_ID) {
3741 /*
3742 * Either we have a TUR
3743 * or we have a SCSI inquiry
3744 */
3745 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY)
3746 scb->scsi_cmd->result = DID_OK << 16;
3747
3748 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3749 IPS_SCSI_INQ_DATA inquiry;
3750
3751 memset(&inquiry, 0,
3752 sizeof (IPS_SCSI_INQ_DATA));
3753
3754 inquiry.DeviceType =
3755 IPS_SCSI_INQ_TYPE_PROCESSOR;
3756 inquiry.DeviceTypeQualifier =
3757 IPS_SCSI_INQ_LU_CONNECTED;
3758 inquiry.Version = IPS_SCSI_INQ_REV2;
3759 inquiry.ResponseDataFormat =
3760 IPS_SCSI_INQ_RD_REV2;
3761 inquiry.AdditionalLength = 31;
3762 inquiry.Flags[0] =
3763 IPS_SCSI_INQ_Address16;
3764 inquiry.Flags[1] =
3765 IPS_SCSI_INQ_WBus16 |
3766 IPS_SCSI_INQ_Sync;
3767 strncpy(inquiry.VendorId, "IBM ",
3768 8);
3769 strncpy(inquiry.ProductId,
3770 "SERVERAID ", 16);
3771 strncpy(inquiry.ProductRevisionLevel,
3772 "1.00", 4);
3773
3774 ips_scmd_buf_write(scb->scsi_cmd,
3775 &inquiry,
3776 sizeof (inquiry));
3777
3778 scb->scsi_cmd->result = DID_OK << 16;
3779 }
3780 } else {
3781 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3782 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3783 scb->cmd.logical_info.reserved = 0;
3784 scb->cmd.logical_info.reserved2 = 0;
3785 scb->data_len = sizeof (IPS_LD_INFO);
3786 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3787 scb->flags = 0;
3788 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3789 ret = IPS_SUCCESS;
3790 }
3791
3792 break;
3793
3794 case REQUEST_SENSE:
3795 ips_reqsen(ha, scb);
3796 scb->scsi_cmd->result = DID_OK << 16;
3797 break;
3798
3799 case READ_6:
3800 case WRITE_6:
3801 if (!scb->sg_len) {
3802 scb->cmd.basic_io.op_code =
3803 (scb->scsi_cmd->cmnd[0] ==
3804 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE;
3805 scb->cmd.basic_io.enhanced_sg = 0;
3806 scb->cmd.basic_io.sg_addr =
3807 cpu_to_le32(scb->data_busaddr);
3808 } else {
3809 scb->cmd.basic_io.op_code =
3810 (scb->scsi_cmd->cmnd[0] ==
3811 READ_6) ? IPS_CMD_READ_SG :
3812 IPS_CMD_WRITE_SG;
3813 scb->cmd.basic_io.enhanced_sg =
3814 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3815 scb->cmd.basic_io.sg_addr =
3816 cpu_to_le32(scb->sg_busaddr);
3817 }
3818
3819 scb->cmd.basic_io.segment_4G = 0;
3820 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3821 scb->cmd.basic_io.log_drv = scb->target_id;
3822 scb->cmd.basic_io.sg_count = scb->sg_len;
3823
3824 if (scb->cmd.basic_io.lba)
3825 scb->cmd.basic_io.lba =
3826 cpu_to_le32(le32_to_cpu
3827 (scb->cmd.basic_io.lba) +
3828 le16_to_cpu(scb->cmd.basic_io.
3829 sector_count));
3830 else
3831 scb->cmd.basic_io.lba =
3832 (((scb->scsi_cmd->
3833 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd->
3834 cmnd[2] << 8) |
3835 (scb->scsi_cmd->cmnd[3]));
3836
3837 scb->cmd.basic_io.sector_count =
3838 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3839
3840 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0)
3841 scb->cmd.basic_io.sector_count =
3842 cpu_to_le16(256);
3843
3844 ret = IPS_SUCCESS;
3845 break;
3846
3847 case READ_10:
3848 case WRITE_10:
3849 if (!scb->sg_len) {
3850 scb->cmd.basic_io.op_code =
3851 (scb->scsi_cmd->cmnd[0] ==
3852 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE;
3853 scb->cmd.basic_io.enhanced_sg = 0;
3854 scb->cmd.basic_io.sg_addr =
3855 cpu_to_le32(scb->data_busaddr);
3856 } else {
3857 scb->cmd.basic_io.op_code =
3858 (scb->scsi_cmd->cmnd[0] ==
3859 READ_10) ? IPS_CMD_READ_SG :
3860 IPS_CMD_WRITE_SG;
3861 scb->cmd.basic_io.enhanced_sg =
3862 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3863 scb->cmd.basic_io.sg_addr =
3864 cpu_to_le32(scb->sg_busaddr);
3865 }
3866
3867 scb->cmd.basic_io.segment_4G = 0;
3868 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3869 scb->cmd.basic_io.log_drv = scb->target_id;
3870 scb->cmd.basic_io.sg_count = scb->sg_len;
3871
3872 if (scb->cmd.basic_io.lba)
3873 scb->cmd.basic_io.lba =
3874 cpu_to_le32(le32_to_cpu
3875 (scb->cmd.basic_io.lba) +
3876 le16_to_cpu(scb->cmd.basic_io.
3877 sector_count));
3878 else
3879 scb->cmd.basic_io.lba =
3880 ((scb->scsi_cmd->cmnd[2] << 24) | (scb->
3881 scsi_cmd->
3882 cmnd[3]
3883 << 16) |
3884 (scb->scsi_cmd->cmnd[4] << 8) | scb->
3885 scsi_cmd->cmnd[5]);
3886
3887 scb->cmd.basic_io.sector_count =
3888 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3889
3890 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) {
3891 /*
3892 * This is a null condition
3893 * we don't have to do anything
3894 * so just return
3895 */
3896 scb->scsi_cmd->result = DID_OK << 16;
3897 } else
3898 ret = IPS_SUCCESS;
3899
3900 break;
3901
3902 case RESERVE:
3903 case RELEASE:
3904 scb->scsi_cmd->result = DID_OK << 16;
3905 break;
3906
3907 case MODE_SENSE:
3908 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
3909 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3910 scb->cmd.basic_io.segment_4G = 0;
3911 scb->cmd.basic_io.enhanced_sg = 0;
3912 scb->data_len = sizeof (*ha->enq);
3913 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
3914 ret = IPS_SUCCESS;
3915 break;
3916
3917 case READ_CAPACITY:
3918 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3919 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3920 scb->cmd.logical_info.reserved = 0;
3921 scb->cmd.logical_info.reserved2 = 0;
3922 scb->cmd.logical_info.reserved3 = 0;
3923 scb->data_len = sizeof (IPS_LD_INFO);
3924 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3925 scb->flags = 0;
3926 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3927 ret = IPS_SUCCESS;
3928 break;
3929
3930 case SEND_DIAGNOSTIC:
3931 case REASSIGN_BLOCKS:
3932 case FORMAT_UNIT:
3933 case SEEK_10:
3934 case VERIFY:
3935 case READ_DEFECT_DATA:
3936 case READ_BUFFER:
3937 case WRITE_BUFFER:
3938 scb->scsi_cmd->result = DID_OK << 16;
3939 break;
3940
3941 default:
3942 /* Set the Return Info to appear like the Command was */
3943 /* attempted, a Check Condition occurred, and Sense */
3944 /* Data indicating an Invalid CDB OpCode is returned. */
3945 sp = (char *) scb->scsi_cmd->sense_buffer;
3946 memset(sp, 0, sizeof (scb->scsi_cmd->sense_buffer));
3947
3948 sp[0] = 0x70; /* Error Code */
3949 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */
3950 sp[7] = 0x0A; /* Additional Sense Length */
3951 sp[12] = 0x20; /* ASC = Invalid OpCode */
3952 sp[13] = 0x00; /* ASCQ */
3953
3954 device_error = 2; /* Indicate Check Condition */
3955 scb->scsi_cmd->result = device_error | (DID_OK << 16);
3956 break;
3957 } /* end switch */
3958 }
3959 /* end if */
3960 if (ret == IPS_SUCCESS_IMM)
3961 return (ret);
3962
3963 /* setup DCDB */
3964 if (scb->bus > 0) {
3965
3966 /* If we already know the Device is Not there, no need to attempt a Command */
3967 /* This also protects an NT FailOver Controller from getting CDB's sent to it */
3968 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
3969 scb->scsi_cmd->result = DID_NO_CONNECT << 16;
3970 return (IPS_SUCCESS_IMM);
3971 }
3972
3973 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
3974 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
3975 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
3976 (unsigned long) &scb->
3977 dcdb -
3978 (unsigned long) scb);
3979 scb->cmd.dcdb.reserved = 0;
3980 scb->cmd.dcdb.reserved2 = 0;
3981 scb->cmd.dcdb.reserved3 = 0;
3982 scb->cmd.dcdb.segment_4G = 0;
3983 scb->cmd.dcdb.enhanced_sg = 0;
3984
3985 TimeOut = scb->scsi_cmd->timeout_per_command;
3986
3987 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */
3988 if (!scb->sg_len) {
3989 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB;
3990 } else {
3991 scb->cmd.dcdb.op_code =
3992 IPS_CMD_EXTENDED_DCDB_SG;
3993 scb->cmd.dcdb.enhanced_sg =
3994 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3995 }
3996
3997 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */
3998 tapeDCDB->device_address =
3999 ((scb->bus - 1) << 4) | scb->target_id;
4000 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED;
4001 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */
4002
4003 if (TimeOut) {
4004 if (TimeOut < (10 * HZ))
4005 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
4006 else if (TimeOut < (60 * HZ))
4007 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
4008 else if (TimeOut < (1200 * HZ))
4009 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
4010 }
4011
4012 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len;
4013 tapeDCDB->reserved_for_LUN = 0;
4014 tapeDCDB->transfer_length = scb->data_len;
4015 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG)
4016 tapeDCDB->buffer_pointer =
4017 cpu_to_le32(scb->sg_busaddr);
4018 else
4019 tapeDCDB->buffer_pointer =
4020 cpu_to_le32(scb->data_busaddr);
4021 tapeDCDB->sg_count = scb->sg_len;
4022 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info);
4023 tapeDCDB->scsi_status = 0;
4024 tapeDCDB->reserved = 0;
4025 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd,
4026 scb->scsi_cmd->cmd_len);
4027 } else {
4028 if (!scb->sg_len) {
4029 scb->cmd.dcdb.op_code = IPS_CMD_DCDB;
4030 } else {
4031 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG;
4032 scb->cmd.dcdb.enhanced_sg =
4033 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
4034 }
4035
4036 scb->dcdb.device_address =
4037 ((scb->bus - 1) << 4) | scb->target_id;
4038 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED;
4039
4040 if (TimeOut) {
4041 if (TimeOut < (10 * HZ))
4042 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
4043 else if (TimeOut < (60 * HZ))
4044 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
4045 else if (TimeOut < (1200 * HZ))
4046 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
4047 }
4048
4049 scb->dcdb.transfer_length = scb->data_len;
4050 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K)
4051 scb->dcdb.transfer_length = 0;
4052 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG)
4053 scb->dcdb.buffer_pointer =
4054 cpu_to_le32(scb->sg_busaddr);
4055 else
4056 scb->dcdb.buffer_pointer =
4057 cpu_to_le32(scb->data_busaddr);
4058 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len;
4059 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info);
4060 scb->dcdb.sg_count = scb->sg_len;
4061 scb->dcdb.reserved = 0;
4062 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd,
4063 scb->scsi_cmd->cmd_len);
4064 scb->dcdb.scsi_status = 0;
4065 scb->dcdb.reserved2[0] = 0;
4066 scb->dcdb.reserved2[1] = 0;
4067 scb->dcdb.reserved2[2] = 0;
4068 }
4069 }
4070
4071 return ((*ha->func.issue) (ha, scb));
4072 }
4073
4074 /****************************************************************************/
4075 /* */
4076 /* Routine Name: ips_chk_status */
4077 /* */
4078 /* Routine Description: */
4079 /* */
4080 /* Check the status of commands to logical drives */
4081 /* Assumed to be called with the HA lock */
4082 /****************************************************************************/
4083 static void
4084 ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
4085 {
4086 ips_scb_t *scb;
4087 ips_stat_t *sp;
4088 uint8_t basic_status;
4089 uint8_t ext_status;
4090 int errcode;
4091
4092 METHOD_TRACE("ips_chkstatus", 1);
4093
4094 scb = &ha->scbs[pstatus->fields.command_id];
4095 scb->basic_status = basic_status =
4096 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK;
4097 scb->extended_status = ext_status = pstatus->fields.extended_status;
4098
4099 sp = &ha->sp;
4100 sp->residue_len = 0;
4101 sp->scb_addr = (void *) scb;
4102
4103 /* Remove the item from the active queue */
4104 ips_removeq_scb(&ha->scb_activelist, scb);
4105
4106 if (!scb->scsi_cmd)
4107 /* internal commands are handled in do_ipsintr */
4108 return;
4109
4110 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)",
4111 ips_name,
4112 ha->host_num,
4113 scb->cdb[0],
4114 scb->cmd.basic_io.command_id,
4115 scb->bus, scb->target_id, scb->lun);
4116
4117 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd)))
4118 /* passthru - just returns the raw result */
4119 return;
4120
4121 errcode = DID_OK;
4122
4123 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) ||
4124 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) {
4125
4126 if (scb->bus == 0) {
4127 if ((basic_status & IPS_GSC_STATUS_MASK) ==
4128 IPS_CMD_RECOVERED_ERROR) {
4129 DEBUG_VAR(1,
4130 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
4131 ips_name, ha->host_num,
4132 scb->cmd.basic_io.op_code,
4133 basic_status, ext_status);
4134 }
4135
4136 switch (scb->scsi_cmd->cmnd[0]) {
4137 case ALLOW_MEDIUM_REMOVAL:
4138 case REZERO_UNIT:
4139 case ERASE:
4140 case WRITE_FILEMARKS:
4141 case SPACE:
4142 errcode = DID_ERROR;
4143 break;
4144
4145 case START_STOP:
4146 break;
4147
4148 case TEST_UNIT_READY:
4149 if (!ips_online(ha, scb)) {
4150 errcode = DID_TIME_OUT;
4151 }
4152 break;
4153
4154 case INQUIRY:
4155 if (ips_online(ha, scb)) {
4156 ips_inquiry(ha, scb);
4157 } else {
4158 errcode = DID_TIME_OUT;
4159 }
4160 break;
4161
4162 case REQUEST_SENSE:
4163 ips_reqsen(ha, scb);
4164 break;
4165
4166 case READ_6:
4167 case WRITE_6:
4168 case READ_10:
4169 case WRITE_10:
4170 case RESERVE:
4171 case RELEASE:
4172 break;
4173
4174 case MODE_SENSE:
4175 if (!ips_online(ha, scb)
4176 || !ips_msense(ha, scb)) {
4177 errcode = DID_ERROR;
4178 }
4179 break;
4180
4181 case READ_CAPACITY:
4182 if (ips_online(ha, scb))
4183 ips_rdcap(ha, scb);
4184 else {
4185 errcode = DID_TIME_OUT;
4186 }
4187 break;
4188
4189 case SEND_DIAGNOSTIC:
4190 case REASSIGN_BLOCKS:
4191 break;
4192
4193 case FORMAT_UNIT:
4194 errcode = DID_ERROR;
4195 break;
4196
4197 case SEEK_10:
4198 case VERIFY:
4199 case READ_DEFECT_DATA:
4200 case READ_BUFFER:
4201 case WRITE_BUFFER:
4202 break;
4203
4204 default:
4205 errcode = DID_ERROR;
4206 } /* end switch */
4207
4208 scb->scsi_cmd->result = errcode << 16;
4209 } else { /* bus == 0 */
4210 /* restrict access to physical drives */
4211 if ((scb->scsi_cmd->cmnd[0] == INQUIRY) &&
4212 ((((char *) scb->scsi_cmd->buffer)[0] & 0x1f) ==
4213 TYPE_DISK)) {
4214
4215 scb->scsi_cmd->result = DID_TIME_OUT << 16;
4216 }
4217 } /* else */
4218 } else { /* recovered error / success */
4219 if (scb->bus == 0) {
4220 DEBUG_VAR(1,
4221 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
4222 ips_name, ha->host_num,
4223 scb->cmd.basic_io.op_code, basic_status,
4224 ext_status);
4225 }
4226
4227 ips_map_status(ha, scb, sp);
4228 } /* else */
4229 }
4230
4231 /****************************************************************************/
4232 /* */
4233 /* Routine Name: ips_online */
4234 /* */
4235 /* Routine Description: */
4236 /* */
4237 /* Determine if a logical drive is online */
4238 /* */
4239 /****************************************************************************/
4240 static int
4241 ips_online(ips_ha_t * ha, ips_scb_t * scb)
4242 {
4243 METHOD_TRACE("ips_online", 1);
4244
4245 if (scb->target_id >= IPS_MAX_LD)
4246 return (0);
4247
4248 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) {
4249 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
4250 return (0);
4251 }
4252
4253 if (ha->logical_drive_info->drive_info[scb->target_id].state !=
4254 IPS_LD_OFFLINE
4255 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4256 IPS_LD_FREE
4257 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4258 IPS_LD_CRS
4259 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4260 IPS_LD_SYS)
4261 return (1);
4262 else
4263 return (0);
4264 }
4265
4266 /****************************************************************************/
4267 /* */
4268 /* Routine Name: ips_inquiry */
4269 /* */
4270 /* Routine Description: */
4271 /* */
4272 /* Simulate an inquiry command to a logical drive */
4273 /* */
4274 /****************************************************************************/
4275 static int
4276 ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
4277 {
4278 IPS_SCSI_INQ_DATA inquiry;
4279
4280 METHOD_TRACE("ips_inquiry", 1);
4281
4282 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA));
4283
4284 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD;
4285 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED;
4286 inquiry.Version = IPS_SCSI_INQ_REV2;
4287 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2;
4288 inquiry.AdditionalLength = 31;
4289 inquiry.Flags[0] = IPS_SCSI_INQ_Address16;
4290 inquiry.Flags[1] =
4291 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue;
4292 strncpy(inquiry.VendorId, "IBM ", 8);
4293 strncpy(inquiry.ProductId, "SERVERAID ", 16);
4294 strncpy(inquiry.ProductRevisionLevel, "1.00", 4);
4295
4296 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry));
4297
4298 return (1);
4299 }
4300
4301 /****************************************************************************/
4302 /* */
4303 /* Routine Name: ips_rdcap */
4304 /* */
4305 /* Routine Description: */
4306 /* */
4307 /* Simulate a read capacity command to a logical drive */
4308 /* */
4309 /****************************************************************************/
4310 static int
4311 ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
4312 {
4313 IPS_SCSI_CAPACITY cap;
4314
4315 METHOD_TRACE("ips_rdcap", 1);
4316
4317 if (scb->scsi_cmd->bufflen < 8)
4318 return (0);
4319
4320 cap.lba =
4321 cpu_to_be32(le32_to_cpu
4322 (ha->logical_drive_info->
4323 drive_info[scb->target_id].sector_count) - 1);
4324 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE);
4325
4326 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap));
4327
4328 return (1);
4329 }
4330
4331 /****************************************************************************/
4332 /* */
4333 /* Routine Name: ips_msense */
4334 /* */
4335 /* Routine Description: */
4336 /* */
4337 /* Simulate a mode sense command to a logical drive */
4338 /* */
4339 /****************************************************************************/
4340 static int
4341 ips_msense(ips_ha_t * ha, ips_scb_t * scb)
4342 {
4343 uint16_t heads;
4344 uint16_t sectors;
4345 uint32_t cylinders;
4346 IPS_SCSI_MODE_PAGE_DATA mdata;
4347
4348 METHOD_TRACE("ips_msense", 1);
4349
4350 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
4351 (ha->enq->ucMiscFlag & 0x8) == 0) {
4352 heads = IPS_NORM_HEADS;
4353 sectors = IPS_NORM_SECTORS;
4354 } else {
4355 heads = IPS_COMP_HEADS;
4356 sectors = IPS_COMP_SECTORS;
4357 }
4358
4359 cylinders =
4360 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
4361 1) / (heads * sectors);
4362
4363 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA));
4364
4365 mdata.hdr.BlockDescLength = 8;
4366
4367 switch (scb->scsi_cmd->cmnd[2] & 0x3f) {
4368 case 0x03: /* page 3 */
4369 mdata.pdata.pg3.PageCode = 3;
4370 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3);
4371 mdata.hdr.DataLength =
4372 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength;
4373 mdata.pdata.pg3.TracksPerZone = 0;
4374 mdata.pdata.pg3.AltSectorsPerZone = 0;
4375 mdata.pdata.pg3.AltTracksPerZone = 0;
4376 mdata.pdata.pg3.AltTracksPerVolume = 0;
4377 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors);
4378 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE);
4379 mdata.pdata.pg3.Interleave = cpu_to_be16(1);
4380 mdata.pdata.pg3.TrackSkew = 0;
4381 mdata.pdata.pg3.CylinderSkew = 0;
4382 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector;
4383 break;
4384
4385 case 0x4:
4386 mdata.pdata.pg4.PageCode = 4;
4387 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4);
4388 mdata.hdr.DataLength =
4389 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength;
4390 mdata.pdata.pg4.CylindersHigh =
4391 cpu_to_be16((cylinders >> 8) & 0xFFFF);
4392 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF);
4393 mdata.pdata.pg4.Heads = heads;
4394 mdata.pdata.pg4.WritePrecompHigh = 0;
4395 mdata.pdata.pg4.WritePrecompLow = 0;
4396 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0;
4397 mdata.pdata.pg4.ReducedWriteCurrentLow = 0;
4398 mdata.pdata.pg4.StepRate = cpu_to_be16(1);
4399 mdata.pdata.pg4.LandingZoneHigh = 0;
4400 mdata.pdata.pg4.LandingZoneLow = 0;
4401 mdata.pdata.pg4.flags = 0;
4402 mdata.pdata.pg4.RotationalOffset = 0;
4403 mdata.pdata.pg4.MediumRotationRate = 0;
4404 break;
4405 case 0x8:
4406 mdata.pdata.pg8.PageCode = 8;
4407 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8);
4408 mdata.hdr.DataLength =
4409 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength;
4410 /* everything else is left set to 0 */
4411 break;
4412
4413 default:
4414 return (0);
4415 } /* end switch */
4416
4417 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata));
4418
4419 return (1);
4420 }
4421
4422 /****************************************************************************/
4423 /* */
4424 /* Routine Name: ips_reqsen */
4425 /* */
4426 /* Routine Description: */
4427 /* */
4428 /* Simulate a request sense command to a logical drive */
4429 /* */
4430 /****************************************************************************/
4431 static int
4432 ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
4433 {
4434 IPS_SCSI_REQSEN reqsen;
4435
4436 METHOD_TRACE("ips_reqsen", 1);
4437
4438 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN));
4439
4440 reqsen.ResponseCode =
4441 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR;
4442 reqsen.AdditionalLength = 10;
4443 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE;
4444 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE;
4445
4446 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen));
4447
4448 return (1);
4449 }
4450
4451 /****************************************************************************/
4452 /* */
4453 /* Routine Name: ips_free */
4454 /* */
4455 /* Routine Description: */
4456 /* */
4457 /* Free any allocated space for this controller */
4458 /* */
4459 /****************************************************************************/
4460 static void
4461 ips_free(ips_ha_t * ha)
4462 {
4463
4464 METHOD_TRACE("ips_free", 1);
4465
4466 if (ha) {
4467 if (ha->enq) {
4468 pci_free_consistent(ha->pcidev, sizeof(IPS_ENQ),
4469 ha->enq, ha->enq_busaddr);
4470 ha->enq = NULL;
4471 }
4472
4473 if (ha->conf) {
4474 kfree(ha->conf);
4475 ha->conf = NULL;
4476 }
4477
4478 if (ha->adapt) {
4479 pci_free_consistent(ha->pcidev,
4480 sizeof (IPS_ADAPTER) +
4481 sizeof (IPS_IO_CMD), ha->adapt,
4482 ha->adapt->hw_status_start);
4483 ha->adapt = NULL;
4484 }
4485
4486 if (ha->logical_drive_info) {
4487 pci_free_consistent(ha->pcidev,
4488 sizeof (IPS_LD_INFO),
4489 ha->logical_drive_info,
4490 ha->logical_drive_info_dma_addr);
4491 ha->logical_drive_info = NULL;
4492 }
4493
4494 if (ha->nvram) {
4495 kfree(ha->nvram);
4496 ha->nvram = NULL;
4497 }
4498
4499 if (ha->subsys) {
4500 kfree(ha->subsys);
4501 ha->subsys = NULL;
4502 }
4503
4504 if (ha->ioctl_data) {
4505 pci_free_consistent(ha->pcidev, ha->ioctl_len,
4506 ha->ioctl_data, ha->ioctl_busaddr);
4507 ha->ioctl_data = NULL;
4508 ha->ioctl_datasize = 0;
4509 ha->ioctl_len = 0;
4510 }
4511 ips_deallocatescbs(ha, ha->max_cmds);
4512
4513 /* free memory mapped (if applicable) */
4514 if (ha->mem_ptr) {
4515 iounmap(ha->ioremap_ptr);
4516 ha->ioremap_ptr = NULL;
4517 ha->mem_ptr = NULL;
4518 }
4519
4520 if (ha->mem_addr)
4521 release_mem_region(ha->mem_addr, ha->mem_len);
4522 ha->mem_addr = 0;
4523
4524 }
4525 }
4526
4527 /****************************************************************************/
4528 /* */
4529 /* Routine Name: ips_deallocatescbs */
4530 /* */
4531 /* Routine Description: */
4532 /* */
4533 /* Free the command blocks */
4534 /* */
4535 /****************************************************************************/
4536 static int
4537 ips_deallocatescbs(ips_ha_t * ha, int cmds)
4538 {
4539 if (ha->scbs) {
4540 pci_free_consistent(ha->pcidev,
4541 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
4542 ha->scbs->sg_list.list,
4543 ha->scbs->sg_busaddr);
4544 pci_free_consistent(ha->pcidev, sizeof (ips_scb_t) * cmds,
4545 ha->scbs, ha->scbs->scb_busaddr);
4546 ha->scbs = NULL;
4547 } /* end if */
4548 return 1;
4549 }
4550
4551 /****************************************************************************/
4552 /* */
4553 /* Routine Name: ips_allocatescbs */
4554 /* */
4555 /* Routine Description: */
4556 /* */
4557 /* Allocate the command blocks */
4558 /* */
4559 /****************************************************************************/
4560 static int
4561 ips_allocatescbs(ips_ha_t * ha)
4562 {
4563 ips_scb_t *scb_p;
4564 IPS_SG_LIST ips_sg;
4565 int i;
4566 dma_addr_t command_dma, sg_dma;
4567
4568 METHOD_TRACE("ips_allocatescbs", 1);
4569
4570 /* Allocate memory for the SCBs */
4571 ha->scbs =
4572 pci_alloc_consistent(ha->pcidev, ha->max_cmds * sizeof (ips_scb_t),
4573 &command_dma);
4574 if (ha->scbs == NULL)
4575 return 0;
4576 ips_sg.list =
4577 pci_alloc_consistent(ha->pcidev,
4578 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG *
4579 ha->max_cmds, &sg_dma);
4580 if (ips_sg.list == NULL) {
4581 pci_free_consistent(ha->pcidev,
4582 ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
4583 command_dma);
4584 return 0;
4585 }
4586
4587 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
4588
4589 for (i = 0; i < ha->max_cmds; i++) {
4590 scb_p = &ha->scbs[i];
4591 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i;
4592 /* set up S/G list */
4593 if (IPS_USE_ENH_SGLIST(ha)) {
4594 scb_p->sg_list.enh_list =
4595 ips_sg.enh_list + i * IPS_MAX_SG;
4596 scb_p->sg_busaddr =
4597 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4598 } else {
4599 scb_p->sg_list.std_list =
4600 ips_sg.std_list + i * IPS_MAX_SG;
4601 scb_p->sg_busaddr =
4602 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4603 }
4604
4605 /* add to the free list */
4606 if (i < ha->max_cmds - 1) {
4607 scb_p->q_next = ha->scb_freelist;
4608 ha->scb_freelist = scb_p;
4609 }
4610 }
4611
4612 /* success */
4613 return (1);
4614 }
4615
4616 /****************************************************************************/
4617 /* */
4618 /* Routine Name: ips_init_scb */
4619 /* */
4620 /* Routine Description: */
4621 /* */
4622 /* Initialize a CCB to default values */
4623 /* */
4624 /****************************************************************************/
4625 static void
4626 ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
4627 {
4628 IPS_SG_LIST sg_list;
4629 uint32_t cmd_busaddr, sg_busaddr;
4630 METHOD_TRACE("ips_init_scb", 1);
4631
4632 if (scb == NULL)
4633 return;
4634
4635 sg_list.list = scb->sg_list.list;
4636 cmd_busaddr = scb->scb_busaddr;
4637 sg_busaddr = scb->sg_busaddr;
4638 /* zero fill */
4639 memset(scb, 0, sizeof (ips_scb_t));
4640 memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
4641
4642 /* Initialize dummy command bucket */
4643 ha->dummy->op_code = 0xFF;
4644 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
4645 + sizeof (IPS_ADAPTER));
4646 ha->dummy->command_id = IPS_MAX_CMDS;
4647
4648 /* set bus address of scb */
4649 scb->scb_busaddr = cmd_busaddr;
4650 scb->sg_busaddr = sg_busaddr;
4651 scb->sg_list.list = sg_list.list;
4652
4653 /* Neptune Fix */
4654 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE);
4655 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
4656 + sizeof (IPS_ADAPTER));
4657 }
4658
4659 /****************************************************************************/
4660 /* */
4661 /* Routine Name: ips_get_scb */
4662 /* */
4663 /* Routine Description: */
4664 /* */
4665 /* Initialize a CCB to default values */
4666 /* */
4667 /* ASSUMED to be callled from within a lock */
4668 /* */
4669 /****************************************************************************/
4670 static ips_scb_t *
4671 ips_getscb(ips_ha_t * ha)
4672 {
4673 ips_scb_t *scb;
4674
4675 METHOD_TRACE("ips_getscb", 1);
4676
4677 if ((scb = ha->scb_freelist) == NULL) {
4678
4679 return (NULL);
4680 }
4681
4682 ha->scb_freelist = scb->q_next;
4683 scb->flags = 0;
4684 scb->q_next = NULL;
4685
4686 ips_init_scb(ha, scb);
4687
4688 return (scb);
4689 }
4690
4691 /****************************************************************************/
4692 /* */
4693 /* Routine Name: ips_free_scb */
4694 /* */
4695 /* Routine Description: */
4696 /* */
4697 /* Return an unused CCB back to the free list */
4698 /* */
4699 /* ASSUMED to be called from within a lock */
4700 /* */
4701 /****************************************************************************/
4702 static void
4703 ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
4704 {
4705
4706 METHOD_TRACE("ips_freescb", 1);
4707 if (scb->flags & IPS_SCB_MAP_SG)
4708 pci_unmap_sg(ha->pcidev, scb->scsi_cmd->request_buffer,
4709 scb->scsi_cmd->use_sg, IPS_DMA_DIR(scb));
4710 else if (scb->flags & IPS_SCB_MAP_SINGLE)
4711 pci_unmap_single(ha->pcidev, scb->data_busaddr, scb->data_len,
4712 IPS_DMA_DIR(scb));
4713
4714 /* check to make sure this is not our "special" scb */
4715 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
4716 scb->q_next = ha->scb_freelist;
4717 ha->scb_freelist = scb;
4718 }
4719 }
4720
4721 /****************************************************************************/
4722 /* */
4723 /* Routine Name: ips_isinit_copperhead */
4724 /* */
4725 /* Routine Description: */
4726 /* */
4727 /* Is controller initialized ? */
4728 /* */
4729 /****************************************************************************/
4730 static int
4731 ips_isinit_copperhead(ips_ha_t * ha)
4732 {
4733 uint8_t scpr;
4734 uint8_t isr;
4735
4736 METHOD_TRACE("ips_isinit_copperhead", 1);
4737
4738 isr = inb(ha->io_addr + IPS_REG_HISR);
4739 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4740
4741 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4742 return (0);
4743 else
4744 return (1);
4745 }
4746
4747 /****************************************************************************/
4748 /* */
4749 /* Routine Name: ips_isinit_copperhead_memio */
4750 /* */
4751 /* Routine Description: */
4752 /* */
4753 /* Is controller initialized ? */
4754 /* */
4755 /****************************************************************************/
4756 static int
4757 ips_isinit_copperhead_memio(ips_ha_t * ha)
4758 {
4759 uint8_t isr = 0;
4760 uint8_t scpr;
4761
4762 METHOD_TRACE("ips_is_init_copperhead_memio", 1);
4763
4764 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4765 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4766
4767 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4768 return (0);
4769 else
4770 return (1);
4771 }
4772
4773 /****************************************************************************/
4774 /* */
4775 /* Routine Name: ips_isinit_morpheus */
4776 /* */
4777 /* Routine Description: */
4778 /* */
4779 /* Is controller initialized ? */
4780 /* */
4781 /****************************************************************************/
4782 static int
4783 ips_isinit_morpheus(ips_ha_t * ha)
4784 {
4785 uint32_t post;
4786 uint32_t bits;
4787
4788 METHOD_TRACE("ips_is_init_morpheus", 1);
4789
4790 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4791 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4792
4793 if (post == 0)
4794 return (0);
4795 else if (bits & 0x3)
4796 return (0);
4797 else
4798 return (1);
4799 }
4800
4801 /****************************************************************************/
4802 /* */
4803 /* Routine Name: ips_enable_int_copperhead */
4804 /* */
4805 /* Routine Description: */
4806 /* Turn on interrupts */
4807 /* */
4808 /****************************************************************************/
4809 static void
4810 ips_enable_int_copperhead(ips_ha_t * ha)
4811 {
4812 METHOD_TRACE("ips_enable_int_copperhead", 1);
4813
4814 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4815 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4816 }
4817
4818 /****************************************************************************/
4819 /* */
4820 /* Routine Name: ips_enable_int_copperhead_memio */
4821 /* */
4822 /* Routine Description: */
4823 /* Turn on interrupts */
4824 /* */
4825 /****************************************************************************/
4826 static void
4827 ips_enable_int_copperhead_memio(ips_ha_t * ha)
4828 {
4829 METHOD_TRACE("ips_enable_int_copperhead_memio", 1);
4830
4831 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4832 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4833 }
4834
4835 /****************************************************************************/
4836 /* */
4837 /* Routine Name: ips_enable_int_morpheus */
4838 /* */
4839 /* Routine Description: */
4840 /* Turn on interrupts */
4841 /* */
4842 /****************************************************************************/
4843 static void
4844 ips_enable_int_morpheus(ips_ha_t * ha)
4845 {
4846 uint32_t Oimr;
4847
4848 METHOD_TRACE("ips_enable_int_morpheus", 1);
4849
4850 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4851 Oimr &= ~0x08;
4852 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4853 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/
4854 }
4855
4856 /****************************************************************************/
4857 /* */
4858 /* Routine Name: ips_init_copperhead */
4859 /* */
4860 /* Routine Description: */
4861 /* */
4862 /* Initialize a copperhead controller */
4863 /* */
4864 /****************************************************************************/
4865 static int
4866 ips_init_copperhead(ips_ha_t * ha)
4867 {
4868 uint8_t Isr;
4869 uint8_t Cbsp;
4870 uint8_t PostByte[IPS_MAX_POST_BYTES];
4871 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4872 int i, j;
4873
4874 METHOD_TRACE("ips_init_copperhead", 1);
4875
4876 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4877 for (j = 0; j < 45; j++) {
4878 Isr = inb(ha->io_addr + IPS_REG_HISR);
4879 if (Isr & IPS_BIT_GHI)
4880 break;
4881
4882 /* Delay for 1 Second */
4883 MDELAY(IPS_ONE_SEC);
4884 }
4885
4886 if (j >= 45)
4887 /* error occurred */
4888 return (0);
4889
4890 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4891 outb(Isr, ha->io_addr + IPS_REG_HISR);
4892 }
4893
4894 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4895 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4896 "reset controller fails (post status %x %x).\n",
4897 PostByte[0], PostByte[1]);
4898
4899 return (0);
4900 }
4901
4902 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4903 for (j = 0; j < 240; j++) {
4904 Isr = inb(ha->io_addr + IPS_REG_HISR);
4905 if (Isr & IPS_BIT_GHI)
4906 break;
4907
4908 /* Delay for 1 Second */
4909 MDELAY(IPS_ONE_SEC);
4910 }
4911
4912 if (j >= 240)
4913 /* error occurred */
4914 return (0);
4915
4916 ConfigByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4917 outb(Isr, ha->io_addr + IPS_REG_HISR);
4918 }
4919
4920 for (i = 0; i < 240; i++) {
4921 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
4922
4923 if ((Cbsp & IPS_BIT_OP) == 0)
4924 break;
4925
4926 /* Delay for 1 Second */
4927 MDELAY(IPS_ONE_SEC);
4928 }
4929
4930 if (i >= 240)
4931 /* reset failed */
4932 return (0);
4933
4934 /* setup CCCR */
4935 outl(cpu_to_le32(0x1010), ha->io_addr + IPS_REG_CCCR);
4936
4937 /* Enable busmastering */
4938 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4939
4940 if (ha->revision_id == IPS_REVID_TROMBONE64)
4941 /* fix for anaconda64 */
4942 outl(0, ha->io_addr + IPS_REG_NDAE);
4943
4944 /* Enable interrupts */
4945 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
4946
4947 return (1);
4948 }
4949
4950 /****************************************************************************/
4951 /* */
4952 /* Routine Name: ips_init_copperhead_memio */
4953 /* */
4954 /* Routine Description: */
4955 /* */
4956 /* Initialize a copperhead controller with memory mapped I/O */
4957 /* */
4958 /****************************************************************************/
4959 static int
4960 ips_init_copperhead_memio(ips_ha_t * ha)
4961 {
4962 uint8_t Isr = 0;
4963 uint8_t Cbsp;
4964 uint8_t PostByte[IPS_MAX_POST_BYTES];
4965 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4966 int i, j;
4967
4968 METHOD_TRACE("ips_init_copperhead_memio", 1);
4969
4970 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4971 for (j = 0; j < 45; j++) {
4972 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4973 if (Isr & IPS_BIT_GHI)
4974 break;
4975
4976 /* Delay for 1 Second */
4977 MDELAY(IPS_ONE_SEC);
4978 }
4979
4980 if (j >= 45)
4981 /* error occurred */
4982 return (0);
4983
4984 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4985 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4986 }
4987
4988 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4989 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4990 "reset controller fails (post status %x %x).\n",
4991 PostByte[0], PostByte[1]);
4992
4993 return (0);
4994 }
4995
4996 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4997 for (j = 0; j < 240; j++) {
4998 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4999 if (Isr & IPS_BIT_GHI)
5000 break;
5001
5002 /* Delay for 1 Second */
5003 MDELAY(IPS_ONE_SEC);
5004 }
5005
5006 if (j >= 240)
5007 /* error occurred */
5008 return (0);
5009
5010 ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
5011 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5012 }
5013
5014 for (i = 0; i < 240; i++) {
5015 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
5016
5017 if ((Cbsp & IPS_BIT_OP) == 0)
5018 break;
5019
5020 /* Delay for 1 Second */
5021 MDELAY(IPS_ONE_SEC);
5022 }
5023
5024 if (i >= 240)
5025 /* error occurred */
5026 return (0);
5027
5028 /* setup CCCR */
5029 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
5030
5031 /* Enable busmastering */
5032 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
5033
5034 if (ha->revision_id == IPS_REVID_TROMBONE64)
5035 /* fix for anaconda64 */
5036 writel(0, ha->mem_ptr + IPS_REG_NDAE);
5037
5038 /* Enable interrupts */
5039 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
5040
5041 /* if we get here then everything went OK */
5042 return (1);
5043 }
5044
5045 /****************************************************************************/
5046 /* */
5047 /* Routine Name: ips_init_morpheus */
5048 /* */
5049 /* Routine Description: */
5050 /* */
5051 /* Initialize a morpheus controller */
5052 /* */
5053 /****************************************************************************/
5054 static int
5055 ips_init_morpheus(ips_ha_t * ha)
5056 {
5057 uint32_t Post;
5058 uint32_t Config;
5059 uint32_t Isr;
5060 uint32_t Oimr;
5061 int i;
5062
5063 METHOD_TRACE("ips_init_morpheus", 1);
5064
5065 /* Wait up to 45 secs for Post */
5066 for (i = 0; i < 45; i++) {
5067 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5068
5069 if (Isr & IPS_BIT_I960_MSG0I)
5070 break;
5071
5072 /* Delay for 1 Second */
5073 MDELAY(IPS_ONE_SEC);
5074 }
5075
5076 if (i >= 45) {
5077 /* error occurred */
5078 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5079 "timeout waiting for post.\n");
5080
5081 return (0);
5082 }
5083
5084 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
5085
5086 if (Post == 0x4F00) { /* If Flashing the Battery PIC */
5087 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5088 "Flashing Battery PIC, Please wait ...\n");
5089
5090 /* Clear the interrupt bit */
5091 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
5092 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5093
5094 for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */
5095 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
5096 if (Post != 0x4F00)
5097 break;
5098 /* Delay for 1 Second */
5099 MDELAY(IPS_ONE_SEC);
5100 }
5101
5102 if (i >= 120) {
5103 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5104 "timeout waiting for Battery PIC Flash\n");
5105 return (0);
5106 }
5107
5108 }
5109
5110 /* Clear the interrupt bit */
5111 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
5112 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5113
5114 if (Post < (IPS_GOOD_POST_STATUS << 8)) {
5115 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5116 "reset controller fails (post status %x).\n", Post);
5117
5118 return (0);
5119 }
5120
5121 /* Wait up to 240 secs for config bytes */
5122 for (i = 0; i < 240; i++) {
5123 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5124
5125 if (Isr & IPS_BIT_I960_MSG1I)
5126 break;
5127
5128 /* Delay for 1 Second */
5129 MDELAY(IPS_ONE_SEC);
5130 }
5131
5132 if (i >= 240) {
5133 /* error occurred */
5134 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5135 "timeout waiting for config.\n");
5136
5137 return (0);
5138 }
5139
5140 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
5141
5142 /* Clear interrupt bit */
5143 Isr = (uint32_t) IPS_BIT_I960_MSG1I;
5144 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5145
5146 /* Turn on the interrupts */
5147 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
5148 Oimr &= ~0x8;
5149 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
5150
5151 /* if we get here then everything went OK */
5152
5153 /* Since we did a RESET, an EraseStripeLock may be needed */
5154 if (Post == 0xEF10) {
5155 if ((Config == 0x000F) || (Config == 0x0009))
5156 ha->requires_esl = 1;
5157 }
5158
5159 return (1);
5160 }
5161
5162 /****************************************************************************/
5163 /* */
5164 /* Routine Name: ips_reset_copperhead */
5165 /* */
5166 /* Routine Description: */
5167 /* */
5168 /* Reset the controller */
5169 /* */
5170 /****************************************************************************/
5171 static int
5172 ips_reset_copperhead(ips_ha_t * ha)
5173 {
5174 int reset_counter;
5175
5176 METHOD_TRACE("ips_reset_copperhead", 1);
5177
5178 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d",
5179 ips_name, ha->host_num, ha->io_addr, ha->irq);
5180
5181 reset_counter = 0;
5182
5183 while (reset_counter < 2) {
5184 reset_counter++;
5185
5186 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5187
5188 /* Delay for 1 Second */
5189 MDELAY(IPS_ONE_SEC);
5190
5191 outb(0, ha->io_addr + IPS_REG_SCPR);
5192
5193 /* Delay for 1 Second */
5194 MDELAY(IPS_ONE_SEC);
5195
5196 if ((*ha->func.init) (ha))
5197 break;
5198 else if (reset_counter >= 2) {
5199
5200 return (0);
5201 }
5202 }
5203
5204 return (1);
5205 }
5206
5207 /****************************************************************************/
5208 /* */
5209 /* Routine Name: ips_reset_copperhead_memio */
5210 /* */
5211 /* Routine Description: */
5212 /* */
5213 /* Reset the controller */
5214 /* */
5215 /****************************************************************************/
5216 static int
5217 ips_reset_copperhead_memio(ips_ha_t * ha)
5218 {
5219 int reset_counter;
5220
5221 METHOD_TRACE("ips_reset_copperhead_memio", 1);
5222
5223 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d",
5224 ips_name, ha->host_num, ha->mem_addr, ha->irq);
5225
5226 reset_counter = 0;
5227
5228 while (reset_counter < 2) {
5229 reset_counter++;
5230
5231 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5232
5233 /* Delay for 1 Second */
5234 MDELAY(IPS_ONE_SEC);
5235
5236 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5237
5238 /* Delay for 1 Second */
5239 MDELAY(IPS_ONE_SEC);
5240
5241 if ((*ha->func.init) (ha))
5242 break;
5243 else if (reset_counter >= 2) {
5244
5245 return (0);
5246 }
5247 }
5248
5249 return (1);
5250 }
5251
5252 /****************************************************************************/
5253 /* */
5254 /* Routine Name: ips_reset_morpheus */
5255 /* */
5256 /* Routine Description: */
5257 /* */
5258 /* Reset the controller */
5259 /* */
5260 /****************************************************************************/
5261 static int
5262 ips_reset_morpheus(ips_ha_t * ha)
5263 {
5264 int reset_counter;
5265 uint8_t junk;
5266
5267 METHOD_TRACE("ips_reset_morpheus", 1);
5268
5269 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d",
5270 ips_name, ha->host_num, ha->mem_addr, ha->irq);
5271
5272 reset_counter = 0;
5273
5274 while (reset_counter < 2) {
5275 reset_counter++;
5276
5277 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5278
5279 /* Delay for 5 Seconds */
5280 MDELAY(5 * IPS_ONE_SEC);
5281
5282 /* Do a PCI config read to wait for adapter */
5283 pci_read_config_byte(ha->pcidev, 4, &junk);
5284
5285 if ((*ha->func.init) (ha))
5286 break;
5287 else if (reset_counter >= 2) {
5288
5289 return (0);
5290 }
5291 }
5292
5293 return (1);
5294 }
5295
5296 /****************************************************************************/
5297 /* */
5298 /* Routine Name: ips_statinit */
5299 /* */
5300 /* Routine Description: */
5301 /* */
5302 /* Initialize the status queues on the controller */
5303 /* */
5304 /****************************************************************************/
5305 static void
5306 ips_statinit(ips_ha_t * ha)
5307 {
5308 uint32_t phys_status_start;
5309
5310 METHOD_TRACE("ips_statinit", 1);
5311
5312 ha->adapt->p_status_start = ha->adapt->status;
5313 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5314 ha->adapt->p_status_tail = ha->adapt->status;
5315
5316 phys_status_start = ha->adapt->hw_status_start;
5317 outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQSR);
5318 outl(cpu_to_le32(phys_status_start + IPS_STATUS_Q_SIZE),
5319 ha->io_addr + IPS_REG_SQER);
5320 outl(cpu_to_le32(phys_status_start + IPS_STATUS_SIZE),
5321 ha->io_addr + IPS_REG_SQHR);
5322 outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQTR);
5323
5324 ha->adapt->hw_status_tail = phys_status_start;
5325 }
5326
5327 /****************************************************************************/
5328 /* */
5329 /* Routine Name: ips_statinit_memio */
5330 /* */
5331 /* Routine Description: */
5332 /* */
5333 /* Initialize the status queues on the controller */
5334 /* */
5335 /****************************************************************************/
5336 static void
5337 ips_statinit_memio(ips_ha_t * ha)
5338 {
5339 uint32_t phys_status_start;
5340
5341 METHOD_TRACE("ips_statinit_memio", 1);
5342
5343 ha->adapt->p_status_start = ha->adapt->status;
5344 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5345 ha->adapt->p_status_tail = ha->adapt->status;
5346
5347 phys_status_start = ha->adapt->hw_status_start;
5348 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5349 writel(phys_status_start + IPS_STATUS_Q_SIZE,
5350 ha->mem_ptr + IPS_REG_SQER);
5351 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5352 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5353
5354 ha->adapt->hw_status_tail = phys_status_start;
5355 }
5356
5357 /****************************************************************************/
5358 /* */
5359 /* Routine Name: ips_statupd_copperhead */
5360 /* */
5361 /* Routine Description: */
5362 /* */
5363 /* Remove an element from the status queue */
5364 /* */
5365 /****************************************************************************/
5366 static uint32_t
5367 ips_statupd_copperhead(ips_ha_t * ha)
5368 {
5369 METHOD_TRACE("ips_statupd_copperhead", 1);
5370
5371 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5372 ha->adapt->p_status_tail++;
5373 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5374 } else {
5375 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5376 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5377 }
5378
5379 outl(cpu_to_le32(ha->adapt->hw_status_tail),
5380 ha->io_addr + IPS_REG_SQTR);
5381
5382 return (ha->adapt->p_status_tail->value);
5383 }
5384
5385 /****************************************************************************/
5386 /* */
5387 /* Routine Name: ips_statupd_copperhead_memio */
5388 /* */
5389 /* Routine Description: */
5390 /* */
5391 /* Remove an element from the status queue */
5392 /* */
5393 /****************************************************************************/
5394 static uint32_t
5395 ips_statupd_copperhead_memio(ips_ha_t * ha)
5396 {
5397 METHOD_TRACE("ips_statupd_copperhead_memio", 1);
5398
5399 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5400 ha->adapt->p_status_tail++;
5401 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5402 } else {
5403 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5404 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5405 }
5406
5407 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5408
5409 return (ha->adapt->p_status_tail->value);
5410 }
5411
5412 /****************************************************************************/
5413 /* */
5414 /* Routine Name: ips_statupd_morpheus */
5415 /* */
5416 /* Routine Description: */
5417 /* */
5418 /* Remove an element from the status queue */
5419 /* */
5420 /****************************************************************************/
5421 static uint32_t
5422 ips_statupd_morpheus(ips_ha_t * ha)
5423 {
5424 uint32_t val;
5425
5426 METHOD_TRACE("ips_statupd_morpheus", 1);
5427
5428 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5429
5430 return (val);
5431 }
5432
5433 /****************************************************************************/
5434 /* */
5435 /* Routine Name: ips_issue_copperhead */
5436 /* */
5437 /* Routine Description: */
5438 /* */
5439 /* Send a command down to the controller */
5440 /* */
5441 /****************************************************************************/
5442 static int
5443 ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
5444 {
5445 uint32_t TimeOut;
5446 uint32_t val;
5447
5448 METHOD_TRACE("ips_issue_copperhead", 1);
5449
5450 if (scb->scsi_cmd) {
5451 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5452 ips_name,
5453 ha->host_num,
5454 scb->cdb[0],
5455 scb->cmd.basic_io.command_id,
5456 scb->bus, scb->target_id, scb->lun);
5457 } else {
5458 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d",
5459 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5460 }
5461
5462 TimeOut = 0;
5463
5464 while ((val =
5465 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5466 udelay(1000);
5467
5468 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5469 if (!(val & IPS_BIT_START_STOP))
5470 break;
5471
5472 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5473 "ips_issue val [0x%x].\n", val);
5474 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5475 "ips_issue semaphore chk timeout.\n");
5476
5477 return (IPS_FAILURE);
5478 } /* end if */
5479 } /* end while */
5480
5481 outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_CCSAR);
5482 outw(cpu_to_le32(IPS_BIT_START_CMD), ha->io_addr + IPS_REG_CCCR);
5483
5484 return (IPS_SUCCESS);
5485 }
5486
5487 /****************************************************************************/
5488 /* */
5489 /* Routine Name: ips_issue_copperhead_memio */
5490 /* */
5491 /* Routine Description: */
5492 /* */
5493 /* Send a command down to the controller */
5494 /* */
5495 /****************************************************************************/
5496 static int
5497 ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
5498 {
5499 uint32_t TimeOut;
5500 uint32_t val;
5501
5502 METHOD_TRACE("ips_issue_copperhead_memio", 1);
5503
5504 if (scb->scsi_cmd) {
5505 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5506 ips_name,
5507 ha->host_num,
5508 scb->cdb[0],
5509 scb->cmd.basic_io.command_id,
5510 scb->bus, scb->target_id, scb->lun);
5511 } else {
5512 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5513 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5514 }
5515
5516 TimeOut = 0;
5517
5518 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5519 udelay(1000);
5520
5521 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5522 if (!(val & IPS_BIT_START_STOP))
5523 break;
5524
5525 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5526 "ips_issue val [0x%x].\n", val);
5527 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5528 "ips_issue semaphore chk timeout.\n");
5529
5530 return (IPS_FAILURE);
5531 } /* end if */
5532 } /* end while */
5533
5534 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5535 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5536
5537 return (IPS_SUCCESS);
5538 }
5539
5540 /****************************************************************************/
5541 /* */
5542 /* Routine Name: ips_issue_i2o */
5543 /* */
5544 /* Routine Description: */
5545 /* */
5546 /* Send a command down to the controller */
5547 /* */
5548 /****************************************************************************/
5549 static int
5550 ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
5551 {
5552
5553 METHOD_TRACE("ips_issue_i2o", 1);
5554
5555 if (scb->scsi_cmd) {
5556 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5557 ips_name,
5558 ha->host_num,
5559 scb->cdb[0],
5560 scb->cmd.basic_io.command_id,
5561 scb->bus, scb->target_id, scb->lun);
5562 } else {
5563 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5564 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5565 }
5566
5567 outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_I2O_INMSGQ);
5568
5569 return (IPS_SUCCESS);
5570 }
5571
5572 /****************************************************************************/
5573 /* */
5574 /* Routine Name: ips_issue_i2o_memio */
5575 /* */
5576 /* Routine Description: */
5577 /* */
5578 /* Send a command down to the controller */
5579 /* */
5580 /****************************************************************************/
5581 static int
5582 ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
5583 {
5584
5585 METHOD_TRACE("ips_issue_i2o_memio", 1);
5586
5587 if (scb->scsi_cmd) {
5588 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5589 ips_name,
5590 ha->host_num,
5591 scb->cdb[0],
5592 scb->cmd.basic_io.command_id,
5593 scb->bus, scb->target_id, scb->lun);
5594 } else {
5595 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5596 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5597 }
5598
5599 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5600
5601 return (IPS_SUCCESS);
5602 }
5603
5604 /****************************************************************************/
5605 /* */
5606 /* Routine Name: ips_isintr_copperhead */
5607 /* */
5608 /* Routine Description: */
5609 /* */
5610 /* Test to see if an interrupt is for us */
5611 /* */
5612 /****************************************************************************/
5613 static int
5614 ips_isintr_copperhead(ips_ha_t * ha)
5615 {
5616 uint8_t Isr;
5617
5618 METHOD_TRACE("ips_isintr_copperhead", 2);
5619
5620 Isr = inb(ha->io_addr + IPS_REG_HISR);
5621
5622 if (Isr == 0xFF)
5623 /* ?!?! Nothing really there */
5624 return (0);
5625
5626 if (Isr & IPS_BIT_SCE)
5627 return (1);
5628 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5629 /* status queue overflow or GHI */
5630 /* just clear the interrupt */
5631 outb(Isr, ha->io_addr + IPS_REG_HISR);
5632 }
5633
5634 return (0);
5635 }
5636
5637 /****************************************************************************/
5638 /* */
5639 /* Routine Name: ips_isintr_copperhead_memio */
5640 /* */
5641 /* Routine Description: */
5642 /* */
5643 /* Test to see if an interrupt is for us */
5644 /* */
5645 /****************************************************************************/
5646 static int
5647 ips_isintr_copperhead_memio(ips_ha_t * ha)
5648 {
5649 uint8_t Isr;
5650
5651 METHOD_TRACE("ips_isintr_memio", 2);
5652
5653 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5654
5655 if (Isr == 0xFF)
5656 /* ?!?! Nothing really there */
5657 return (0);
5658
5659 if (Isr & IPS_BIT_SCE)
5660 return (1);
5661 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5662 /* status queue overflow or GHI */
5663 /* just clear the interrupt */
5664 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5665 }
5666
5667 return (0);
5668 }
5669
5670 /****************************************************************************/
5671 /* */
5672 /* Routine Name: ips_isintr_morpheus */
5673 /* */
5674 /* Routine Description: */
5675 /* */
5676 /* Test to see if an interrupt is for us */
5677 /* */
5678 /****************************************************************************/
5679 static int
5680 ips_isintr_morpheus(ips_ha_t * ha)
5681 {
5682 uint32_t Isr;
5683
5684 METHOD_TRACE("ips_isintr_morpheus", 2);
5685
5686 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5687
5688 if (Isr & IPS_BIT_I2O_OPQI)
5689 return (1);
5690 else
5691 return (0);
5692 }
5693
5694 /****************************************************************************/
5695 /* */
5696 /* Routine Name: ips_wait */
5697 /* */
5698 /* Routine Description: */
5699 /* */
5700 /* Wait for a command to complete */
5701 /* */
5702 /****************************************************************************/
5703 static int
5704 ips_wait(ips_ha_t * ha, int time, int intr)
5705 {
5706 int ret;
5707 int done;
5708
5709 METHOD_TRACE("ips_wait", 1);
5710
5711 ret = IPS_FAILURE;
5712 done = FALSE;
5713
5714 time *= IPS_ONE_SEC; /* convert seconds */
5715
5716 while ((time > 0) && (!done)) {
5717 if (intr == IPS_INTR_ON) {
5718 if (ha->waitflag == FALSE) {
5719 ret = IPS_SUCCESS;
5720 done = TRUE;
5721 break;
5722 }
5723 } else if (intr == IPS_INTR_IORL) {
5724 if (ha->waitflag == FALSE) {
5725 /*
5726 * controller generated an interrupt to
5727 * acknowledge completion of the command
5728 * and ips_intr() has serviced the interrupt.
5729 */
5730 ret = IPS_SUCCESS;
5731 done = TRUE;
5732 break;
5733 }
5734
5735 /*
5736 * NOTE: we already have the io_request_lock so
5737 * even if we get an interrupt it won't get serviced
5738 * until after we finish.
5739 */
5740
5741 (*ha->func.intr) (ha);
5742 }
5743
5744 /* This looks like a very evil loop, but it only does this during start-up */
5745 udelay(1000);
5746 time--;
5747 }
5748
5749 return (ret);
5750 }
5751
5752 /****************************************************************************/
5753 /* */
5754 /* Routine Name: ips_write_driver_status */
5755 /* */
5756 /* Routine Description: */
5757 /* */
5758 /* Write OS/Driver version to Page 5 of the nvram on the controller */
5759 /* */
5760 /****************************************************************************/
5761 static int
5762 ips_write_driver_status(ips_ha_t * ha, int intr)
5763 {
5764 METHOD_TRACE("ips_write_driver_status", 1);
5765
5766 if (!ips_readwrite_page5(ha, FALSE, intr)) {
5767 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5768 "unable to read NVRAM page 5.\n");
5769
5770 return (0);
5771 }
5772
5773 /* check to make sure the page has a valid */
5774 /* signature */
5775 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
5776 DEBUG_VAR(1,
5777 "(%s%d) NVRAM page 5 has an invalid signature: %X.",
5778 ips_name, ha->host_num, ha->nvram->signature);
5779 ha->nvram->signature = IPS_NVRAM_P5_SIG;
5780 }
5781
5782 DEBUG_VAR(2,
5783 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.",
5784 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
5785 ha->nvram->adapter_slot, ha->nvram->bios_high[0],
5786 ha->nvram->bios_high[1], ha->nvram->bios_high[2],
5787 ha->nvram->bios_high[3], ha->nvram->bios_low[0],
5788 ha->nvram->bios_low[1], ha->nvram->bios_low[2],
5789 ha->nvram->bios_low[3]);
5790
5791 ips_get_bios_version(ha, intr);
5792
5793 /* change values (as needed) */
5794 ha->nvram->operating_system = IPS_OS_LINUX;
5795 ha->nvram->adapter_type = ha->ad_type;
5796 strncpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
5797 strncpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
5798 strncpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
5799 strncpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
5800
5801 ips_version_check(ha, intr); /* Check BIOS/FW/Driver Versions */
5802
5803 /* now update the page */
5804 if (!ips_readwrite_page5(ha, TRUE, intr)) {
5805 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5806 "unable to write NVRAM page 5.\n");
5807
5808 return (0);
5809 }
5810
5811 /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */
5812 ha->slot_num = ha->nvram->adapter_slot;
5813
5814 return (1);
5815 }
5816
5817 /****************************************************************************/
5818 /* */
5819 /* Routine Name: ips_read_adapter_status */
5820 /* */
5821 /* Routine Description: */
5822 /* */
5823 /* Do an Inquiry command to the adapter */
5824 /* */
5825 /****************************************************************************/
5826 static int
5827 ips_read_adapter_status(ips_ha_t * ha, int intr)
5828 {
5829 ips_scb_t *scb;
5830 int ret;
5831
5832 METHOD_TRACE("ips_read_adapter_status", 1);
5833
5834 scb = &ha->scbs[ha->max_cmds - 1];
5835
5836 ips_init_scb(ha, scb);
5837
5838 scb->timeout = ips_cmd_timeout;
5839 scb->cdb[0] = IPS_CMD_ENQUIRY;
5840
5841 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
5842 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5843 scb->cmd.basic_io.sg_count = 0;
5844 scb->cmd.basic_io.lba = 0;
5845 scb->cmd.basic_io.sector_count = 0;
5846 scb->cmd.basic_io.log_drv = 0;
5847 scb->data_len = sizeof (*ha->enq);
5848 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
5849
5850 /* send command */
5851 if (((ret =
5852 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5853 || (ret == IPS_SUCCESS_IMM)
5854 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5855 return (0);
5856
5857 return (1);
5858 }
5859
5860 /****************************************************************************/
5861 /* */
5862 /* Routine Name: ips_read_subsystem_parameters */
5863 /* */
5864 /* Routine Description: */
5865 /* */
5866 /* Read subsystem parameters from the adapter */
5867 /* */
5868 /****************************************************************************/
5869 static int
5870 ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
5871 {
5872 ips_scb_t *scb;
5873 int ret;
5874
5875 METHOD_TRACE("ips_read_subsystem_parameters", 1);
5876
5877 scb = &ha->scbs[ha->max_cmds - 1];
5878
5879 ips_init_scb(ha, scb);
5880
5881 scb->timeout = ips_cmd_timeout;
5882 scb->cdb[0] = IPS_CMD_GET_SUBSYS;
5883
5884 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS;
5885 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5886 scb->cmd.basic_io.sg_count = 0;
5887 scb->cmd.basic_io.lba = 0;
5888 scb->cmd.basic_io.sector_count = 0;
5889 scb->cmd.basic_io.log_drv = 0;
5890 scb->data_len = sizeof (*ha->subsys);
5891 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5892
5893 /* send command */
5894 if (((ret =
5895 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5896 || (ret == IPS_SUCCESS_IMM)
5897 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5898 return (0);
5899
5900 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
5901 return (1);
5902 }
5903
5904 /****************************************************************************/
5905 /* */
5906 /* Routine Name: ips_read_config */
5907 /* */
5908 /* Routine Description: */
5909 /* */
5910 /* Read the configuration on the adapter */
5911 /* */
5912 /****************************************************************************/
5913 static int
5914 ips_read_config(ips_ha_t * ha, int intr)
5915 {
5916 ips_scb_t *scb;
5917 int i;
5918 int ret;
5919
5920 METHOD_TRACE("ips_read_config", 1);
5921
5922 /* set defaults for initiator IDs */
5923 for (i = 0; i < 4; i++)
5924 ha->conf->init_id[i] = 7;
5925
5926 scb = &ha->scbs[ha->max_cmds - 1];
5927
5928 ips_init_scb(ha, scb);
5929
5930 scb->timeout = ips_cmd_timeout;
5931 scb->cdb[0] = IPS_CMD_READ_CONF;
5932
5933 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF;
5934 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5935 scb->data_len = sizeof (*ha->conf);
5936 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5937
5938 /* send command */
5939 if (((ret =
5940 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5941 || (ret == IPS_SUCCESS_IMM)
5942 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5943
5944 memset(ha->conf, 0, sizeof (IPS_CONF));
5945
5946 /* reset initiator IDs */
5947 for (i = 0; i < 4; i++)
5948 ha->conf->init_id[i] = 7;
5949
5950 /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */
5951 if ((scb->basic_status & IPS_GSC_STATUS_MASK) ==
5952 IPS_CMD_CMPLT_WERROR)
5953 return (1);
5954
5955 return (0);
5956 }
5957
5958 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
5959 return (1);
5960 }
5961
5962 /****************************************************************************/
5963 /* */
5964 /* Routine Name: ips_readwrite_page5 */
5965 /* */
5966 /* Routine Description: */
5967 /* */
5968 /* Read nvram page 5 from the adapter */
5969 /* */
5970 /****************************************************************************/
5971 static int
5972 ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
5973 {
5974 ips_scb_t *scb;
5975 int ret;
5976
5977 METHOD_TRACE("ips_readwrite_page5", 1);
5978
5979 scb = &ha->scbs[ha->max_cmds - 1];
5980
5981 ips_init_scb(ha, scb);
5982
5983 scb->timeout = ips_cmd_timeout;
5984 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE;
5985
5986 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE;
5987 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
5988 scb->cmd.nvram.page = 5;
5989 scb->cmd.nvram.write = write;
5990 scb->cmd.nvram.reserved = 0;
5991 scb->cmd.nvram.reserved2 = 0;
5992 scb->data_len = sizeof (*ha->nvram);
5993 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
5994 if (write)
5995 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
5996
5997 /* issue the command */
5998 if (((ret =
5999 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
6000 || (ret == IPS_SUCCESS_IMM)
6001 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
6002
6003 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
6004
6005 return (0);
6006 }
6007 if (!write)
6008 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
6009 return (1);
6010 }
6011
6012 /****************************************************************************/
6013 /* */
6014 /* Routine Name: ips_clear_adapter */
6015 /* */
6016 /* Routine Description: */
6017 /* */
6018 /* Clear the stripe lock tables */
6019 /* */
6020 /****************************************************************************/
6021 static int
6022 ips_clear_adapter(ips_ha_t * ha, int intr)
6023 {
6024 ips_scb_t *scb;
6025 int ret;
6026
6027 METHOD_TRACE("ips_clear_adapter", 1);
6028
6029 scb = &ha->scbs[ha->max_cmds - 1];
6030
6031 ips_init_scb(ha, scb);
6032
6033 scb->timeout = ips_reset_timeout;
6034 scb->cdb[0] = IPS_CMD_CONFIG_SYNC;
6035
6036 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC;
6037 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
6038 scb->cmd.config_sync.channel = 0;
6039 scb->cmd.config_sync.source_target = IPS_POCL;
6040 scb->cmd.config_sync.reserved = 0;
6041 scb->cmd.config_sync.reserved2 = 0;
6042 scb->cmd.config_sync.reserved3 = 0;
6043
6044 /* issue command */
6045 if (((ret =
6046 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE)
6047 || (ret == IPS_SUCCESS_IMM)
6048 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
6049 return (0);
6050
6051 /* send unlock stripe command */
6052 ips_init_scb(ha, scb);
6053
6054 scb->cdb[0] = IPS_CMD_ERROR_TABLE;
6055 scb->timeout = ips_reset_timeout;
6056
6057 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE;
6058 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
6059 scb->cmd.unlock_stripe.log_drv = 0;
6060 scb->cmd.unlock_stripe.control = IPS_CSL;
6061 scb->cmd.unlock_stripe.reserved = 0;
6062 scb->cmd.unlock_stripe.reserved2 = 0;
6063 scb->cmd.unlock_stripe.reserved3 = 0;
6064
6065 /* issue command */
6066 if (((ret =
6067 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
6068 || (ret == IPS_SUCCESS_IMM)
6069 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
6070 return (0);
6071
6072 return (1);
6073 }
6074
6075 /****************************************************************************/
6076 /* */
6077 /* Routine Name: ips_ffdc_reset */
6078 /* */
6079 /* Routine Description: */
6080 /* */
6081 /* FFDC: write reset info */
6082 /* */
6083 /****************************************************************************/
6084 static void
6085 ips_ffdc_reset(ips_ha_t * ha, int intr)
6086 {
6087 ips_scb_t *scb;
6088
6089 METHOD_TRACE("ips_ffdc_reset", 1);
6090
6091 scb = &ha->scbs[ha->max_cmds - 1];
6092
6093 ips_init_scb(ha, scb);
6094
6095 scb->timeout = ips_cmd_timeout;
6096 scb->cdb[0] = IPS_CMD_FFDC;
6097 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
6098 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
6099 scb->cmd.ffdc.reset_count = ha->reset_count;
6100 scb->cmd.ffdc.reset_type = 0x80;
6101
6102 /* convert time to what the card wants */
6103 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
6104
6105 /* issue command */
6106 ips_send_wait(ha, scb, ips_cmd_timeout, intr);
6107 }
6108
6109 /****************************************************************************/
6110 /* */
6111 /* Routine Name: ips_ffdc_time */
6112 /* */
6113 /* Routine Description: */
6114 /* */
6115 /* FFDC: write time info */
6116 /* */
6117 /****************************************************************************/
6118 static void
6119 ips_ffdc_time(ips_ha_t * ha)
6120 {
6121 ips_scb_t *scb;
6122
6123 METHOD_TRACE("ips_ffdc_time", 1);
6124
6125 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
6126
6127 scb = &ha->scbs[ha->max_cmds - 1];
6128
6129 ips_init_scb(ha, scb);
6130
6131 scb->timeout = ips_cmd_timeout;
6132 scb->cdb[0] = IPS_CMD_FFDC;
6133 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
6134 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
6135 scb->cmd.ffdc.reset_count = 0;
6136 scb->cmd.ffdc.reset_type = 0;
6137
6138 /* convert time to what the card wants */
6139 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
6140
6141 /* issue command */
6142 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
6143 }
6144
6145 /****************************************************************************/
6146 /* */
6147 /* Routine Name: ips_fix_ffdc_time */
6148 /* */
6149 /* Routine Description: */
6150 /* Adjust time_t to what the card wants */
6151 /* */
6152 /****************************************************************************/
6153 static void
6154 ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time_t current_time)
6155 {
6156 long days;
6157 long rem;
6158 int i;
6159 int year;
6160 int yleap;
6161 int year_lengths[2] = { IPS_DAYS_NORMAL_YEAR, IPS_DAYS_LEAP_YEAR };
6162 int month_lengths[12][2] = { {31, 31},
6163 {28, 29},
6164 {31, 31},
6165 {30, 30},
6166 {31, 31},
6167 {30, 30},
6168 {31, 31},
6169 {31, 31},
6170 {30, 30},
6171 {31, 31},
6172 {30, 30},
6173 {31, 31}
6174 };
6175
6176 METHOD_TRACE("ips_fix_ffdc_time", 1);
6177
6178 days = current_time / IPS_SECS_DAY;
6179 rem = current_time % IPS_SECS_DAY;
6180
6181 scb->cmd.ffdc.hour = (rem / IPS_SECS_HOUR);
6182 rem = rem % IPS_SECS_HOUR;
6183 scb->cmd.ffdc.minute = (rem / IPS_SECS_MIN);
6184 scb->cmd.ffdc.second = (rem % IPS_SECS_MIN);
6185
6186 year = IPS_EPOCH_YEAR;
6187 while (days < 0 || days >= year_lengths[yleap = IPS_IS_LEAP_YEAR(year)]) {
6188 int newy;
6189
6190 newy = year + (days / IPS_DAYS_NORMAL_YEAR);
6191 if (days < 0)
6192 --newy;
6193 days -= (newy - year) * IPS_DAYS_NORMAL_YEAR +
6194 IPS_NUM_LEAP_YEARS_THROUGH(newy - 1) -
6195 IPS_NUM_LEAP_YEARS_THROUGH(year - 1);
6196 year = newy;
6197 }
6198
6199 scb->cmd.ffdc.yearH = year / 100;
6200 scb->cmd.ffdc.yearL = year % 100;
6201
6202 for (i = 0; days >= month_lengths[i][yleap]; ++i)
6203 days -= month_lengths[i][yleap];
6204
6205 scb->cmd.ffdc.month = i + 1;
6206 scb->cmd.ffdc.day = days + 1;
6207 }
6208
6209 /****************************************************************************
6210 * BIOS Flash Routines *
6211 ****************************************************************************/
6212
6213 /****************************************************************************/
6214 /* */
6215 /* Routine Name: ips_erase_bios */
6216 /* */
6217 /* Routine Description: */
6218 /* Erase the BIOS on the adapter */
6219 /* */
6220 /****************************************************************************/
6221 static int
6222 ips_erase_bios(ips_ha_t * ha)
6223 {
6224 int timeout;
6225 uint8_t status = 0;
6226
6227 METHOD_TRACE("ips_erase_bios", 1);
6228
6229 status = 0;
6230
6231 /* Clear the status register */
6232 outl(0, ha->io_addr + IPS_REG_FLAP);
6233 if (ha->revision_id == IPS_REVID_TROMBONE64)
6234 udelay(25); /* 25 us */
6235
6236 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6237 if (ha->revision_id == IPS_REVID_TROMBONE64)
6238 udelay(25); /* 25 us */
6239
6240 /* Erase Setup */
6241 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6242 if (ha->revision_id == IPS_REVID_TROMBONE64)
6243 udelay(25); /* 25 us */
6244
6245 /* Erase Confirm */
6246 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6247 if (ha->revision_id == IPS_REVID_TROMBONE64)
6248 udelay(25); /* 25 us */
6249
6250 /* Erase Status */
6251 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6252 if (ha->revision_id == IPS_REVID_TROMBONE64)
6253 udelay(25); /* 25 us */
6254
6255 timeout = 80000; /* 80 seconds */
6256
6257 while (timeout > 0) {
6258 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6259 outl(0, ha->io_addr + IPS_REG_FLAP);
6260 udelay(25); /* 25 us */
6261 }
6262
6263 status = inb(ha->io_addr + IPS_REG_FLDP);
6264
6265 if (status & 0x80)
6266 break;
6267
6268 MDELAY(1);
6269 timeout--;
6270 }
6271
6272 /* check for timeout */
6273 if (timeout <= 0) {
6274 /* timeout */
6275
6276 /* try to suspend the erase */
6277 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6278 if (ha->revision_id == IPS_REVID_TROMBONE64)
6279 udelay(25); /* 25 us */
6280
6281 /* wait for 10 seconds */
6282 timeout = 10000;
6283 while (timeout > 0) {
6284 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6285 outl(0, ha->io_addr + IPS_REG_FLAP);
6286 udelay(25); /* 25 us */
6287 }
6288
6289 status = inb(ha->io_addr + IPS_REG_FLDP);
6290
6291 if (status & 0xC0)
6292 break;
6293
6294 MDELAY(1);
6295 timeout--;
6296 }
6297
6298 return (1);
6299 }
6300
6301 /* check for valid VPP */
6302 if (status & 0x08)
6303 /* VPP failure */
6304 return (1);
6305
6306 /* check for succesful flash */
6307 if (status & 0x30)
6308 /* sequence error */
6309 return (1);
6310
6311 /* Otherwise, we were successful */
6312 /* clear status */
6313 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6314 if (ha->revision_id == IPS_REVID_TROMBONE64)
6315 udelay(25); /* 25 us */
6316
6317 /* enable reads */
6318 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6319 if (ha->revision_id == IPS_REVID_TROMBONE64)
6320 udelay(25); /* 25 us */
6321
6322 return (0);
6323 }
6324
6325 /****************************************************************************/
6326 /* */
6327 /* Routine Name: ips_erase_bios_memio */
6328 /* */
6329 /* Routine Description: */
6330 /* Erase the BIOS on the adapter */
6331 /* */
6332 /****************************************************************************/
6333 static int
6334 ips_erase_bios_memio(ips_ha_t * ha)
6335 {
6336 int timeout;
6337 uint8_t status;
6338
6339 METHOD_TRACE("ips_erase_bios_memio", 1);
6340
6341 status = 0;
6342
6343 /* Clear the status register */
6344 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6345 if (ha->revision_id == IPS_REVID_TROMBONE64)
6346 udelay(25); /* 25 us */
6347
6348 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6349 if (ha->revision_id == IPS_REVID_TROMBONE64)
6350 udelay(25); /* 25 us */
6351
6352 /* Erase Setup */
6353 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6354 if (ha->revision_id == IPS_REVID_TROMBONE64)
6355 udelay(25); /* 25 us */
6356
6357 /* Erase Confirm */
6358 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6359 if (ha->revision_id == IPS_REVID_TROMBONE64)
6360 udelay(25); /* 25 us */
6361
6362 /* Erase Status */
6363 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6364 if (ha->revision_id == IPS_REVID_TROMBONE64)
6365 udelay(25); /* 25 us */
6366
6367 timeout = 80000; /* 80 seconds */
6368
6369 while (timeout > 0) {
6370 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6371 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6372 udelay(25); /* 25 us */
6373 }
6374
6375 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6376
6377 if (status & 0x80)
6378 break;
6379
6380 MDELAY(1);
6381 timeout--;
6382 }
6383
6384 /* check for timeout */
6385 if (timeout <= 0) {
6386 /* timeout */
6387
6388 /* try to suspend the erase */
6389 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6390 if (ha->revision_id == IPS_REVID_TROMBONE64)
6391 udelay(25); /* 25 us */
6392
6393 /* wait for 10 seconds */
6394 timeout = 10000;
6395 while (timeout > 0) {
6396 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6397 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6398 udelay(25); /* 25 us */
6399 }
6400
6401 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6402
6403 if (status & 0xC0)
6404 break;
6405
6406 MDELAY(1);
6407 timeout--;
6408 }
6409
6410 return (1);
6411 }
6412
6413 /* check for valid VPP */
6414 if (status & 0x08)
6415 /* VPP failure */
6416 return (1);
6417
6418 /* check for succesful flash */
6419 if (status & 0x30)
6420 /* sequence error */
6421 return (1);
6422
6423 /* Otherwise, we were successful */
6424 /* clear status */
6425 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6426 if (ha->revision_id == IPS_REVID_TROMBONE64)
6427 udelay(25); /* 25 us */
6428
6429 /* enable reads */
6430 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6431 if (ha->revision_id == IPS_REVID_TROMBONE64)
6432 udelay(25); /* 25 us */
6433
6434 return (0);
6435 }
6436
6437 /****************************************************************************/
6438 /* */
6439 /* Routine Name: ips_program_bios */
6440 /* */
6441 /* Routine Description: */
6442 /* Program the BIOS on the adapter */
6443 /* */
6444 /****************************************************************************/
6445 static int
6446 ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6447 uint32_t offset)
6448 {
6449 int i;
6450 int timeout;
6451 uint8_t status = 0;
6452
6453 METHOD_TRACE("ips_program_bios", 1);
6454
6455 status = 0;
6456
6457 for (i = 0; i < buffersize; i++) {
6458 /* write a byte */
6459 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP);
6460 if (ha->revision_id == IPS_REVID_TROMBONE64)
6461 udelay(25); /* 25 us */
6462
6463 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6464 if (ha->revision_id == IPS_REVID_TROMBONE64)
6465 udelay(25); /* 25 us */
6466
6467 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6468 if (ha->revision_id == IPS_REVID_TROMBONE64)
6469 udelay(25); /* 25 us */
6470
6471 /* wait up to one second */
6472 timeout = 1000;
6473 while (timeout > 0) {
6474 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6475 outl(0, ha->io_addr + IPS_REG_FLAP);
6476 udelay(25); /* 25 us */
6477 }
6478
6479 status = inb(ha->io_addr + IPS_REG_FLDP);
6480
6481 if (status & 0x80)
6482 break;
6483
6484 MDELAY(1);
6485 timeout--;
6486 }
6487
6488 if (timeout == 0) {
6489 /* timeout error */
6490 outl(0, ha->io_addr + IPS_REG_FLAP);
6491 if (ha->revision_id == IPS_REVID_TROMBONE64)
6492 udelay(25); /* 25 us */
6493
6494 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6495 if (ha->revision_id == IPS_REVID_TROMBONE64)
6496 udelay(25); /* 25 us */
6497
6498 return (1);
6499 }
6500
6501 /* check the status */
6502 if (status & 0x18) {
6503 /* programming error */
6504 outl(0, ha->io_addr + IPS_REG_FLAP);
6505 if (ha->revision_id == IPS_REVID_TROMBONE64)
6506 udelay(25); /* 25 us */
6507
6508 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6509 if (ha->revision_id == IPS_REVID_TROMBONE64)
6510 udelay(25); /* 25 us */
6511
6512 return (1);
6513 }
6514 } /* end for */
6515
6516 /* Enable reading */
6517 outl(0, ha->io_addr + IPS_REG_FLAP);
6518 if (ha->revision_id == IPS_REVID_TROMBONE64)
6519 udelay(25); /* 25 us */
6520
6521 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6522 if (ha->revision_id == IPS_REVID_TROMBONE64)
6523 udelay(25); /* 25 us */
6524
6525 return (0);
6526 }
6527
6528 /****************************************************************************/
6529 /* */
6530 /* Routine Name: ips_program_bios_memio */
6531 /* */
6532 /* Routine Description: */
6533 /* Program the BIOS on the adapter */
6534 /* */
6535 /****************************************************************************/
6536 static int
6537 ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6538 uint32_t offset)
6539 {
6540 int i;
6541 int timeout;
6542 uint8_t status = 0;
6543
6544 METHOD_TRACE("ips_program_bios_memio", 1);
6545
6546 status = 0;
6547
6548 for (i = 0; i < buffersize; i++) {
6549 /* write a byte */
6550 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6551 if (ha->revision_id == IPS_REVID_TROMBONE64)
6552 udelay(25); /* 25 us */
6553
6554 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6555 if (ha->revision_id == IPS_REVID_TROMBONE64)
6556 udelay(25); /* 25 us */
6557
6558 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6559 if (ha->revision_id == IPS_REVID_TROMBONE64)
6560 udelay(25); /* 25 us */
6561
6562 /* wait up to one second */
6563 timeout = 1000;
6564 while (timeout > 0) {
6565 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6566 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6567 udelay(25); /* 25 us */
6568 }
6569
6570 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6571
6572 if (status & 0x80)
6573 break;
6574
6575 MDELAY(1);
6576 timeout--;
6577 }
6578
6579 if (timeout == 0) {
6580 /* timeout error */
6581 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6582 if (ha->revision_id == IPS_REVID_TROMBONE64)
6583 udelay(25); /* 25 us */
6584
6585 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6586 if (ha->revision_id == IPS_REVID_TROMBONE64)
6587 udelay(25); /* 25 us */
6588
6589 return (1);
6590 }
6591
6592 /* check the status */
6593 if (status & 0x18) {
6594 /* programming error */
6595 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6596 if (ha->revision_id == IPS_REVID_TROMBONE64)
6597 udelay(25); /* 25 us */
6598
6599 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6600 if (ha->revision_id == IPS_REVID_TROMBONE64)
6601 udelay(25); /* 25 us */
6602
6603 return (1);
6604 }
6605 } /* end for */
6606
6607 /* Enable reading */
6608 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6609 if (ha->revision_id == IPS_REVID_TROMBONE64)
6610 udelay(25); /* 25 us */
6611
6612 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6613 if (ha->revision_id == IPS_REVID_TROMBONE64)
6614 udelay(25); /* 25 us */
6615
6616 return (0);
6617 }
6618
6619 /****************************************************************************/
6620 /* */
6621 /* Routine Name: ips_verify_bios */
6622 /* */
6623 /* Routine Description: */
6624 /* Verify the BIOS on the adapter */
6625 /* */
6626 /****************************************************************************/
6627 static int
6628 ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6629 uint32_t offset)
6630 {
6631 uint8_t checksum;
6632 int i;
6633
6634 METHOD_TRACE("ips_verify_bios", 1);
6635
6636 /* test 1st byte */
6637 outl(0, ha->io_addr + IPS_REG_FLAP);
6638 if (ha->revision_id == IPS_REVID_TROMBONE64)
6639 udelay(25); /* 25 us */
6640
6641 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6642 return (1);
6643
6644 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP);
6645 if (ha->revision_id == IPS_REVID_TROMBONE64)
6646 udelay(25); /* 25 us */
6647 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6648 return (1);
6649
6650 checksum = 0xff;
6651 for (i = 2; i < buffersize; i++) {
6652
6653 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP);
6654 if (ha->revision_id == IPS_REVID_TROMBONE64)
6655 udelay(25); /* 25 us */
6656
6657 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6658 }
6659
6660 if (checksum != 0)
6661 /* failure */
6662 return (1);
6663 else
6664 /* success */
6665 return (0);
6666 }
6667
6668 /****************************************************************************/
6669 /* */
6670 /* Routine Name: ips_verify_bios_memio */
6671 /* */
6672 /* Routine Description: */
6673 /* Verify the BIOS on the adapter */
6674 /* */
6675 /****************************************************************************/
6676 static int
6677 ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6678 uint32_t offset)
6679 {
6680 uint8_t checksum;
6681 int i;
6682
6683 METHOD_TRACE("ips_verify_bios_memio", 1);
6684
6685 /* test 1st byte */
6686 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6687 if (ha->revision_id == IPS_REVID_TROMBONE64)
6688 udelay(25); /* 25 us */
6689
6690 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6691 return (1);
6692
6693 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6694 if (ha->revision_id == IPS_REVID_TROMBONE64)
6695 udelay(25); /* 25 us */
6696 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6697 return (1);
6698
6699 checksum = 0xff;
6700 for (i = 2; i < buffersize; i++) {
6701
6702 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6703 if (ha->revision_id == IPS_REVID_TROMBONE64)
6704 udelay(25); /* 25 us */
6705
6706 checksum =
6707 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6708 }
6709
6710 if (checksum != 0)
6711 /* failure */
6712 return (1);
6713 else
6714 /* success */
6715 return (0);
6716 }
6717
6718 /*---------------------------------------------------------------------------*/
6719 /* Routine Name: ips_version_check */
6720 /* */
6721 /* Dependencies: */
6722 /* Assumes that ips_read_adapter_status() is called first filling in */
6723 /* the data for SubSystem Parameters. */
6724 /* Called from ips_write_driver_status() so it also assumes NVRAM Page 5 */
6725 /* Data is available. */
6726 /* */
6727 /*---------------------------------------------------------------------------*/
6728 static void
6729 ips_version_check(ips_ha_t * ha, int intr)
6730 {
6731 IPS_VERSION_DATA *VersionInfo;
6732 uint8_t FirmwareVersion[IPS_COMPAT_ID_LENGTH + 1];
6733 uint8_t BiosVersion[IPS_COMPAT_ID_LENGTH + 1];
6734 int MatchError;
6735 int rc;
6736 char BiosString[10];
6737 char FirmwareString[10];
6738
6739 METHOD_TRACE("ips_version_check", 1);
6740
6741 VersionInfo = ( IPS_VERSION_DATA * ) ha->ioctl_data;
6742
6743 memset(FirmwareVersion, 0, IPS_COMPAT_ID_LENGTH + 1);
6744 memset(BiosVersion, 0, IPS_COMPAT_ID_LENGTH + 1);
6745
6746 /* Get the Compatible BIOS Version from NVRAM Page 5 */
6747 memcpy(BiosVersion, ha->nvram->BiosCompatibilityID,
6748 IPS_COMPAT_ID_LENGTH);
6749
6750 rc = IPS_FAILURE;
6751 if (ha->subsys->param[4] & IPS_GET_VERSION_SUPPORT) { /* If Versioning is Supported */
6752 /* Get the Version Info with a Get Version Command */
6753 memset( VersionInfo, 0, sizeof (IPS_VERSION_DATA));
6754 rc = ips_get_version_info(ha, ha->ioctl_busaddr, intr);
6755 if (rc == IPS_SUCCESS)
6756 memcpy(FirmwareVersion, VersionInfo->compatibilityId,
6757 IPS_COMPAT_ID_LENGTH);
6758 }
6759
6760 if (rc != IPS_SUCCESS) { /* If Data Not Obtainable from a GetVersion Command */
6761 /* Get the Firmware Version from Enquiry Data */
6762 memcpy(FirmwareVersion, ha->enq->CodeBlkVersion,
6763 IPS_COMPAT_ID_LENGTH);
6764 }
6765
6766 /* printk(KERN_WARNING "Adapter's BIOS Version = %s\n", BiosVersion); */
6767 /* printk(KERN_WARNING "BIOS Compatible Version = %s\n", IPS_COMPAT_BIOS); */
6768 /* printk(KERN_WARNING "Adapter's Firmware Version = %s\n", FirmwareVersion); */
6769 /* printk(KERN_WARNING "Firmware Compatible Version = %s \n", Compatable[ ha->nvram->adapter_type ]); */
6770
6771 MatchError = 0;
6772
6773 if (strncmp
6774 (FirmwareVersion, Compatable[ha->nvram->adapter_type],
6775 IPS_COMPAT_ID_LENGTH) != 0)
6776 MatchError = 1;
6777
6778 if (strncmp(BiosVersion, IPS_COMPAT_BIOS, IPS_COMPAT_ID_LENGTH) != 0)
6779 MatchError = 1;
6780
6781 ha->nvram->versioning = 1; /* Indicate the Driver Supports Versioning */
6782
6783 if (MatchError) {
6784 ha->nvram->version_mismatch = 1;
6785 if (ips_cd_boot == 0) {
6786 strncpy(&BiosString[0], ha->nvram->bios_high, 4);
6787 strncpy(&BiosString[4], ha->nvram->bios_low, 4);
6788 BiosString[8] = 0;
6789
6790 strncpy(&FirmwareString[0], ha->enq->CodeBlkVersion, 8);
6791 FirmwareString[8] = 0;
6792
6793 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6794 "Warning ! ! ! ServeRAID Version Mismatch\n");
6795 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6796 "Bios = %s, Firmware = %s, Device Driver = %s%s\n",
6797 BiosString, FirmwareString, IPS_VERSION_HIGH,
6798 IPS_VERSION_LOW);
6799 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6800 "These levels should match to avoid possible compatibility problems.\n");
6801 }
6802 } else {
6803 ha->nvram->version_mismatch = 0;
6804 }
6805
6806 return;
6807 }
6808
6809 /*---------------------------------------------------------------------------*/
6810 /* Routine Name: ips_get_version_info */
6811 /* */
6812 /* Routine Description: */
6813 /* Issue an internal GETVERSION Command */
6814 /* */
6815 /* Return Value: */
6816 /* 0 if Successful, else non-zero */
6817 /*---------------------------------------------------------------------------*/
6818 static int
6819 ips_get_version_info(ips_ha_t * ha, dma_addr_t Buffer, int intr)
6820 {
6821 ips_scb_t *scb;
6822 int rc;
6823
6824 METHOD_TRACE("ips_get_version_info", 1);
6825
6826 scb = &ha->scbs[ha->max_cmds - 1];
6827
6828 ips_init_scb(ha, scb);
6829
6830 scb->timeout = ips_cmd_timeout;
6831 scb->cdb[0] = IPS_CMD_GET_VERSION_INFO;
6832 scb->cmd.version_info.op_code = IPS_CMD_GET_VERSION_INFO;
6833 scb->cmd.version_info.command_id = IPS_COMMAND_ID(ha, scb);
6834 scb->cmd.version_info.reserved = 0;
6835 scb->cmd.version_info.count = sizeof (IPS_VERSION_DATA);
6836 scb->cmd.version_info.reserved2 = 0;
6837 scb->data_len = sizeof (IPS_VERSION_DATA);
6838 scb->data_busaddr = Buffer;
6839 scb->cmd.version_info.buffer_addr = Buffer;
6840 scb->flags = 0;
6841
6842 /* issue command */
6843 rc = ips_send_wait(ha, scb, ips_cmd_timeout, intr);
6844 return (rc);
6845 }
6846
6847 /****************************************************************************/
6848 /* */
6849 /* Routine Name: ips_abort_init */
6850 /* */
6851 /* Routine Description: */
6852 /* cleanup routine for a failed adapter initialization */
6853 /****************************************************************************/
6854 static int
6855 ips_abort_init(ips_ha_t * ha, int index)
6856 {
6857 ha->active = 0;
6858 ips_free(ha);
6859 ips_ha[index] = NULL;
6860 ips_sh[index] = NULL;
6861 return -1;
6862 }
6863
6864 /****************************************************************************/
6865 /* */
6866 /* Routine Name: ips_shift_controllers */
6867 /* */
6868 /* Routine Description: */
6869 /* helper function for ordering adapters */
6870 /****************************************************************************/
6871 static void
6872 ips_shift_controllers(int lowindex, int highindex)
6873 {
6874 ips_ha_t *ha_sav = ips_ha[highindex];
6875 struct Scsi_Host *sh_sav = ips_sh[highindex];
6876 int i;
6877
6878 for (i = highindex; i > lowindex; i--) {
6879 ips_ha[i] = ips_ha[i - 1];
6880 ips_sh[i] = ips_sh[i - 1];
6881 ips_ha[i]->host_num = i;
6882 }
6883 ha_sav->host_num = lowindex;
6884 ips_ha[lowindex] = ha_sav;
6885 ips_sh[lowindex] = sh_sav;
6886 }
6887
6888 /****************************************************************************/
6889 /* */
6890 /* Routine Name: ips_order_controllers */
6891 /* */
6892 /* Routine Description: */
6893 /* place controllers is the "proper" boot order */
6894 /****************************************************************************/
6895 static void
6896 ips_order_controllers(void)
6897 {
6898 int i, j, tmp, position = 0;
6899 IPS_NVRAM_P5 *nvram;
6900 if (!ips_ha[0])
6901 return;
6902 nvram = ips_ha[0]->nvram;
6903
6904 if (nvram->adapter_order[0]) {
6905 for (i = 1; i <= nvram->adapter_order[0]; i++) {
6906 for (j = position; j < ips_num_controllers; j++) {
6907 switch (ips_ha[j]->ad_type) {
6908 case IPS_ADTYPE_SERVERAID6M:
6909 case IPS_ADTYPE_SERVERAID7M:
6910 if (nvram->adapter_order[i] == 'M') {
6911 ips_shift_controllers(position,
6912 j);
6913 position++;
6914 }
6915 break;
6916 case IPS_ADTYPE_SERVERAID4L:
6917 case IPS_ADTYPE_SERVERAID4M:
6918 case IPS_ADTYPE_SERVERAID4MX:
6919 case IPS_ADTYPE_SERVERAID4LX:
6920 if (nvram->adapter_order[i] == 'N') {
6921 ips_shift_controllers(position,
6922 j);
6923 position++;
6924 }
6925 break;
6926 case IPS_ADTYPE_SERVERAID6I:
6927 case IPS_ADTYPE_SERVERAID5I2:
6928 case IPS_ADTYPE_SERVERAID5I1:
6929 case IPS_ADTYPE_SERVERAID7k:
6930 if (nvram->adapter_order[i] == 'S') {
6931 ips_shift_controllers(position,
6932 j);
6933 position++;
6934 }
6935 break;
6936 case IPS_ADTYPE_SERVERAID:
6937 case IPS_ADTYPE_SERVERAID2:
6938 case IPS_ADTYPE_NAVAJO:
6939 case IPS_ADTYPE_KIOWA:
6940 case IPS_ADTYPE_SERVERAID3L:
6941 case IPS_ADTYPE_SERVERAID3:
6942 case IPS_ADTYPE_SERVERAID4H:
6943 if (nvram->adapter_order[i] == 'A') {
6944 ips_shift_controllers(position,
6945 j);
6946 position++;
6947 }
6948 break;
6949 default:
6950 break;
6951 }
6952 }
6953 }
6954 /* if adapter_order[0], then ordering is complete */
6955 return;
6956 }
6957 /* old bios, use older ordering */
6958 tmp = 0;
6959 for (i = position; i < ips_num_controllers; i++) {
6960 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 ||
6961 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) {
6962 ips_shift_controllers(position, i);
6963 position++;
6964 tmp = 1;
6965 }
6966 }
6967 /* if there were no 5I cards, then don't do any extra ordering */
6968 if (!tmp)
6969 return;
6970 for (i = position; i < ips_num_controllers; i++) {
6971 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L ||
6972 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M ||
6973 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX ||
6974 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) {
6975 ips_shift_controllers(position, i);
6976 position++;
6977 }
6978 }
6979
6980 return;
6981 }
6982
6983 /****************************************************************************/
6984 /* */
6985 /* Routine Name: ips_register_scsi */
6986 /* */
6987 /* Routine Description: */
6988 /* perform any registration and setup with the scsi layer */
6989 /****************************************************************************/
6990 static int
6991 ips_register_scsi(int index)
6992 {
6993 struct Scsi_Host *sh;
6994 ips_ha_t *ha, *oldha = ips_ha[index];
6995 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t));
6996 if (!sh) {
6997 IPS_PRINTK(KERN_WARNING, oldha->pcidev,
6998 "Unable to register controller with SCSI subsystem\n");
6999 return -1;
7000 }
7001 ha = IPS_HA(sh);
7002 memcpy(ha, oldha, sizeof (ips_ha_t));
7003 free_irq(oldha->irq, oldha);
7004 /* Install the interrupt handler with the new ha */
7005 if (request_irq(ha->irq, do_ipsintr, SA_SHIRQ, ips_name, ha)) {
7006 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7007 "Unable to install interrupt handler\n");
7008 scsi_host_put(sh);
7009 return -1;
7010 }
7011
7012 kfree(oldha);
7013 ips_sh[index] = sh;
7014 ips_ha[index] = ha;
7015 IPS_SCSI_SET_DEVICE(sh, ha);
7016
7017 /* Store away needed values for later use */
7018 sh->io_port = ha->io_addr;
7019 sh->n_io_port = ha->io_addr ? 255 : 0;
7020 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
7021 sh->irq = ha->irq;
7022 sh->sg_tablesize = sh->hostt->sg_tablesize;
7023 sh->can_queue = sh->hostt->can_queue;
7024 sh->cmd_per_lun = sh->hostt->cmd_per_lun;
7025 sh->unchecked_isa_dma = sh->hostt->unchecked_isa_dma;
7026 sh->use_clustering = sh->hostt->use_clustering;
7027
7028 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,7)
7029 sh->max_sectors = 128;
7030 #endif
7031
7032 sh->max_id = ha->ntargets;
7033 sh->max_lun = ha->nlun;
7034 sh->max_channel = ha->nbus - 1;
7035 sh->can_queue = ha->max_cmds - 1;
7036
7037 IPS_ADD_HOST(sh, NULL);
7038 return 0;
7039 }
7040
7041 /*---------------------------------------------------------------------------*/
7042 /* Routine Name: ips_remove_device */
7043 /* */
7044 /* Routine Description: */
7045 /* Remove one Adapter ( Hot Plugging ) */
7046 /*---------------------------------------------------------------------------*/
7047 static void __devexit
7048 ips_remove_device(struct pci_dev *pci_dev)
7049 {
7050 int i;
7051 struct Scsi_Host *sh;
7052 ips_ha_t *ha;
7053
7054 for (i = 0; i < IPS_MAX_ADAPTERS; i++) {
7055 ha = ips_ha[i];
7056 if (ha) {
7057 if ((pci_dev->bus->number == ha->pcidev->bus->number) &&
7058 (pci_dev->devfn == ha->pcidev->devfn)) {
7059 sh = ips_sh[i];
7060 ips_release(sh);
7061 }
7062 }
7063 }
7064 }
7065
7066 /****************************************************************************/
7067 /* */
7068 /* Routine Name: ips_module_init */
7069 /* */
7070 /* Routine Description: */
7071 /* function called on module load */
7072 /****************************************************************************/
7073 static int __init
7074 ips_module_init(void)
7075 {
7076 if (pci_module_init(&ips_pci_driver) < 0)
7077 return -ENODEV;
7078 ips_driver_template.module = THIS_MODULE;
7079 ips_order_controllers();
7080 if (IPS_REGISTER_HOSTS(&ips_driver_template)) {
7081 pci_unregister_driver(&ips_pci_driver);
7082 return -ENODEV;
7083 }
7084 register_reboot_notifier(&ips_notifier);
7085 return 0;
7086 }
7087
7088 /****************************************************************************/
7089 /* */
7090 /* Routine Name: ips_module_exit */
7091 /* */
7092 /* Routine Description: */
7093 /* function called on module unload */
7094 /****************************************************************************/
7095 static void __exit
7096 ips_module_exit(void)
7097 {
7098 IPS_UNREGISTER_HOSTS(&ips_driver_template);
7099 pci_unregister_driver(&ips_pci_driver);
7100 unregister_reboot_notifier(&ips_notifier);
7101 }
7102
7103 module_init(ips_module_init);
7104 module_exit(ips_module_exit);
7105
7106 /*---------------------------------------------------------------------------*/
7107 /* Routine Name: ips_insert_device */
7108 /* */
7109 /* Routine Description: */
7110 /* Add One Adapter ( Hot Plug ) */
7111 /* */
7112 /* Return Value: */
7113 /* 0 if Successful, else non-zero */
7114 /*---------------------------------------------------------------------------*/
7115 static int __devinit
7116 ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
7117 {
7118 int index;
7119 int rc;
7120
7121 METHOD_TRACE("ips_insert_device", 1);
7122 if (pci_enable_device(pci_dev))
7123 return -1;
7124
7125 rc = ips_init_phase1(pci_dev, &index);
7126 if (rc == SUCCESS)
7127 rc = ips_init_phase2(index);
7128
7129 if (ips_hotplug)
7130 if (ips_register_scsi(index)) {
7131 ips_free(ips_ha[index]);
7132 rc = -1;
7133 }
7134
7135 if (rc == SUCCESS)
7136 ips_num_controllers++;
7137
7138 ips_next_controller = ips_num_controllers;
7139 return rc;
7140 }
7141
7142 /*---------------------------------------------------------------------------*/
7143 /* Routine Name: ips_init_phase1 */
7144 /* */
7145 /* Routine Description: */
7146 /* Adapter Initialization */
7147 /* */
7148 /* Return Value: */
7149 /* 0 if Successful, else non-zero */
7150 /*---------------------------------------------------------------------------*/
7151 static int
7152 ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
7153 {
7154 ips_ha_t *ha;
7155 uint32_t io_addr;
7156 uint32_t mem_addr;
7157 uint32_t io_len;
7158 uint32_t mem_len;
7159 uint8_t revision_id;
7160 uint8_t bus;
7161 uint8_t func;
7162 uint8_t irq;
7163 uint16_t subdevice_id;
7164 int j;
7165 int index;
7166 dma_addr_t dma_address;
7167 char __iomem *ioremap_ptr;
7168 char __iomem *mem_ptr;
7169 uint32_t IsDead;
7170
7171 METHOD_TRACE("ips_init_phase1", 1);
7172 index = IPS_MAX_ADAPTERS;
7173 for (j = 0; j < IPS_MAX_ADAPTERS; j++) {
7174 if (ips_ha[j] == 0) {
7175 index = j;
7176 break;
7177 }
7178 }
7179
7180 if (index >= IPS_MAX_ADAPTERS)
7181 return -1;
7182
7183 /* stuff that we get in dev */
7184 irq = pci_dev->irq;
7185 bus = pci_dev->bus->number;
7186 func = pci_dev->devfn;
7187
7188 /* Init MEM/IO addresses to 0 */
7189 mem_addr = 0;
7190 io_addr = 0;
7191 mem_len = 0;
7192 io_len = 0;
7193
7194 for (j = 0; j < 2; j++) {
7195 if (!pci_resource_start(pci_dev, j))
7196 break;
7197
7198 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) {
7199 io_addr = pci_resource_start(pci_dev, j);
7200 io_len = pci_resource_len(pci_dev, j);
7201 } else {
7202 mem_addr = pci_resource_start(pci_dev, j);
7203 mem_len = pci_resource_len(pci_dev, j);
7204 }
7205 }
7206
7207 /* setup memory mapped area (if applicable) */
7208 if (mem_addr) {
7209 uint32_t base;
7210 uint32_t offs;
7211
7212 if (!request_mem_region(mem_addr, mem_len, "ips")) {
7213 IPS_PRINTK(KERN_WARNING, pci_dev,
7214 "Couldn't allocate IO Memory space %x len %d.\n",
7215 mem_addr, mem_len);
7216 return -1;
7217 }
7218
7219 base = mem_addr & PAGE_MASK;
7220 offs = mem_addr - base;
7221 ioremap_ptr = ioremap(base, PAGE_SIZE);
7222 mem_ptr = ioremap_ptr + offs;
7223 } else {
7224 ioremap_ptr = NULL;
7225 mem_ptr = NULL;
7226 }
7227
7228 /* setup I/O mapped area (if applicable) */
7229 if (io_addr) {
7230 if (!request_region(io_addr, io_len, "ips")) {
7231 IPS_PRINTK(KERN_WARNING, pci_dev,
7232 "Couldn't allocate IO space %x len %d.\n",
7233 io_addr, io_len);
7234 return -1;
7235 }
7236 }
7237
7238 /* get the revision ID */
7239 if (pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id)) {
7240 IPS_PRINTK(KERN_WARNING, pci_dev, "Can't get revision id.\n");
7241 return -1;
7242 }
7243
7244 subdevice_id = pci_dev->subsystem_device;
7245
7246 /* found a controller */
7247 ha = kmalloc(sizeof (ips_ha_t), GFP_KERNEL);
7248 if (ha == NULL) {
7249 IPS_PRINTK(KERN_WARNING, pci_dev,
7250 "Unable to allocate temporary ha struct\n");
7251 return -1;
7252 }
7253
7254 memset(ha, 0, sizeof (ips_ha_t));
7255
7256 ips_sh[index] = NULL;
7257 ips_ha[index] = ha;
7258 ha->active = 1;
7259
7260 /* Store info in HA structure */
7261 ha->irq = irq;
7262 ha->io_addr = io_addr;
7263 ha->io_len = io_len;
7264 ha->mem_addr = mem_addr;
7265 ha->mem_len = mem_len;
7266 ha->mem_ptr = mem_ptr;
7267 ha->ioremap_ptr = ioremap_ptr;
7268 ha->host_num = (uint32_t) index;
7269 ha->revision_id = revision_id;
7270 ha->slot_num = PCI_SLOT(pci_dev->devfn);
7271 ha->device_id = pci_dev->device;
7272 ha->subdevice_id = subdevice_id;
7273 ha->pcidev = pci_dev;
7274
7275 /*
7276 * Set the pci_dev's dma_mask. Not all adapters support 64bit
7277 * addressing so don't enable it if the adapter can't support
7278 * it! Also, don't use 64bit addressing if dma addresses
7279 * are guaranteed to be < 4G.
7280 */
7281 if (IPS_ENABLE_DMA64 && IPS_HAS_ENH_SGLIST(ha) &&
7282 !pci_set_dma_mask(ha->pcidev, 0xffffffffffffffffULL)) {
7283 (ha)->flags |= IPS_HA_ENH_SG;
7284 } else {
7285 if (pci_set_dma_mask(ha->pcidev, 0xffffffffULL) != 0) {
7286 printk(KERN_WARNING "Unable to set DMA Mask\n");
7287 return ips_abort_init(ha, index);
7288 }
7289 }
7290 if(ips_cd_boot && !ips_FlashData){
7291 ips_FlashData = pci_alloc_consistent(pci_dev, PAGE_SIZE << 7,
7292 &ips_flashbusaddr);
7293 }
7294
7295 ha->enq = pci_alloc_consistent(pci_dev, sizeof (IPS_ENQ),
7296 &ha->enq_busaddr);
7297 if (!ha->enq) {
7298 IPS_PRINTK(KERN_WARNING, pci_dev,
7299 "Unable to allocate host inquiry structure\n");
7300 return ips_abort_init(ha, index);
7301 }
7302
7303 ha->adapt = pci_alloc_consistent(pci_dev, sizeof (IPS_ADAPTER) +
7304 sizeof (IPS_IO_CMD), &dma_address);
7305 if (!ha->adapt) {
7306 IPS_PRINTK(KERN_WARNING, pci_dev,
7307 "Unable to allocate host adapt & dummy structures\n");
7308 return ips_abort_init(ha, index);
7309 }
7310 ha->adapt->hw_status_start = dma_address;
7311 ha->dummy = (void *) (ha->adapt + 1);
7312
7313
7314
7315 ha->logical_drive_info = pci_alloc_consistent(pci_dev, sizeof (IPS_LD_INFO), &dma_address);
7316 if (!ha->logical_drive_info) {
7317 IPS_PRINTK(KERN_WARNING, pci_dev,
7318 "Unable to allocate logical drive info structure\n");
7319 return ips_abort_init(ha, index);
7320 }
7321 ha->logical_drive_info_dma_addr = dma_address;
7322
7323
7324 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL);
7325
7326 if (!ha->conf) {
7327 IPS_PRINTK(KERN_WARNING, pci_dev,
7328 "Unable to allocate host conf structure\n");
7329 return ips_abort_init(ha, index);
7330 }
7331
7332 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL);
7333
7334 if (!ha->nvram) {
7335 IPS_PRINTK(KERN_WARNING, pci_dev,
7336 "Unable to allocate host NVRAM structure\n");
7337 return ips_abort_init(ha, index);
7338 }
7339
7340 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL);
7341
7342 if (!ha->subsys) {
7343 IPS_PRINTK(KERN_WARNING, pci_dev,
7344 "Unable to allocate host subsystem structure\n");
7345 return ips_abort_init(ha, index);
7346 }
7347
7348 /* the ioctl buffer is now used during adapter initialization, so its
7349 * successful allocation is now required */
7350 if (ips_ioctlsize < PAGE_SIZE)
7351 ips_ioctlsize = PAGE_SIZE;
7352
7353 ha->ioctl_data = pci_alloc_consistent(pci_dev, ips_ioctlsize,
7354 &ha->ioctl_busaddr);
7355 ha->ioctl_len = ips_ioctlsize;
7356 if (!ha->ioctl_data) {
7357 IPS_PRINTK(KERN_WARNING, pci_dev,
7358 "Unable to allocate IOCTL data\n");
7359 return ips_abort_init(ha, index);
7360 }
7361
7362 /*
7363 * Setup Functions
7364 */
7365 ips_setup_funclist(ha);
7366
7367 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
7368 /* If Morpheus appears dead, reset it */
7369 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
7370 if (IsDead == 0xDEADBEEF) {
7371 ips_reset_morpheus(ha);
7372 }
7373 }
7374
7375 /*
7376 * Initialize the card if it isn't already
7377 */
7378
7379 if (!(*ha->func.isinit) (ha)) {
7380 if (!(*ha->func.init) (ha)) {
7381 /*
7382 * Initialization failed
7383 */
7384 IPS_PRINTK(KERN_WARNING, pci_dev,
7385 "Unable to initialize controller\n");
7386 return ips_abort_init(ha, index);
7387 }
7388 }
7389
7390 *indexPtr = index;
7391 return SUCCESS;
7392 }
7393
7394 /*---------------------------------------------------------------------------*/
7395 /* Routine Name: ips_init_phase2 */
7396 /* */
7397 /* Routine Description: */
7398 /* Adapter Initialization Phase 2 */
7399 /* */
7400 /* Return Value: */
7401 /* 0 if Successful, else non-zero */
7402 /*---------------------------------------------------------------------------*/
7403 static int
7404 ips_init_phase2(int index)
7405 {
7406 ips_ha_t *ha;
7407
7408 ha = ips_ha[index];
7409
7410 METHOD_TRACE("ips_init_phase2", 1);
7411 if (!ha->active) {
7412 ips_ha[index] = NULL;
7413 return -1;
7414 }
7415
7416 /* Install the interrupt handler */
7417 if (request_irq(ha->irq, do_ipsintr, SA_SHIRQ, ips_name, ha)) {
7418 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7419 "Unable to install interrupt handler\n");
7420 return ips_abort_init(ha, index);
7421 }
7422
7423 /*
7424 * Allocate a temporary SCB for initialization
7425 */
7426 ha->max_cmds = 1;
7427 if (!ips_allocatescbs(ha)) {
7428 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7429 "Unable to allocate a CCB\n");
7430 free_irq(ha->irq, ha);
7431 return ips_abort_init(ha, index);
7432 }
7433
7434 if (!ips_hainit(ha)) {
7435 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7436 "Unable to initialize controller\n");
7437 free_irq(ha->irq, ha);
7438 return ips_abort_init(ha, index);
7439 }
7440 /* Free the temporary SCB */
7441 ips_deallocatescbs(ha, 1);
7442
7443 /* allocate CCBs */
7444 if (!ips_allocatescbs(ha)) {
7445 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7446 "Unable to allocate CCBs\n");
7447 free_irq(ha->irq, ha);
7448 return ips_abort_init(ha, index);
7449 }
7450
7451 return SUCCESS;
7452 }
7453
7454 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,9)
7455 MODULE_LICENSE("GPL");
7456 #endif
7457
7458 MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING);
7459
7460 #ifdef MODULE_VERSION
7461 MODULE_VERSION(IPS_VER_STRING);
7462 #endif
7463
7464
7465 /*
7466 * Overrides for Emacs so that we almost follow Linus's tabbing style.
7467 * Emacs will notice this stuff at the end of the file and automatically
7468 * adjust the settings for this buffer only. This must remain at the end
7469 * of the file.
7470 * ---------------------------------------------------------------------------
7471 * Local variables:
7472 * c-indent-level: 2
7473 * c-brace-imaginary-offset: 0
7474 * c-brace-offset: -2
7475 * c-argdecl-indent: 2
7476 * c-label-offset: -2
7477 * c-continued-statement-offset: 2
7478 * c-continued-brace-offset: 0
7479 * indent-tabs-mode: nil
7480 * tab-width: 8
7481 * End:
7482 */
Linux kernel - Deliverables
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