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[deliverable/linux.git] / drivers / scsi / isci / host.c
1 /*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * BSD LICENSE
25 *
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
27 * All rights reserved.
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 *
33 * * Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * * Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in
37 * the documentation and/or other materials provided with the
38 * distribution.
39 * * Neither the name of Intel Corporation nor the names of its
40 * contributors may be used to endorse or promote products derived
41 * from this software without specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55 #include <linux/device.h>
56 #include <scsi/sas.h>
57 #include "host.h"
58 #include "isci.h"
59 #include "port.h"
60 #include "host.h"
61 #include "probe_roms.h"
62 #include "remote_device.h"
63 #include "request.h"
64 #include "scu_completion_codes.h"
65 #include "scu_event_codes.h"
66 #include "registers.h"
67 #include "scu_remote_node_context.h"
68 #include "scu_task_context.h"
69 #include "scu_unsolicited_frame.h"
70 #include "timers.h"
71
72 #define SCU_CONTEXT_RAM_INIT_STALL_TIME 200
73
74 /**
75 * smu_dcc_get_max_ports() -
76 *
77 * This macro returns the maximum number of logical ports supported by the
78 * hardware. The caller passes in the value read from the device context
79 * capacity register and this macro will mash and shift the value appropriately.
80 */
81 #define smu_dcc_get_max_ports(dcc_value) \
82 (\
83 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
84 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \
85 )
86
87 /**
88 * smu_dcc_get_max_task_context() -
89 *
90 * This macro returns the maximum number of task contexts supported by the
91 * hardware. The caller passes in the value read from the device context
92 * capacity register and this macro will mash and shift the value appropriately.
93 */
94 #define smu_dcc_get_max_task_context(dcc_value) \
95 (\
96 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
97 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \
98 )
99
100 /**
101 * smu_dcc_get_max_remote_node_context() -
102 *
103 * This macro returns the maximum number of remote node contexts supported by
104 * the hardware. The caller passes in the value read from the device context
105 * capacity register and this macro will mash and shift the value appropriately.
106 */
107 #define smu_dcc_get_max_remote_node_context(dcc_value) \
108 (\
109 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
110 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \
111 )
112
113
114 #define SCIC_SDS_CONTROLLER_MIN_TIMER_COUNT 3
115 #define SCIC_SDS_CONTROLLER_MAX_TIMER_COUNT 3
116
117 /**
118 *
119 *
120 * The number of milliseconds to wait for a phy to start.
121 */
122 #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT 100
123
124 /**
125 *
126 *
127 * The number of milliseconds to wait while a given phy is consuming power
128 * before allowing another set of phys to consume power. Ultimately, this will
129 * be specified by OEM parameter.
130 */
131 #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500
132
133 /**
134 * NORMALIZE_PUT_POINTER() -
135 *
136 * This macro will normalize the completion queue put pointer so its value can
137 * be used as an array inde
138 */
139 #define NORMALIZE_PUT_POINTER(x) \
140 ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK)
141
142
143 /**
144 * NORMALIZE_EVENT_POINTER() -
145 *
146 * This macro will normalize the completion queue event entry so its value can
147 * be used as an index.
148 */
149 #define NORMALIZE_EVENT_POINTER(x) \
150 (\
151 ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \
152 >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \
153 )
154
155 /**
156 * INCREMENT_COMPLETION_QUEUE_GET() -
157 *
158 * This macro will increment the controllers completion queue index value and
159 * possibly toggle the cycle bit if the completion queue index wraps back to 0.
160 */
161 #define INCREMENT_COMPLETION_QUEUE_GET(controller, index, cycle) \
162 INCREMENT_QUEUE_GET(\
163 (index), \
164 (cycle), \
165 (controller)->completion_queue_entries, \
166 SMU_CQGR_CYCLE_BIT \
167 )
168
169 /**
170 * INCREMENT_EVENT_QUEUE_GET() -
171 *
172 * This macro will increment the controllers event queue index value and
173 * possibly toggle the event cycle bit if the event queue index wraps back to 0.
174 */
175 #define INCREMENT_EVENT_QUEUE_GET(controller, index, cycle) \
176 INCREMENT_QUEUE_GET(\
177 (index), \
178 (cycle), \
179 (controller)->completion_event_entries, \
180 SMU_CQGR_EVENT_CYCLE_BIT \
181 )
182
183
184 /**
185 * NORMALIZE_GET_POINTER() -
186 *
187 * This macro will normalize the completion queue get pointer so its value can
188 * be used as an index into an array
189 */
190 #define NORMALIZE_GET_POINTER(x) \
191 ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK)
192
193 /**
194 * NORMALIZE_GET_POINTER_CYCLE_BIT() -
195 *
196 * This macro will normalize the completion queue cycle pointer so it matches
197 * the completion queue cycle bit
198 */
199 #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \
200 ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
201
202 /**
203 * COMPLETION_QUEUE_CYCLE_BIT() -
204 *
205 * This macro will return the cycle bit of the completion queue entry
206 */
207 #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000)
208
209 static bool scic_sds_controller_completion_queue_has_entries(
210 struct scic_sds_controller *scic)
211 {
212 u32 get_value = scic->completion_queue_get;
213 u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK;
214
215 if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) ==
216 COMPLETION_QUEUE_CYCLE_BIT(scic->completion_queue[get_index]))
217 return true;
218
219 return false;
220 }
221
222 static bool scic_sds_controller_isr(struct scic_sds_controller *scic)
223 {
224 if (scic_sds_controller_completion_queue_has_entries(scic)) {
225 return true;
226 } else {
227 /*
228 * we have a spurious interrupt it could be that we have already
229 * emptied the completion queue from a previous interrupt */
230 writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status);
231
232 /*
233 * There is a race in the hardware that could cause us not to be notified
234 * of an interrupt completion if we do not take this step. We will mask
235 * then unmask the interrupts so if there is another interrupt pending
236 * the clearing of the interrupt source we get the next interrupt message. */
237 writel(0xFF000000, &scic->smu_registers->interrupt_mask);
238 writel(0, &scic->smu_registers->interrupt_mask);
239 }
240
241 return false;
242 }
243
244 irqreturn_t isci_msix_isr(int vec, void *data)
245 {
246 struct isci_host *ihost = data;
247
248 if (scic_sds_controller_isr(&ihost->sci))
249 tasklet_schedule(&ihost->completion_tasklet);
250
251 return IRQ_HANDLED;
252 }
253
254 static bool scic_sds_controller_error_isr(struct scic_sds_controller *scic)
255 {
256 u32 interrupt_status;
257
258 interrupt_status =
259 readl(&scic->smu_registers->interrupt_status);
260 interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
261
262 if (interrupt_status != 0) {
263 /*
264 * There is an error interrupt pending so let it through and handle
265 * in the callback */
266 return true;
267 }
268
269 /*
270 * There is a race in the hardware that could cause us not to be notified
271 * of an interrupt completion if we do not take this step. We will mask
272 * then unmask the error interrupts so if there was another interrupt
273 * pending we will be notified.
274 * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */
275 writel(0xff, &scic->smu_registers->interrupt_mask);
276 writel(0, &scic->smu_registers->interrupt_mask);
277
278 return false;
279 }
280
281 static void scic_sds_controller_task_completion(struct scic_sds_controller *scic,
282 u32 completion_entry)
283 {
284 u32 index;
285 struct scic_sds_request *io_request;
286
287 index = SCU_GET_COMPLETION_INDEX(completion_entry);
288 io_request = scic->io_request_table[index];
289
290 /* Make sure that we really want to process this IO request */
291 if (
292 (io_request != NULL)
293 && (io_request->io_tag != SCI_CONTROLLER_INVALID_IO_TAG)
294 && (
295 scic_sds_io_tag_get_sequence(io_request->io_tag)
296 == scic->io_request_sequence[index]
297 )
298 ) {
299 /* Yep this is a valid io request pass it along to the io request handler */
300 scic_sds_io_request_tc_completion(io_request, completion_entry);
301 }
302 }
303
304 static void scic_sds_controller_sdma_completion(struct scic_sds_controller *scic,
305 u32 completion_entry)
306 {
307 u32 index;
308 struct scic_sds_request *io_request;
309 struct scic_sds_remote_device *device;
310
311 index = SCU_GET_COMPLETION_INDEX(completion_entry);
312
313 switch (scu_get_command_request_type(completion_entry)) {
314 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC:
315 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC:
316 io_request = scic->io_request_table[index];
317 dev_warn(scic_to_dev(scic),
318 "%s: SCIC SDS Completion type SDMA %x for io request "
319 "%p\n",
320 __func__,
321 completion_entry,
322 io_request);
323 /* @todo For a post TC operation we need to fail the IO
324 * request
325 */
326 break;
327
328 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC:
329 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC:
330 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC:
331 device = scic->device_table[index];
332 dev_warn(scic_to_dev(scic),
333 "%s: SCIC SDS Completion type SDMA %x for remote "
334 "device %p\n",
335 __func__,
336 completion_entry,
337 device);
338 /* @todo For a port RNC operation we need to fail the
339 * device
340 */
341 break;
342
343 default:
344 dev_warn(scic_to_dev(scic),
345 "%s: SCIC SDS Completion unknown SDMA completion "
346 "type %x\n",
347 __func__,
348 completion_entry);
349 break;
350
351 }
352 }
353
354 static void scic_sds_controller_unsolicited_frame(struct scic_sds_controller *scic,
355 u32 completion_entry)
356 {
357 u32 index;
358 u32 frame_index;
359
360 struct isci_host *ihost = scic_to_ihost(scic);
361 struct scu_unsolicited_frame_header *frame_header;
362 struct scic_sds_phy *phy;
363 struct scic_sds_remote_device *device;
364
365 enum sci_status result = SCI_FAILURE;
366
367 frame_index = SCU_GET_FRAME_INDEX(completion_entry);
368
369 frame_header = scic->uf_control.buffers.array[frame_index].header;
370 scic->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE;
371
372 if (SCU_GET_FRAME_ERROR(completion_entry)) {
373 /*
374 * / @todo If the IAF frame or SIGNATURE FIS frame has an error will
375 * / this cause a problem? We expect the phy initialization will
376 * / fail if there is an error in the frame. */
377 scic_sds_controller_release_frame(scic, frame_index);
378 return;
379 }
380
381 if (frame_header->is_address_frame) {
382 index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry);
383 phy = &ihost->phys[index].sci;
384 result = scic_sds_phy_frame_handler(phy, frame_index);
385 } else {
386
387 index = SCU_GET_COMPLETION_INDEX(completion_entry);
388
389 if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
390 /*
391 * This is a signature fis or a frame from a direct attached SATA
392 * device that has not yet been created. In either case forwared
393 * the frame to the PE and let it take care of the frame data. */
394 index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry);
395 phy = &ihost->phys[index].sci;
396 result = scic_sds_phy_frame_handler(phy, frame_index);
397 } else {
398 if (index < scic->remote_node_entries)
399 device = scic->device_table[index];
400 else
401 device = NULL;
402
403 if (device != NULL)
404 result = scic_sds_remote_device_frame_handler(device, frame_index);
405 else
406 scic_sds_controller_release_frame(scic, frame_index);
407 }
408 }
409
410 if (result != SCI_SUCCESS) {
411 /*
412 * / @todo Is there any reason to report some additional error message
413 * / when we get this failure notifiction? */
414 }
415 }
416
417 static void scic_sds_controller_event_completion(struct scic_sds_controller *scic,
418 u32 completion_entry)
419 {
420 struct isci_host *ihost = scic_to_ihost(scic);
421 struct scic_sds_request *io_request;
422 struct scic_sds_remote_device *device;
423 struct scic_sds_phy *phy;
424 u32 index;
425
426 index = SCU_GET_COMPLETION_INDEX(completion_entry);
427
428 switch (scu_get_event_type(completion_entry)) {
429 case SCU_EVENT_TYPE_SMU_COMMAND_ERROR:
430 /* / @todo The driver did something wrong and we need to fix the condtion. */
431 dev_err(scic_to_dev(scic),
432 "%s: SCIC Controller 0x%p received SMU command error "
433 "0x%x\n",
434 __func__,
435 scic,
436 completion_entry);
437 break;
438
439 case SCU_EVENT_TYPE_SMU_PCQ_ERROR:
440 case SCU_EVENT_TYPE_SMU_ERROR:
441 case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR:
442 /*
443 * / @todo This is a hardware failure and its likely that we want to
444 * / reset the controller. */
445 dev_err(scic_to_dev(scic),
446 "%s: SCIC Controller 0x%p received fatal controller "
447 "event 0x%x\n",
448 __func__,
449 scic,
450 completion_entry);
451 break;
452
453 case SCU_EVENT_TYPE_TRANSPORT_ERROR:
454 io_request = scic->io_request_table[index];
455 scic_sds_io_request_event_handler(io_request, completion_entry);
456 break;
457
458 case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT:
459 switch (scu_get_event_specifier(completion_entry)) {
460 case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE:
461 case SCU_EVENT_SPECIFIC_TASK_TIMEOUT:
462 io_request = scic->io_request_table[index];
463 if (io_request != NULL)
464 scic_sds_io_request_event_handler(io_request, completion_entry);
465 else
466 dev_warn(scic_to_dev(scic),
467 "%s: SCIC Controller 0x%p received "
468 "event 0x%x for io request object "
469 "that doesnt exist.\n",
470 __func__,
471 scic,
472 completion_entry);
473
474 break;
475
476 case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT:
477 device = scic->device_table[index];
478 if (device != NULL)
479 scic_sds_remote_device_event_handler(device, completion_entry);
480 else
481 dev_warn(scic_to_dev(scic),
482 "%s: SCIC Controller 0x%p received "
483 "event 0x%x for remote device object "
484 "that doesnt exist.\n",
485 __func__,
486 scic,
487 completion_entry);
488
489 break;
490 }
491 break;
492
493 case SCU_EVENT_TYPE_BROADCAST_CHANGE:
494 /*
495 * direct the broadcast change event to the phy first and then let
496 * the phy redirect the broadcast change to the port object */
497 case SCU_EVENT_TYPE_ERR_CNT_EVENT:
498 /*
499 * direct error counter event to the phy object since that is where
500 * we get the event notification. This is a type 4 event. */
501 case SCU_EVENT_TYPE_OSSP_EVENT:
502 index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry);
503 phy = &ihost->phys[index].sci;
504 scic_sds_phy_event_handler(phy, completion_entry);
505 break;
506
507 case SCU_EVENT_TYPE_RNC_SUSPEND_TX:
508 case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX:
509 case SCU_EVENT_TYPE_RNC_OPS_MISC:
510 if (index < scic->remote_node_entries) {
511 device = scic->device_table[index];
512
513 if (device != NULL)
514 scic_sds_remote_device_event_handler(device, completion_entry);
515 } else
516 dev_err(scic_to_dev(scic),
517 "%s: SCIC Controller 0x%p received event 0x%x "
518 "for remote device object 0x%0x that doesnt "
519 "exist.\n",
520 __func__,
521 scic,
522 completion_entry,
523 index);
524
525 break;
526
527 default:
528 dev_warn(scic_to_dev(scic),
529 "%s: SCIC Controller received unknown event code %x\n",
530 __func__,
531 completion_entry);
532 break;
533 }
534 }
535
536
537
538 static void scic_sds_controller_process_completions(struct scic_sds_controller *scic)
539 {
540 u32 completion_count = 0;
541 u32 completion_entry;
542 u32 get_index;
543 u32 get_cycle;
544 u32 event_index;
545 u32 event_cycle;
546
547 dev_dbg(scic_to_dev(scic),
548 "%s: completion queue begining get:0x%08x\n",
549 __func__,
550 scic->completion_queue_get);
551
552 /* Get the component parts of the completion queue */
553 get_index = NORMALIZE_GET_POINTER(scic->completion_queue_get);
554 get_cycle = SMU_CQGR_CYCLE_BIT & scic->completion_queue_get;
555
556 event_index = NORMALIZE_EVENT_POINTER(scic->completion_queue_get);
557 event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & scic->completion_queue_get;
558
559 while (
560 NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle)
561 == COMPLETION_QUEUE_CYCLE_BIT(scic->completion_queue[get_index])
562 ) {
563 completion_count++;
564
565 completion_entry = scic->completion_queue[get_index];
566 INCREMENT_COMPLETION_QUEUE_GET(scic, get_index, get_cycle);
567
568 dev_dbg(scic_to_dev(scic),
569 "%s: completion queue entry:0x%08x\n",
570 __func__,
571 completion_entry);
572
573 switch (SCU_GET_COMPLETION_TYPE(completion_entry)) {
574 case SCU_COMPLETION_TYPE_TASK:
575 scic_sds_controller_task_completion(scic, completion_entry);
576 break;
577
578 case SCU_COMPLETION_TYPE_SDMA:
579 scic_sds_controller_sdma_completion(scic, completion_entry);
580 break;
581
582 case SCU_COMPLETION_TYPE_UFI:
583 scic_sds_controller_unsolicited_frame(scic, completion_entry);
584 break;
585
586 case SCU_COMPLETION_TYPE_EVENT:
587 INCREMENT_EVENT_QUEUE_GET(scic, event_index, event_cycle);
588 scic_sds_controller_event_completion(scic, completion_entry);
589 break;
590
591 case SCU_COMPLETION_TYPE_NOTIFY:
592 /*
593 * Presently we do the same thing with a notify event that we do with the
594 * other event codes. */
595 INCREMENT_EVENT_QUEUE_GET(scic, event_index, event_cycle);
596 scic_sds_controller_event_completion(scic, completion_entry);
597 break;
598
599 default:
600 dev_warn(scic_to_dev(scic),
601 "%s: SCIC Controller received unknown "
602 "completion type %x\n",
603 __func__,
604 completion_entry);
605 break;
606 }
607 }
608
609 /* Update the get register if we completed one or more entries */
610 if (completion_count > 0) {
611 scic->completion_queue_get =
612 SMU_CQGR_GEN_BIT(ENABLE) |
613 SMU_CQGR_GEN_BIT(EVENT_ENABLE) |
614 event_cycle |
615 SMU_CQGR_GEN_VAL(EVENT_POINTER, event_index) |
616 get_cycle |
617 SMU_CQGR_GEN_VAL(POINTER, get_index);
618
619 writel(scic->completion_queue_get,
620 &scic->smu_registers->completion_queue_get);
621
622 }
623
624 dev_dbg(scic_to_dev(scic),
625 "%s: completion queue ending get:0x%08x\n",
626 __func__,
627 scic->completion_queue_get);
628
629 }
630
631 static void scic_sds_controller_error_handler(struct scic_sds_controller *scic)
632 {
633 u32 interrupt_status;
634
635 interrupt_status =
636 readl(&scic->smu_registers->interrupt_status);
637
638 if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) &&
639 scic_sds_controller_completion_queue_has_entries(scic)) {
640
641 scic_sds_controller_process_completions(scic);
642 writel(SMU_ISR_QUEUE_SUSPEND, &scic->smu_registers->interrupt_status);
643 } else {
644 dev_err(scic_to_dev(scic), "%s: status: %#x\n", __func__,
645 interrupt_status);
646
647 sci_base_state_machine_change_state(&scic->state_machine,
648 SCI_BASE_CONTROLLER_STATE_FAILED);
649
650 return;
651 }
652
653 /* If we dont process any completions I am not sure that we want to do this.
654 * We are in the middle of a hardware fault and should probably be reset.
655 */
656 writel(0, &scic->smu_registers->interrupt_mask);
657 }
658
659 irqreturn_t isci_intx_isr(int vec, void *data)
660 {
661 irqreturn_t ret = IRQ_NONE;
662 struct isci_host *ihost = data;
663 struct scic_sds_controller *scic = &ihost->sci;
664
665 if (scic_sds_controller_isr(scic)) {
666 writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status);
667 tasklet_schedule(&ihost->completion_tasklet);
668 ret = IRQ_HANDLED;
669 } else if (scic_sds_controller_error_isr(scic)) {
670 spin_lock(&ihost->scic_lock);
671 scic_sds_controller_error_handler(scic);
672 spin_unlock(&ihost->scic_lock);
673 ret = IRQ_HANDLED;
674 }
675
676 return ret;
677 }
678
679 irqreturn_t isci_error_isr(int vec, void *data)
680 {
681 struct isci_host *ihost = data;
682
683 if (scic_sds_controller_error_isr(&ihost->sci))
684 scic_sds_controller_error_handler(&ihost->sci);
685
686 return IRQ_HANDLED;
687 }
688
689 /**
690 * isci_host_start_complete() - This function is called by the core library,
691 * through the ISCI Module, to indicate controller start status.
692 * @isci_host: This parameter specifies the ISCI host object
693 * @completion_status: This parameter specifies the completion status from the
694 * core library.
695 *
696 */
697 static void isci_host_start_complete(struct isci_host *ihost, enum sci_status completion_status)
698 {
699 if (completion_status != SCI_SUCCESS)
700 dev_info(&ihost->pdev->dev,
701 "controller start timed out, continuing...\n");
702 isci_host_change_state(ihost, isci_ready);
703 clear_bit(IHOST_START_PENDING, &ihost->flags);
704 wake_up(&ihost->eventq);
705 }
706
707 int isci_host_scan_finished(struct Scsi_Host *shost, unsigned long time)
708 {
709 struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
710
711 if (test_bit(IHOST_START_PENDING, &ihost->flags))
712 return 0;
713
714 /* todo: use sas_flush_discovery once it is upstream */
715 scsi_flush_work(shost);
716
717 scsi_flush_work(shost);
718
719 dev_dbg(&ihost->pdev->dev,
720 "%s: ihost->status = %d, time = %ld\n",
721 __func__, isci_host_get_state(ihost), time);
722
723 return 1;
724
725 }
726
727 /**
728 * scic_controller_get_suggested_start_timeout() - This method returns the
729 * suggested scic_controller_start() timeout amount. The user is free to
730 * use any timeout value, but this method provides the suggested minimum
731 * start timeout value. The returned value is based upon empirical
732 * information determined as a result of interoperability testing.
733 * @controller: the handle to the controller object for which to return the
734 * suggested start timeout.
735 *
736 * This method returns the number of milliseconds for the suggested start
737 * operation timeout.
738 */
739 static u32 scic_controller_get_suggested_start_timeout(
740 struct scic_sds_controller *sc)
741 {
742 /* Validate the user supplied parameters. */
743 if (sc == NULL)
744 return 0;
745
746 /*
747 * The suggested minimum timeout value for a controller start operation:
748 *
749 * Signature FIS Timeout
750 * + Phy Start Timeout
751 * + Number of Phy Spin Up Intervals
752 * ---------------------------------
753 * Number of milliseconds for the controller start operation.
754 *
755 * NOTE: The number of phy spin up intervals will be equivalent
756 * to the number of phys divided by the number phys allowed
757 * per interval - 1 (once OEM parameters are supported).
758 * Currently we assume only 1 phy per interval. */
759
760 return SCIC_SDS_SIGNATURE_FIS_TIMEOUT
761 + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
762 + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
763 }
764
765 static void scic_controller_enable_interrupts(
766 struct scic_sds_controller *scic)
767 {
768 BUG_ON(scic->smu_registers == NULL);
769 writel(0, &scic->smu_registers->interrupt_mask);
770 }
771
772 void scic_controller_disable_interrupts(
773 struct scic_sds_controller *scic)
774 {
775 BUG_ON(scic->smu_registers == NULL);
776 writel(0xffffffff, &scic->smu_registers->interrupt_mask);
777 }
778
779 static void scic_sds_controller_enable_port_task_scheduler(
780 struct scic_sds_controller *scic)
781 {
782 u32 port_task_scheduler_value;
783
784 port_task_scheduler_value =
785 readl(&scic->scu_registers->peg0.ptsg.control);
786 port_task_scheduler_value |=
787 (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) |
788 SCU_PTSGCR_GEN_BIT(PTSG_ENABLE));
789 writel(port_task_scheduler_value,
790 &scic->scu_registers->peg0.ptsg.control);
791 }
792
793 static void scic_sds_controller_assign_task_entries(struct scic_sds_controller *scic)
794 {
795 u32 task_assignment;
796
797 /*
798 * Assign all the TCs to function 0
799 * TODO: Do we actually need to read this register to write it back?
800 */
801
802 task_assignment =
803 readl(&scic->smu_registers->task_context_assignment[0]);
804
805 task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) |
806 (SMU_TCA_GEN_VAL(ENDING, scic->task_context_entries - 1)) |
807 (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE));
808
809 writel(task_assignment,
810 &scic->smu_registers->task_context_assignment[0]);
811
812 }
813
814 static void scic_sds_controller_initialize_completion_queue(struct scic_sds_controller *scic)
815 {
816 u32 index;
817 u32 completion_queue_control_value;
818 u32 completion_queue_get_value;
819 u32 completion_queue_put_value;
820
821 scic->completion_queue_get = 0;
822
823 completion_queue_control_value = (
824 SMU_CQC_QUEUE_LIMIT_SET(scic->completion_queue_entries - 1)
825 | SMU_CQC_EVENT_LIMIT_SET(scic->completion_event_entries - 1)
826 );
827
828 writel(completion_queue_control_value,
829 &scic->smu_registers->completion_queue_control);
830
831
832 /* Set the completion queue get pointer and enable the queue */
833 completion_queue_get_value = (
834 (SMU_CQGR_GEN_VAL(POINTER, 0))
835 | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0))
836 | (SMU_CQGR_GEN_BIT(ENABLE))
837 | (SMU_CQGR_GEN_BIT(EVENT_ENABLE))
838 );
839
840 writel(completion_queue_get_value,
841 &scic->smu_registers->completion_queue_get);
842
843 /* Set the completion queue put pointer */
844 completion_queue_put_value = (
845 (SMU_CQPR_GEN_VAL(POINTER, 0))
846 | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0))
847 );
848
849 writel(completion_queue_put_value,
850 &scic->smu_registers->completion_queue_put);
851
852 /* Initialize the cycle bit of the completion queue entries */
853 for (index = 0; index < scic->completion_queue_entries; index++) {
854 /*
855 * If get.cycle_bit != completion_queue.cycle_bit
856 * its not a valid completion queue entry
857 * so at system start all entries are invalid */
858 scic->completion_queue[index] = 0x80000000;
859 }
860 }
861
862 static void scic_sds_controller_initialize_unsolicited_frame_queue(struct scic_sds_controller *scic)
863 {
864 u32 frame_queue_control_value;
865 u32 frame_queue_get_value;
866 u32 frame_queue_put_value;
867
868 /* Write the queue size */
869 frame_queue_control_value =
870 SCU_UFQC_GEN_VAL(QUEUE_SIZE,
871 scic->uf_control.address_table.count);
872
873 writel(frame_queue_control_value,
874 &scic->scu_registers->sdma.unsolicited_frame_queue_control);
875
876 /* Setup the get pointer for the unsolicited frame queue */
877 frame_queue_get_value = (
878 SCU_UFQGP_GEN_VAL(POINTER, 0)
879 | SCU_UFQGP_GEN_BIT(ENABLE_BIT)
880 );
881
882 writel(frame_queue_get_value,
883 &scic->scu_registers->sdma.unsolicited_frame_get_pointer);
884 /* Setup the put pointer for the unsolicited frame queue */
885 frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0);
886 writel(frame_queue_put_value,
887 &scic->scu_registers->sdma.unsolicited_frame_put_pointer);
888 }
889
890 /**
891 * This method will attempt to transition into the ready state for the
892 * controller and indicate that the controller start operation has completed
893 * if all criteria are met.
894 * @scic: This parameter indicates the controller object for which
895 * to transition to ready.
896 * @status: This parameter indicates the status value to be pass into the call
897 * to scic_cb_controller_start_complete().
898 *
899 * none.
900 */
901 static void scic_sds_controller_transition_to_ready(
902 struct scic_sds_controller *scic,
903 enum sci_status status)
904 {
905 struct isci_host *ihost = scic_to_ihost(scic);
906
907 if (scic->state_machine.current_state_id ==
908 SCI_BASE_CONTROLLER_STATE_STARTING) {
909 /*
910 * We move into the ready state, because some of the phys/ports
911 * may be up and operational.
912 */
913 sci_base_state_machine_change_state(&scic->state_machine,
914 SCI_BASE_CONTROLLER_STATE_READY);
915
916 isci_host_start_complete(ihost, status);
917 }
918 }
919
920 static bool is_phy_starting(struct scic_sds_phy *sci_phy)
921 {
922 enum scic_sds_phy_states state;
923
924 state = sci_phy->state_machine.current_state_id;
925 switch (state) {
926 case SCI_BASE_PHY_STATE_STARTING:
927 case SCIC_SDS_PHY_STARTING_SUBSTATE_INITIAL:
928 case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_SPEED_EN:
929 case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_IAF_UF:
930 case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_POWER:
931 case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_POWER:
932 case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_PHY_EN:
933 case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_SPEED_EN:
934 case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SIG_FIS_UF:
935 case SCIC_SDS_PHY_STARTING_SUBSTATE_FINAL:
936 return true;
937 default:
938 return false;
939 }
940 }
941
942 /**
943 * scic_sds_controller_start_next_phy - start phy
944 * @scic: controller
945 *
946 * If all the phys have been started, then attempt to transition the
947 * controller to the READY state and inform the user
948 * (scic_cb_controller_start_complete()).
949 */
950 static enum sci_status scic_sds_controller_start_next_phy(struct scic_sds_controller *scic)
951 {
952 struct isci_host *ihost = scic_to_ihost(scic);
953 struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1;
954 struct scic_sds_phy *sci_phy;
955 enum sci_status status;
956
957 status = SCI_SUCCESS;
958
959 if (scic->phy_startup_timer_pending)
960 return status;
961
962 if (scic->next_phy_to_start >= SCI_MAX_PHYS) {
963 bool is_controller_start_complete = true;
964 u32 state;
965 u8 index;
966
967 for (index = 0; index < SCI_MAX_PHYS; index++) {
968 sci_phy = &ihost->phys[index].sci;
969 state = sci_phy->state_machine.current_state_id;
970
971 if (!phy_get_non_dummy_port(sci_phy))
972 continue;
973
974 /* The controller start operation is complete iff:
975 * - all links have been given an opportunity to start
976 * - have no indication of a connected device
977 * - have an indication of a connected device and it has
978 * finished the link training process.
979 */
980 if ((sci_phy->is_in_link_training == false &&
981 state == SCI_BASE_PHY_STATE_INITIAL) ||
982 (sci_phy->is_in_link_training == false &&
983 state == SCI_BASE_PHY_STATE_STOPPED) ||
984 (sci_phy->is_in_link_training == true &&
985 is_phy_starting(sci_phy))) {
986 is_controller_start_complete = false;
987 break;
988 }
989 }
990
991 /*
992 * The controller has successfully finished the start process.
993 * Inform the SCI Core user and transition to the READY state. */
994 if (is_controller_start_complete == true) {
995 scic_sds_controller_transition_to_ready(scic, SCI_SUCCESS);
996 sci_del_timer(&scic->phy_timer);
997 scic->phy_startup_timer_pending = false;
998 }
999 } else {
1000 sci_phy = &ihost->phys[scic->next_phy_to_start].sci;
1001
1002 if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
1003 if (phy_get_non_dummy_port(sci_phy) == NULL) {
1004 scic->next_phy_to_start++;
1005
1006 /* Caution recursion ahead be forwarned
1007 *
1008 * The PHY was never added to a PORT in MPC mode
1009 * so start the next phy in sequence This phy
1010 * will never go link up and will not draw power
1011 * the OEM parameters either configured the phy
1012 * incorrectly for the PORT or it was never
1013 * assigned to a PORT
1014 */
1015 return scic_sds_controller_start_next_phy(scic);
1016 }
1017 }
1018
1019 status = scic_sds_phy_start(sci_phy);
1020
1021 if (status == SCI_SUCCESS) {
1022 sci_mod_timer(&scic->phy_timer,
1023 SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT);
1024 scic->phy_startup_timer_pending = true;
1025 } else {
1026 dev_warn(scic_to_dev(scic),
1027 "%s: Controller stop operation failed "
1028 "to stop phy %d because of status "
1029 "%d.\n",
1030 __func__,
1031 ihost->phys[scic->next_phy_to_start].sci.phy_index,
1032 status);
1033 }
1034
1035 scic->next_phy_to_start++;
1036 }
1037
1038 return status;
1039 }
1040
1041 static void phy_startup_timeout(unsigned long data)
1042 {
1043 struct sci_timer *tmr = (struct sci_timer *)data;
1044 struct scic_sds_controller *scic = container_of(tmr, typeof(*scic), phy_timer);
1045 struct isci_host *ihost = scic_to_ihost(scic);
1046 unsigned long flags;
1047 enum sci_status status;
1048
1049 spin_lock_irqsave(&ihost->scic_lock, flags);
1050
1051 if (tmr->cancel)
1052 goto done;
1053
1054 scic->phy_startup_timer_pending = false;
1055
1056 do {
1057 status = scic_sds_controller_start_next_phy(scic);
1058 } while (status != SCI_SUCCESS);
1059
1060 done:
1061 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1062 }
1063
1064 static enum sci_status scic_controller_start(struct scic_sds_controller *scic,
1065 u32 timeout)
1066 {
1067 struct isci_host *ihost = scic_to_ihost(scic);
1068 enum sci_status result;
1069 u16 index;
1070
1071 if (scic->state_machine.current_state_id !=
1072 SCI_BASE_CONTROLLER_STATE_INITIALIZED) {
1073 dev_warn(scic_to_dev(scic),
1074 "SCIC Controller start operation requested in "
1075 "invalid state\n");
1076 return SCI_FAILURE_INVALID_STATE;
1077 }
1078
1079 /* Build the TCi free pool */
1080 sci_pool_initialize(scic->tci_pool);
1081 for (index = 0; index < scic->task_context_entries; index++)
1082 sci_pool_put(scic->tci_pool, index);
1083
1084 /* Build the RNi free pool */
1085 scic_sds_remote_node_table_initialize(
1086 &scic->available_remote_nodes,
1087 scic->remote_node_entries);
1088
1089 /*
1090 * Before anything else lets make sure we will not be
1091 * interrupted by the hardware.
1092 */
1093 scic_controller_disable_interrupts(scic);
1094
1095 /* Enable the port task scheduler */
1096 scic_sds_controller_enable_port_task_scheduler(scic);
1097
1098 /* Assign all the task entries to scic physical function */
1099 scic_sds_controller_assign_task_entries(scic);
1100
1101 /* Now initialize the completion queue */
1102 scic_sds_controller_initialize_completion_queue(scic);
1103
1104 /* Initialize the unsolicited frame queue for use */
1105 scic_sds_controller_initialize_unsolicited_frame_queue(scic);
1106
1107 /* Start all of the ports on this controller */
1108 for (index = 0; index < scic->logical_port_entries; index++) {
1109 struct scic_sds_port *sci_port = &ihost->ports[index].sci;
1110
1111 result = scic_sds_port_start(sci_port);
1112 if (result)
1113 return result;
1114 }
1115
1116 scic_sds_controller_start_next_phy(scic);
1117
1118 sci_mod_timer(&scic->timer, timeout);
1119
1120 sci_base_state_machine_change_state(&scic->state_machine,
1121 SCI_BASE_CONTROLLER_STATE_STARTING);
1122
1123 return SCI_SUCCESS;
1124 }
1125
1126 void isci_host_scan_start(struct Scsi_Host *shost)
1127 {
1128 struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
1129 unsigned long tmo = scic_controller_get_suggested_start_timeout(&ihost->sci);
1130
1131 set_bit(IHOST_START_PENDING, &ihost->flags);
1132
1133 spin_lock_irq(&ihost->scic_lock);
1134 scic_controller_start(&ihost->sci, tmo);
1135 scic_controller_enable_interrupts(&ihost->sci);
1136 spin_unlock_irq(&ihost->scic_lock);
1137 }
1138
1139 static void isci_host_stop_complete(struct isci_host *ihost, enum sci_status completion_status)
1140 {
1141 isci_host_change_state(ihost, isci_stopped);
1142 scic_controller_disable_interrupts(&ihost->sci);
1143 clear_bit(IHOST_STOP_PENDING, &ihost->flags);
1144 wake_up(&ihost->eventq);
1145 }
1146
1147 static void scic_sds_controller_completion_handler(struct scic_sds_controller *scic)
1148 {
1149 /* Empty out the completion queue */
1150 if (scic_sds_controller_completion_queue_has_entries(scic))
1151 scic_sds_controller_process_completions(scic);
1152
1153 /* Clear the interrupt and enable all interrupts again */
1154 writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status);
1155 /* Could we write the value of SMU_ISR_COMPLETION? */
1156 writel(0xFF000000, &scic->smu_registers->interrupt_mask);
1157 writel(0, &scic->smu_registers->interrupt_mask);
1158 }
1159
1160 /**
1161 * isci_host_completion_routine() - This function is the delayed service
1162 * routine that calls the sci core library's completion handler. It's
1163 * scheduled as a tasklet from the interrupt service routine when interrupts
1164 * in use, or set as the timeout function in polled mode.
1165 * @data: This parameter specifies the ISCI host object
1166 *
1167 */
1168 static void isci_host_completion_routine(unsigned long data)
1169 {
1170 struct isci_host *isci_host = (struct isci_host *)data;
1171 struct list_head completed_request_list;
1172 struct list_head errored_request_list;
1173 struct list_head *current_position;
1174 struct list_head *next_position;
1175 struct isci_request *request;
1176 struct isci_request *next_request;
1177 struct sas_task *task;
1178
1179 INIT_LIST_HEAD(&completed_request_list);
1180 INIT_LIST_HEAD(&errored_request_list);
1181
1182 spin_lock_irq(&isci_host->scic_lock);
1183
1184 scic_sds_controller_completion_handler(&isci_host->sci);
1185
1186 /* Take the lists of completed I/Os from the host. */
1187
1188 list_splice_init(&isci_host->requests_to_complete,
1189 &completed_request_list);
1190
1191 /* Take the list of errored I/Os from the host. */
1192 list_splice_init(&isci_host->requests_to_errorback,
1193 &errored_request_list);
1194
1195 spin_unlock_irq(&isci_host->scic_lock);
1196
1197 /* Process any completions in the lists. */
1198 list_for_each_safe(current_position, next_position,
1199 &completed_request_list) {
1200
1201 request = list_entry(current_position, struct isci_request,
1202 completed_node);
1203 task = isci_request_access_task(request);
1204
1205 /* Normal notification (task_done) */
1206 dev_dbg(&isci_host->pdev->dev,
1207 "%s: Normal - request/task = %p/%p\n",
1208 __func__,
1209 request,
1210 task);
1211
1212 /* Return the task to libsas */
1213 if (task != NULL) {
1214
1215 task->lldd_task = NULL;
1216 if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
1217
1218 /* If the task is already in the abort path,
1219 * the task_done callback cannot be called.
1220 */
1221 task->task_done(task);
1222 }
1223 }
1224 /* Free the request object. */
1225 isci_request_free(isci_host, request);
1226 }
1227 list_for_each_entry_safe(request, next_request, &errored_request_list,
1228 completed_node) {
1229
1230 task = isci_request_access_task(request);
1231
1232 /* Use sas_task_abort */
1233 dev_warn(&isci_host->pdev->dev,
1234 "%s: Error - request/task = %p/%p\n",
1235 __func__,
1236 request,
1237 task);
1238
1239 if (task != NULL) {
1240
1241 /* Put the task into the abort path if it's not there
1242 * already.
1243 */
1244 if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED))
1245 sas_task_abort(task);
1246
1247 } else {
1248 /* This is a case where the request has completed with a
1249 * status such that it needed further target servicing,
1250 * but the sas_task reference has already been removed
1251 * from the request. Since it was errored, it was not
1252 * being aborted, so there is nothing to do except free
1253 * it.
1254 */
1255
1256 spin_lock_irq(&isci_host->scic_lock);
1257 /* Remove the request from the remote device's list
1258 * of pending requests.
1259 */
1260 list_del_init(&request->dev_node);
1261 spin_unlock_irq(&isci_host->scic_lock);
1262
1263 /* Free the request object. */
1264 isci_request_free(isci_host, request);
1265 }
1266 }
1267
1268 }
1269
1270 /**
1271 * scic_controller_stop() - This method will stop an individual controller
1272 * object.This method will invoke the associated user callback upon
1273 * completion. The completion callback is called when the following
1274 * conditions are met: -# the method return status is SCI_SUCCESS. -# the
1275 * controller has been quiesced. This method will ensure that all IO
1276 * requests are quiesced, phys are stopped, and all additional operation by
1277 * the hardware is halted.
1278 * @controller: the handle to the controller object to stop.
1279 * @timeout: This parameter specifies the number of milliseconds in which the
1280 * stop operation should complete.
1281 *
1282 * The controller must be in the STARTED or STOPPED state. Indicate if the
1283 * controller stop method succeeded or failed in some way. SCI_SUCCESS if the
1284 * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the
1285 * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the
1286 * controller is not either in the STARTED or STOPPED states.
1287 */
1288 static enum sci_status scic_controller_stop(struct scic_sds_controller *scic,
1289 u32 timeout)
1290 {
1291 if (scic->state_machine.current_state_id !=
1292 SCI_BASE_CONTROLLER_STATE_READY) {
1293 dev_warn(scic_to_dev(scic),
1294 "SCIC Controller stop operation requested in "
1295 "invalid state\n");
1296 return SCI_FAILURE_INVALID_STATE;
1297 }
1298
1299 sci_mod_timer(&scic->timer, timeout);
1300 sci_base_state_machine_change_state(&scic->state_machine,
1301 SCI_BASE_CONTROLLER_STATE_STOPPING);
1302 return SCI_SUCCESS;
1303 }
1304
1305 /**
1306 * scic_controller_reset() - This method will reset the supplied core
1307 * controller regardless of the state of said controller. This operation is
1308 * considered destructive. In other words, all current operations are wiped
1309 * out. No IO completions for outstanding devices occur. Outstanding IO
1310 * requests are not aborted or completed at the actual remote device.
1311 * @controller: the handle to the controller object to reset.
1312 *
1313 * Indicate if the controller reset method succeeded or failed in some way.
1314 * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if
1315 * the controller reset operation is unable to complete.
1316 */
1317 static enum sci_status scic_controller_reset(struct scic_sds_controller *scic)
1318 {
1319 switch (scic->state_machine.current_state_id) {
1320 case SCI_BASE_CONTROLLER_STATE_RESET:
1321 case SCI_BASE_CONTROLLER_STATE_READY:
1322 case SCI_BASE_CONTROLLER_STATE_STOPPED:
1323 case SCI_BASE_CONTROLLER_STATE_FAILED:
1324 /*
1325 * The reset operation is not a graceful cleanup, just
1326 * perform the state transition.
1327 */
1328 sci_base_state_machine_change_state(&scic->state_machine,
1329 SCI_BASE_CONTROLLER_STATE_RESETTING);
1330 return SCI_SUCCESS;
1331 default:
1332 dev_warn(scic_to_dev(scic),
1333 "SCIC Controller reset operation requested in "
1334 "invalid state\n");
1335 return SCI_FAILURE_INVALID_STATE;
1336 }
1337 }
1338
1339 void isci_host_deinit(struct isci_host *ihost)
1340 {
1341 int i;
1342
1343 isci_host_change_state(ihost, isci_stopping);
1344 for (i = 0; i < SCI_MAX_PORTS; i++) {
1345 struct isci_port *iport = &ihost->ports[i];
1346 struct isci_remote_device *idev, *d;
1347
1348 list_for_each_entry_safe(idev, d, &iport->remote_dev_list, node) {
1349 isci_remote_device_change_state(idev, isci_stopping);
1350 isci_remote_device_stop(ihost, idev);
1351 }
1352 }
1353
1354 set_bit(IHOST_STOP_PENDING, &ihost->flags);
1355
1356 spin_lock_irq(&ihost->scic_lock);
1357 scic_controller_stop(&ihost->sci, SCIC_CONTROLLER_STOP_TIMEOUT);
1358 spin_unlock_irq(&ihost->scic_lock);
1359
1360 wait_for_stop(ihost);
1361 scic_controller_reset(&ihost->sci);
1362
1363 /* Cancel any/all outstanding port timers */
1364 for (i = 0; i < ihost->sci.logical_port_entries; i++) {
1365 struct scic_sds_port *sci_port = &ihost->ports[i].sci;
1366 del_timer_sync(&sci_port->timer.timer);
1367 }
1368
1369 /* Cancel any/all outstanding phy timers */
1370 for (i = 0; i < SCI_MAX_PHYS; i++) {
1371 struct scic_sds_phy *sci_phy = &ihost->phys[i].sci;
1372 del_timer_sync(&sci_phy->sata_timer.timer);
1373 }
1374
1375 del_timer_sync(&ihost->sci.port_agent.timer.timer);
1376
1377 del_timer_sync(&ihost->sci.power_control.timer.timer);
1378
1379 del_timer_sync(&ihost->sci.timer.timer);
1380
1381 del_timer_sync(&ihost->sci.phy_timer.timer);
1382
1383 isci_timer_list_destroy(ihost);
1384 }
1385
1386 static void __iomem *scu_base(struct isci_host *isci_host)
1387 {
1388 struct pci_dev *pdev = isci_host->pdev;
1389 int id = isci_host->id;
1390
1391 return pcim_iomap_table(pdev)[SCI_SCU_BAR * 2] + SCI_SCU_BAR_SIZE * id;
1392 }
1393
1394 static void __iomem *smu_base(struct isci_host *isci_host)
1395 {
1396 struct pci_dev *pdev = isci_host->pdev;
1397 int id = isci_host->id;
1398
1399 return pcim_iomap_table(pdev)[SCI_SMU_BAR * 2] + SCI_SMU_BAR_SIZE * id;
1400 }
1401
1402 static void isci_user_parameters_get(
1403 struct isci_host *isci_host,
1404 union scic_user_parameters *scic_user_params)
1405 {
1406 struct scic_sds_user_parameters *u = &scic_user_params->sds1;
1407 int i;
1408
1409 for (i = 0; i < SCI_MAX_PHYS; i++) {
1410 struct sci_phy_user_params *u_phy = &u->phys[i];
1411
1412 u_phy->max_speed_generation = phy_gen;
1413
1414 /* we are not exporting these for now */
1415 u_phy->align_insertion_frequency = 0x7f;
1416 u_phy->in_connection_align_insertion_frequency = 0xff;
1417 u_phy->notify_enable_spin_up_insertion_frequency = 0x33;
1418 }
1419
1420 u->stp_inactivity_timeout = stp_inactive_to;
1421 u->ssp_inactivity_timeout = ssp_inactive_to;
1422 u->stp_max_occupancy_timeout = stp_max_occ_to;
1423 u->ssp_max_occupancy_timeout = ssp_max_occ_to;
1424 u->no_outbound_task_timeout = no_outbound_task_to;
1425 u->max_number_concurrent_device_spin_up = max_concurr_spinup;
1426 }
1427
1428 static void scic_sds_controller_initial_state_enter(struct sci_base_state_machine *sm)
1429 {
1430 struct scic_sds_controller *scic = container_of(sm, typeof(*scic), state_machine);
1431
1432 sci_base_state_machine_change_state(&scic->state_machine,
1433 SCI_BASE_CONTROLLER_STATE_RESET);
1434 }
1435
1436 static inline void scic_sds_controller_starting_state_exit(struct sci_base_state_machine *sm)
1437 {
1438 struct scic_sds_controller *scic = container_of(sm, typeof(*scic), state_machine);
1439
1440 sci_del_timer(&scic->timer);
1441 }
1442
1443 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853
1444 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280
1445 #define INTERRUPT_COALESCE_TIMEOUT_MAX_US 2700000
1446 #define INTERRUPT_COALESCE_NUMBER_MAX 256
1447 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN 7
1448 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX 28
1449
1450 /**
1451 * scic_controller_set_interrupt_coalescence() - This method allows the user to
1452 * configure the interrupt coalescence.
1453 * @controller: This parameter represents the handle to the controller object
1454 * for which its interrupt coalesce register is overridden.
1455 * @coalesce_number: Used to control the number of entries in the Completion
1456 * Queue before an interrupt is generated. If the number of entries exceed
1457 * this number, an interrupt will be generated. The valid range of the input
1458 * is [0, 256]. A setting of 0 results in coalescing being disabled.
1459 * @coalesce_timeout: Timeout value in microseconds. The valid range of the
1460 * input is [0, 2700000] . A setting of 0 is allowed and results in no
1461 * interrupt coalescing timeout.
1462 *
1463 * Indicate if the user successfully set the interrupt coalesce parameters.
1464 * SCI_SUCCESS The user successfully updated the interrutp coalescence.
1465 * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range.
1466 */
1467 static enum sci_status scic_controller_set_interrupt_coalescence(
1468 struct scic_sds_controller *scic_controller,
1469 u32 coalesce_number,
1470 u32 coalesce_timeout)
1471 {
1472 u8 timeout_encode = 0;
1473 u32 min = 0;
1474 u32 max = 0;
1475
1476 /* Check if the input parameters fall in the range. */
1477 if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX)
1478 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1479
1480 /*
1481 * Defined encoding for interrupt coalescing timeout:
1482 * Value Min Max Units
1483 * ----- --- --- -----
1484 * 0 - - Disabled
1485 * 1 13.3 20.0 ns
1486 * 2 26.7 40.0
1487 * 3 53.3 80.0
1488 * 4 106.7 160.0
1489 * 5 213.3 320.0
1490 * 6 426.7 640.0
1491 * 7 853.3 1280.0
1492 * 8 1.7 2.6 us
1493 * 9 3.4 5.1
1494 * 10 6.8 10.2
1495 * 11 13.7 20.5
1496 * 12 27.3 41.0
1497 * 13 54.6 81.9
1498 * 14 109.2 163.8
1499 * 15 218.5 327.7
1500 * 16 436.9 655.4
1501 * 17 873.8 1310.7
1502 * 18 1.7 2.6 ms
1503 * 19 3.5 5.2
1504 * 20 7.0 10.5
1505 * 21 14.0 21.0
1506 * 22 28.0 41.9
1507 * 23 55.9 83.9
1508 * 24 111.8 167.8
1509 * 25 223.7 335.5
1510 * 26 447.4 671.1
1511 * 27 894.8 1342.2
1512 * 28 1.8 2.7 s
1513 * Others Undefined */
1514
1515 /*
1516 * Use the table above to decide the encode of interrupt coalescing timeout
1517 * value for register writing. */
1518 if (coalesce_timeout == 0)
1519 timeout_encode = 0;
1520 else{
1521 /* make the timeout value in unit of (10 ns). */
1522 coalesce_timeout = coalesce_timeout * 100;
1523 min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10;
1524 max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10;
1525
1526 /* get the encode of timeout for register writing. */
1527 for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN;
1528 timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX;
1529 timeout_encode++) {
1530 if (min <= coalesce_timeout && max > coalesce_timeout)
1531 break;
1532 else if (coalesce_timeout >= max && coalesce_timeout < min * 2
1533 && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) {
1534 if ((coalesce_timeout - max) < (2 * min - coalesce_timeout))
1535 break;
1536 else{
1537 timeout_encode++;
1538 break;
1539 }
1540 } else {
1541 max = max * 2;
1542 min = min * 2;
1543 }
1544 }
1545
1546 if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1)
1547 /* the value is out of range. */
1548 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1549 }
1550
1551 writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) |
1552 SMU_ICC_GEN_VAL(TIMER, timeout_encode),
1553 &scic_controller->smu_registers->interrupt_coalesce_control);
1554
1555
1556 scic_controller->interrupt_coalesce_number = (u16)coalesce_number;
1557 scic_controller->interrupt_coalesce_timeout = coalesce_timeout / 100;
1558
1559 return SCI_SUCCESS;
1560 }
1561
1562
1563 static void scic_sds_controller_ready_state_enter(struct sci_base_state_machine *sm)
1564 {
1565 struct scic_sds_controller *scic = container_of(sm, typeof(*scic), state_machine);
1566
1567 /* set the default interrupt coalescence number and timeout value. */
1568 scic_controller_set_interrupt_coalescence(scic, 0x10, 250);
1569 }
1570
1571 static void scic_sds_controller_ready_state_exit(struct sci_base_state_machine *sm)
1572 {
1573 struct scic_sds_controller *scic = container_of(sm, typeof(*scic), state_machine);
1574
1575 /* disable interrupt coalescence. */
1576 scic_controller_set_interrupt_coalescence(scic, 0, 0);
1577 }
1578
1579 static enum sci_status scic_sds_controller_stop_phys(struct scic_sds_controller *scic)
1580 {
1581 u32 index;
1582 enum sci_status status;
1583 enum sci_status phy_status;
1584 struct isci_host *ihost = scic_to_ihost(scic);
1585
1586 status = SCI_SUCCESS;
1587
1588 for (index = 0; index < SCI_MAX_PHYS; index++) {
1589 phy_status = scic_sds_phy_stop(&ihost->phys[index].sci);
1590
1591 if (phy_status != SCI_SUCCESS &&
1592 phy_status != SCI_FAILURE_INVALID_STATE) {
1593 status = SCI_FAILURE;
1594
1595 dev_warn(scic_to_dev(scic),
1596 "%s: Controller stop operation failed to stop "
1597 "phy %d because of status %d.\n",
1598 __func__,
1599 ihost->phys[index].sci.phy_index, phy_status);
1600 }
1601 }
1602
1603 return status;
1604 }
1605
1606 static enum sci_status scic_sds_controller_stop_ports(struct scic_sds_controller *scic)
1607 {
1608 u32 index;
1609 enum sci_status port_status;
1610 enum sci_status status = SCI_SUCCESS;
1611 struct isci_host *ihost = scic_to_ihost(scic);
1612
1613 for (index = 0; index < scic->logical_port_entries; index++) {
1614 struct scic_sds_port *sci_port = &ihost->ports[index].sci;
1615
1616 port_status = scic_sds_port_stop(sci_port);
1617
1618 if ((port_status != SCI_SUCCESS) &&
1619 (port_status != SCI_FAILURE_INVALID_STATE)) {
1620 status = SCI_FAILURE;
1621
1622 dev_warn(scic_to_dev(scic),
1623 "%s: Controller stop operation failed to "
1624 "stop port %d because of status %d.\n",
1625 __func__,
1626 sci_port->logical_port_index,
1627 port_status);
1628 }
1629 }
1630
1631 return status;
1632 }
1633
1634 static enum sci_status scic_sds_controller_stop_devices(struct scic_sds_controller *scic)
1635 {
1636 u32 index;
1637 enum sci_status status;
1638 enum sci_status device_status;
1639
1640 status = SCI_SUCCESS;
1641
1642 for (index = 0; index < scic->remote_node_entries; index++) {
1643 if (scic->device_table[index] != NULL) {
1644 /* / @todo What timeout value do we want to provide to this request? */
1645 device_status = scic_remote_device_stop(scic->device_table[index], 0);
1646
1647 if ((device_status != SCI_SUCCESS) &&
1648 (device_status != SCI_FAILURE_INVALID_STATE)) {
1649 dev_warn(scic_to_dev(scic),
1650 "%s: Controller stop operation failed "
1651 "to stop device 0x%p because of "
1652 "status %d.\n",
1653 __func__,
1654 scic->device_table[index], device_status);
1655 }
1656 }
1657 }
1658
1659 return status;
1660 }
1661
1662 static void scic_sds_controller_stopping_state_enter(struct sci_base_state_machine *sm)
1663 {
1664 struct scic_sds_controller *scic = container_of(sm, typeof(*scic), state_machine);
1665
1666 /* Stop all of the components for this controller */
1667 scic_sds_controller_stop_phys(scic);
1668 scic_sds_controller_stop_ports(scic);
1669 scic_sds_controller_stop_devices(scic);
1670 }
1671
1672 static void scic_sds_controller_stopping_state_exit(struct sci_base_state_machine *sm)
1673 {
1674 struct scic_sds_controller *scic = container_of(sm, typeof(*scic), state_machine);
1675
1676 sci_del_timer(&scic->timer);
1677 }
1678
1679
1680 /**
1681 * scic_sds_controller_reset_hardware() -
1682 *
1683 * This method will reset the controller hardware.
1684 */
1685 static void scic_sds_controller_reset_hardware(struct scic_sds_controller *scic)
1686 {
1687 /* Disable interrupts so we dont take any spurious interrupts */
1688 scic_controller_disable_interrupts(scic);
1689
1690 /* Reset the SCU */
1691 writel(0xFFFFFFFF, &scic->smu_registers->soft_reset_control);
1692
1693 /* Delay for 1ms to before clearing the CQP and UFQPR. */
1694 udelay(1000);
1695
1696 /* The write to the CQGR clears the CQP */
1697 writel(0x00000000, &scic->smu_registers->completion_queue_get);
1698
1699 /* The write to the UFQGP clears the UFQPR */
1700 writel(0, &scic->scu_registers->sdma.unsolicited_frame_get_pointer);
1701 }
1702
1703 static void scic_sds_controller_resetting_state_enter(struct sci_base_state_machine *sm)
1704 {
1705 struct scic_sds_controller *scic = container_of(sm, typeof(*scic), state_machine);
1706
1707 scic_sds_controller_reset_hardware(scic);
1708 sci_base_state_machine_change_state(&scic->state_machine,
1709 SCI_BASE_CONTROLLER_STATE_RESET);
1710 }
1711
1712 static const struct sci_base_state scic_sds_controller_state_table[] = {
1713 [SCI_BASE_CONTROLLER_STATE_INITIAL] = {
1714 .enter_state = scic_sds_controller_initial_state_enter,
1715 },
1716 [SCI_BASE_CONTROLLER_STATE_RESET] = {},
1717 [SCI_BASE_CONTROLLER_STATE_INITIALIZING] = {},
1718 [SCI_BASE_CONTROLLER_STATE_INITIALIZED] = {},
1719 [SCI_BASE_CONTROLLER_STATE_STARTING] = {
1720 .exit_state = scic_sds_controller_starting_state_exit,
1721 },
1722 [SCI_BASE_CONTROLLER_STATE_READY] = {
1723 .enter_state = scic_sds_controller_ready_state_enter,
1724 .exit_state = scic_sds_controller_ready_state_exit,
1725 },
1726 [SCI_BASE_CONTROLLER_STATE_RESETTING] = {
1727 .enter_state = scic_sds_controller_resetting_state_enter,
1728 },
1729 [SCI_BASE_CONTROLLER_STATE_STOPPING] = {
1730 .enter_state = scic_sds_controller_stopping_state_enter,
1731 .exit_state = scic_sds_controller_stopping_state_exit,
1732 },
1733 [SCI_BASE_CONTROLLER_STATE_STOPPED] = {},
1734 [SCI_BASE_CONTROLLER_STATE_FAILED] = {}
1735 };
1736
1737 static void scic_sds_controller_set_default_config_parameters(struct scic_sds_controller *scic)
1738 {
1739 /* these defaults are overridden by the platform / firmware */
1740 struct isci_host *ihost = scic_to_ihost(scic);
1741 u16 index;
1742
1743 /* Default to APC mode. */
1744 scic->oem_parameters.sds1.controller.mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE;
1745
1746 /* Default to APC mode. */
1747 scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up = 1;
1748
1749 /* Default to no SSC operation. */
1750 scic->oem_parameters.sds1.controller.do_enable_ssc = false;
1751
1752 /* Initialize all of the port parameter information to narrow ports. */
1753 for (index = 0; index < SCI_MAX_PORTS; index++) {
1754 scic->oem_parameters.sds1.ports[index].phy_mask = 0;
1755 }
1756
1757 /* Initialize all of the phy parameter information. */
1758 for (index = 0; index < SCI_MAX_PHYS; index++) {
1759 /* Default to 6G (i.e. Gen 3) for now. */
1760 scic->user_parameters.sds1.phys[index].max_speed_generation = 3;
1761
1762 /* the frequencies cannot be 0 */
1763 scic->user_parameters.sds1.phys[index].align_insertion_frequency = 0x7f;
1764 scic->user_parameters.sds1.phys[index].in_connection_align_insertion_frequency = 0xff;
1765 scic->user_parameters.sds1.phys[index].notify_enable_spin_up_insertion_frequency = 0x33;
1766
1767 /*
1768 * Previous Vitesse based expanders had a arbitration issue that
1769 * is worked around by having the upper 32-bits of SAS address
1770 * with a value greater then the Vitesse company identifier.
1771 * Hence, usage of 0x5FCFFFFF. */
1772 scic->oem_parameters.sds1.phys[index].sas_address.low = 0x1 + ihost->id;
1773 scic->oem_parameters.sds1.phys[index].sas_address.high = 0x5FCFFFFF;
1774 }
1775
1776 scic->user_parameters.sds1.stp_inactivity_timeout = 5;
1777 scic->user_parameters.sds1.ssp_inactivity_timeout = 5;
1778 scic->user_parameters.sds1.stp_max_occupancy_timeout = 5;
1779 scic->user_parameters.sds1.ssp_max_occupancy_timeout = 20;
1780 scic->user_parameters.sds1.no_outbound_task_timeout = 20;
1781 }
1782
1783 static void controller_timeout(unsigned long data)
1784 {
1785 struct sci_timer *tmr = (struct sci_timer *)data;
1786 struct scic_sds_controller *scic = container_of(tmr, typeof(*scic), timer);
1787 struct isci_host *ihost = scic_to_ihost(scic);
1788 struct sci_base_state_machine *sm = &scic->state_machine;
1789 unsigned long flags;
1790
1791 spin_lock_irqsave(&ihost->scic_lock, flags);
1792
1793 if (tmr->cancel)
1794 goto done;
1795
1796 if (sm->current_state_id == SCI_BASE_CONTROLLER_STATE_STARTING)
1797 scic_sds_controller_transition_to_ready(scic, SCI_FAILURE_TIMEOUT);
1798 else if (sm->current_state_id == SCI_BASE_CONTROLLER_STATE_STOPPING) {
1799 sci_base_state_machine_change_state(sm, SCI_BASE_CONTROLLER_STATE_FAILED);
1800 isci_host_stop_complete(ihost, SCI_FAILURE_TIMEOUT);
1801 } else /* / @todo Now what do we want to do in this case? */
1802 dev_err(scic_to_dev(scic),
1803 "%s: Controller timer fired when controller was not "
1804 "in a state being timed.\n",
1805 __func__);
1806
1807 done:
1808 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1809 }
1810
1811 /**
1812 * scic_controller_construct() - This method will attempt to construct a
1813 * controller object utilizing the supplied parameter information.
1814 * @c: This parameter specifies the controller to be constructed.
1815 * @scu_base: mapped base address of the scu registers
1816 * @smu_base: mapped base address of the smu registers
1817 *
1818 * Indicate if the controller was successfully constructed or if it failed in
1819 * some way. SCI_SUCCESS This value is returned if the controller was
1820 * successfully constructed. SCI_WARNING_TIMER_CONFLICT This value is returned
1821 * if the interrupt coalescence timer may cause SAS compliance issues for SMP
1822 * Target mode response processing. SCI_FAILURE_UNSUPPORTED_CONTROLLER_TYPE
1823 * This value is returned if the controller does not support the supplied type.
1824 * SCI_FAILURE_UNSUPPORTED_INIT_DATA_VERSION This value is returned if the
1825 * controller does not support the supplied initialization data version.
1826 */
1827 static enum sci_status scic_controller_construct(struct scic_sds_controller *scic,
1828 void __iomem *scu_base,
1829 void __iomem *smu_base)
1830 {
1831 struct isci_host *ihost = scic_to_ihost(scic);
1832 u8 i;
1833
1834 sci_base_state_machine_construct(&scic->state_machine,
1835 scic_sds_controller_state_table,
1836 SCI_BASE_CONTROLLER_STATE_INITIAL);
1837
1838 sci_base_state_machine_start(&scic->state_machine);
1839
1840 scic->scu_registers = scu_base;
1841 scic->smu_registers = smu_base;
1842
1843 scic_sds_port_configuration_agent_construct(&scic->port_agent);
1844
1845 /* Construct the ports for this controller */
1846 for (i = 0; i < SCI_MAX_PORTS; i++)
1847 scic_sds_port_construct(&ihost->ports[i].sci, i, scic);
1848 scic_sds_port_construct(&ihost->ports[i].sci, SCIC_SDS_DUMMY_PORT, scic);
1849
1850 /* Construct the phys for this controller */
1851 for (i = 0; i < SCI_MAX_PHYS; i++) {
1852 /* Add all the PHYs to the dummy port */
1853 scic_sds_phy_construct(&ihost->phys[i].sci,
1854 &ihost->ports[SCI_MAX_PORTS].sci, i);
1855 }
1856
1857 scic->invalid_phy_mask = 0;
1858
1859 sci_init_timer(&scic->timer, controller_timeout);
1860
1861 /* Set the default maximum values */
1862 scic->completion_event_entries = SCU_EVENT_COUNT;
1863 scic->completion_queue_entries = SCU_COMPLETION_QUEUE_COUNT;
1864 scic->remote_node_entries = SCI_MAX_REMOTE_DEVICES;
1865 scic->logical_port_entries = SCI_MAX_PORTS;
1866 scic->task_context_entries = SCU_IO_REQUEST_COUNT;
1867 scic->uf_control.buffers.count = SCU_UNSOLICITED_FRAME_COUNT;
1868 scic->uf_control.address_table.count = SCU_UNSOLICITED_FRAME_COUNT;
1869
1870 /* Initialize the User and OEM parameters to default values. */
1871 scic_sds_controller_set_default_config_parameters(scic);
1872
1873 return scic_controller_reset(scic);
1874 }
1875
1876 int scic_oem_parameters_validate(struct scic_sds_oem_params *oem)
1877 {
1878 int i;
1879
1880 for (i = 0; i < SCI_MAX_PORTS; i++)
1881 if (oem->ports[i].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX)
1882 return -EINVAL;
1883
1884 for (i = 0; i < SCI_MAX_PHYS; i++)
1885 if (oem->phys[i].sas_address.high == 0 &&
1886 oem->phys[i].sas_address.low == 0)
1887 return -EINVAL;
1888
1889 if (oem->controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) {
1890 for (i = 0; i < SCI_MAX_PHYS; i++)
1891 if (oem->ports[i].phy_mask != 0)
1892 return -EINVAL;
1893 } else if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
1894 u8 phy_mask = 0;
1895
1896 for (i = 0; i < SCI_MAX_PHYS; i++)
1897 phy_mask |= oem->ports[i].phy_mask;
1898
1899 if (phy_mask == 0)
1900 return -EINVAL;
1901 } else
1902 return -EINVAL;
1903
1904 if (oem->controller.max_concurrent_dev_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT)
1905 return -EINVAL;
1906
1907 return 0;
1908 }
1909
1910 static enum sci_status scic_oem_parameters_set(struct scic_sds_controller *scic,
1911 union scic_oem_parameters *scic_parms)
1912 {
1913 u32 state = scic->state_machine.current_state_id;
1914
1915 if (state == SCI_BASE_CONTROLLER_STATE_RESET ||
1916 state == SCI_BASE_CONTROLLER_STATE_INITIALIZING ||
1917 state == SCI_BASE_CONTROLLER_STATE_INITIALIZED) {
1918
1919 if (scic_oem_parameters_validate(&scic_parms->sds1))
1920 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1921 scic->oem_parameters.sds1 = scic_parms->sds1;
1922
1923 return SCI_SUCCESS;
1924 }
1925
1926 return SCI_FAILURE_INVALID_STATE;
1927 }
1928
1929 void scic_oem_parameters_get(
1930 struct scic_sds_controller *scic,
1931 union scic_oem_parameters *scic_parms)
1932 {
1933 memcpy(scic_parms, (&scic->oem_parameters), sizeof(*scic_parms));
1934 }
1935
1936 static void power_control_timeout(unsigned long data)
1937 {
1938 struct sci_timer *tmr = (struct sci_timer *)data;
1939 struct scic_sds_controller *scic = container_of(tmr, typeof(*scic), power_control.timer);
1940 struct isci_host *ihost = scic_to_ihost(scic);
1941 struct scic_sds_phy *sci_phy;
1942 unsigned long flags;
1943 u8 i;
1944
1945 spin_lock_irqsave(&ihost->scic_lock, flags);
1946
1947 if (tmr->cancel)
1948 goto done;
1949
1950 scic->power_control.phys_granted_power = 0;
1951
1952 if (scic->power_control.phys_waiting == 0) {
1953 scic->power_control.timer_started = false;
1954 goto done;
1955 }
1956
1957 for (i = 0; i < SCI_MAX_PHYS; i++) {
1958
1959 if (scic->power_control.phys_waiting == 0)
1960 break;
1961
1962 sci_phy = scic->power_control.requesters[i];
1963 if (sci_phy == NULL)
1964 continue;
1965
1966 if (scic->power_control.phys_granted_power >=
1967 scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up)
1968 break;
1969
1970 scic->power_control.requesters[i] = NULL;
1971 scic->power_control.phys_waiting--;
1972 scic->power_control.phys_granted_power++;
1973 scic_sds_phy_consume_power_handler(sci_phy);
1974 }
1975
1976 /*
1977 * It doesn't matter if the power list is empty, we need to start the
1978 * timer in case another phy becomes ready.
1979 */
1980 sci_mod_timer(tmr, SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1981 scic->power_control.timer_started = true;
1982
1983 done:
1984 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1985 }
1986
1987 /**
1988 * This method inserts the phy in the stagger spinup control queue.
1989 * @scic:
1990 *
1991 *
1992 */
1993 void scic_sds_controller_power_control_queue_insert(
1994 struct scic_sds_controller *scic,
1995 struct scic_sds_phy *sci_phy)
1996 {
1997 BUG_ON(sci_phy == NULL);
1998
1999 if (scic->power_control.phys_granted_power <
2000 scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up) {
2001 scic->power_control.phys_granted_power++;
2002 scic_sds_phy_consume_power_handler(sci_phy);
2003
2004 /*
2005 * stop and start the power_control timer. When the timer fires, the
2006 * no_of_phys_granted_power will be set to 0
2007 */
2008 if (scic->power_control.timer_started)
2009 sci_del_timer(&scic->power_control.timer);
2010
2011 sci_mod_timer(&scic->power_control.timer,
2012 SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
2013 scic->power_control.timer_started = true;
2014
2015 } else {
2016 /* Add the phy in the waiting list */
2017 scic->power_control.requesters[sci_phy->phy_index] = sci_phy;
2018 scic->power_control.phys_waiting++;
2019 }
2020 }
2021
2022 /**
2023 * This method removes the phy from the stagger spinup control queue.
2024 * @scic:
2025 *
2026 *
2027 */
2028 void scic_sds_controller_power_control_queue_remove(
2029 struct scic_sds_controller *scic,
2030 struct scic_sds_phy *sci_phy)
2031 {
2032 BUG_ON(sci_phy == NULL);
2033
2034 if (scic->power_control.requesters[sci_phy->phy_index] != NULL) {
2035 scic->power_control.phys_waiting--;
2036 }
2037
2038 scic->power_control.requesters[sci_phy->phy_index] = NULL;
2039 }
2040
2041 #define AFE_REGISTER_WRITE_DELAY 10
2042
2043 /* Initialize the AFE for this phy index. We need to read the AFE setup from
2044 * the OEM parameters
2045 */
2046 static void scic_sds_controller_afe_initialization(struct scic_sds_controller *scic)
2047 {
2048 const struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1;
2049 u32 afe_status;
2050 u32 phy_id;
2051
2052 /* Clear DFX Status registers */
2053 writel(0x0081000f, &scic->scu_registers->afe.afe_dfx_master_control0);
2054 udelay(AFE_REGISTER_WRITE_DELAY);
2055
2056 if (is_b0()) {
2057 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
2058 * Timer, PM Stagger Timer */
2059 writel(0x0007BFFF, &scic->scu_registers->afe.afe_pmsn_master_control2);
2060 udelay(AFE_REGISTER_WRITE_DELAY);
2061 }
2062
2063 /* Configure bias currents to normal */
2064 if (is_a0())
2065 writel(0x00005500, &scic->scu_registers->afe.afe_bias_control);
2066 else if (is_a2())
2067 writel(0x00005A00, &scic->scu_registers->afe.afe_bias_control);
2068 else if (is_b0())
2069 writel(0x00005F00, &scic->scu_registers->afe.afe_bias_control);
2070
2071 udelay(AFE_REGISTER_WRITE_DELAY);
2072
2073 /* Enable PLL */
2074 if (is_b0())
2075 writel(0x80040A08, &scic->scu_registers->afe.afe_pll_control0);
2076 else
2077 writel(0x80040908, &scic->scu_registers->afe.afe_pll_control0);
2078
2079 udelay(AFE_REGISTER_WRITE_DELAY);
2080
2081 /* Wait for the PLL to lock */
2082 do {
2083 afe_status = readl(&scic->scu_registers->afe.afe_common_block_status);
2084 udelay(AFE_REGISTER_WRITE_DELAY);
2085 } while ((afe_status & 0x00001000) == 0);
2086
2087 if (is_a0() || is_a2()) {
2088 /* Shorten SAS SNW lock time (RxLock timer value from 76 us to 50 us) */
2089 writel(0x7bcc96ad, &scic->scu_registers->afe.afe_pmsn_master_control0);
2090 udelay(AFE_REGISTER_WRITE_DELAY);
2091 }
2092
2093 for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
2094 const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
2095
2096 if (is_b0()) {
2097 /* Configure transmitter SSC parameters */
2098 writel(0x00030000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control);
2099 udelay(AFE_REGISTER_WRITE_DELAY);
2100 } else {
2101 /*
2102 * All defaults, except the Receive Word Alignament/Comma Detect
2103 * Enable....(0xe800) */
2104 writel(0x00004512, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
2105 udelay(AFE_REGISTER_WRITE_DELAY);
2106
2107 writel(0x0050100F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control1);
2108 udelay(AFE_REGISTER_WRITE_DELAY);
2109 }
2110
2111 /*
2112 * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
2113 * & increase TX int & ext bias 20%....(0xe85c) */
2114 if (is_a0())
2115 writel(0x000003D4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2116 else if (is_a2())
2117 writel(0x000003F0, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2118 else {
2119 /* Power down TX and RX (PWRDNTX and PWRDNRX) */
2120 writel(0x000003d7, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2121 udelay(AFE_REGISTER_WRITE_DELAY);
2122
2123 /*
2124 * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
2125 * & increase TX int & ext bias 20%....(0xe85c) */
2126 writel(0x000003d4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2127 }
2128 udelay(AFE_REGISTER_WRITE_DELAY);
2129
2130 if (is_a0() || is_a2()) {
2131 /* Enable TX equalization (0xe824) */
2132 writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
2133 udelay(AFE_REGISTER_WRITE_DELAY);
2134 }
2135
2136 /*
2137 * RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0, TPD=0x0(TX Power On),
2138 * RDD=0x0(RX Detect Enabled) ....(0xe800) */
2139 writel(0x00004100, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
2140 udelay(AFE_REGISTER_WRITE_DELAY);
2141
2142 /* Leave DFE/FFE on */
2143 if (is_a0())
2144 writel(0x3F09983F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2145 else if (is_a2())
2146 writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2147 else {
2148 writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2149 udelay(AFE_REGISTER_WRITE_DELAY);
2150 /* Enable TX equalization (0xe824) */
2151 writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
2152 }
2153 udelay(AFE_REGISTER_WRITE_DELAY);
2154
2155 writel(oem_phy->afe_tx_amp_control0,
2156 &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control0);
2157 udelay(AFE_REGISTER_WRITE_DELAY);
2158
2159 writel(oem_phy->afe_tx_amp_control1,
2160 &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control1);
2161 udelay(AFE_REGISTER_WRITE_DELAY);
2162
2163 writel(oem_phy->afe_tx_amp_control2,
2164 &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control2);
2165 udelay(AFE_REGISTER_WRITE_DELAY);
2166
2167 writel(oem_phy->afe_tx_amp_control3,
2168 &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control3);
2169 udelay(AFE_REGISTER_WRITE_DELAY);
2170 }
2171
2172 /* Transfer control to the PEs */
2173 writel(0x00010f00, &scic->scu_registers->afe.afe_dfx_master_control0);
2174 udelay(AFE_REGISTER_WRITE_DELAY);
2175 }
2176
2177 static enum sci_status scic_controller_set_mode(struct scic_sds_controller *scic,
2178 enum sci_controller_mode operating_mode)
2179 {
2180 enum sci_status status = SCI_SUCCESS;
2181
2182 if ((scic->state_machine.current_state_id ==
2183 SCI_BASE_CONTROLLER_STATE_INITIALIZING) ||
2184 (scic->state_machine.current_state_id ==
2185 SCI_BASE_CONTROLLER_STATE_INITIALIZED)) {
2186 switch (operating_mode) {
2187 case SCI_MODE_SPEED:
2188 scic->remote_node_entries = SCI_MAX_REMOTE_DEVICES;
2189 scic->task_context_entries = SCU_IO_REQUEST_COUNT;
2190 scic->uf_control.buffers.count =
2191 SCU_UNSOLICITED_FRAME_COUNT;
2192 scic->completion_event_entries = SCU_EVENT_COUNT;
2193 scic->completion_queue_entries =
2194 SCU_COMPLETION_QUEUE_COUNT;
2195 break;
2196
2197 case SCI_MODE_SIZE:
2198 scic->remote_node_entries = SCI_MIN_REMOTE_DEVICES;
2199 scic->task_context_entries = SCI_MIN_IO_REQUESTS;
2200 scic->uf_control.buffers.count =
2201 SCU_MIN_UNSOLICITED_FRAMES;
2202 scic->completion_event_entries = SCU_MIN_EVENTS;
2203 scic->completion_queue_entries =
2204 SCU_MIN_COMPLETION_QUEUE_ENTRIES;
2205 break;
2206
2207 default:
2208 status = SCI_FAILURE_INVALID_PARAMETER_VALUE;
2209 break;
2210 }
2211 } else
2212 status = SCI_FAILURE_INVALID_STATE;
2213
2214 return status;
2215 }
2216
2217 static void scic_sds_controller_initialize_power_control(struct scic_sds_controller *scic)
2218 {
2219 sci_init_timer(&scic->power_control.timer, power_control_timeout);
2220
2221 memset(scic->power_control.requesters, 0,
2222 sizeof(scic->power_control.requesters));
2223
2224 scic->power_control.phys_waiting = 0;
2225 scic->power_control.phys_granted_power = 0;
2226 }
2227
2228 static enum sci_status scic_controller_initialize(struct scic_sds_controller *scic)
2229 {
2230 struct sci_base_state_machine *sm = &scic->state_machine;
2231 enum sci_status result = SCI_SUCCESS;
2232 struct isci_host *ihost = scic_to_ihost(scic);
2233 u32 index, state;
2234
2235 if (scic->state_machine.current_state_id !=
2236 SCI_BASE_CONTROLLER_STATE_RESET) {
2237 dev_warn(scic_to_dev(scic),
2238 "SCIC Controller initialize operation requested "
2239 "in invalid state\n");
2240 return SCI_FAILURE_INVALID_STATE;
2241 }
2242
2243 sci_base_state_machine_change_state(sm, SCI_BASE_CONTROLLER_STATE_INITIALIZING);
2244
2245 sci_init_timer(&scic->phy_timer, phy_startup_timeout);
2246
2247 scic->next_phy_to_start = 0;
2248 scic->phy_startup_timer_pending = false;
2249
2250 scic_sds_controller_initialize_power_control(scic);
2251
2252 /*
2253 * There is nothing to do here for B0 since we do not have to
2254 * program the AFE registers.
2255 * / @todo The AFE settings are supposed to be correct for the B0 but
2256 * / presently they seem to be wrong. */
2257 scic_sds_controller_afe_initialization(scic);
2258
2259 if (result == SCI_SUCCESS) {
2260 u32 status;
2261 u32 terminate_loop;
2262
2263 /* Take the hardware out of reset */
2264 writel(0, &scic->smu_registers->soft_reset_control);
2265
2266 /*
2267 * / @todo Provide meaningfull error code for hardware failure
2268 * result = SCI_FAILURE_CONTROLLER_HARDWARE; */
2269 result = SCI_FAILURE;
2270 terminate_loop = 100;
2271
2272 while (terminate_loop-- && (result != SCI_SUCCESS)) {
2273 /* Loop until the hardware reports success */
2274 udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME);
2275 status = readl(&scic->smu_registers->control_status);
2276
2277 if ((status & SCU_RAM_INIT_COMPLETED) ==
2278 SCU_RAM_INIT_COMPLETED)
2279 result = SCI_SUCCESS;
2280 }
2281 }
2282
2283 if (result == SCI_SUCCESS) {
2284 u32 max_supported_ports;
2285 u32 max_supported_devices;
2286 u32 max_supported_io_requests;
2287 u32 device_context_capacity;
2288
2289 /*
2290 * Determine what are the actaul device capacities that the
2291 * hardware will support */
2292 device_context_capacity =
2293 readl(&scic->smu_registers->device_context_capacity);
2294
2295
2296 max_supported_ports = smu_dcc_get_max_ports(device_context_capacity);
2297 max_supported_devices = smu_dcc_get_max_remote_node_context(device_context_capacity);
2298 max_supported_io_requests = smu_dcc_get_max_task_context(device_context_capacity);
2299
2300 /*
2301 * Make all PEs that are unassigned match up with the
2302 * logical ports
2303 */
2304 for (index = 0; index < max_supported_ports; index++) {
2305 struct scu_port_task_scheduler_group_registers __iomem
2306 *ptsg = &scic->scu_registers->peg0.ptsg;
2307
2308 writel(index, &ptsg->protocol_engine[index]);
2309 }
2310
2311 /* Record the smaller of the two capacity values */
2312 scic->logical_port_entries =
2313 min(max_supported_ports, scic->logical_port_entries);
2314
2315 scic->task_context_entries =
2316 min(max_supported_io_requests,
2317 scic->task_context_entries);
2318
2319 scic->remote_node_entries =
2320 min(max_supported_devices, scic->remote_node_entries);
2321
2322 /*
2323 * Now that we have the correct hardware reported minimum values
2324 * build the MDL for the controller. Default to a performance
2325 * configuration.
2326 */
2327 scic_controller_set_mode(scic, SCI_MODE_SPEED);
2328 }
2329
2330 /* Initialize hardware PCI Relaxed ordering in DMA engines */
2331 if (result == SCI_SUCCESS) {
2332 u32 dma_configuration;
2333
2334 /* Configure the payload DMA */
2335 dma_configuration =
2336 readl(&scic->scu_registers->sdma.pdma_configuration);
2337 dma_configuration |=
2338 SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2339 writel(dma_configuration,
2340 &scic->scu_registers->sdma.pdma_configuration);
2341
2342 /* Configure the control DMA */
2343 dma_configuration =
2344 readl(&scic->scu_registers->sdma.cdma_configuration);
2345 dma_configuration |=
2346 SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2347 writel(dma_configuration,
2348 &scic->scu_registers->sdma.cdma_configuration);
2349 }
2350
2351 /*
2352 * Initialize the PHYs before the PORTs because the PHY registers
2353 * are accessed during the port initialization.
2354 */
2355 if (result == SCI_SUCCESS) {
2356 /* Initialize the phys */
2357 for (index = 0;
2358 (result == SCI_SUCCESS) && (index < SCI_MAX_PHYS);
2359 index++) {
2360 result = scic_sds_phy_initialize(
2361 &ihost->phys[index].sci,
2362 &scic->scu_registers->peg0.pe[index].tl,
2363 &scic->scu_registers->peg0.pe[index].ll);
2364 }
2365 }
2366
2367 if (result == SCI_SUCCESS) {
2368 /* Initialize the logical ports */
2369 for (index = 0;
2370 (index < scic->logical_port_entries) &&
2371 (result == SCI_SUCCESS);
2372 index++) {
2373 result = scic_sds_port_initialize(
2374 &ihost->ports[index].sci,
2375 &scic->scu_registers->peg0.ptsg.port[index],
2376 &scic->scu_registers->peg0.ptsg.protocol_engine,
2377 &scic->scu_registers->peg0.viit[index]);
2378 }
2379 }
2380
2381 if (result == SCI_SUCCESS)
2382 result = scic_sds_port_configuration_agent_initialize(
2383 scic,
2384 &scic->port_agent);
2385
2386 /* Advance the controller state machine */
2387 if (result == SCI_SUCCESS)
2388 state = SCI_BASE_CONTROLLER_STATE_INITIALIZED;
2389 else
2390 state = SCI_BASE_CONTROLLER_STATE_FAILED;
2391 sci_base_state_machine_change_state(sm, state);
2392
2393 return result;
2394 }
2395
2396 static enum sci_status scic_user_parameters_set(
2397 struct scic_sds_controller *scic,
2398 union scic_user_parameters *scic_parms)
2399 {
2400 u32 state = scic->state_machine.current_state_id;
2401
2402 if (state == SCI_BASE_CONTROLLER_STATE_RESET ||
2403 state == SCI_BASE_CONTROLLER_STATE_INITIALIZING ||
2404 state == SCI_BASE_CONTROLLER_STATE_INITIALIZED) {
2405 u16 index;
2406
2407 /*
2408 * Validate the user parameters. If they are not legal, then
2409 * return a failure.
2410 */
2411 for (index = 0; index < SCI_MAX_PHYS; index++) {
2412 struct sci_phy_user_params *user_phy;
2413
2414 user_phy = &scic_parms->sds1.phys[index];
2415
2416 if (!((user_phy->max_speed_generation <=
2417 SCIC_SDS_PARM_MAX_SPEED) &&
2418 (user_phy->max_speed_generation >
2419 SCIC_SDS_PARM_NO_SPEED)))
2420 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2421
2422 if (user_phy->in_connection_align_insertion_frequency <
2423 3)
2424 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2425
2426 if ((user_phy->in_connection_align_insertion_frequency <
2427 3) ||
2428 (user_phy->align_insertion_frequency == 0) ||
2429 (user_phy->
2430 notify_enable_spin_up_insertion_frequency ==
2431 0))
2432 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2433 }
2434
2435 if ((scic_parms->sds1.stp_inactivity_timeout == 0) ||
2436 (scic_parms->sds1.ssp_inactivity_timeout == 0) ||
2437 (scic_parms->sds1.stp_max_occupancy_timeout == 0) ||
2438 (scic_parms->sds1.ssp_max_occupancy_timeout == 0) ||
2439 (scic_parms->sds1.no_outbound_task_timeout == 0))
2440 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2441
2442 memcpy(&scic->user_parameters, scic_parms, sizeof(*scic_parms));
2443
2444 return SCI_SUCCESS;
2445 }
2446
2447 return SCI_FAILURE_INVALID_STATE;
2448 }
2449
2450 static int scic_controller_mem_init(struct scic_sds_controller *scic)
2451 {
2452 struct device *dev = scic_to_dev(scic);
2453 dma_addr_t dma_handle;
2454 enum sci_status result;
2455
2456 scic->completion_queue = dmam_alloc_coherent(dev,
2457 scic->completion_queue_entries * sizeof(u32),
2458 &dma_handle, GFP_KERNEL);
2459 if (!scic->completion_queue)
2460 return -ENOMEM;
2461
2462 writel(lower_32_bits(dma_handle),
2463 &scic->smu_registers->completion_queue_lower);
2464 writel(upper_32_bits(dma_handle),
2465 &scic->smu_registers->completion_queue_upper);
2466
2467 scic->remote_node_context_table = dmam_alloc_coherent(dev,
2468 scic->remote_node_entries *
2469 sizeof(union scu_remote_node_context),
2470 &dma_handle, GFP_KERNEL);
2471 if (!scic->remote_node_context_table)
2472 return -ENOMEM;
2473
2474 writel(lower_32_bits(dma_handle),
2475 &scic->smu_registers->remote_node_context_lower);
2476 writel(upper_32_bits(dma_handle),
2477 &scic->smu_registers->remote_node_context_upper);
2478
2479 scic->task_context_table = dmam_alloc_coherent(dev,
2480 scic->task_context_entries *
2481 sizeof(struct scu_task_context),
2482 &dma_handle, GFP_KERNEL);
2483 if (!scic->task_context_table)
2484 return -ENOMEM;
2485
2486 writel(lower_32_bits(dma_handle),
2487 &scic->smu_registers->host_task_table_lower);
2488 writel(upper_32_bits(dma_handle),
2489 &scic->smu_registers->host_task_table_upper);
2490
2491 result = scic_sds_unsolicited_frame_control_construct(scic);
2492 if (result)
2493 return result;
2494
2495 /*
2496 * Inform the silicon as to the location of the UF headers and
2497 * address table.
2498 */
2499 writel(lower_32_bits(scic->uf_control.headers.physical_address),
2500 &scic->scu_registers->sdma.uf_header_base_address_lower);
2501 writel(upper_32_bits(scic->uf_control.headers.physical_address),
2502 &scic->scu_registers->sdma.uf_header_base_address_upper);
2503
2504 writel(lower_32_bits(scic->uf_control.address_table.physical_address),
2505 &scic->scu_registers->sdma.uf_address_table_lower);
2506 writel(upper_32_bits(scic->uf_control.address_table.physical_address),
2507 &scic->scu_registers->sdma.uf_address_table_upper);
2508
2509 return 0;
2510 }
2511
2512 int isci_host_init(struct isci_host *isci_host)
2513 {
2514 int err = 0, i;
2515 enum sci_status status;
2516 union scic_oem_parameters oem;
2517 union scic_user_parameters scic_user_params;
2518 struct isci_pci_info *pci_info = to_pci_info(isci_host->pdev);
2519
2520 isci_timer_list_construct(isci_host);
2521
2522 spin_lock_init(&isci_host->state_lock);
2523 spin_lock_init(&isci_host->scic_lock);
2524 spin_lock_init(&isci_host->queue_lock);
2525 init_waitqueue_head(&isci_host->eventq);
2526
2527 isci_host_change_state(isci_host, isci_starting);
2528 isci_host->can_queue = ISCI_CAN_QUEUE_VAL;
2529
2530 status = scic_controller_construct(&isci_host->sci, scu_base(isci_host),
2531 smu_base(isci_host));
2532
2533 if (status != SCI_SUCCESS) {
2534 dev_err(&isci_host->pdev->dev,
2535 "%s: scic_controller_construct failed - status = %x\n",
2536 __func__,
2537 status);
2538 return -ENODEV;
2539 }
2540
2541 isci_host->sas_ha.dev = &isci_host->pdev->dev;
2542 isci_host->sas_ha.lldd_ha = isci_host;
2543
2544 /*
2545 * grab initial values stored in the controller object for OEM and USER
2546 * parameters
2547 */
2548 isci_user_parameters_get(isci_host, &scic_user_params);
2549 status = scic_user_parameters_set(&isci_host->sci,
2550 &scic_user_params);
2551 if (status != SCI_SUCCESS) {
2552 dev_warn(&isci_host->pdev->dev,
2553 "%s: scic_user_parameters_set failed\n",
2554 __func__);
2555 return -ENODEV;
2556 }
2557
2558 scic_oem_parameters_get(&isci_host->sci, &oem);
2559
2560 /* grab any OEM parameters specified in orom */
2561 if (pci_info->orom) {
2562 status = isci_parse_oem_parameters(&oem,
2563 pci_info->orom,
2564 isci_host->id);
2565 if (status != SCI_SUCCESS) {
2566 dev_warn(&isci_host->pdev->dev,
2567 "parsing firmware oem parameters failed\n");
2568 return -EINVAL;
2569 }
2570 }
2571
2572 status = scic_oem_parameters_set(&isci_host->sci, &oem);
2573 if (status != SCI_SUCCESS) {
2574 dev_warn(&isci_host->pdev->dev,
2575 "%s: scic_oem_parameters_set failed\n",
2576 __func__);
2577 return -ENODEV;
2578 }
2579
2580 tasklet_init(&isci_host->completion_tasklet,
2581 isci_host_completion_routine, (unsigned long)isci_host);
2582
2583 INIT_LIST_HEAD(&isci_host->requests_to_complete);
2584 INIT_LIST_HEAD(&isci_host->requests_to_errorback);
2585
2586 spin_lock_irq(&isci_host->scic_lock);
2587 status = scic_controller_initialize(&isci_host->sci);
2588 spin_unlock_irq(&isci_host->scic_lock);
2589 if (status != SCI_SUCCESS) {
2590 dev_warn(&isci_host->pdev->dev,
2591 "%s: scic_controller_initialize failed -"
2592 " status = 0x%x\n",
2593 __func__, status);
2594 return -ENODEV;
2595 }
2596
2597 err = scic_controller_mem_init(&isci_host->sci);
2598 if (err)
2599 return err;
2600
2601 isci_host->dma_pool = dmam_pool_create(DRV_NAME, &isci_host->pdev->dev,
2602 sizeof(struct isci_request),
2603 SLAB_HWCACHE_ALIGN, 0);
2604
2605 if (!isci_host->dma_pool)
2606 return -ENOMEM;
2607
2608 for (i = 0; i < SCI_MAX_PORTS; i++)
2609 isci_port_init(&isci_host->ports[i], isci_host, i);
2610
2611 for (i = 0; i < SCI_MAX_PHYS; i++)
2612 isci_phy_init(&isci_host->phys[i], isci_host, i);
2613
2614 for (i = 0; i < SCI_MAX_REMOTE_DEVICES; i++) {
2615 struct isci_remote_device *idev = &isci_host->devices[i];
2616
2617 INIT_LIST_HEAD(&idev->reqs_in_process);
2618 INIT_LIST_HEAD(&idev->node);
2619 spin_lock_init(&idev->state_lock);
2620 }
2621
2622 return 0;
2623 }
2624
2625 void scic_sds_controller_link_up(struct scic_sds_controller *scic,
2626 struct scic_sds_port *port, struct scic_sds_phy *phy)
2627 {
2628 switch (scic->state_machine.current_state_id) {
2629 case SCI_BASE_CONTROLLER_STATE_STARTING:
2630 sci_del_timer(&scic->phy_timer);
2631 scic->phy_startup_timer_pending = false;
2632 scic->port_agent.link_up_handler(scic, &scic->port_agent,
2633 port, phy);
2634 scic_sds_controller_start_next_phy(scic);
2635 break;
2636 case SCI_BASE_CONTROLLER_STATE_READY:
2637 scic->port_agent.link_up_handler(scic, &scic->port_agent,
2638 port, phy);
2639 break;
2640 default:
2641 dev_dbg(scic_to_dev(scic),
2642 "%s: SCIC Controller linkup event from phy %d in "
2643 "unexpected state %d\n", __func__, phy->phy_index,
2644 scic->state_machine.current_state_id);
2645 }
2646 }
2647
2648 void scic_sds_controller_link_down(struct scic_sds_controller *scic,
2649 struct scic_sds_port *port, struct scic_sds_phy *phy)
2650 {
2651 switch (scic->state_machine.current_state_id) {
2652 case SCI_BASE_CONTROLLER_STATE_STARTING:
2653 case SCI_BASE_CONTROLLER_STATE_READY:
2654 scic->port_agent.link_down_handler(scic, &scic->port_agent,
2655 port, phy);
2656 break;
2657 default:
2658 dev_dbg(scic_to_dev(scic),
2659 "%s: SCIC Controller linkdown event from phy %d in "
2660 "unexpected state %d\n",
2661 __func__,
2662 phy->phy_index,
2663 scic->state_machine.current_state_id);
2664 }
2665 }
2666
2667 /**
2668 * This is a helper method to determine if any remote devices on this
2669 * controller are still in the stopping state.
2670 *
2671 */
2672 static bool scic_sds_controller_has_remote_devices_stopping(
2673 struct scic_sds_controller *controller)
2674 {
2675 u32 index;
2676
2677 for (index = 0; index < controller->remote_node_entries; index++) {
2678 if ((controller->device_table[index] != NULL) &&
2679 (controller->device_table[index]->state_machine.current_state_id
2680 == SCI_BASE_REMOTE_DEVICE_STATE_STOPPING))
2681 return true;
2682 }
2683
2684 return false;
2685 }
2686
2687 /**
2688 * This method is called by the remote device to inform the controller
2689 * object that the remote device has stopped.
2690 */
2691 void scic_sds_controller_remote_device_stopped(struct scic_sds_controller *scic,
2692 struct scic_sds_remote_device *sci_dev)
2693 {
2694 if (scic->state_machine.current_state_id !=
2695 SCI_BASE_CONTROLLER_STATE_STOPPING) {
2696 dev_dbg(scic_to_dev(scic),
2697 "SCIC Controller 0x%p remote device stopped event "
2698 "from device 0x%p in unexpected state %d\n",
2699 scic, sci_dev,
2700 scic->state_machine.current_state_id);
2701 return;
2702 }
2703
2704 if (!scic_sds_controller_has_remote_devices_stopping(scic)) {
2705 sci_base_state_machine_change_state(&scic->state_machine,
2706 SCI_BASE_CONTROLLER_STATE_STOPPED);
2707 }
2708 }
2709
2710 /**
2711 * This method will write to the SCU PCP register the request value. The method
2712 * is used to suspend/resume ports, devices, and phys.
2713 * @scic:
2714 *
2715 *
2716 */
2717 void scic_sds_controller_post_request(
2718 struct scic_sds_controller *scic,
2719 u32 request)
2720 {
2721 dev_dbg(scic_to_dev(scic),
2722 "%s: SCIC Controller 0x%p post request 0x%08x\n",
2723 __func__,
2724 scic,
2725 request);
2726
2727 writel(request, &scic->smu_registers->post_context_port);
2728 }
2729
2730 /**
2731 * This method will copy the soft copy of the task context into the physical
2732 * memory accessible by the controller.
2733 * @scic: This parameter specifies the controller for which to copy
2734 * the task context.
2735 * @sci_req: This parameter specifies the request for which the task
2736 * context is being copied.
2737 *
2738 * After this call is made the SCIC_SDS_IO_REQUEST object will always point to
2739 * the physical memory version of the task context. Thus, all subsequent
2740 * updates to the task context are performed in the TC table (i.e. DMAable
2741 * memory). none
2742 */
2743 void scic_sds_controller_copy_task_context(
2744 struct scic_sds_controller *scic,
2745 struct scic_sds_request *sci_req)
2746 {
2747 struct scu_task_context *task_context_buffer;
2748
2749 task_context_buffer = scic_sds_controller_get_task_context_buffer(
2750 scic, sci_req->io_tag);
2751
2752 memcpy(task_context_buffer,
2753 sci_req->task_context_buffer,
2754 offsetof(struct scu_task_context, sgl_snapshot_ac));
2755
2756 /*
2757 * Now that the soft copy of the TC has been copied into the TC
2758 * table accessible by the silicon. Thus, any further changes to
2759 * the TC (e.g. TC termination) occur in the appropriate location. */
2760 sci_req->task_context_buffer = task_context_buffer;
2761 }
2762
2763 /**
2764 * This method returns the task context buffer for the given io tag.
2765 * @scic:
2766 * @io_tag:
2767 *
2768 * struct scu_task_context*
2769 */
2770 struct scu_task_context *scic_sds_controller_get_task_context_buffer(
2771 struct scic_sds_controller *scic,
2772 u16 io_tag
2773 ) {
2774 u16 task_index = scic_sds_io_tag_get_index(io_tag);
2775
2776 if (task_index < scic->task_context_entries) {
2777 return &scic->task_context_table[task_index];
2778 }
2779
2780 return NULL;
2781 }
2782
2783 struct scic_sds_request *scic_request_by_tag(struct scic_sds_controller *scic,
2784 u16 io_tag)
2785 {
2786 u16 task_index;
2787 u16 task_sequence;
2788
2789 task_index = scic_sds_io_tag_get_index(io_tag);
2790
2791 if (task_index < scic->task_context_entries) {
2792 if (scic->io_request_table[task_index] != NULL) {
2793 task_sequence = scic_sds_io_tag_get_sequence(io_tag);
2794
2795 if (task_sequence == scic->io_request_sequence[task_index]) {
2796 return scic->io_request_table[task_index];
2797 }
2798 }
2799 }
2800
2801 return NULL;
2802 }
2803
2804 /**
2805 * This method allocates remote node index and the reserves the remote node
2806 * context space for use. This method can fail if there are no more remote
2807 * node index available.
2808 * @scic: This is the controller object which contains the set of
2809 * free remote node ids
2810 * @sci_dev: This is the device object which is requesting the a remote node
2811 * id
2812 * @node_id: This is the remote node id that is assinged to the device if one
2813 * is available
2814 *
2815 * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote
2816 * node index available.
2817 */
2818 enum sci_status scic_sds_controller_allocate_remote_node_context(
2819 struct scic_sds_controller *scic,
2820 struct scic_sds_remote_device *sci_dev,
2821 u16 *node_id)
2822 {
2823 u16 node_index;
2824 u32 remote_node_count = scic_sds_remote_device_node_count(sci_dev);
2825
2826 node_index = scic_sds_remote_node_table_allocate_remote_node(
2827 &scic->available_remote_nodes, remote_node_count
2828 );
2829
2830 if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
2831 scic->device_table[node_index] = sci_dev;
2832
2833 *node_id = node_index;
2834
2835 return SCI_SUCCESS;
2836 }
2837
2838 return SCI_FAILURE_INSUFFICIENT_RESOURCES;
2839 }
2840
2841 /**
2842 * This method frees the remote node index back to the available pool. Once
2843 * this is done the remote node context buffer is no longer valid and can
2844 * not be used.
2845 * @scic:
2846 * @sci_dev:
2847 * @node_id:
2848 *
2849 */
2850 void scic_sds_controller_free_remote_node_context(
2851 struct scic_sds_controller *scic,
2852 struct scic_sds_remote_device *sci_dev,
2853 u16 node_id)
2854 {
2855 u32 remote_node_count = scic_sds_remote_device_node_count(sci_dev);
2856
2857 if (scic->device_table[node_id] == sci_dev) {
2858 scic->device_table[node_id] = NULL;
2859
2860 scic_sds_remote_node_table_release_remote_node_index(
2861 &scic->available_remote_nodes, remote_node_count, node_id
2862 );
2863 }
2864 }
2865
2866 /**
2867 * This method returns the union scu_remote_node_context for the specified remote
2868 * node id.
2869 * @scic:
2870 * @node_id:
2871 *
2872 * union scu_remote_node_context*
2873 */
2874 union scu_remote_node_context *scic_sds_controller_get_remote_node_context_buffer(
2875 struct scic_sds_controller *scic,
2876 u16 node_id
2877 ) {
2878 if (
2879 (node_id < scic->remote_node_entries)
2880 && (scic->device_table[node_id] != NULL)
2881 ) {
2882 return &scic->remote_node_context_table[node_id];
2883 }
2884
2885 return NULL;
2886 }
2887
2888 /**
2889 *
2890 * @resposne_buffer: This is the buffer into which the D2H register FIS will be
2891 * constructed.
2892 * @frame_header: This is the frame header returned by the hardware.
2893 * @frame_buffer: This is the frame buffer returned by the hardware.
2894 *
2895 * This method will combind the frame header and frame buffer to create a SATA
2896 * D2H register FIS none
2897 */
2898 void scic_sds_controller_copy_sata_response(
2899 void *response_buffer,
2900 void *frame_header,
2901 void *frame_buffer)
2902 {
2903 memcpy(response_buffer, frame_header, sizeof(u32));
2904
2905 memcpy(response_buffer + sizeof(u32),
2906 frame_buffer,
2907 sizeof(struct dev_to_host_fis) - sizeof(u32));
2908 }
2909
2910 /**
2911 * This method releases the frame once this is done the frame is available for
2912 * re-use by the hardware. The data contained in the frame header and frame
2913 * buffer is no longer valid. The UF queue get pointer is only updated if UF
2914 * control indicates this is appropriate.
2915 * @scic:
2916 * @frame_index:
2917 *
2918 */
2919 void scic_sds_controller_release_frame(
2920 struct scic_sds_controller *scic,
2921 u32 frame_index)
2922 {
2923 if (scic_sds_unsolicited_frame_control_release_frame(
2924 &scic->uf_control, frame_index) == true)
2925 writel(scic->uf_control.get,
2926 &scic->scu_registers->sdma.unsolicited_frame_get_pointer);
2927 }
2928
2929 /**
2930 * scic_controller_start_io() - This method is called by the SCI user to
2931 * send/start an IO request. If the method invocation is successful, then
2932 * the IO request has been queued to the hardware for processing.
2933 * @controller: the handle to the controller object for which to start an IO
2934 * request.
2935 * @remote_device: the handle to the remote device object for which to start an
2936 * IO request.
2937 * @io_request: the handle to the io request object to start.
2938 * @io_tag: This parameter specifies a previously allocated IO tag that the
2939 * user desires to be utilized for this request. This parameter is optional.
2940 * The user is allowed to supply SCI_CONTROLLER_INVALID_IO_TAG as the value
2941 * for this parameter.
2942 *
2943 * - IO tags are a protected resource. It is incumbent upon the SCI Core user
2944 * to ensure that each of the methods that may allocate or free available IO
2945 * tags are handled in a mutually exclusive manner. This method is one of said
2946 * methods requiring proper critical code section protection (e.g. semaphore,
2947 * spin-lock, etc.). - For SATA, the user is required to manage NCQ tags. As a
2948 * result, it is expected the user will have set the NCQ tag field in the host
2949 * to device register FIS prior to calling this method. There is also a
2950 * requirement for the user to call scic_stp_io_set_ncq_tag() prior to invoking
2951 * the scic_controller_start_io() method. scic_controller_allocate_tag() for
2952 * more information on allocating a tag. Indicate if the controller
2953 * successfully started the IO request. SCI_SUCCESS if the IO request was
2954 * successfully started. Determine the failure situations and return values.
2955 */
2956 enum sci_status scic_controller_start_io(
2957 struct scic_sds_controller *scic,
2958 struct scic_sds_remote_device *rdev,
2959 struct scic_sds_request *req,
2960 u16 io_tag)
2961 {
2962 enum sci_status status;
2963
2964 if (scic->state_machine.current_state_id !=
2965 SCI_BASE_CONTROLLER_STATE_READY) {
2966 dev_warn(scic_to_dev(scic), "invalid state to start I/O");
2967 return SCI_FAILURE_INVALID_STATE;
2968 }
2969
2970 status = scic_sds_remote_device_start_io(scic, rdev, req);
2971 if (status != SCI_SUCCESS)
2972 return status;
2973
2974 scic->io_request_table[scic_sds_io_tag_get_index(req->io_tag)] = req;
2975 scic_sds_controller_post_request(scic, scic_sds_request_get_post_context(req));
2976 return SCI_SUCCESS;
2977 }
2978
2979 /**
2980 * scic_controller_terminate_request() - This method is called by the SCI Core
2981 * user to terminate an ongoing (i.e. started) core IO request. This does
2982 * not abort the IO request at the target, but rather removes the IO request
2983 * from the host controller.
2984 * @controller: the handle to the controller object for which to terminate a
2985 * request.
2986 * @remote_device: the handle to the remote device object for which to
2987 * terminate a request.
2988 * @request: the handle to the io or task management request object to
2989 * terminate.
2990 *
2991 * Indicate if the controller successfully began the terminate process for the
2992 * IO request. SCI_SUCCESS if the terminate process was successfully started
2993 * for the request. Determine the failure situations and return values.
2994 */
2995 enum sci_status scic_controller_terminate_request(
2996 struct scic_sds_controller *scic,
2997 struct scic_sds_remote_device *rdev,
2998 struct scic_sds_request *req)
2999 {
3000 enum sci_status status;
3001
3002 if (scic->state_machine.current_state_id !=
3003 SCI_BASE_CONTROLLER_STATE_READY) {
3004 dev_warn(scic_to_dev(scic),
3005 "invalid state to terminate request\n");
3006 return SCI_FAILURE_INVALID_STATE;
3007 }
3008
3009 status = scic_sds_io_request_terminate(req);
3010 if (status != SCI_SUCCESS)
3011 return status;
3012
3013 /*
3014 * Utilize the original post context command and or in the POST_TC_ABORT
3015 * request sub-type.
3016 */
3017 scic_sds_controller_post_request(scic,
3018 scic_sds_request_get_post_context(req) |
3019 SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT);
3020 return SCI_SUCCESS;
3021 }
3022
3023 /**
3024 * scic_controller_complete_io() - This method will perform core specific
3025 * completion operations for an IO request. After this method is invoked,
3026 * the user should consider the IO request as invalid until it is properly
3027 * reused (i.e. re-constructed).
3028 * @controller: The handle to the controller object for which to complete the
3029 * IO request.
3030 * @remote_device: The handle to the remote device object for which to complete
3031 * the IO request.
3032 * @io_request: the handle to the io request object to complete.
3033 *
3034 * - IO tags are a protected resource. It is incumbent upon the SCI Core user
3035 * to ensure that each of the methods that may allocate or free available IO
3036 * tags are handled in a mutually exclusive manner. This method is one of said
3037 * methods requiring proper critical code section protection (e.g. semaphore,
3038 * spin-lock, etc.). - If the IO tag for a request was allocated, by the SCI
3039 * Core user, using the scic_controller_allocate_io_tag() method, then it is
3040 * the responsibility of the caller to invoke the scic_controller_free_io_tag()
3041 * method to free the tag (i.e. this method will not free the IO tag). Indicate
3042 * if the controller successfully completed the IO request. SCI_SUCCESS if the
3043 * completion process was successful.
3044 */
3045 enum sci_status scic_controller_complete_io(
3046 struct scic_sds_controller *scic,
3047 struct scic_sds_remote_device *rdev,
3048 struct scic_sds_request *request)
3049 {
3050 enum sci_status status;
3051 u16 index;
3052
3053 switch (scic->state_machine.current_state_id) {
3054 case SCI_BASE_CONTROLLER_STATE_STOPPING:
3055 /* XXX: Implement this function */
3056 return SCI_FAILURE;
3057 case SCI_BASE_CONTROLLER_STATE_READY:
3058 status = scic_sds_remote_device_complete_io(scic, rdev, request);
3059 if (status != SCI_SUCCESS)
3060 return status;
3061
3062 index = scic_sds_io_tag_get_index(request->io_tag);
3063 scic->io_request_table[index] = NULL;
3064 return SCI_SUCCESS;
3065 default:
3066 dev_warn(scic_to_dev(scic), "invalid state to complete I/O");
3067 return SCI_FAILURE_INVALID_STATE;
3068 }
3069
3070 }
3071
3072 enum sci_status scic_controller_continue_io(struct scic_sds_request *sci_req)
3073 {
3074 struct scic_sds_controller *scic = sci_req->owning_controller;
3075
3076 if (scic->state_machine.current_state_id !=
3077 SCI_BASE_CONTROLLER_STATE_READY) {
3078 dev_warn(scic_to_dev(scic), "invalid state to continue I/O");
3079 return SCI_FAILURE_INVALID_STATE;
3080 }
3081
3082 scic->io_request_table[scic_sds_io_tag_get_index(sci_req->io_tag)] = sci_req;
3083 scic_sds_controller_post_request(scic, scic_sds_request_get_post_context(sci_req));
3084 return SCI_SUCCESS;
3085 }
3086
3087 /**
3088 * scic_controller_start_task() - This method is called by the SCIC user to
3089 * send/start a framework task management request.
3090 * @controller: the handle to the controller object for which to start the task
3091 * management request.
3092 * @remote_device: the handle to the remote device object for which to start
3093 * the task management request.
3094 * @task_request: the handle to the task request object to start.
3095 * @io_tag: This parameter specifies a previously allocated IO tag that the
3096 * user desires to be utilized for this request. Note this not the io_tag
3097 * of the request being managed. It is to be utilized for the task request
3098 * itself. This parameter is optional. The user is allowed to supply
3099 * SCI_CONTROLLER_INVALID_IO_TAG as the value for this parameter.
3100 *
3101 * - IO tags are a protected resource. It is incumbent upon the SCI Core user
3102 * to ensure that each of the methods that may allocate or free available IO
3103 * tags are handled in a mutually exclusive manner. This method is one of said
3104 * methods requiring proper critical code section protection (e.g. semaphore,
3105 * spin-lock, etc.). - The user must synchronize this task with completion
3106 * queue processing. If they are not synchronized then it is possible for the
3107 * io requests that are being managed by the task request can complete before
3108 * starting the task request. scic_controller_allocate_tag() for more
3109 * information on allocating a tag. Indicate if the controller successfully
3110 * started the IO request. SCI_TASK_SUCCESS if the task request was
3111 * successfully started. SCI_TASK_FAILURE_REQUIRES_SCSI_ABORT This value is
3112 * returned if there is/are task(s) outstanding that require termination or
3113 * completion before this request can succeed.
3114 */
3115 enum sci_task_status scic_controller_start_task(
3116 struct scic_sds_controller *scic,
3117 struct scic_sds_remote_device *rdev,
3118 struct scic_sds_request *req,
3119 u16 task_tag)
3120 {
3121 enum sci_status status;
3122
3123 if (scic->state_machine.current_state_id !=
3124 SCI_BASE_CONTROLLER_STATE_READY) {
3125 dev_warn(scic_to_dev(scic),
3126 "%s: SCIC Controller starting task from invalid "
3127 "state\n",
3128 __func__);
3129 return SCI_TASK_FAILURE_INVALID_STATE;
3130 }
3131
3132 status = scic_sds_remote_device_start_task(scic, rdev, req);
3133 switch (status) {
3134 case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS:
3135 scic->io_request_table[scic_sds_io_tag_get_index(req->io_tag)] = req;
3136
3137 /*
3138 * We will let framework know this task request started successfully,
3139 * although core is still woring on starting the request (to post tc when
3140 * RNC is resumed.)
3141 */
3142 return SCI_SUCCESS;
3143 case SCI_SUCCESS:
3144 scic->io_request_table[scic_sds_io_tag_get_index(req->io_tag)] = req;
3145
3146 scic_sds_controller_post_request(scic,
3147 scic_sds_request_get_post_context(req));
3148 break;
3149 default:
3150 break;
3151 }
3152
3153 return status;
3154 }
3155
3156 /**
3157 * scic_controller_allocate_io_tag() - This method will allocate a tag from the
3158 * pool of free IO tags. Direct allocation of IO tags by the SCI Core user
3159 * is optional. The scic_controller_start_io() method will allocate an IO
3160 * tag if this method is not utilized and the tag is not supplied to the IO
3161 * construct routine. Direct allocation of IO tags may provide additional
3162 * performance improvements in environments capable of supporting this usage
3163 * model. Additionally, direct allocation of IO tags also provides
3164 * additional flexibility to the SCI Core user. Specifically, the user may
3165 * retain IO tags across the lives of multiple IO requests.
3166 * @controller: the handle to the controller object for which to allocate the
3167 * tag.
3168 *
3169 * IO tags are a protected resource. It is incumbent upon the SCI Core user to
3170 * ensure that each of the methods that may allocate or free available IO tags
3171 * are handled in a mutually exclusive manner. This method is one of said
3172 * methods requiring proper critical code section protection (e.g. semaphore,
3173 * spin-lock, etc.). An unsigned integer representing an available IO tag.
3174 * SCI_CONTROLLER_INVALID_IO_TAG This value is returned if there are no
3175 * currently available tags to be allocated. All return other values indicate a
3176 * legitimate tag.
3177 */
3178 u16 scic_controller_allocate_io_tag(
3179 struct scic_sds_controller *scic)
3180 {
3181 u16 task_context;
3182 u16 sequence_count;
3183
3184 if (!sci_pool_empty(scic->tci_pool)) {
3185 sci_pool_get(scic->tci_pool, task_context);
3186
3187 sequence_count = scic->io_request_sequence[task_context];
3188
3189 return scic_sds_io_tag_construct(sequence_count, task_context);
3190 }
3191
3192 return SCI_CONTROLLER_INVALID_IO_TAG;
3193 }
3194
3195 /**
3196 * scic_controller_free_io_tag() - This method will free an IO tag to the pool
3197 * of free IO tags. This method provides the SCI Core user more flexibility
3198 * with regards to IO tags. The user may desire to keep an IO tag after an
3199 * IO request has completed, because they plan on re-using the tag for a
3200 * subsequent IO request. This method is only legal if the tag was
3201 * allocated via scic_controller_allocate_io_tag().
3202 * @controller: This parameter specifies the handle to the controller object
3203 * for which to free/return the tag.
3204 * @io_tag: This parameter represents the tag to be freed to the pool of
3205 * available tags.
3206 *
3207 * - IO tags are a protected resource. It is incumbent upon the SCI Core user
3208 * to ensure that each of the methods that may allocate or free available IO
3209 * tags are handled in a mutually exclusive manner. This method is one of said
3210 * methods requiring proper critical code section protection (e.g. semaphore,
3211 * spin-lock, etc.). - If the IO tag for a request was allocated, by the SCI
3212 * Core user, using the scic_controller_allocate_io_tag() method, then it is
3213 * the responsibility of the caller to invoke this method to free the tag. This
3214 * method returns an indication of whether the tag was successfully put back
3215 * (freed) to the pool of available tags. SCI_SUCCESS This return value
3216 * indicates the tag was successfully placed into the pool of available IO
3217 * tags. SCI_FAILURE_INVALID_IO_TAG This value is returned if the supplied tag
3218 * is not a valid IO tag value.
3219 */
3220 enum sci_status scic_controller_free_io_tag(
3221 struct scic_sds_controller *scic,
3222 u16 io_tag)
3223 {
3224 u16 sequence;
3225 u16 index;
3226
3227 BUG_ON(io_tag == SCI_CONTROLLER_INVALID_IO_TAG);
3228
3229 sequence = scic_sds_io_tag_get_sequence(io_tag);
3230 index = scic_sds_io_tag_get_index(io_tag);
3231
3232 if (!sci_pool_full(scic->tci_pool)) {
3233 if (sequence == scic->io_request_sequence[index]) {
3234 scic_sds_io_sequence_increment(
3235 scic->io_request_sequence[index]);
3236
3237 sci_pool_put(scic->tci_pool, index);
3238
3239 return SCI_SUCCESS;
3240 }
3241 }
3242
3243 return SCI_FAILURE_INVALID_IO_TAG;
3244 }
3245
3246
Linux kernel - Deliverables
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