drivers/scsi/lpfc/lpfc_hw.h

   1 /*******************************************************************
   2  * This file is part of the Emulex Linux Device Driver for         *
   3  * Fibre Channel Host Bus Adapters.                                *
   4  * Copyright (C) 2004-2007 Emulex.  All rights reserved.           *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *******************************************************************/
  20
  21 #define FDMI_DID        0xfffffaU
  22 #define NameServer_DID  0xfffffcU
  23 #define SCR_DID         0xfffffdU
  24 #define Fabric_DID      0xfffffeU
  25 #define Bcast_DID       0xffffffU
  26 #define Mask_DID        0xffffffU
  27 #define CT_DID_MASK     0xffff00U
  28 #define Fabric_DID_MASK 0xfff000U
  29 #define WELL_KNOWN_DID_MASK 0xfffff0U
  30
  31 #define PT2PT_LocalID   1
  32 #define PT2PT_RemoteID  2
  33
  34 #define FF_DEF_EDTOV          2000      /* Default E_D_TOV (2000ms) */
  35 #define FF_DEF_ALTOV            15      /* Default AL_TIME (15ms) */
  36 #define FF_DEF_RATOV             2      /* Default RA_TOV (2s) */
  37 #define FF_DEF_ARBTOV         1900      /* Default ARB_TOV (1900ms) */
  38
  39 #define LPFC_BUF_RING0        64        /* Number of buffers to post to RING
  40                                            0 */
  41
  42 #define FCELSSIZE             1024      /* maximum ELS transfer size */
  43
  44 #define LPFC_FCP_RING            0      /* ring 0 for FCP initiator commands */
  45 #define LPFC_EXTRA_RING          1      /* ring 1 for other protocols */
  46 #define LPFC_ELS_RING            2      /* ring 2 for ELS commands */
  47 #define LPFC_FCP_NEXT_RING       3
  48
  49 #define SLI2_IOCB_CMD_R0_ENTRIES    172 /* SLI-2 FCP command ring entries */
  50 #define SLI2_IOCB_RSP_R0_ENTRIES    134 /* SLI-2 FCP response ring entries */
  51 #define SLI2_IOCB_CMD_R1_ENTRIES      4 /* SLI-2 extra command ring entries */
  52 #define SLI2_IOCB_RSP_R1_ENTRIES      4 /* SLI-2 extra response ring entries */
  53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
  54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
  55 #define SLI2_IOCB_CMD_R2_ENTRIES     20 /* SLI-2 ELS command ring entries */
  56 #define SLI2_IOCB_RSP_R2_ENTRIES     20 /* SLI-2 ELS response ring entries */
  57 #define SLI2_IOCB_CMD_R3_ENTRIES      0
  58 #define SLI2_IOCB_RSP_R3_ENTRIES      0
  59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
  60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
  61
  62 #define SLI2_IOCB_CMD_SIZE      32
  63 #define SLI2_IOCB_RSP_SIZE      32
  64 #define SLI3_IOCB_CMD_SIZE      128
  65 #define SLI3_IOCB_RSP_SIZE      64
  66
  67 /* Common Transport structures and definitions */
  68
  69 union CtRevisionId {
  70         /* Structure is in Big Endian format */
  71         struct {
  72                 uint32_t Revision:8;
  73                 uint32_t InId:24;
  74         } bits;
  75         uint32_t word;
  76 };
  77
  78 union CtCommandResponse {
  79         /* Structure is in Big Endian format */
  80         struct {
  81                 uint32_t CmdRsp:16;
  82                 uint32_t Size:16;
  83         } bits;
  84         uint32_t word;
  85 };
  86
  87 struct lpfc_sli_ct_request {
  88         /* Structure is in Big Endian format */
  89         union CtRevisionId RevisionId;
  90         uint8_t FsType;
  91         uint8_t FsSubType;
  92         uint8_t Options;
  93         uint8_t Rsrvd1;
  94         union CtCommandResponse CommandResponse;
  95         uint8_t Rsrvd2;
  96         uint8_t ReasonCode;
  97         uint8_t Explanation;
  98         uint8_t VendorUnique;
  99
 100         union {
 101                 uint32_t PortID;
 102                 struct gid {
 103                         uint8_t PortType;       /* for GID_PT requests */
 104                         uint8_t DomainScope;
 105                         uint8_t AreaScope;
 106                         uint8_t Fc4Type;        /* for GID_FT requests */
 107                 } gid;
 108                 struct rft {
 109                         uint32_t PortId;        /* For RFT_ID requests */
 110
 111 #ifdef __BIG_ENDIAN_BITFIELD
 112                         uint32_t rsvd0:16;
 113                         uint32_t rsvd1:7;
 114                         uint32_t fcpReg:1;      /* Type 8 */
 115                         uint32_t rsvd2:2;
 116                         uint32_t ipReg:1;       /* Type 5 */
 117                         uint32_t rsvd3:5;
 118 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 119                         uint32_t rsvd0:16;
 120                         uint32_t fcpReg:1;      /* Type 8 */
 121                         uint32_t rsvd1:7;
 122                         uint32_t rsvd3:5;
 123                         uint32_t ipReg:1;       /* Type 5 */
 124                         uint32_t rsvd2:2;
 125 #endif
 126
 127                         uint32_t rsvd[7];
 128                 } rft;
 129                 struct rff {
 130                         uint32_t PortId;
 131                         uint8_t reserved[2];
 132 #ifdef __BIG_ENDIAN_BITFIELD
 133                         uint8_t feature_res:6;
 134                         uint8_t feature_init:1;
 135                         uint8_t feature_tgt:1;
 136 #else  /*  __LITTLE_ENDIAN_BITFIELD */
 137                         uint8_t feature_tgt:1;
 138                         uint8_t feature_init:1;
 139                         uint8_t feature_res:6;
 140 #endif
 141                         uint8_t type_code;     /* type=8 for FCP */
 142                 } rff;
 143                 struct rnn {
 144                         uint32_t PortId;        /* For RNN_ID requests */
 145                         uint8_t wwnn[8];
 146                 } rnn;
 147                 struct rsnn {   /* For RSNN_ID requests */
 148                         uint8_t wwnn[8];
 149                         uint8_t len;
 150                         uint8_t symbname[255];
 151                 } rsnn;
 152         } un;
 153 };
 154
 155 #define  SLI_CT_REVISION        1
 156 #define  GID_REQUEST_SZ         (sizeof(struct lpfc_sli_ct_request) - 260)
 157 #define  RFT_REQUEST_SZ         (sizeof(struct lpfc_sli_ct_request) - 228)
 158 #define  RFF_REQUEST_SZ         (sizeof(struct lpfc_sli_ct_request) - 235)
 159 #define  RNN_REQUEST_SZ         (sizeof(struct lpfc_sli_ct_request) - 252)
 160 #define  RSNN_REQUEST_SZ        (sizeof(struct lpfc_sli_ct_request))
 161
 162 /*
 163  * FsType Definitions
 164  */
 165
 166 #define  SLI_CT_MANAGEMENT_SERVICE        0xFA
 167 #define  SLI_CT_TIME_SERVICE              0xFB
 168 #define  SLI_CT_DIRECTORY_SERVICE         0xFC
 169 #define  SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
 170
 171 /*
 172  * Directory Service Subtypes
 173  */
 174
 175 #define  SLI_CT_DIRECTORY_NAME_SERVER     0x02
 176
 177 /*
 178  * Response Codes
 179  */
 180
 181 #define  SLI_CT_RESPONSE_FS_RJT           0x8001
 182 #define  SLI_CT_RESPONSE_FS_ACC           0x8002
 183
 184 /*
 185  * Reason Codes
 186  */
 187
 188 #define  SLI_CT_NO_ADDITIONAL_EXPL        0x0
 189 #define  SLI_CT_INVALID_COMMAND           0x01
 190 #define  SLI_CT_INVALID_VERSION           0x02
 191 #define  SLI_CT_LOGICAL_ERROR             0x03
 192 #define  SLI_CT_INVALID_IU_SIZE           0x04
 193 #define  SLI_CT_LOGICAL_BUSY              0x05
 194 #define  SLI_CT_PROTOCOL_ERROR            0x07
 195 #define  SLI_CT_UNABLE_TO_PERFORM_REQ     0x09
 196 #define  SLI_CT_REQ_NOT_SUPPORTED         0x0b
 197 #define  SLI_CT_HBA_INFO_NOT_REGISTERED   0x10
 198 #define  SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE  0x11
 199 #define  SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN      0x12
 200 #define  SLI_CT_HBA_ATTR_NOT_PRESENT      0x13
 201 #define  SLI_CT_PORT_INFO_NOT_REGISTERED  0x20
 202 #define  SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
 203 #define  SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN     0x22
 204 #define  SLI_CT_VENDOR_UNIQUE             0xff
 205
 206 /*
 207  * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
 208  */
 209
 210 #define  SLI_CT_NO_PORT_ID                0x01
 211 #define  SLI_CT_NO_PORT_NAME              0x02
 212 #define  SLI_CT_NO_NODE_NAME              0x03
 213 #define  SLI_CT_NO_CLASS_OF_SERVICE       0x04
 214 #define  SLI_CT_NO_IP_ADDRESS             0x05
 215 #define  SLI_CT_NO_IPA                    0x06
 216 #define  SLI_CT_NO_FC4_TYPES              0x07
 217 #define  SLI_CT_NO_SYMBOLIC_PORT_NAME     0x08
 218 #define  SLI_CT_NO_SYMBOLIC_NODE_NAME     0x09
 219 #define  SLI_CT_NO_PORT_TYPE              0x0A
 220 #define  SLI_CT_ACCESS_DENIED             0x10
 221 #define  SLI_CT_INVALID_PORT_ID           0x11
 222 #define  SLI_CT_DATABASE_EMPTY            0x12
 223
 224 /*
 225  * Name Server Command Codes
 226  */
 227
 228 #define  SLI_CTNS_GA_NXT      0x0100
 229 #define  SLI_CTNS_GPN_ID      0x0112
 230 #define  SLI_CTNS_GNN_ID      0x0113
 231 #define  SLI_CTNS_GCS_ID      0x0114
 232 #define  SLI_CTNS_GFT_ID      0x0117
 233 #define  SLI_CTNS_GSPN_ID     0x0118
 234 #define  SLI_CTNS_GPT_ID      0x011A
 235 #define  SLI_CTNS_GID_PN      0x0121
 236 #define  SLI_CTNS_GID_NN      0x0131
 237 #define  SLI_CTNS_GIP_NN      0x0135
 238 #define  SLI_CTNS_GIPA_NN     0x0136
 239 #define  SLI_CTNS_GSNN_NN     0x0139
 240 #define  SLI_CTNS_GNN_IP      0x0153
 241 #define  SLI_CTNS_GIPA_IP     0x0156
 242 #define  SLI_CTNS_GID_FT      0x0171
 243 #define  SLI_CTNS_GID_PT      0x01A1
 244 #define  SLI_CTNS_RPN_ID      0x0212
 245 #define  SLI_CTNS_RNN_ID      0x0213
 246 #define  SLI_CTNS_RCS_ID      0x0214
 247 #define  SLI_CTNS_RFT_ID      0x0217
 248 #define  SLI_CTNS_RFF_ID      0x021F
 249 #define  SLI_CTNS_RSPN_ID     0x0218
 250 #define  SLI_CTNS_RPT_ID      0x021A
 251 #define  SLI_CTNS_RIP_NN      0x0235
 252 #define  SLI_CTNS_RIPA_NN     0x0236
 253 #define  SLI_CTNS_RSNN_NN     0x0239
 254 #define  SLI_CTNS_DA_ID       0x0300
 255
 256 /*
 257  * Port Types
 258  */
 259
 260 #define  SLI_CTPT_N_PORT      0x01
 261 #define  SLI_CTPT_NL_PORT     0x02
 262 #define  SLI_CTPT_FNL_PORT    0x03
 263 #define  SLI_CTPT_IP          0x04
 264 #define  SLI_CTPT_FCP         0x08
 265 #define  SLI_CTPT_NX_PORT     0x7F
 266 #define  SLI_CTPT_F_PORT      0x81
 267 #define  SLI_CTPT_FL_PORT     0x82
 268 #define  SLI_CTPT_E_PORT      0x84
 269
 270 #define SLI_CT_LAST_ENTRY     0x80000000
 271
 272 /* Fibre Channel Service Parameter definitions */
 273
 274 #define FC_PH_4_0   6           /* FC-PH version 4.0 */
 275 #define FC_PH_4_1   7           /* FC-PH version 4.1 */
 276 #define FC_PH_4_2   8           /* FC-PH version 4.2 */
 277 #define FC_PH_4_3   9           /* FC-PH version 4.3 */
 278
 279 #define FC_PH_LOW   8           /* Lowest supported FC-PH version */
 280 #define FC_PH_HIGH  9           /* Highest supported FC-PH version */
 281 #define FC_PH3   0x20           /* FC-PH-3 version */
 282
 283 #define FF_FRAME_SIZE     2048
 284
 285 struct lpfc_name {
 286         union {
 287                 struct {
 288 #ifdef __BIG_ENDIAN_BITFIELD
 289                         uint8_t nameType:4;     /* FC Word 0, bit 28:31 */
 290                         uint8_t IEEEextMsn:4;   /* FC Word 0, bit 24:27, bit
 291                                                    8:11 of IEEE ext */
 292 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 293                         uint8_t IEEEextMsn:4;   /* FC Word 0, bit 24:27, bit
 294                                                    8:11 of IEEE ext */
 295                         uint8_t nameType:4;     /* FC Word 0, bit 28:31 */
 296 #endif
 297
 298 #define NAME_IEEE           0x1 /* IEEE name - nameType */
 299 #define NAME_IEEE_EXT       0x2 /* IEEE extended name */
 300 #define NAME_FC_TYPE        0x3 /* FC native name type */
 301 #define NAME_IP_TYPE        0x4 /* IP address */
 302 #define NAME_CCITT_TYPE     0xC
 303 #define NAME_CCITT_GR_TYPE  0xE
 304                         uint8_t IEEEextLsb;     /* FC Word 0, bit 16:23, IEEE
 305                                                    extended Lsb */
 306                         uint8_t IEEE[6];        /* FC IEEE address */
 307                 } s;
 308                 uint8_t wwn[8];
 309         } u;
 310 };
 311
 312 struct csp {
 313         uint8_t fcphHigh;       /* FC Word 0, byte 0 */
 314         uint8_t fcphLow;
 315         uint8_t bbCreditMsb;
 316         uint8_t bbCreditlsb;    /* FC Word 0, byte 3 */
 317
 318 #ifdef __BIG_ENDIAN_BITFIELD
 319         uint16_t increasingOffset:1;    /* FC Word 1, bit 31 */
 320         uint16_t response_multiple_Nport:1;     /* FC Word 1, bit 29 */
 321         uint16_t fPort:1;       /* FC Word 1, bit 28 */
 322         uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
 323         uint16_t edtovResolution:1;     /* FC Word 1, bit 26 */
 324         uint16_t multicast:1;   /* FC Word 1, bit 25 */
 325         uint16_t broadcast:1;   /* FC Word 1, bit 24 */
 326
 327         uint16_t huntgroup:1;   /* FC Word 1, bit 23 */
 328         uint16_t simplex:1;     /* FC Word 1, bit 22 */
 329         uint16_t word1Reserved1:3;      /* FC Word 1, bit 21:19 */
 330         uint16_t dhd:1;         /* FC Word 1, bit 18 */
 331         uint16_t contIncSeqCnt:1;       /* FC Word 1, bit 17 */
 332         uint16_t payloadlength:1;       /* FC Word 1, bit 16 */
 333 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 334         uint16_t broadcast:1;   /* FC Word 1, bit 24 */
 335         uint16_t multicast:1;   /* FC Word 1, bit 25 */
 336         uint16_t edtovResolution:1;     /* FC Word 1, bit 26 */
 337         uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
 338         uint16_t fPort:1;       /* FC Word 1, bit 28 */
 339         uint16_t word1Reserved2:1;      /* FC Word 1, bit 29 */
 340         uint16_t randomOffset:1;        /* FC Word 1, bit 30 */
 341         uint16_t increasingOffset:1;    /* FC Word 1, bit 31 */
 342
 343         uint16_t payloadlength:1;       /* FC Word 1, bit 16 */
 344         uint16_t contIncSeqCnt:1;       /* FC Word 1, bit 17 */
 345         uint16_t dhd:1;         /* FC Word 1, bit 18 */
 346         uint16_t word1Reserved1:3;      /* FC Word 1, bit 21:19 */
 347         uint16_t simplex:1;     /* FC Word 1, bit 22 */
 348         uint16_t huntgroup:1;   /* FC Word 1, bit 23 */
 349 #endif
 350
 351         uint8_t bbRcvSizeMsb;   /* Upper nibble is reserved */
 352         uint8_t bbRcvSizeLsb;   /* FC Word 1, byte 3 */
 353         union {
 354                 struct {
 355                         uint8_t word2Reserved1; /* FC Word 2 byte 0 */
 356
 357                         uint8_t totalConcurrSeq;        /* FC Word 2 byte 1 */
 358                         uint8_t roByCategoryMsb;        /* FC Word 2 byte 2 */
 359
 360                         uint8_t roByCategoryLsb;        /* FC Word 2 byte 3 */
 361                 } nPort;
 362                 uint32_t r_a_tov;       /* R_A_TOV must be in B.E. format */
 363         } w2;
 364
 365         uint32_t e_d_tov;       /* E_D_TOV must be in B.E. format */
 366 };
 367
 368 struct class_parms {
 369 #ifdef __BIG_ENDIAN_BITFIELD
 370         uint8_t classValid:1;   /* FC Word 0, bit 31 */
 371         uint8_t intermix:1;     /* FC Word 0, bit 30 */
 372         uint8_t stackedXparent:1;       /* FC Word 0, bit 29 */
 373         uint8_t stackedLockDown:1;      /* FC Word 0, bit 28 */
 374         uint8_t seqDelivery:1;  /* FC Word 0, bit 27 */
 375         uint8_t word0Reserved1:3;       /* FC Word 0, bit 24:26 */
 376 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 377         uint8_t word0Reserved1:3;       /* FC Word 0, bit 24:26 */
 378         uint8_t seqDelivery:1;  /* FC Word 0, bit 27 */
 379         uint8_t stackedLockDown:1;      /* FC Word 0, bit 28 */
 380         uint8_t stackedXparent:1;       /* FC Word 0, bit 29 */
 381         uint8_t intermix:1;     /* FC Word 0, bit 30 */
 382         uint8_t classValid:1;   /* FC Word 0, bit 31 */
 383
 384 #endif
 385
 386         uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
 387
 388 #ifdef __BIG_ENDIAN_BITFIELD
 389         uint8_t iCtlXidReAssgn:2;       /* FC Word 0, Bit 14:15 */
 390         uint8_t iCtlInitialPa:2;        /* FC Word 0, bit 12:13 */
 391         uint8_t iCtlAck0capable:1;      /* FC Word 0, bit 11 */
 392         uint8_t iCtlAckNcapable:1;      /* FC Word 0, bit 10 */
 393         uint8_t word0Reserved3:2;       /* FC Word 0, bit  8: 9 */
 394 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 395         uint8_t word0Reserved3:2;       /* FC Word 0, bit  8: 9 */
 396         uint8_t iCtlAckNcapable:1;      /* FC Word 0, bit 10 */
 397         uint8_t iCtlAck0capable:1;      /* FC Word 0, bit 11 */
 398         uint8_t iCtlInitialPa:2;        /* FC Word 0, bit 12:13 */
 399         uint8_t iCtlXidReAssgn:2;       /* FC Word 0, Bit 14:15 */
 400 #endif
 401
 402         uint8_t word0Reserved4; /* FC Word 0, bit  0: 7 */
 403
 404 #ifdef __BIG_ENDIAN_BITFIELD
 405         uint8_t rCtlAck0capable:1;      /* FC Word 1, bit 31 */
 406         uint8_t rCtlAckNcapable:1;      /* FC Word 1, bit 30 */
 407         uint8_t rCtlXidInterlck:1;      /* FC Word 1, bit 29 */
 408         uint8_t rCtlErrorPolicy:2;      /* FC Word 1, bit 27:28 */
 409         uint8_t word1Reserved1:1;       /* FC Word 1, bit 26 */
 410         uint8_t rCtlCatPerSeq:2;        /* FC Word 1, bit 24:25 */
 411 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 412         uint8_t rCtlCatPerSeq:2;        /* FC Word 1, bit 24:25 */
 413         uint8_t word1Reserved1:1;       /* FC Word 1, bit 26 */
 414         uint8_t rCtlErrorPolicy:2;      /* FC Word 1, bit 27:28 */
 415         uint8_t rCtlXidInterlck:1;      /* FC Word 1, bit 29 */
 416         uint8_t rCtlAckNcapable:1;      /* FC Word 1, bit 30 */
 417         uint8_t rCtlAck0capable:1;      /* FC Word 1, bit 31 */
 418 #endif
 419
 420         uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
 421         uint8_t rcvDataSizeMsb; /* FC Word 1, bit  8:15 */
 422         uint8_t rcvDataSizeLsb; /* FC Word 1, bit  0: 7 */
 423
 424         uint8_t concurrentSeqMsb;       /* FC Word 2, bit 24:31 */
 425         uint8_t concurrentSeqLsb;       /* FC Word 2, bit 16:23 */
 426         uint8_t EeCreditSeqMsb; /* FC Word 2, bit  8:15 */
 427         uint8_t EeCreditSeqLsb; /* FC Word 2, bit  0: 7 */
 428
 429         uint8_t openSeqPerXchgMsb;      /* FC Word 3, bit 24:31 */
 430         uint8_t openSeqPerXchgLsb;      /* FC Word 3, bit 16:23 */
 431         uint8_t word3Reserved1; /* Fc Word 3, bit  8:15 */
 432         uint8_t word3Reserved2; /* Fc Word 3, bit  0: 7 */
 433 };
 434
 435 struct serv_parm {      /* Structure is in Big Endian format */
 436         struct csp cmn;
 437         struct lpfc_name portName;
 438         struct lpfc_name nodeName;
 439         struct class_parms cls1;
 440         struct class_parms cls2;
 441         struct class_parms cls3;
 442         struct class_parms cls4;
 443         uint8_t vendorVersion[16];
 444 };
 445
 446 /*
 447  *  Extended Link Service LS_COMMAND codes (Payload Word 0)
 448  */
 449 #ifdef __BIG_ENDIAN_BITFIELD
 450 #define ELS_CMD_MASK      0xffff0000
 451 #define ELS_RSP_MASK      0xff000000
 452 #define ELS_CMD_LS_RJT    0x01000000
 453 #define ELS_CMD_ACC       0x02000000
 454 #define ELS_CMD_PLOGI     0x03000000
 455 #define ELS_CMD_FLOGI     0x04000000
 456 #define ELS_CMD_LOGO      0x05000000
 457 #define ELS_CMD_ABTX      0x06000000
 458 #define ELS_CMD_RCS       0x07000000
 459 #define ELS_CMD_RES       0x08000000
 460 #define ELS_CMD_RSS       0x09000000
 461 #define ELS_CMD_RSI       0x0A000000
 462 #define ELS_CMD_ESTS      0x0B000000
 463 #define ELS_CMD_ESTC      0x0C000000
 464 #define ELS_CMD_ADVC      0x0D000000
 465 #define ELS_CMD_RTV       0x0E000000
 466 #define ELS_CMD_RLS       0x0F000000
 467 #define ELS_CMD_ECHO      0x10000000
 468 #define ELS_CMD_TEST      0x11000000
 469 #define ELS_CMD_RRQ       0x12000000
 470 #define ELS_CMD_PRLI      0x20100014
 471 #define ELS_CMD_PRLO      0x21100014
 472 #define ELS_CMD_PRLO_ACC  0x02100014
 473 #define ELS_CMD_PDISC     0x50000000
 474 #define ELS_CMD_FDISC     0x51000000
 475 #define ELS_CMD_ADISC     0x52000000
 476 #define ELS_CMD_FARP      0x54000000
 477 #define ELS_CMD_FARPR     0x55000000
 478 #define ELS_CMD_RPS       0x56000000
 479 #define ELS_CMD_RPL       0x57000000
 480 #define ELS_CMD_FAN       0x60000000
 481 #define ELS_CMD_RSCN      0x61040000
 482 #define ELS_CMD_SCR       0x62000000
 483 #define ELS_CMD_RNID      0x78000000
 484 #define ELS_CMD_LIRR      0x7A000000
 485 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 486 #define ELS_CMD_MASK      0xffff
 487 #define ELS_RSP_MASK      0xff
 488 #define ELS_CMD_LS_RJT    0x01
 489 #define ELS_CMD_ACC       0x02
 490 #define ELS_CMD_PLOGI     0x03
 491 #define ELS_CMD_FLOGI     0x04
 492 #define ELS_CMD_LOGO      0x05
 493 #define ELS_CMD_ABTX      0x06
 494 #define ELS_CMD_RCS       0x07
 495 #define ELS_CMD_RES       0x08
 496 #define ELS_CMD_RSS       0x09
 497 #define ELS_CMD_RSI       0x0A
 498 #define ELS_CMD_ESTS      0x0B
 499 #define ELS_CMD_ESTC      0x0C
 500 #define ELS_CMD_ADVC      0x0D
 501 #define ELS_CMD_RTV       0x0E
 502 #define ELS_CMD_RLS       0x0F
 503 #define ELS_CMD_ECHO      0x10
 504 #define ELS_CMD_TEST      0x11
 505 #define ELS_CMD_RRQ       0x12
 506 #define ELS_CMD_PRLI      0x14001020
 507 #define ELS_CMD_PRLO      0x14001021
 508 #define ELS_CMD_PRLO_ACC  0x14001002
 509 #define ELS_CMD_PDISC     0x50
 510 #define ELS_CMD_FDISC     0x51
 511 #define ELS_CMD_ADISC     0x52
 512 #define ELS_CMD_FARP      0x54
 513 #define ELS_CMD_FARPR     0x55
 514 #define ELS_CMD_RPS       0x56
 515 #define ELS_CMD_RPL       0x57
 516 #define ELS_CMD_FAN       0x60
 517 #define ELS_CMD_RSCN      0x0461
 518 #define ELS_CMD_SCR       0x62
 519 #define ELS_CMD_RNID      0x78
 520 #define ELS_CMD_LIRR      0x7A
 521 #endif
 522
 523 /*
 524  *  LS_RJT Payload Definition
 525  */
 526
 527 struct ls_rjt { /* Structure is in Big Endian format */
 528         union {
 529                 uint32_t lsRjtError;
 530                 struct {
 531                         uint8_t lsRjtRsvd0;     /* FC Word 0, bit 24:31 */
 532
 533                         uint8_t lsRjtRsnCode;   /* FC Word 0, bit 16:23 */
 534                         /* LS_RJT reason codes */
 535 #define LSRJT_INVALID_CMD     0x01
 536 #define LSRJT_LOGICAL_ERR     0x03
 537 #define LSRJT_LOGICAL_BSY     0x05
 538 #define LSRJT_PROTOCOL_ERR    0x07
 539 #define LSRJT_UNABLE_TPC      0x09      /* Unable to perform command */
 540 #define LSRJT_CMD_UNSUPPORTED 0x0B
 541 #define LSRJT_VENDOR_UNIQUE   0xFF      /* See Byte 3 */
 542
 543                         uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
 544                         /* LS_RJT reason explanation */
 545 #define LSEXP_NOTHING_MORE      0x00
 546 #define LSEXP_SPARM_OPTIONS     0x01
 547 #define LSEXP_SPARM_ICTL        0x03
 548 #define LSEXP_SPARM_RCTL        0x05
 549 #define LSEXP_SPARM_RCV_SIZE    0x07
 550 #define LSEXP_SPARM_CONCUR_SEQ  0x09
 551 #define LSEXP_SPARM_CREDIT      0x0B
 552 #define LSEXP_INVALID_PNAME     0x0D
 553 #define LSEXP_INVALID_NNAME     0x0E
 554 #define LSEXP_INVALID_CSP       0x0F
 555 #define LSEXP_INVALID_ASSOC_HDR 0x11
 556 #define LSEXP_ASSOC_HDR_REQ     0x13
 557 #define LSEXP_INVALID_O_SID     0x15
 558 #define LSEXP_INVALID_OX_RX     0x17
 559 #define LSEXP_CMD_IN_PROGRESS   0x19
 560 #define LSEXP_INVALID_NPORT_ID  0x1F
 561 #define LSEXP_INVALID_SEQ_ID    0x21
 562 #define LSEXP_INVALID_XCHG      0x23
 563 #define LSEXP_INACTIVE_XCHG     0x25
 564 #define LSEXP_RQ_REQUIRED       0x27
 565 #define LSEXP_OUT_OF_RESOURCE   0x29
 566 #define LSEXP_CANT_GIVE_DATA    0x2A
 567 #define LSEXP_REQ_UNSUPPORTED   0x2C
 568                         uint8_t vendorUnique;   /* FC Word 0, bit  0: 7 */
 569                 } b;
 570         } un;
 571 };
 572
 573 /*
 574  *  N_Port Login (FLOGO/PLOGO Request) Payload Definition
 575  */
 576
 577 typedef struct _LOGO {          /* Structure is in Big Endian format */
 578         union {
 579                 uint32_t nPortId32;     /* Access nPortId as a word */
 580                 struct {
 581                         uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
 582                         uint8_t nPortIdByte0;   /* N_port  ID bit 16:23 */
 583                         uint8_t nPortIdByte1;   /* N_port  ID bit  8:15 */
 584                         uint8_t nPortIdByte2;   /* N_port  ID bit  0: 7 */
 585                 } b;
 586         } un;
 587         struct lpfc_name portName;      /* N_port name field */
 588 } LOGO;
 589
 590 /*
 591  *  FCP Login (PRLI Request / ACC) Payload Definition
 592  */
 593
 594 #define PRLX_PAGE_LEN   0x10
 595 #define TPRLO_PAGE_LEN  0x14
 596
 597 typedef struct _PRLI {          /* Structure is in Big Endian format */
 598         uint8_t prliType;       /* FC Parm Word 0, bit 24:31 */
 599
 600 #define PRLI_FCP_TYPE 0x08
 601         uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
 602
 603 #ifdef __BIG_ENDIAN_BITFIELD
 604         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 605         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 606         uint8_t estabImagePair:1;       /* FC Parm Word 0, bit 13 */
 607
 608         /*    ACC = imagePairEstablished */
 609         uint8_t word0Reserved2:1;       /* FC Parm Word 0, bit 12 */
 610         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 611 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 612         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 613         uint8_t word0Reserved2:1;       /* FC Parm Word 0, bit 12 */
 614         uint8_t estabImagePair:1;       /* FC Parm Word 0, bit 13 */
 615         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 616         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 617         /*    ACC = imagePairEstablished */
 618 #endif
 619
 620 #define PRLI_REQ_EXECUTED     0x1       /* acceptRspCode */
 621 #define PRLI_NO_RESOURCES     0x2
 622 #define PRLI_INIT_INCOMPLETE  0x3
 623 #define PRLI_NO_SUCH_PA       0x4
 624 #define PRLI_PREDEF_CONFIG    0x5
 625 #define PRLI_PARTIAL_SUCCESS  0x6
 626 #define PRLI_INVALID_PAGE_CNT 0x7
 627         uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
 628
 629         uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
 630
 631         uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
 632
 633         uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
 634         uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
 635
 636 #ifdef __BIG_ENDIAN_BITFIELD
 637         uint16_t Word3bit15Resved:1;    /* FC Parm Word 3, bit 15 */
 638         uint16_t Word3bit14Resved:1;    /* FC Parm Word 3, bit 14 */
 639         uint16_t Word3bit13Resved:1;    /* FC Parm Word 3, bit 13 */
 640         uint16_t Word3bit12Resved:1;    /* FC Parm Word 3, bit 12 */
 641         uint16_t Word3bit11Resved:1;    /* FC Parm Word 3, bit 11 */
 642         uint16_t Word3bit10Resved:1;    /* FC Parm Word 3, bit 10 */
 643         uint16_t TaskRetryIdReq:1;      /* FC Parm Word 3, bit  9 */
 644         uint16_t Retry:1;       /* FC Parm Word 3, bit  8 */
 645         uint16_t ConfmComplAllowed:1;   /* FC Parm Word 3, bit  7 */
 646         uint16_t dataOverLay:1; /* FC Parm Word 3, bit  6 */
 647         uint16_t initiatorFunc:1;       /* FC Parm Word 3, bit  5 */
 648         uint16_t targetFunc:1;  /* FC Parm Word 3, bit  4 */
 649         uint16_t cmdDataMixEna:1;       /* FC Parm Word 3, bit  3 */
 650         uint16_t dataRspMixEna:1;       /* FC Parm Word 3, bit  2 */
 651         uint16_t readXferRdyDis:1;      /* FC Parm Word 3, bit  1 */
 652         uint16_t writeXferRdyDis:1;     /* FC Parm Word 3, bit  0 */
 653 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 654         uint16_t Retry:1;       /* FC Parm Word 3, bit  8 */
 655         uint16_t TaskRetryIdReq:1;      /* FC Parm Word 3, bit  9 */
 656         uint16_t Word3bit10Resved:1;    /* FC Parm Word 3, bit 10 */
 657         uint16_t Word3bit11Resved:1;    /* FC Parm Word 3, bit 11 */
 658         uint16_t Word3bit12Resved:1;    /* FC Parm Word 3, bit 12 */
 659         uint16_t Word3bit13Resved:1;    /* FC Parm Word 3, bit 13 */
 660         uint16_t Word3bit14Resved:1;    /* FC Parm Word 3, bit 14 */
 661         uint16_t Word3bit15Resved:1;    /* FC Parm Word 3, bit 15 */
 662         uint16_t writeXferRdyDis:1;     /* FC Parm Word 3, bit  0 */
 663         uint16_t readXferRdyDis:1;      /* FC Parm Word 3, bit  1 */
 664         uint16_t dataRspMixEna:1;       /* FC Parm Word 3, bit  2 */
 665         uint16_t cmdDataMixEna:1;       /* FC Parm Word 3, bit  3 */
 666         uint16_t targetFunc:1;  /* FC Parm Word 3, bit  4 */
 667         uint16_t initiatorFunc:1;       /* FC Parm Word 3, bit  5 */
 668         uint16_t dataOverLay:1; /* FC Parm Word 3, bit  6 */
 669         uint16_t ConfmComplAllowed:1;   /* FC Parm Word 3, bit  7 */
 670 #endif
 671 } PRLI;
 672
 673 /*
 674  *  FCP Logout (PRLO Request / ACC) Payload Definition
 675  */
 676
 677 typedef struct _PRLO {          /* Structure is in Big Endian format */
 678         uint8_t prloType;       /* FC Parm Word 0, bit 24:31 */
 679
 680 #define PRLO_FCP_TYPE  0x08
 681         uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
 682
 683 #ifdef __BIG_ENDIAN_BITFIELD
 684         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 685         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 686         uint8_t word0Reserved2:2;       /* FC Parm Word 0, bit 12:13 */
 687         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 688 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 689         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 690         uint8_t word0Reserved2:2;       /* FC Parm Word 0, bit 12:13 */
 691         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 692         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 693 #endif
 694
 695 #define PRLO_REQ_EXECUTED     0x1       /* acceptRspCode */
 696 #define PRLO_NO_SUCH_IMAGE    0x4
 697 #define PRLO_INVALID_PAGE_CNT 0x7
 698
 699         uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
 700
 701         uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
 702
 703         uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
 704
 705         uint32_t word3Reserved1;        /* FC Parm Word 3, bit 0:31 */
 706 } PRLO;
 707
 708 typedef struct _ADISC {         /* Structure is in Big Endian format */
 709         uint32_t hardAL_PA;
 710         struct lpfc_name portName;
 711         struct lpfc_name nodeName;
 712         uint32_t DID;
 713 } ADISC;
 714
 715 typedef struct _FARP {          /* Structure is in Big Endian format */
 716         uint32_t Mflags:8;
 717         uint32_t Odid:24;
 718 #define FARP_NO_ACTION          0       /* FARP information enclosed, no
 719                                            action */
 720 #define FARP_MATCH_PORT         0x1     /* Match on Responder Port Name */
 721 #define FARP_MATCH_NODE         0x2     /* Match on Responder Node Name */
 722 #define FARP_MATCH_IP           0x4     /* Match on IP address, not supported */
 723 #define FARP_MATCH_IPV4         0x5     /* Match on IPV4 address, not
 724                                            supported */
 725 #define FARP_MATCH_IPV6         0x6     /* Match on IPV6 address, not
 726                                            supported */
 727         uint32_t Rflags:8;
 728         uint32_t Rdid:24;
 729 #define FARP_REQUEST_PLOGI      0x1     /* Request for PLOGI */
 730 #define FARP_REQUEST_FARPR      0x2     /* Request for FARP Response */
 731         struct lpfc_name OportName;
 732         struct lpfc_name OnodeName;
 733         struct lpfc_name RportName;
 734         struct lpfc_name RnodeName;
 735         uint8_t Oipaddr[16];
 736         uint8_t Ripaddr[16];
 737 } FARP;
 738
 739 typedef struct _FAN {           /* Structure is in Big Endian format */
 740         uint32_t Fdid;
 741         struct lpfc_name FportName;
 742         struct lpfc_name FnodeName;
 743 } FAN;
 744
 745 typedef struct _SCR {           /* Structure is in Big Endian format */
 746         uint8_t resvd1;
 747         uint8_t resvd2;
 748         uint8_t resvd3;
 749         uint8_t Function;
 750 #define  SCR_FUNC_FABRIC     0x01
 751 #define  SCR_FUNC_NPORT      0x02
 752 #define  SCR_FUNC_FULL       0x03
 753 #define  SCR_CLEAR           0xff
 754 } SCR;
 755
 756 typedef struct _RNID_TOP_DISC {
 757         struct lpfc_name portName;
 758         uint8_t resvd[8];
 759         uint32_t unitType;
 760 #define RNID_HBA            0x7
 761 #define RNID_HOST           0xa
 762 #define RNID_DRIVER         0xd
 763         uint32_t physPort;
 764         uint32_t attachedNodes;
 765         uint16_t ipVersion;
 766 #define RNID_IPV4           0x1
 767 #define RNID_IPV6           0x2
 768         uint16_t UDPport;
 769         uint8_t ipAddr[16];
 770         uint16_t resvd1;
 771         uint16_t flags;
 772 #define RNID_TD_SUPPORT     0x1
 773 #define RNID_LP_VALID       0x2
 774 } RNID_TOP_DISC;
 775
 776 typedef struct _RNID {          /* Structure is in Big Endian format */
 777         uint8_t Format;
 778 #define RNID_TOPOLOGY_DISC  0xdf
 779         uint8_t CommonLen;
 780         uint8_t resvd1;
 781         uint8_t SpecificLen;
 782         struct lpfc_name portName;
 783         struct lpfc_name nodeName;
 784         union {
 785                 RNID_TOP_DISC topologyDisc;     /* topology disc (0xdf) */
 786         } un;
 787 } RNID;
 788
 789 typedef struct  _RPS {          /* Structure is in Big Endian format */
 790         union {
 791                 uint32_t portNum;
 792                 struct lpfc_name portName;
 793         } un;
 794 } RPS;
 795
 796 typedef struct  _RPS_RSP {      /* Structure is in Big Endian format */
 797         uint16_t rsvd1;
 798         uint16_t portStatus;
 799         uint32_t linkFailureCnt;
 800         uint32_t lossSyncCnt;
 801         uint32_t lossSignalCnt;
 802         uint32_t primSeqErrCnt;
 803         uint32_t invalidXmitWord;
 804         uint32_t crcCnt;
 805 } RPS_RSP;
 806
 807 typedef struct  _RPL {          /* Structure is in Big Endian format */
 808         uint32_t maxsize;
 809         uint32_t index;
 810 } RPL;
 811
 812 typedef struct  _PORT_NUM_BLK {
 813         uint32_t portNum;
 814         uint32_t portID;
 815         struct lpfc_name portName;
 816 } PORT_NUM_BLK;
 817
 818 typedef struct  _RPL_RSP {      /* Structure is in Big Endian format */
 819         uint32_t listLen;
 820         uint32_t index;
 821         PORT_NUM_BLK port_num_blk;
 822 } RPL_RSP;
 823
 824 /* This is used for RSCN command */
 825 typedef struct _D_ID {          /* Structure is in Big Endian format */
 826         union {
 827                 uint32_t word;
 828                 struct {
 829 #ifdef __BIG_ENDIAN_BITFIELD
 830                         uint8_t resv;
 831                         uint8_t domain;
 832                         uint8_t area;
 833                         uint8_t id;
 834 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 835                         uint8_t id;
 836                         uint8_t area;
 837                         uint8_t domain;
 838                         uint8_t resv;
 839 #endif
 840                 } b;
 841         } un;
 842 } D_ID;
 843
 844 /*
 845  *  Structure to define all ELS Payload types
 846  */
 847
 848 typedef struct _ELS_PKT {       /* Structure is in Big Endian format */
 849         uint8_t elsCode;        /* FC Word 0, bit 24:31 */
 850         uint8_t elsByte1;
 851         uint8_t elsByte2;
 852         uint8_t elsByte3;
 853         union {
 854                 struct ls_rjt lsRjt;    /* Payload for LS_RJT ELS response */
 855                 struct serv_parm logi;  /* Payload for PLOGI/FLOGI/PDISC/ACC */
 856                 LOGO logo;      /* Payload for PLOGO/FLOGO/ACC */
 857                 PRLI prli;      /* Payload for PRLI/ACC */
 858                 PRLO prlo;      /* Payload for PRLO/ACC */
 859                 ADISC adisc;    /* Payload for ADISC/ACC */
 860                 FARP farp;      /* Payload for FARP/ACC */
 861                 FAN fan;        /* Payload for FAN */
 862                 SCR scr;        /* Payload for SCR/ACC */
 863                 RNID rnid;      /* Payload for RNID */
 864                 uint8_t pad[128 - 4];   /* Pad out to payload of 128 bytes */
 865         } un;
 866 } ELS_PKT;
 867
 868 /*
 869  * FDMI
 870  * HBA MAnagement Operations Command Codes
 871  */
 872 #define  SLI_MGMT_GRHL     0x100        /* Get registered HBA list */
 873 #define  SLI_MGMT_GHAT     0x101        /* Get HBA attributes */
 874 #define  SLI_MGMT_GRPL     0x102        /* Get registered Port list */
 875 #define  SLI_MGMT_GPAT     0x110        /* Get Port attributes */
 876 #define  SLI_MGMT_RHBA     0x200        /* Register HBA */
 877 #define  SLI_MGMT_RHAT     0x201        /* Register HBA atttributes */
 878 #define  SLI_MGMT_RPRT     0x210        /* Register Port */
 879 #define  SLI_MGMT_RPA      0x211        /* Register Port attributes */
 880 #define  SLI_MGMT_DHBA     0x300        /* De-register HBA */
 881 #define  SLI_MGMT_DPRT     0x310        /* De-register Port */
 882
 883 /*
 884  * Management Service Subtypes
 885  */
 886 #define  SLI_CT_FDMI_Subtypes     0x10
 887
 888 /*
 889  * HBA Management Service Reject Code
 890  */
 891 #define  REJECT_CODE             0x9    /* Unable to perform command request */
 892
 893 /*
 894  * HBA Management Service Reject Reason Code
 895  * Please refer to the Reason Codes above
 896  */
 897
 898 /*
 899  * HBA Attribute Types
 900  */
 901 #define  NODE_NAME               0x1
 902 #define  MANUFACTURER            0x2
 903 #define  SERIAL_NUMBER           0x3
 904 #define  MODEL                   0x4
 905 #define  MODEL_DESCRIPTION       0x5
 906 #define  HARDWARE_VERSION        0x6
 907 #define  DRIVER_VERSION          0x7
 908 #define  OPTION_ROM_VERSION      0x8
 909 #define  FIRMWARE_VERSION        0x9
 910 #define  OS_NAME_VERSION         0xa
 911 #define  MAX_CT_PAYLOAD_LEN      0xb
 912
 913 /*
 914  * Port Attrubute Types
 915  */
 916 #define  SUPPORTED_FC4_TYPES     0x1
 917 #define  SUPPORTED_SPEED         0x2
 918 #define  PORT_SPEED              0x3
 919 #define  MAX_FRAME_SIZE          0x4
 920 #define  OS_DEVICE_NAME          0x5
 921 #define  HOST_NAME               0x6
 922
 923 union AttributesDef {
 924         /* Structure is in Big Endian format */
 925         struct {
 926                 uint32_t AttrType:16;
 927                 uint32_t AttrLen:16;
 928         } bits;
 929         uint32_t word;
 930 };
 931
 932
 933 /*
 934  * HBA Attribute Entry (8 - 260 bytes)
 935  */
 936 typedef struct {
 937         union AttributesDef ad;
 938         union {
 939                 uint32_t VendorSpecific;
 940                 uint8_t Manufacturer[64];
 941                 uint8_t SerialNumber[64];
 942                 uint8_t Model[256];
 943                 uint8_t ModelDescription[256];
 944                 uint8_t HardwareVersion[256];
 945                 uint8_t DriverVersion[256];
 946                 uint8_t OptionROMVersion[256];
 947                 uint8_t FirmwareVersion[256];
 948                 struct lpfc_name NodeName;
 949                 uint8_t SupportFC4Types[32];
 950                 uint32_t SupportSpeed;
 951                 uint32_t PortSpeed;
 952                 uint32_t MaxFrameSize;
 953                 uint8_t OsDeviceName[256];
 954                 uint8_t OsNameVersion[256];
 955                 uint32_t MaxCTPayloadLen;
 956                 uint8_t HostName[256];
 957         } un;
 958 } ATTRIBUTE_ENTRY;
 959
 960 /*
 961  * HBA Attribute Block
 962  */
 963 typedef struct {
 964         uint32_t EntryCnt;      /* Number of HBA attribute entries */
 965         ATTRIBUTE_ENTRY Entry;  /* Variable-length array */
 966 } ATTRIBUTE_BLOCK;
 967
 968 /*
 969  * Port Entry
 970  */
 971 typedef struct {
 972         struct lpfc_name PortName;
 973 } PORT_ENTRY;
 974
 975 /*
 976  * HBA Identifier
 977  */
 978 typedef struct {
 979         struct lpfc_name PortName;
 980 } HBA_IDENTIFIER;
 981
 982 /*
 983  * Registered Port List Format
 984  */
 985 typedef struct {
 986         uint32_t EntryCnt;
 987         PORT_ENTRY pe;          /* Variable-length array */
 988 } REG_PORT_LIST;
 989
 990 /*
 991  * Register HBA(RHBA)
 992  */
 993 typedef struct {
 994         HBA_IDENTIFIER hi;
 995         REG_PORT_LIST rpl;      /* variable-length array */
 996 /* ATTRIBUTE_BLOCK   ab; */
 997 } REG_HBA;
 998
 999 /*
1000  * Register HBA Attributes (RHAT)
1001  */
1002 typedef struct {
1003         struct lpfc_name HBA_PortName;
1004         ATTRIBUTE_BLOCK ab;
1005 } REG_HBA_ATTRIBUTE;
1006
1007 /*
1008  * Register Port Attributes (RPA)
1009  */
1010 typedef struct {
1011         struct lpfc_name PortName;
1012         ATTRIBUTE_BLOCK ab;
1013 } REG_PORT_ATTRIBUTE;
1014
1015 /*
1016  * Get Registered HBA List (GRHL) Accept Payload Format
1017  */
1018 typedef struct {
1019         uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1020         struct lpfc_name HBA_PortName;  /* Variable-length array */
1021 } GRHL_ACC_PAYLOAD;
1022
1023 /*
1024  * Get Registered Port List (GRPL) Accept Payload Format
1025  */
1026 typedef struct {
1027         uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
1028         PORT_ENTRY Reg_Port_Entry[1];   /* Variable-length array */
1029 } GRPL_ACC_PAYLOAD;
1030
1031 /*
1032  * Get Port Attributes (GPAT) Accept Payload Format
1033  */
1034
1035 typedef struct {
1036         ATTRIBUTE_BLOCK pab;
1037 } GPAT_ACC_PAYLOAD;
1038
1039
1040 /*
1041  *  Begin HBA configuration parameters.
1042  *  The PCI configuration register BAR assignments are:
1043  *  BAR0, offset 0x10 - SLIM base memory address
1044  *  BAR1, offset 0x14 - SLIM base memory high address
1045  *  BAR2, offset 0x18 - REGISTER base memory address
1046  *  BAR3, offset 0x1c - REGISTER base memory high address
1047  *  BAR4, offset 0x20 - BIU I/O registers
1048  *  BAR5, offset 0x24 - REGISTER base io high address
1049  */
1050
1051 /* Number of rings currently used and available. */
1052 #define MAX_CONFIGURED_RINGS     3
1053 #define MAX_RINGS                4
1054
1055 /* IOCB / Mailbox is owned by FireFly */
1056 #define OWN_CHIP        1
1057
1058 /* IOCB / Mailbox is owned by Host */
1059 #define OWN_HOST        0
1060
1061 /* Number of 4-byte words in an IOCB. */
1062 #define IOCB_WORD_SZ    8
1063
1064 /* defines for type field in fc header */
1065 #define FC_ELS_DATA     0x1
1066 #define FC_LLC_SNAP     0x5
1067 #define FC_FCP_DATA     0x8
1068 #define FC_COMMON_TRANSPORT_ULP 0x20
1069
1070 /* defines for rctl field in fc header */
1071 #define FC_DEV_DATA     0x0
1072 #define FC_UNSOL_CTL    0x2
1073 #define FC_SOL_CTL      0x3
1074 #define FC_UNSOL_DATA   0x4
1075 #define FC_FCP_CMND     0x6
1076 #define FC_ELS_REQ      0x22
1077 #define FC_ELS_RSP      0x23
1078
1079 /* network headers for Dfctl field */
1080 #define FC_NET_HDR      0x20
1081
1082 /* Start FireFly Register definitions */
1083 #define PCI_VENDOR_ID_EMULEX        0x10df
1084 #define PCI_DEVICE_ID_FIREFLY       0x1ae5
1085 #define PCI_DEVICE_ID_SAT_SMB       0xf011
1086 #define PCI_DEVICE_ID_SAT_MID       0xf015
1087 #define PCI_DEVICE_ID_RFLY          0xf095
1088 #define PCI_DEVICE_ID_PFLY          0xf098
1089 #define PCI_DEVICE_ID_LP101         0xf0a1
1090 #define PCI_DEVICE_ID_TFLY          0xf0a5
1091 #define PCI_DEVICE_ID_BSMB          0xf0d1
1092 #define PCI_DEVICE_ID_BMID          0xf0d5
1093 #define PCI_DEVICE_ID_ZSMB          0xf0e1
1094 #define PCI_DEVICE_ID_ZMID          0xf0e5
1095 #define PCI_DEVICE_ID_NEPTUNE       0xf0f5
1096 #define PCI_DEVICE_ID_NEPTUNE_SCSP  0xf0f6
1097 #define PCI_DEVICE_ID_NEPTUNE_DCSP  0xf0f7
1098 #define PCI_DEVICE_ID_SAT           0xf100
1099 #define PCI_DEVICE_ID_SAT_SCSP      0xf111
1100 #define PCI_DEVICE_ID_SAT_DCSP      0xf112
1101 #define PCI_DEVICE_ID_SUPERFLY      0xf700
1102 #define PCI_DEVICE_ID_DRAGONFLY     0xf800
1103 #define PCI_DEVICE_ID_CENTAUR       0xf900
1104 #define PCI_DEVICE_ID_PEGASUS       0xf980
1105 #define PCI_DEVICE_ID_THOR          0xfa00
1106 #define PCI_DEVICE_ID_VIPER         0xfb00
1107 #define PCI_DEVICE_ID_LP10000S      0xfc00
1108 #define PCI_DEVICE_ID_LP11000S      0xfc10
1109 #define PCI_DEVICE_ID_LPE11000S     0xfc20
1110 #define PCI_DEVICE_ID_SAT_S         0xfc40
1111 #define PCI_DEVICE_ID_HELIOS        0xfd00
1112 #define PCI_DEVICE_ID_HELIOS_SCSP   0xfd11
1113 #define PCI_DEVICE_ID_HELIOS_DCSP   0xfd12
1114 #define PCI_DEVICE_ID_ZEPHYR        0xfe00
1115 #define PCI_DEVICE_ID_ZEPHYR_SCSP   0xfe11
1116 #define PCI_DEVICE_ID_ZEPHYR_DCSP   0xfe12
1117
1118 #define JEDEC_ID_ADDRESS            0x0080001c
1119 #define FIREFLY_JEDEC_ID            0x1ACC
1120 #define SUPERFLY_JEDEC_ID           0x0020
1121 #define DRAGONFLY_JEDEC_ID          0x0021
1122 #define DRAGONFLY_V2_JEDEC_ID       0x0025
1123 #define CENTAUR_2G_JEDEC_ID         0x0026
1124 #define CENTAUR_1G_JEDEC_ID         0x0028
1125 #define PEGASUS_ORION_JEDEC_ID      0x0036
1126 #define PEGASUS_JEDEC_ID            0x0038
1127 #define THOR_JEDEC_ID               0x0012
1128 #define HELIOS_JEDEC_ID             0x0364
1129 #define ZEPHYR_JEDEC_ID             0x0577
1130 #define VIPER_JEDEC_ID              0x4838
1131 #define SATURN_JEDEC_ID             0x1004
1132
1133 #define JEDEC_ID_MASK               0x0FFFF000
1134 #define JEDEC_ID_SHIFT              12
1135 #define FC_JEDEC_ID(id)             ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1136
1137 typedef struct {                /* FireFly BIU registers */
1138         uint32_t hostAtt;       /* See definitions for Host Attention
1139                                    register */
1140         uint32_t chipAtt;       /* See definitions for Chip Attention
1141                                    register */
1142         uint32_t hostStatus;    /* See definitions for Host Status register */
1143         uint32_t hostControl;   /* See definitions for Host Control register */
1144         uint32_t buiConfig;     /* See definitions for BIU configuration
1145                                    register */
1146 } FF_REGS;
1147
1148 /* IO Register size in bytes */
1149 #define FF_REG_AREA_SIZE       256
1150
1151 /* Host Attention Register */
1152
1153 #define HA_REG_OFFSET  0        /* Byte offset from register base address */
1154
1155 #define HA_R0RE_REQ    0x00000001       /* Bit  0 */
1156 #define HA_R0CE_RSP    0x00000002       /* Bit  1 */
1157 #define HA_R0ATT       0x00000008       /* Bit  3 */
1158 #define HA_R1RE_REQ    0x00000010       /* Bit  4 */
1159 #define HA_R1CE_RSP    0x00000020       /* Bit  5 */
1160 #define HA_R1ATT       0x00000080       /* Bit  7 */
1161 #define HA_R2RE_REQ    0x00000100       /* Bit  8 */
1162 #define HA_R2CE_RSP    0x00000200       /* Bit  9 */
1163 #define HA_R2ATT       0x00000800       /* Bit 11 */
1164 #define HA_R3RE_REQ    0x00001000       /* Bit 12 */
1165 #define HA_R3CE_RSP    0x00002000       /* Bit 13 */
1166 #define HA_R3ATT       0x00008000       /* Bit 15 */
1167 #define HA_LATT        0x20000000       /* Bit 29 */
1168 #define HA_MBATT       0x40000000       /* Bit 30 */
1169 #define HA_ERATT       0x80000000       /* Bit 31 */
1170
1171 #define HA_RXRE_REQ    0x00000001       /* Bit  0 */
1172 #define HA_RXCE_RSP    0x00000002       /* Bit  1 */
1173 #define HA_RXATT       0x00000008       /* Bit  3 */
1174 #define HA_RXMASK      0x0000000f
1175
1176 /* Chip Attention Register */
1177
1178 #define CA_REG_OFFSET  4        /* Byte offset from register base address */
1179
1180 #define CA_R0CE_REQ    0x00000001       /* Bit  0 */
1181 #define CA_R0RE_RSP    0x00000002       /* Bit  1 */
1182 #define CA_R0ATT       0x00000008       /* Bit  3 */
1183 #define CA_R1CE_REQ    0x00000010       /* Bit  4 */
1184 #define CA_R1RE_RSP    0x00000020       /* Bit  5 */
1185 #define CA_R1ATT       0x00000080       /* Bit  7 */
1186 #define CA_R2CE_REQ    0x00000100       /* Bit  8 */
1187 #define CA_R2RE_RSP    0x00000200       /* Bit  9 */
1188 #define CA_R2ATT       0x00000800       /* Bit 11 */
1189 #define CA_R3CE_REQ    0x00001000       /* Bit 12 */
1190 #define CA_R3RE_RSP    0x00002000       /* Bit 13 */
1191 #define CA_R3ATT       0x00008000       /* Bit 15 */
1192 #define CA_MBATT       0x40000000       /* Bit 30 */
1193
1194 /* Host Status Register */
1195
1196 #define HS_REG_OFFSET  8        /* Byte offset from register base address */
1197
1198 #define HS_MBRDY       0x00400000       /* Bit 22 */
1199 #define HS_FFRDY       0x00800000       /* Bit 23 */
1200 #define HS_FFER8       0x01000000       /* Bit 24 */
1201 #define HS_FFER7       0x02000000       /* Bit 25 */
1202 #define HS_FFER6       0x04000000       /* Bit 26 */
1203 #define HS_FFER5       0x08000000       /* Bit 27 */
1204 #define HS_FFER4       0x10000000       /* Bit 28 */
1205 #define HS_FFER3       0x20000000       /* Bit 29 */
1206 #define HS_FFER2       0x40000000       /* Bit 30 */
1207 #define HS_FFER1       0x80000000       /* Bit 31 */
1208 #define HS_FFERM       0xFF000000       /* Mask for error bits 31:24 */
1209
1210 /* Host Control Register */
1211
1212 #define HC_REG_OFFSET  12       /* Word offset from register base address */
1213
1214 #define HC_MBINT_ENA   0x00000001       /* Bit  0 */
1215 #define HC_R0INT_ENA   0x00000002       /* Bit  1 */
1216 #define HC_R1INT_ENA   0x00000004       /* Bit  2 */
1217 #define HC_R2INT_ENA   0x00000008       /* Bit  3 */
1218 #define HC_R3INT_ENA   0x00000010       /* Bit  4 */
1219 #define HC_INITHBI     0x02000000       /* Bit 25 */
1220 #define HC_INITMB      0x04000000       /* Bit 26 */
1221 #define HC_INITFF      0x08000000       /* Bit 27 */
1222 #define HC_LAINT_ENA   0x20000000       /* Bit 29 */
1223 #define HC_ERINT_ENA   0x80000000       /* Bit 31 */
1224
1225 /* Mailbox Commands */
1226 #define MBX_SHUTDOWN        0x00        /* terminate testing */
1227 #define MBX_LOAD_SM         0x01
1228 #define MBX_READ_NV         0x02
1229 #define MBX_WRITE_NV        0x03
1230 #define MBX_RUN_BIU_DIAG    0x04
1231 #define MBX_INIT_LINK       0x05
1232 #define MBX_DOWN_LINK       0x06
1233 #define MBX_CONFIG_LINK     0x07
1234 #define MBX_CONFIG_RING     0x09
1235 #define MBX_RESET_RING      0x0A
1236 #define MBX_READ_CONFIG     0x0B
1237 #define MBX_READ_RCONFIG    0x0C
1238 #define MBX_READ_SPARM      0x0D
1239 #define MBX_READ_STATUS     0x0E
1240 #define MBX_READ_RPI        0x0F
1241 #define MBX_READ_XRI        0x10
1242 #define MBX_READ_REV        0x11
1243 #define MBX_READ_LNK_STAT   0x12
1244 #define MBX_REG_LOGIN       0x13
1245 #define MBX_UNREG_LOGIN     0x14
1246 #define MBX_READ_LA         0x15
1247 #define MBX_CLEAR_LA        0x16
1248 #define MBX_DUMP_MEMORY     0x17
1249 #define MBX_DUMP_CONTEXT    0x18
1250 #define MBX_RUN_DIAGS       0x19
1251 #define MBX_RESTART         0x1A
1252 #define MBX_UPDATE_CFG      0x1B
1253 #define MBX_DOWN_LOAD       0x1C
1254 #define MBX_DEL_LD_ENTRY    0x1D
1255 #define MBX_RUN_PROGRAM     0x1E
1256 #define MBX_SET_MASK        0x20
1257 #define MBX_SET_SLIM        0x21
1258 #define MBX_UNREG_D_ID      0x23
1259 #define MBX_KILL_BOARD      0x24
1260 #define MBX_CONFIG_FARP     0x25
1261 #define MBX_BEACON          0x2A
1262
1263 #define MBX_CONFIG_HBQ      0x7C
1264 #define MBX_LOAD_AREA       0x81
1265 #define MBX_RUN_BIU_DIAG64  0x84
1266 #define MBX_CONFIG_PORT     0x88
1267 #define MBX_READ_SPARM64    0x8D
1268 #define MBX_READ_RPI64      0x8F
1269 #define MBX_REG_LOGIN64     0x93
1270 #define MBX_READ_LA64       0x95
1271
1272 #define MBX_FLASH_WR_ULA    0x98
1273 #define MBX_SET_DEBUG       0x99
1274 #define MBX_LOAD_EXP_ROM    0x9C
1275
1276 #define MBX_MAX_CMDS        0x9D
1277 #define MBX_SLI2_CMD_MASK   0x80
1278
1279 /* IOCB Commands */
1280
1281 #define CMD_RCV_SEQUENCE_CX     0x01
1282 #define CMD_XMIT_SEQUENCE_CR    0x02
1283 #define CMD_XMIT_SEQUENCE_CX    0x03
1284 #define CMD_XMIT_BCAST_CN       0x04
1285 #define CMD_XMIT_BCAST_CX       0x05
1286 #define CMD_QUE_RING_BUF_CN     0x06
1287 #define CMD_QUE_XRI_BUF_CX      0x07
1288 #define CMD_IOCB_CONTINUE_CN    0x08
1289 #define CMD_RET_XRI_BUF_CX      0x09
1290 #define CMD_ELS_REQUEST_CR      0x0A
1291 #define CMD_ELS_REQUEST_CX      0x0B
1292 #define CMD_RCV_ELS_REQ_CX      0x0D
1293 #define CMD_ABORT_XRI_CN        0x0E
1294 #define CMD_ABORT_XRI_CX        0x0F
1295 #define CMD_CLOSE_XRI_CN        0x10
1296 #define CMD_CLOSE_XRI_CX        0x11
1297 #define CMD_CREATE_XRI_CR       0x12
1298 #define CMD_CREATE_XRI_CX       0x13
1299 #define CMD_GET_RPI_CN          0x14
1300 #define CMD_XMIT_ELS_RSP_CX     0x15
1301 #define CMD_GET_RPI_CR          0x16
1302 #define CMD_XRI_ABORTED_CX      0x17
1303 #define CMD_FCP_IWRITE_CR       0x18
1304 #define CMD_FCP_IWRITE_CX       0x19
1305 #define CMD_FCP_IREAD_CR        0x1A
1306 #define CMD_FCP_IREAD_CX        0x1B
1307 #define CMD_FCP_ICMND_CR        0x1C
1308 #define CMD_FCP_ICMND_CX        0x1D
1309 #define CMD_FCP_TSEND_CX        0x1F
1310 #define CMD_FCP_TRECEIVE_CX     0x21
1311 #define CMD_FCP_TRSP_CX         0x23
1312 #define CMD_FCP_AUTO_TRSP_CX    0x29
1313
1314 #define CMD_ADAPTER_MSG         0x20
1315 #define CMD_ADAPTER_DUMP        0x22
1316
1317 /*  SLI_2 IOCB Command Set */
1318
1319 #define CMD_RCV_SEQUENCE64_CX   0x81
1320 #define CMD_XMIT_SEQUENCE64_CR  0x82
1321 #define CMD_XMIT_SEQUENCE64_CX  0x83
1322 #define CMD_XMIT_BCAST64_CN     0x84
1323 #define CMD_XMIT_BCAST64_CX     0x85
1324 #define CMD_QUE_RING_BUF64_CN   0x86
1325 #define CMD_QUE_XRI_BUF64_CX    0x87
1326 #define CMD_IOCB_CONTINUE64_CN  0x88
1327 #define CMD_RET_XRI_BUF64_CX    0x89
1328 #define CMD_ELS_REQUEST64_CR    0x8A
1329 #define CMD_ELS_REQUEST64_CX    0x8B
1330 #define CMD_ABORT_MXRI64_CN     0x8C
1331 #define CMD_RCV_ELS_REQ64_CX    0x8D
1332 #define CMD_XMIT_ELS_RSP64_CX   0x95
1333 #define CMD_FCP_IWRITE64_CR     0x98
1334 #define CMD_FCP_IWRITE64_CX     0x99
1335 #define CMD_FCP_IREAD64_CR      0x9A
1336 #define CMD_FCP_IREAD64_CX      0x9B
1337 #define CMD_FCP_ICMND64_CR      0x9C
1338 #define CMD_FCP_ICMND64_CX      0x9D
1339 #define CMD_FCP_TSEND64_CX      0x9F
1340 #define CMD_FCP_TRECEIVE64_CX   0xA1
1341 #define CMD_FCP_TRSP64_CX       0xA3
1342
1343 #define CMD_IOCB_RCV_SEQ64_CX   0xB5
1344 #define CMD_IOCB_RCV_ELS64_CX   0xB7
1345 #define CMD_IOCB_RCV_CONT64_CX  0xBB
1346
1347 #define CMD_GEN_REQUEST64_CR    0xC2
1348 #define CMD_GEN_REQUEST64_CX    0xC3
1349
1350 #define CMD_MAX_IOCB_CMD        0xE6
1351 #define CMD_IOCB_MASK           0xff
1352
1353 #define MAX_MSG_DATA            28      /* max msg data in CMD_ADAPTER_MSG
1354                                            iocb */
1355 #define LPFC_MAX_ADPTMSG         32     /* max msg data */
1356 /*
1357  *  Define Status
1358  */
1359 #define MBX_SUCCESS                 0
1360 #define MBXERR_NUM_RINGS            1
1361 #define MBXERR_NUM_IOCBS            2
1362 #define MBXERR_IOCBS_EXCEEDED       3
1363 #define MBXERR_BAD_RING_NUMBER      4
1364 #define MBXERR_MASK_ENTRIES_RANGE   5
1365 #define MBXERR_MASKS_EXCEEDED       6
1366 #define MBXERR_BAD_PROFILE          7
1367 #define MBXERR_BAD_DEF_CLASS        8
1368 #define MBXERR_BAD_MAX_RESPONDER    9
1369 #define MBXERR_BAD_MAX_ORIGINATOR   10
1370 #define MBXERR_RPI_REGISTERED       11
1371 #define MBXERR_RPI_FULL             12
1372 #define MBXERR_NO_RESOURCES         13
1373 #define MBXERR_BAD_RCV_LENGTH       14
1374 #define MBXERR_DMA_ERROR            15
1375 #define MBXERR_ERROR                16
1376 #define MBX_NOT_FINISHED           255
1377
1378 #define MBX_BUSY                   0xffffff /* Attempted cmd to busy Mailbox */
1379 #define MBX_TIMEOUT                0xfffffe /* time-out expired waiting for */
1380
1381 /*
1382  *    Begin Structure Definitions for Mailbox Commands
1383  */
1384
1385 typedef struct {
1386 #ifdef __BIG_ENDIAN_BITFIELD
1387         uint8_t tval;
1388         uint8_t tmask;
1389         uint8_t rval;
1390         uint8_t rmask;
1391 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1392         uint8_t rmask;
1393         uint8_t rval;
1394         uint8_t tmask;
1395         uint8_t tval;
1396 #endif
1397 } RR_REG;
1398
1399 struct ulp_bde {
1400         uint32_t bdeAddress;
1401 #ifdef __BIG_ENDIAN_BITFIELD
1402         uint32_t bdeReserved:4;
1403         uint32_t bdeAddrHigh:4;
1404         uint32_t bdeSize:24;
1405 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1406         uint32_t bdeSize:24;
1407         uint32_t bdeAddrHigh:4;
1408         uint32_t bdeReserved:4;
1409 #endif
1410 };
1411
1412 struct ulp_bde64 {      /* SLI-2 */
1413         union ULP_BDE_TUS {
1414                 uint32_t w;
1415                 struct {
1416 #ifdef __BIG_ENDIAN_BITFIELD
1417                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
1418                                                    VALUE !! */
1419                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
1420 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1421                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
1422                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
1423                                                    VALUE !! */
1424 #endif
1425
1426 #define BUFF_USE_RSVD       0x01        /* bdeFlags */
1427 #define BUFF_USE_INTRPT     0x02        /* Not Implemented with LP6000 */
1428 #define BUFF_USE_CMND       0x04        /* Optional, 1=cmd/rsp 0=data buffer */
1429 #define BUFF_USE_RCV        0x08        /*  "" "", 1=rcv buffer, 0=xmit
1430                                             buffer */
1431 #define BUFF_TYPE_32BIT     0x10        /*  "" "", 1=32 bit addr 0=64 bit
1432                                             addr */
1433 #define BUFF_TYPE_SPECIAL   0x20        /* Not Implemented with LP6000  */
1434 #define BUFF_TYPE_BDL       0x40        /* Optional,  may be set in BDL */
1435 #define BUFF_TYPE_INVALID   0x80        /*  ""  "" */
1436                 } f;
1437         } tus;
1438         uint32_t addrLow;
1439         uint32_t addrHigh;
1440 };
1441 #define BDE64_SIZE_WORD 0
1442 #define BPL64_SIZE_WORD 0x40
1443
1444 typedef struct ULP_BDL {        /* SLI-2 */
1445 #ifdef __BIG_ENDIAN_BITFIELD
1446         uint32_t bdeFlags:8;    /* BDL Flags */
1447         uint32_t bdeSize:24;    /* Size of BDL array in host memory (bytes) */
1448 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1449         uint32_t bdeSize:24;    /* Size of BDL array in host memory (bytes) */
1450         uint32_t bdeFlags:8;    /* BDL Flags */
1451 #endif
1452
1453         uint32_t addrLow;       /* Address 0:31 */
1454         uint32_t addrHigh;      /* Address 32:63 */
1455         uint32_t ulpIoTag32;    /* Can be used for 32 bit I/O Tag */
1456 } ULP_BDL;
1457
1458 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1459
1460 typedef struct {
1461 #ifdef __BIG_ENDIAN_BITFIELD
1462         uint32_t rsvd2:25;
1463         uint32_t acknowledgment:1;
1464         uint32_t version:1;
1465         uint32_t erase_or_prog:1;
1466         uint32_t update_flash:1;
1467         uint32_t update_ram:1;
1468         uint32_t method:1;
1469         uint32_t load_cmplt:1;
1470 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1471         uint32_t load_cmplt:1;
1472         uint32_t method:1;
1473         uint32_t update_ram:1;
1474         uint32_t update_flash:1;
1475         uint32_t erase_or_prog:1;
1476         uint32_t version:1;
1477         uint32_t acknowledgment:1;
1478         uint32_t rsvd2:25;
1479 #endif
1480
1481         uint32_t dl_to_adr_low;
1482         uint32_t dl_to_adr_high;
1483         uint32_t dl_len;
1484         union {
1485                 uint32_t dl_from_mbx_offset;
1486                 struct ulp_bde dl_from_bde;
1487                 struct ulp_bde64 dl_from_bde64;
1488         } un;
1489
1490 } LOAD_SM_VAR;
1491
1492 /* Structure for MB Command READ_NVPARM (02) */
1493
1494 typedef struct {
1495         uint32_t rsvd1[3];      /* Read as all one's */
1496         uint32_t rsvd2;         /* Read as all zero's */
1497         uint32_t portname[2];   /* N_PORT name */
1498         uint32_t nodename[2];   /* NODE name */
1499
1500 #ifdef __BIG_ENDIAN_BITFIELD
1501         uint32_t pref_DID:24;
1502         uint32_t hardAL_PA:8;
1503 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1504         uint32_t hardAL_PA:8;
1505         uint32_t pref_DID:24;
1506 #endif
1507
1508         uint32_t rsvd3[21];     /* Read as all one's */
1509 } READ_NV_VAR;
1510
1511 /* Structure for MB Command WRITE_NVPARMS (03) */
1512
1513 typedef struct {
1514         uint32_t rsvd1[3];      /* Must be all one's */
1515         uint32_t rsvd2;         /* Must be all zero's */
1516         uint32_t portname[2];   /* N_PORT name */
1517         uint32_t nodename[2];   /* NODE name */
1518
1519 #ifdef __BIG_ENDIAN_BITFIELD
1520         uint32_t pref_DID:24;
1521         uint32_t hardAL_PA:8;
1522 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1523         uint32_t hardAL_PA:8;
1524         uint32_t pref_DID:24;
1525 #endif
1526
1527         uint32_t rsvd3[21];     /* Must be all one's */
1528 } WRITE_NV_VAR;
1529
1530 /* Structure for MB Command RUN_BIU_DIAG (04) */
1531 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1532
1533 typedef struct {
1534         uint32_t rsvd1;
1535         union {
1536                 struct {
1537                         struct ulp_bde xmit_bde;
1538                         struct ulp_bde rcv_bde;
1539                 } s1;
1540                 struct {
1541                         struct ulp_bde64 xmit_bde64;
1542                         struct ulp_bde64 rcv_bde64;
1543                 } s2;
1544         } un;
1545 } BIU_DIAG_VAR;
1546
1547 /* Structure for MB Command INIT_LINK (05) */
1548
1549 typedef struct {
1550 #ifdef __BIG_ENDIAN_BITFIELD
1551         uint32_t rsvd1:24;
1552         uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1553 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1554         uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1555         uint32_t rsvd1:24;
1556 #endif
1557
1558 #ifdef __BIG_ENDIAN_BITFIELD
1559         uint8_t fabric_AL_PA;   /* If using a Fabric Assigned AL_PA */
1560         uint8_t rsvd2;
1561         uint16_t link_flags;
1562 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1563         uint16_t link_flags;
1564         uint8_t rsvd2;
1565         uint8_t fabric_AL_PA;   /* If using a Fabric Assigned AL_PA */
1566 #endif
1567
1568 #define FLAGS_LOCAL_LB               0x01 /* link_flags (=1) ENDEC loopback */
1569 #define FLAGS_TOPOLOGY_MODE_LOOP_PT  0x00 /* Attempt loop then pt-pt */
1570 #define FLAGS_TOPOLOGY_MODE_PT_PT    0x02 /* Attempt pt-pt only */
1571 #define FLAGS_TOPOLOGY_MODE_LOOP     0x04 /* Attempt loop only */
1572 #define FLAGS_TOPOLOGY_MODE_PT_LOOP  0x06 /* Attempt pt-pt then loop */
1573 #define FLAGS_UNREG_LOGIN_ALL        0x08 /* UNREG_LOGIN all on link down */
1574 #define FLAGS_LIRP_LILP              0x80 /* LIRP / LILP is disabled */
1575
1576 #define FLAGS_TOPOLOGY_FAILOVER      0x0400     /* Bit 10 */
1577 #define FLAGS_LINK_SPEED             0x0800     /* Bit 11 */
1578 #define FLAGS_IMED_ABORT             0x04000    /* Bit 14 */
1579
1580         uint32_t link_speed;
1581 #define LINK_SPEED_AUTO 0       /* Auto selection */
1582 #define LINK_SPEED_1G   1       /* 1 Gigabaud */
1583 #define LINK_SPEED_2G   2       /* 2 Gigabaud */
1584 #define LINK_SPEED_4G   4       /* 4 Gigabaud */
1585 #define LINK_SPEED_8G   8       /* 8 Gigabaud */
1586 #define LINK_SPEED_10G   16      /* 10 Gigabaud */
1587
1588 } INIT_LINK_VAR;
1589
1590 /* Structure for MB Command DOWN_LINK (06) */
1591
1592 typedef struct {
1593         uint32_t rsvd1;
1594 } DOWN_LINK_VAR;
1595
1596 /* Structure for MB Command CONFIG_LINK (07) */
1597
1598 typedef struct {
1599 #ifdef __BIG_ENDIAN_BITFIELD
1600         uint32_t cr:1;
1601         uint32_t ci:1;
1602         uint32_t cr_delay:6;
1603         uint32_t cr_count:8;
1604         uint32_t rsvd1:8;
1605         uint32_t MaxBBC:8;
1606 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1607         uint32_t MaxBBC:8;
1608         uint32_t rsvd1:8;
1609         uint32_t cr_count:8;
1610         uint32_t cr_delay:6;
1611         uint32_t ci:1;
1612         uint32_t cr:1;
1613 #endif
1614
1615         uint32_t myId;
1616         uint32_t rsvd2;
1617         uint32_t edtov;
1618         uint32_t arbtov;
1619         uint32_t ratov;
1620         uint32_t rttov;
1621         uint32_t altov;
1622         uint32_t crtov;
1623         uint32_t citov;
1624 #ifdef __BIG_ENDIAN_BITFIELD
1625         uint32_t rrq_enable:1;
1626         uint32_t rrq_immed:1;
1627         uint32_t rsvd4:29;
1628         uint32_t ack0_enable:1;
1629 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1630         uint32_t ack0_enable:1;
1631         uint32_t rsvd4:29;
1632         uint32_t rrq_immed:1;
1633         uint32_t rrq_enable:1;
1634 #endif
1635 } CONFIG_LINK;
1636
1637 /* Structure for MB Command PART_SLIM (08)
1638  * will be removed since SLI1 is no longer supported!
1639  */
1640 typedef struct {
1641 #ifdef __BIG_ENDIAN_BITFIELD
1642         uint16_t offCiocb;
1643         uint16_t numCiocb;
1644         uint16_t offRiocb;
1645         uint16_t numRiocb;
1646 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1647         uint16_t numCiocb;
1648         uint16_t offCiocb;
1649         uint16_t numRiocb;
1650         uint16_t offRiocb;
1651 #endif
1652 } RING_DEF;
1653
1654 typedef struct {
1655 #ifdef __BIG_ENDIAN_BITFIELD
1656         uint32_t unused1:24;
1657         uint32_t numRing:8;
1658 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1659         uint32_t numRing:8;
1660         uint32_t unused1:24;
1661 #endif
1662
1663         RING_DEF ringdef[4];
1664         uint32_t hbainit;
1665 } PART_SLIM_VAR;
1666
1667 /* Structure for MB Command CONFIG_RING (09) */
1668
1669 typedef struct {
1670 #ifdef __BIG_ENDIAN_BITFIELD
1671         uint32_t unused2:6;
1672         uint32_t recvSeq:1;
1673         uint32_t recvNotify:1;
1674         uint32_t numMask:8;
1675         uint32_t profile:8;
1676         uint32_t unused1:4;
1677         uint32_t ring:4;
1678 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1679         uint32_t ring:4;
1680         uint32_t unused1:4;
1681         uint32_t profile:8;
1682         uint32_t numMask:8;
1683         uint32_t recvNotify:1;
1684         uint32_t recvSeq:1;
1685         uint32_t unused2:6;
1686 #endif
1687
1688 #ifdef __BIG_ENDIAN_BITFIELD
1689         uint16_t maxRespXchg;
1690         uint16_t maxOrigXchg;
1691 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1692         uint16_t maxOrigXchg;
1693         uint16_t maxRespXchg;
1694 #endif
1695
1696         RR_REG rrRegs[6];
1697 } CONFIG_RING_VAR;
1698
1699 /* Structure for MB Command RESET_RING (10) */
1700
1701 typedef struct {
1702         uint32_t ring_no;
1703 } RESET_RING_VAR;
1704
1705 /* Structure for MB Command READ_CONFIG (11) */
1706
1707 typedef struct {
1708 #ifdef __BIG_ENDIAN_BITFIELD
1709         uint32_t cr:1;
1710         uint32_t ci:1;
1711         uint32_t cr_delay:6;
1712         uint32_t cr_count:8;
1713         uint32_t InitBBC:8;
1714         uint32_t MaxBBC:8;
1715 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1716         uint32_t MaxBBC:8;
1717         uint32_t InitBBC:8;
1718         uint32_t cr_count:8;
1719         uint32_t cr_delay:6;
1720         uint32_t ci:1;
1721         uint32_t cr:1;
1722 #endif
1723
1724 #ifdef __BIG_ENDIAN_BITFIELD
1725         uint32_t topology:8;
1726         uint32_t myDid:24;
1727 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1728         uint32_t myDid:24;
1729         uint32_t topology:8;
1730 #endif
1731
1732         /* Defines for topology (defined previously) */
1733 #ifdef __BIG_ENDIAN_BITFIELD
1734         uint32_t AR:1;
1735         uint32_t IR:1;
1736         uint32_t rsvd1:29;
1737         uint32_t ack0:1;
1738 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1739         uint32_t ack0:1;
1740         uint32_t rsvd1:29;
1741         uint32_t IR:1;
1742         uint32_t AR:1;
1743 #endif
1744
1745         uint32_t edtov;
1746         uint32_t arbtov;
1747         uint32_t ratov;
1748         uint32_t rttov;
1749         uint32_t altov;
1750         uint32_t lmt;
1751 #define LMT_RESERVED  0x000    /* Not used */
1752 #define LMT_1Gb       0x004
1753 #define LMT_2Gb       0x008
1754 #define LMT_4Gb       0x040
1755 #define LMT_8Gb       0x080
1756 #define LMT_10Gb      0x100
1757
1758
1759         uint32_t rsvd2;
1760         uint32_t rsvd3;
1761         uint32_t max_xri;
1762         uint32_t max_iocb;
1763         uint32_t max_rpi;
1764         uint32_t avail_xri;
1765         uint32_t avail_iocb;
1766         uint32_t avail_rpi;
1767         uint32_t default_rpi;
1768 } READ_CONFIG_VAR;
1769
1770 /* Structure for MB Command READ_RCONFIG (12) */
1771
1772 typedef struct {
1773 #ifdef __BIG_ENDIAN_BITFIELD
1774         uint32_t rsvd2:7;
1775         uint32_t recvNotify:1;
1776         uint32_t numMask:8;
1777         uint32_t profile:8;
1778         uint32_t rsvd1:4;
1779         uint32_t ring:4;
1780 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1781         uint32_t ring:4;
1782         uint32_t rsvd1:4;
1783         uint32_t profile:8;
1784         uint32_t numMask:8;
1785         uint32_t recvNotify:1;
1786         uint32_t rsvd2:7;
1787 #endif
1788
1789 #ifdef __BIG_ENDIAN_BITFIELD
1790         uint16_t maxResp;
1791         uint16_t maxOrig;
1792 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1793         uint16_t maxOrig;
1794         uint16_t maxResp;
1795 #endif
1796
1797         RR_REG rrRegs[6];
1798
1799 #ifdef __BIG_ENDIAN_BITFIELD
1800         uint16_t cmdRingOffset;
1801         uint16_t cmdEntryCnt;
1802         uint16_t rspRingOffset;
1803         uint16_t rspEntryCnt;
1804         uint16_t nextCmdOffset;
1805         uint16_t rsvd3;
1806         uint16_t nextRspOffset;
1807         uint16_t rsvd4;
1808 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1809         uint16_t cmdEntryCnt;
1810         uint16_t cmdRingOffset;
1811         uint16_t rspEntryCnt;
1812         uint16_t rspRingOffset;
1813         uint16_t rsvd3;
1814         uint16_t nextCmdOffset;
1815         uint16_t rsvd4;
1816         uint16_t nextRspOffset;
1817 #endif
1818 } READ_RCONF_VAR;
1819
1820 /* Structure for MB Command READ_SPARM (13) */
1821 /* Structure for MB Command READ_SPARM64 (0x8D) */
1822
1823 typedef struct {
1824         uint32_t rsvd1;
1825         uint32_t rsvd2;
1826         union {
1827                 struct ulp_bde sp; /* This BDE points to struct serv_parm
1828                                       structure */
1829                 struct ulp_bde64 sp64;
1830         } un;
1831 #ifdef __BIG_ENDIAN_BITFIELD
1832         uint16_t rsvd3;
1833         uint16_t vpi;
1834 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1835         uint16_t vpi;
1836         uint16_t rsvd3;
1837 #endif
1838 } READ_SPARM_VAR;
1839
1840 /* Structure for MB Command READ_STATUS (14) */
1841
1842 typedef struct {
1843 #ifdef __BIG_ENDIAN_BITFIELD
1844         uint32_t rsvd1:31;
1845         uint32_t clrCounters:1;
1846         uint16_t activeXriCnt;
1847         uint16_t activeRpiCnt;
1848 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1849         uint32_t clrCounters:1;
1850         uint32_t rsvd1:31;
1851         uint16_t activeRpiCnt;
1852         uint16_t activeXriCnt;
1853 #endif
1854
1855         uint32_t xmitByteCnt;
1856         uint32_t rcvByteCnt;
1857         uint32_t xmitFrameCnt;
1858         uint32_t rcvFrameCnt;
1859         uint32_t xmitSeqCnt;
1860         uint32_t rcvSeqCnt;
1861         uint32_t totalOrigExchanges;
1862         uint32_t totalRespExchanges;
1863         uint32_t rcvPbsyCnt;
1864         uint32_t rcvFbsyCnt;
1865 } READ_STATUS_VAR;
1866
1867 /* Structure for MB Command READ_RPI (15) */
1868 /* Structure for MB Command READ_RPI64 (0x8F) */
1869
1870 typedef struct {
1871 #ifdef __BIG_ENDIAN_BITFIELD
1872         uint16_t nextRpi;
1873         uint16_t reqRpi;
1874         uint32_t rsvd2:8;
1875         uint32_t DID:24;
1876 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1877         uint16_t reqRpi;
1878         uint16_t nextRpi;
1879         uint32_t DID:24;
1880         uint32_t rsvd2:8;
1881 #endif
1882
1883         union {
1884                 struct ulp_bde sp;
1885                 struct ulp_bde64 sp64;
1886         } un;
1887
1888 } READ_RPI_VAR;
1889
1890 /* Structure for MB Command READ_XRI (16) */
1891
1892 typedef struct {
1893 #ifdef __BIG_ENDIAN_BITFIELD
1894         uint16_t nextXri;
1895         uint16_t reqXri;
1896         uint16_t rsvd1;
1897         uint16_t rpi;
1898         uint32_t rsvd2:8;
1899         uint32_t DID:24;
1900         uint32_t rsvd3:8;
1901         uint32_t SID:24;
1902         uint32_t rsvd4;
1903         uint8_t seqId;
1904         uint8_t rsvd5;
1905         uint16_t seqCount;
1906         uint16_t oxId;
1907         uint16_t rxId;
1908         uint32_t rsvd6:30;
1909         uint32_t si:1;
1910         uint32_t exchOrig:1;
1911 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1912         uint16_t reqXri;
1913         uint16_t nextXri;
1914         uint16_t rpi;
1915         uint16_t rsvd1;
1916         uint32_t DID:24;
1917         uint32_t rsvd2:8;
1918         uint32_t SID:24;
1919         uint32_t rsvd3:8;
1920         uint32_t rsvd4;
1921         uint16_t seqCount;
1922         uint8_t rsvd5;
1923         uint8_t seqId;
1924         uint16_t rxId;
1925         uint16_t oxId;
1926         uint32_t exchOrig:1;
1927         uint32_t si:1;
1928         uint32_t rsvd6:30;
1929 #endif
1930 } READ_XRI_VAR;
1931
1932 /* Structure for MB Command READ_REV (17) */
1933
1934 typedef struct {
1935 #ifdef __BIG_ENDIAN_BITFIELD
1936         uint32_t cv:1;
1937         uint32_t rr:1;
1938         uint32_t rsvd2:2;
1939         uint32_t v3req:1;
1940         uint32_t v3rsp:1;
1941         uint32_t rsvd1:25;
1942         uint32_t rv:1;
1943 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1944         uint32_t rv:1;
1945         uint32_t rsvd1:25;
1946         uint32_t v3rsp:1;
1947         uint32_t v3req:1;
1948         uint32_t rsvd2:2;
1949         uint32_t rr:1;
1950         uint32_t cv:1;
1951 #endif
1952
1953         uint32_t biuRev;
1954         uint32_t smRev;
1955         union {
1956                 uint32_t smFwRev;
1957                 struct {
1958 #ifdef __BIG_ENDIAN_BITFIELD
1959                         uint8_t ProgType;
1960                         uint8_t ProgId;
1961                         uint16_t ProgVer:4;
1962                         uint16_t ProgRev:4;
1963                         uint16_t ProgFixLvl:2;
1964                         uint16_t ProgDistType:2;
1965                         uint16_t DistCnt:4;
1966 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1967                         uint16_t DistCnt:4;
1968                         uint16_t ProgDistType:2;
1969                         uint16_t ProgFixLvl:2;
1970                         uint16_t ProgRev:4;
1971                         uint16_t ProgVer:4;
1972                         uint8_t ProgId;
1973                         uint8_t ProgType;
1974 #endif
1975
1976                 } b;
1977         } un;
1978         uint32_t endecRev;
1979 #ifdef __BIG_ENDIAN_BITFIELD
1980         uint8_t feaLevelHigh;
1981         uint8_t feaLevelLow;
1982         uint8_t fcphHigh;
1983         uint8_t fcphLow;
1984 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1985         uint8_t fcphLow;
1986         uint8_t fcphHigh;
1987         uint8_t feaLevelLow;
1988         uint8_t feaLevelHigh;
1989 #endif
1990
1991         uint32_t postKernRev;
1992         uint32_t opFwRev;
1993         uint8_t opFwName[16];
1994         uint32_t sli1FwRev;
1995         uint8_t sli1FwName[16];
1996         uint32_t sli2FwRev;
1997         uint8_t sli2FwName[16];
1998         uint32_t sli3Feat;
1999         uint32_t RandomData[6];
2000 } READ_REV_VAR;
2001
2002 /* Structure for MB Command READ_LINK_STAT (18) */
2003
2004 typedef struct {
2005         uint32_t rsvd1;
2006         uint32_t linkFailureCnt;
2007         uint32_t lossSyncCnt;
2008
2009         uint32_t lossSignalCnt;
2010         uint32_t primSeqErrCnt;
2011         uint32_t invalidXmitWord;
2012         uint32_t crcCnt;
2013         uint32_t primSeqTimeout;
2014         uint32_t elasticOverrun;
2015         uint32_t arbTimeout;
2016 } READ_LNK_VAR;
2017
2018 /* Structure for MB Command REG_LOGIN (19) */
2019 /* Structure for MB Command REG_LOGIN64 (0x93) */
2020
2021 typedef struct {
2022 #ifdef __BIG_ENDIAN_BITFIELD
2023         uint16_t rsvd1;
2024         uint16_t rpi;
2025         uint32_t rsvd2:8;
2026         uint32_t did:24;
2027 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2028         uint16_t rpi;
2029         uint16_t rsvd1;
2030         uint32_t did:24;
2031         uint32_t rsvd2:8;
2032 #endif
2033
2034         union {
2035                 struct ulp_bde sp;
2036                 struct ulp_bde64 sp64;
2037         } un;
2038
2039 #ifdef __BIG_ENDIAN_BITFIELD
2040         uint16_t rsvd6;
2041         uint16_t vpi;
2042 #else /* __LITTLE_ENDIAN_BITFIELD */
2043         uint16_t vpi;
2044         uint16_t rsvd6;
2045 #endif
2046
2047 } REG_LOGIN_VAR;
2048
2049 /* Word 30 contents for REG_LOGIN */
2050 typedef union {
2051         struct {
2052 #ifdef __BIG_ENDIAN_BITFIELD
2053                 uint16_t rsvd1:12;
2054                 uint16_t wd30_class:4;
2055                 uint16_t xri;
2056 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2057                 uint16_t xri;
2058                 uint16_t wd30_class:4;
2059                 uint16_t rsvd1:12;
2060 #endif
2061         } f;
2062         uint32_t word;
2063 } REG_WD30;
2064
2065 /* Structure for MB Command UNREG_LOGIN (20) */
2066
2067 typedef struct {
2068 #ifdef __BIG_ENDIAN_BITFIELD
2069         uint16_t rsvd1;
2070         uint16_t rpi;
2071         uint32_t rsvd2;
2072         uint32_t rsvd3;
2073         uint32_t rsvd4;
2074         uint32_t rsvd5;
2075         uint16_t rsvd6;
2076         uint16_t vpi;
2077 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2078         uint16_t rpi;
2079         uint16_t rsvd1;
2080         uint32_t rsvd2;
2081         uint32_t rsvd3;
2082         uint32_t rsvd4;
2083         uint32_t rsvd5;
2084         uint16_t vpi;
2085         uint16_t rsvd6;
2086 #endif
2087 } UNREG_LOGIN_VAR;
2088
2089 /* Structure for MB Command UNREG_D_ID (0x23) */
2090
2091 typedef struct {
2092         uint32_t did;
2093         uint32_t rsvd2;
2094         uint32_t rsvd3;
2095         uint32_t rsvd4;
2096         uint32_t rsvd5;
2097 #ifdef __BIG_ENDIAN_BITFIELD
2098         uint16_t rsvd6;
2099         uint16_t vpi;
2100 #else
2101         uint16_t vpi;
2102         uint16_t rsvd6;
2103 #endif
2104 } UNREG_D_ID_VAR;
2105
2106 /* Structure for MB Command READ_LA (21) */
2107 /* Structure for MB Command READ_LA64 (0x95) */
2108
2109 typedef struct {
2110         uint32_t eventTag;      /* Event tag */
2111 #ifdef __BIG_ENDIAN_BITFIELD
2112         uint32_t rsvd1:22;
2113         uint32_t pb:1;
2114         uint32_t il:1;
2115         uint32_t attType:8;
2116 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2117         uint32_t attType:8;
2118         uint32_t il:1;
2119         uint32_t pb:1;
2120         uint32_t rsvd1:22;
2121 #endif
2122
2123 #define AT_RESERVED    0x00     /* Reserved - attType */
2124 #define AT_LINK_UP     0x01     /* Link is up */
2125 #define AT_LINK_DOWN   0x02     /* Link is down */
2126
2127 #ifdef __BIG_ENDIAN_BITFIELD
2128         uint8_t granted_AL_PA;
2129         uint8_t lipAlPs;
2130         uint8_t lipType;
2131         uint8_t topology;
2132 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2133         uint8_t topology;
2134         uint8_t lipType;
2135         uint8_t lipAlPs;
2136         uint8_t granted_AL_PA;
2137 #endif
2138
2139 #define TOPOLOGY_PT_PT 0x01     /* Topology is pt-pt / pt-fabric */
2140 #define TOPOLOGY_LOOP  0x02     /* Topology is FC-AL */
2141
2142         union {
2143                 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer
2144                                            to */
2145                 /* store the LILP AL_PA position map into */
2146                 struct ulp_bde64 lilpBde64;
2147         } un;
2148
2149 #ifdef __BIG_ENDIAN_BITFIELD
2150         uint32_t Dlu:1;
2151         uint32_t Dtf:1;
2152         uint32_t Drsvd2:14;
2153         uint32_t DlnkSpeed:8;
2154         uint32_t DnlPort:4;
2155         uint32_t Dtx:2;
2156         uint32_t Drx:2;
2157 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2158         uint32_t Drx:2;
2159         uint32_t Dtx:2;
2160         uint32_t DnlPort:4;
2161         uint32_t DlnkSpeed:8;
2162         uint32_t Drsvd2:14;
2163         uint32_t Dtf:1;
2164         uint32_t Dlu:1;
2165 #endif
2166
2167 #ifdef __BIG_ENDIAN_BITFIELD
2168         uint32_t Ulu:1;
2169         uint32_t Utf:1;
2170         uint32_t Ursvd2:14;
2171         uint32_t UlnkSpeed:8;
2172         uint32_t UnlPort:4;
2173         uint32_t Utx:2;
2174         uint32_t Urx:2;
2175 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2176         uint32_t Urx:2;
2177         uint32_t Utx:2;
2178         uint32_t UnlPort:4;
2179         uint32_t UlnkSpeed:8;
2180         uint32_t Ursvd2:14;
2181         uint32_t Utf:1;
2182         uint32_t Ulu:1;
2183 #endif
2184
2185 #define LA_UNKNW_LINK  0x0    /* lnkSpeed */
2186 #define LA_1GHZ_LINK   0x04   /* lnkSpeed */
2187 #define LA_2GHZ_LINK   0x08   /* lnkSpeed */
2188 #define LA_4GHZ_LINK   0x10   /* lnkSpeed */
2189 #define LA_8GHZ_LINK   0x20   /* lnkSpeed */
2190 #define LA_10GHZ_LINK  0x40   /* lnkSpeed */
2191
2192 } READ_LA_VAR;
2193
2194 /* Structure for MB Command CLEAR_LA (22) */
2195
2196 typedef struct {
2197         uint32_t eventTag;      /* Event tag */
2198         uint32_t rsvd1;
2199 } CLEAR_LA_VAR;
2200
2201 /* Structure for MB Command DUMP */
2202
2203 typedef struct {
2204 #ifdef __BIG_ENDIAN_BITFIELD
2205         uint32_t rsvd:25;
2206         uint32_t ra:1;
2207         uint32_t co:1;
2208         uint32_t cv:1;
2209         uint32_t type:4;
2210         uint32_t entry_index:16;
2211         uint32_t region_id:16;
2212 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2213         uint32_t type:4;
2214         uint32_t cv:1;
2215         uint32_t co:1;
2216         uint32_t ra:1;
2217         uint32_t rsvd:25;
2218         uint32_t region_id:16;
2219         uint32_t entry_index:16;
2220 #endif
2221
2222         uint32_t rsvd1;
2223         uint32_t word_cnt;
2224         uint32_t resp_offset;
2225 } DUMP_VAR;
2226
2227 #define  DMP_MEM_REG             0x1
2228 #define  DMP_NV_PARAMS           0x2
2229
2230 #define  DMP_REGION_VPD          0xe
2231 #define  DMP_VPD_SIZE            0x400  /* maximum amount of VPD */
2232 #define  DMP_RSP_OFFSET          0x14   /* word 5 contains first word of rsp */
2233 #define  DMP_RSP_SIZE            0x6C   /* maximum of 27 words of rsp data */
2234
2235 struct hbq_mask {
2236 #ifdef __BIG_ENDIAN_BITFIELD
2237         uint8_t tmatch;
2238         uint8_t tmask;
2239         uint8_t rctlmatch;
2240         uint8_t rctlmask;
2241 #else   /*  __LITTLE_ENDIAN */
2242         uint8_t rctlmask;
2243         uint8_t rctlmatch;
2244         uint8_t tmask;
2245         uint8_t tmatch;
2246 #endif
2247 };
2248
2249
2250 /* Structure for MB Command CONFIG_HBQ (7c) */
2251
2252 struct config_hbq_var {
2253 #ifdef __BIG_ENDIAN_BITFIELD
2254         uint32_t rsvd1      :7;
2255         uint32_t recvNotify :1;     /* Receive Notification */
2256         uint32_t numMask    :8;     /* # Mask Entries       */
2257         uint32_t profile    :8;     /* Selection Profile    */
2258         uint32_t rsvd2      :8;
2259 #else   /*  __LITTLE_ENDIAN */
2260         uint32_t rsvd2      :8;
2261         uint32_t profile    :8;     /* Selection Profile    */
2262         uint32_t numMask    :8;     /* # Mask Entries       */
2263         uint32_t recvNotify :1;     /* Receive Notification */
2264         uint32_t rsvd1      :7;
2265 #endif
2266
2267 #ifdef __BIG_ENDIAN_BITFIELD
2268         uint32_t hbqId      :16;
2269         uint32_t rsvd3      :12;
2270         uint32_t ringMask   :4;
2271 #else   /*  __LITTLE_ENDIAN */
2272         uint32_t ringMask   :4;
2273         uint32_t rsvd3      :12;
2274         uint32_t hbqId      :16;
2275 #endif
2276
2277 #ifdef __BIG_ENDIAN_BITFIELD
2278         uint32_t entry_count :16;
2279         uint32_t rsvd4        :8;
2280         uint32_t headerLen    :8;
2281 #else   /*  __LITTLE_ENDIAN */
2282         uint32_t headerLen    :8;
2283         uint32_t rsvd4        :8;
2284         uint32_t entry_count :16;
2285 #endif
2286
2287         uint32_t hbqaddrLow;
2288         uint32_t hbqaddrHigh;
2289
2290 #ifdef __BIG_ENDIAN_BITFIELD
2291         uint32_t rsvd5      :31;
2292         uint32_t logEntry   :1;
2293 #else   /*  __LITTLE_ENDIAN */
2294         uint32_t logEntry   :1;
2295         uint32_t rsvd5      :31;
2296 #endif
2297
2298         uint32_t rsvd6;    /* w7 */
2299         uint32_t rsvd7;    /* w8 */
2300         uint32_t rsvd8;    /* w9 */
2301
2302         struct hbq_mask hbqMasks[6];
2303
2304
2305         union {
2306                 uint32_t allprofiles[12];
2307
2308                 struct {
2309                         #ifdef __BIG_ENDIAN_BITFIELD
2310                                 uint32_t        seqlenoff       :16;
2311                                 uint32_t        maxlen          :16;
2312                         #else   /*  __LITTLE_ENDIAN */
2313                                 uint32_t        maxlen          :16;
2314                                 uint32_t        seqlenoff       :16;
2315                         #endif
2316                         #ifdef __BIG_ENDIAN_BITFIELD
2317                                 uint32_t        rsvd1           :28;
2318                                 uint32_t        seqlenbcnt      :4;
2319                         #else   /*  __LITTLE_ENDIAN */
2320                                 uint32_t        seqlenbcnt      :4;
2321                                 uint32_t        rsvd1           :28;
2322                         #endif
2323                         uint32_t rsvd[10];
2324                 } profile2;
2325
2326                 struct {
2327                         #ifdef __BIG_ENDIAN_BITFIELD
2328                                 uint32_t        seqlenoff       :16;
2329                                 uint32_t        maxlen          :16;
2330                         #else   /*  __LITTLE_ENDIAN */
2331                                 uint32_t        maxlen          :16;
2332                                 uint32_t        seqlenoff       :16;
2333                         #endif
2334                         #ifdef __BIG_ENDIAN_BITFIELD
2335                                 uint32_t        cmdcodeoff      :28;
2336                                 uint32_t        rsvd1           :12;
2337                                 uint32_t        seqlenbcnt      :4;
2338                         #else   /*  __LITTLE_ENDIAN */
2339                                 uint32_t        seqlenbcnt      :4;
2340                                 uint32_t        rsvd1           :12;
2341                                 uint32_t        cmdcodeoff      :28;
2342                         #endif
2343                         uint32_t cmdmatch[8];
2344
2345                         uint32_t rsvd[2];
2346                 } profile3;
2347
2348                 struct {
2349                         #ifdef __BIG_ENDIAN_BITFIELD
2350                                 uint32_t        seqlenoff       :16;
2351                                 uint32_t        maxlen          :16;
2352                         #else   /*  __LITTLE_ENDIAN */
2353                                 uint32_t        maxlen          :16;
2354                                 uint32_t        seqlenoff       :16;
2355                         #endif
2356                         #ifdef __BIG_ENDIAN_BITFIELD
2357                                 uint32_t        cmdcodeoff      :28;
2358                                 uint32_t        rsvd1           :12;
2359                                 uint32_t        seqlenbcnt      :4;
2360                         #else   /*  __LITTLE_ENDIAN */
2361                                 uint32_t        seqlenbcnt      :4;
2362                                 uint32_t        rsvd1           :12;
2363                                 uint32_t        cmdcodeoff      :28;
2364                         #endif
2365                         uint32_t cmdmatch[8];
2366
2367                         uint32_t rsvd[2];
2368                 } profile5;
2369
2370         } profiles;
2371
2372 };
2373
2374
2375
2376 /* Structure for MB Command CONFIG_PORT (0x88) */
2377 typedef struct {
2378 #ifdef __BIG_ENDIAN_BITFIELD
2379         uint32_t cBE       :  1;
2380         uint32_t cET       :  1;
2381         uint32_t cHpcb     :  1;
2382         uint32_t cMA       :  1;
2383         uint32_t sli_mode  :  4;
2384         uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
2385                                         * config block */
2386 #else   /*  __LITTLE_ENDIAN */
2387         uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
2388                                         * config block */
2389         uint32_t sli_mode  :  4;
2390         uint32_t cMA       :  1;
2391         uint32_t cHpcb     :  1;
2392         uint32_t cET       :  1;
2393         uint32_t cBE       :  1;
2394 #endif
2395
2396         uint32_t pcbLow;       /* bit 31:0  of memory based port config block */
2397         uint32_t pcbHigh;      /* bit 63:32 of memory based port config block */
2398         uint32_t hbainit[6];
2399
2400 #ifdef __BIG_ENDIAN_BITFIELD
2401         uint32_t rsvd      : 24;  /* Reserved                             */
2402         uint32_t cmv       :  1;  /* Configure Max VPIs                   */
2403         uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
2404         uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
2405         uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
2406         uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
2407         uint32_t cerbm     :  1;  /* Configure Enhanced Receive Buf Mgmt  */
2408         uint32_t cmx       :  1;  /* Configure Max XRIs                   */
2409         uint32_t cmr       :  1;  /* Configure Max RPIs                   */
2410 #else   /*  __LITTLE_ENDIAN */
2411         uint32_t cmr       :  1;  /* Configure Max RPIs                   */
2412         uint32_t cmx       :  1;  /* Configure Max XRIs                   */
2413         uint32_t cerbm     :  1;  /* Configure Enhanced Receive Buf Mgmt  */
2414         uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
2415         uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
2416         uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
2417         uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
2418         uint32_t cmv       :  1;  /* Configure Max VPIs                   */
2419         uint32_t rsvd      : 24;  /* Reserved                             */
2420 #endif
2421 #ifdef __BIG_ENDIAN_BITFIELD
2422         uint32_t rsvd2     : 24;  /* Reserved                             */
2423         uint32_t gmv       :  1;  /* Grant Max VPIs                       */
2424         uint32_t gcrp      :  1;  /* Grant Command Ring Polling           */
2425         uint32_t gsah      :  1;  /* Grant Synchronous Abort Handling     */
2426         uint32_t ghbs      :  1;  /* Grant Host Backing Store             */
2427         uint32_t ginb      :  1;  /* Grant Interrupt Notification Block   */
2428         uint32_t gerbm     :  1;  /* Grant ERBM Request                   */
2429         uint32_t gmx       :  1;  /* Grant Max XRIs                       */
2430         uint32_t gmr       :  1;  /* Grant Max RPIs                       */
2431 #else   /*  __LITTLE_ENDIAN */
2432         uint32_t gmr       :  1;  /* Grant Max RPIs                       */
2433         uint32_t gmx       :  1;  /* Grant Max XRIs                       */
2434         uint32_t gerbm     :  1;  /* Grant ERBM Request                   */
2435         uint32_t ginb      :  1;  /* Grant Interrupt Notification Block   */
2436         uint32_t ghbs      :  1;  /* Grant Host Backing Store             */
2437         uint32_t gsah      :  1;  /* Grant Synchronous Abort Handling     */
2438         uint32_t gcrp      :  1;  /* Grant Command Ring Polling           */
2439         uint32_t gmv       :  1;  /* Grant Max VPIs                       */
2440         uint32_t rsvd2     : 24;  /* Reserved                             */
2441 #endif
2442
2443 #ifdef __BIG_ENDIAN_BITFIELD
2444         uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
2445         uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
2446 #else   /*  __LITTLE_ENDIAN */
2447         uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
2448         uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
2449 #endif
2450
2451 #ifdef __BIG_ENDIAN_BITFIELD
2452         uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
2453         uint32_t rsvd3     : 16;  /* Max HBQs Host expect to configure    */
2454 #else   /*  __LITTLE_ENDIAN */
2455         uint32_t rsvd3     : 16;  /* Max HBQs Host expect to configure    */
2456         uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
2457 #endif
2458
2459         uint32_t rsvd4;           /* Reserved                             */
2460
2461 #ifdef __BIG_ENDIAN_BITFIELD
2462         uint32_t rsvd5      : 16;  /* Reserved                             */
2463         uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
2464 #else   /*  __LITTLE_ENDIAN */
2465         uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
2466         uint32_t rsvd5      : 16;  /* Reserved                             */
2467 #endif
2468
2469 } CONFIG_PORT_VAR;
2470
2471 /* SLI-2 Port Control Block */
2472
2473 /* SLIM POINTER */
2474 #define SLIMOFF 0x30            /* WORD */
2475
2476 typedef struct _SLI2_RDSC {
2477         uint32_t cmdEntries;
2478         uint32_t cmdAddrLow;
2479         uint32_t cmdAddrHigh;
2480
2481         uint32_t rspEntries;
2482         uint32_t rspAddrLow;
2483         uint32_t rspAddrHigh;
2484 } SLI2_RDSC;
2485
2486 typedef struct _PCB {
2487 #ifdef __BIG_ENDIAN_BITFIELD
2488         uint32_t type:8;
2489 #define TYPE_NATIVE_SLI2       0x01;
2490         uint32_t feature:8;
2491 #define FEATURE_INITIAL_SLI2   0x01;
2492         uint32_t rsvd:12;
2493         uint32_t maxRing:4;
2494 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2495         uint32_t maxRing:4;
2496         uint32_t rsvd:12;
2497         uint32_t feature:8;
2498 #define FEATURE_INITIAL_SLI2   0x01;
2499         uint32_t type:8;
2500 #define TYPE_NATIVE_SLI2       0x01;
2501 #endif
2502
2503         uint32_t mailBoxSize;
2504         uint32_t mbAddrLow;
2505         uint32_t mbAddrHigh;
2506
2507         uint32_t hgpAddrLow;
2508         uint32_t hgpAddrHigh;
2509
2510         uint32_t pgpAddrLow;
2511         uint32_t pgpAddrHigh;
2512         SLI2_RDSC rdsc[MAX_RINGS];
2513 } PCB_t;
2514
2515 /* NEW_FEATURE */
2516 typedef struct {
2517 #ifdef __BIG_ENDIAN_BITFIELD
2518         uint32_t rsvd0:27;
2519         uint32_t discardFarp:1;
2520         uint32_t IPEnable:1;
2521         uint32_t nodeName:1;
2522         uint32_t portName:1;
2523         uint32_t filterEnable:1;
2524 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2525         uint32_t filterEnable:1;
2526         uint32_t portName:1;
2527         uint32_t nodeName:1;
2528         uint32_t IPEnable:1;
2529         uint32_t discardFarp:1;
2530         uint32_t rsvd:27;
2531 #endif
2532
2533         uint8_t portname[8];    /* Used to be struct lpfc_name */
2534         uint8_t nodename[8];
2535         uint32_t rsvd1;
2536         uint32_t rsvd2;
2537         uint32_t rsvd3;
2538         uint32_t IPAddress;
2539 } CONFIG_FARP_VAR;
2540
2541 /* Union of all Mailbox Command types */
2542 #define MAILBOX_CMD_WSIZE       32
2543 #define MAILBOX_CMD_SIZE        (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
2544
2545 typedef union {
2546         uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
2547                                                     * feature/max ring number
2548                                                     */
2549         LOAD_SM_VAR varLdSM;            /* cmd =  1 (LOAD_SM)        */
2550         READ_NV_VAR varRDnvp;           /* cmd =  2 (READ_NVPARMS)   */
2551         WRITE_NV_VAR varWTnvp;          /* cmd =  3 (WRITE_NVPARMS)  */
2552         BIU_DIAG_VAR varBIUdiag;        /* cmd =  4 (RUN_BIU_DIAG)   */
2553         INIT_LINK_VAR varInitLnk;       /* cmd =  5 (INIT_LINK)      */
2554         DOWN_LINK_VAR varDwnLnk;        /* cmd =  6 (DOWN_LINK)      */
2555         CONFIG_LINK varCfgLnk;          /* cmd =  7 (CONFIG_LINK)    */
2556         PART_SLIM_VAR varSlim;          /* cmd =  8 (PART_SLIM)      */
2557         CONFIG_RING_VAR varCfgRing;     /* cmd =  9 (CONFIG_RING)    */
2558         RESET_RING_VAR varRstRing;      /* cmd = 10 (RESET_RING)     */
2559         READ_CONFIG_VAR varRdConfig;    /* cmd = 11 (READ_CONFIG)    */
2560         READ_RCONF_VAR varRdRConfig;    /* cmd = 12 (READ_RCONFIG)   */
2561         READ_SPARM_VAR varRdSparm;      /* cmd = 13 (READ_SPARM(64)) */
2562         READ_STATUS_VAR varRdStatus;    /* cmd = 14 (READ_STATUS)    */
2563         READ_RPI_VAR varRdRPI;          /* cmd = 15 (READ_RPI(64))   */
2564         READ_XRI_VAR varRdXRI;          /* cmd = 16 (READ_XRI)       */
2565         READ_REV_VAR varRdRev;          /* cmd = 17 (READ_REV)       */
2566         READ_LNK_VAR varRdLnk;          /* cmd = 18 (READ_LNK_STAT)  */
2567         REG_LOGIN_VAR varRegLogin;      /* cmd = 19 (REG_LOGIN(64))  */
2568         UNREG_LOGIN_VAR varUnregLogin;  /* cmd = 20 (UNREG_LOGIN)    */
2569         READ_LA_VAR varReadLA;          /* cmd = 21 (READ_LA(64))    */
2570         CLEAR_LA_VAR varClearLA;        /* cmd = 22 (CLEAR_LA)       */
2571         DUMP_VAR varDmp;                /* Warm Start DUMP mbx cmd   */
2572         UNREG_D_ID_VAR varUnregDID;     /* cmd = 0x23 (UNREG_D_ID)   */
2573         CONFIG_FARP_VAR varCfgFarp;     /* cmd = 0x25 (CONFIG_FARP)
2574                                          * NEW_FEATURE
2575                                          */
2576         struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ)  */
2577         CONFIG_PORT_VAR varCfgPort;     /* cmd = 0x88 (CONFIG_PORT)  */
2578 } MAILVARIANTS;
2579
2580 /*
2581  * SLI-2 specific structures
2582  */
2583
2584 struct lpfc_hgp {
2585         __le32 cmdPutInx;
2586         __le32 rspGetInx;
2587 };
2588
2589 struct lpfc_pgp {
2590         __le32 cmdGetInx;
2591         __le32 rspPutInx;
2592 };
2593
2594 struct sli2_desc {
2595         uint32_t unused1[16];
2596         struct lpfc_hgp host[MAX_RINGS];
2597         struct lpfc_pgp port[MAX_RINGS];
2598 };
2599
2600 struct sli3_desc {
2601         struct lpfc_hgp host[MAX_RINGS];
2602         uint32_t reserved[8];
2603         uint32_t hbq_put[16];
2604 };
2605
2606 struct sli3_pgp {
2607         struct lpfc_pgp port[MAX_RINGS];
2608         uint32_t hbq_get[16];
2609 };
2610
2611 typedef union {
2612         struct sli2_desc s2;
2613         struct sli3_desc s3;
2614         struct sli3_pgp  s3_pgp;
2615 } SLI_VAR;
2616
2617
2618 typedef struct {
2619 #ifdef __BIG_ENDIAN_BITFIELD
2620         uint16_t mbxStatus;
2621         uint8_t mbxCommand;
2622         uint8_t mbxReserved:6;
2623         uint8_t mbxHc:1;
2624         uint8_t mbxOwner:1;     /* Low order bit first word */
2625 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2626         uint8_t mbxOwner:1;     /* Low order bit first word */
2627         uint8_t mbxHc:1;
2628         uint8_t mbxReserved:6;
2629         uint8_t mbxCommand;
2630         uint16_t mbxStatus;
2631 #endif
2632
2633         MAILVARIANTS un;
2634         SLI_VAR us;
2635 } MAILBOX_t;
2636
2637 /*
2638  *    Begin Structure Definitions for IOCB Commands
2639  */
2640
2641 typedef struct {
2642 #ifdef __BIG_ENDIAN_BITFIELD
2643         uint8_t statAction;
2644         uint8_t statRsn;
2645         uint8_t statBaExp;
2646         uint8_t statLocalError;
2647 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2648         uint8_t statLocalError;
2649         uint8_t statBaExp;
2650         uint8_t statRsn;
2651         uint8_t statAction;
2652 #endif
2653         /* statRsn  P/F_RJT reason codes */
2654 #define RJT_BAD_D_ID       0x01 /* Invalid D_ID field */
2655 #define RJT_BAD_S_ID       0x02 /* Invalid S_ID field */
2656 #define RJT_UNAVAIL_TEMP   0x03 /* N_Port unavailable temp. */
2657 #define RJT_UNAVAIL_PERM   0x04 /* N_Port unavailable perm. */
2658 #define RJT_UNSUP_CLASS    0x05 /* Class not supported */
2659 #define RJT_DELIM_ERR      0x06 /* Delimiter usage error */
2660 #define RJT_UNSUP_TYPE     0x07 /* Type not supported */
2661 #define RJT_BAD_CONTROL    0x08 /* Invalid link conrtol */
2662 #define RJT_BAD_RCTL       0x09 /* R_CTL invalid */
2663 #define RJT_BAD_FCTL       0x0A /* F_CTL invalid */
2664 #define RJT_BAD_OXID       0x0B /* OX_ID invalid */
2665 #define RJT_BAD_RXID       0x0C /* RX_ID invalid */
2666 #define RJT_BAD_SEQID      0x0D /* SEQ_ID invalid */
2667 #define RJT_BAD_DFCTL      0x0E /* DF_CTL invalid */
2668 #define RJT_BAD_SEQCNT     0x0F /* SEQ_CNT invalid */
2669 #define RJT_BAD_PARM       0x10 /* Param. field invalid */
2670 #define RJT_XCHG_ERR       0x11 /* Exchange error */
2671 #define RJT_PROT_ERR       0x12 /* Protocol error */
2672 #define RJT_BAD_LENGTH     0x13 /* Invalid Length */
2673 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
2674 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
2675 #define RJT_TOO_MANY_SEQ   0x17 /* Excessive sequences */
2676 #define RJT_XCHG_NOT_STRT  0x18 /* Exchange not started */
2677 #define RJT_UNSUP_SEC_HDR  0x19 /* Security hdr not supported */
2678 #define RJT_UNAVAIL_PATH   0x1A /* Fabric Path not available */
2679 #define RJT_VENDOR_UNIQUE  0xFF /* Vendor unique error */
2680
2681 #define IOERR_SUCCESS                 0x00      /* statLocalError */
2682 #define IOERR_MISSING_CONTINUE        0x01
2683 #define IOERR_SEQUENCE_TIMEOUT        0x02
2684 #define IOERR_INTERNAL_ERROR          0x03
2685 #define IOERR_INVALID_RPI             0x04
2686 #define IOERR_NO_XRI                  0x05
2687 #define IOERR_ILLEGAL_COMMAND         0x06
2688 #define IOERR_XCHG_DROPPED            0x07
2689 #define IOERR_ILLEGAL_FIELD           0x08
2690 #define IOERR_BAD_CONTINUE            0x09
2691 #define IOERR_TOO_MANY_BUFFERS        0x0A
2692 #define IOERR_RCV_BUFFER_WAITING      0x0B
2693 #define IOERR_NO_CONNECTION           0x0C
2694 #define IOERR_TX_DMA_FAILED           0x0D
2695 #define IOERR_RX_DMA_FAILED           0x0E
2696 #define IOERR_ILLEGAL_FRAME           0x0F
2697 #define IOERR_EXTRA_DATA              0x10
2698 #define IOERR_NO_RESOURCES            0x11
2699 #define IOERR_RESERVED                0x12
2700 #define IOERR_ILLEGAL_LENGTH          0x13
2701 #define IOERR_UNSUPPORTED_FEATURE     0x14
2702 #define IOERR_ABORT_IN_PROGRESS       0x15
2703 #define IOERR_ABORT_REQUESTED         0x16
2704 #define IOERR_RECEIVE_BUFFER_TIMEOUT  0x17
2705 #define IOERR_LOOP_OPEN_FAILURE       0x18
2706 #define IOERR_RING_RESET              0x19
2707 #define IOERR_LINK_DOWN               0x1A
2708 #define IOERR_CORRUPTED_DATA          0x1B
2709 #define IOERR_CORRUPTED_RPI           0x1C
2710 #define IOERR_OUT_OF_ORDER_DATA       0x1D
2711 #define IOERR_OUT_OF_ORDER_ACK        0x1E
2712 #define IOERR_DUP_FRAME               0x1F
2713 #define IOERR_LINK_CONTROL_FRAME      0x20      /* ACK_N received */
2714 #define IOERR_BAD_HOST_ADDRESS        0x21
2715 #define IOERR_RCV_HDRBUF_WAITING      0x22
2716 #define IOERR_MISSING_HDR_BUFFER      0x23
2717 #define IOERR_MSEQ_CHAIN_CORRUPTED    0x24
2718 #define IOERR_ABORTMULT_REQUESTED     0x25
2719 #define IOERR_BUFFER_SHORTAGE         0x28
2720 #define IOERR_DEFAULT                 0x29
2721 #define IOERR_CNT                     0x2A
2722
2723 #define IOERR_DRVR_MASK               0x100
2724 #define IOERR_SLI_DOWN                0x101  /* ulpStatus  - Driver defined */
2725 #define IOERR_SLI_BRESET              0x102
2726 #define IOERR_SLI_ABORTED             0x103
2727 } PARM_ERR;
2728
2729 typedef union {
2730         struct {
2731 #ifdef __BIG_ENDIAN_BITFIELD
2732                 uint8_t Rctl;   /* R_CTL field */
2733                 uint8_t Type;   /* TYPE field */
2734                 uint8_t Dfctl;  /* DF_CTL field */
2735                 uint8_t Fctl;   /* Bits 0-7 of IOCB word 5 */
2736 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2737                 uint8_t Fctl;   /* Bits 0-7 of IOCB word 5 */
2738                 uint8_t Dfctl;  /* DF_CTL field */
2739                 uint8_t Type;   /* TYPE field */
2740                 uint8_t Rctl;   /* R_CTL field */
2741 #endif
2742
2743 #define BC      0x02            /* Broadcast Received  - Fctl */
2744 #define SI      0x04            /* Sequence Initiative */
2745 #define LA      0x08            /* Ignore Link Attention state */
2746 #define LS      0x80            /* Last Sequence */
2747         } hcsw;
2748         uint32_t reserved;
2749 } WORD5;
2750
2751 /* IOCB Command template for a generic response */
2752 typedef struct {
2753         uint32_t reserved[4];
2754         PARM_ERR perr;
2755 } GENERIC_RSP;
2756
2757 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
2758 typedef struct {
2759         struct ulp_bde xrsqbde[2];
2760         uint32_t xrsqRo;        /* Starting Relative Offset */
2761         WORD5 w5;               /* Header control/status word */
2762 } XR_SEQ_FIELDS;
2763
2764 /* IOCB Command template for ELS_REQUEST */
2765 typedef struct {
2766         struct ulp_bde elsReq;
2767         struct ulp_bde elsRsp;
2768
2769 #ifdef __BIG_ENDIAN_BITFIELD
2770         uint32_t word4Rsvd:7;
2771         uint32_t fl:1;
2772         uint32_t myID:24;
2773         uint32_t word5Rsvd:8;
2774         uint32_t remoteID:24;
2775 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2776         uint32_t myID:24;
2777         uint32_t fl:1;
2778         uint32_t word4Rsvd:7;
2779         uint32_t remoteID:24;
2780         uint32_t word5Rsvd:8;
2781 #endif
2782 } ELS_REQUEST;
2783
2784 /* IOCB Command template for RCV_ELS_REQ */
2785 typedef struct {
2786         struct ulp_bde elsReq[2];
2787         uint32_t parmRo;
2788
2789 #ifdef __BIG_ENDIAN_BITFIELD
2790         uint32_t word5Rsvd:8;
2791         uint32_t remoteID:24;
2792 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2793         uint32_t remoteID:24;
2794         uint32_t word5Rsvd:8;
2795 #endif
2796 } RCV_ELS_REQ;
2797
2798 /* IOCB Command template for ABORT / CLOSE_XRI */
2799 typedef struct {
2800         uint32_t rsvd[3];
2801         uint32_t abortType;
2802 #define ABORT_TYPE_ABTX  0x00000000
2803 #define ABORT_TYPE_ABTS  0x00000001
2804         uint32_t parm;
2805 #ifdef __BIG_ENDIAN_BITFIELD
2806         uint16_t abortContextTag; /* ulpContext from command to abort/close */
2807         uint16_t abortIoTag;    /* ulpIoTag from command to abort/close */
2808 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2809         uint16_t abortIoTag;    /* ulpIoTag from command to abort/close */
2810         uint16_t abortContextTag; /* ulpContext from command to abort/close */
2811 #endif
2812 } AC_XRI;
2813
2814 /* IOCB Command template for ABORT_MXRI64 */
2815 typedef struct {
2816         uint32_t rsvd[3];
2817         uint32_t abortType;
2818         uint32_t parm;
2819         uint32_t iotag32;
2820 } A_MXRI64;
2821
2822 /* IOCB Command template for GET_RPI */
2823 typedef struct {
2824         uint32_t rsvd[4];
2825         uint32_t parmRo;
2826 #ifdef __BIG_ENDIAN_BITFIELD
2827         uint32_t word5Rsvd:8;
2828         uint32_t remoteID:24;
2829 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2830         uint32_t remoteID:24;
2831         uint32_t word5Rsvd:8;
2832 #endif
2833 } GET_RPI;
2834
2835 /* IOCB Command template for all FCP Initiator commands */
2836 typedef struct {
2837         struct ulp_bde fcpi_cmnd;       /* FCP_CMND payload descriptor */
2838         struct ulp_bde fcpi_rsp;        /* Rcv buffer */
2839         uint32_t fcpi_parm;
2840         uint32_t fcpi_XRdy;     /* transfer ready for IWRITE */
2841 } FCPI_FIELDS;
2842
2843 /* IOCB Command template for all FCP Target commands */
2844 typedef struct {
2845         struct ulp_bde fcpt_Buffer[2];  /* FCP_CMND payload descriptor */
2846         uint32_t fcpt_Offset;
2847         uint32_t fcpt_Length;   /* transfer ready for IWRITE */
2848 } FCPT_FIELDS;
2849
2850 /* SLI-2 IOCB structure definitions */
2851
2852 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
2853 typedef struct {
2854         ULP_BDL bdl;
2855         uint32_t xrsqRo;        /* Starting Relative Offset */
2856         WORD5 w5;               /* Header control/status word */
2857 } XMT_SEQ_FIELDS64;
2858
2859 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
2860 typedef struct {
2861         struct ulp_bde64 rcvBde;
2862         uint32_t rsvd1;
2863         uint32_t xrsqRo;        /* Starting Relative Offset */
2864         WORD5 w5;               /* Header control/status word */
2865 } RCV_SEQ_FIELDS64;
2866
2867 /* IOCB Command template for ELS_REQUEST64 */
2868 typedef struct {
2869         ULP_BDL bdl;
2870 #ifdef __BIG_ENDIAN_BITFIELD
2871         uint32_t word4Rsvd:7;
2872         uint32_t fl:1;
2873         uint32_t myID:24;
2874         uint32_t word5Rsvd:8;
2875         uint32_t remoteID:24;
2876 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2877         uint32_t myID:24;
2878         uint32_t fl:1;
2879         uint32_t word4Rsvd:7;
2880         uint32_t remoteID:24;
2881         uint32_t word5Rsvd:8;
2882 #endif
2883 } ELS_REQUEST64;
2884
2885 /* IOCB Command template for GEN_REQUEST64 */
2886 typedef struct {
2887         ULP_BDL bdl;
2888         uint32_t xrsqRo;        /* Starting Relative Offset */
2889         WORD5 w5;               /* Header control/status word */
2890 } GEN_REQUEST64;
2891
2892 /* IOCB Command template for RCV_ELS_REQ64 */
2893 typedef struct {
2894         struct ulp_bde64 elsReq;
2895         uint32_t rcvd1;
2896         uint32_t parmRo;
2897
2898 #ifdef __BIG_ENDIAN_BITFIELD
2899         uint32_t word5Rsvd:8;
2900         uint32_t remoteID:24;
2901 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2902         uint32_t remoteID:24;
2903         uint32_t word5Rsvd:8;
2904 #endif
2905 } RCV_ELS_REQ64;
2906
2907 /* IOCB Command template for all 64 bit FCP Initiator commands */
2908 typedef struct {
2909         ULP_BDL bdl;
2910         uint32_t fcpi_parm;
2911         uint32_t fcpi_XRdy;     /* transfer ready for IWRITE */
2912 } FCPI_FIELDS64;
2913
2914 /* IOCB Command template for all 64 bit FCP Target commands */
2915 typedef struct {
2916         ULP_BDL bdl;
2917         uint32_t fcpt_Offset;
2918         uint32_t fcpt_Length;   /* transfer ready for IWRITE */
2919 } FCPT_FIELDS64;
2920
2921 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
2922    or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
2923
2924 struct rcv_sli3 {
2925         uint32_t word8Rsvd;
2926 #ifdef __BIG_ENDIAN_BITFIELD
2927         uint16_t vpi;
2928         uint16_t word9Rsvd;
2929 #else  /*  __LITTLE_ENDIAN */
2930         uint16_t word9Rsvd;
2931         uint16_t vpi;
2932 #endif
2933         uint32_t word10Rsvd;
2934         uint32_t acc_len;      /* accumulated length */
2935         struct ulp_bde64 bde2;
2936 };
2937
2938 typedef struct _IOCB {  /* IOCB structure */
2939         union {
2940                 GENERIC_RSP grsp;       /* Generic response */
2941                 XR_SEQ_FIELDS xrseq;    /* XMIT / BCAST / RCV_SEQUENCE cmd */
2942                 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
2943                 RCV_ELS_REQ rcvels;     /* RCV_ELS_REQ template */
2944                 AC_XRI acxri;   /* ABORT / CLOSE_XRI template */
2945                 A_MXRI64 amxri; /* abort multiple xri command overlay */
2946                 GET_RPI getrpi; /* GET_RPI template */
2947                 FCPI_FIELDS fcpi;       /* FCP Initiator template */
2948                 FCPT_FIELDS fcpt;       /* FCP target template */
2949
2950                 /* SLI-2 structures */
2951
2952                 struct ulp_bde64 cont64[2];  /* up to 2 64 bit continuation
2953                                               * bde_64s */
2954                 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
2955                 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
2956                 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
2957                 XMT_SEQ_FIELDS64 xseq64;        /* XMIT / BCAST cmd */
2958                 FCPI_FIELDS64 fcpi64;   /* FCP 64 bit Initiator template */
2959                 FCPT_FIELDS64 fcpt64;   /* FCP 64 bit target template */
2960
2961                 uint32_t ulpWord[IOCB_WORD_SZ - 2];     /* generic 6 'words' */
2962         } un;
2963         union {
2964                 struct {
2965 #ifdef __BIG_ENDIAN_BITFIELD
2966                         uint16_t ulpContext;    /* High order bits word 6 */
2967                         uint16_t ulpIoTag;      /* Low  order bits word 6 */
2968 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2969                         uint16_t ulpIoTag;      /* Low  order bits word 6 */
2970                         uint16_t ulpContext;    /* High order bits word 6 */
2971 #endif
2972                 } t1;
2973                 struct {
2974 #ifdef __BIG_ENDIAN_BITFIELD
2975                         uint16_t ulpContext;    /* High order bits word 6 */
2976                         uint16_t ulpIoTag1:2;   /* Low  order bits word 6 */
2977                         uint16_t ulpIoTag0:14;  /* Low  order bits word 6 */
2978 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2979                         uint16_t ulpIoTag0:14;  /* Low  order bits word 6 */
2980                         uint16_t ulpIoTag1:2;   /* Low  order bits word 6 */
2981                         uint16_t ulpContext;    /* High order bits word 6 */
2982 #endif
2983                 } t2;
2984         } un1;
2985 #define ulpContext un1.t1.ulpContext
2986 #define ulpIoTag   un1.t1.ulpIoTag
2987 #define ulpIoTag0  un1.t2.ulpIoTag0
2988
2989 #ifdef __BIG_ENDIAN_BITFIELD
2990         uint32_t ulpTimeout:8;
2991         uint32_t ulpXS:1;
2992         uint32_t ulpFCP2Rcvy:1;
2993         uint32_t ulpPU:2;
2994         uint32_t ulpIr:1;
2995         uint32_t ulpClass:3;
2996         uint32_t ulpCommand:8;
2997         uint32_t ulpStatus:4;
2998         uint32_t ulpBdeCount:2;
2999         uint32_t ulpLe:1;
3000         uint32_t ulpOwner:1;    /* Low order bit word 7 */
3001 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3002         uint32_t ulpOwner:1;    /* Low order bit word 7 */
3003         uint32_t ulpLe:1;
3004         uint32_t ulpBdeCount:2;
3005         uint32_t ulpStatus:4;
3006         uint32_t ulpCommand:8;
3007         uint32_t ulpClass:3;
3008         uint32_t ulpIr:1;
3009         uint32_t ulpPU:2;
3010         uint32_t ulpFCP2Rcvy:1;
3011         uint32_t ulpXS:1;
3012         uint32_t ulpTimeout:8;
3013 #endif
3014         union {
3015                 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
3016                 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
3017         } unsli3;
3018
3019 #define ulpCt_h ulpXS
3020 #define ulpCt_l ulpFCP2Rcvy
3021
3022 #define IOCB_FCP           1    /* IOCB is used for FCP ELS cmds-ulpRsvByte */
3023 #define IOCB_IP            2    /* IOCB is used for IP ELS cmds */
3024 #define PARM_UNUSED        0    /* PU field (Word 4) not used */
3025 #define PARM_REL_OFF       1    /* PU field (Word 4) = R. O. */
3026 #define PARM_READ_CHECK    2    /* PU field (Word 4) = Data Transfer Length */
3027 #define CLASS1             0    /* Class 1 */
3028 #define CLASS2             1    /* Class 2 */
3029 #define CLASS3             2    /* Class 3 */
3030 #define CLASS_FCP_INTERMIX 7    /* FCP Data->Cls 1, all else->Cls 2 */
3031
3032 #define IOSTAT_SUCCESS         0x0      /* ulpStatus  - HBA defined */
3033 #define IOSTAT_FCP_RSP_ERROR   0x1
3034 #define IOSTAT_REMOTE_STOP     0x2
3035 #define IOSTAT_LOCAL_REJECT    0x3
3036 #define IOSTAT_NPORT_RJT       0x4
3037 #define IOSTAT_FABRIC_RJT      0x5
3038 #define IOSTAT_NPORT_BSY       0x6
3039 #define IOSTAT_FABRIC_BSY      0x7
3040 #define IOSTAT_INTERMED_RSP    0x8
3041 #define IOSTAT_LS_RJT          0x9
3042 #define IOSTAT_BA_RJT          0xA
3043 #define IOSTAT_RSVD1           0xB
3044 #define IOSTAT_RSVD2           0xC
3045 #define IOSTAT_RSVD3           0xD
3046 #define IOSTAT_RSVD4           0xE
3047 #define IOSTAT_RSVD5           0xF
3048 #define IOSTAT_DRIVER_REJECT   0x10   /* ulpStatus  - Driver defined */
3049 #define IOSTAT_DEFAULT         0xF    /* Same as rsvd5 for now */
3050 #define IOSTAT_CNT             0x11
3051
3052 } IOCB_t;
3053
3054 /* Structure used for a single HBQ entry */
3055 struct lpfc_hbq_entry {
3056         struct ulp_bde64 bde;
3057         uint32_t buffer_tag;
3058 };
3059
3060
3061 #define SLI1_SLIM_SIZE   (4 * 1024)
3062
3063 /* Up to 498 IOCBs will fit into 16k
3064  * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
3065  */
3066 #define SLI2_SLIM_SIZE   (64 * 1024)
3067
3068 /* Maximum IOCBs that will fit in SLI2 slim */
3069 #define MAX_SLI2_IOCB    498
3070 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
3071                             (sizeof(MAILBOX_t) + sizeof(PCB_t)))
3072
3073 /* HBQ entries are 4 words each = 4k */
3074 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) *  \
3075                              lpfc_sli_hbq_count())
3076
3077 struct lpfc_sli2_slim {
3078         MAILBOX_t mbx;
3079         PCB_t pcb;
3080         IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
3081 };
3082
3083 /*
3084  * This function checks PCI device to allow special handling for LC HBAs.
3085  *
3086  * Parameters:
3087  * device : struct pci_dev 's device field
3088  *
3089  * return 1 => TRUE
3090  *        0 => FALSE
3091  */
3092 static inline int
3093 lpfc_is_LC_HBA(unsigned short device)
3094 {
3095         if ((device == PCI_DEVICE_ID_TFLY) ||
3096             (device == PCI_DEVICE_ID_PFLY) ||
3097             (device == PCI_DEVICE_ID_LP101) ||
3098             (device == PCI_DEVICE_ID_BMID) ||
3099             (device == PCI_DEVICE_ID_BSMB) ||
3100             (device == PCI_DEVICE_ID_ZMID) ||
3101             (device == PCI_DEVICE_ID_ZSMB) ||
3102             (device == PCI_DEVICE_ID_RFLY))
3103                 return 1;
3104         else
3105                 return 0;
3106 }