projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
[SCSI] lpfc 8.3.13: Misc fixes
[deliverable/linux.git] / drivers / scsi / lpfc / lpfc_hw.h
1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2004-2010 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
20
21 #define FDMI_DID 0xfffffaU
22 #define NameServer_DID 0xfffffcU
23 #define SCR_DID 0xfffffdU
24 #define Fabric_DID 0xfffffeU
25 #define Bcast_DID 0xffffffU
26 #define Mask_DID 0xffffffU
27 #define CT_DID_MASK 0xffff00U
28 #define Fabric_DID_MASK 0xfff000U
29 #define WELL_KNOWN_DID_MASK 0xfffff0U
30
31 #define PT2PT_LocalID 1
32 #define PT2PT_RemoteID 2
33
34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
36 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */
37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
38
39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
40 0 */
41
42 #define FCELSSIZE 1024 /* maximum ELS transfer size */
43
44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
45 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
47 #define LPFC_FCP_NEXT_RING 3
48
49 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
50 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
51 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
52 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
55 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
56 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
57 #define SLI2_IOCB_CMD_R3_ENTRIES 0
58 #define SLI2_IOCB_RSP_R3_ENTRIES 0
59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
61
62 #define SLI2_IOCB_CMD_SIZE 32
63 #define SLI2_IOCB_RSP_SIZE 32
64 #define SLI3_IOCB_CMD_SIZE 128
65 #define SLI3_IOCB_RSP_SIZE 64
66
67
68 /* vendor ID used in SCSI netlink calls */
69 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
70
71 /* Common Transport structures and definitions */
72
73 union CtRevisionId {
74 /* Structure is in Big Endian format */
75 struct {
76 uint32_t Revision:8;
77 uint32_t InId:24;
78 } bits;
79 uint32_t word;
80 };
81
82 union CtCommandResponse {
83 /* Structure is in Big Endian format */
84 struct {
85 uint32_t CmdRsp:16;
86 uint32_t Size:16;
87 } bits;
88 uint32_t word;
89 };
90
91 #define FC4_FEATURE_INIT 0x2
92 #define FC4_FEATURE_TARGET 0x1
93
94 struct lpfc_sli_ct_request {
95 /* Structure is in Big Endian format */
96 union CtRevisionId RevisionId;
97 uint8_t FsType;
98 uint8_t FsSubType;
99 uint8_t Options;
100 uint8_t Rsrvd1;
101 union CtCommandResponse CommandResponse;
102 uint8_t Rsrvd2;
103 uint8_t ReasonCode;
104 uint8_t Explanation;
105 uint8_t VendorUnique;
106
107 union {
108 uint32_t PortID;
109 struct gid {
110 uint8_t PortType; /* for GID_PT requests */
111 uint8_t DomainScope;
112 uint8_t AreaScope;
113 uint8_t Fc4Type; /* for GID_FT requests */
114 } gid;
115 struct rft {
116 uint32_t PortId; /* For RFT_ID requests */
117
118 #ifdef __BIG_ENDIAN_BITFIELD
119 uint32_t rsvd0:16;
120 uint32_t rsvd1:7;
121 uint32_t fcpReg:1; /* Type 8 */
122 uint32_t rsvd2:2;
123 uint32_t ipReg:1; /* Type 5 */
124 uint32_t rsvd3:5;
125 #else /* __LITTLE_ENDIAN_BITFIELD */
126 uint32_t rsvd0:16;
127 uint32_t fcpReg:1; /* Type 8 */
128 uint32_t rsvd1:7;
129 uint32_t rsvd3:5;
130 uint32_t ipReg:1; /* Type 5 */
131 uint32_t rsvd2:2;
132 #endif
133
134 uint32_t rsvd[7];
135 } rft;
136 struct rnn {
137 uint32_t PortId; /* For RNN_ID requests */
138 uint8_t wwnn[8];
139 } rnn;
140 struct rsnn { /* For RSNN_ID requests */
141 uint8_t wwnn[8];
142 uint8_t len;
143 uint8_t symbname[255];
144 } rsnn;
145 struct da_id { /* For DA_ID requests */
146 uint32_t port_id;
147 } da_id;
148 struct rspn { /* For RSPN_ID requests */
149 uint32_t PortId;
150 uint8_t len;
151 uint8_t symbname[255];
152 } rspn;
153 struct gff {
154 uint32_t PortId;
155 } gff;
156 struct gff_acc {
157 uint8_t fbits[128];
158 } gff_acc;
159 #define FCP_TYPE_FEATURE_OFFSET 7
160 struct rff {
161 uint32_t PortId;
162 uint8_t reserved[2];
163 uint8_t fbits;
164 uint8_t type_code; /* type=8 for FCP */
165 } rff;
166 } un;
167 };
168
169 #define SLI_CT_REVISION 1
170 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
171 sizeof(struct gid))
172 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
173 sizeof(struct gff))
174 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
175 sizeof(struct rft))
176 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
177 sizeof(struct rff))
178 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
179 sizeof(struct rnn))
180 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
181 sizeof(struct rsnn))
182 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
183 sizeof(struct da_id))
184 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
185 sizeof(struct rspn))
186
187 /*
188 * FsType Definitions
189 */
190
191 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
192 #define SLI_CT_TIME_SERVICE 0xFB
193 #define SLI_CT_DIRECTORY_SERVICE 0xFC
194 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
195
196 /*
197 * Directory Service Subtypes
198 */
199
200 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
201
202 /*
203 * Response Codes
204 */
205
206 #define SLI_CT_RESPONSE_FS_RJT 0x8001
207 #define SLI_CT_RESPONSE_FS_ACC 0x8002
208
209 /*
210 * Reason Codes
211 */
212
213 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
214 #define SLI_CT_INVALID_COMMAND 0x01
215 #define SLI_CT_INVALID_VERSION 0x02
216 #define SLI_CT_LOGICAL_ERROR 0x03
217 #define SLI_CT_INVALID_IU_SIZE 0x04
218 #define SLI_CT_LOGICAL_BUSY 0x05
219 #define SLI_CT_PROTOCOL_ERROR 0x07
220 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
221 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
222 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
223 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
224 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
225 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
226 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
227 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
228 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
229 #define SLI_CT_VENDOR_UNIQUE 0xff
230
231 /*
232 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
233 */
234
235 #define SLI_CT_NO_PORT_ID 0x01
236 #define SLI_CT_NO_PORT_NAME 0x02
237 #define SLI_CT_NO_NODE_NAME 0x03
238 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
239 #define SLI_CT_NO_IP_ADDRESS 0x05
240 #define SLI_CT_NO_IPA 0x06
241 #define SLI_CT_NO_FC4_TYPES 0x07
242 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
243 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
244 #define SLI_CT_NO_PORT_TYPE 0x0A
245 #define SLI_CT_ACCESS_DENIED 0x10
246 #define SLI_CT_INVALID_PORT_ID 0x11
247 #define SLI_CT_DATABASE_EMPTY 0x12
248
249 /*
250 * Name Server Command Codes
251 */
252
253 #define SLI_CTNS_GA_NXT 0x0100
254 #define SLI_CTNS_GPN_ID 0x0112
255 #define SLI_CTNS_GNN_ID 0x0113
256 #define SLI_CTNS_GCS_ID 0x0114
257 #define SLI_CTNS_GFT_ID 0x0117
258 #define SLI_CTNS_GSPN_ID 0x0118
259 #define SLI_CTNS_GPT_ID 0x011A
260 #define SLI_CTNS_GFF_ID 0x011F
261 #define SLI_CTNS_GID_PN 0x0121
262 #define SLI_CTNS_GID_NN 0x0131
263 #define SLI_CTNS_GIP_NN 0x0135
264 #define SLI_CTNS_GIPA_NN 0x0136
265 #define SLI_CTNS_GSNN_NN 0x0139
266 #define SLI_CTNS_GNN_IP 0x0153
267 #define SLI_CTNS_GIPA_IP 0x0156
268 #define SLI_CTNS_GID_FT 0x0171
269 #define SLI_CTNS_GID_PT 0x01A1
270 #define SLI_CTNS_RPN_ID 0x0212
271 #define SLI_CTNS_RNN_ID 0x0213
272 #define SLI_CTNS_RCS_ID 0x0214
273 #define SLI_CTNS_RFT_ID 0x0217
274 #define SLI_CTNS_RSPN_ID 0x0218
275 #define SLI_CTNS_RPT_ID 0x021A
276 #define SLI_CTNS_RFF_ID 0x021F
277 #define SLI_CTNS_RIP_NN 0x0235
278 #define SLI_CTNS_RIPA_NN 0x0236
279 #define SLI_CTNS_RSNN_NN 0x0239
280 #define SLI_CTNS_DA_ID 0x0300
281
282 /*
283 * Port Types
284 */
285
286 #define SLI_CTPT_N_PORT 0x01
287 #define SLI_CTPT_NL_PORT 0x02
288 #define SLI_CTPT_FNL_PORT 0x03
289 #define SLI_CTPT_IP 0x04
290 #define SLI_CTPT_FCP 0x08
291 #define SLI_CTPT_NX_PORT 0x7F
292 #define SLI_CTPT_F_PORT 0x81
293 #define SLI_CTPT_FL_PORT 0x82
294 #define SLI_CTPT_E_PORT 0x84
295
296 #define SLI_CT_LAST_ENTRY 0x80000000
297
298 /* Fibre Channel Service Parameter definitions */
299
300 #define FC_PH_4_0 6 /* FC-PH version 4.0 */
301 #define FC_PH_4_1 7 /* FC-PH version 4.1 */
302 #define FC_PH_4_2 8 /* FC-PH version 4.2 */
303 #define FC_PH_4_3 9 /* FC-PH version 4.3 */
304
305 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
306 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
307 #define FC_PH3 0x20 /* FC-PH-3 version */
308
309 #define FF_FRAME_SIZE 2048
310
311 struct lpfc_name {
312 union {
313 struct {
314 #ifdef __BIG_ENDIAN_BITFIELD
315 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
316 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
317 8:11 of IEEE ext */
318 #else /* __LITTLE_ENDIAN_BITFIELD */
319 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
320 8:11 of IEEE ext */
321 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
322 #endif
323
324 #define NAME_IEEE 0x1 /* IEEE name - nameType */
325 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
326 #define NAME_FC_TYPE 0x3 /* FC native name type */
327 #define NAME_IP_TYPE 0x4 /* IP address */
328 #define NAME_CCITT_TYPE 0xC
329 #define NAME_CCITT_GR_TYPE 0xE
330 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
331 extended Lsb */
332 uint8_t IEEE[6]; /* FC IEEE address */
333 } s;
334 uint8_t wwn[8];
335 } u;
336 };
337
338 struct csp {
339 uint8_t fcphHigh; /* FC Word 0, byte 0 */
340 uint8_t fcphLow;
341 uint8_t bbCreditMsb;
342 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
343
344 #ifdef __BIG_ENDIAN_BITFIELD
345 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
346 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
347 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
348 uint16_t fPort:1; /* FC Word 1, bit 28 */
349 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
350 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
351 uint16_t multicast:1; /* FC Word 1, bit 25 */
352 uint16_t broadcast:1; /* FC Word 1, bit 24 */
353
354 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
355 uint16_t simplex:1; /* FC Word 1, bit 22 */
356 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
357 uint16_t dhd:1; /* FC Word 1, bit 18 */
358 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
359 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
360 #else /* __LITTLE_ENDIAN_BITFIELD */
361 uint16_t broadcast:1; /* FC Word 1, bit 24 */
362 uint16_t multicast:1; /* FC Word 1, bit 25 */
363 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
364 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
365 uint16_t fPort:1; /* FC Word 1, bit 28 */
366 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
367 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
368 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
369
370 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
371 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
372 uint16_t dhd:1; /* FC Word 1, bit 18 */
373 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
374 uint16_t simplex:1; /* FC Word 1, bit 22 */
375 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
376 #endif
377
378 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
379 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
380 union {
381 struct {
382 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
383
384 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
385 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
386
387 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
388 } nPort;
389 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
390 } w2;
391
392 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
393 };
394
395 struct class_parms {
396 #ifdef __BIG_ENDIAN_BITFIELD
397 uint8_t classValid:1; /* FC Word 0, bit 31 */
398 uint8_t intermix:1; /* FC Word 0, bit 30 */
399 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
400 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
401 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
402 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
403 #else /* __LITTLE_ENDIAN_BITFIELD */
404 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
405 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
406 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
407 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
408 uint8_t intermix:1; /* FC Word 0, bit 30 */
409 uint8_t classValid:1; /* FC Word 0, bit 31 */
410
411 #endif
412
413 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
414
415 #ifdef __BIG_ENDIAN_BITFIELD
416 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
417 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
418 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
419 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
420 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
421 #else /* __LITTLE_ENDIAN_BITFIELD */
422 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
423 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
424 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
425 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
426 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
427 #endif
428
429 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
430
431 #ifdef __BIG_ENDIAN_BITFIELD
432 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
433 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
434 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
435 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
436 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
437 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
438 #else /* __LITTLE_ENDIAN_BITFIELD */
439 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
440 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
441 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
442 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
443 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
444 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
445 #endif
446
447 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
448 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
449 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
450
451 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
452 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
453 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
454 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
455
456 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
457 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
458 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
459 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
460 };
461
462 struct serv_parm { /* Structure is in Big Endian format */
463 struct csp cmn;
464 struct lpfc_name portName;
465 struct lpfc_name nodeName;
466 struct class_parms cls1;
467 struct class_parms cls2;
468 struct class_parms cls3;
469 struct class_parms cls4;
470 uint8_t vendorVersion[16];
471 };
472
473 /*
474 * Virtual Fabric Tagging Header
475 */
476 struct fc_vft_header {
477 uint32_t word0;
478 #define fc_vft_hdr_r_ctl_SHIFT 24
479 #define fc_vft_hdr_r_ctl_MASK 0xFF
480 #define fc_vft_hdr_r_ctl_WORD word0
481 #define fc_vft_hdr_ver_SHIFT 22
482 #define fc_vft_hdr_ver_MASK 0x3
483 #define fc_vft_hdr_ver_WORD word0
484 #define fc_vft_hdr_type_SHIFT 18
485 #define fc_vft_hdr_type_MASK 0xF
486 #define fc_vft_hdr_type_WORD word0
487 #define fc_vft_hdr_e_SHIFT 16
488 #define fc_vft_hdr_e_MASK 0x1
489 #define fc_vft_hdr_e_WORD word0
490 #define fc_vft_hdr_priority_SHIFT 13
491 #define fc_vft_hdr_priority_MASK 0x7
492 #define fc_vft_hdr_priority_WORD word0
493 #define fc_vft_hdr_vf_id_SHIFT 1
494 #define fc_vft_hdr_vf_id_MASK 0xFFF
495 #define fc_vft_hdr_vf_id_WORD word0
496 uint32_t word1;
497 #define fc_vft_hdr_hopct_SHIFT 24
498 #define fc_vft_hdr_hopct_MASK 0xFF
499 #define fc_vft_hdr_hopct_WORD word1
500 };
501
502 /*
503 * Extended Link Service LS_COMMAND codes (Payload Word 0)
504 */
505 #ifdef __BIG_ENDIAN_BITFIELD
506 #define ELS_CMD_MASK 0xffff0000
507 #define ELS_RSP_MASK 0xff000000
508 #define ELS_CMD_LS_RJT 0x01000000
509 #define ELS_CMD_ACC 0x02000000
510 #define ELS_CMD_PLOGI 0x03000000
511 #define ELS_CMD_FLOGI 0x04000000
512 #define ELS_CMD_LOGO 0x05000000
513 #define ELS_CMD_ABTX 0x06000000
514 #define ELS_CMD_RCS 0x07000000
515 #define ELS_CMD_RES 0x08000000
516 #define ELS_CMD_RSS 0x09000000
517 #define ELS_CMD_RSI 0x0A000000
518 #define ELS_CMD_ESTS 0x0B000000
519 #define ELS_CMD_ESTC 0x0C000000
520 #define ELS_CMD_ADVC 0x0D000000
521 #define ELS_CMD_RTV 0x0E000000
522 #define ELS_CMD_RLS 0x0F000000
523 #define ELS_CMD_ECHO 0x10000000
524 #define ELS_CMD_TEST 0x11000000
525 #define ELS_CMD_RRQ 0x12000000
526 #define ELS_CMD_PRLI 0x20100014
527 #define ELS_CMD_PRLO 0x21100014
528 #define ELS_CMD_PRLO_ACC 0x02100014
529 #define ELS_CMD_PDISC 0x50000000
530 #define ELS_CMD_FDISC 0x51000000
531 #define ELS_CMD_ADISC 0x52000000
532 #define ELS_CMD_FARP 0x54000000
533 #define ELS_CMD_FARPR 0x55000000
534 #define ELS_CMD_RPS 0x56000000
535 #define ELS_CMD_RPL 0x57000000
536 #define ELS_CMD_FAN 0x60000000
537 #define ELS_CMD_RSCN 0x61040000
538 #define ELS_CMD_SCR 0x62000000
539 #define ELS_CMD_RNID 0x78000000
540 #define ELS_CMD_LIRR 0x7A000000
541 #else /* __LITTLE_ENDIAN_BITFIELD */
542 #define ELS_CMD_MASK 0xffff
543 #define ELS_RSP_MASK 0xff
544 #define ELS_CMD_LS_RJT 0x01
545 #define ELS_CMD_ACC 0x02
546 #define ELS_CMD_PLOGI 0x03
547 #define ELS_CMD_FLOGI 0x04
548 #define ELS_CMD_LOGO 0x05
549 #define ELS_CMD_ABTX 0x06
550 #define ELS_CMD_RCS 0x07
551 #define ELS_CMD_RES 0x08
552 #define ELS_CMD_RSS 0x09
553 #define ELS_CMD_RSI 0x0A
554 #define ELS_CMD_ESTS 0x0B
555 #define ELS_CMD_ESTC 0x0C
556 #define ELS_CMD_ADVC 0x0D
557 #define ELS_CMD_RTV 0x0E
558 #define ELS_CMD_RLS 0x0F
559 #define ELS_CMD_ECHO 0x10
560 #define ELS_CMD_TEST 0x11
561 #define ELS_CMD_RRQ 0x12
562 #define ELS_CMD_PRLI 0x14001020
563 #define ELS_CMD_PRLO 0x14001021
564 #define ELS_CMD_PRLO_ACC 0x14001002
565 #define ELS_CMD_PDISC 0x50
566 #define ELS_CMD_FDISC 0x51
567 #define ELS_CMD_ADISC 0x52
568 #define ELS_CMD_FARP 0x54
569 #define ELS_CMD_FARPR 0x55
570 #define ELS_CMD_RPS 0x56
571 #define ELS_CMD_RPL 0x57
572 #define ELS_CMD_FAN 0x60
573 #define ELS_CMD_RSCN 0x0461
574 #define ELS_CMD_SCR 0x62
575 #define ELS_CMD_RNID 0x78
576 #define ELS_CMD_LIRR 0x7A
577 #endif
578
579 /*
580 * LS_RJT Payload Definition
581 */
582
583 struct ls_rjt { /* Structure is in Big Endian format */
584 union {
585 uint32_t lsRjtError;
586 struct {
587 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
588
589 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
590 /* LS_RJT reason codes */
591 #define LSRJT_INVALID_CMD 0x01
592 #define LSRJT_LOGICAL_ERR 0x03
593 #define LSRJT_LOGICAL_BSY 0x05
594 #define LSRJT_PROTOCOL_ERR 0x07
595 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
596 #define LSRJT_CMD_UNSUPPORTED 0x0B
597 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
598
599 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
600 /* LS_RJT reason explanation */
601 #define LSEXP_NOTHING_MORE 0x00
602 #define LSEXP_SPARM_OPTIONS 0x01
603 #define LSEXP_SPARM_ICTL 0x03
604 #define LSEXP_SPARM_RCTL 0x05
605 #define LSEXP_SPARM_RCV_SIZE 0x07
606 #define LSEXP_SPARM_CONCUR_SEQ 0x09
607 #define LSEXP_SPARM_CREDIT 0x0B
608 #define LSEXP_INVALID_PNAME 0x0D
609 #define LSEXP_INVALID_NNAME 0x0E
610 #define LSEXP_INVALID_CSP 0x0F
611 #define LSEXP_INVALID_ASSOC_HDR 0x11
612 #define LSEXP_ASSOC_HDR_REQ 0x13
613 #define LSEXP_INVALID_O_SID 0x15
614 #define LSEXP_INVALID_OX_RX 0x17
615 #define LSEXP_CMD_IN_PROGRESS 0x19
616 #define LSEXP_PORT_LOGIN_REQ 0x1E
617 #define LSEXP_INVALID_NPORT_ID 0x1F
618 #define LSEXP_INVALID_SEQ_ID 0x21
619 #define LSEXP_INVALID_XCHG 0x23
620 #define LSEXP_INACTIVE_XCHG 0x25
621 #define LSEXP_RQ_REQUIRED 0x27
622 #define LSEXP_OUT_OF_RESOURCE 0x29
623 #define LSEXP_CANT_GIVE_DATA 0x2A
624 #define LSEXP_REQ_UNSUPPORTED 0x2C
625 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
626 } b;
627 } un;
628 };
629
630 /*
631 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
632 */
633
634 typedef struct _LOGO { /* Structure is in Big Endian format */
635 union {
636 uint32_t nPortId32; /* Access nPortId as a word */
637 struct {
638 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
639 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
640 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
641 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
642 } b;
643 } un;
644 struct lpfc_name portName; /* N_port name field */
645 } LOGO;
646
647 /*
648 * FCP Login (PRLI Request / ACC) Payload Definition
649 */
650
651 #define PRLX_PAGE_LEN 0x10
652 #define TPRLO_PAGE_LEN 0x14
653
654 typedef struct _PRLI { /* Structure is in Big Endian format */
655 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
656
657 #define PRLI_FCP_TYPE 0x08
658 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
659
660 #ifdef __BIG_ENDIAN_BITFIELD
661 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
662 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
663 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
664
665 /* ACC = imagePairEstablished */
666 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
667 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
668 #else /* __LITTLE_ENDIAN_BITFIELD */
669 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
670 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
671 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
672 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
673 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
674 /* ACC = imagePairEstablished */
675 #endif
676
677 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
678 #define PRLI_NO_RESOURCES 0x2
679 #define PRLI_INIT_INCOMPLETE 0x3
680 #define PRLI_NO_SUCH_PA 0x4
681 #define PRLI_PREDEF_CONFIG 0x5
682 #define PRLI_PARTIAL_SUCCESS 0x6
683 #define PRLI_INVALID_PAGE_CNT 0x7
684 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
685
686 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
687
688 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
689
690 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
691 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
692
693 #ifdef __BIG_ENDIAN_BITFIELD
694 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
695 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
696 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
697 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
698 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
699 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
700 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
701 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
702 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
703 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
704 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
705 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
706 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
707 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
708 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
709 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
710 #else /* __LITTLE_ENDIAN_BITFIELD */
711 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
712 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
713 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
714 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
715 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
716 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
717 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
718 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
719 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
720 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
721 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
722 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
723 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
724 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
725 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
726 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
727 #endif
728 } PRLI;
729
730 /*
731 * FCP Logout (PRLO Request / ACC) Payload Definition
732 */
733
734 typedef struct _PRLO { /* Structure is in Big Endian format */
735 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
736
737 #define PRLO_FCP_TYPE 0x08
738 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
739
740 #ifdef __BIG_ENDIAN_BITFIELD
741 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
742 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
743 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
744 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
745 #else /* __LITTLE_ENDIAN_BITFIELD */
746 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
747 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
748 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
749 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
750 #endif
751
752 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
753 #define PRLO_NO_SUCH_IMAGE 0x4
754 #define PRLO_INVALID_PAGE_CNT 0x7
755
756 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
757
758 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
759
760 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
761
762 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
763 } PRLO;
764
765 typedef struct _ADISC { /* Structure is in Big Endian format */
766 uint32_t hardAL_PA;
767 struct lpfc_name portName;
768 struct lpfc_name nodeName;
769 uint32_t DID;
770 } ADISC;
771
772 typedef struct _FARP { /* Structure is in Big Endian format */
773 uint32_t Mflags:8;
774 uint32_t Odid:24;
775 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
776 action */
777 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
778 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
779 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
780 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
781 supported */
782 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
783 supported */
784 uint32_t Rflags:8;
785 uint32_t Rdid:24;
786 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
787 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
788 struct lpfc_name OportName;
789 struct lpfc_name OnodeName;
790 struct lpfc_name RportName;
791 struct lpfc_name RnodeName;
792 uint8_t Oipaddr[16];
793 uint8_t Ripaddr[16];
794 } FARP;
795
796 typedef struct _FAN { /* Structure is in Big Endian format */
797 uint32_t Fdid;
798 struct lpfc_name FportName;
799 struct lpfc_name FnodeName;
800 } FAN;
801
802 typedef struct _SCR { /* Structure is in Big Endian format */
803 uint8_t resvd1;
804 uint8_t resvd2;
805 uint8_t resvd3;
806 uint8_t Function;
807 #define SCR_FUNC_FABRIC 0x01
808 #define SCR_FUNC_NPORT 0x02
809 #define SCR_FUNC_FULL 0x03
810 #define SCR_CLEAR 0xff
811 } SCR;
812
813 typedef struct _RNID_TOP_DISC {
814 struct lpfc_name portName;
815 uint8_t resvd[8];
816 uint32_t unitType;
817 #define RNID_HBA 0x7
818 #define RNID_HOST 0xa
819 #define RNID_DRIVER 0xd
820 uint32_t physPort;
821 uint32_t attachedNodes;
822 uint16_t ipVersion;
823 #define RNID_IPV4 0x1
824 #define RNID_IPV6 0x2
825 uint16_t UDPport;
826 uint8_t ipAddr[16];
827 uint16_t resvd1;
828 uint16_t flags;
829 #define RNID_TD_SUPPORT 0x1
830 #define RNID_LP_VALID 0x2
831 } RNID_TOP_DISC;
832
833 typedef struct _RNID { /* Structure is in Big Endian format */
834 uint8_t Format;
835 #define RNID_TOPOLOGY_DISC 0xdf
836 uint8_t CommonLen;
837 uint8_t resvd1;
838 uint8_t SpecificLen;
839 struct lpfc_name portName;
840 struct lpfc_name nodeName;
841 union {
842 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
843 } un;
844 } RNID;
845
846 typedef struct _RPS { /* Structure is in Big Endian format */
847 union {
848 uint32_t portNum;
849 struct lpfc_name portName;
850 } un;
851 } RPS;
852
853 typedef struct _RPS_RSP { /* Structure is in Big Endian format */
854 uint16_t rsvd1;
855 uint16_t portStatus;
856 uint32_t linkFailureCnt;
857 uint32_t lossSyncCnt;
858 uint32_t lossSignalCnt;
859 uint32_t primSeqErrCnt;
860 uint32_t invalidXmitWord;
861 uint32_t crcCnt;
862 } RPS_RSP;
863
864 typedef struct _RPL { /* Structure is in Big Endian format */
865 uint32_t maxsize;
866 uint32_t index;
867 } RPL;
868
869 typedef struct _PORT_NUM_BLK {
870 uint32_t portNum;
871 uint32_t portID;
872 struct lpfc_name portName;
873 } PORT_NUM_BLK;
874
875 typedef struct _RPL_RSP { /* Structure is in Big Endian format */
876 uint32_t listLen;
877 uint32_t index;
878 PORT_NUM_BLK port_num_blk;
879 } RPL_RSP;
880
881 /* This is used for RSCN command */
882 typedef struct _D_ID { /* Structure is in Big Endian format */
883 union {
884 uint32_t word;
885 struct {
886 #ifdef __BIG_ENDIAN_BITFIELD
887 uint8_t resv;
888 uint8_t domain;
889 uint8_t area;
890 uint8_t id;
891 #else /* __LITTLE_ENDIAN_BITFIELD */
892 uint8_t id;
893 uint8_t area;
894 uint8_t domain;
895 uint8_t resv;
896 #endif
897 } b;
898 } un;
899 } D_ID;
900
901 #define RSCN_ADDRESS_FORMAT_PORT 0x0
902 #define RSCN_ADDRESS_FORMAT_AREA 0x1
903 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
904 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3
905 #define RSCN_ADDRESS_FORMAT_MASK 0x3
906
907 /*
908 * Structure to define all ELS Payload types
909 */
910
911 typedef struct _ELS_PKT { /* Structure is in Big Endian format */
912 uint8_t elsCode; /* FC Word 0, bit 24:31 */
913 uint8_t elsByte1;
914 uint8_t elsByte2;
915 uint8_t elsByte3;
916 union {
917 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
918 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
919 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
920 PRLI prli; /* Payload for PRLI/ACC */
921 PRLO prlo; /* Payload for PRLO/ACC */
922 ADISC adisc; /* Payload for ADISC/ACC */
923 FARP farp; /* Payload for FARP/ACC */
924 FAN fan; /* Payload for FAN */
925 SCR scr; /* Payload for SCR/ACC */
926 RNID rnid; /* Payload for RNID */
927 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
928 } un;
929 } ELS_PKT;
930
931 /*
932 * FDMI
933 * HBA MAnagement Operations Command Codes
934 */
935 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
936 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
937 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
938 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
939 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
940 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */
941 #define SLI_MGMT_RPRT 0x210 /* Register Port */
942 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
943 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
944 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
945
946 /*
947 * Management Service Subtypes
948 */
949 #define SLI_CT_FDMI_Subtypes 0x10
950
951 /*
952 * HBA Management Service Reject Code
953 */
954 #define REJECT_CODE 0x9 /* Unable to perform command request */
955
956 /*
957 * HBA Management Service Reject Reason Code
958 * Please refer to the Reason Codes above
959 */
960
961 /*
962 * HBA Attribute Types
963 */
964 #define NODE_NAME 0x1
965 #define MANUFACTURER 0x2
966 #define SERIAL_NUMBER 0x3
967 #define MODEL 0x4
968 #define MODEL_DESCRIPTION 0x5
969 #define HARDWARE_VERSION 0x6
970 #define DRIVER_VERSION 0x7
971 #define OPTION_ROM_VERSION 0x8
972 #define FIRMWARE_VERSION 0x9
973 #define OS_NAME_VERSION 0xa
974 #define MAX_CT_PAYLOAD_LEN 0xb
975
976 /*
977 * Port Attrubute Types
978 */
979 #define SUPPORTED_FC4_TYPES 0x1
980 #define SUPPORTED_SPEED 0x2
981 #define PORT_SPEED 0x3
982 #define MAX_FRAME_SIZE 0x4
983 #define OS_DEVICE_NAME 0x5
984 #define HOST_NAME 0x6
985
986 union AttributesDef {
987 /* Structure is in Big Endian format */
988 struct {
989 uint32_t AttrType:16;
990 uint32_t AttrLen:16;
991 } bits;
992 uint32_t word;
993 };
994
995
996 /*
997 * HBA Attribute Entry (8 - 260 bytes)
998 */
999 typedef struct {
1000 union AttributesDef ad;
1001 union {
1002 uint32_t VendorSpecific;
1003 uint8_t Manufacturer[64];
1004 uint8_t SerialNumber[64];
1005 uint8_t Model[256];
1006 uint8_t ModelDescription[256];
1007 uint8_t HardwareVersion[256];
1008 uint8_t DriverVersion[256];
1009 uint8_t OptionROMVersion[256];
1010 uint8_t FirmwareVersion[256];
1011 struct lpfc_name NodeName;
1012 uint8_t SupportFC4Types[32];
1013 uint32_t SupportSpeed;
1014 uint32_t PortSpeed;
1015 uint32_t MaxFrameSize;
1016 uint8_t OsDeviceName[256];
1017 uint8_t OsNameVersion[256];
1018 uint32_t MaxCTPayloadLen;
1019 uint8_t HostName[256];
1020 } un;
1021 } ATTRIBUTE_ENTRY;
1022
1023 /*
1024 * HBA Attribute Block
1025 */
1026 typedef struct {
1027 uint32_t EntryCnt; /* Number of HBA attribute entries */
1028 ATTRIBUTE_ENTRY Entry; /* Variable-length array */
1029 } ATTRIBUTE_BLOCK;
1030
1031 /*
1032 * Port Entry
1033 */
1034 typedef struct {
1035 struct lpfc_name PortName;
1036 } PORT_ENTRY;
1037
1038 /*
1039 * HBA Identifier
1040 */
1041 typedef struct {
1042 struct lpfc_name PortName;
1043 } HBA_IDENTIFIER;
1044
1045 /*
1046 * Registered Port List Format
1047 */
1048 typedef struct {
1049 uint32_t EntryCnt;
1050 PORT_ENTRY pe; /* Variable-length array */
1051 } REG_PORT_LIST;
1052
1053 /*
1054 * Register HBA(RHBA)
1055 */
1056 typedef struct {
1057 HBA_IDENTIFIER hi;
1058 REG_PORT_LIST rpl; /* variable-length array */
1059 /* ATTRIBUTE_BLOCK ab; */
1060 } REG_HBA;
1061
1062 /*
1063 * Register HBA Attributes (RHAT)
1064 */
1065 typedef struct {
1066 struct lpfc_name HBA_PortName;
1067 ATTRIBUTE_BLOCK ab;
1068 } REG_HBA_ATTRIBUTE;
1069
1070 /*
1071 * Register Port Attributes (RPA)
1072 */
1073 typedef struct {
1074 struct lpfc_name PortName;
1075 ATTRIBUTE_BLOCK ab;
1076 } REG_PORT_ATTRIBUTE;
1077
1078 /*
1079 * Get Registered HBA List (GRHL) Accept Payload Format
1080 */
1081 typedef struct {
1082 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1083 struct lpfc_name HBA_PortName; /* Variable-length array */
1084 } GRHL_ACC_PAYLOAD;
1085
1086 /*
1087 * Get Registered Port List (GRPL) Accept Payload Format
1088 */
1089 typedef struct {
1090 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
1091 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */
1092 } GRPL_ACC_PAYLOAD;
1093
1094 /*
1095 * Get Port Attributes (GPAT) Accept Payload Format
1096 */
1097
1098 typedef struct {
1099 ATTRIBUTE_BLOCK pab;
1100 } GPAT_ACC_PAYLOAD;
1101
1102
1103 /*
1104 * Begin HBA configuration parameters.
1105 * The PCI configuration register BAR assignments are:
1106 * BAR0, offset 0x10 - SLIM base memory address
1107 * BAR1, offset 0x14 - SLIM base memory high address
1108 * BAR2, offset 0x18 - REGISTER base memory address
1109 * BAR3, offset 0x1c - REGISTER base memory high address
1110 * BAR4, offset 0x20 - BIU I/O registers
1111 * BAR5, offset 0x24 - REGISTER base io high address
1112 */
1113
1114 /* Number of rings currently used and available. */
1115 #define MAX_CONFIGURED_RINGS 3
1116 #define MAX_RINGS 4
1117
1118 /* IOCB / Mailbox is owned by FireFly */
1119 #define OWN_CHIP 1
1120
1121 /* IOCB / Mailbox is owned by Host */
1122 #define OWN_HOST 0
1123
1124 /* Number of 4-byte words in an IOCB. */
1125 #define IOCB_WORD_SZ 8
1126
1127 /* network headers for Dfctl field */
1128 #define FC_NET_HDR 0x20
1129
1130 /* Start FireFly Register definitions */
1131 #define PCI_VENDOR_ID_EMULEX 0x10df
1132 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1133 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1134 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1135 #define PCI_DEVICE_ID_SAT_SMB 0xf011
1136 #define PCI_DEVICE_ID_SAT_MID 0xf015
1137 #define PCI_DEVICE_ID_RFLY 0xf095
1138 #define PCI_DEVICE_ID_PFLY 0xf098
1139 #define PCI_DEVICE_ID_LP101 0xf0a1
1140 #define PCI_DEVICE_ID_TFLY 0xf0a5
1141 #define PCI_DEVICE_ID_BSMB 0xf0d1
1142 #define PCI_DEVICE_ID_BMID 0xf0d5
1143 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1144 #define PCI_DEVICE_ID_ZMID 0xf0e5
1145 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1146 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1147 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1148 #define PCI_DEVICE_ID_SAT 0xf100
1149 #define PCI_DEVICE_ID_SAT_SCSP 0xf111
1150 #define PCI_DEVICE_ID_SAT_DCSP 0xf112
1151 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1152 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1153 #define PCI_DEVICE_ID_CENTAUR 0xf900
1154 #define PCI_DEVICE_ID_PEGASUS 0xf980
1155 #define PCI_DEVICE_ID_THOR 0xfa00
1156 #define PCI_DEVICE_ID_VIPER 0xfb00
1157 #define PCI_DEVICE_ID_LP10000S 0xfc00
1158 #define PCI_DEVICE_ID_LP11000S 0xfc10
1159 #define PCI_DEVICE_ID_LPE11000S 0xfc20
1160 #define PCI_DEVICE_ID_SAT_S 0xfc40
1161 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1162 #define PCI_DEVICE_ID_HELIOS 0xfd00
1163 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1164 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1165 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1166 #define PCI_DEVICE_ID_HORNET 0xfe05
1167 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1168 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1169 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1170 #define PCI_DEVICE_ID_TIGERSHARK 0x0704
1171 #define PCI_DEVICE_ID_TOMCAT 0x0714
1172 #define PCI_DEVICE_ID_FALCON 0xf180
1173 #define PCI_DEVICE_ID_BALIUS 0xe131
1174
1175 #define JEDEC_ID_ADDRESS 0x0080001c
1176 #define FIREFLY_JEDEC_ID 0x1ACC
1177 #define SUPERFLY_JEDEC_ID 0x0020
1178 #define DRAGONFLY_JEDEC_ID 0x0021
1179 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1180 #define CENTAUR_2G_JEDEC_ID 0x0026
1181 #define CENTAUR_1G_JEDEC_ID 0x0028
1182 #define PEGASUS_ORION_JEDEC_ID 0x0036
1183 #define PEGASUS_JEDEC_ID 0x0038
1184 #define THOR_JEDEC_ID 0x0012
1185 #define HELIOS_JEDEC_ID 0x0364
1186 #define ZEPHYR_JEDEC_ID 0x0577
1187 #define VIPER_JEDEC_ID 0x4838
1188 #define SATURN_JEDEC_ID 0x1004
1189 #define HORNET_JDEC_ID 0x2057706D
1190
1191 #define JEDEC_ID_MASK 0x0FFFF000
1192 #define JEDEC_ID_SHIFT 12
1193 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1194
1195 typedef struct { /* FireFly BIU registers */
1196 uint32_t hostAtt; /* See definitions for Host Attention
1197 register */
1198 uint32_t chipAtt; /* See definitions for Chip Attention
1199 register */
1200 uint32_t hostStatus; /* See definitions for Host Status register */
1201 uint32_t hostControl; /* See definitions for Host Control register */
1202 uint32_t buiConfig; /* See definitions for BIU configuration
1203 register */
1204 } FF_REGS;
1205
1206 /* IO Register size in bytes */
1207 #define FF_REG_AREA_SIZE 256
1208
1209 /* Host Attention Register */
1210
1211 #define HA_REG_OFFSET 0 /* Byte offset from register base address */
1212
1213 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1214 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1215 #define HA_R0ATT 0x00000008 /* Bit 3 */
1216 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1217 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1218 #define HA_R1ATT 0x00000080 /* Bit 7 */
1219 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1220 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1221 #define HA_R2ATT 0x00000800 /* Bit 11 */
1222 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1223 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1224 #define HA_R3ATT 0x00008000 /* Bit 15 */
1225 #define HA_LATT 0x20000000 /* Bit 29 */
1226 #define HA_MBATT 0x40000000 /* Bit 30 */
1227 #define HA_ERATT 0x80000000 /* Bit 31 */
1228
1229 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1230 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1231 #define HA_RXATT 0x00000008 /* Bit 3 */
1232 #define HA_RXMASK 0x0000000f
1233
1234 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1235 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1236 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1237 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1238
1239 #define HA_R0_POS 3
1240 #define HA_R1_POS 7
1241 #define HA_R2_POS 11
1242 #define HA_R3_POS 15
1243 #define HA_LE_POS 29
1244 #define HA_MB_POS 30
1245 #define HA_ER_POS 31
1246 /* Chip Attention Register */
1247
1248 #define CA_REG_OFFSET 4 /* Byte offset from register base address */
1249
1250 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1251 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1252 #define CA_R0ATT 0x00000008 /* Bit 3 */
1253 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1254 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1255 #define CA_R1ATT 0x00000080 /* Bit 7 */
1256 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1257 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1258 #define CA_R2ATT 0x00000800 /* Bit 11 */
1259 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1260 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1261 #define CA_R3ATT 0x00008000 /* Bit 15 */
1262 #define CA_MBATT 0x40000000 /* Bit 30 */
1263
1264 /* Host Status Register */
1265
1266 #define HS_REG_OFFSET 8 /* Byte offset from register base address */
1267
1268 #define HS_MBRDY 0x00400000 /* Bit 22 */
1269 #define HS_FFRDY 0x00800000 /* Bit 23 */
1270 #define HS_FFER8 0x01000000 /* Bit 24 */
1271 #define HS_FFER7 0x02000000 /* Bit 25 */
1272 #define HS_FFER6 0x04000000 /* Bit 26 */
1273 #define HS_FFER5 0x08000000 /* Bit 27 */
1274 #define HS_FFER4 0x10000000 /* Bit 28 */
1275 #define HS_FFER3 0x20000000 /* Bit 29 */
1276 #define HS_FFER2 0x40000000 /* Bit 30 */
1277 #define HS_FFER1 0x80000000 /* Bit 31 */
1278 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1279 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
1280
1281 /* Host Control Register */
1282
1283 #define HC_REG_OFFSET 12 /* Byte offset from register base address */
1284
1285 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1286 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1287 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1288 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1289 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1290 #define HC_INITHBI 0x02000000 /* Bit 25 */
1291 #define HC_INITMB 0x04000000 /* Bit 26 */
1292 #define HC_INITFF 0x08000000 /* Bit 27 */
1293 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1294 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1295
1296 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1297 #define MSIX_DFLT_ID 0
1298 #define MSIX_RNG0_ID 0
1299 #define MSIX_RNG1_ID 1
1300 #define MSIX_RNG2_ID 2
1301 #define MSIX_RNG3_ID 3
1302
1303 #define MSIX_LINK_ID 4
1304 #define MSIX_MBOX_ID 5
1305
1306 #define MSIX_SPARE0_ID 6
1307 #define MSIX_SPARE1_ID 7
1308
1309 /* Mailbox Commands */
1310 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1311 #define MBX_LOAD_SM 0x01
1312 #define MBX_READ_NV 0x02
1313 #define MBX_WRITE_NV 0x03
1314 #define MBX_RUN_BIU_DIAG 0x04
1315 #define MBX_INIT_LINK 0x05
1316 #define MBX_DOWN_LINK 0x06
1317 #define MBX_CONFIG_LINK 0x07
1318 #define MBX_CONFIG_RING 0x09
1319 #define MBX_RESET_RING 0x0A
1320 #define MBX_READ_CONFIG 0x0B
1321 #define MBX_READ_RCONFIG 0x0C
1322 #define MBX_READ_SPARM 0x0D
1323 #define MBX_READ_STATUS 0x0E
1324 #define MBX_READ_RPI 0x0F
1325 #define MBX_READ_XRI 0x10
1326 #define MBX_READ_REV 0x11
1327 #define MBX_READ_LNK_STAT 0x12
1328 #define MBX_REG_LOGIN 0x13
1329 #define MBX_UNREG_LOGIN 0x14
1330 #define MBX_READ_LA 0x15
1331 #define MBX_CLEAR_LA 0x16
1332 #define MBX_DUMP_MEMORY 0x17
1333 #define MBX_DUMP_CONTEXT 0x18
1334 #define MBX_RUN_DIAGS 0x19
1335 #define MBX_RESTART 0x1A
1336 #define MBX_UPDATE_CFG 0x1B
1337 #define MBX_DOWN_LOAD 0x1C
1338 #define MBX_DEL_LD_ENTRY 0x1D
1339 #define MBX_RUN_PROGRAM 0x1E
1340 #define MBX_SET_MASK 0x20
1341 #define MBX_SET_VARIABLE 0x21
1342 #define MBX_UNREG_D_ID 0x23
1343 #define MBX_KILL_BOARD 0x24
1344 #define MBX_CONFIG_FARP 0x25
1345 #define MBX_BEACON 0x2A
1346 #define MBX_CONFIG_MSI 0x30
1347 #define MBX_HEARTBEAT 0x31
1348 #define MBX_WRITE_VPARMS 0x32
1349 #define MBX_ASYNCEVT_ENABLE 0x33
1350 #define MBX_READ_EVENT_LOG_STATUS 0x37
1351 #define MBX_READ_EVENT_LOG 0x38
1352 #define MBX_WRITE_EVENT_LOG 0x39
1353
1354 #define MBX_PORT_CAPABILITIES 0x3B
1355 #define MBX_PORT_IOV_CONTROL 0x3C
1356
1357 #define MBX_CONFIG_HBQ 0x7C
1358 #define MBX_LOAD_AREA 0x81
1359 #define MBX_RUN_BIU_DIAG64 0x84
1360 #define MBX_CONFIG_PORT 0x88
1361 #define MBX_READ_SPARM64 0x8D
1362 #define MBX_READ_RPI64 0x8F
1363 #define MBX_REG_LOGIN64 0x93
1364 #define MBX_READ_LA64 0x95
1365 #define MBX_REG_VPI 0x96
1366 #define MBX_UNREG_VPI 0x97
1367
1368 #define MBX_WRITE_WWN 0x98
1369 #define MBX_SET_DEBUG 0x99
1370 #define MBX_LOAD_EXP_ROM 0x9C
1371 #define MBX_SLI4_CONFIG 0x9B
1372 #define MBX_SLI4_REQ_FTRS 0x9D
1373 #define MBX_MAX_CMDS 0x9E
1374 #define MBX_RESUME_RPI 0x9E
1375 #define MBX_SLI2_CMD_MASK 0x80
1376 #define MBX_REG_VFI 0x9F
1377 #define MBX_REG_FCFI 0xA0
1378 #define MBX_UNREG_VFI 0xA1
1379 #define MBX_UNREG_FCFI 0xA2
1380 #define MBX_INIT_VFI 0xA3
1381 #define MBX_INIT_VPI 0xA4
1382
1383 /* IOCB Commands */
1384
1385 #define CMD_RCV_SEQUENCE_CX 0x01
1386 #define CMD_XMIT_SEQUENCE_CR 0x02
1387 #define CMD_XMIT_SEQUENCE_CX 0x03
1388 #define CMD_XMIT_BCAST_CN 0x04
1389 #define CMD_XMIT_BCAST_CX 0x05
1390 #define CMD_QUE_RING_BUF_CN 0x06
1391 #define CMD_QUE_XRI_BUF_CX 0x07
1392 #define CMD_IOCB_CONTINUE_CN 0x08
1393 #define CMD_RET_XRI_BUF_CX 0x09
1394 #define CMD_ELS_REQUEST_CR 0x0A
1395 #define CMD_ELS_REQUEST_CX 0x0B
1396 #define CMD_RCV_ELS_REQ_CX 0x0D
1397 #define CMD_ABORT_XRI_CN 0x0E
1398 #define CMD_ABORT_XRI_CX 0x0F
1399 #define CMD_CLOSE_XRI_CN 0x10
1400 #define CMD_CLOSE_XRI_CX 0x11
1401 #define CMD_CREATE_XRI_CR 0x12
1402 #define CMD_CREATE_XRI_CX 0x13
1403 #define CMD_GET_RPI_CN 0x14
1404 #define CMD_XMIT_ELS_RSP_CX 0x15
1405 #define CMD_GET_RPI_CR 0x16
1406 #define CMD_XRI_ABORTED_CX 0x17
1407 #define CMD_FCP_IWRITE_CR 0x18
1408 #define CMD_FCP_IWRITE_CX 0x19
1409 #define CMD_FCP_IREAD_CR 0x1A
1410 #define CMD_FCP_IREAD_CX 0x1B
1411 #define CMD_FCP_ICMND_CR 0x1C
1412 #define CMD_FCP_ICMND_CX 0x1D
1413 #define CMD_FCP_TSEND_CX 0x1F
1414 #define CMD_FCP_TRECEIVE_CX 0x21
1415 #define CMD_FCP_TRSP_CX 0x23
1416 #define CMD_FCP_AUTO_TRSP_CX 0x29
1417
1418 #define CMD_ADAPTER_MSG 0x20
1419 #define CMD_ADAPTER_DUMP 0x22
1420
1421 /* SLI_2 IOCB Command Set */
1422
1423 #define CMD_ASYNC_STATUS 0x7C
1424 #define CMD_RCV_SEQUENCE64_CX 0x81
1425 #define CMD_XMIT_SEQUENCE64_CR 0x82
1426 #define CMD_XMIT_SEQUENCE64_CX 0x83
1427 #define CMD_XMIT_BCAST64_CN 0x84
1428 #define CMD_XMIT_BCAST64_CX 0x85
1429 #define CMD_QUE_RING_BUF64_CN 0x86
1430 #define CMD_QUE_XRI_BUF64_CX 0x87
1431 #define CMD_IOCB_CONTINUE64_CN 0x88
1432 #define CMD_RET_XRI_BUF64_CX 0x89
1433 #define CMD_ELS_REQUEST64_CR 0x8A
1434 #define CMD_ELS_REQUEST64_CX 0x8B
1435 #define CMD_ABORT_MXRI64_CN 0x8C
1436 #define CMD_RCV_ELS_REQ64_CX 0x8D
1437 #define CMD_XMIT_ELS_RSP64_CX 0x95
1438 #define CMD_XMIT_BLS_RSP64_CX 0x97
1439 #define CMD_FCP_IWRITE64_CR 0x98
1440 #define CMD_FCP_IWRITE64_CX 0x99
1441 #define CMD_FCP_IREAD64_CR 0x9A
1442 #define CMD_FCP_IREAD64_CX 0x9B
1443 #define CMD_FCP_ICMND64_CR 0x9C
1444 #define CMD_FCP_ICMND64_CX 0x9D
1445 #define CMD_FCP_TSEND64_CX 0x9F
1446 #define CMD_FCP_TRECEIVE64_CX 0xA1
1447 #define CMD_FCP_TRSP64_CX 0xA3
1448
1449 #define CMD_QUE_XRI64_CX 0xB3
1450 #define CMD_IOCB_RCV_SEQ64_CX 0xB5
1451 #define CMD_IOCB_RCV_ELS64_CX 0xB7
1452 #define CMD_IOCB_RET_XRI64_CX 0xB9
1453 #define CMD_IOCB_RCV_CONT64_CX 0xBB
1454
1455 #define CMD_GEN_REQUEST64_CR 0xC2
1456 #define CMD_GEN_REQUEST64_CX 0xC3
1457
1458 /* Unhandled SLI-3 Commands */
1459 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1460 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1461 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1462 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1463 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1464 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1465 #define CMD_IOCB_RET_HBQE64_CN 0xCA
1466 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1467 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1468 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1469 #define CMD_IOCB_LOGENTRY_CN 0x94
1470 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1471
1472 /* Data Security SLI Commands */
1473 #define DSSCMD_IWRITE64_CR 0xF8
1474 #define DSSCMD_IWRITE64_CX 0xF9
1475 #define DSSCMD_IREAD64_CR 0xFA
1476 #define DSSCMD_IREAD64_CX 0xFB
1477
1478 #define CMD_MAX_IOCB_CMD 0xFB
1479 #define CMD_IOCB_MASK 0xff
1480
1481 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1482 iocb */
1483 #define LPFC_MAX_ADPTMSG 32 /* max msg data */
1484 /*
1485 * Define Status
1486 */
1487 #define MBX_SUCCESS 0
1488 #define MBXERR_NUM_RINGS 1
1489 #define MBXERR_NUM_IOCBS 2
1490 #define MBXERR_IOCBS_EXCEEDED 3
1491 #define MBXERR_BAD_RING_NUMBER 4
1492 #define MBXERR_MASK_ENTRIES_RANGE 5
1493 #define MBXERR_MASKS_EXCEEDED 6
1494 #define MBXERR_BAD_PROFILE 7
1495 #define MBXERR_BAD_DEF_CLASS 8
1496 #define MBXERR_BAD_MAX_RESPONDER 9
1497 #define MBXERR_BAD_MAX_ORIGINATOR 10
1498 #define MBXERR_RPI_REGISTERED 11
1499 #define MBXERR_RPI_FULL 12
1500 #define MBXERR_NO_RESOURCES 13
1501 #define MBXERR_BAD_RCV_LENGTH 14
1502 #define MBXERR_DMA_ERROR 15
1503 #define MBXERR_ERROR 16
1504 #define MBXERR_LINK_DOWN 0x33
1505 #define MBX_NOT_FINISHED 255
1506
1507 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1508 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1509
1510 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1511
1512 /*
1513 * Begin Structure Definitions for Mailbox Commands
1514 */
1515
1516 typedef struct {
1517 #ifdef __BIG_ENDIAN_BITFIELD
1518 uint8_t tval;
1519 uint8_t tmask;
1520 uint8_t rval;
1521 uint8_t rmask;
1522 #else /* __LITTLE_ENDIAN_BITFIELD */
1523 uint8_t rmask;
1524 uint8_t rval;
1525 uint8_t tmask;
1526 uint8_t tval;
1527 #endif
1528 } RR_REG;
1529
1530 struct ulp_bde {
1531 uint32_t bdeAddress;
1532 #ifdef __BIG_ENDIAN_BITFIELD
1533 uint32_t bdeReserved:4;
1534 uint32_t bdeAddrHigh:4;
1535 uint32_t bdeSize:24;
1536 #else /* __LITTLE_ENDIAN_BITFIELD */
1537 uint32_t bdeSize:24;
1538 uint32_t bdeAddrHigh:4;
1539 uint32_t bdeReserved:4;
1540 #endif
1541 };
1542
1543 typedef struct ULP_BDL { /* SLI-2 */
1544 #ifdef __BIG_ENDIAN_BITFIELD
1545 uint32_t bdeFlags:8; /* BDL Flags */
1546 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1547 #else /* __LITTLE_ENDIAN_BITFIELD */
1548 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1549 uint32_t bdeFlags:8; /* BDL Flags */
1550 #endif
1551
1552 uint32_t addrLow; /* Address 0:31 */
1553 uint32_t addrHigh; /* Address 32:63 */
1554 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1555 } ULP_BDL;
1556
1557 /*
1558 * BlockGuard Definitions
1559 */
1560
1561 enum lpfc_protgrp_type {
1562 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
1563 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
1564 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
1565 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
1566 };
1567
1568 /* PDE Descriptors */
1569 #define LPFC_PDE5_DESCRIPTOR 0x85
1570 #define LPFC_PDE6_DESCRIPTOR 0x86
1571 #define LPFC_PDE7_DESCRIPTOR 0x87
1572
1573 /* BlockGuard Opcodes */
1574 #define BG_OP_IN_NODIF_OUT_CRC 0x0
1575 #define BG_OP_IN_CRC_OUT_NODIF 0x1
1576 #define BG_OP_IN_NODIF_OUT_CSUM 0x2
1577 #define BG_OP_IN_CSUM_OUT_NODIF 0x3
1578 #define BG_OP_IN_CRC_OUT_CRC 0x4
1579 #define BG_OP_IN_CSUM_OUT_CSUM 0x5
1580 #define BG_OP_IN_CRC_OUT_CSUM 0x6
1581 #define BG_OP_IN_CSUM_OUT_CRC 0x7
1582
1583 struct lpfc_pde5 {
1584 uint32_t word0;
1585 #define pde5_type_SHIFT 24
1586 #define pde5_type_MASK 0x000000ff
1587 #define pde5_type_WORD word0
1588 #define pde5_rsvd0_SHIFT 0
1589 #define pde5_rsvd0_MASK 0x00ffffff
1590 #define pde5_rsvd0_WORD word0
1591 uint32_t reftag; /* Reference Tag Value */
1592 uint32_t reftagtr; /* Reference Tag Translation Value */
1593 };
1594
1595 struct lpfc_pde6 {
1596 uint32_t word0;
1597 #define pde6_type_SHIFT 24
1598 #define pde6_type_MASK 0x000000ff
1599 #define pde6_type_WORD word0
1600 #define pde6_rsvd0_SHIFT 0
1601 #define pde6_rsvd0_MASK 0x00ffffff
1602 #define pde6_rsvd0_WORD word0
1603 uint32_t word1;
1604 #define pde6_rsvd1_SHIFT 26
1605 #define pde6_rsvd1_MASK 0x0000003f
1606 #define pde6_rsvd1_WORD word1
1607 #define pde6_na_SHIFT 25
1608 #define pde6_na_MASK 0x00000001
1609 #define pde6_na_WORD word1
1610 #define pde6_rsvd2_SHIFT 16
1611 #define pde6_rsvd2_MASK 0x000001FF
1612 #define pde6_rsvd2_WORD word1
1613 #define pde6_apptagtr_SHIFT 0
1614 #define pde6_apptagtr_MASK 0x0000ffff
1615 #define pde6_apptagtr_WORD word1
1616 uint32_t word2;
1617 #define pde6_optx_SHIFT 28
1618 #define pde6_optx_MASK 0x0000000f
1619 #define pde6_optx_WORD word2
1620 #define pde6_oprx_SHIFT 24
1621 #define pde6_oprx_MASK 0x0000000f
1622 #define pde6_oprx_WORD word2
1623 #define pde6_nr_SHIFT 23
1624 #define pde6_nr_MASK 0x00000001
1625 #define pde6_nr_WORD word2
1626 #define pde6_ce_SHIFT 22
1627 #define pde6_ce_MASK 0x00000001
1628 #define pde6_ce_WORD word2
1629 #define pde6_re_SHIFT 21
1630 #define pde6_re_MASK 0x00000001
1631 #define pde6_re_WORD word2
1632 #define pde6_ae_SHIFT 20
1633 #define pde6_ae_MASK 0x00000001
1634 #define pde6_ae_WORD word2
1635 #define pde6_ai_SHIFT 19
1636 #define pde6_ai_MASK 0x00000001
1637 #define pde6_ai_WORD word2
1638 #define pde6_bs_SHIFT 16
1639 #define pde6_bs_MASK 0x00000007
1640 #define pde6_bs_WORD word2
1641 #define pde6_apptagval_SHIFT 0
1642 #define pde6_apptagval_MASK 0x0000ffff
1643 #define pde6_apptagval_WORD word2
1644 };
1645
1646
1647 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1648
1649 typedef struct {
1650 #ifdef __BIG_ENDIAN_BITFIELD
1651 uint32_t rsvd2:25;
1652 uint32_t acknowledgment:1;
1653 uint32_t version:1;
1654 uint32_t erase_or_prog:1;
1655 uint32_t update_flash:1;
1656 uint32_t update_ram:1;
1657 uint32_t method:1;
1658 uint32_t load_cmplt:1;
1659 #else /* __LITTLE_ENDIAN_BITFIELD */
1660 uint32_t load_cmplt:1;
1661 uint32_t method:1;
1662 uint32_t update_ram:1;
1663 uint32_t update_flash:1;
1664 uint32_t erase_or_prog:1;
1665 uint32_t version:1;
1666 uint32_t acknowledgment:1;
1667 uint32_t rsvd2:25;
1668 #endif
1669
1670 uint32_t dl_to_adr_low;
1671 uint32_t dl_to_adr_high;
1672 uint32_t dl_len;
1673 union {
1674 uint32_t dl_from_mbx_offset;
1675 struct ulp_bde dl_from_bde;
1676 struct ulp_bde64 dl_from_bde64;
1677 } un;
1678
1679 } LOAD_SM_VAR;
1680
1681 /* Structure for MB Command READ_NVPARM (02) */
1682
1683 typedef struct {
1684 uint32_t rsvd1[3]; /* Read as all one's */
1685 uint32_t rsvd2; /* Read as all zero's */
1686 uint32_t portname[2]; /* N_PORT name */
1687 uint32_t nodename[2]; /* NODE name */
1688
1689 #ifdef __BIG_ENDIAN_BITFIELD
1690 uint32_t pref_DID:24;
1691 uint32_t hardAL_PA:8;
1692 #else /* __LITTLE_ENDIAN_BITFIELD */
1693 uint32_t hardAL_PA:8;
1694 uint32_t pref_DID:24;
1695 #endif
1696
1697 uint32_t rsvd3[21]; /* Read as all one's */
1698 } READ_NV_VAR;
1699
1700 /* Structure for MB Command WRITE_NVPARMS (03) */
1701
1702 typedef struct {
1703 uint32_t rsvd1[3]; /* Must be all one's */
1704 uint32_t rsvd2; /* Must be all zero's */
1705 uint32_t portname[2]; /* N_PORT name */
1706 uint32_t nodename[2]; /* NODE name */
1707
1708 #ifdef __BIG_ENDIAN_BITFIELD
1709 uint32_t pref_DID:24;
1710 uint32_t hardAL_PA:8;
1711 #else /* __LITTLE_ENDIAN_BITFIELD */
1712 uint32_t hardAL_PA:8;
1713 uint32_t pref_DID:24;
1714 #endif
1715
1716 uint32_t rsvd3[21]; /* Must be all one's */
1717 } WRITE_NV_VAR;
1718
1719 /* Structure for MB Command RUN_BIU_DIAG (04) */
1720 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1721
1722 typedef struct {
1723 uint32_t rsvd1;
1724 union {
1725 struct {
1726 struct ulp_bde xmit_bde;
1727 struct ulp_bde rcv_bde;
1728 } s1;
1729 struct {
1730 struct ulp_bde64 xmit_bde64;
1731 struct ulp_bde64 rcv_bde64;
1732 } s2;
1733 } un;
1734 } BIU_DIAG_VAR;
1735
1736 /* Structure for MB command READ_EVENT_LOG (0x38) */
1737 struct READ_EVENT_LOG_VAR {
1738 uint32_t word1;
1739 #define lpfc_event_log_SHIFT 29
1740 #define lpfc_event_log_MASK 0x00000001
1741 #define lpfc_event_log_WORD word1
1742 #define USE_MAILBOX_RESPONSE 1
1743 uint32_t offset;
1744 struct ulp_bde64 rcv_bde64;
1745 };
1746
1747 /* Structure for MB Command INIT_LINK (05) */
1748
1749 typedef struct {
1750 #ifdef __BIG_ENDIAN_BITFIELD
1751 uint32_t rsvd1:24;
1752 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1753 #else /* __LITTLE_ENDIAN_BITFIELD */
1754 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1755 uint32_t rsvd1:24;
1756 #endif
1757
1758 #ifdef __BIG_ENDIAN_BITFIELD
1759 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1760 uint8_t rsvd2;
1761 uint16_t link_flags;
1762 #else /* __LITTLE_ENDIAN_BITFIELD */
1763 uint16_t link_flags;
1764 uint8_t rsvd2;
1765 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1766 #endif
1767
1768 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
1769 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
1770 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
1771 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
1772 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
1773 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
1774 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
1775
1776 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
1777 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
1778 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
1779
1780 uint32_t link_speed;
1781 #define LINK_SPEED_AUTO 0 /* Auto selection */
1782 #define LINK_SPEED_1G 1 /* 1 Gigabaud */
1783 #define LINK_SPEED_2G 2 /* 2 Gigabaud */
1784 #define LINK_SPEED_4G 4 /* 4 Gigabaud */
1785 #define LINK_SPEED_8G 8 /* 8 Gigabaud */
1786 #define LINK_SPEED_10G 16 /* 10 Gigabaud */
1787
1788 } INIT_LINK_VAR;
1789
1790 /* Structure for MB Command DOWN_LINK (06) */
1791
1792 typedef struct {
1793 uint32_t rsvd1;
1794 } DOWN_LINK_VAR;
1795
1796 /* Structure for MB Command CONFIG_LINK (07) */
1797
1798 typedef struct {
1799 #ifdef __BIG_ENDIAN_BITFIELD
1800 uint32_t cr:1;
1801 uint32_t ci:1;
1802 uint32_t cr_delay:6;
1803 uint32_t cr_count:8;
1804 uint32_t rsvd1:8;
1805 uint32_t MaxBBC:8;
1806 #else /* __LITTLE_ENDIAN_BITFIELD */
1807 uint32_t MaxBBC:8;
1808 uint32_t rsvd1:8;
1809 uint32_t cr_count:8;
1810 uint32_t cr_delay:6;
1811 uint32_t ci:1;
1812 uint32_t cr:1;
1813 #endif
1814
1815 uint32_t myId;
1816 uint32_t rsvd2;
1817 uint32_t edtov;
1818 uint32_t arbtov;
1819 uint32_t ratov;
1820 uint32_t rttov;
1821 uint32_t altov;
1822 uint32_t crtov;
1823 uint32_t citov;
1824 #ifdef __BIG_ENDIAN_BITFIELD
1825 uint32_t rrq_enable:1;
1826 uint32_t rrq_immed:1;
1827 uint32_t rsvd4:29;
1828 uint32_t ack0_enable:1;
1829 #else /* __LITTLE_ENDIAN_BITFIELD */
1830 uint32_t ack0_enable:1;
1831 uint32_t rsvd4:29;
1832 uint32_t rrq_immed:1;
1833 uint32_t rrq_enable:1;
1834 #endif
1835 } CONFIG_LINK;
1836
1837 /* Structure for MB Command PART_SLIM (08)
1838 * will be removed since SLI1 is no longer supported!
1839 */
1840 typedef struct {
1841 #ifdef __BIG_ENDIAN_BITFIELD
1842 uint16_t offCiocb;
1843 uint16_t numCiocb;
1844 uint16_t offRiocb;
1845 uint16_t numRiocb;
1846 #else /* __LITTLE_ENDIAN_BITFIELD */
1847 uint16_t numCiocb;
1848 uint16_t offCiocb;
1849 uint16_t numRiocb;
1850 uint16_t offRiocb;
1851 #endif
1852 } RING_DEF;
1853
1854 typedef struct {
1855 #ifdef __BIG_ENDIAN_BITFIELD
1856 uint32_t unused1:24;
1857 uint32_t numRing:8;
1858 #else /* __LITTLE_ENDIAN_BITFIELD */
1859 uint32_t numRing:8;
1860 uint32_t unused1:24;
1861 #endif
1862
1863 RING_DEF ringdef[4];
1864 uint32_t hbainit;
1865 } PART_SLIM_VAR;
1866
1867 /* Structure for MB Command CONFIG_RING (09) */
1868
1869 typedef struct {
1870 #ifdef __BIG_ENDIAN_BITFIELD
1871 uint32_t unused2:6;
1872 uint32_t recvSeq:1;
1873 uint32_t recvNotify:1;
1874 uint32_t numMask:8;
1875 uint32_t profile:8;
1876 uint32_t unused1:4;
1877 uint32_t ring:4;
1878 #else /* __LITTLE_ENDIAN_BITFIELD */
1879 uint32_t ring:4;
1880 uint32_t unused1:4;
1881 uint32_t profile:8;
1882 uint32_t numMask:8;
1883 uint32_t recvNotify:1;
1884 uint32_t recvSeq:1;
1885 uint32_t unused2:6;
1886 #endif
1887
1888 #ifdef __BIG_ENDIAN_BITFIELD
1889 uint16_t maxRespXchg;
1890 uint16_t maxOrigXchg;
1891 #else /* __LITTLE_ENDIAN_BITFIELD */
1892 uint16_t maxOrigXchg;
1893 uint16_t maxRespXchg;
1894 #endif
1895
1896 RR_REG rrRegs[6];
1897 } CONFIG_RING_VAR;
1898
1899 /* Structure for MB Command RESET_RING (10) */
1900
1901 typedef struct {
1902 uint32_t ring_no;
1903 } RESET_RING_VAR;
1904
1905 /* Structure for MB Command READ_CONFIG (11) */
1906
1907 typedef struct {
1908 #ifdef __BIG_ENDIAN_BITFIELD
1909 uint32_t cr:1;
1910 uint32_t ci:1;
1911 uint32_t cr_delay:6;
1912 uint32_t cr_count:8;
1913 uint32_t InitBBC:8;
1914 uint32_t MaxBBC:8;
1915 #else /* __LITTLE_ENDIAN_BITFIELD */
1916 uint32_t MaxBBC:8;
1917 uint32_t InitBBC:8;
1918 uint32_t cr_count:8;
1919 uint32_t cr_delay:6;
1920 uint32_t ci:1;
1921 uint32_t cr:1;
1922 #endif
1923
1924 #ifdef __BIG_ENDIAN_BITFIELD
1925 uint32_t topology:8;
1926 uint32_t myDid:24;
1927 #else /* __LITTLE_ENDIAN_BITFIELD */
1928 uint32_t myDid:24;
1929 uint32_t topology:8;
1930 #endif
1931
1932 /* Defines for topology (defined previously) */
1933 #ifdef __BIG_ENDIAN_BITFIELD
1934 uint32_t AR:1;
1935 uint32_t IR:1;
1936 uint32_t rsvd1:29;
1937 uint32_t ack0:1;
1938 #else /* __LITTLE_ENDIAN_BITFIELD */
1939 uint32_t ack0:1;
1940 uint32_t rsvd1:29;
1941 uint32_t IR:1;
1942 uint32_t AR:1;
1943 #endif
1944
1945 uint32_t edtov;
1946 uint32_t arbtov;
1947 uint32_t ratov;
1948 uint32_t rttov;
1949 uint32_t altov;
1950 uint32_t lmt;
1951 #define LMT_RESERVED 0x000 /* Not used */
1952 #define LMT_1Gb 0x004
1953 #define LMT_2Gb 0x008
1954 #define LMT_4Gb 0x040
1955 #define LMT_8Gb 0x080
1956 #define LMT_10Gb 0x100
1957 uint32_t rsvd2;
1958 uint32_t rsvd3;
1959 uint32_t max_xri;
1960 uint32_t max_iocb;
1961 uint32_t max_rpi;
1962 uint32_t avail_xri;
1963 uint32_t avail_iocb;
1964 uint32_t avail_rpi;
1965 uint32_t max_vpi;
1966 uint32_t rsvd4;
1967 uint32_t rsvd5;
1968 uint32_t avail_vpi;
1969 } READ_CONFIG_VAR;
1970
1971 /* Structure for MB Command READ_RCONFIG (12) */
1972
1973 typedef struct {
1974 #ifdef __BIG_ENDIAN_BITFIELD
1975 uint32_t rsvd2:7;
1976 uint32_t recvNotify:1;
1977 uint32_t numMask:8;
1978 uint32_t profile:8;
1979 uint32_t rsvd1:4;
1980 uint32_t ring:4;
1981 #else /* __LITTLE_ENDIAN_BITFIELD */
1982 uint32_t ring:4;
1983 uint32_t rsvd1:4;
1984 uint32_t profile:8;
1985 uint32_t numMask:8;
1986 uint32_t recvNotify:1;
1987 uint32_t rsvd2:7;
1988 #endif
1989
1990 #ifdef __BIG_ENDIAN_BITFIELD
1991 uint16_t maxResp;
1992 uint16_t maxOrig;
1993 #else /* __LITTLE_ENDIAN_BITFIELD */
1994 uint16_t maxOrig;
1995 uint16_t maxResp;
1996 #endif
1997
1998 RR_REG rrRegs[6];
1999
2000 #ifdef __BIG_ENDIAN_BITFIELD
2001 uint16_t cmdRingOffset;
2002 uint16_t cmdEntryCnt;
2003 uint16_t rspRingOffset;
2004 uint16_t rspEntryCnt;
2005 uint16_t nextCmdOffset;
2006 uint16_t rsvd3;
2007 uint16_t nextRspOffset;
2008 uint16_t rsvd4;
2009 #else /* __LITTLE_ENDIAN_BITFIELD */
2010 uint16_t cmdEntryCnt;
2011 uint16_t cmdRingOffset;
2012 uint16_t rspEntryCnt;
2013 uint16_t rspRingOffset;
2014 uint16_t rsvd3;
2015 uint16_t nextCmdOffset;
2016 uint16_t rsvd4;
2017 uint16_t nextRspOffset;
2018 #endif
2019 } READ_RCONF_VAR;
2020
2021 /* Structure for MB Command READ_SPARM (13) */
2022 /* Structure for MB Command READ_SPARM64 (0x8D) */
2023
2024 typedef struct {
2025 uint32_t rsvd1;
2026 uint32_t rsvd2;
2027 union {
2028 struct ulp_bde sp; /* This BDE points to struct serv_parm
2029 structure */
2030 struct ulp_bde64 sp64;
2031 } un;
2032 #ifdef __BIG_ENDIAN_BITFIELD
2033 uint16_t rsvd3;
2034 uint16_t vpi;
2035 #else /* __LITTLE_ENDIAN_BITFIELD */
2036 uint16_t vpi;
2037 uint16_t rsvd3;
2038 #endif
2039 } READ_SPARM_VAR;
2040
2041 /* Structure for MB Command READ_STATUS (14) */
2042
2043 typedef struct {
2044 #ifdef __BIG_ENDIAN_BITFIELD
2045 uint32_t rsvd1:31;
2046 uint32_t clrCounters:1;
2047 uint16_t activeXriCnt;
2048 uint16_t activeRpiCnt;
2049 #else /* __LITTLE_ENDIAN_BITFIELD */
2050 uint32_t clrCounters:1;
2051 uint32_t rsvd1:31;
2052 uint16_t activeRpiCnt;
2053 uint16_t activeXriCnt;
2054 #endif
2055
2056 uint32_t xmitByteCnt;
2057 uint32_t rcvByteCnt;
2058 uint32_t xmitFrameCnt;
2059 uint32_t rcvFrameCnt;
2060 uint32_t xmitSeqCnt;
2061 uint32_t rcvSeqCnt;
2062 uint32_t totalOrigExchanges;
2063 uint32_t totalRespExchanges;
2064 uint32_t rcvPbsyCnt;
2065 uint32_t rcvFbsyCnt;
2066 } READ_STATUS_VAR;
2067
2068 /* Structure for MB Command READ_RPI (15) */
2069 /* Structure for MB Command READ_RPI64 (0x8F) */
2070
2071 typedef struct {
2072 #ifdef __BIG_ENDIAN_BITFIELD
2073 uint16_t nextRpi;
2074 uint16_t reqRpi;
2075 uint32_t rsvd2:8;
2076 uint32_t DID:24;
2077 #else /* __LITTLE_ENDIAN_BITFIELD */
2078 uint16_t reqRpi;
2079 uint16_t nextRpi;
2080 uint32_t DID:24;
2081 uint32_t rsvd2:8;
2082 #endif
2083
2084 union {
2085 struct ulp_bde sp;
2086 struct ulp_bde64 sp64;
2087 } un;
2088
2089 } READ_RPI_VAR;
2090
2091 /* Structure for MB Command READ_XRI (16) */
2092
2093 typedef struct {
2094 #ifdef __BIG_ENDIAN_BITFIELD
2095 uint16_t nextXri;
2096 uint16_t reqXri;
2097 uint16_t rsvd1;
2098 uint16_t rpi;
2099 uint32_t rsvd2:8;
2100 uint32_t DID:24;
2101 uint32_t rsvd3:8;
2102 uint32_t SID:24;
2103 uint32_t rsvd4;
2104 uint8_t seqId;
2105 uint8_t rsvd5;
2106 uint16_t seqCount;
2107 uint16_t oxId;
2108 uint16_t rxId;
2109 uint32_t rsvd6:30;
2110 uint32_t si:1;
2111 uint32_t exchOrig:1;
2112 #else /* __LITTLE_ENDIAN_BITFIELD */
2113 uint16_t reqXri;
2114 uint16_t nextXri;
2115 uint16_t rpi;
2116 uint16_t rsvd1;
2117 uint32_t DID:24;
2118 uint32_t rsvd2:8;
2119 uint32_t SID:24;
2120 uint32_t rsvd3:8;
2121 uint32_t rsvd4;
2122 uint16_t seqCount;
2123 uint8_t rsvd5;
2124 uint8_t seqId;
2125 uint16_t rxId;
2126 uint16_t oxId;
2127 uint32_t exchOrig:1;
2128 uint32_t si:1;
2129 uint32_t rsvd6:30;
2130 #endif
2131 } READ_XRI_VAR;
2132
2133 /* Structure for MB Command READ_REV (17) */
2134
2135 typedef struct {
2136 #ifdef __BIG_ENDIAN_BITFIELD
2137 uint32_t cv:1;
2138 uint32_t rr:1;
2139 uint32_t rsvd2:2;
2140 uint32_t v3req:1;
2141 uint32_t v3rsp:1;
2142 uint32_t rsvd1:25;
2143 uint32_t rv:1;
2144 #else /* __LITTLE_ENDIAN_BITFIELD */
2145 uint32_t rv:1;
2146 uint32_t rsvd1:25;
2147 uint32_t v3rsp:1;
2148 uint32_t v3req:1;
2149 uint32_t rsvd2:2;
2150 uint32_t rr:1;
2151 uint32_t cv:1;
2152 #endif
2153
2154 uint32_t biuRev;
2155 uint32_t smRev;
2156 union {
2157 uint32_t smFwRev;
2158 struct {
2159 #ifdef __BIG_ENDIAN_BITFIELD
2160 uint8_t ProgType;
2161 uint8_t ProgId;
2162 uint16_t ProgVer:4;
2163 uint16_t ProgRev:4;
2164 uint16_t ProgFixLvl:2;
2165 uint16_t ProgDistType:2;
2166 uint16_t DistCnt:4;
2167 #else /* __LITTLE_ENDIAN_BITFIELD */
2168 uint16_t DistCnt:4;
2169 uint16_t ProgDistType:2;
2170 uint16_t ProgFixLvl:2;
2171 uint16_t ProgRev:4;
2172 uint16_t ProgVer:4;
2173 uint8_t ProgId;
2174 uint8_t ProgType;
2175 #endif
2176
2177 } b;
2178 } un;
2179 uint32_t endecRev;
2180 #ifdef __BIG_ENDIAN_BITFIELD
2181 uint8_t feaLevelHigh;
2182 uint8_t feaLevelLow;
2183 uint8_t fcphHigh;
2184 uint8_t fcphLow;
2185 #else /* __LITTLE_ENDIAN_BITFIELD */
2186 uint8_t fcphLow;
2187 uint8_t fcphHigh;
2188 uint8_t feaLevelLow;
2189 uint8_t feaLevelHigh;
2190 #endif
2191
2192 uint32_t postKernRev;
2193 uint32_t opFwRev;
2194 uint8_t opFwName[16];
2195 uint32_t sli1FwRev;
2196 uint8_t sli1FwName[16];
2197 uint32_t sli2FwRev;
2198 uint8_t sli2FwName[16];
2199 uint32_t sli3Feat;
2200 uint32_t RandomData[6];
2201 } READ_REV_VAR;
2202
2203 /* Structure for MB Command READ_LINK_STAT (18) */
2204
2205 typedef struct {
2206 uint32_t rsvd1;
2207 uint32_t linkFailureCnt;
2208 uint32_t lossSyncCnt;
2209
2210 uint32_t lossSignalCnt;
2211 uint32_t primSeqErrCnt;
2212 uint32_t invalidXmitWord;
2213 uint32_t crcCnt;
2214 uint32_t primSeqTimeout;
2215 uint32_t elasticOverrun;
2216 uint32_t arbTimeout;
2217 } READ_LNK_VAR;
2218
2219 /* Structure for MB Command REG_LOGIN (19) */
2220 /* Structure for MB Command REG_LOGIN64 (0x93) */
2221
2222 typedef struct {
2223 #ifdef __BIG_ENDIAN_BITFIELD
2224 uint16_t rsvd1;
2225 uint16_t rpi;
2226 uint32_t rsvd2:8;
2227 uint32_t did:24;
2228 #else /* __LITTLE_ENDIAN_BITFIELD */
2229 uint16_t rpi;
2230 uint16_t rsvd1;
2231 uint32_t did:24;
2232 uint32_t rsvd2:8;
2233 #endif
2234
2235 union {
2236 struct ulp_bde sp;
2237 struct ulp_bde64 sp64;
2238 } un;
2239
2240 #ifdef __BIG_ENDIAN_BITFIELD
2241 uint16_t rsvd6;
2242 uint16_t vpi;
2243 #else /* __LITTLE_ENDIAN_BITFIELD */
2244 uint16_t vpi;
2245 uint16_t rsvd6;
2246 #endif
2247
2248 } REG_LOGIN_VAR;
2249
2250 /* Word 30 contents for REG_LOGIN */
2251 typedef union {
2252 struct {
2253 #ifdef __BIG_ENDIAN_BITFIELD
2254 uint16_t rsvd1:12;
2255 uint16_t wd30_class:4;
2256 uint16_t xri;
2257 #else /* __LITTLE_ENDIAN_BITFIELD */
2258 uint16_t xri;
2259 uint16_t wd30_class:4;
2260 uint16_t rsvd1:12;
2261 #endif
2262 } f;
2263 uint32_t word;
2264 } REG_WD30;
2265
2266 /* Structure for MB Command UNREG_LOGIN (20) */
2267
2268 typedef struct {
2269 #ifdef __BIG_ENDIAN_BITFIELD
2270 uint16_t rsvd1;
2271 uint16_t rpi;
2272 uint32_t rsvd2;
2273 uint32_t rsvd3;
2274 uint32_t rsvd4;
2275 uint32_t rsvd5;
2276 uint16_t rsvd6;
2277 uint16_t vpi;
2278 #else /* __LITTLE_ENDIAN_BITFIELD */
2279 uint16_t rpi;
2280 uint16_t rsvd1;
2281 uint32_t rsvd2;
2282 uint32_t rsvd3;
2283 uint32_t rsvd4;
2284 uint32_t rsvd5;
2285 uint16_t vpi;
2286 uint16_t rsvd6;
2287 #endif
2288 } UNREG_LOGIN_VAR;
2289
2290 /* Structure for MB Command REG_VPI (0x96) */
2291 typedef struct {
2292 #ifdef __BIG_ENDIAN_BITFIELD
2293 uint32_t rsvd1;
2294 uint32_t rsvd2:8;
2295 uint32_t sid:24;
2296 uint32_t wwn[2];
2297 uint32_t rsvd5;
2298 uint16_t vfi;
2299 uint16_t vpi;
2300 #else /* __LITTLE_ENDIAN */
2301 uint32_t rsvd1;
2302 uint32_t sid:24;
2303 uint32_t rsvd2:8;
2304 uint32_t wwn[2];
2305 uint32_t rsvd5;
2306 uint16_t vpi;
2307 uint16_t vfi;
2308 #endif
2309 } REG_VPI_VAR;
2310
2311 /* Structure for MB Command UNREG_VPI (0x97) */
2312 typedef struct {
2313 uint32_t rsvd1;
2314 #ifdef __BIG_ENDIAN_BITFIELD
2315 uint16_t rsvd2;
2316 uint16_t sli4_vpi;
2317 #else /* __LITTLE_ENDIAN */
2318 uint16_t sli4_vpi;
2319 uint16_t rsvd2;
2320 #endif
2321 uint32_t rsvd3;
2322 uint32_t rsvd4;
2323 uint32_t rsvd5;
2324 #ifdef __BIG_ENDIAN_BITFIELD
2325 uint16_t rsvd6;
2326 uint16_t vpi;
2327 #else /* __LITTLE_ENDIAN */
2328 uint16_t vpi;
2329 uint16_t rsvd6;
2330 #endif
2331 } UNREG_VPI_VAR;
2332
2333 /* Structure for MB Command UNREG_D_ID (0x23) */
2334
2335 typedef struct {
2336 uint32_t did;
2337 uint32_t rsvd2;
2338 uint32_t rsvd3;
2339 uint32_t rsvd4;
2340 uint32_t rsvd5;
2341 #ifdef __BIG_ENDIAN_BITFIELD
2342 uint16_t rsvd6;
2343 uint16_t vpi;
2344 #else
2345 uint16_t vpi;
2346 uint16_t rsvd6;
2347 #endif
2348 } UNREG_D_ID_VAR;
2349
2350 /* Structure for MB Command READ_LA (21) */
2351 /* Structure for MB Command READ_LA64 (0x95) */
2352
2353 typedef struct {
2354 uint32_t eventTag; /* Event tag */
2355 #ifdef __BIG_ENDIAN_BITFIELD
2356 uint32_t rsvd1:19;
2357 uint32_t fa:1;
2358 uint32_t mm:1; /* Menlo Maintenance mode enabled */
2359 uint32_t rx:1;
2360 uint32_t pb:1;
2361 uint32_t il:1;
2362 uint32_t attType:8;
2363 #else /* __LITTLE_ENDIAN_BITFIELD */
2364 uint32_t attType:8;
2365 uint32_t il:1;
2366 uint32_t pb:1;
2367 uint32_t rx:1;
2368 uint32_t mm:1;
2369 uint32_t fa:1;
2370 uint32_t rsvd1:19;
2371 #endif
2372
2373 #define AT_RESERVED 0x00 /* Reserved - attType */
2374 #define AT_LINK_UP 0x01 /* Link is up */
2375 #define AT_LINK_DOWN 0x02 /* Link is down */
2376
2377 #ifdef __BIG_ENDIAN_BITFIELD
2378 uint8_t granted_AL_PA;
2379 uint8_t lipAlPs;
2380 uint8_t lipType;
2381 uint8_t topology;
2382 #else /* __LITTLE_ENDIAN_BITFIELD */
2383 uint8_t topology;
2384 uint8_t lipType;
2385 uint8_t lipAlPs;
2386 uint8_t granted_AL_PA;
2387 #endif
2388
2389 #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2390 #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2391 #define TOPOLOGY_LNK_MENLO_MAINTENANCE 0x05 /* maint mode zephtr to menlo */
2392
2393 union {
2394 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer
2395 to */
2396 /* store the LILP AL_PA position map into */
2397 struct ulp_bde64 lilpBde64;
2398 } un;
2399
2400 #ifdef __BIG_ENDIAN_BITFIELD
2401 uint32_t Dlu:1;
2402 uint32_t Dtf:1;
2403 uint32_t Drsvd2:14;
2404 uint32_t DlnkSpeed:8;
2405 uint32_t DnlPort:4;
2406 uint32_t Dtx:2;
2407 uint32_t Drx:2;
2408 #else /* __LITTLE_ENDIAN_BITFIELD */
2409 uint32_t Drx:2;
2410 uint32_t Dtx:2;
2411 uint32_t DnlPort:4;
2412 uint32_t DlnkSpeed:8;
2413 uint32_t Drsvd2:14;
2414 uint32_t Dtf:1;
2415 uint32_t Dlu:1;
2416 #endif
2417
2418 #ifdef __BIG_ENDIAN_BITFIELD
2419 uint32_t Ulu:1;
2420 uint32_t Utf:1;
2421 uint32_t Ursvd2:14;
2422 uint32_t UlnkSpeed:8;
2423 uint32_t UnlPort:4;
2424 uint32_t Utx:2;
2425 uint32_t Urx:2;
2426 #else /* __LITTLE_ENDIAN_BITFIELD */
2427 uint32_t Urx:2;
2428 uint32_t Utx:2;
2429 uint32_t UnlPort:4;
2430 uint32_t UlnkSpeed:8;
2431 uint32_t Ursvd2:14;
2432 uint32_t Utf:1;
2433 uint32_t Ulu:1;
2434 #endif
2435
2436 #define LA_UNKNW_LINK 0x0 /* lnkSpeed */
2437 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */
2438 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */
2439 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */
2440 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */
2441 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */
2442
2443 } READ_LA_VAR;
2444
2445 /* Structure for MB Command CLEAR_LA (22) */
2446
2447 typedef struct {
2448 uint32_t eventTag; /* Event tag */
2449 uint32_t rsvd1;
2450 } CLEAR_LA_VAR;
2451
2452 /* Structure for MB Command DUMP */
2453
2454 typedef struct {
2455 #ifdef __BIG_ENDIAN_BITFIELD
2456 uint32_t rsvd:25;
2457 uint32_t ra:1;
2458 uint32_t co:1;
2459 uint32_t cv:1;
2460 uint32_t type:4;
2461 uint32_t entry_index:16;
2462 uint32_t region_id:16;
2463 #else /* __LITTLE_ENDIAN_BITFIELD */
2464 uint32_t type:4;
2465 uint32_t cv:1;
2466 uint32_t co:1;
2467 uint32_t ra:1;
2468 uint32_t rsvd:25;
2469 uint32_t region_id:16;
2470 uint32_t entry_index:16;
2471 #endif
2472
2473 uint32_t sli4_length;
2474 uint32_t word_cnt;
2475 uint32_t resp_offset;
2476 } DUMP_VAR;
2477
2478 #define DMP_MEM_REG 0x1
2479 #define DMP_NV_PARAMS 0x2
2480
2481 #define DMP_REGION_VPD 0xe
2482 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2483 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2484 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2485
2486 #define DMP_REGION_VPORT 0x16 /* VPort info region */
2487 #define DMP_VPORT_REGION_SIZE 0x200
2488 #define DMP_MBOX_OFFSET_WORD 0x5
2489
2490 #define DMP_REGION_23 0x17 /* fcoe param and port state region */
2491 #define DMP_RGN23_SIZE 0x400
2492
2493 #define WAKE_UP_PARMS_REGION_ID 4
2494 #define WAKE_UP_PARMS_WORD_SIZE 15
2495
2496 struct vport_rec {
2497 uint8_t wwpn[8];
2498 uint8_t wwnn[8];
2499 };
2500
2501 #define VPORT_INFO_SIG 0x32324752
2502 #define VPORT_INFO_REV_MASK 0xff
2503 #define VPORT_INFO_REV 0x1
2504 #define MAX_STATIC_VPORT_COUNT 16
2505 struct static_vport_info {
2506 uint32_t signature;
2507 uint32_t rev;
2508 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
2509 uint32_t resvd[66];
2510 };
2511
2512 /* Option rom version structure */
2513 struct prog_id {
2514 #ifdef __BIG_ENDIAN_BITFIELD
2515 uint8_t type;
2516 uint8_t id;
2517 uint32_t ver:4; /* Major Version */
2518 uint32_t rev:4; /* Revision */
2519 uint32_t lev:2; /* Level */
2520 uint32_t dist:2; /* Dist Type */
2521 uint32_t num:4; /* number after dist type */
2522 #else /* __LITTLE_ENDIAN_BITFIELD */
2523 uint32_t num:4; /* number after dist type */
2524 uint32_t dist:2; /* Dist Type */
2525 uint32_t lev:2; /* Level */
2526 uint32_t rev:4; /* Revision */
2527 uint32_t ver:4; /* Major Version */
2528 uint8_t id;
2529 uint8_t type;
2530 #endif
2531 };
2532
2533 /* Structure for MB Command UPDATE_CFG (0x1B) */
2534
2535 struct update_cfg_var {
2536 #ifdef __BIG_ENDIAN_BITFIELD
2537 uint32_t rsvd2:16;
2538 uint32_t type:8;
2539 uint32_t rsvd:1;
2540 uint32_t ra:1;
2541 uint32_t co:1;
2542 uint32_t cv:1;
2543 uint32_t req:4;
2544 uint32_t entry_length:16;
2545 uint32_t region_id:16;
2546 #else /* __LITTLE_ENDIAN_BITFIELD */
2547 uint32_t req:4;
2548 uint32_t cv:1;
2549 uint32_t co:1;
2550 uint32_t ra:1;
2551 uint32_t rsvd:1;
2552 uint32_t type:8;
2553 uint32_t rsvd2:16;
2554 uint32_t region_id:16;
2555 uint32_t entry_length:16;
2556 #endif
2557
2558 uint32_t resp_info;
2559 uint32_t byte_cnt;
2560 uint32_t data_offset;
2561 };
2562
2563 struct hbq_mask {
2564 #ifdef __BIG_ENDIAN_BITFIELD
2565 uint8_t tmatch;
2566 uint8_t tmask;
2567 uint8_t rctlmatch;
2568 uint8_t rctlmask;
2569 #else /* __LITTLE_ENDIAN */
2570 uint8_t rctlmask;
2571 uint8_t rctlmatch;
2572 uint8_t tmask;
2573 uint8_t tmatch;
2574 #endif
2575 };
2576
2577
2578 /* Structure for MB Command CONFIG_HBQ (7c) */
2579
2580 struct config_hbq_var {
2581 #ifdef __BIG_ENDIAN_BITFIELD
2582 uint32_t rsvd1 :7;
2583 uint32_t recvNotify :1; /* Receive Notification */
2584 uint32_t numMask :8; /* # Mask Entries */
2585 uint32_t profile :8; /* Selection Profile */
2586 uint32_t rsvd2 :8;
2587 #else /* __LITTLE_ENDIAN */
2588 uint32_t rsvd2 :8;
2589 uint32_t profile :8; /* Selection Profile */
2590 uint32_t numMask :8; /* # Mask Entries */
2591 uint32_t recvNotify :1; /* Receive Notification */
2592 uint32_t rsvd1 :7;
2593 #endif
2594
2595 #ifdef __BIG_ENDIAN_BITFIELD
2596 uint32_t hbqId :16;
2597 uint32_t rsvd3 :12;
2598 uint32_t ringMask :4;
2599 #else /* __LITTLE_ENDIAN */
2600 uint32_t ringMask :4;
2601 uint32_t rsvd3 :12;
2602 uint32_t hbqId :16;
2603 #endif
2604
2605 #ifdef __BIG_ENDIAN_BITFIELD
2606 uint32_t entry_count :16;
2607 uint32_t rsvd4 :8;
2608 uint32_t headerLen :8;
2609 #else /* __LITTLE_ENDIAN */
2610 uint32_t headerLen :8;
2611 uint32_t rsvd4 :8;
2612 uint32_t entry_count :16;
2613 #endif
2614
2615 uint32_t hbqaddrLow;
2616 uint32_t hbqaddrHigh;
2617
2618 #ifdef __BIG_ENDIAN_BITFIELD
2619 uint32_t rsvd5 :31;
2620 uint32_t logEntry :1;
2621 #else /* __LITTLE_ENDIAN */
2622 uint32_t logEntry :1;
2623 uint32_t rsvd5 :31;
2624 #endif
2625
2626 uint32_t rsvd6; /* w7 */
2627 uint32_t rsvd7; /* w8 */
2628 uint32_t rsvd8; /* w9 */
2629
2630 struct hbq_mask hbqMasks[6];
2631
2632
2633 union {
2634 uint32_t allprofiles[12];
2635
2636 struct {
2637 #ifdef __BIG_ENDIAN_BITFIELD
2638 uint32_t seqlenoff :16;
2639 uint32_t maxlen :16;
2640 #else /* __LITTLE_ENDIAN */
2641 uint32_t maxlen :16;
2642 uint32_t seqlenoff :16;
2643 #endif
2644 #ifdef __BIG_ENDIAN_BITFIELD
2645 uint32_t rsvd1 :28;
2646 uint32_t seqlenbcnt :4;
2647 #else /* __LITTLE_ENDIAN */
2648 uint32_t seqlenbcnt :4;
2649 uint32_t rsvd1 :28;
2650 #endif
2651 uint32_t rsvd[10];
2652 } profile2;
2653
2654 struct {
2655 #ifdef __BIG_ENDIAN_BITFIELD
2656 uint32_t seqlenoff :16;
2657 uint32_t maxlen :16;
2658 #else /* __LITTLE_ENDIAN */
2659 uint32_t maxlen :16;
2660 uint32_t seqlenoff :16;
2661 #endif
2662 #ifdef __BIG_ENDIAN_BITFIELD
2663 uint32_t cmdcodeoff :28;
2664 uint32_t rsvd1 :12;
2665 uint32_t seqlenbcnt :4;
2666 #else /* __LITTLE_ENDIAN */
2667 uint32_t seqlenbcnt :4;
2668 uint32_t rsvd1 :12;
2669 uint32_t cmdcodeoff :28;
2670 #endif
2671 uint32_t cmdmatch[8];
2672
2673 uint32_t rsvd[2];
2674 } profile3;
2675
2676 struct {
2677 #ifdef __BIG_ENDIAN_BITFIELD
2678 uint32_t seqlenoff :16;
2679 uint32_t maxlen :16;
2680 #else /* __LITTLE_ENDIAN */
2681 uint32_t maxlen :16;
2682 uint32_t seqlenoff :16;
2683 #endif
2684 #ifdef __BIG_ENDIAN_BITFIELD
2685 uint32_t cmdcodeoff :28;
2686 uint32_t rsvd1 :12;
2687 uint32_t seqlenbcnt :4;
2688 #else /* __LITTLE_ENDIAN */
2689 uint32_t seqlenbcnt :4;
2690 uint32_t rsvd1 :12;
2691 uint32_t cmdcodeoff :28;
2692 #endif
2693 uint32_t cmdmatch[8];
2694
2695 uint32_t rsvd[2];
2696 } profile5;
2697
2698 } profiles;
2699
2700 };
2701
2702
2703
2704 /* Structure for MB Command CONFIG_PORT (0x88) */
2705 typedef struct {
2706 #ifdef __BIG_ENDIAN_BITFIELD
2707 uint32_t cBE : 1;
2708 uint32_t cET : 1;
2709 uint32_t cHpcb : 1;
2710 uint32_t cMA : 1;
2711 uint32_t sli_mode : 4;
2712 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2713 * config block */
2714 #else /* __LITTLE_ENDIAN */
2715 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2716 * config block */
2717 uint32_t sli_mode : 4;
2718 uint32_t cMA : 1;
2719 uint32_t cHpcb : 1;
2720 uint32_t cET : 1;
2721 uint32_t cBE : 1;
2722 #endif
2723
2724 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
2725 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
2726 uint32_t hbainit[5];
2727 #ifdef __BIG_ENDIAN_BITFIELD
2728 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
2729 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
2730 #else /* __LITTLE_ENDIAN */
2731 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
2732 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
2733 #endif
2734
2735 #ifdef __BIG_ENDIAN_BITFIELD
2736 uint32_t rsvd1 : 19; /* Reserved */
2737 uint32_t cdss : 1; /* Configure Data Security SLI */
2738 uint32_t rsvd2 : 3; /* Reserved */
2739 uint32_t cbg : 1; /* Configure BlockGuard */
2740 uint32_t cmv : 1; /* Configure Max VPIs */
2741 uint32_t ccrp : 1; /* Config Command Ring Polling */
2742 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2743 uint32_t chbs : 1; /* Cofigure Host Backing store */
2744 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2745 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2746 uint32_t cmx : 1; /* Configure Max XRIs */
2747 uint32_t cmr : 1; /* Configure Max RPIs */
2748 #else /* __LITTLE_ENDIAN */
2749 uint32_t cmr : 1; /* Configure Max RPIs */
2750 uint32_t cmx : 1; /* Configure Max XRIs */
2751 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2752 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2753 uint32_t chbs : 1; /* Cofigure Host Backing store */
2754 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2755 uint32_t ccrp : 1; /* Config Command Ring Polling */
2756 uint32_t cmv : 1; /* Configure Max VPIs */
2757 uint32_t cbg : 1; /* Configure BlockGuard */
2758 uint32_t rsvd2 : 3; /* Reserved */
2759 uint32_t cdss : 1; /* Configure Data Security SLI */
2760 uint32_t rsvd1 : 19; /* Reserved */
2761 #endif
2762 #ifdef __BIG_ENDIAN_BITFIELD
2763 uint32_t rsvd3 : 19; /* Reserved */
2764 uint32_t gdss : 1; /* Configure Data Security SLI */
2765 uint32_t rsvd4 : 3; /* Reserved */
2766 uint32_t gbg : 1; /* Grant BlockGuard */
2767 uint32_t gmv : 1; /* Grant Max VPIs */
2768 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2769 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2770 uint32_t ghbs : 1; /* Grant Host Backing Store */
2771 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2772 uint32_t gerbm : 1; /* Grant ERBM Request */
2773 uint32_t gmx : 1; /* Grant Max XRIs */
2774 uint32_t gmr : 1; /* Grant Max RPIs */
2775 #else /* __LITTLE_ENDIAN */
2776 uint32_t gmr : 1; /* Grant Max RPIs */
2777 uint32_t gmx : 1; /* Grant Max XRIs */
2778 uint32_t gerbm : 1; /* Grant ERBM Request */
2779 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2780 uint32_t ghbs : 1; /* Grant Host Backing Store */
2781 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2782 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2783 uint32_t gmv : 1; /* Grant Max VPIs */
2784 uint32_t gbg : 1; /* Grant BlockGuard */
2785 uint32_t rsvd4 : 3; /* Reserved */
2786 uint32_t gdss : 1; /* Configure Data Security SLI */
2787 uint32_t rsvd3 : 19; /* Reserved */
2788 #endif
2789
2790 #ifdef __BIG_ENDIAN_BITFIELD
2791 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2792 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2793 #else /* __LITTLE_ENDIAN */
2794 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2795 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2796 #endif
2797
2798 #ifdef __BIG_ENDIAN_BITFIELD
2799 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2800 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
2801 #else /* __LITTLE_ENDIAN */
2802 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
2803 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2804 #endif
2805
2806 uint32_t rsvd6; /* Reserved */
2807
2808 #ifdef __BIG_ENDIAN_BITFIELD
2809 uint32_t rsvd7 : 16; /* Reserved */
2810 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2811 #else /* __LITTLE_ENDIAN */
2812 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2813 uint32_t rsvd7 : 16; /* Reserved */
2814 #endif
2815
2816 } CONFIG_PORT_VAR;
2817
2818 /* Structure for MB Command CONFIG_MSI (0x30) */
2819 struct config_msi_var {
2820 #ifdef __BIG_ENDIAN_BITFIELD
2821 uint32_t dfltMsgNum:8; /* Default message number */
2822 uint32_t rsvd1:11; /* Reserved */
2823 uint32_t NID:5; /* Number of secondary attention IDs */
2824 uint32_t rsvd2:5; /* Reserved */
2825 uint32_t dfltPresent:1; /* Default message number present */
2826 uint32_t addFlag:1; /* Add association flag */
2827 uint32_t reportFlag:1; /* Report association flag */
2828 #else /* __LITTLE_ENDIAN_BITFIELD */
2829 uint32_t reportFlag:1; /* Report association flag */
2830 uint32_t addFlag:1; /* Add association flag */
2831 uint32_t dfltPresent:1; /* Default message number present */
2832 uint32_t rsvd2:5; /* Reserved */
2833 uint32_t NID:5; /* Number of secondary attention IDs */
2834 uint32_t rsvd1:11; /* Reserved */
2835 uint32_t dfltMsgNum:8; /* Default message number */
2836 #endif
2837 uint32_t attentionConditions[2];
2838 uint8_t attentionId[16];
2839 uint8_t messageNumberByHA[64];
2840 uint8_t messageNumberByID[16];
2841 uint32_t autoClearHA[2];
2842 #ifdef __BIG_ENDIAN_BITFIELD
2843 uint32_t rsvd3:16;
2844 uint32_t autoClearID:16;
2845 #else /* __LITTLE_ENDIAN_BITFIELD */
2846 uint32_t autoClearID:16;
2847 uint32_t rsvd3:16;
2848 #endif
2849 uint32_t rsvd4;
2850 };
2851
2852 /* SLI-2 Port Control Block */
2853
2854 /* SLIM POINTER */
2855 #define SLIMOFF 0x30 /* WORD */
2856
2857 typedef struct _SLI2_RDSC {
2858 uint32_t cmdEntries;
2859 uint32_t cmdAddrLow;
2860 uint32_t cmdAddrHigh;
2861
2862 uint32_t rspEntries;
2863 uint32_t rspAddrLow;
2864 uint32_t rspAddrHigh;
2865 } SLI2_RDSC;
2866
2867 typedef struct _PCB {
2868 #ifdef __BIG_ENDIAN_BITFIELD
2869 uint32_t type:8;
2870 #define TYPE_NATIVE_SLI2 0x01;
2871 uint32_t feature:8;
2872 #define FEATURE_INITIAL_SLI2 0x01;
2873 uint32_t rsvd:12;
2874 uint32_t maxRing:4;
2875 #else /* __LITTLE_ENDIAN_BITFIELD */
2876 uint32_t maxRing:4;
2877 uint32_t rsvd:12;
2878 uint32_t feature:8;
2879 #define FEATURE_INITIAL_SLI2 0x01;
2880 uint32_t type:8;
2881 #define TYPE_NATIVE_SLI2 0x01;
2882 #endif
2883
2884 uint32_t mailBoxSize;
2885 uint32_t mbAddrLow;
2886 uint32_t mbAddrHigh;
2887
2888 uint32_t hgpAddrLow;
2889 uint32_t hgpAddrHigh;
2890
2891 uint32_t pgpAddrLow;
2892 uint32_t pgpAddrHigh;
2893 SLI2_RDSC rdsc[MAX_RINGS];
2894 } PCB_t;
2895
2896 /* NEW_FEATURE */
2897 typedef struct {
2898 #ifdef __BIG_ENDIAN_BITFIELD
2899 uint32_t rsvd0:27;
2900 uint32_t discardFarp:1;
2901 uint32_t IPEnable:1;
2902 uint32_t nodeName:1;
2903 uint32_t portName:1;
2904 uint32_t filterEnable:1;
2905 #else /* __LITTLE_ENDIAN_BITFIELD */
2906 uint32_t filterEnable:1;
2907 uint32_t portName:1;
2908 uint32_t nodeName:1;
2909 uint32_t IPEnable:1;
2910 uint32_t discardFarp:1;
2911 uint32_t rsvd:27;
2912 #endif
2913
2914 uint8_t portname[8]; /* Used to be struct lpfc_name */
2915 uint8_t nodename[8];
2916 uint32_t rsvd1;
2917 uint32_t rsvd2;
2918 uint32_t rsvd3;
2919 uint32_t IPAddress;
2920 } CONFIG_FARP_VAR;
2921
2922 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
2923
2924 typedef struct {
2925 #ifdef __BIG_ENDIAN_BITFIELD
2926 uint32_t rsvd:30;
2927 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
2928 #else /* __LITTLE_ENDIAN */
2929 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
2930 uint32_t rsvd:30;
2931 #endif
2932 } ASYNCEVT_ENABLE_VAR;
2933
2934 /* Union of all Mailbox Command types */
2935 #define MAILBOX_CMD_WSIZE 32
2936 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
2937 /* ext_wsize times 4 bytes should not be greater than max xmit size */
2938 #define MAILBOX_EXT_WSIZE 512
2939 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
2940 #define MAILBOX_HBA_EXT_OFFSET 0x100
2941 /* max mbox xmit size is a page size for sysfs IO operations */
2942 #define MAILBOX_MAX_XMIT_SIZE PAGE_SIZE
2943
2944 typedef union {
2945 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
2946 * feature/max ring number
2947 */
2948 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
2949 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
2950 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
2951 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
2952 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
2953 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
2954 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
2955 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
2956 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
2957 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
2958 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
2959 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
2960 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
2961 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
2962 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
2963 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
2964 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
2965 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
2966 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
2967 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
2968 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */
2969 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
2970 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
2971 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
2972 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
2973 * NEW_FEATURE
2974 */
2975 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
2976 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
2977 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
2978 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
2979 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
2980 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
2981 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
2982 * (READ_EVENT_LOG)
2983 */
2984 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
2985 } MAILVARIANTS;
2986
2987 /*
2988 * SLI-2 specific structures
2989 */
2990
2991 struct lpfc_hgp {
2992 __le32 cmdPutInx;
2993 __le32 rspGetInx;
2994 };
2995
2996 struct lpfc_pgp {
2997 __le32 cmdGetInx;
2998 __le32 rspPutInx;
2999 };
3000
3001 struct sli2_desc {
3002 uint32_t unused1[16];
3003 struct lpfc_hgp host[MAX_RINGS];
3004 struct lpfc_pgp port[MAX_RINGS];
3005 };
3006
3007 struct sli3_desc {
3008 struct lpfc_hgp host[MAX_RINGS];
3009 uint32_t reserved[8];
3010 uint32_t hbq_put[16];
3011 };
3012
3013 struct sli3_pgp {
3014 struct lpfc_pgp port[MAX_RINGS];
3015 uint32_t hbq_get[16];
3016 };
3017
3018 union sli_var {
3019 struct sli2_desc s2;
3020 struct sli3_desc s3;
3021 struct sli3_pgp s3_pgp;
3022 };
3023
3024 typedef struct {
3025 #ifdef __BIG_ENDIAN_BITFIELD
3026 uint16_t mbxStatus;
3027 uint8_t mbxCommand;
3028 uint8_t mbxReserved:6;
3029 uint8_t mbxHc:1;
3030 uint8_t mbxOwner:1; /* Low order bit first word */
3031 #else /* __LITTLE_ENDIAN_BITFIELD */
3032 uint8_t mbxOwner:1; /* Low order bit first word */
3033 uint8_t mbxHc:1;
3034 uint8_t mbxReserved:6;
3035 uint8_t mbxCommand;
3036 uint16_t mbxStatus;
3037 #endif
3038
3039 MAILVARIANTS un;
3040 union sli_var us;
3041 } MAILBOX_t;
3042
3043 /*
3044 * Begin Structure Definitions for IOCB Commands
3045 */
3046
3047 typedef struct {
3048 #ifdef __BIG_ENDIAN_BITFIELD
3049 uint8_t statAction;
3050 uint8_t statRsn;
3051 uint8_t statBaExp;
3052 uint8_t statLocalError;
3053 #else /* __LITTLE_ENDIAN_BITFIELD */
3054 uint8_t statLocalError;
3055 uint8_t statBaExp;
3056 uint8_t statRsn;
3057 uint8_t statAction;
3058 #endif
3059 /* statRsn P/F_RJT reason codes */
3060 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3061 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3062 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3063 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3064 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3065 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3066 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3067 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3068 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3069 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3070 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3071 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3072 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3073 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3074 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3075 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
3076 #define RJT_XCHG_ERR 0x11 /* Exchange error */
3077 #define RJT_PROT_ERR 0x12 /* Protocol error */
3078 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3079 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3080 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3081 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3082 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3083 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3084 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3085 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3086
3087 #define IOERR_SUCCESS 0x00 /* statLocalError */
3088 #define IOERR_MISSING_CONTINUE 0x01
3089 #define IOERR_SEQUENCE_TIMEOUT 0x02
3090 #define IOERR_INTERNAL_ERROR 0x03
3091 #define IOERR_INVALID_RPI 0x04
3092 #define IOERR_NO_XRI 0x05
3093 #define IOERR_ILLEGAL_COMMAND 0x06
3094 #define IOERR_XCHG_DROPPED 0x07
3095 #define IOERR_ILLEGAL_FIELD 0x08
3096 #define IOERR_BAD_CONTINUE 0x09
3097 #define IOERR_TOO_MANY_BUFFERS 0x0A
3098 #define IOERR_RCV_BUFFER_WAITING 0x0B
3099 #define IOERR_NO_CONNECTION 0x0C
3100 #define IOERR_TX_DMA_FAILED 0x0D
3101 #define IOERR_RX_DMA_FAILED 0x0E
3102 #define IOERR_ILLEGAL_FRAME 0x0F
3103 #define IOERR_EXTRA_DATA 0x10
3104 #define IOERR_NO_RESOURCES 0x11
3105 #define IOERR_RESERVED 0x12
3106 #define IOERR_ILLEGAL_LENGTH 0x13
3107 #define IOERR_UNSUPPORTED_FEATURE 0x14
3108 #define IOERR_ABORT_IN_PROGRESS 0x15
3109 #define IOERR_ABORT_REQUESTED 0x16
3110 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3111 #define IOERR_LOOP_OPEN_FAILURE 0x18
3112 #define IOERR_RING_RESET 0x19
3113 #define IOERR_LINK_DOWN 0x1A
3114 #define IOERR_CORRUPTED_DATA 0x1B
3115 #define IOERR_CORRUPTED_RPI 0x1C
3116 #define IOERR_OUT_OF_ORDER_DATA 0x1D
3117 #define IOERR_OUT_OF_ORDER_ACK 0x1E
3118 #define IOERR_DUP_FRAME 0x1F
3119 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3120 #define IOERR_BAD_HOST_ADDRESS 0x21
3121 #define IOERR_RCV_HDRBUF_WAITING 0x22
3122 #define IOERR_MISSING_HDR_BUFFER 0x23
3123 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3124 #define IOERR_ABORTMULT_REQUESTED 0x25
3125 #define IOERR_BUFFER_SHORTAGE 0x28
3126 #define IOERR_DEFAULT 0x29
3127 #define IOERR_CNT 0x2A
3128 #define IOERR_SLER_FAILURE 0x46
3129 #define IOERR_SLER_CMD_RCV_FAILURE 0x47
3130 #define IOERR_SLER_REC_RJT_ERR 0x48
3131 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3132 #define IOERR_SLER_SRR_RJT_ERR 0x4A
3133 #define IOERR_SLER_RRQ_RJT_ERR 0x4C
3134 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3135 #define IOERR_SLER_ABTS_ERR 0x4E
3136
3137 #define IOERR_DRVR_MASK 0x100
3138 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3139 #define IOERR_SLI_BRESET 0x102
3140 #define IOERR_SLI_ABORTED 0x103
3141 } PARM_ERR;
3142
3143 typedef union {
3144 struct {
3145 #ifdef __BIG_ENDIAN_BITFIELD
3146 uint8_t Rctl; /* R_CTL field */
3147 uint8_t Type; /* TYPE field */
3148 uint8_t Dfctl; /* DF_CTL field */
3149 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3150 #else /* __LITTLE_ENDIAN_BITFIELD */
3151 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3152 uint8_t Dfctl; /* DF_CTL field */
3153 uint8_t Type; /* TYPE field */
3154 uint8_t Rctl; /* R_CTL field */
3155 #endif
3156
3157 #define BC 0x02 /* Broadcast Received - Fctl */
3158 #define SI 0x04 /* Sequence Initiative */
3159 #define LA 0x08 /* Ignore Link Attention state */
3160 #define LS 0x80 /* Last Sequence */
3161 } hcsw;
3162 uint32_t reserved;
3163 } WORD5;
3164
3165 /* IOCB Command template for a generic response */
3166 typedef struct {
3167 uint32_t reserved[4];
3168 PARM_ERR perr;
3169 } GENERIC_RSP;
3170
3171 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3172 typedef struct {
3173 struct ulp_bde xrsqbde[2];
3174 uint32_t xrsqRo; /* Starting Relative Offset */
3175 WORD5 w5; /* Header control/status word */
3176 } XR_SEQ_FIELDS;
3177
3178 /* IOCB Command template for ELS_REQUEST */
3179 typedef struct {
3180 struct ulp_bde elsReq;
3181 struct ulp_bde elsRsp;
3182
3183 #ifdef __BIG_ENDIAN_BITFIELD
3184 uint32_t word4Rsvd:7;
3185 uint32_t fl:1;
3186 uint32_t myID:24;
3187 uint32_t word5Rsvd:8;
3188 uint32_t remoteID:24;
3189 #else /* __LITTLE_ENDIAN_BITFIELD */
3190 uint32_t myID:24;
3191 uint32_t fl:1;
3192 uint32_t word4Rsvd:7;
3193 uint32_t remoteID:24;
3194 uint32_t word5Rsvd:8;
3195 #endif
3196 } ELS_REQUEST;
3197
3198 /* IOCB Command template for RCV_ELS_REQ */
3199 typedef struct {
3200 struct ulp_bde elsReq[2];
3201 uint32_t parmRo;
3202
3203 #ifdef __BIG_ENDIAN_BITFIELD
3204 uint32_t word5Rsvd:8;
3205 uint32_t remoteID:24;
3206 #else /* __LITTLE_ENDIAN_BITFIELD */
3207 uint32_t remoteID:24;
3208 uint32_t word5Rsvd:8;
3209 #endif
3210 } RCV_ELS_REQ;
3211
3212 /* IOCB Command template for ABORT / CLOSE_XRI */
3213 typedef struct {
3214 uint32_t rsvd[3];
3215 uint32_t abortType;
3216 #define ABORT_TYPE_ABTX 0x00000000
3217 #define ABORT_TYPE_ABTS 0x00000001
3218 uint32_t parm;
3219 #ifdef __BIG_ENDIAN_BITFIELD
3220 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3221 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3222 #else /* __LITTLE_ENDIAN_BITFIELD */
3223 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3224 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3225 #endif
3226 } AC_XRI;
3227
3228 /* IOCB Command template for ABORT_MXRI64 */
3229 typedef struct {
3230 uint32_t rsvd[3];
3231 uint32_t abortType;
3232 uint32_t parm;
3233 uint32_t iotag32;
3234 } A_MXRI64;
3235
3236 /* IOCB Command template for GET_RPI */
3237 typedef struct {
3238 uint32_t rsvd[4];
3239 uint32_t parmRo;
3240 #ifdef __BIG_ENDIAN_BITFIELD
3241 uint32_t word5Rsvd:8;
3242 uint32_t remoteID:24;
3243 #else /* __LITTLE_ENDIAN_BITFIELD */
3244 uint32_t remoteID:24;
3245 uint32_t word5Rsvd:8;
3246 #endif
3247 } GET_RPI;
3248
3249 /* IOCB Command template for all FCP Initiator commands */
3250 typedef struct {
3251 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
3252 struct ulp_bde fcpi_rsp; /* Rcv buffer */
3253 uint32_t fcpi_parm;
3254 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3255 } FCPI_FIELDS;
3256
3257 /* IOCB Command template for all FCP Target commands */
3258 typedef struct {
3259 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
3260 uint32_t fcpt_Offset;
3261 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3262 } FCPT_FIELDS;
3263
3264 /* SLI-2 IOCB structure definitions */
3265
3266 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3267 typedef struct {
3268 ULP_BDL bdl;
3269 uint32_t xrsqRo; /* Starting Relative Offset */
3270 WORD5 w5; /* Header control/status word */
3271 } XMT_SEQ_FIELDS64;
3272
3273 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3274 typedef struct {
3275 struct ulp_bde64 rcvBde;
3276 uint32_t rsvd1;
3277 uint32_t xrsqRo; /* Starting Relative Offset */
3278 WORD5 w5; /* Header control/status word */
3279 } RCV_SEQ_FIELDS64;
3280
3281 /* IOCB Command template for ELS_REQUEST64 */
3282 typedef struct {
3283 ULP_BDL bdl;
3284 #ifdef __BIG_ENDIAN_BITFIELD
3285 uint32_t word4Rsvd:7;
3286 uint32_t fl:1;
3287 uint32_t myID:24;
3288 uint32_t word5Rsvd:8;
3289 uint32_t remoteID:24;
3290 #else /* __LITTLE_ENDIAN_BITFIELD */
3291 uint32_t myID:24;
3292 uint32_t fl:1;
3293 uint32_t word4Rsvd:7;
3294 uint32_t remoteID:24;
3295 uint32_t word5Rsvd:8;
3296 #endif
3297 } ELS_REQUEST64;
3298
3299 /* IOCB Command template for GEN_REQUEST64 */
3300 typedef struct {
3301 ULP_BDL bdl;
3302 uint32_t xrsqRo; /* Starting Relative Offset */
3303 WORD5 w5; /* Header control/status word */
3304 } GEN_REQUEST64;
3305
3306 /* IOCB Command template for RCV_ELS_REQ64 */
3307 typedef struct {
3308 struct ulp_bde64 elsReq;
3309 uint32_t rcvd1;
3310 uint32_t parmRo;
3311
3312 #ifdef __BIG_ENDIAN_BITFIELD
3313 uint32_t word5Rsvd:8;
3314 uint32_t remoteID:24;
3315 #else /* __LITTLE_ENDIAN_BITFIELD */
3316 uint32_t remoteID:24;
3317 uint32_t word5Rsvd:8;
3318 #endif
3319 } RCV_ELS_REQ64;
3320
3321 /* IOCB Command template for RCV_SEQ64 */
3322 struct rcv_seq64 {
3323 struct ulp_bde64 elsReq;
3324 uint32_t hbq_1;
3325 uint32_t parmRo;
3326 #ifdef __BIG_ENDIAN_BITFIELD
3327 uint32_t rctl:8;
3328 uint32_t type:8;
3329 uint32_t dfctl:8;
3330 uint32_t ls:1;
3331 uint32_t fs:1;
3332 uint32_t rsvd2:3;
3333 uint32_t si:1;
3334 uint32_t bc:1;
3335 uint32_t rsvd3:1;
3336 #else /* __LITTLE_ENDIAN_BITFIELD */
3337 uint32_t rsvd3:1;
3338 uint32_t bc:1;
3339 uint32_t si:1;
3340 uint32_t rsvd2:3;
3341 uint32_t fs:1;
3342 uint32_t ls:1;
3343 uint32_t dfctl:8;
3344 uint32_t type:8;
3345 uint32_t rctl:8;
3346 #endif
3347 };
3348
3349 /* IOCB Command template for all 64 bit FCP Initiator commands */
3350 typedef struct {
3351 ULP_BDL bdl;
3352 uint32_t fcpi_parm;
3353 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3354 } FCPI_FIELDS64;
3355
3356 /* IOCB Command template for all 64 bit FCP Target commands */
3357 typedef struct {
3358 ULP_BDL bdl;
3359 uint32_t fcpt_Offset;
3360 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3361 } FCPT_FIELDS64;
3362
3363 /* IOCB Command template for Async Status iocb commands */
3364 typedef struct {
3365 uint32_t rsvd[4];
3366 uint32_t param;
3367 #ifdef __BIG_ENDIAN_BITFIELD
3368 uint16_t evt_code; /* High order bits word 5 */
3369 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
3370 #else /* __LITTLE_ENDIAN_BITFIELD */
3371 uint16_t sub_ctxt_tag; /* High order bits word 5 */
3372 uint16_t evt_code; /* Low order bits word 5 */
3373 #endif
3374 } ASYNCSTAT_FIELDS;
3375 #define ASYNC_TEMP_WARN 0x100
3376 #define ASYNC_TEMP_SAFE 0x101
3377
3378 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3379 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3380
3381 struct rcv_sli3 {
3382 uint32_t word8Rsvd;
3383 #ifdef __BIG_ENDIAN_BITFIELD
3384 uint16_t vpi;
3385 uint16_t word9Rsvd;
3386 #else /* __LITTLE_ENDIAN */
3387 uint16_t word9Rsvd;
3388 uint16_t vpi;
3389 #endif
3390 uint32_t word10Rsvd;
3391 uint32_t acc_len; /* accumulated length */
3392 struct ulp_bde64 bde2;
3393 };
3394
3395 /* Structure used for a single HBQ entry */
3396 struct lpfc_hbq_entry {
3397 struct ulp_bde64 bde;
3398 uint32_t buffer_tag;
3399 };
3400
3401 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3402 typedef struct {
3403 struct lpfc_hbq_entry buff;
3404 uint32_t rsvd;
3405 uint32_t rsvd1;
3406 } QUE_XRI64_CX_FIELDS;
3407
3408 struct que_xri64cx_ext_fields {
3409 uint32_t iotag64_low;
3410 uint32_t iotag64_high;
3411 uint32_t ebde_count;
3412 uint32_t rsvd;
3413 struct lpfc_hbq_entry buff[5];
3414 };
3415
3416 struct sli3_bg_fields {
3417 uint32_t filler[6]; /* word 8-13 in IOCB */
3418 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
3419 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3420 #define BGS_BIDIR_BG_PROF_MASK 0xff000000
3421 #define BGS_BIDIR_BG_PROF_SHIFT 24
3422 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
3423 #define BGS_BIDIR_ERR_COND_SHIFT 16
3424 #define BGS_BG_PROFILE_MASK 0x0000ff00
3425 #define BGS_BG_PROFILE_SHIFT 8
3426 #define BGS_INVALID_PROF_MASK 0x00000020
3427 #define BGS_INVALID_PROF_SHIFT 5
3428 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
3429 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4
3430 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
3431 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
3432 #define BGS_REFTAG_ERR_MASK 0x00000004
3433 #define BGS_REFTAG_ERR_SHIFT 2
3434 #define BGS_APPTAG_ERR_MASK 0x00000002
3435 #define BGS_APPTAG_ERR_SHIFT 1
3436 #define BGS_GUARD_ERR_MASK 0x00000001
3437 #define BGS_GUARD_ERR_SHIFT 0
3438 uint32_t bgstat; /* word 15 - BlockGuard Status */
3439 };
3440
3441 static inline uint32_t
3442 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
3443 {
3444 return (le32_to_cpu(bgstat) & BGS_BIDIR_BG_PROF_MASK) >>
3445 BGS_BIDIR_BG_PROF_SHIFT;
3446 }
3447
3448 static inline uint32_t
3449 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
3450 {
3451 return (le32_to_cpu(bgstat) & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
3452 BGS_BIDIR_ERR_COND_SHIFT;
3453 }
3454
3455 static inline uint32_t
3456 lpfc_bgs_get_bg_prof(uint32_t bgstat)
3457 {
3458 return (le32_to_cpu(bgstat) & BGS_BG_PROFILE_MASK) >>
3459 BGS_BG_PROFILE_SHIFT;
3460 }
3461
3462 static inline uint32_t
3463 lpfc_bgs_get_invalid_prof(uint32_t bgstat)
3464 {
3465 return (le32_to_cpu(bgstat) & BGS_INVALID_PROF_MASK) >>
3466 BGS_INVALID_PROF_SHIFT;
3467 }
3468
3469 static inline uint32_t
3470 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
3471 {
3472 return (le32_to_cpu(bgstat) & BGS_UNINIT_DIF_BLOCK_MASK) >>
3473 BGS_UNINIT_DIF_BLOCK_SHIFT;
3474 }
3475
3476 static inline uint32_t
3477 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
3478 {
3479 return (le32_to_cpu(bgstat) & BGS_HI_WATER_MARK_PRESENT_MASK) >>
3480 BGS_HI_WATER_MARK_PRESENT_SHIFT;
3481 }
3482
3483 static inline uint32_t
3484 lpfc_bgs_get_reftag_err(uint32_t bgstat)
3485 {
3486 return (le32_to_cpu(bgstat) & BGS_REFTAG_ERR_MASK) >>
3487 BGS_REFTAG_ERR_SHIFT;
3488 }
3489
3490 static inline uint32_t
3491 lpfc_bgs_get_apptag_err(uint32_t bgstat)
3492 {
3493 return (le32_to_cpu(bgstat) & BGS_APPTAG_ERR_MASK) >>
3494 BGS_APPTAG_ERR_SHIFT;
3495 }
3496
3497 static inline uint32_t
3498 lpfc_bgs_get_guard_err(uint32_t bgstat)
3499 {
3500 return (le32_to_cpu(bgstat) & BGS_GUARD_ERR_MASK) >>
3501 BGS_GUARD_ERR_SHIFT;
3502 }
3503
3504 #define LPFC_EXT_DATA_BDE_COUNT 3
3505 struct fcp_irw_ext {
3506 uint32_t io_tag64_low;
3507 uint32_t io_tag64_high;
3508 #ifdef __BIG_ENDIAN_BITFIELD
3509 uint8_t reserved1;
3510 uint8_t reserved2;
3511 uint8_t reserved3;
3512 uint8_t ebde_count;
3513 #else /* __LITTLE_ENDIAN */
3514 uint8_t ebde_count;
3515 uint8_t reserved3;
3516 uint8_t reserved2;
3517 uint8_t reserved1;
3518 #endif
3519 uint32_t reserved4;
3520 struct ulp_bde64 rbde; /* response bde */
3521 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
3522 uint8_t icd[32]; /* immediate command data (32 bytes) */
3523 };
3524
3525 typedef struct _IOCB { /* IOCB structure */
3526 union {
3527 GENERIC_RSP grsp; /* Generic response */
3528 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
3529 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
3530 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
3531 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
3532 A_MXRI64 amxri; /* abort multiple xri command overlay */
3533 GET_RPI getrpi; /* GET_RPI template */
3534 FCPI_FIELDS fcpi; /* FCP Initiator template */
3535 FCPT_FIELDS fcpt; /* FCP target template */
3536
3537 /* SLI-2 structures */
3538
3539 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
3540 * bde_64s */
3541 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
3542 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
3543 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
3544 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
3545 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
3546 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
3547 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
3548 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
3549 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
3550 struct sli4_bls_acc bls_acc; /* UNSOL ABTS BLS_ACC params */
3551 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
3552 } un;
3553 union {
3554 struct {
3555 #ifdef __BIG_ENDIAN_BITFIELD
3556 uint16_t ulpContext; /* High order bits word 6 */
3557 uint16_t ulpIoTag; /* Low order bits word 6 */
3558 #else /* __LITTLE_ENDIAN_BITFIELD */
3559 uint16_t ulpIoTag; /* Low order bits word 6 */
3560 uint16_t ulpContext; /* High order bits word 6 */
3561 #endif
3562 } t1;
3563 struct {
3564 #ifdef __BIG_ENDIAN_BITFIELD
3565 uint16_t ulpContext; /* High order bits word 6 */
3566 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3567 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3568 #else /* __LITTLE_ENDIAN_BITFIELD */
3569 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3570 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3571 uint16_t ulpContext; /* High order bits word 6 */
3572 #endif
3573 } t2;
3574 } un1;
3575 #define ulpContext un1.t1.ulpContext
3576 #define ulpIoTag un1.t1.ulpIoTag
3577 #define ulpIoTag0 un1.t2.ulpIoTag0
3578
3579 #ifdef __BIG_ENDIAN_BITFIELD
3580 uint32_t ulpTimeout:8;
3581 uint32_t ulpXS:1;
3582 uint32_t ulpFCP2Rcvy:1;
3583 uint32_t ulpPU:2;
3584 uint32_t ulpIr:1;
3585 uint32_t ulpClass:3;
3586 uint32_t ulpCommand:8;
3587 uint32_t ulpStatus:4;
3588 uint32_t ulpBdeCount:2;
3589 uint32_t ulpLe:1;
3590 uint32_t ulpOwner:1; /* Low order bit word 7 */
3591 #else /* __LITTLE_ENDIAN_BITFIELD */
3592 uint32_t ulpOwner:1; /* Low order bit word 7 */
3593 uint32_t ulpLe:1;
3594 uint32_t ulpBdeCount:2;
3595 uint32_t ulpStatus:4;
3596 uint32_t ulpCommand:8;
3597 uint32_t ulpClass:3;
3598 uint32_t ulpIr:1;
3599 uint32_t ulpPU:2;
3600 uint32_t ulpFCP2Rcvy:1;
3601 uint32_t ulpXS:1;
3602 uint32_t ulpTimeout:8;
3603 #endif
3604
3605 union {
3606 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
3607
3608 /* words 8-31 used for que_xri_cx iocb */
3609 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
3610 struct fcp_irw_ext fcp_ext;
3611 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
3612
3613 /* words 8-15 for BlockGuard */
3614 struct sli3_bg_fields sli3_bg;
3615 } unsli3;
3616
3617 #define ulpCt_h ulpXS
3618 #define ulpCt_l ulpFCP2Rcvy
3619
3620 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
3621 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
3622 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
3623 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
3624 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
3625 #define PARM_NPIV_DID 3
3626 #define CLASS1 0 /* Class 1 */
3627 #define CLASS2 1 /* Class 2 */
3628 #define CLASS3 2 /* Class 3 */
3629 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
3630
3631 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
3632 #define IOSTAT_FCP_RSP_ERROR 0x1
3633 #define IOSTAT_REMOTE_STOP 0x2
3634 #define IOSTAT_LOCAL_REJECT 0x3
3635 #define IOSTAT_NPORT_RJT 0x4
3636 #define IOSTAT_FABRIC_RJT 0x5
3637 #define IOSTAT_NPORT_BSY 0x6
3638 #define IOSTAT_FABRIC_BSY 0x7
3639 #define IOSTAT_INTERMED_RSP 0x8
3640 #define IOSTAT_LS_RJT 0x9
3641 #define IOSTAT_BA_RJT 0xA
3642 #define IOSTAT_RSVD1 0xB
3643 #define IOSTAT_RSVD2 0xC
3644 #define IOSTAT_RSVD3 0xD
3645 #define IOSTAT_RSVD4 0xE
3646 #define IOSTAT_NEED_BUFFER 0xF
3647 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
3648 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
3649 #define IOSTAT_CNT 0x11
3650
3651 } IOCB_t;
3652
3653
3654 #define SLI1_SLIM_SIZE (4 * 1024)
3655
3656 /* Up to 498 IOCBs will fit into 16k
3657 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
3658 */
3659 #define SLI2_SLIM_SIZE (64 * 1024)
3660
3661 /* Maximum IOCBs that will fit in SLI2 slim */
3662 #define MAX_SLI2_IOCB 498
3663 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
3664 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
3665 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
3666
3667 /* HBQ entries are 4 words each = 4k */
3668 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
3669 lpfc_sli_hbq_count())
3670
3671 struct lpfc_sli2_slim {
3672 MAILBOX_t mbx;
3673 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
3674 PCB_t pcb;
3675 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
3676 };
3677
3678 /*
3679 * This function checks PCI device to allow special handling for LC HBAs.
3680 *
3681 * Parameters:
3682 * device : struct pci_dev 's device field
3683 *
3684 * return 1 => TRUE
3685 * 0 => FALSE
3686 */
3687 static inline int
3688 lpfc_is_LC_HBA(unsigned short device)
3689 {
3690 if ((device == PCI_DEVICE_ID_TFLY) ||
3691 (device == PCI_DEVICE_ID_PFLY) ||
3692 (device == PCI_DEVICE_ID_LP101) ||
3693 (device == PCI_DEVICE_ID_BMID) ||
3694 (device == PCI_DEVICE_ID_BSMB) ||
3695 (device == PCI_DEVICE_ID_ZMID) ||
3696 (device == PCI_DEVICE_ID_ZSMB) ||
3697 (device == PCI_DEVICE_ID_SAT_MID) ||
3698 (device == PCI_DEVICE_ID_SAT_SMB) ||
3699 (device == PCI_DEVICE_ID_RFLY))
3700 return 1;
3701 else
3702 return 0;
3703 }
3704
3705 /*
3706 * Determine if an IOCB failed because of a link event or firmware reset.
3707 */
3708
3709 static inline int
3710 lpfc_error_lost_link(IOCB_t *iocbp)
3711 {
3712 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
3713 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
3714 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
3715 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
3716 }
3717
3718 #define MENLO_TRANSPORT_TYPE 0xfe
3719 #define MENLO_CONTEXT 0
3720 #define MENLO_PU 3
3721 #define MENLO_TIMEOUT 30
3722 #define SETVAR_MLOMNT 0x103107
3723 #define SETVAR_MLORST 0x103007
3724
3725 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
Linux kernel - Deliverables
This page took 0.124206 seconds and 5 git commands to generate.