projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge remote-tracking branch 'asoc/topic/tlv320aic26' into asoc-next
[deliverable/linux.git] / drivers / scsi / pm8001 / pm8001_init.c
1 /*
2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41 #include <linux/slab.h>
42 #include "pm8001_sas.h"
43 #include "pm8001_chips.h"
44
45 static struct scsi_transport_template *pm8001_stt;
46
47 /**
48 * chip info structure to identify chip key functionality as
49 * encryption available/not, no of ports, hw specific function ref
50 */
51 static const struct pm8001_chip_info pm8001_chips[] = {
52 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
53 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
54 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
55 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
56 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
57 };
58 static int pm8001_id;
59
60 LIST_HEAD(hba_list);
61
62 struct workqueue_struct *pm8001_wq;
63
64 /**
65 * The main structure which LLDD must register for scsi core.
66 */
67 static struct scsi_host_template pm8001_sht = {
68 .module = THIS_MODULE,
69 .name = DRV_NAME,
70 .queuecommand = sas_queuecommand,
71 .target_alloc = sas_target_alloc,
72 .slave_configure = sas_slave_configure,
73 .scan_finished = pm8001_scan_finished,
74 .scan_start = pm8001_scan_start,
75 .change_queue_depth = sas_change_queue_depth,
76 .change_queue_type = sas_change_queue_type,
77 .bios_param = sas_bios_param,
78 .can_queue = 1,
79 .cmd_per_lun = 1,
80 .this_id = -1,
81 .sg_tablesize = SG_ALL,
82 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
83 .use_clustering = ENABLE_CLUSTERING,
84 .eh_device_reset_handler = sas_eh_device_reset_handler,
85 .eh_bus_reset_handler = sas_eh_bus_reset_handler,
86 .target_destroy = sas_target_destroy,
87 .ioctl = sas_ioctl,
88 .shost_attrs = pm8001_host_attrs,
89 };
90
91 /**
92 * Sas layer call this function to execute specific task.
93 */
94 static struct sas_domain_function_template pm8001_transport_ops = {
95 .lldd_dev_found = pm8001_dev_found,
96 .lldd_dev_gone = pm8001_dev_gone,
97
98 .lldd_execute_task = pm8001_queue_command,
99 .lldd_control_phy = pm8001_phy_control,
100
101 .lldd_abort_task = pm8001_abort_task,
102 .lldd_abort_task_set = pm8001_abort_task_set,
103 .lldd_clear_aca = pm8001_clear_aca,
104 .lldd_clear_task_set = pm8001_clear_task_set,
105 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
106 .lldd_lu_reset = pm8001_lu_reset,
107 .lldd_query_task = pm8001_query_task,
108 };
109
110 /**
111 *pm8001_phy_init - initiate our adapter phys
112 *@pm8001_ha: our hba structure.
113 *@phy_id: phy id.
114 */
115 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
116 {
117 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
118 struct asd_sas_phy *sas_phy = &phy->sas_phy;
119 phy->phy_state = 0;
120 phy->pm8001_ha = pm8001_ha;
121 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
122 sas_phy->class = SAS;
123 sas_phy->iproto = SAS_PROTOCOL_ALL;
124 sas_phy->tproto = 0;
125 sas_phy->type = PHY_TYPE_PHYSICAL;
126 sas_phy->role = PHY_ROLE_INITIATOR;
127 sas_phy->oob_mode = OOB_NOT_CONNECTED;
128 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
129 sas_phy->id = phy_id;
130 sas_phy->sas_addr = &pm8001_ha->sas_addr[0];
131 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
132 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
133 sas_phy->lldd_phy = phy;
134 }
135
136 /**
137 *pm8001_free - free hba
138 *@pm8001_ha: our hba structure.
139 *
140 */
141 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
142 {
143 int i;
144
145 if (!pm8001_ha)
146 return;
147
148 for (i = 0; i < USI_MAX_MEMCNT; i++) {
149 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
150 pci_free_consistent(pm8001_ha->pdev,
151 (pm8001_ha->memoryMap.region[i].total_len +
152 pm8001_ha->memoryMap.region[i].alignment),
153 pm8001_ha->memoryMap.region[i].virt_ptr,
154 pm8001_ha->memoryMap.region[i].phys_addr);
155 }
156 }
157 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
158 if (pm8001_ha->shost)
159 scsi_host_put(pm8001_ha->shost);
160 flush_workqueue(pm8001_wq);
161 kfree(pm8001_ha->tags);
162 kfree(pm8001_ha);
163 }
164
165 #ifdef PM8001_USE_TASKLET
166
167 /**
168 * tasklet for 64 msi-x interrupt handler
169 * @opaque: the passed general host adapter struct
170 * Note: pm8001_tasklet is common for pm8001 & pm80xx
171 */
172 static void pm8001_tasklet(unsigned long opaque)
173 {
174 struct pm8001_hba_info *pm8001_ha;
175 u32 vec;
176 pm8001_ha = (struct pm8001_hba_info *)opaque;
177 if (unlikely(!pm8001_ha))
178 BUG_ON(1);
179 vec = pm8001_ha->int_vector;
180 PM8001_CHIP_DISP->isr(pm8001_ha, vec);
181 }
182 #endif
183
184 static struct pm8001_hba_info *outq_to_hba(u8 *outq)
185 {
186 return container_of((outq - *outq), struct pm8001_hba_info, outq[0]);
187 }
188
189 /**
190 * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
191 * It obtains the vector number and calls the equivalent bottom
192 * half or services directly.
193 * @opaque: the passed outbound queue/vector. Host structure is
194 * retrieved from the same.
195 */
196 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
197 {
198 struct pm8001_hba_info *pm8001_ha = outq_to_hba(opaque);
199 u8 outq = *(u8 *)opaque;
200 irqreturn_t ret = IRQ_HANDLED;
201 if (unlikely(!pm8001_ha))
202 return IRQ_NONE;
203 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
204 return IRQ_NONE;
205 pm8001_ha->int_vector = outq;
206 #ifdef PM8001_USE_TASKLET
207 tasklet_schedule(&pm8001_ha->tasklet);
208 #else
209 ret = PM8001_CHIP_DISP->isr(pm8001_ha, outq);
210 #endif
211 return ret;
212 }
213
214 /**
215 * pm8001_interrupt_handler_intx - main INTx interrupt handler.
216 * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
217 */
218
219 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
220 {
221 struct pm8001_hba_info *pm8001_ha;
222 irqreturn_t ret = IRQ_HANDLED;
223 struct sas_ha_struct *sha = dev_id;
224 pm8001_ha = sha->lldd_ha;
225 if (unlikely(!pm8001_ha))
226 return IRQ_NONE;
227 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
228 return IRQ_NONE;
229
230 pm8001_ha->int_vector = 0;
231 #ifdef PM8001_USE_TASKLET
232 tasklet_schedule(&pm8001_ha->tasklet);
233 #else
234 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
235 #endif
236 return ret;
237 }
238
239 /**
240 * pm8001_alloc - initiate our hba structure and 6 DMAs area.
241 * @pm8001_ha:our hba structure.
242 *
243 */
244 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
245 const struct pci_device_id *ent)
246 {
247 int i;
248 spin_lock_init(&pm8001_ha->lock);
249 PM8001_INIT_DBG(pm8001_ha,
250 pm8001_printk("pm8001_alloc: PHY:%x\n",
251 pm8001_ha->chip->n_phy));
252 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
253 pm8001_phy_init(pm8001_ha, i);
254 pm8001_ha->port[i].wide_port_phymap = 0;
255 pm8001_ha->port[i].port_attached = 0;
256 pm8001_ha->port[i].port_state = 0;
257 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
258 }
259
260 pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
261 if (!pm8001_ha->tags)
262 goto err_out;
263 /* MPI Memory region 1 for AAP Event Log for fw */
264 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
265 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
266 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
267 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
268
269 /* MPI Memory region 2 for IOP Event Log for fw */
270 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
271 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
272 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
273 pm8001_ha->memoryMap.region[IOP].alignment = 32;
274
275 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
276 /* MPI Memory region 3 for consumer Index of inbound queues */
277 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
278 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
279 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
280 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
281
282 if ((ent->driver_data) != chip_8001) {
283 /* MPI Memory region 5 inbound queues */
284 pm8001_ha->memoryMap.region[IB+i].num_elements =
285 PM8001_MPI_QUEUE;
286 pm8001_ha->memoryMap.region[IB+i].element_size = 128;
287 pm8001_ha->memoryMap.region[IB+i].total_len =
288 PM8001_MPI_QUEUE * 128;
289 pm8001_ha->memoryMap.region[IB+i].alignment = 128;
290 } else {
291 pm8001_ha->memoryMap.region[IB+i].num_elements =
292 PM8001_MPI_QUEUE;
293 pm8001_ha->memoryMap.region[IB+i].element_size = 64;
294 pm8001_ha->memoryMap.region[IB+i].total_len =
295 PM8001_MPI_QUEUE * 64;
296 pm8001_ha->memoryMap.region[IB+i].alignment = 64;
297 }
298 }
299
300 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
301 /* MPI Memory region 4 for producer Index of outbound queues */
302 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
303 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
304 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
305 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
306
307 if (ent->driver_data != chip_8001) {
308 /* MPI Memory region 6 Outbound queues */
309 pm8001_ha->memoryMap.region[OB+i].num_elements =
310 PM8001_MPI_QUEUE;
311 pm8001_ha->memoryMap.region[OB+i].element_size = 128;
312 pm8001_ha->memoryMap.region[OB+i].total_len =
313 PM8001_MPI_QUEUE * 128;
314 pm8001_ha->memoryMap.region[OB+i].alignment = 128;
315 } else {
316 /* MPI Memory region 6 Outbound queues */
317 pm8001_ha->memoryMap.region[OB+i].num_elements =
318 PM8001_MPI_QUEUE;
319 pm8001_ha->memoryMap.region[OB+i].element_size = 64;
320 pm8001_ha->memoryMap.region[OB+i].total_len =
321 PM8001_MPI_QUEUE * 64;
322 pm8001_ha->memoryMap.region[OB+i].alignment = 64;
323 }
324
325 }
326 /* Memory region write DMA*/
327 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
328 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
329 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
330 /* Memory region for devices*/
331 pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
332 pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
333 sizeof(struct pm8001_device);
334 pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
335 sizeof(struct pm8001_device);
336
337 /* Memory region for ccb_info*/
338 pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
339 pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
340 sizeof(struct pm8001_ccb_info);
341 pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
342 sizeof(struct pm8001_ccb_info);
343
344 /* Memory region for fw flash */
345 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
346
347 for (i = 0; i < USI_MAX_MEMCNT; i++) {
348 if (pm8001_mem_alloc(pm8001_ha->pdev,
349 &pm8001_ha->memoryMap.region[i].virt_ptr,
350 &pm8001_ha->memoryMap.region[i].phys_addr,
351 &pm8001_ha->memoryMap.region[i].phys_addr_hi,
352 &pm8001_ha->memoryMap.region[i].phys_addr_lo,
353 pm8001_ha->memoryMap.region[i].total_len,
354 pm8001_ha->memoryMap.region[i].alignment) != 0) {
355 PM8001_FAIL_DBG(pm8001_ha,
356 pm8001_printk("Mem%d alloc failed\n",
357 i));
358 goto err_out;
359 }
360 }
361
362 pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
363 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
364 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
365 pm8001_ha->devices[i].id = i;
366 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
367 pm8001_ha->devices[i].running_req = 0;
368 }
369 pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
370 for (i = 0; i < PM8001_MAX_CCB; i++) {
371 pm8001_ha->ccb_info[i].ccb_dma_handle =
372 pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
373 i * sizeof(struct pm8001_ccb_info);
374 pm8001_ha->ccb_info[i].task = NULL;
375 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
376 pm8001_ha->ccb_info[i].device = NULL;
377 ++pm8001_ha->tags_num;
378 }
379 pm8001_ha->flags = PM8001F_INIT_TIME;
380 /* Initialize tags */
381 pm8001_tag_init(pm8001_ha);
382 return 0;
383 err_out:
384 return 1;
385 }
386
387 /**
388 * pm8001_ioremap - remap the pci high physical address to kernal virtual
389 * address so that we can access them.
390 * @pm8001_ha:our hba structure.
391 */
392 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
393 {
394 u32 bar;
395 u32 logicalBar = 0;
396 struct pci_dev *pdev;
397
398 pdev = pm8001_ha->pdev;
399 /* map pci mem (PMC pci base 0-3)*/
400 for (bar = 0; bar < 6; bar++) {
401 /*
402 ** logical BARs for SPC:
403 ** bar 0 and 1 - logical BAR0
404 ** bar 2 and 3 - logical BAR1
405 ** bar4 - logical BAR2
406 ** bar5 - logical BAR3
407 ** Skip the appropriate assignments:
408 */
409 if ((bar == 1) || (bar == 3))
410 continue;
411 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
412 pm8001_ha->io_mem[logicalBar].membase =
413 pci_resource_start(pdev, bar);
414 pm8001_ha->io_mem[logicalBar].membase &=
415 (u32)PCI_BASE_ADDRESS_MEM_MASK;
416 pm8001_ha->io_mem[logicalBar].memsize =
417 pci_resource_len(pdev, bar);
418 pm8001_ha->io_mem[logicalBar].memvirtaddr =
419 ioremap(pm8001_ha->io_mem[logicalBar].membase,
420 pm8001_ha->io_mem[logicalBar].memsize);
421 PM8001_INIT_DBG(pm8001_ha,
422 pm8001_printk("PCI: bar %d, logicalBar %d ",
423 bar, logicalBar));
424 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
425 "base addr %llx virt_addr=%llx len=%d\n",
426 (u64)pm8001_ha->io_mem[logicalBar].membase,
427 (u64)(unsigned long)
428 pm8001_ha->io_mem[logicalBar].memvirtaddr,
429 pm8001_ha->io_mem[logicalBar].memsize));
430 } else {
431 pm8001_ha->io_mem[logicalBar].membase = 0;
432 pm8001_ha->io_mem[logicalBar].memsize = 0;
433 pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
434 }
435 logicalBar++;
436 }
437 return 0;
438 }
439
440 /**
441 * pm8001_pci_alloc - initialize our ha card structure
442 * @pdev: pci device.
443 * @ent: ent
444 * @shost: scsi host struct which has been initialized before.
445 */
446 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
447 const struct pci_device_id *ent,
448 struct Scsi_Host *shost)
449
450 {
451 struct pm8001_hba_info *pm8001_ha;
452 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
453
454
455 pm8001_ha = sha->lldd_ha;
456 if (!pm8001_ha)
457 return NULL;
458
459 pm8001_ha->pdev = pdev;
460 pm8001_ha->dev = &pdev->dev;
461 pm8001_ha->chip_id = ent->driver_data;
462 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
463 pm8001_ha->irq = pdev->irq;
464 pm8001_ha->sas = sha;
465 pm8001_ha->shost = shost;
466 pm8001_ha->id = pm8001_id++;
467 pm8001_ha->logging_level = 0x01;
468 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
469 /* IOMB size is 128 for 8088/89 controllers */
470 if (pm8001_ha->chip_id != chip_8001)
471 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
472 else
473 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
474
475 #ifdef PM8001_USE_TASKLET
476 /**
477 * default tasklet for non msi-x interrupt handler/first msi-x
478 * interrupt handler
479 **/
480 tasklet_init(&pm8001_ha->tasklet, pm8001_tasklet,
481 (unsigned long)pm8001_ha);
482 #endif
483 pm8001_ioremap(pm8001_ha);
484 if (!pm8001_alloc(pm8001_ha, ent))
485 return pm8001_ha;
486 pm8001_free(pm8001_ha);
487 return NULL;
488 }
489
490 /**
491 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
492 * @pdev: pci device.
493 */
494 static int pci_go_44(struct pci_dev *pdev)
495 {
496 int rc;
497
498 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) {
499 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44));
500 if (rc) {
501 rc = pci_set_consistent_dma_mask(pdev,
502 DMA_BIT_MASK(32));
503 if (rc) {
504 dev_printk(KERN_ERR, &pdev->dev,
505 "44-bit DMA enable failed\n");
506 return rc;
507 }
508 }
509 } else {
510 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
511 if (rc) {
512 dev_printk(KERN_ERR, &pdev->dev,
513 "32-bit DMA enable failed\n");
514 return rc;
515 }
516 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
517 if (rc) {
518 dev_printk(KERN_ERR, &pdev->dev,
519 "32-bit consistent DMA enable failed\n");
520 return rc;
521 }
522 }
523 return rc;
524 }
525
526 /**
527 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
528 * @shost: scsi host which has been allocated outside.
529 * @chip_info: our ha struct.
530 */
531 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
532 const struct pm8001_chip_info *chip_info)
533 {
534 int phy_nr, port_nr;
535 struct asd_sas_phy **arr_phy;
536 struct asd_sas_port **arr_port;
537 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
538
539 phy_nr = chip_info->n_phy;
540 port_nr = phy_nr;
541 memset(sha, 0x00, sizeof(*sha));
542 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
543 if (!arr_phy)
544 goto exit;
545 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
546 if (!arr_port)
547 goto exit_free2;
548
549 sha->sas_phy = arr_phy;
550 sha->sas_port = arr_port;
551 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
552 if (!sha->lldd_ha)
553 goto exit_free1;
554
555 shost->transportt = pm8001_stt;
556 shost->max_id = PM8001_MAX_DEVICES;
557 shost->max_lun = 8;
558 shost->max_channel = 0;
559 shost->unique_id = pm8001_id;
560 shost->max_cmd_len = 16;
561 shost->can_queue = PM8001_CAN_QUEUE;
562 shost->cmd_per_lun = 32;
563 return 0;
564 exit_free1:
565 kfree(arr_port);
566 exit_free2:
567 kfree(arr_phy);
568 exit:
569 return -1;
570 }
571
572 /**
573 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
574 * @shost: scsi host which has been allocated outside
575 * @chip_info: our ha struct.
576 */
577 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
578 const struct pm8001_chip_info *chip_info)
579 {
580 int i = 0;
581 struct pm8001_hba_info *pm8001_ha;
582 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
583
584 pm8001_ha = sha->lldd_ha;
585 for (i = 0; i < chip_info->n_phy; i++) {
586 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
587 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
588 }
589 sha->sas_ha_name = DRV_NAME;
590 sha->dev = pm8001_ha->dev;
591
592 sha->lldd_module = THIS_MODULE;
593 sha->sas_addr = &pm8001_ha->sas_addr[0];
594 sha->num_phys = chip_info->n_phy;
595 sha->lldd_max_execute_num = 1;
596 sha->lldd_queue_size = PM8001_CAN_QUEUE;
597 sha->core.shost = shost;
598 }
599
600 /**
601 * pm8001_init_sas_add - initialize sas address
602 * @chip_info: our ha struct.
603 *
604 * Currently we just set the fixed SAS address to our HBA,for manufacture,
605 * it should read from the EEPROM
606 */
607 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
608 {
609 u8 i, j;
610 #ifdef PM8001_READ_VPD
611 /* For new SPC controllers WWN is stored in flash vpd
612 * For SPC/SPCve controllers WWN is stored in EEPROM
613 * For Older SPC WWN is stored in NVMD
614 */
615 DECLARE_COMPLETION_ONSTACK(completion);
616 struct pm8001_ioctl_payload payload;
617 u16 deviceid;
618 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
619 pm8001_ha->nvmd_completion = &completion;
620
621 if (pm8001_ha->chip_id == chip_8001) {
622 if (deviceid == 0x8081) {
623 payload.minor_function = 4;
624 payload.length = 4096;
625 } else {
626 payload.minor_function = 0;
627 payload.length = 128;
628 }
629 } else {
630 payload.minor_function = 1;
631 payload.length = 4096;
632 }
633 payload.offset = 0;
634 payload.func_specific = kzalloc(payload.length, GFP_KERNEL);
635 PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
636 wait_for_completion(&completion);
637
638 for (i = 0, j = 0; i <= 7; i++, j++) {
639 if (pm8001_ha->chip_id == chip_8001) {
640 if (deviceid == 0x8081)
641 pm8001_ha->sas_addr[j] =
642 payload.func_specific[0x704 + i];
643 } else
644 pm8001_ha->sas_addr[j] =
645 payload.func_specific[0x804 + i];
646 }
647
648 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
649 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
650 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
651 PM8001_INIT_DBG(pm8001_ha,
652 pm8001_printk("phy %d sas_addr = %016llx\n", i,
653 pm8001_ha->phy[i].dev_sas_addr));
654 }
655 #else
656 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
657 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
658 pm8001_ha->phy[i].dev_sas_addr =
659 cpu_to_be64((u64)
660 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
661 }
662 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
663 SAS_ADDR_SIZE);
664 #endif
665 }
666
667 #ifdef PM8001_USE_MSIX
668 /**
669 * pm8001_setup_msix - enable MSI-X interrupt
670 * @chip_info: our ha struct.
671 * @irq_handler: irq_handler
672 */
673 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
674 {
675 u32 i = 0, j = 0;
676 u32 number_of_intr;
677 int flag = 0;
678 u32 max_entry;
679 int rc;
680 static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3];
681
682 /* SPCv controllers supports 64 msi-x */
683 if (pm8001_ha->chip_id == chip_8001) {
684 number_of_intr = 1;
685 flag |= IRQF_DISABLED;
686 } else {
687 number_of_intr = PM8001_MAX_MSIX_VEC;
688 flag &= ~IRQF_SHARED;
689 flag |= IRQF_DISABLED;
690 }
691
692 max_entry = sizeof(pm8001_ha->msix_entries) /
693 sizeof(pm8001_ha->msix_entries[0]);
694 for (i = 0; i < max_entry ; i++)
695 pm8001_ha->msix_entries[i].entry = i;
696 rc = pci_enable_msix(pm8001_ha->pdev, pm8001_ha->msix_entries,
697 number_of_intr);
698 pm8001_ha->number_of_intr = number_of_intr;
699 if (!rc) {
700 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
701 "pci_enable_msix request ret:%d no of intr %d\n",
702 rc, pm8001_ha->number_of_intr));
703
704 for (i = 0; i < number_of_intr; i++)
705 pm8001_ha->outq[i] = i;
706
707 for (i = 0; i < number_of_intr; i++) {
708 snprintf(intr_drvname[i], sizeof(intr_drvname[0]),
709 DRV_NAME"%d", i);
710 if (request_irq(pm8001_ha->msix_entries[i].vector,
711 pm8001_interrupt_handler_msix, flag,
712 intr_drvname[i], &pm8001_ha->outq[i])) {
713 for (j = 0; j < i; j++)
714 free_irq(
715 pm8001_ha->msix_entries[j].vector,
716 &pm8001_ha->outq[j]);
717 pci_disable_msix(pm8001_ha->pdev);
718 break;
719 }
720 }
721 }
722 return rc;
723 }
724 #endif
725
726 /**
727 * pm8001_request_irq - register interrupt
728 * @chip_info: our ha struct.
729 */
730 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
731 {
732 struct pci_dev *pdev;
733 int rc;
734
735 pdev = pm8001_ha->pdev;
736
737 #ifdef PM8001_USE_MSIX
738 if (pdev->msix_cap)
739 return pm8001_setup_msix(pm8001_ha);
740 else {
741 PM8001_INIT_DBG(pm8001_ha,
742 pm8001_printk("MSIX not supported!!!\n"));
743 goto intx;
744 }
745 #endif
746
747 intx:
748 /* initialize the INT-X interrupt */
749 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
750 DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost));
751 return rc;
752 }
753
754 /**
755 * pm8001_pci_probe - probe supported device
756 * @pdev: pci device which kernel has been prepared for.
757 * @ent: pci device id
758 *
759 * This function is the main initialization function, when register a new
760 * pci driver it is invoked, all struct an hardware initilization should be done
761 * here, also, register interrupt
762 */
763 static int pm8001_pci_probe(struct pci_dev *pdev,
764 const struct pci_device_id *ent)
765 {
766 unsigned int rc;
767 u32 pci_reg;
768 u8 i = 0;
769 struct pm8001_hba_info *pm8001_ha;
770 struct Scsi_Host *shost = NULL;
771 const struct pm8001_chip_info *chip;
772
773 dev_printk(KERN_INFO, &pdev->dev,
774 "pm80xx: driver version %s\n", DRV_VERSION);
775 rc = pci_enable_device(pdev);
776 if (rc)
777 goto err_out_enable;
778 pci_set_master(pdev);
779 /*
780 * Enable pci slot busmaster by setting pci command register.
781 * This is required by FW for Cyclone card.
782 */
783
784 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
785 pci_reg |= 0x157;
786 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
787 rc = pci_request_regions(pdev, DRV_NAME);
788 if (rc)
789 goto err_out_disable;
790 rc = pci_go_44(pdev);
791 if (rc)
792 goto err_out_regions;
793
794 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
795 if (!shost) {
796 rc = -ENOMEM;
797 goto err_out_regions;
798 }
799 chip = &pm8001_chips[ent->driver_data];
800 SHOST_TO_SAS_HA(shost) =
801 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
802 if (!SHOST_TO_SAS_HA(shost)) {
803 rc = -ENOMEM;
804 goto err_out_free_host;
805 }
806
807 rc = pm8001_prep_sas_ha_init(shost, chip);
808 if (rc) {
809 rc = -ENOMEM;
810 goto err_out_free;
811 }
812 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
813 /* ent->driver variable is used to differentiate between controllers */
814 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
815 if (!pm8001_ha) {
816 rc = -ENOMEM;
817 goto err_out_free;
818 }
819 list_add_tail(&pm8001_ha->list, &hba_list);
820 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
821 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
822 if (rc) {
823 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
824 "chip_init failed [ret: %d]\n", rc));
825 goto err_out_ha_free;
826 }
827
828 rc = scsi_add_host(shost, &pdev->dev);
829 if (rc)
830 goto err_out_ha_free;
831 rc = pm8001_request_irq(pm8001_ha);
832 if (rc) {
833 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
834 "pm8001_request_irq failed [ret: %d]\n", rc));
835 goto err_out_shost;
836 }
837
838 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
839 if (pm8001_ha->chip_id != chip_8001) {
840 for (i = 1; i < pm8001_ha->number_of_intr; i++)
841 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
842 /* setup thermal configuration. */
843 pm80xx_set_thermal_config(pm8001_ha);
844 }
845
846 pm8001_init_sas_add(pm8001_ha);
847 pm8001_post_sas_ha_init(shost, chip);
848 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
849 if (rc)
850 goto err_out_shost;
851 scsi_scan_host(pm8001_ha->shost);
852 return 0;
853
854 err_out_shost:
855 scsi_remove_host(pm8001_ha->shost);
856 err_out_ha_free:
857 pm8001_free(pm8001_ha);
858 err_out_free:
859 kfree(SHOST_TO_SAS_HA(shost));
860 err_out_free_host:
861 kfree(shost);
862 err_out_regions:
863 pci_release_regions(pdev);
864 err_out_disable:
865 pci_disable_device(pdev);
866 err_out_enable:
867 return rc;
868 }
869
870 static void pm8001_pci_remove(struct pci_dev *pdev)
871 {
872 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
873 struct pm8001_hba_info *pm8001_ha;
874 int i;
875 pm8001_ha = sha->lldd_ha;
876 pci_set_drvdata(pdev, NULL);
877 sas_unregister_ha(sha);
878 sas_remove_host(pm8001_ha->shost);
879 list_del(&pm8001_ha->list);
880 scsi_remove_host(pm8001_ha->shost);
881 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
882 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
883
884 #ifdef PM8001_USE_MSIX
885 for (i = 0; i < pm8001_ha->number_of_intr; i++)
886 synchronize_irq(pm8001_ha->msix_entries[i].vector);
887 for (i = 0; i < pm8001_ha->number_of_intr; i++)
888 free_irq(pm8001_ha->msix_entries[i].vector,
889 &pm8001_ha->outq[i]);
890 pci_disable_msix(pdev);
891 #else
892 free_irq(pm8001_ha->irq, sha);
893 #endif
894 #ifdef PM8001_USE_TASKLET
895 tasklet_kill(&pm8001_ha->tasklet);
896 #endif
897 pm8001_free(pm8001_ha);
898 kfree(sha->sas_phy);
899 kfree(sha->sas_port);
900 kfree(sha);
901 pci_release_regions(pdev);
902 pci_disable_device(pdev);
903 }
904
905 /**
906 * pm8001_pci_suspend - power management suspend main entry point
907 * @pdev: PCI device struct
908 * @state: PM state change to (usually PCI_D3)
909 *
910 * Returns 0 success, anything else error.
911 */
912 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
913 {
914 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
915 struct pm8001_hba_info *pm8001_ha;
916 int i;
917 u32 device_state;
918 pm8001_ha = sha->lldd_ha;
919 flush_workqueue(pm8001_wq);
920 scsi_block_requests(pm8001_ha->shost);
921 if (!pdev->pm_cap) {
922 dev_err(&pdev->dev, " PCI PM not supported\n");
923 return -ENODEV;
924 }
925 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
926 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
927 #ifdef PM8001_USE_MSIX
928 for (i = 0; i < pm8001_ha->number_of_intr; i++)
929 synchronize_irq(pm8001_ha->msix_entries[i].vector);
930 for (i = 0; i < pm8001_ha->number_of_intr; i++)
931 free_irq(pm8001_ha->msix_entries[i].vector,
932 &pm8001_ha->outq[i]);
933 pci_disable_msix(pdev);
934 #else
935 free_irq(pm8001_ha->irq, sha);
936 #endif
937 #ifdef PM8001_USE_TASKLET
938 tasklet_kill(&pm8001_ha->tasklet);
939 #endif
940 device_state = pci_choose_state(pdev, state);
941 pm8001_printk("pdev=0x%p, slot=%s, entering "
942 "operating state [D%d]\n", pdev,
943 pm8001_ha->name, device_state);
944 pci_save_state(pdev);
945 pci_disable_device(pdev);
946 pci_set_power_state(pdev, device_state);
947 return 0;
948 }
949
950 /**
951 * pm8001_pci_resume - power management resume main entry point
952 * @pdev: PCI device struct
953 *
954 * Returns 0 success, anything else error.
955 */
956 static int pm8001_pci_resume(struct pci_dev *pdev)
957 {
958 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
959 struct pm8001_hba_info *pm8001_ha;
960 int rc;
961 u8 i = 0;
962 u32 device_state;
963 pm8001_ha = sha->lldd_ha;
964 device_state = pdev->current_state;
965
966 pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
967 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
968
969 pci_set_power_state(pdev, PCI_D0);
970 pci_enable_wake(pdev, PCI_D0, 0);
971 pci_restore_state(pdev);
972 rc = pci_enable_device(pdev);
973 if (rc) {
974 pm8001_printk("slot=%s Enable device failed during resume\n",
975 pm8001_ha->name);
976 goto err_out_enable;
977 }
978
979 pci_set_master(pdev);
980 rc = pci_go_44(pdev);
981 if (rc)
982 goto err_out_disable;
983
984 /* chip soft rst only for spc */
985 if (pm8001_ha->chip_id == chip_8001) {
986 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
987 PM8001_INIT_DBG(pm8001_ha,
988 pm8001_printk("chip soft reset successful\n"));
989 }
990 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
991 if (rc)
992 goto err_out_disable;
993
994 /* disable all the interrupt bits */
995 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
996
997 rc = pm8001_request_irq(pm8001_ha);
998 if (rc)
999 goto err_out_disable;
1000 #ifdef PM8001_USE_TASKLET
1001 /* default tasklet for non msi-x interrupt handler/first msi-x
1002 * interrupt handler */
1003 tasklet_init(&pm8001_ha->tasklet, pm8001_tasklet,
1004 (unsigned long)pm8001_ha);
1005 #endif
1006 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1007 if (pm8001_ha->chip_id != chip_8001) {
1008 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1009 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1010 }
1011 scsi_unblock_requests(pm8001_ha->shost);
1012 return 0;
1013
1014 err_out_disable:
1015 scsi_remove_host(pm8001_ha->shost);
1016 pci_disable_device(pdev);
1017 err_out_enable:
1018 return rc;
1019 }
1020
1021 /* update of pci device, vendor id and driver data with
1022 * unique value for each of the controller
1023 */
1024 static struct pci_device_id pm8001_pci_table[] = {
1025 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1026 {
1027 PCI_DEVICE(0x117c, 0x0042),
1028 .driver_data = chip_8001
1029 },
1030 /* Support for SPC/SPCv/SPCve controllers */
1031 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1032 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1033 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1034 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1035 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1036 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1037 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1038 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1039 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1040 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1041 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1042 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1043 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1044 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1045 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1046 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1047 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1048 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1049 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1050 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1051 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1052 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1053 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1054 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1055 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1056 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1057 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1058 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1059 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1060 {} /* terminate list */
1061 };
1062
1063 static struct pci_driver pm8001_pci_driver = {
1064 .name = DRV_NAME,
1065 .id_table = pm8001_pci_table,
1066 .probe = pm8001_pci_probe,
1067 .remove = pm8001_pci_remove,
1068 .suspend = pm8001_pci_suspend,
1069 .resume = pm8001_pci_resume,
1070 };
1071
1072 /**
1073 * pm8001_init - initialize scsi transport template
1074 */
1075 static int __init pm8001_init(void)
1076 {
1077 int rc = -ENOMEM;
1078
1079 pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1080 if (!pm8001_wq)
1081 goto err;
1082
1083 pm8001_id = 0;
1084 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1085 if (!pm8001_stt)
1086 goto err_wq;
1087 rc = pci_register_driver(&pm8001_pci_driver);
1088 if (rc)
1089 goto err_tp;
1090 return 0;
1091
1092 err_tp:
1093 sas_release_transport(pm8001_stt);
1094 err_wq:
1095 destroy_workqueue(pm8001_wq);
1096 err:
1097 return rc;
1098 }
1099
1100 static void __exit pm8001_exit(void)
1101 {
1102 pci_unregister_driver(&pm8001_pci_driver);
1103 sas_release_transport(pm8001_stt);
1104 destroy_workqueue(pm8001_wq);
1105 }
1106
1107 module_init(pm8001_init);
1108 module_exit(pm8001_exit);
1109
1110 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1111 MODULE_DESCRIPTION(
1112 "PMC-Sierra PM8001/8081/8088/8089 SAS/SATA controller driver");
1113 MODULE_VERSION(DRV_VERSION);
1114 MODULE_LICENSE("GPL");
1115 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1116
Linux kernel - Deliverables
This page took 0.060265 seconds and 5 git commands to generate.