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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[deliverable/linux.git] / drivers / scsi / pm8001 / pm80xx_hwi.c
1 /*
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm80xx_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46 #define SMP_DIRECT 1
47 #define SMP_INDIRECT 2
48
49
50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
51 {
52 u32 reg_val;
53 unsigned long start;
54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
55 /* confirm the setting is written */
56 start = jiffies + HZ; /* 1 sec */
57 do {
58 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
59 } while ((reg_val != shift_value) && time_before(jiffies, start));
60 if (reg_val != shift_value) {
61 PM8001_FAIL_DBG(pm8001_ha,
62 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
63 " = 0x%x\n", reg_val));
64 return -1;
65 }
66 return 0;
67 }
68
69 void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset,
70 const void *destination,
71 u32 dw_count, u32 bus_base_number)
72 {
73 u32 index, value, offset;
74 u32 *destination1;
75 destination1 = (u32 *)destination;
76
77 for (index = 0; index < dw_count; index += 4, destination1++) {
78 offset = (soffset + index / 4);
79 if (offset < (64 * 1024)) {
80 value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
81 *destination1 = cpu_to_le32(value);
82 }
83 }
84 return;
85 }
86
87 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
88 struct device_attribute *attr, char *buf)
89 {
90 struct Scsi_Host *shost = class_to_shost(cdev);
91 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
92 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
93 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
94 u32 accum_len , reg_val, index, *temp;
95 unsigned long start;
96 u8 *direct_data;
97 char *fatal_error_data = buf;
98
99 pm8001_ha->forensic_info.data_buf.direct_data = buf;
100 if (pm8001_ha->chip_id == chip_8001) {
101 pm8001_ha->forensic_info.data_buf.direct_data +=
102 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
103 "Not supported for SPC controller");
104 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
105 (char *)buf;
106 }
107 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
108 PM8001_IO_DBG(pm8001_ha,
109 pm8001_printk("forensic_info TYPE_NON_FATAL..............\n"));
110 direct_data = (u8 *)fatal_error_data;
111 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
112 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
113 pm8001_ha->forensic_info.data_buf.read_len = 0;
114
115 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
116
117 /* start to get data */
118 /* Program the MEMBASE II Shifting Register with 0x00.*/
119 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
120 pm8001_ha->fatal_forensic_shift_offset);
121 pm8001_ha->forensic_last_offset = 0;
122 pm8001_ha->forensic_fatal_step = 0;
123 pm8001_ha->fatal_bar_loc = 0;
124 }
125
126 /* Read until accum_len is retrived */
127 accum_len = pm8001_mr32(fatal_table_address,
128 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
129 PM8001_IO_DBG(pm8001_ha, pm8001_printk("accum_len 0x%x\n",
130 accum_len));
131 if (accum_len == 0xFFFFFFFF) {
132 PM8001_IO_DBG(pm8001_ha,
133 pm8001_printk("Possible PCI issue 0x%x not expected\n",
134 accum_len));
135 return -EIO;
136 }
137 if (accum_len == 0 || accum_len >= 0x100000) {
138 pm8001_ha->forensic_info.data_buf.direct_data +=
139 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
140 "%08x ", 0xFFFFFFFF);
141 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
142 (char *)buf;
143 }
144 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
145 if (pm8001_ha->forensic_fatal_step == 0) {
146 moreData:
147 if (pm8001_ha->forensic_info.data_buf.direct_data) {
148 /* Data is in bar, copy to host memory */
149 pm80xx_pci_mem_copy(pm8001_ha, pm8001_ha->fatal_bar_loc,
150 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
151 pm8001_ha->forensic_info.data_buf.direct_len ,
152 1);
153 }
154 pm8001_ha->fatal_bar_loc +=
155 pm8001_ha->forensic_info.data_buf.direct_len;
156 pm8001_ha->forensic_info.data_buf.direct_offset +=
157 pm8001_ha->forensic_info.data_buf.direct_len;
158 pm8001_ha->forensic_last_offset +=
159 pm8001_ha->forensic_info.data_buf.direct_len;
160 pm8001_ha->forensic_info.data_buf.read_len =
161 pm8001_ha->forensic_info.data_buf.direct_len;
162
163 if (pm8001_ha->forensic_last_offset >= accum_len) {
164 pm8001_ha->forensic_info.data_buf.direct_data +=
165 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
166 "%08x ", 3);
167 for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
168 pm8001_ha->forensic_info.data_buf.direct_data +=
169 sprintf(pm8001_ha->
170 forensic_info.data_buf.direct_data,
171 "%08x ", *(temp + index));
172 }
173
174 pm8001_ha->fatal_bar_loc = 0;
175 pm8001_ha->forensic_fatal_step = 1;
176 pm8001_ha->fatal_forensic_shift_offset = 0;
177 pm8001_ha->forensic_last_offset = 0;
178 return (char *)pm8001_ha->
179 forensic_info.data_buf.direct_data -
180 (char *)buf;
181 }
182 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
183 pm8001_ha->forensic_info.data_buf.direct_data +=
184 sprintf(pm8001_ha->
185 forensic_info.data_buf.direct_data,
186 "%08x ", 2);
187 for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
188 pm8001_ha->forensic_info.data_buf.direct_data +=
189 sprintf(pm8001_ha->
190 forensic_info.data_buf.direct_data,
191 "%08x ", *(temp + index));
192 }
193 return (char *)pm8001_ha->
194 forensic_info.data_buf.direct_data -
195 (char *)buf;
196 }
197
198 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
199 pm8001_ha->forensic_info.data_buf.direct_data +=
200 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
201 "%08x ", 2);
202 for (index = 0; index < 256; index++) {
203 pm8001_ha->forensic_info.data_buf.direct_data +=
204 sprintf(pm8001_ha->
205 forensic_info.data_buf.direct_data,
206 "%08x ", *(temp + index));
207 }
208 pm8001_ha->fatal_forensic_shift_offset += 0x100;
209 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
210 pm8001_ha->fatal_forensic_shift_offset);
211 pm8001_ha->fatal_bar_loc = 0;
212 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
213 (char *)buf;
214 }
215 if (pm8001_ha->forensic_fatal_step == 1) {
216 pm8001_ha->fatal_forensic_shift_offset = 0;
217 /* Read 64K of the debug data. */
218 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
219 pm8001_ha->fatal_forensic_shift_offset);
220 pm8001_mw32(fatal_table_address,
221 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
222 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
223
224 /* Poll FDDHSHK until clear */
225 start = jiffies + (2 * HZ); /* 2 sec */
226
227 do {
228 reg_val = pm8001_mr32(fatal_table_address,
229 MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
230 } while ((reg_val) && time_before(jiffies, start));
231
232 if (reg_val != 0) {
233 PM8001_FAIL_DBG(pm8001_ha,
234 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
235 " = 0x%x\n", reg_val));
236 return -EIO;
237 }
238
239 /* Read the next 64K of the debug data. */
240 pm8001_ha->forensic_fatal_step = 0;
241 if (pm8001_mr32(fatal_table_address,
242 MPI_FATAL_EDUMP_TABLE_STATUS) !=
243 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
244 pm8001_mw32(fatal_table_address,
245 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 0);
246 goto moreData;
247 } else {
248 pm8001_ha->forensic_info.data_buf.direct_data +=
249 sprintf(pm8001_ha->
250 forensic_info.data_buf.direct_data,
251 "%08x ", 4);
252 pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
253 pm8001_ha->forensic_info.data_buf.direct_len = 0;
254 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
255 pm8001_ha->forensic_info.data_buf.read_len = 0;
256 }
257 }
258
259 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
260 (char *)buf;
261 }
262
263 /**
264 * read_main_config_table - read the configure table and save it.
265 * @pm8001_ha: our hba card information
266 */
267 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
268 {
269 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
270
271 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
272 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
273 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
274 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
275 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
276 pm8001_mr32(address, MAIN_FW_REVISION);
277 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
278 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
279 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
280 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
281 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
282 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
283 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
284 pm8001_mr32(address, MAIN_GST_OFFSET);
285 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
286 pm8001_mr32(address, MAIN_IBQ_OFFSET);
287 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
288 pm8001_mr32(address, MAIN_OBQ_OFFSET);
289
290 /* read Error Dump Offset and Length */
291 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
292 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
293 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
294 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
295 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
296 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
297 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
298 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
299
300 /* read GPIO LED settings from the configuration table */
301 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
302 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
303
304 /* read analog Setting offset from the configuration table */
305 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
306 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
307
308 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
309 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
310 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
311 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
312 /* read port recover and reset timeout */
313 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
314 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
315 }
316
317 /**
318 * read_general_status_table - read the general status table and save it.
319 * @pm8001_ha: our hba card information
320 */
321 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
322 {
323 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
324 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
325 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
326 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
327 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
328 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
329 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
330 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
331 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
332 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
333 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
334 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
335 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
336 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
337 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
338 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
339 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
340 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
341 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
342 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
343 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
344 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
345 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
346 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
347 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
348 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
349 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
350 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
351 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
352 }
353 /**
354 * read_phy_attr_table - read the phy attribute table and save it.
355 * @pm8001_ha: our hba card information
356 */
357 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
358 {
359 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
360 pm8001_ha->phy_attr_table.phystart1_16[0] =
361 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
362 pm8001_ha->phy_attr_table.phystart1_16[1] =
363 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
364 pm8001_ha->phy_attr_table.phystart1_16[2] =
365 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
366 pm8001_ha->phy_attr_table.phystart1_16[3] =
367 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
368 pm8001_ha->phy_attr_table.phystart1_16[4] =
369 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
370 pm8001_ha->phy_attr_table.phystart1_16[5] =
371 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
372 pm8001_ha->phy_attr_table.phystart1_16[6] =
373 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
374 pm8001_ha->phy_attr_table.phystart1_16[7] =
375 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
376 pm8001_ha->phy_attr_table.phystart1_16[8] =
377 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
378 pm8001_ha->phy_attr_table.phystart1_16[9] =
379 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
380 pm8001_ha->phy_attr_table.phystart1_16[10] =
381 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
382 pm8001_ha->phy_attr_table.phystart1_16[11] =
383 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
384 pm8001_ha->phy_attr_table.phystart1_16[12] =
385 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
386 pm8001_ha->phy_attr_table.phystart1_16[13] =
387 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
388 pm8001_ha->phy_attr_table.phystart1_16[14] =
389 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
390 pm8001_ha->phy_attr_table.phystart1_16[15] =
391 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
392
393 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
394 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
395 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
396 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
397 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
398 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
399 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
400 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
401 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
402 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
403 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
404 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
405 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
406 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
407 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
408 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
409 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
410 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
411 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
412 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
413 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
414 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
415 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
416 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
417 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
418 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
419 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
420 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
421 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
422 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
423 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
424 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
425
426 }
427
428 /**
429 * read_inbnd_queue_table - read the inbound queue table and save it.
430 * @pm8001_ha: our hba card information
431 */
432 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
433 {
434 int i;
435 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
436 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
437 u32 offset = i * 0x20;
438 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
439 get_pci_bar_index(pm8001_mr32(address,
440 (offset + IB_PIPCI_BAR)));
441 pm8001_ha->inbnd_q_tbl[i].pi_offset =
442 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
443 }
444 }
445
446 /**
447 * read_outbnd_queue_table - read the outbound queue table and save it.
448 * @pm8001_ha: our hba card information
449 */
450 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
451 {
452 int i;
453 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
454 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
455 u32 offset = i * 0x24;
456 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
457 get_pci_bar_index(pm8001_mr32(address,
458 (offset + OB_CIPCI_BAR)));
459 pm8001_ha->outbnd_q_tbl[i].ci_offset =
460 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
461 }
462 }
463
464 /**
465 * init_default_table_values - init the default table.
466 * @pm8001_ha: our hba card information
467 */
468 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
469 {
470 int i;
471 u32 offsetib, offsetob;
472 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
473 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
474
475 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
476 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
477 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
478 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
479 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
480 PM8001_EVENT_LOG_SIZE;
481 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
482 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
483 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
484 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
485 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
486 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
487 PM8001_EVENT_LOG_SIZE;
488 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
489 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
490
491 /* Disable end to end CRC checking */
492 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
493
494 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
495 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
496 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
497 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
498 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
499 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
500 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
501 pm8001_ha->inbnd_q_tbl[i].base_virt =
502 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
503 pm8001_ha->inbnd_q_tbl[i].total_length =
504 pm8001_ha->memoryMap.region[IB + i].total_len;
505 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
506 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
507 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
508 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
509 pm8001_ha->inbnd_q_tbl[i].ci_virt =
510 pm8001_ha->memoryMap.region[CI + i].virt_ptr;
511 offsetib = i * 0x20;
512 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
513 get_pci_bar_index(pm8001_mr32(addressib,
514 (offsetib + 0x14)));
515 pm8001_ha->inbnd_q_tbl[i].pi_offset =
516 pm8001_mr32(addressib, (offsetib + 0x18));
517 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
518 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
519 }
520 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
521 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
522 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
523 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
524 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
525 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
526 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
527 pm8001_ha->outbnd_q_tbl[i].base_virt =
528 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
529 pm8001_ha->outbnd_q_tbl[i].total_length =
530 pm8001_ha->memoryMap.region[OB + i].total_len;
531 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
532 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
533 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
534 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
535 /* interrupt vector based on oq */
536 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
537 pm8001_ha->outbnd_q_tbl[i].pi_virt =
538 pm8001_ha->memoryMap.region[PI + i].virt_ptr;
539 offsetob = i * 0x24;
540 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
541 get_pci_bar_index(pm8001_mr32(addressob,
542 offsetob + 0x14));
543 pm8001_ha->outbnd_q_tbl[i].ci_offset =
544 pm8001_mr32(addressob, (offsetob + 0x18));
545 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
546 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
547 }
548 }
549
550 /**
551 * update_main_config_table - update the main default table to the HBA.
552 * @pm8001_ha: our hba card information
553 */
554 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
555 {
556 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
557 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
558 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
559 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
560 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
561 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
562 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
563 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
564 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
565 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
566 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
567 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
568 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
569 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
570 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
571 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
572 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
573 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
574 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
575 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
576 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
577 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
578 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
579
580 /* SPCv specific */
581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
582 /* Set GPIOLED to 0x2 for LED indicator */
583 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
584 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
585 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
586
587 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
588 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
589 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
590 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
591
592 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
593 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
594 PORT_RECOVERY_TIMEOUT;
595 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
596 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
597 }
598
599 /**
600 * update_inbnd_queue_table - update the inbound queue table to the HBA.
601 * @pm8001_ha: our hba card information
602 */
603 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
604 int number)
605 {
606 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
607 u16 offset = number * 0x20;
608 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
609 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
610 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
611 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
612 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
613 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
614 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
615 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
616 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
617 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
618 }
619
620 /**
621 * update_outbnd_queue_table - update the outbound queue table to the HBA.
622 * @pm8001_ha: our hba card information
623 */
624 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
625 int number)
626 {
627 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
628 u16 offset = number * 0x24;
629 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
630 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
631 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
632 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
633 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
634 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
635 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
636 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
637 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
638 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
639 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
640 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
641 }
642
643 /**
644 * mpi_init_check - check firmware initialization status.
645 * @pm8001_ha: our hba card information
646 */
647 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
648 {
649 u32 max_wait_count;
650 u32 value;
651 u32 gst_len_mpistate;
652
653 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
654 table is updated */
655 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
656 /* wait until Inbound DoorBell Clear Register toggled */
657 if (IS_SPCV_12G(pm8001_ha->pdev)) {
658 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
659 } else {
660 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
661 }
662 do {
663 udelay(1);
664 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
665 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
666 } while ((value != 0) && (--max_wait_count));
667
668 if (!max_wait_count)
669 return -1;
670 /* check the MPI-State for initialization upto 100ms*/
671 max_wait_count = 100 * 1000;/* 100 msec */
672 do {
673 udelay(1);
674 gst_len_mpistate =
675 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
676 GST_GSTLEN_MPIS_OFFSET);
677 } while ((GST_MPI_STATE_INIT !=
678 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
679 if (!max_wait_count)
680 return -1;
681
682 /* check MPI Initialization error */
683 gst_len_mpistate = gst_len_mpistate >> 16;
684 if (0x0000 != gst_len_mpistate)
685 return -1;
686
687 return 0;
688 }
689
690 /**
691 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
692 * @pm8001_ha: our hba card information
693 */
694 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
695 {
696 u32 value;
697 u32 max_wait_count;
698 u32 max_wait_time;
699 int ret = 0;
700
701 /* reset / PCIe ready */
702 max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */
703 do {
704 udelay(1);
705 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
706 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
707
708 /* check ila status */
709 max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */
710 do {
711 udelay(1);
712 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
713 } while (((value & SCRATCH_PAD_ILA_READY) !=
714 SCRATCH_PAD_ILA_READY) && (--max_wait_count));
715 if (!max_wait_count)
716 ret = -1;
717 else {
718 PM8001_MSG_DBG(pm8001_ha,
719 pm8001_printk(" ila ready status in %d millisec\n",
720 (max_wait_time - max_wait_count)));
721 }
722
723 /* check RAAE status */
724 max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */
725 do {
726 udelay(1);
727 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
728 } while (((value & SCRATCH_PAD_RAAE_READY) !=
729 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
730 if (!max_wait_count)
731 ret = -1;
732 else {
733 PM8001_MSG_DBG(pm8001_ha,
734 pm8001_printk(" raae ready status in %d millisec\n",
735 (max_wait_time - max_wait_count)));
736 }
737
738 /* check iop0 status */
739 max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */
740 do {
741 udelay(1);
742 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
743 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
744 (--max_wait_count));
745 if (!max_wait_count)
746 ret = -1;
747 else {
748 PM8001_MSG_DBG(pm8001_ha,
749 pm8001_printk(" iop0 ready status in %d millisec\n",
750 (max_wait_time - max_wait_count)));
751 }
752
753 /* check iop1 status only for 16 port controllers */
754 if ((pm8001_ha->chip_id != chip_8008) &&
755 (pm8001_ha->chip_id != chip_8009)) {
756 /* 200 milli sec */
757 max_wait_time = max_wait_count = 200 * 1000;
758 do {
759 udelay(1);
760 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
761 } while (((value & SCRATCH_PAD_IOP1_READY) !=
762 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
763 if (!max_wait_count)
764 ret = -1;
765 else {
766 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
767 "iop1 ready status in %d millisec\n",
768 (max_wait_time - max_wait_count)));
769 }
770 }
771
772 return ret;
773 }
774
775 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
776 {
777 void __iomem *base_addr;
778 u32 value;
779 u32 offset;
780 u32 pcibar;
781 u32 pcilogic;
782
783 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
784 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
785
786 PM8001_INIT_DBG(pm8001_ha,
787 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
788 offset, value));
789 pcilogic = (value & 0xFC000000) >> 26;
790 pcibar = get_pci_bar_index(pcilogic);
791 PM8001_INIT_DBG(pm8001_ha,
792 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
793 pm8001_ha->main_cfg_tbl_addr = base_addr =
794 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
795 pm8001_ha->general_stat_tbl_addr =
796 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
797 0xFFFFFF);
798 pm8001_ha->inbnd_q_tbl_addr =
799 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
800 0xFFFFFF);
801 pm8001_ha->outbnd_q_tbl_addr =
802 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
803 0xFFFFFF);
804 pm8001_ha->ivt_tbl_addr =
805 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
806 0xFFFFFF);
807 pm8001_ha->pspa_q_tbl_addr =
808 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
809 0xFFFFFF);
810 pm8001_ha->fatal_tbl_addr =
811 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
812 0xFFFFFF);
813
814 PM8001_INIT_DBG(pm8001_ha,
815 pm8001_printk("GST OFFSET 0x%x\n",
816 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
817 PM8001_INIT_DBG(pm8001_ha,
818 pm8001_printk("INBND OFFSET 0x%x\n",
819 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
820 PM8001_INIT_DBG(pm8001_ha,
821 pm8001_printk("OBND OFFSET 0x%x\n",
822 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
823 PM8001_INIT_DBG(pm8001_ha,
824 pm8001_printk("IVT OFFSET 0x%x\n",
825 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
826 PM8001_INIT_DBG(pm8001_ha,
827 pm8001_printk("PSPA OFFSET 0x%x\n",
828 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
829 PM8001_INIT_DBG(pm8001_ha,
830 pm8001_printk("addr - main cfg %p general status %p\n",
831 pm8001_ha->main_cfg_tbl_addr,
832 pm8001_ha->general_stat_tbl_addr));
833 PM8001_INIT_DBG(pm8001_ha,
834 pm8001_printk("addr - inbnd %p obnd %p\n",
835 pm8001_ha->inbnd_q_tbl_addr,
836 pm8001_ha->outbnd_q_tbl_addr));
837 PM8001_INIT_DBG(pm8001_ha,
838 pm8001_printk("addr - pspa %p ivt %p\n",
839 pm8001_ha->pspa_q_tbl_addr,
840 pm8001_ha->ivt_tbl_addr));
841 }
842
843 /**
844 * pm80xx_set_thermal_config - support the thermal configuration
845 * @pm8001_ha: our hba card information.
846 */
847 int
848 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
849 {
850 struct set_ctrl_cfg_req payload;
851 struct inbound_queue_table *circularQ;
852 int rc;
853 u32 tag;
854 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
855 u32 page_code;
856
857 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
858 rc = pm8001_tag_alloc(pm8001_ha, &tag);
859 if (rc)
860 return -1;
861
862 circularQ = &pm8001_ha->inbnd_q_tbl[0];
863 payload.tag = cpu_to_le32(tag);
864
865 if (IS_SPCV_12G(pm8001_ha->pdev))
866 page_code = THERMAL_PAGE_CODE_7H;
867 else
868 page_code = THERMAL_PAGE_CODE_8H;
869
870 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
871 (THERMAL_ENABLE << 8) | page_code;
872 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
873
874 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
875 if (rc)
876 pm8001_tag_free(pm8001_ha, tag);
877 return rc;
878
879 }
880
881 /**
882 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
883 * Timer configuration page
884 * @pm8001_ha: our hba card information.
885 */
886 static int
887 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
888 {
889 struct set_ctrl_cfg_req payload;
890 struct inbound_queue_table *circularQ;
891 SASProtocolTimerConfig_t SASConfigPage;
892 int rc;
893 u32 tag;
894 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
895
896 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
897 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
898
899 rc = pm8001_tag_alloc(pm8001_ha, &tag);
900
901 if (rc)
902 return -1;
903
904 circularQ = &pm8001_ha->inbnd_q_tbl[0];
905 payload.tag = cpu_to_le32(tag);
906
907 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE;
908 SASConfigPage.MST_MSI = 3 << 15;
909 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO;
910 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) |
911 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
912 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME;
913
914 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
915 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
916
917
918 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) |
919 SAS_OPNRJT_RTRY_INTVL;
920 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16)
921 | SAS_COPNRJT_RTRY_TMO;
922 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16)
923 | SAS_COPNRJT_RTRY_THR;
924 SASConfigPage.MAX_AIP = SAS_MAX_AIP;
925
926 PM8001_INIT_DBG(pm8001_ha,
927 pm8001_printk("SASConfigPage.pageCode "
928 "0x%08x\n", SASConfigPage.pageCode));
929 PM8001_INIT_DBG(pm8001_ha,
930 pm8001_printk("SASConfigPage.MST_MSI "
931 " 0x%08x\n", SASConfigPage.MST_MSI));
932 PM8001_INIT_DBG(pm8001_ha,
933 pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
934 " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
935 PM8001_INIT_DBG(pm8001_ha,
936 pm8001_printk("SASConfigPage.STP_FRM_TMO "
937 " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
938 PM8001_INIT_DBG(pm8001_ha,
939 pm8001_printk("SASConfigPage.STP_IDLE_TMO "
940 " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
941 PM8001_INIT_DBG(pm8001_ha,
942 pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
943 " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
944 PM8001_INIT_DBG(pm8001_ha,
945 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
946 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
947 PM8001_INIT_DBG(pm8001_ha,
948 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
949 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
950 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
951 " 0x%08x\n", SASConfigPage.MAX_AIP));
952
953 memcpy(&payload.cfg_pg, &SASConfigPage,
954 sizeof(SASProtocolTimerConfig_t));
955
956 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
957 if (rc)
958 pm8001_tag_free(pm8001_ha, tag);
959
960 return rc;
961 }
962
963 /**
964 * pm80xx_get_encrypt_info - Check for encryption
965 * @pm8001_ha: our hba card information.
966 */
967 static int
968 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
969 {
970 u32 scratch3_value;
971 int ret = -1;
972
973 /* Read encryption status from SCRATCH PAD 3 */
974 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
975
976 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
977 SCRATCH_PAD3_ENC_READY) {
978 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
979 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
980 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
981 SCRATCH_PAD3_SMF_ENABLED)
982 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
983 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
984 SCRATCH_PAD3_SMA_ENABLED)
985 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
986 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
987 SCRATCH_PAD3_SMB_ENABLED)
988 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
989 pm8001_ha->encrypt_info.status = 0;
990 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
991 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
992 "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
993 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
994 pm8001_ha->encrypt_info.sec_mode,
995 pm8001_ha->encrypt_info.status));
996 ret = 0;
997 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
998 SCRATCH_PAD3_ENC_DISABLED) {
999 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1000 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1001 scratch3_value));
1002 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1003 pm8001_ha->encrypt_info.cipher_mode = 0;
1004 pm8001_ha->encrypt_info.sec_mode = 0;
1005 ret = 0;
1006 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1007 SCRATCH_PAD3_ENC_DIS_ERR) {
1008 pm8001_ha->encrypt_info.status =
1009 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1010 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1011 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1012 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1013 SCRATCH_PAD3_SMF_ENABLED)
1014 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1015 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1016 SCRATCH_PAD3_SMA_ENABLED)
1017 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1018 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1019 SCRATCH_PAD3_SMB_ENABLED)
1020 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1021 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1022 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
1023 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1024 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1025 pm8001_ha->encrypt_info.sec_mode,
1026 pm8001_ha->encrypt_info.status));
1027 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1028 SCRATCH_PAD3_ENC_ENA_ERR) {
1029
1030 pm8001_ha->encrypt_info.status =
1031 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1032 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1033 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1034 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1035 SCRATCH_PAD3_SMF_ENABLED)
1036 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1037 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1038 SCRATCH_PAD3_SMA_ENABLED)
1039 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1040 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1041 SCRATCH_PAD3_SMB_ENABLED)
1042 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1043
1044 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1045 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
1046 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1047 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1048 pm8001_ha->encrypt_info.sec_mode,
1049 pm8001_ha->encrypt_info.status));
1050 }
1051 return ret;
1052 }
1053
1054 /**
1055 * pm80xx_encrypt_update - update flash with encryption informtion
1056 * @pm8001_ha: our hba card information.
1057 */
1058 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1059 {
1060 struct kek_mgmt_req payload;
1061 struct inbound_queue_table *circularQ;
1062 int rc;
1063 u32 tag;
1064 u32 opc = OPC_INB_KEK_MANAGEMENT;
1065
1066 memset(&payload, 0, sizeof(struct kek_mgmt_req));
1067 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1068 if (rc)
1069 return -1;
1070
1071 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1072 payload.tag = cpu_to_le32(tag);
1073 /* Currently only one key is used. New KEK index is 1.
1074 * Current KEK index is 1. Store KEK to NVRAM is 1.
1075 */
1076 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
1077 KEK_MGMT_SUBOP_KEYCARDUPDATE);
1078
1079 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
1080 if (rc)
1081 pm8001_tag_free(pm8001_ha, tag);
1082
1083 return rc;
1084 }
1085
1086 /**
1087 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
1088 * @pm8001_ha: our hba card information
1089 */
1090 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1091 {
1092 int ret;
1093 u8 i = 0;
1094
1095 /* check the firmware status */
1096 if (-1 == check_fw_ready(pm8001_ha)) {
1097 PM8001_FAIL_DBG(pm8001_ha,
1098 pm8001_printk("Firmware is not ready!\n"));
1099 return -EBUSY;
1100 }
1101
1102 /* Initialize pci space address eg: mpi offset */
1103 init_pci_device_addresses(pm8001_ha);
1104 init_default_table_values(pm8001_ha);
1105 read_main_config_table(pm8001_ha);
1106 read_general_status_table(pm8001_ha);
1107 read_inbnd_queue_table(pm8001_ha);
1108 read_outbnd_queue_table(pm8001_ha);
1109 read_phy_attr_table(pm8001_ha);
1110
1111 /* update main config table ,inbound table and outbound table */
1112 update_main_config_table(pm8001_ha);
1113 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
1114 update_inbnd_queue_table(pm8001_ha, i);
1115 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
1116 update_outbnd_queue_table(pm8001_ha, i);
1117
1118 /* notify firmware update finished and check initialization status */
1119 if (0 == mpi_init_check(pm8001_ha)) {
1120 PM8001_INIT_DBG(pm8001_ha,
1121 pm8001_printk("MPI initialize successful!\n"));
1122 } else
1123 return -EBUSY;
1124
1125 /* send SAS protocol timer configuration page to FW */
1126 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1127
1128 /* Check for encryption */
1129 if (pm8001_ha->chip->encrypt) {
1130 PM8001_INIT_DBG(pm8001_ha,
1131 pm8001_printk("Checking for encryption\n"));
1132 ret = pm80xx_get_encrypt_info(pm8001_ha);
1133 if (ret == -1) {
1134 PM8001_INIT_DBG(pm8001_ha,
1135 pm8001_printk("Encryption error !!\n"));
1136 if (pm8001_ha->encrypt_info.status == 0x81) {
1137 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1138 "Encryption enabled with error."
1139 "Saving encryption key to flash\n"));
1140 pm80xx_encrypt_update(pm8001_ha);
1141 }
1142 }
1143 }
1144 return 0;
1145 }
1146
1147 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1148 {
1149 u32 max_wait_count;
1150 u32 value;
1151 u32 gst_len_mpistate;
1152 init_pci_device_addresses(pm8001_ha);
1153 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1154 table is stop */
1155 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1156
1157 /* wait until Inbound DoorBell Clear Register toggled */
1158 if (IS_SPCV_12G(pm8001_ha->pdev)) {
1159 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
1160 } else {
1161 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1162 }
1163 do {
1164 udelay(1);
1165 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1166 value &= SPCv_MSGU_CFG_TABLE_RESET;
1167 } while ((value != 0) && (--max_wait_count));
1168
1169 if (!max_wait_count) {
1170 PM8001_FAIL_DBG(pm8001_ha,
1171 pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
1172 return -1;
1173 }
1174
1175 /* check the MPI-State for termination in progress */
1176 /* wait until Inbound DoorBell Clear Register toggled */
1177 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
1178 do {
1179 udelay(1);
1180 gst_len_mpistate =
1181 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1182 GST_GSTLEN_MPIS_OFFSET);
1183 if (GST_MPI_STATE_UNINIT ==
1184 (gst_len_mpistate & GST_MPI_STATE_MASK))
1185 break;
1186 } while (--max_wait_count);
1187 if (!max_wait_count) {
1188 PM8001_FAIL_DBG(pm8001_ha,
1189 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
1190 gst_len_mpistate & GST_MPI_STATE_MASK));
1191 return -1;
1192 }
1193
1194 return 0;
1195 }
1196
1197 /**
1198 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
1199 * the FW register status to the originated status.
1200 * @pm8001_ha: our hba card information
1201 */
1202
1203 static int
1204 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1205 {
1206 u32 regval;
1207 u32 bootloader_state;
1208 u32 ibutton0, ibutton1;
1209
1210 /* Check if MPI is in ready state to reset */
1211 if (mpi_uninit_check(pm8001_ha) != 0) {
1212 PM8001_FAIL_DBG(pm8001_ha,
1213 pm8001_printk("MPI state is not ready\n"));
1214 return -1;
1215 }
1216
1217 /* checked for reset register normal state; 0x0 */
1218 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1219 PM8001_INIT_DBG(pm8001_ha,
1220 pm8001_printk("reset register before write : 0x%x\n", regval));
1221
1222 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1223 mdelay(500);
1224
1225 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1226 PM8001_INIT_DBG(pm8001_ha,
1227 pm8001_printk("reset register after write 0x%x\n", regval));
1228
1229 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1230 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1231 PM8001_MSG_DBG(pm8001_ha,
1232 pm8001_printk(" soft reset successful [regval: 0x%x]\n",
1233 regval));
1234 } else {
1235 PM8001_MSG_DBG(pm8001_ha,
1236 pm8001_printk(" soft reset failed [regval: 0x%x]\n",
1237 regval));
1238
1239 /* check bootloader is successfully executed or in HDA mode */
1240 bootloader_state =
1241 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1242 SCRATCH_PAD1_BOOTSTATE_MASK;
1243
1244 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1245 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1246 "Bootloader state - HDA mode SEEPROM\n"));
1247 } else if (bootloader_state ==
1248 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1249 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1250 "Bootloader state - HDA mode Bootstrap Pin\n"));
1251 } else if (bootloader_state ==
1252 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1253 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1254 "Bootloader state - HDA mode soft reset\n"));
1255 } else if (bootloader_state ==
1256 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1257 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1258 "Bootloader state-HDA mode critical error\n"));
1259 }
1260 return -EBUSY;
1261 }
1262
1263 /* check the firmware status after reset */
1264 if (-1 == check_fw_ready(pm8001_ha)) {
1265 PM8001_FAIL_DBG(pm8001_ha,
1266 pm8001_printk("Firmware is not ready!\n"));
1267 /* check iButton feature support for motherboard controller */
1268 if (pm8001_ha->pdev->subsystem_vendor !=
1269 PCI_VENDOR_ID_ADAPTEC2 &&
1270 pm8001_ha->pdev->subsystem_vendor !=
1271 PCI_VENDOR_ID_ATTO &&
1272 pm8001_ha->pdev->subsystem_vendor != 0) {
1273 ibutton0 = pm8001_cr32(pm8001_ha, 0,
1274 MSGU_HOST_SCRATCH_PAD_6);
1275 ibutton1 = pm8001_cr32(pm8001_ha, 0,
1276 MSGU_HOST_SCRATCH_PAD_7);
1277 if (!ibutton0 && !ibutton1) {
1278 PM8001_FAIL_DBG(pm8001_ha,
1279 pm8001_printk("iButton Feature is"
1280 " not Available!!!\n"));
1281 return -EBUSY;
1282 }
1283 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1284 PM8001_FAIL_DBG(pm8001_ha,
1285 pm8001_printk("CRC Check for iButton"
1286 " Feature Failed!!!\n"));
1287 return -EBUSY;
1288 }
1289 }
1290 }
1291 PM8001_INIT_DBG(pm8001_ha,
1292 pm8001_printk("SPCv soft reset Complete\n"));
1293 return 0;
1294 }
1295
1296 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1297 {
1298 u32 i;
1299
1300 PM8001_INIT_DBG(pm8001_ha,
1301 pm8001_printk("chip reset start\n"));
1302
1303 /* do SPCv chip reset. */
1304 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1305 PM8001_INIT_DBG(pm8001_ha,
1306 pm8001_printk("SPC soft reset Complete\n"));
1307
1308 /* Check this ..whether delay is required or no */
1309 /* delay 10 usec */
1310 udelay(10);
1311
1312 /* wait for 20 msec until the firmware gets reloaded */
1313 i = 20;
1314 do {
1315 mdelay(1);
1316 } while ((--i) != 0);
1317
1318 PM8001_INIT_DBG(pm8001_ha,
1319 pm8001_printk("chip reset finished\n"));
1320 }
1321
1322 /**
1323 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1324 * @pm8001_ha: our hba card information
1325 */
1326 static void
1327 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1328 {
1329 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1330 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1331 }
1332
1333 /**
1334 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1335 * @pm8001_ha: our hba card information
1336 */
1337 static void
1338 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1339 {
1340 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1341 }
1342
1343 /**
1344 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1345 * @pm8001_ha: our hba card information
1346 */
1347 static void
1348 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1349 {
1350 #ifdef PM8001_USE_MSIX
1351 u32 mask;
1352 mask = (u32)(1 << vec);
1353
1354 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1355 return;
1356 #endif
1357 pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1358
1359 }
1360
1361 /**
1362 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1363 * @pm8001_ha: our hba card information
1364 */
1365 static void
1366 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1367 {
1368 #ifdef PM8001_USE_MSIX
1369 u32 mask;
1370 if (vec == 0xFF)
1371 mask = 0xFFFFFFFF;
1372 else
1373 mask = (u32)(1 << vec);
1374 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1375 return;
1376 #endif
1377 pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1378 }
1379
1380 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1381 struct pm8001_device *pm8001_ha_dev)
1382 {
1383 int res;
1384 u32 ccb_tag;
1385 struct pm8001_ccb_info *ccb;
1386 struct sas_task *task = NULL;
1387 struct task_abort_req task_abort;
1388 struct inbound_queue_table *circularQ;
1389 u32 opc = OPC_INB_SATA_ABORT;
1390 int ret;
1391
1392 if (!pm8001_ha_dev) {
1393 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1394 return;
1395 }
1396
1397 task = sas_alloc_slow_task(GFP_ATOMIC);
1398
1399 if (!task) {
1400 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1401 "allocate task\n"));
1402 return;
1403 }
1404
1405 task->task_done = pm8001_task_done;
1406
1407 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1408 if (res) {
1409 sas_free_task(task);
1410 return;
1411 }
1412
1413 ccb = &pm8001_ha->ccb_info[ccb_tag];
1414 ccb->device = pm8001_ha_dev;
1415 ccb->ccb_tag = ccb_tag;
1416 ccb->task = task;
1417
1418 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1419
1420 memset(&task_abort, 0, sizeof(task_abort));
1421 task_abort.abort_all = cpu_to_le32(1);
1422 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1423 task_abort.tag = cpu_to_le32(ccb_tag);
1424
1425 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1426 if (ret) {
1427 sas_free_task(task);
1428 pm8001_tag_free(pm8001_ha, ccb_tag);
1429 }
1430 }
1431
1432 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1433 struct pm8001_device *pm8001_ha_dev)
1434 {
1435 struct sata_start_req sata_cmd;
1436 int res;
1437 u32 ccb_tag;
1438 struct pm8001_ccb_info *ccb;
1439 struct sas_task *task = NULL;
1440 struct host_to_dev_fis fis;
1441 struct domain_device *dev;
1442 struct inbound_queue_table *circularQ;
1443 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1444
1445 task = sas_alloc_slow_task(GFP_ATOMIC);
1446
1447 if (!task) {
1448 PM8001_FAIL_DBG(pm8001_ha,
1449 pm8001_printk("cannot allocate task !!!\n"));
1450 return;
1451 }
1452 task->task_done = pm8001_task_done;
1453
1454 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1455 if (res) {
1456 sas_free_task(task);
1457 PM8001_FAIL_DBG(pm8001_ha,
1458 pm8001_printk("cannot allocate tag !!!\n"));
1459 return;
1460 }
1461
1462 /* allocate domain device by ourselves as libsas
1463 * is not going to provide any
1464 */
1465 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1466 if (!dev) {
1467 sas_free_task(task);
1468 pm8001_tag_free(pm8001_ha, ccb_tag);
1469 PM8001_FAIL_DBG(pm8001_ha,
1470 pm8001_printk("Domain device cannot be allocated\n"));
1471 return;
1472 }
1473
1474 task->dev = dev;
1475 task->dev->lldd_dev = pm8001_ha_dev;
1476
1477 ccb = &pm8001_ha->ccb_info[ccb_tag];
1478 ccb->device = pm8001_ha_dev;
1479 ccb->ccb_tag = ccb_tag;
1480 ccb->task = task;
1481 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1482 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1483
1484 memset(&sata_cmd, 0, sizeof(sata_cmd));
1485 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1486
1487 /* construct read log FIS */
1488 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1489 fis.fis_type = 0x27;
1490 fis.flags = 0x80;
1491 fis.command = ATA_CMD_READ_LOG_EXT;
1492 fis.lbal = 0x10;
1493 fis.sector_count = 0x1;
1494
1495 sata_cmd.tag = cpu_to_le32(ccb_tag);
1496 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1497 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1498 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1499
1500 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1501 if (res) {
1502 sas_free_task(task);
1503 pm8001_tag_free(pm8001_ha, ccb_tag);
1504 kfree(dev);
1505 }
1506 }
1507
1508 /**
1509 * mpi_ssp_completion- process the event that FW response to the SSP request.
1510 * @pm8001_ha: our hba card information
1511 * @piomb: the message contents of this outbound message.
1512 *
1513 * When FW has completed a ssp request for example a IO request, after it has
1514 * filled the SG data with the data, it will trigger this event represent
1515 * that he has finished the job,please check the coresponding buffer.
1516 * So we will tell the caller who maybe waiting the result to tell upper layer
1517 * that the task has been finished.
1518 */
1519 static void
1520 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1521 {
1522 struct sas_task *t;
1523 struct pm8001_ccb_info *ccb;
1524 unsigned long flags;
1525 u32 status;
1526 u32 param;
1527 u32 tag;
1528 struct ssp_completion_resp *psspPayload;
1529 struct task_status_struct *ts;
1530 struct ssp_response_iu *iu;
1531 struct pm8001_device *pm8001_dev;
1532 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1533 status = le32_to_cpu(psspPayload->status);
1534 tag = le32_to_cpu(psspPayload->tag);
1535 ccb = &pm8001_ha->ccb_info[tag];
1536 if ((status == IO_ABORTED) && ccb->open_retry) {
1537 /* Being completed by another */
1538 ccb->open_retry = 0;
1539 return;
1540 }
1541 pm8001_dev = ccb->device;
1542 param = le32_to_cpu(psspPayload->param);
1543 t = ccb->task;
1544
1545 if (status && status != IO_UNDERFLOW)
1546 PM8001_FAIL_DBG(pm8001_ha,
1547 pm8001_printk("sas IO status 0x%x\n", status));
1548 if (unlikely(!t || !t->lldd_task || !t->dev))
1549 return;
1550 ts = &t->task_status;
1551 /* Print sas address of IO failed device */
1552 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1553 (status != IO_UNDERFLOW))
1554 PM8001_FAIL_DBG(pm8001_ha,
1555 pm8001_printk("SAS Address of IO Failure Drive"
1556 ":%016llx", SAS_ADDR(t->dev->sas_addr)));
1557
1558 switch (status) {
1559 case IO_SUCCESS:
1560 PM8001_IO_DBG(pm8001_ha,
1561 pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1562 param));
1563 if (param == 0) {
1564 ts->resp = SAS_TASK_COMPLETE;
1565 ts->stat = SAM_STAT_GOOD;
1566 } else {
1567 ts->resp = SAS_TASK_COMPLETE;
1568 ts->stat = SAS_PROTO_RESPONSE;
1569 ts->residual = param;
1570 iu = &psspPayload->ssp_resp_iu;
1571 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1572 }
1573 if (pm8001_dev)
1574 pm8001_dev->running_req--;
1575 break;
1576 case IO_ABORTED:
1577 PM8001_IO_DBG(pm8001_ha,
1578 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1579 ts->resp = SAS_TASK_COMPLETE;
1580 ts->stat = SAS_ABORTED_TASK;
1581 break;
1582 case IO_UNDERFLOW:
1583 /* SSP Completion with error */
1584 PM8001_IO_DBG(pm8001_ha,
1585 pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1586 param));
1587 ts->resp = SAS_TASK_COMPLETE;
1588 ts->stat = SAS_DATA_UNDERRUN;
1589 ts->residual = param;
1590 if (pm8001_dev)
1591 pm8001_dev->running_req--;
1592 break;
1593 case IO_NO_DEVICE:
1594 PM8001_IO_DBG(pm8001_ha,
1595 pm8001_printk("IO_NO_DEVICE\n"));
1596 ts->resp = SAS_TASK_UNDELIVERED;
1597 ts->stat = SAS_PHY_DOWN;
1598 break;
1599 case IO_XFER_ERROR_BREAK:
1600 PM8001_IO_DBG(pm8001_ha,
1601 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1602 ts->resp = SAS_TASK_COMPLETE;
1603 ts->stat = SAS_OPEN_REJECT;
1604 /* Force the midlayer to retry */
1605 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1606 break;
1607 case IO_XFER_ERROR_PHY_NOT_READY:
1608 PM8001_IO_DBG(pm8001_ha,
1609 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1610 ts->resp = SAS_TASK_COMPLETE;
1611 ts->stat = SAS_OPEN_REJECT;
1612 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1613 break;
1614 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
1615 PM8001_IO_DBG(pm8001_ha,
1616 pm8001_printk("IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"));
1617 ts->resp = SAS_TASK_COMPLETE;
1618 ts->stat = SAS_OPEN_REJECT;
1619 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1620 break;
1621 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1622 PM8001_IO_DBG(pm8001_ha,
1623 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1624 ts->resp = SAS_TASK_COMPLETE;
1625 ts->stat = SAS_OPEN_REJECT;
1626 ts->open_rej_reason = SAS_OREJ_EPROTO;
1627 break;
1628 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1629 PM8001_IO_DBG(pm8001_ha,
1630 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1631 ts->resp = SAS_TASK_COMPLETE;
1632 ts->stat = SAS_OPEN_REJECT;
1633 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1634 break;
1635 case IO_OPEN_CNX_ERROR_BREAK:
1636 PM8001_IO_DBG(pm8001_ha,
1637 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1638 ts->resp = SAS_TASK_COMPLETE;
1639 ts->stat = SAS_OPEN_REJECT;
1640 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1641 break;
1642 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1643 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1644 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1645 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1646 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1647 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1648 PM8001_IO_DBG(pm8001_ha,
1649 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1650 ts->resp = SAS_TASK_COMPLETE;
1651 ts->stat = SAS_OPEN_REJECT;
1652 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1653 if (!t->uldd_task)
1654 pm8001_handle_event(pm8001_ha,
1655 pm8001_dev,
1656 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1657 break;
1658 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1659 PM8001_IO_DBG(pm8001_ha,
1660 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1661 ts->resp = SAS_TASK_COMPLETE;
1662 ts->stat = SAS_OPEN_REJECT;
1663 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1664 break;
1665 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1666 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1667 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1668 ts->resp = SAS_TASK_COMPLETE;
1669 ts->stat = SAS_OPEN_REJECT;
1670 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1671 break;
1672 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1673 PM8001_IO_DBG(pm8001_ha,
1674 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1675 ts->resp = SAS_TASK_UNDELIVERED;
1676 ts->stat = SAS_OPEN_REJECT;
1677 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1678 break;
1679 case IO_XFER_ERROR_NAK_RECEIVED:
1680 PM8001_IO_DBG(pm8001_ha,
1681 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1682 ts->resp = SAS_TASK_COMPLETE;
1683 ts->stat = SAS_OPEN_REJECT;
1684 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1685 break;
1686 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1687 PM8001_IO_DBG(pm8001_ha,
1688 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1689 ts->resp = SAS_TASK_COMPLETE;
1690 ts->stat = SAS_NAK_R_ERR;
1691 break;
1692 case IO_XFER_ERROR_DMA:
1693 PM8001_IO_DBG(pm8001_ha,
1694 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1695 ts->resp = SAS_TASK_COMPLETE;
1696 ts->stat = SAS_OPEN_REJECT;
1697 break;
1698 case IO_XFER_OPEN_RETRY_TIMEOUT:
1699 PM8001_IO_DBG(pm8001_ha,
1700 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1701 ts->resp = SAS_TASK_COMPLETE;
1702 ts->stat = SAS_OPEN_REJECT;
1703 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1704 break;
1705 case IO_XFER_ERROR_OFFSET_MISMATCH:
1706 PM8001_IO_DBG(pm8001_ha,
1707 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1708 ts->resp = SAS_TASK_COMPLETE;
1709 ts->stat = SAS_OPEN_REJECT;
1710 break;
1711 case IO_PORT_IN_RESET:
1712 PM8001_IO_DBG(pm8001_ha,
1713 pm8001_printk("IO_PORT_IN_RESET\n"));
1714 ts->resp = SAS_TASK_COMPLETE;
1715 ts->stat = SAS_OPEN_REJECT;
1716 break;
1717 case IO_DS_NON_OPERATIONAL:
1718 PM8001_IO_DBG(pm8001_ha,
1719 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1720 ts->resp = SAS_TASK_COMPLETE;
1721 ts->stat = SAS_OPEN_REJECT;
1722 if (!t->uldd_task)
1723 pm8001_handle_event(pm8001_ha,
1724 pm8001_dev,
1725 IO_DS_NON_OPERATIONAL);
1726 break;
1727 case IO_DS_IN_RECOVERY:
1728 PM8001_IO_DBG(pm8001_ha,
1729 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1730 ts->resp = SAS_TASK_COMPLETE;
1731 ts->stat = SAS_OPEN_REJECT;
1732 break;
1733 case IO_TM_TAG_NOT_FOUND:
1734 PM8001_IO_DBG(pm8001_ha,
1735 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1736 ts->resp = SAS_TASK_COMPLETE;
1737 ts->stat = SAS_OPEN_REJECT;
1738 break;
1739 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1740 PM8001_IO_DBG(pm8001_ha,
1741 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1742 ts->resp = SAS_TASK_COMPLETE;
1743 ts->stat = SAS_OPEN_REJECT;
1744 break;
1745 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1746 PM8001_IO_DBG(pm8001_ha,
1747 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1748 ts->resp = SAS_TASK_COMPLETE;
1749 ts->stat = SAS_OPEN_REJECT;
1750 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1751 break;
1752 default:
1753 PM8001_IO_DBG(pm8001_ha,
1754 pm8001_printk("Unknown status 0x%x\n", status));
1755 /* not allowed case. Therefore, return failed status */
1756 ts->resp = SAS_TASK_COMPLETE;
1757 ts->stat = SAS_OPEN_REJECT;
1758 break;
1759 }
1760 PM8001_IO_DBG(pm8001_ha,
1761 pm8001_printk("scsi_status = 0x%x\n ",
1762 psspPayload->ssp_resp_iu.status));
1763 spin_lock_irqsave(&t->task_state_lock, flags);
1764 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1765 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1766 t->task_state_flags |= SAS_TASK_STATE_DONE;
1767 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1768 spin_unlock_irqrestore(&t->task_state_lock, flags);
1769 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1770 "task 0x%p done with io_status 0x%x resp 0x%x "
1771 "stat 0x%x but aborted by upper layer!\n",
1772 t, status, ts->resp, ts->stat));
1773 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1774 } else {
1775 spin_unlock_irqrestore(&t->task_state_lock, flags);
1776 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1777 mb();/* in order to force CPU ordering */
1778 t->task_done(t);
1779 }
1780 }
1781
1782 /*See the comments for mpi_ssp_completion */
1783 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1784 {
1785 struct sas_task *t;
1786 unsigned long flags;
1787 struct task_status_struct *ts;
1788 struct pm8001_ccb_info *ccb;
1789 struct pm8001_device *pm8001_dev;
1790 struct ssp_event_resp *psspPayload =
1791 (struct ssp_event_resp *)(piomb + 4);
1792 u32 event = le32_to_cpu(psspPayload->event);
1793 u32 tag = le32_to_cpu(psspPayload->tag);
1794 u32 port_id = le32_to_cpu(psspPayload->port_id);
1795
1796 ccb = &pm8001_ha->ccb_info[tag];
1797 t = ccb->task;
1798 pm8001_dev = ccb->device;
1799 if (event)
1800 PM8001_FAIL_DBG(pm8001_ha,
1801 pm8001_printk("sas IO status 0x%x\n", event));
1802 if (unlikely(!t || !t->lldd_task || !t->dev))
1803 return;
1804 ts = &t->task_status;
1805 PM8001_IO_DBG(pm8001_ha,
1806 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
1807 port_id, tag, event));
1808 switch (event) {
1809 case IO_OVERFLOW:
1810 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1811 ts->resp = SAS_TASK_COMPLETE;
1812 ts->stat = SAS_DATA_OVERRUN;
1813 ts->residual = 0;
1814 if (pm8001_dev)
1815 pm8001_dev->running_req--;
1816 break;
1817 case IO_XFER_ERROR_BREAK:
1818 PM8001_IO_DBG(pm8001_ha,
1819 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1820 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1821 return;
1822 case IO_XFER_ERROR_PHY_NOT_READY:
1823 PM8001_IO_DBG(pm8001_ha,
1824 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1825 ts->resp = SAS_TASK_COMPLETE;
1826 ts->stat = SAS_OPEN_REJECT;
1827 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1828 break;
1829 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1830 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1831 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1832 ts->resp = SAS_TASK_COMPLETE;
1833 ts->stat = SAS_OPEN_REJECT;
1834 ts->open_rej_reason = SAS_OREJ_EPROTO;
1835 break;
1836 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1837 PM8001_IO_DBG(pm8001_ha,
1838 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1839 ts->resp = SAS_TASK_COMPLETE;
1840 ts->stat = SAS_OPEN_REJECT;
1841 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1842 break;
1843 case IO_OPEN_CNX_ERROR_BREAK:
1844 PM8001_IO_DBG(pm8001_ha,
1845 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1846 ts->resp = SAS_TASK_COMPLETE;
1847 ts->stat = SAS_OPEN_REJECT;
1848 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1849 break;
1850 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1851 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1852 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1853 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1854 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1855 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1856 PM8001_IO_DBG(pm8001_ha,
1857 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1858 ts->resp = SAS_TASK_COMPLETE;
1859 ts->stat = SAS_OPEN_REJECT;
1860 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1861 if (!t->uldd_task)
1862 pm8001_handle_event(pm8001_ha,
1863 pm8001_dev,
1864 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1865 break;
1866 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1867 PM8001_IO_DBG(pm8001_ha,
1868 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1869 ts->resp = SAS_TASK_COMPLETE;
1870 ts->stat = SAS_OPEN_REJECT;
1871 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1872 break;
1873 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1874 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1875 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1876 ts->resp = SAS_TASK_COMPLETE;
1877 ts->stat = SAS_OPEN_REJECT;
1878 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1879 break;
1880 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1881 PM8001_IO_DBG(pm8001_ha,
1882 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1883 ts->resp = SAS_TASK_COMPLETE;
1884 ts->stat = SAS_OPEN_REJECT;
1885 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1886 break;
1887 case IO_XFER_ERROR_NAK_RECEIVED:
1888 PM8001_IO_DBG(pm8001_ha,
1889 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1890 ts->resp = SAS_TASK_COMPLETE;
1891 ts->stat = SAS_OPEN_REJECT;
1892 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1893 break;
1894 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1895 PM8001_IO_DBG(pm8001_ha,
1896 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1897 ts->resp = SAS_TASK_COMPLETE;
1898 ts->stat = SAS_NAK_R_ERR;
1899 break;
1900 case IO_XFER_OPEN_RETRY_TIMEOUT:
1901 PM8001_IO_DBG(pm8001_ha,
1902 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1903 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
1904 return;
1905 case IO_XFER_ERROR_UNEXPECTED_PHASE:
1906 PM8001_IO_DBG(pm8001_ha,
1907 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1908 ts->resp = SAS_TASK_COMPLETE;
1909 ts->stat = SAS_DATA_OVERRUN;
1910 break;
1911 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1912 PM8001_IO_DBG(pm8001_ha,
1913 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1914 ts->resp = SAS_TASK_COMPLETE;
1915 ts->stat = SAS_DATA_OVERRUN;
1916 break;
1917 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1918 PM8001_IO_DBG(pm8001_ha,
1919 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1920 ts->resp = SAS_TASK_COMPLETE;
1921 ts->stat = SAS_DATA_OVERRUN;
1922 break;
1923 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1924 PM8001_IO_DBG(pm8001_ha,
1925 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1926 ts->resp = SAS_TASK_COMPLETE;
1927 ts->stat = SAS_DATA_OVERRUN;
1928 break;
1929 case IO_XFER_ERROR_OFFSET_MISMATCH:
1930 PM8001_IO_DBG(pm8001_ha,
1931 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1932 ts->resp = SAS_TASK_COMPLETE;
1933 ts->stat = SAS_DATA_OVERRUN;
1934 break;
1935 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1936 PM8001_IO_DBG(pm8001_ha,
1937 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1938 ts->resp = SAS_TASK_COMPLETE;
1939 ts->stat = SAS_DATA_OVERRUN;
1940 break;
1941 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
1942 PM8001_IO_DBG(pm8001_ha,
1943 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
1944 /* TBC: used default set values */
1945 ts->resp = SAS_TASK_COMPLETE;
1946 ts->stat = SAS_DATA_OVERRUN;
1947 break;
1948 case IO_XFER_CMD_FRAME_ISSUED:
1949 PM8001_IO_DBG(pm8001_ha,
1950 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
1951 return;
1952 default:
1953 PM8001_IO_DBG(pm8001_ha,
1954 pm8001_printk("Unknown status 0x%x\n", event));
1955 /* not allowed case. Therefore, return failed status */
1956 ts->resp = SAS_TASK_COMPLETE;
1957 ts->stat = SAS_DATA_OVERRUN;
1958 break;
1959 }
1960 spin_lock_irqsave(&t->task_state_lock, flags);
1961 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1962 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1963 t->task_state_flags |= SAS_TASK_STATE_DONE;
1964 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1965 spin_unlock_irqrestore(&t->task_state_lock, flags);
1966 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1967 "task 0x%p done with event 0x%x resp 0x%x "
1968 "stat 0x%x but aborted by upper layer!\n",
1969 t, event, ts->resp, ts->stat));
1970 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1971 } else {
1972 spin_unlock_irqrestore(&t->task_state_lock, flags);
1973 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1974 mb();/* in order to force CPU ordering */
1975 t->task_done(t);
1976 }
1977 }
1978
1979 /*See the comments for mpi_ssp_completion */
1980 static void
1981 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1982 {
1983 struct sas_task *t;
1984 struct pm8001_ccb_info *ccb;
1985 u32 param;
1986 u32 status;
1987 u32 tag;
1988 int i, j;
1989 u8 sata_addr_low[4];
1990 u32 temp_sata_addr_low, temp_sata_addr_hi;
1991 u8 sata_addr_hi[4];
1992 struct sata_completion_resp *psataPayload;
1993 struct task_status_struct *ts;
1994 struct ata_task_resp *resp ;
1995 u32 *sata_resp;
1996 struct pm8001_device *pm8001_dev;
1997 unsigned long flags;
1998
1999 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2000 status = le32_to_cpu(psataPayload->status);
2001 tag = le32_to_cpu(psataPayload->tag);
2002
2003 if (!tag) {
2004 PM8001_FAIL_DBG(pm8001_ha,
2005 pm8001_printk("tag null\n"));
2006 return;
2007 }
2008 ccb = &pm8001_ha->ccb_info[tag];
2009 param = le32_to_cpu(psataPayload->param);
2010 if (ccb) {
2011 t = ccb->task;
2012 pm8001_dev = ccb->device;
2013 } else {
2014 PM8001_FAIL_DBG(pm8001_ha,
2015 pm8001_printk("ccb null\n"));
2016 return;
2017 }
2018
2019 if (t) {
2020 if (t->dev && (t->dev->lldd_dev))
2021 pm8001_dev = t->dev->lldd_dev;
2022 } else {
2023 PM8001_FAIL_DBG(pm8001_ha,
2024 pm8001_printk("task null\n"));
2025 return;
2026 }
2027
2028 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2029 && unlikely(!t || !t->lldd_task || !t->dev)) {
2030 PM8001_FAIL_DBG(pm8001_ha,
2031 pm8001_printk("task or dev null\n"));
2032 return;
2033 }
2034
2035 ts = &t->task_status;
2036 if (!ts) {
2037 PM8001_FAIL_DBG(pm8001_ha,
2038 pm8001_printk("ts null\n"));
2039 return;
2040 }
2041 /* Print sas address of IO failed device */
2042 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2043 (status != IO_UNDERFLOW)) {
2044 if (!((t->dev->parent) &&
2045 (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) {
2046 for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
2047 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2048 for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
2049 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2050 memcpy(&temp_sata_addr_low, sata_addr_low,
2051 sizeof(sata_addr_low));
2052 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2053 sizeof(sata_addr_hi));
2054 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2055 |((temp_sata_addr_hi << 8) &
2056 0xff0000) |
2057 ((temp_sata_addr_hi >> 8)
2058 & 0xff00) |
2059 ((temp_sata_addr_hi << 24) &
2060 0xff000000));
2061 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2062 & 0xff) |
2063 ((temp_sata_addr_low << 8)
2064 & 0xff0000) |
2065 ((temp_sata_addr_low >> 8)
2066 & 0xff00) |
2067 ((temp_sata_addr_low << 24)
2068 & 0xff000000)) +
2069 pm8001_dev->attached_phy +
2070 0x10);
2071 PM8001_FAIL_DBG(pm8001_ha,
2072 pm8001_printk("SAS Address of IO Failure Drive:"
2073 "%08x%08x", temp_sata_addr_hi,
2074 temp_sata_addr_low));
2075
2076 } else {
2077 PM8001_FAIL_DBG(pm8001_ha,
2078 pm8001_printk("SAS Address of IO Failure Drive:"
2079 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2080 }
2081 }
2082 switch (status) {
2083 case IO_SUCCESS:
2084 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2085 if (param == 0) {
2086 ts->resp = SAS_TASK_COMPLETE;
2087 ts->stat = SAM_STAT_GOOD;
2088 /* check if response is for SEND READ LOG */
2089 if (pm8001_dev &&
2090 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2091 /* set new bit for abort_all */
2092 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2093 /* clear bit for read log */
2094 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2095 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2096 /* Free the tag */
2097 pm8001_tag_free(pm8001_ha, tag);
2098 sas_free_task(t);
2099 return;
2100 }
2101 } else {
2102 u8 len;
2103 ts->resp = SAS_TASK_COMPLETE;
2104 ts->stat = SAS_PROTO_RESPONSE;
2105 ts->residual = param;
2106 PM8001_IO_DBG(pm8001_ha,
2107 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2108 param));
2109 sata_resp = &psataPayload->sata_resp[0];
2110 resp = (struct ata_task_resp *)ts->buf;
2111 if (t->ata_task.dma_xfer == 0 &&
2112 t->data_dir == PCI_DMA_FROMDEVICE) {
2113 len = sizeof(struct pio_setup_fis);
2114 PM8001_IO_DBG(pm8001_ha,
2115 pm8001_printk("PIO read len = %d\n", len));
2116 } else if (t->ata_task.use_ncq) {
2117 len = sizeof(struct set_dev_bits_fis);
2118 PM8001_IO_DBG(pm8001_ha,
2119 pm8001_printk("FPDMA len = %d\n", len));
2120 } else {
2121 len = sizeof(struct dev_to_host_fis);
2122 PM8001_IO_DBG(pm8001_ha,
2123 pm8001_printk("other len = %d\n", len));
2124 }
2125 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2126 resp->frame_len = len;
2127 memcpy(&resp->ending_fis[0], sata_resp, len);
2128 ts->buf_valid_size = sizeof(*resp);
2129 } else
2130 PM8001_IO_DBG(pm8001_ha,
2131 pm8001_printk("response to large\n"));
2132 }
2133 if (pm8001_dev)
2134 pm8001_dev->running_req--;
2135 break;
2136 case IO_ABORTED:
2137 PM8001_IO_DBG(pm8001_ha,
2138 pm8001_printk("IO_ABORTED IOMB Tag\n"));
2139 ts->resp = SAS_TASK_COMPLETE;
2140 ts->stat = SAS_ABORTED_TASK;
2141 if (pm8001_dev)
2142 pm8001_dev->running_req--;
2143 break;
2144 /* following cases are to do cases */
2145 case IO_UNDERFLOW:
2146 /* SATA Completion with error */
2147 PM8001_IO_DBG(pm8001_ha,
2148 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2149 ts->resp = SAS_TASK_COMPLETE;
2150 ts->stat = SAS_DATA_UNDERRUN;
2151 ts->residual = param;
2152 if (pm8001_dev)
2153 pm8001_dev->running_req--;
2154 break;
2155 case IO_NO_DEVICE:
2156 PM8001_IO_DBG(pm8001_ha,
2157 pm8001_printk("IO_NO_DEVICE\n"));
2158 ts->resp = SAS_TASK_UNDELIVERED;
2159 ts->stat = SAS_PHY_DOWN;
2160 break;
2161 case IO_XFER_ERROR_BREAK:
2162 PM8001_IO_DBG(pm8001_ha,
2163 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2164 ts->resp = SAS_TASK_COMPLETE;
2165 ts->stat = SAS_INTERRUPTED;
2166 break;
2167 case IO_XFER_ERROR_PHY_NOT_READY:
2168 PM8001_IO_DBG(pm8001_ha,
2169 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2170 ts->resp = SAS_TASK_COMPLETE;
2171 ts->stat = SAS_OPEN_REJECT;
2172 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2173 break;
2174 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2175 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2176 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2177 ts->resp = SAS_TASK_COMPLETE;
2178 ts->stat = SAS_OPEN_REJECT;
2179 ts->open_rej_reason = SAS_OREJ_EPROTO;
2180 break;
2181 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2182 PM8001_IO_DBG(pm8001_ha,
2183 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2184 ts->resp = SAS_TASK_COMPLETE;
2185 ts->stat = SAS_OPEN_REJECT;
2186 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2187 break;
2188 case IO_OPEN_CNX_ERROR_BREAK:
2189 PM8001_IO_DBG(pm8001_ha,
2190 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2191 ts->resp = SAS_TASK_COMPLETE;
2192 ts->stat = SAS_OPEN_REJECT;
2193 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2194 break;
2195 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2196 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2197 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2198 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2199 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2200 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2201 PM8001_IO_DBG(pm8001_ha,
2202 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2203 ts->resp = SAS_TASK_COMPLETE;
2204 ts->stat = SAS_DEV_NO_RESPONSE;
2205 if (!t->uldd_task) {
2206 pm8001_handle_event(pm8001_ha,
2207 pm8001_dev,
2208 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2209 ts->resp = SAS_TASK_UNDELIVERED;
2210 ts->stat = SAS_QUEUE_FULL;
2211 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2212 return;
2213 }
2214 break;
2215 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2216 PM8001_IO_DBG(pm8001_ha,
2217 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2218 ts->resp = SAS_TASK_UNDELIVERED;
2219 ts->stat = SAS_OPEN_REJECT;
2220 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2221 if (!t->uldd_task) {
2222 pm8001_handle_event(pm8001_ha,
2223 pm8001_dev,
2224 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2225 ts->resp = SAS_TASK_UNDELIVERED;
2226 ts->stat = SAS_QUEUE_FULL;
2227 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2228 return;
2229 }
2230 break;
2231 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2232 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2233 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2234 ts->resp = SAS_TASK_COMPLETE;
2235 ts->stat = SAS_OPEN_REJECT;
2236 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2237 break;
2238 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2239 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2240 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
2241 ts->resp = SAS_TASK_COMPLETE;
2242 ts->stat = SAS_DEV_NO_RESPONSE;
2243 if (!t->uldd_task) {
2244 pm8001_handle_event(pm8001_ha,
2245 pm8001_dev,
2246 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2247 ts->resp = SAS_TASK_UNDELIVERED;
2248 ts->stat = SAS_QUEUE_FULL;
2249 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2250 return;
2251 }
2252 break;
2253 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2254 PM8001_IO_DBG(pm8001_ha,
2255 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2256 ts->resp = SAS_TASK_COMPLETE;
2257 ts->stat = SAS_OPEN_REJECT;
2258 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2259 break;
2260 case IO_XFER_ERROR_NAK_RECEIVED:
2261 PM8001_IO_DBG(pm8001_ha,
2262 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2263 ts->resp = SAS_TASK_COMPLETE;
2264 ts->stat = SAS_NAK_R_ERR;
2265 break;
2266 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2267 PM8001_IO_DBG(pm8001_ha,
2268 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2269 ts->resp = SAS_TASK_COMPLETE;
2270 ts->stat = SAS_NAK_R_ERR;
2271 break;
2272 case IO_XFER_ERROR_DMA:
2273 PM8001_IO_DBG(pm8001_ha,
2274 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2275 ts->resp = SAS_TASK_COMPLETE;
2276 ts->stat = SAS_ABORTED_TASK;
2277 break;
2278 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2279 PM8001_IO_DBG(pm8001_ha,
2280 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2281 ts->resp = SAS_TASK_UNDELIVERED;
2282 ts->stat = SAS_DEV_NO_RESPONSE;
2283 break;
2284 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2285 PM8001_IO_DBG(pm8001_ha,
2286 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2287 ts->resp = SAS_TASK_COMPLETE;
2288 ts->stat = SAS_DATA_UNDERRUN;
2289 break;
2290 case IO_XFER_OPEN_RETRY_TIMEOUT:
2291 PM8001_IO_DBG(pm8001_ha,
2292 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2293 ts->resp = SAS_TASK_COMPLETE;
2294 ts->stat = SAS_OPEN_TO;
2295 break;
2296 case IO_PORT_IN_RESET:
2297 PM8001_IO_DBG(pm8001_ha,
2298 pm8001_printk("IO_PORT_IN_RESET\n"));
2299 ts->resp = SAS_TASK_COMPLETE;
2300 ts->stat = SAS_DEV_NO_RESPONSE;
2301 break;
2302 case IO_DS_NON_OPERATIONAL:
2303 PM8001_IO_DBG(pm8001_ha,
2304 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2305 ts->resp = SAS_TASK_COMPLETE;
2306 ts->stat = SAS_DEV_NO_RESPONSE;
2307 if (!t->uldd_task) {
2308 pm8001_handle_event(pm8001_ha, pm8001_dev,
2309 IO_DS_NON_OPERATIONAL);
2310 ts->resp = SAS_TASK_UNDELIVERED;
2311 ts->stat = SAS_QUEUE_FULL;
2312 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2313 return;
2314 }
2315 break;
2316 case IO_DS_IN_RECOVERY:
2317 PM8001_IO_DBG(pm8001_ha,
2318 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2319 ts->resp = SAS_TASK_COMPLETE;
2320 ts->stat = SAS_DEV_NO_RESPONSE;
2321 break;
2322 case IO_DS_IN_ERROR:
2323 PM8001_IO_DBG(pm8001_ha,
2324 pm8001_printk("IO_DS_IN_ERROR\n"));
2325 ts->resp = SAS_TASK_COMPLETE;
2326 ts->stat = SAS_DEV_NO_RESPONSE;
2327 if (!t->uldd_task) {
2328 pm8001_handle_event(pm8001_ha, pm8001_dev,
2329 IO_DS_IN_ERROR);
2330 ts->resp = SAS_TASK_UNDELIVERED;
2331 ts->stat = SAS_QUEUE_FULL;
2332 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2333 return;
2334 }
2335 break;
2336 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2337 PM8001_IO_DBG(pm8001_ha,
2338 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2339 ts->resp = SAS_TASK_COMPLETE;
2340 ts->stat = SAS_OPEN_REJECT;
2341 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2342 break;
2343 default:
2344 PM8001_IO_DBG(pm8001_ha,
2345 pm8001_printk("Unknown status 0x%x\n", status));
2346 /* not allowed case. Therefore, return failed status */
2347 ts->resp = SAS_TASK_COMPLETE;
2348 ts->stat = SAS_DEV_NO_RESPONSE;
2349 break;
2350 }
2351 spin_lock_irqsave(&t->task_state_lock, flags);
2352 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2353 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2354 t->task_state_flags |= SAS_TASK_STATE_DONE;
2355 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2356 spin_unlock_irqrestore(&t->task_state_lock, flags);
2357 PM8001_FAIL_DBG(pm8001_ha,
2358 pm8001_printk("task 0x%p done with io_status 0x%x"
2359 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2360 t, status, ts->resp, ts->stat));
2361 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2362 } else {
2363 spin_unlock_irqrestore(&t->task_state_lock, flags);
2364 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2365 }
2366 }
2367
2368 /*See the comments for mpi_ssp_completion */
2369 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2370 {
2371 struct sas_task *t;
2372 struct task_status_struct *ts;
2373 struct pm8001_ccb_info *ccb;
2374 struct pm8001_device *pm8001_dev;
2375 struct sata_event_resp *psataPayload =
2376 (struct sata_event_resp *)(piomb + 4);
2377 u32 event = le32_to_cpu(psataPayload->event);
2378 u32 tag = le32_to_cpu(psataPayload->tag);
2379 u32 port_id = le32_to_cpu(psataPayload->port_id);
2380 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2381 unsigned long flags;
2382
2383 ccb = &pm8001_ha->ccb_info[tag];
2384
2385 if (ccb) {
2386 t = ccb->task;
2387 pm8001_dev = ccb->device;
2388 } else {
2389 PM8001_FAIL_DBG(pm8001_ha,
2390 pm8001_printk("No CCB !!!. returning\n"));
2391 return;
2392 }
2393 if (event)
2394 PM8001_FAIL_DBG(pm8001_ha,
2395 pm8001_printk("SATA EVENT 0x%x\n", event));
2396
2397 /* Check if this is NCQ error */
2398 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2399 /* find device using device id */
2400 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2401 /* send read log extension */
2402 if (pm8001_dev)
2403 pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2404 return;
2405 }
2406
2407 if (unlikely(!t || !t->lldd_task || !t->dev)) {
2408 PM8001_FAIL_DBG(pm8001_ha,
2409 pm8001_printk("task or dev null\n"));
2410 return;
2411 }
2412
2413 ts = &t->task_status;
2414 PM8001_IO_DBG(pm8001_ha,
2415 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2416 port_id, tag, event));
2417 switch (event) {
2418 case IO_OVERFLOW:
2419 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2420 ts->resp = SAS_TASK_COMPLETE;
2421 ts->stat = SAS_DATA_OVERRUN;
2422 ts->residual = 0;
2423 if (pm8001_dev)
2424 pm8001_dev->running_req--;
2425 break;
2426 case IO_XFER_ERROR_BREAK:
2427 PM8001_IO_DBG(pm8001_ha,
2428 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2429 ts->resp = SAS_TASK_COMPLETE;
2430 ts->stat = SAS_INTERRUPTED;
2431 break;
2432 case IO_XFER_ERROR_PHY_NOT_READY:
2433 PM8001_IO_DBG(pm8001_ha,
2434 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2435 ts->resp = SAS_TASK_COMPLETE;
2436 ts->stat = SAS_OPEN_REJECT;
2437 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2438 break;
2439 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2440 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2441 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2442 ts->resp = SAS_TASK_COMPLETE;
2443 ts->stat = SAS_OPEN_REJECT;
2444 ts->open_rej_reason = SAS_OREJ_EPROTO;
2445 break;
2446 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2447 PM8001_IO_DBG(pm8001_ha,
2448 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2449 ts->resp = SAS_TASK_COMPLETE;
2450 ts->stat = SAS_OPEN_REJECT;
2451 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2452 break;
2453 case IO_OPEN_CNX_ERROR_BREAK:
2454 PM8001_IO_DBG(pm8001_ha,
2455 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2456 ts->resp = SAS_TASK_COMPLETE;
2457 ts->stat = SAS_OPEN_REJECT;
2458 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2459 break;
2460 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2461 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2462 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2463 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2464 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2465 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2466 PM8001_FAIL_DBG(pm8001_ha,
2467 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2468 ts->resp = SAS_TASK_UNDELIVERED;
2469 ts->stat = SAS_DEV_NO_RESPONSE;
2470 if (!t->uldd_task) {
2471 pm8001_handle_event(pm8001_ha,
2472 pm8001_dev,
2473 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2474 ts->resp = SAS_TASK_COMPLETE;
2475 ts->stat = SAS_QUEUE_FULL;
2476 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2477 return;
2478 }
2479 break;
2480 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2481 PM8001_IO_DBG(pm8001_ha,
2482 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2483 ts->resp = SAS_TASK_UNDELIVERED;
2484 ts->stat = SAS_OPEN_REJECT;
2485 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2486 break;
2487 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2488 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2489 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2490 ts->resp = SAS_TASK_COMPLETE;
2491 ts->stat = SAS_OPEN_REJECT;
2492 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2493 break;
2494 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2495 PM8001_IO_DBG(pm8001_ha,
2496 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2497 ts->resp = SAS_TASK_COMPLETE;
2498 ts->stat = SAS_OPEN_REJECT;
2499 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2500 break;
2501 case IO_XFER_ERROR_NAK_RECEIVED:
2502 PM8001_IO_DBG(pm8001_ha,
2503 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2504 ts->resp = SAS_TASK_COMPLETE;
2505 ts->stat = SAS_NAK_R_ERR;
2506 break;
2507 case IO_XFER_ERROR_PEER_ABORTED:
2508 PM8001_IO_DBG(pm8001_ha,
2509 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2510 ts->resp = SAS_TASK_COMPLETE;
2511 ts->stat = SAS_NAK_R_ERR;
2512 break;
2513 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2514 PM8001_IO_DBG(pm8001_ha,
2515 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2516 ts->resp = SAS_TASK_COMPLETE;
2517 ts->stat = SAS_DATA_UNDERRUN;
2518 break;
2519 case IO_XFER_OPEN_RETRY_TIMEOUT:
2520 PM8001_IO_DBG(pm8001_ha,
2521 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2522 ts->resp = SAS_TASK_COMPLETE;
2523 ts->stat = SAS_OPEN_TO;
2524 break;
2525 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2526 PM8001_IO_DBG(pm8001_ha,
2527 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2528 ts->resp = SAS_TASK_COMPLETE;
2529 ts->stat = SAS_OPEN_TO;
2530 break;
2531 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2532 PM8001_IO_DBG(pm8001_ha,
2533 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2534 ts->resp = SAS_TASK_COMPLETE;
2535 ts->stat = SAS_OPEN_TO;
2536 break;
2537 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2538 PM8001_IO_DBG(pm8001_ha,
2539 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2540 ts->resp = SAS_TASK_COMPLETE;
2541 ts->stat = SAS_OPEN_TO;
2542 break;
2543 case IO_XFER_ERROR_OFFSET_MISMATCH:
2544 PM8001_IO_DBG(pm8001_ha,
2545 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2546 ts->resp = SAS_TASK_COMPLETE;
2547 ts->stat = SAS_OPEN_TO;
2548 break;
2549 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2550 PM8001_IO_DBG(pm8001_ha,
2551 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2552 ts->resp = SAS_TASK_COMPLETE;
2553 ts->stat = SAS_OPEN_TO;
2554 break;
2555 case IO_XFER_CMD_FRAME_ISSUED:
2556 PM8001_IO_DBG(pm8001_ha,
2557 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2558 break;
2559 case IO_XFER_PIO_SETUP_ERROR:
2560 PM8001_IO_DBG(pm8001_ha,
2561 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2562 ts->resp = SAS_TASK_COMPLETE;
2563 ts->stat = SAS_OPEN_TO;
2564 break;
2565 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2566 PM8001_FAIL_DBG(pm8001_ha,
2567 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2568 /* TBC: used default set values */
2569 ts->resp = SAS_TASK_COMPLETE;
2570 ts->stat = SAS_OPEN_TO;
2571 break;
2572 case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2573 PM8001_FAIL_DBG(pm8001_ha,
2574 pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2575 /* TBC: used default set values */
2576 ts->resp = SAS_TASK_COMPLETE;
2577 ts->stat = SAS_OPEN_TO;
2578 break;
2579 default:
2580 PM8001_IO_DBG(pm8001_ha,
2581 pm8001_printk("Unknown status 0x%x\n", event));
2582 /* not allowed case. Therefore, return failed status */
2583 ts->resp = SAS_TASK_COMPLETE;
2584 ts->stat = SAS_OPEN_TO;
2585 break;
2586 }
2587 spin_lock_irqsave(&t->task_state_lock, flags);
2588 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2589 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2590 t->task_state_flags |= SAS_TASK_STATE_DONE;
2591 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2592 spin_unlock_irqrestore(&t->task_state_lock, flags);
2593 PM8001_FAIL_DBG(pm8001_ha,
2594 pm8001_printk("task 0x%p done with io_status 0x%x"
2595 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2596 t, event, ts->resp, ts->stat));
2597 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2598 } else {
2599 spin_unlock_irqrestore(&t->task_state_lock, flags);
2600 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2601 }
2602 }
2603
2604 /*See the comments for mpi_ssp_completion */
2605 static void
2606 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2607 {
2608 u32 param, i;
2609 struct sas_task *t;
2610 struct pm8001_ccb_info *ccb;
2611 unsigned long flags;
2612 u32 status;
2613 u32 tag;
2614 struct smp_completion_resp *psmpPayload;
2615 struct task_status_struct *ts;
2616 struct pm8001_device *pm8001_dev;
2617 char *pdma_respaddr = NULL;
2618
2619 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2620 status = le32_to_cpu(psmpPayload->status);
2621 tag = le32_to_cpu(psmpPayload->tag);
2622
2623 ccb = &pm8001_ha->ccb_info[tag];
2624 param = le32_to_cpu(psmpPayload->param);
2625 t = ccb->task;
2626 ts = &t->task_status;
2627 pm8001_dev = ccb->device;
2628 if (status)
2629 PM8001_FAIL_DBG(pm8001_ha,
2630 pm8001_printk("smp IO status 0x%x\n", status));
2631 if (unlikely(!t || !t->lldd_task || !t->dev))
2632 return;
2633
2634 switch (status) {
2635
2636 case IO_SUCCESS:
2637 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2638 ts->resp = SAS_TASK_COMPLETE;
2639 ts->stat = SAM_STAT_GOOD;
2640 if (pm8001_dev)
2641 pm8001_dev->running_req--;
2642 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2643 PM8001_IO_DBG(pm8001_ha,
2644 pm8001_printk("DIRECT RESPONSE Length:%d\n",
2645 param));
2646 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2647 ((u64)sg_dma_address
2648 (&t->smp_task.smp_resp))));
2649 for (i = 0; i < param; i++) {
2650 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
2651 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2652 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2653 i, *(pdma_respaddr+i),
2654 psmpPayload->_r_a[i]));
2655 }
2656 }
2657 break;
2658 case IO_ABORTED:
2659 PM8001_IO_DBG(pm8001_ha,
2660 pm8001_printk("IO_ABORTED IOMB\n"));
2661 ts->resp = SAS_TASK_COMPLETE;
2662 ts->stat = SAS_ABORTED_TASK;
2663 if (pm8001_dev)
2664 pm8001_dev->running_req--;
2665 break;
2666 case IO_OVERFLOW:
2667 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2668 ts->resp = SAS_TASK_COMPLETE;
2669 ts->stat = SAS_DATA_OVERRUN;
2670 ts->residual = 0;
2671 if (pm8001_dev)
2672 pm8001_dev->running_req--;
2673 break;
2674 case IO_NO_DEVICE:
2675 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2676 ts->resp = SAS_TASK_COMPLETE;
2677 ts->stat = SAS_PHY_DOWN;
2678 break;
2679 case IO_ERROR_HW_TIMEOUT:
2680 PM8001_IO_DBG(pm8001_ha,
2681 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2682 ts->resp = SAS_TASK_COMPLETE;
2683 ts->stat = SAM_STAT_BUSY;
2684 break;
2685 case IO_XFER_ERROR_BREAK:
2686 PM8001_IO_DBG(pm8001_ha,
2687 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2688 ts->resp = SAS_TASK_COMPLETE;
2689 ts->stat = SAM_STAT_BUSY;
2690 break;
2691 case IO_XFER_ERROR_PHY_NOT_READY:
2692 PM8001_IO_DBG(pm8001_ha,
2693 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2694 ts->resp = SAS_TASK_COMPLETE;
2695 ts->stat = SAM_STAT_BUSY;
2696 break;
2697 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2698 PM8001_IO_DBG(pm8001_ha,
2699 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2700 ts->resp = SAS_TASK_COMPLETE;
2701 ts->stat = SAS_OPEN_REJECT;
2702 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2703 break;
2704 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2705 PM8001_IO_DBG(pm8001_ha,
2706 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2707 ts->resp = SAS_TASK_COMPLETE;
2708 ts->stat = SAS_OPEN_REJECT;
2709 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2710 break;
2711 case IO_OPEN_CNX_ERROR_BREAK:
2712 PM8001_IO_DBG(pm8001_ha,
2713 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2714 ts->resp = SAS_TASK_COMPLETE;
2715 ts->stat = SAS_OPEN_REJECT;
2716 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2717 break;
2718 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2719 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2720 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2721 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2722 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2723 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2724 PM8001_IO_DBG(pm8001_ha,
2725 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2726 ts->resp = SAS_TASK_COMPLETE;
2727 ts->stat = SAS_OPEN_REJECT;
2728 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2729 pm8001_handle_event(pm8001_ha,
2730 pm8001_dev,
2731 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2732 break;
2733 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2734 PM8001_IO_DBG(pm8001_ha,
2735 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2736 ts->resp = SAS_TASK_COMPLETE;
2737 ts->stat = SAS_OPEN_REJECT;
2738 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2739 break;
2740 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2741 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
2742 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2743 ts->resp = SAS_TASK_COMPLETE;
2744 ts->stat = SAS_OPEN_REJECT;
2745 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2746 break;
2747 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2748 PM8001_IO_DBG(pm8001_ha,
2749 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2750 ts->resp = SAS_TASK_COMPLETE;
2751 ts->stat = SAS_OPEN_REJECT;
2752 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2753 break;
2754 case IO_XFER_ERROR_RX_FRAME:
2755 PM8001_IO_DBG(pm8001_ha,
2756 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2757 ts->resp = SAS_TASK_COMPLETE;
2758 ts->stat = SAS_DEV_NO_RESPONSE;
2759 break;
2760 case IO_XFER_OPEN_RETRY_TIMEOUT:
2761 PM8001_IO_DBG(pm8001_ha,
2762 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2763 ts->resp = SAS_TASK_COMPLETE;
2764 ts->stat = SAS_OPEN_REJECT;
2765 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2766 break;
2767 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2768 PM8001_IO_DBG(pm8001_ha,
2769 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2770 ts->resp = SAS_TASK_COMPLETE;
2771 ts->stat = SAS_QUEUE_FULL;
2772 break;
2773 case IO_PORT_IN_RESET:
2774 PM8001_IO_DBG(pm8001_ha,
2775 pm8001_printk("IO_PORT_IN_RESET\n"));
2776 ts->resp = SAS_TASK_COMPLETE;
2777 ts->stat = SAS_OPEN_REJECT;
2778 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2779 break;
2780 case IO_DS_NON_OPERATIONAL:
2781 PM8001_IO_DBG(pm8001_ha,
2782 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2783 ts->resp = SAS_TASK_COMPLETE;
2784 ts->stat = SAS_DEV_NO_RESPONSE;
2785 break;
2786 case IO_DS_IN_RECOVERY:
2787 PM8001_IO_DBG(pm8001_ha,
2788 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2789 ts->resp = SAS_TASK_COMPLETE;
2790 ts->stat = SAS_OPEN_REJECT;
2791 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2792 break;
2793 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2794 PM8001_IO_DBG(pm8001_ha,
2795 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2796 ts->resp = SAS_TASK_COMPLETE;
2797 ts->stat = SAS_OPEN_REJECT;
2798 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2799 break;
2800 default:
2801 PM8001_IO_DBG(pm8001_ha,
2802 pm8001_printk("Unknown status 0x%x\n", status));
2803 ts->resp = SAS_TASK_COMPLETE;
2804 ts->stat = SAS_DEV_NO_RESPONSE;
2805 /* not allowed case. Therefore, return failed status */
2806 break;
2807 }
2808 spin_lock_irqsave(&t->task_state_lock, flags);
2809 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2810 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2811 t->task_state_flags |= SAS_TASK_STATE_DONE;
2812 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2813 spin_unlock_irqrestore(&t->task_state_lock, flags);
2814 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2815 "task 0x%p done with io_status 0x%x resp 0x%x"
2816 "stat 0x%x but aborted by upper layer!\n",
2817 t, status, ts->resp, ts->stat));
2818 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2819 } else {
2820 spin_unlock_irqrestore(&t->task_state_lock, flags);
2821 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2822 mb();/* in order to force CPU ordering */
2823 t->task_done(t);
2824 }
2825 }
2826
2827 /**
2828 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2829 * @pm8001_ha: our hba card information
2830 * @Qnum: the outbound queue message number.
2831 * @SEA: source of event to ack
2832 * @port_id: port id.
2833 * @phyId: phy id.
2834 * @param0: parameter 0.
2835 * @param1: parameter 1.
2836 */
2837 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2838 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2839 {
2840 struct hw_event_ack_req payload;
2841 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2842
2843 struct inbound_queue_table *circularQ;
2844
2845 memset((u8 *)&payload, 0, sizeof(payload));
2846 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2847 payload.tag = cpu_to_le32(1);
2848 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2849 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
2850 payload.param0 = cpu_to_le32(param0);
2851 payload.param1 = cpu_to_le32(param1);
2852 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
2853 }
2854
2855 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2856 u32 phyId, u32 phy_op);
2857
2858 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
2859 void *piomb)
2860 {
2861 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
2862 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2863 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2864 u32 lr_status_evt_portid =
2865 le32_to_cpu(pPayload->lr_status_evt_portid);
2866 u8 deviceType = pPayload->sas_identify.dev_type;
2867 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2868 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2869 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2870 struct pm8001_port *port = &pm8001_ha->port[port_id];
2871
2872 if (deviceType == SAS_END_DEVICE) {
2873 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2874 PHY_NOTIFY_ENABLE_SPINUP);
2875 }
2876
2877 port->wide_port_phymap |= (1U << phy_id);
2878 pm8001_get_lrate_mode(phy, link_rate);
2879 phy->sas_phy.oob_mode = SAS_OOB_MODE;
2880 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2881 phy->phy_attached = 1;
2882 }
2883
2884 /**
2885 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2886 * @pm8001_ha: our hba card information
2887 * @piomb: IO message buffer
2888 */
2889 static void
2890 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2891 {
2892 struct hw_event_resp *pPayload =
2893 (struct hw_event_resp *)(piomb + 4);
2894 u32 lr_status_evt_portid =
2895 le32_to_cpu(pPayload->lr_status_evt_portid);
2896 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2897
2898 u8 link_rate =
2899 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2900 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2901 u8 phy_id =
2902 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2903 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2904
2905 struct pm8001_port *port = &pm8001_ha->port[port_id];
2906 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2907 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2908 unsigned long flags;
2909 u8 deviceType = pPayload->sas_identify.dev_type;
2910 port->port_state = portstate;
2911 port->wide_port_phymap |= (1U << phy_id);
2912 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2913 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2914 "portid:%d; phyid:%d; linkrate:%d; "
2915 "portstate:%x; devicetype:%x\n",
2916 port_id, phy_id, link_rate, portstate, deviceType));
2917
2918 switch (deviceType) {
2919 case SAS_PHY_UNUSED:
2920 PM8001_MSG_DBG(pm8001_ha,
2921 pm8001_printk("device type no device.\n"));
2922 break;
2923 case SAS_END_DEVICE:
2924 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2925 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2926 PHY_NOTIFY_ENABLE_SPINUP);
2927 port->port_attached = 1;
2928 pm8001_get_lrate_mode(phy, link_rate);
2929 break;
2930 case SAS_EDGE_EXPANDER_DEVICE:
2931 PM8001_MSG_DBG(pm8001_ha,
2932 pm8001_printk("expander device.\n"));
2933 port->port_attached = 1;
2934 pm8001_get_lrate_mode(phy, link_rate);
2935 break;
2936 case SAS_FANOUT_EXPANDER_DEVICE:
2937 PM8001_MSG_DBG(pm8001_ha,
2938 pm8001_printk("fanout expander device.\n"));
2939 port->port_attached = 1;
2940 pm8001_get_lrate_mode(phy, link_rate);
2941 break;
2942 default:
2943 PM8001_MSG_DBG(pm8001_ha,
2944 pm8001_printk("unknown device type(%x)\n", deviceType));
2945 break;
2946 }
2947 phy->phy_type |= PORT_TYPE_SAS;
2948 phy->identify.device_type = deviceType;
2949 phy->phy_attached = 1;
2950 if (phy->identify.device_type == SAS_END_DEVICE)
2951 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2952 else if (phy->identify.device_type != SAS_PHY_UNUSED)
2953 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2954 phy->sas_phy.oob_mode = SAS_OOB_MODE;
2955 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2956 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2957 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2958 sizeof(struct sas_identify_frame)-4);
2959 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2960 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2961 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2962 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2963 mdelay(200);/*delay a moment to wait disk to spinup*/
2964 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2965 }
2966
2967 /**
2968 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2969 * @pm8001_ha: our hba card information
2970 * @piomb: IO message buffer
2971 */
2972 static void
2973 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2974 {
2975 struct hw_event_resp *pPayload =
2976 (struct hw_event_resp *)(piomb + 4);
2977 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2978 u32 lr_status_evt_portid =
2979 le32_to_cpu(pPayload->lr_status_evt_portid);
2980 u8 link_rate =
2981 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2982 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2983 u8 phy_id =
2984 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2985
2986 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2987
2988 struct pm8001_port *port = &pm8001_ha->port[port_id];
2989 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2990 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2991 unsigned long flags;
2992 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2993 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
2994 port_id, phy_id, link_rate, portstate));
2995
2996 port->port_state = portstate;
2997 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2998 port->port_attached = 1;
2999 pm8001_get_lrate_mode(phy, link_rate);
3000 phy->phy_type |= PORT_TYPE_SATA;
3001 phy->phy_attached = 1;
3002 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3003 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3004 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3005 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3006 sizeof(struct dev_to_host_fis));
3007 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3008 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3009 phy->identify.device_type = SAS_SATA_DEV;
3010 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3011 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3012 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3013 }
3014
3015 /**
3016 * hw_event_phy_down -we should notify the libsas the phy is down.
3017 * @pm8001_ha: our hba card information
3018 * @piomb: IO message buffer
3019 */
3020 static void
3021 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3022 {
3023 struct hw_event_resp *pPayload =
3024 (struct hw_event_resp *)(piomb + 4);
3025
3026 u32 lr_status_evt_portid =
3027 le32_to_cpu(pPayload->lr_status_evt_portid);
3028 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3029 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3030 u8 phy_id =
3031 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3032 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3033
3034 struct pm8001_port *port = &pm8001_ha->port[port_id];
3035 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3036 port->port_state = portstate;
3037 phy->identify.device_type = 0;
3038 phy->phy_attached = 0;
3039 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3040 switch (portstate) {
3041 case PORT_VALID:
3042 break;
3043 case PORT_INVALID:
3044 PM8001_MSG_DBG(pm8001_ha,
3045 pm8001_printk(" PortInvalid portID %d\n", port_id));
3046 PM8001_MSG_DBG(pm8001_ha,
3047 pm8001_printk(" Last phy Down and port invalid\n"));
3048 if (phy->phy_type & PORT_TYPE_SATA) {
3049 phy->phy_type = 0;
3050 port->port_attached = 0;
3051 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3052 port_id, phy_id, 0, 0);
3053 }
3054 sas_phy_disconnected(&phy->sas_phy);
3055 break;
3056 case PORT_IN_RESET:
3057 PM8001_MSG_DBG(pm8001_ha,
3058 pm8001_printk(" Port In Reset portID %d\n", port_id));
3059 break;
3060 case PORT_NOT_ESTABLISHED:
3061 PM8001_MSG_DBG(pm8001_ha,
3062 pm8001_printk(" Phy Down and PORT_NOT_ESTABLISHED\n"));
3063 port->port_attached = 0;
3064 break;
3065 case PORT_LOSTCOMM:
3066 PM8001_MSG_DBG(pm8001_ha,
3067 pm8001_printk(" Phy Down and PORT_LOSTCOMM\n"));
3068 PM8001_MSG_DBG(pm8001_ha,
3069 pm8001_printk(" Last phy Down and port invalid\n"));
3070 if (phy->phy_type & PORT_TYPE_SATA) {
3071 port->port_attached = 0;
3072 phy->phy_type = 0;
3073 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3074 port_id, phy_id, 0, 0);
3075 }
3076 sas_phy_disconnected(&phy->sas_phy);
3077 break;
3078 default:
3079 port->port_attached = 0;
3080 PM8001_MSG_DBG(pm8001_ha,
3081 pm8001_printk(" Phy Down and(default) = 0x%x\n",
3082 portstate));
3083 break;
3084
3085 }
3086 }
3087
3088 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3089 {
3090 struct phy_start_resp *pPayload =
3091 (struct phy_start_resp *)(piomb + 4);
3092 u32 status =
3093 le32_to_cpu(pPayload->status);
3094 u32 phy_id =
3095 le32_to_cpu(pPayload->phyid);
3096 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3097
3098 PM8001_INIT_DBG(pm8001_ha,
3099 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
3100 status, phy_id));
3101 if (status == 0) {
3102 phy->phy_state = 1;
3103 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3104 complete(phy->enable_completion);
3105 }
3106 return 0;
3107
3108 }
3109
3110 /**
3111 * mpi_thermal_hw_event -The hw event has come.
3112 * @pm8001_ha: our hba card information
3113 * @piomb: IO message buffer
3114 */
3115 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3116 {
3117 struct thermal_hw_event *pPayload =
3118 (struct thermal_hw_event *)(piomb + 4);
3119
3120 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3121 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3122
3123 if (thermal_event & 0x40) {
3124 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3125 "Thermal Event: Local high temperature violated!\n"));
3126 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3127 "Thermal Event: Measured local high temperature %d\n",
3128 ((rht_lht & 0xFF00) >> 8)));
3129 }
3130 if (thermal_event & 0x10) {
3131 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3132 "Thermal Event: Remote high temperature violated!\n"));
3133 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3134 "Thermal Event: Measured remote high temperature %d\n",
3135 ((rht_lht & 0xFF000000) >> 24)));
3136 }
3137 return 0;
3138 }
3139
3140 /**
3141 * mpi_hw_event -The hw event has come.
3142 * @pm8001_ha: our hba card information
3143 * @piomb: IO message buffer
3144 */
3145 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3146 {
3147 unsigned long flags, i;
3148 struct hw_event_resp *pPayload =
3149 (struct hw_event_resp *)(piomb + 4);
3150 u32 lr_status_evt_portid =
3151 le32_to_cpu(pPayload->lr_status_evt_portid);
3152 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3153 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3154 u8 phy_id =
3155 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3156 u16 eventType =
3157 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3158 u8 status =
3159 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3160 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3161 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3162 struct pm8001_port *port = &pm8001_ha->port[port_id];
3163 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3164 PM8001_MSG_DBG(pm8001_ha,
3165 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
3166 port_id, phy_id, eventType, status));
3167
3168 switch (eventType) {
3169
3170 case HW_EVENT_SAS_PHY_UP:
3171 PM8001_MSG_DBG(pm8001_ha,
3172 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3173 hw_event_sas_phy_up(pm8001_ha, piomb);
3174 break;
3175 case HW_EVENT_SATA_PHY_UP:
3176 PM8001_MSG_DBG(pm8001_ha,
3177 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3178 hw_event_sata_phy_up(pm8001_ha, piomb);
3179 break;
3180 case HW_EVENT_SATA_SPINUP_HOLD:
3181 PM8001_MSG_DBG(pm8001_ha,
3182 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3183 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3184 break;
3185 case HW_EVENT_PHY_DOWN:
3186 PM8001_MSG_DBG(pm8001_ha,
3187 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3188 if (phy->phy_type & PORT_TYPE_SATA)
3189 sas_ha->notify_phy_event(&phy->sas_phy,
3190 PHYE_LOSS_OF_SIGNAL);
3191 phy->phy_attached = 0;
3192 phy->phy_state = 0;
3193 hw_event_phy_down(pm8001_ha, piomb);
3194 break;
3195 case HW_EVENT_PORT_INVALID:
3196 PM8001_MSG_DBG(pm8001_ha,
3197 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3198 sas_phy_disconnected(sas_phy);
3199 phy->phy_attached = 0;
3200 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3201 break;
3202 /* the broadcast change primitive received, tell the LIBSAS this event
3203 to revalidate the sas domain*/
3204 case HW_EVENT_BROADCAST_CHANGE:
3205 PM8001_MSG_DBG(pm8001_ha,
3206 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3207 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3208 port_id, phy_id, 1, 0);
3209 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3210 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3211 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3212 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3213 break;
3214 case HW_EVENT_PHY_ERROR:
3215 PM8001_MSG_DBG(pm8001_ha,
3216 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3217 sas_phy_disconnected(&phy->sas_phy);
3218 phy->phy_attached = 0;
3219 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3220 break;
3221 case HW_EVENT_BROADCAST_EXP:
3222 PM8001_MSG_DBG(pm8001_ha,
3223 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3224 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3225 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3226 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3227 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3228 break;
3229 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3230 PM8001_MSG_DBG(pm8001_ha,
3231 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3232 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3233 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3234 break;
3235 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3236 PM8001_MSG_DBG(pm8001_ha,
3237 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3238 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3239 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3240 port_id, phy_id, 0, 0);
3241 break;
3242 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3243 PM8001_MSG_DBG(pm8001_ha,
3244 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3245 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3246 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3247 port_id, phy_id, 0, 0);
3248 break;
3249 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3250 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3251 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3252 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3253 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3254 port_id, phy_id, 0, 0);
3255 break;
3256 case HW_EVENT_MALFUNCTION:
3257 PM8001_MSG_DBG(pm8001_ha,
3258 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3259 break;
3260 case HW_EVENT_BROADCAST_SES:
3261 PM8001_MSG_DBG(pm8001_ha,
3262 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3263 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3264 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3265 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3266 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3267 break;
3268 case HW_EVENT_INBOUND_CRC_ERROR:
3269 PM8001_MSG_DBG(pm8001_ha,
3270 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3271 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3272 HW_EVENT_INBOUND_CRC_ERROR,
3273 port_id, phy_id, 0, 0);
3274 break;
3275 case HW_EVENT_HARD_RESET_RECEIVED:
3276 PM8001_MSG_DBG(pm8001_ha,
3277 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3278 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3279 break;
3280 case HW_EVENT_ID_FRAME_TIMEOUT:
3281 PM8001_MSG_DBG(pm8001_ha,
3282 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3283 sas_phy_disconnected(sas_phy);
3284 phy->phy_attached = 0;
3285 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3286 break;
3287 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3288 PM8001_MSG_DBG(pm8001_ha,
3289 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3290 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3291 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3292 port_id, phy_id, 0, 0);
3293 sas_phy_disconnected(sas_phy);
3294 phy->phy_attached = 0;
3295 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3296 break;
3297 case HW_EVENT_PORT_RESET_TIMER_TMO:
3298 PM8001_MSG_DBG(pm8001_ha,
3299 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3300 sas_phy_disconnected(sas_phy);
3301 phy->phy_attached = 0;
3302 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3303 break;
3304 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3305 PM8001_MSG_DBG(pm8001_ha,
3306 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3307 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3308 HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3309 port_id, phy_id, 0, 0);
3310 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3311 if (port->wide_port_phymap & (1 << i)) {
3312 phy = &pm8001_ha->phy[i];
3313 sas_ha->notify_phy_event(&phy->sas_phy,
3314 PHYE_LOSS_OF_SIGNAL);
3315 port->wide_port_phymap &= ~(1 << i);
3316 }
3317 }
3318 break;
3319 case HW_EVENT_PORT_RECOVER:
3320 PM8001_MSG_DBG(pm8001_ha,
3321 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3322 hw_event_port_recover(pm8001_ha, piomb);
3323 break;
3324 case HW_EVENT_PORT_RESET_COMPLETE:
3325 PM8001_MSG_DBG(pm8001_ha,
3326 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3327 break;
3328 case EVENT_BROADCAST_ASYNCH_EVENT:
3329 PM8001_MSG_DBG(pm8001_ha,
3330 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3331 break;
3332 default:
3333 PM8001_MSG_DBG(pm8001_ha,
3334 pm8001_printk("Unknown event type 0x%x\n", eventType));
3335 break;
3336 }
3337 return 0;
3338 }
3339
3340 /**
3341 * mpi_phy_stop_resp - SPCv specific
3342 * @pm8001_ha: our hba card information
3343 * @piomb: IO message buffer
3344 */
3345 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3346 {
3347 struct phy_stop_resp *pPayload =
3348 (struct phy_stop_resp *)(piomb + 4);
3349 u32 status =
3350 le32_to_cpu(pPayload->status);
3351 u32 phyid =
3352 le32_to_cpu(pPayload->phyid);
3353 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3354 PM8001_MSG_DBG(pm8001_ha,
3355 pm8001_printk("phy:0x%x status:0x%x\n",
3356 phyid, status));
3357 if (status == 0)
3358 phy->phy_state = 0;
3359 return 0;
3360 }
3361
3362 /**
3363 * mpi_set_controller_config_resp - SPCv specific
3364 * @pm8001_ha: our hba card information
3365 * @piomb: IO message buffer
3366 */
3367 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3368 void *piomb)
3369 {
3370 struct set_ctrl_cfg_resp *pPayload =
3371 (struct set_ctrl_cfg_resp *)(piomb + 4);
3372 u32 status = le32_to_cpu(pPayload->status);
3373 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3374
3375 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3376 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3377 status, err_qlfr_pgcd));
3378
3379 return 0;
3380 }
3381
3382 /**
3383 * mpi_get_controller_config_resp - SPCv specific
3384 * @pm8001_ha: our hba card information
3385 * @piomb: IO message buffer
3386 */
3387 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3388 void *piomb)
3389 {
3390 PM8001_MSG_DBG(pm8001_ha,
3391 pm8001_printk(" pm80xx_addition_functionality\n"));
3392
3393 return 0;
3394 }
3395
3396 /**
3397 * mpi_get_phy_profile_resp - SPCv specific
3398 * @pm8001_ha: our hba card information
3399 * @piomb: IO message buffer
3400 */
3401 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3402 void *piomb)
3403 {
3404 PM8001_MSG_DBG(pm8001_ha,
3405 pm8001_printk(" pm80xx_addition_functionality\n"));
3406
3407 return 0;
3408 }
3409
3410 /**
3411 * mpi_flash_op_ext_resp - SPCv specific
3412 * @pm8001_ha: our hba card information
3413 * @piomb: IO message buffer
3414 */
3415 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3416 {
3417 PM8001_MSG_DBG(pm8001_ha,
3418 pm8001_printk(" pm80xx_addition_functionality\n"));
3419
3420 return 0;
3421 }
3422
3423 /**
3424 * mpi_set_phy_profile_resp - SPCv specific
3425 * @pm8001_ha: our hba card information
3426 * @piomb: IO message buffer
3427 */
3428 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3429 void *piomb)
3430 {
3431 u8 page_code;
3432 struct set_phy_profile_resp *pPayload =
3433 (struct set_phy_profile_resp *)(piomb + 4);
3434 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3435 u32 status = le32_to_cpu(pPayload->status);
3436
3437 page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3438 if (status) {
3439 /* status is FAILED */
3440 PM8001_FAIL_DBG(pm8001_ha,
3441 pm8001_printk("PhyProfile command failed with status "
3442 "0x%08X \n", status));
3443 return -1;
3444 } else {
3445 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3446 PM8001_FAIL_DBG(pm8001_ha,
3447 pm8001_printk("Invalid page code 0x%X\n",
3448 page_code));
3449 return -1;
3450 }
3451 }
3452 return 0;
3453 }
3454
3455 /**
3456 * mpi_kek_management_resp - SPCv specific
3457 * @pm8001_ha: our hba card information
3458 * @piomb: IO message buffer
3459 */
3460 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3461 void *piomb)
3462 {
3463 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3464
3465 u32 status = le32_to_cpu(pPayload->status);
3466 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3467 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3468
3469 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3470 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3471 status, kidx_new_curr_ksop, err_qlfr));
3472
3473 return 0;
3474 }
3475
3476 /**
3477 * mpi_dek_management_resp - SPCv specific
3478 * @pm8001_ha: our hba card information
3479 * @piomb: IO message buffer
3480 */
3481 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3482 void *piomb)
3483 {
3484 PM8001_MSG_DBG(pm8001_ha,
3485 pm8001_printk(" pm80xx_addition_functionality\n"));
3486
3487 return 0;
3488 }
3489
3490 /**
3491 * ssp_coalesced_comp_resp - SPCv specific
3492 * @pm8001_ha: our hba card information
3493 * @piomb: IO message buffer
3494 */
3495 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3496 void *piomb)
3497 {
3498 PM8001_MSG_DBG(pm8001_ha,
3499 pm8001_printk(" pm80xx_addition_functionality\n"));
3500
3501 return 0;
3502 }
3503
3504 /**
3505 * process_one_iomb - process one outbound Queue memory block
3506 * @pm8001_ha: our hba card information
3507 * @piomb: IO message buffer
3508 */
3509 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3510 {
3511 __le32 pHeader = *(__le32 *)piomb;
3512 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3513
3514 switch (opc) {
3515 case OPC_OUB_ECHO:
3516 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3517 break;
3518 case OPC_OUB_HW_EVENT:
3519 PM8001_MSG_DBG(pm8001_ha,
3520 pm8001_printk("OPC_OUB_HW_EVENT\n"));
3521 mpi_hw_event(pm8001_ha, piomb);
3522 break;
3523 case OPC_OUB_THERM_HW_EVENT:
3524 PM8001_MSG_DBG(pm8001_ha,
3525 pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3526 mpi_thermal_hw_event(pm8001_ha, piomb);
3527 break;
3528 case OPC_OUB_SSP_COMP:
3529 PM8001_MSG_DBG(pm8001_ha,
3530 pm8001_printk("OPC_OUB_SSP_COMP\n"));
3531 mpi_ssp_completion(pm8001_ha, piomb);
3532 break;
3533 case OPC_OUB_SMP_COMP:
3534 PM8001_MSG_DBG(pm8001_ha,
3535 pm8001_printk("OPC_OUB_SMP_COMP\n"));
3536 mpi_smp_completion(pm8001_ha, piomb);
3537 break;
3538 case OPC_OUB_LOCAL_PHY_CNTRL:
3539 PM8001_MSG_DBG(pm8001_ha,
3540 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3541 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3542 break;
3543 case OPC_OUB_DEV_REGIST:
3544 PM8001_MSG_DBG(pm8001_ha,
3545 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3546 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3547 break;
3548 case OPC_OUB_DEREG_DEV:
3549 PM8001_MSG_DBG(pm8001_ha,
3550 pm8001_printk("unregister the device\n"));
3551 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3552 break;
3553 case OPC_OUB_GET_DEV_HANDLE:
3554 PM8001_MSG_DBG(pm8001_ha,
3555 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3556 break;
3557 case OPC_OUB_SATA_COMP:
3558 PM8001_MSG_DBG(pm8001_ha,
3559 pm8001_printk("OPC_OUB_SATA_COMP\n"));
3560 mpi_sata_completion(pm8001_ha, piomb);
3561 break;
3562 case OPC_OUB_SATA_EVENT:
3563 PM8001_MSG_DBG(pm8001_ha,
3564 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3565 mpi_sata_event(pm8001_ha, piomb);
3566 break;
3567 case OPC_OUB_SSP_EVENT:
3568 PM8001_MSG_DBG(pm8001_ha,
3569 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3570 mpi_ssp_event(pm8001_ha, piomb);
3571 break;
3572 case OPC_OUB_DEV_HANDLE_ARRIV:
3573 PM8001_MSG_DBG(pm8001_ha,
3574 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3575 /*This is for target*/
3576 break;
3577 case OPC_OUB_SSP_RECV_EVENT:
3578 PM8001_MSG_DBG(pm8001_ha,
3579 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3580 /*This is for target*/
3581 break;
3582 case OPC_OUB_FW_FLASH_UPDATE:
3583 PM8001_MSG_DBG(pm8001_ha,
3584 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3585 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3586 break;
3587 case OPC_OUB_GPIO_RESPONSE:
3588 PM8001_MSG_DBG(pm8001_ha,
3589 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3590 break;
3591 case OPC_OUB_GPIO_EVENT:
3592 PM8001_MSG_DBG(pm8001_ha,
3593 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3594 break;
3595 case OPC_OUB_GENERAL_EVENT:
3596 PM8001_MSG_DBG(pm8001_ha,
3597 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3598 pm8001_mpi_general_event(pm8001_ha, piomb);
3599 break;
3600 case OPC_OUB_SSP_ABORT_RSP:
3601 PM8001_MSG_DBG(pm8001_ha,
3602 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3603 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3604 break;
3605 case OPC_OUB_SATA_ABORT_RSP:
3606 PM8001_MSG_DBG(pm8001_ha,
3607 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3608 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3609 break;
3610 case OPC_OUB_SAS_DIAG_MODE_START_END:
3611 PM8001_MSG_DBG(pm8001_ha,
3612 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3613 break;
3614 case OPC_OUB_SAS_DIAG_EXECUTE:
3615 PM8001_MSG_DBG(pm8001_ha,
3616 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3617 break;
3618 case OPC_OUB_GET_TIME_STAMP:
3619 PM8001_MSG_DBG(pm8001_ha,
3620 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3621 break;
3622 case OPC_OUB_SAS_HW_EVENT_ACK:
3623 PM8001_MSG_DBG(pm8001_ha,
3624 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3625 break;
3626 case OPC_OUB_PORT_CONTROL:
3627 PM8001_MSG_DBG(pm8001_ha,
3628 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3629 break;
3630 case OPC_OUB_SMP_ABORT_RSP:
3631 PM8001_MSG_DBG(pm8001_ha,
3632 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3633 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3634 break;
3635 case OPC_OUB_GET_NVMD_DATA:
3636 PM8001_MSG_DBG(pm8001_ha,
3637 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3638 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3639 break;
3640 case OPC_OUB_SET_NVMD_DATA:
3641 PM8001_MSG_DBG(pm8001_ha,
3642 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3643 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3644 break;
3645 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3646 PM8001_MSG_DBG(pm8001_ha,
3647 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3648 break;
3649 case OPC_OUB_SET_DEVICE_STATE:
3650 PM8001_MSG_DBG(pm8001_ha,
3651 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3652 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3653 break;
3654 case OPC_OUB_GET_DEVICE_STATE:
3655 PM8001_MSG_DBG(pm8001_ha,
3656 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3657 break;
3658 case OPC_OUB_SET_DEV_INFO:
3659 PM8001_MSG_DBG(pm8001_ha,
3660 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3661 break;
3662 /* spcv specifc commands */
3663 case OPC_OUB_PHY_START_RESP:
3664 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3665 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
3666 mpi_phy_start_resp(pm8001_ha, piomb);
3667 break;
3668 case OPC_OUB_PHY_STOP_RESP:
3669 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3670 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
3671 mpi_phy_stop_resp(pm8001_ha, piomb);
3672 break;
3673 case OPC_OUB_SET_CONTROLLER_CONFIG:
3674 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3675 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
3676 mpi_set_controller_config_resp(pm8001_ha, piomb);
3677 break;
3678 case OPC_OUB_GET_CONTROLLER_CONFIG:
3679 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3680 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
3681 mpi_get_controller_config_resp(pm8001_ha, piomb);
3682 break;
3683 case OPC_OUB_GET_PHY_PROFILE:
3684 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3685 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
3686 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3687 break;
3688 case OPC_OUB_FLASH_OP_EXT:
3689 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3690 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
3691 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3692 break;
3693 case OPC_OUB_SET_PHY_PROFILE:
3694 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3695 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
3696 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3697 break;
3698 case OPC_OUB_KEK_MANAGEMENT_RESP:
3699 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3700 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
3701 mpi_kek_management_resp(pm8001_ha, piomb);
3702 break;
3703 case OPC_OUB_DEK_MANAGEMENT_RESP:
3704 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3705 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
3706 mpi_dek_management_resp(pm8001_ha, piomb);
3707 break;
3708 case OPC_OUB_SSP_COALESCED_COMP_RESP:
3709 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3710 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
3711 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3712 break;
3713 default:
3714 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3715 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
3716 break;
3717 }
3718 }
3719
3720 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3721 {
3722 struct outbound_queue_table *circularQ;
3723 void *pMsg1 = NULL;
3724 u8 uninitialized_var(bc);
3725 u32 ret = MPI_IO_STATUS_FAIL;
3726 unsigned long flags;
3727
3728 spin_lock_irqsave(&pm8001_ha->lock, flags);
3729 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
3730 do {
3731 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3732 if (MPI_IO_STATUS_SUCCESS == ret) {
3733 /* process the outbound message */
3734 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3735 /* free the message from the outbound circular buffer */
3736 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3737 circularQ, bc);
3738 }
3739 if (MPI_IO_STATUS_BUSY == ret) {
3740 /* Update the producer index from SPC */
3741 circularQ->producer_index =
3742 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3743 if (le32_to_cpu(circularQ->producer_index) ==
3744 circularQ->consumer_idx)
3745 /* OQ is empty */
3746 break;
3747 }
3748 } while (1);
3749 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3750 return ret;
3751 }
3752
3753 /* PCI_DMA_... to our direction translation. */
3754 static const u8 data_dir_flags[] = {
3755 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3756 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */
3757 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */
3758 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */
3759 };
3760
3761 static void build_smp_cmd(u32 deviceID, __le32 hTag,
3762 struct smp_req *psmp_cmd, int mode, int length)
3763 {
3764 psmp_cmd->tag = hTag;
3765 psmp_cmd->device_id = cpu_to_le32(deviceID);
3766 if (mode == SMP_DIRECT) {
3767 length = length - 4; /* subtract crc */
3768 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
3769 } else {
3770 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3771 }
3772 }
3773
3774 /**
3775 * pm8001_chip_smp_req - send a SMP task to FW
3776 * @pm8001_ha: our hba card information.
3777 * @ccb: the ccb information this request used.
3778 */
3779 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3780 struct pm8001_ccb_info *ccb)
3781 {
3782 int elem, rc;
3783 struct sas_task *task = ccb->task;
3784 struct domain_device *dev = task->dev;
3785 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3786 struct scatterlist *sg_req, *sg_resp;
3787 u32 req_len, resp_len;
3788 struct smp_req smp_cmd;
3789 u32 opc;
3790 struct inbound_queue_table *circularQ;
3791 char *preq_dma_addr = NULL;
3792 __le64 tmp_addr;
3793 u32 i, length;
3794
3795 memset(&smp_cmd, 0, sizeof(smp_cmd));
3796 /*
3797 * DMA-map SMP request, response buffers
3798 */
3799 sg_req = &task->smp_task.smp_req;
3800 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3801 if (!elem)
3802 return -ENOMEM;
3803 req_len = sg_dma_len(sg_req);
3804
3805 sg_resp = &task->smp_task.smp_resp;
3806 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3807 if (!elem) {
3808 rc = -ENOMEM;
3809 goto err_out;
3810 }
3811 resp_len = sg_dma_len(sg_resp);
3812 /* must be in dwords */
3813 if ((req_len & 0x3) || (resp_len & 0x3)) {
3814 rc = -EINVAL;
3815 goto err_out_2;
3816 }
3817
3818 opc = OPC_INB_SMP_REQUEST;
3819 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3820 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3821
3822 length = sg_req->length;
3823 PM8001_IO_DBG(pm8001_ha,
3824 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
3825 if (!(length - 8))
3826 pm8001_ha->smp_exp_mode = SMP_DIRECT;
3827 else
3828 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
3829
3830
3831 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3832 preq_dma_addr = (char *)phys_to_virt(tmp_addr);
3833
3834 /* INDIRECT MODE command settings. Use DMA */
3835 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
3836 PM8001_IO_DBG(pm8001_ha,
3837 pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
3838 /* for SPCv indirect mode. Place the top 4 bytes of
3839 * SMP Request header here. */
3840 for (i = 0; i < 4; i++)
3841 smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
3842 /* exclude top 4 bytes for SMP req header */
3843 smp_cmd.long_smp_req.long_req_addr =
3844 cpu_to_le64((u64)sg_dma_address
3845 (&task->smp_task.smp_req) + 4);
3846 /* exclude 4 bytes for SMP req header and CRC */
3847 smp_cmd.long_smp_req.long_req_size =
3848 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
3849 smp_cmd.long_smp_req.long_resp_addr =
3850 cpu_to_le64((u64)sg_dma_address
3851 (&task->smp_task.smp_resp));
3852 smp_cmd.long_smp_req.long_resp_size =
3853 cpu_to_le32((u32)sg_dma_len
3854 (&task->smp_task.smp_resp)-4);
3855 } else { /* DIRECT MODE */
3856 smp_cmd.long_smp_req.long_req_addr =
3857 cpu_to_le64((u64)sg_dma_address
3858 (&task->smp_task.smp_req));
3859 smp_cmd.long_smp_req.long_req_size =
3860 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3861 smp_cmd.long_smp_req.long_resp_addr =
3862 cpu_to_le64((u64)sg_dma_address
3863 (&task->smp_task.smp_resp));
3864 smp_cmd.long_smp_req.long_resp_size =
3865 cpu_to_le32
3866 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3867 }
3868 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3869 PM8001_IO_DBG(pm8001_ha,
3870 pm8001_printk("SMP REQUEST DIRECT MODE\n"));
3871 for (i = 0; i < length; i++)
3872 if (i < 16) {
3873 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
3874 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3875 "Byte[%d]:%x (DMA data:%x)\n",
3876 i, smp_cmd.smp_req16[i],
3877 *(preq_dma_addr)));
3878 } else {
3879 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
3880 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3881 "Byte[%d]:%x (DMA data:%x)\n",
3882 i, smp_cmd.smp_req[i],
3883 *(preq_dma_addr)));
3884 }
3885 }
3886
3887 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
3888 &smp_cmd, pm8001_ha->smp_exp_mode, length);
3889 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
3890 (u32 *)&smp_cmd, 0);
3891 if (rc)
3892 goto err_out_2;
3893 return 0;
3894
3895 err_out_2:
3896 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3897 PCI_DMA_FROMDEVICE);
3898 err_out:
3899 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3900 PCI_DMA_TODEVICE);
3901 return rc;
3902 }
3903
3904 static int check_enc_sas_cmd(struct sas_task *task)
3905 {
3906 u8 cmd = task->ssp_task.cmd->cmnd[0];
3907
3908 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
3909 return 1;
3910 else
3911 return 0;
3912 }
3913
3914 static int check_enc_sat_cmd(struct sas_task *task)
3915 {
3916 int ret = 0;
3917 switch (task->ata_task.fis.command) {
3918 case ATA_CMD_FPDMA_READ:
3919 case ATA_CMD_READ_EXT:
3920 case ATA_CMD_READ:
3921 case ATA_CMD_FPDMA_WRITE:
3922 case ATA_CMD_WRITE_EXT:
3923 case ATA_CMD_WRITE:
3924 case ATA_CMD_PIO_READ:
3925 case ATA_CMD_PIO_READ_EXT:
3926 case ATA_CMD_PIO_WRITE:
3927 case ATA_CMD_PIO_WRITE_EXT:
3928 ret = 1;
3929 break;
3930 default:
3931 ret = 0;
3932 break;
3933 }
3934 return ret;
3935 }
3936
3937 /**
3938 * pm80xx_chip_ssp_io_req - send a SSP task to FW
3939 * @pm8001_ha: our hba card information.
3940 * @ccb: the ccb information this request used.
3941 */
3942 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3943 struct pm8001_ccb_info *ccb)
3944 {
3945 struct sas_task *task = ccb->task;
3946 struct domain_device *dev = task->dev;
3947 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3948 struct ssp_ini_io_start_req ssp_cmd;
3949 u32 tag = ccb->ccb_tag;
3950 int ret;
3951 u64 phys_addr, start_addr, end_addr;
3952 u32 end_addr_high, end_addr_low;
3953 struct inbound_queue_table *circularQ;
3954 u32 q_index;
3955 u32 opc = OPC_INB_SSPINIIOSTART;
3956 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
3957 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
3958 /* data address domain added for spcv; set to 0 by host,
3959 * used internally by controller
3960 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
3961 */
3962 ssp_cmd.dad_dir_m_tlr =
3963 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
3964 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3965 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
3966 ssp_cmd.tag = cpu_to_le32(tag);
3967 if (task->ssp_task.enable_first_burst)
3968 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
3969 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
3970 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
3971 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
3972 task->ssp_task.cmd->cmd_len);
3973 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
3974 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
3975
3976 /* Check if encryption is set */
3977 if (pm8001_ha->chip->encrypt &&
3978 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
3979 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3980 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
3981 task->ssp_task.cmd->cmnd[0]));
3982 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
3983 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
3984 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
3985 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
3986
3987 /* fill in PRD (scatter/gather) table, if any */
3988 if (task->num_scatter > 1) {
3989 pm8001_chip_make_sg(task->scatter,
3990 ccb->n_elem, ccb->buf_prd);
3991 phys_addr = ccb->ccb_dma_handle +
3992 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3993 ssp_cmd.enc_addr_low =
3994 cpu_to_le32(lower_32_bits(phys_addr));
3995 ssp_cmd.enc_addr_high =
3996 cpu_to_le32(upper_32_bits(phys_addr));
3997 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
3998 } else if (task->num_scatter == 1) {
3999 u64 dma_addr = sg_dma_address(task->scatter);
4000 ssp_cmd.enc_addr_low =
4001 cpu_to_le32(lower_32_bits(dma_addr));
4002 ssp_cmd.enc_addr_high =
4003 cpu_to_le32(upper_32_bits(dma_addr));
4004 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4005 ssp_cmd.enc_esgl = 0;
4006 /* Check 4G Boundary */
4007 start_addr = cpu_to_le64(dma_addr);
4008 end_addr = (start_addr + ssp_cmd.enc_len) - 1;
4009 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4010 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4011 if (end_addr_high != ssp_cmd.enc_addr_high) {
4012 PM8001_FAIL_DBG(pm8001_ha,
4013 pm8001_printk("The sg list address "
4014 "start_addr=0x%016llx data_len=0x%x "
4015 "end_addr_high=0x%08x end_addr_low="
4016 "0x%08x has crossed 4G boundary\n",
4017 start_addr, ssp_cmd.enc_len,
4018 end_addr_high, end_addr_low));
4019 pm8001_chip_make_sg(task->scatter, 1,
4020 ccb->buf_prd);
4021 phys_addr = ccb->ccb_dma_handle +
4022 offsetof(struct pm8001_ccb_info,
4023 buf_prd[0]);
4024 ssp_cmd.enc_addr_low =
4025 cpu_to_le32(lower_32_bits(phys_addr));
4026 ssp_cmd.enc_addr_high =
4027 cpu_to_le32(upper_32_bits(phys_addr));
4028 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4029 }
4030 } else if (task->num_scatter == 0) {
4031 ssp_cmd.enc_addr_low = 0;
4032 ssp_cmd.enc_addr_high = 0;
4033 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4034 ssp_cmd.enc_esgl = 0;
4035 }
4036 /* XTS mode. All other fields are 0 */
4037 ssp_cmd.key_cmode = 0x6 << 4;
4038 /* set tweak values. Should be the start lba */
4039 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4040 (task->ssp_task.cmd->cmnd[3] << 16) |
4041 (task->ssp_task.cmd->cmnd[4] << 8) |
4042 (task->ssp_task.cmd->cmnd[5]));
4043 } else {
4044 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4045 "Sending Normal SAS command 0x%x inb q %x\n",
4046 task->ssp_task.cmd->cmnd[0], q_index));
4047 /* fill in PRD (scatter/gather) table, if any */
4048 if (task->num_scatter > 1) {
4049 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4050 ccb->buf_prd);
4051 phys_addr = ccb->ccb_dma_handle +
4052 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4053 ssp_cmd.addr_low =
4054 cpu_to_le32(lower_32_bits(phys_addr));
4055 ssp_cmd.addr_high =
4056 cpu_to_le32(upper_32_bits(phys_addr));
4057 ssp_cmd.esgl = cpu_to_le32(1<<31);
4058 } else if (task->num_scatter == 1) {
4059 u64 dma_addr = sg_dma_address(task->scatter);
4060 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4061 ssp_cmd.addr_high =
4062 cpu_to_le32(upper_32_bits(dma_addr));
4063 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4064 ssp_cmd.esgl = 0;
4065 /* Check 4G Boundary */
4066 start_addr = cpu_to_le64(dma_addr);
4067 end_addr = (start_addr + ssp_cmd.len) - 1;
4068 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4069 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4070 if (end_addr_high != ssp_cmd.addr_high) {
4071 PM8001_FAIL_DBG(pm8001_ha,
4072 pm8001_printk("The sg list address "
4073 "start_addr=0x%016llx data_len=0x%x "
4074 "end_addr_high=0x%08x end_addr_low="
4075 "0x%08x has crossed 4G boundary\n",
4076 start_addr, ssp_cmd.len,
4077 end_addr_high, end_addr_low));
4078 pm8001_chip_make_sg(task->scatter, 1,
4079 ccb->buf_prd);
4080 phys_addr = ccb->ccb_dma_handle +
4081 offsetof(struct pm8001_ccb_info,
4082 buf_prd[0]);
4083 ssp_cmd.addr_low =
4084 cpu_to_le32(lower_32_bits(phys_addr));
4085 ssp_cmd.addr_high =
4086 cpu_to_le32(upper_32_bits(phys_addr));
4087 ssp_cmd.esgl = cpu_to_le32(1<<31);
4088 }
4089 } else if (task->num_scatter == 0) {
4090 ssp_cmd.addr_low = 0;
4091 ssp_cmd.addr_high = 0;
4092 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4093 ssp_cmd.esgl = 0;
4094 }
4095 }
4096 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4097 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4098 &ssp_cmd, q_index);
4099 return ret;
4100 }
4101
4102 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4103 struct pm8001_ccb_info *ccb)
4104 {
4105 struct sas_task *task = ccb->task;
4106 struct domain_device *dev = task->dev;
4107 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4108 u32 tag = ccb->ccb_tag;
4109 int ret;
4110 u32 q_index;
4111 struct sata_start_req sata_cmd;
4112 u32 hdr_tag, ncg_tag = 0;
4113 u64 phys_addr, start_addr, end_addr;
4114 u32 end_addr_high, end_addr_low;
4115 u32 ATAP = 0x0;
4116 u32 dir;
4117 struct inbound_queue_table *circularQ;
4118 unsigned long flags;
4119 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4120 memset(&sata_cmd, 0, sizeof(sata_cmd));
4121 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4122 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4123
4124 if (task->data_dir == PCI_DMA_NONE) {
4125 ATAP = 0x04; /* no data*/
4126 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4127 } else if (likely(!task->ata_task.device_control_reg_update)) {
4128 if (task->ata_task.dma_xfer) {
4129 ATAP = 0x06; /* DMA */
4130 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4131 } else {
4132 ATAP = 0x05; /* PIO*/
4133 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4134 }
4135 if (task->ata_task.use_ncq &&
4136 dev->sata_dev.class != ATA_DEV_ATAPI) {
4137 ATAP = 0x07; /* FPDMA */
4138 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4139 }
4140 }
4141 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4142 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4143 ncg_tag = hdr_tag;
4144 }
4145 dir = data_dir_flags[task->data_dir] << 8;
4146 sata_cmd.tag = cpu_to_le32(tag);
4147 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4148 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4149
4150 sata_cmd.sata_fis = task->ata_task.fis;
4151 if (likely(!task->ata_task.device_control_reg_update))
4152 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4153 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4154
4155 /* Check if encryption is set */
4156 if (pm8001_ha->chip->encrypt &&
4157 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4158 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4159 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4160 sata_cmd.sata_fis.command));
4161 opc = OPC_INB_SATA_DIF_ENC_IO;
4162
4163 /* set encryption bit */
4164 sata_cmd.ncqtag_atap_dir_m_dad =
4165 cpu_to_le32(((ncg_tag & 0xff)<<16)|
4166 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4167 /* dad (bit 0-1) is 0 */
4168 /* fill in PRD (scatter/gather) table, if any */
4169 if (task->num_scatter > 1) {
4170 pm8001_chip_make_sg(task->scatter,
4171 ccb->n_elem, ccb->buf_prd);
4172 phys_addr = ccb->ccb_dma_handle +
4173 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4174 sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
4175 sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
4176 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4177 } else if (task->num_scatter == 1) {
4178 u64 dma_addr = sg_dma_address(task->scatter);
4179 sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
4180 sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
4181 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4182 sata_cmd.enc_esgl = 0;
4183 /* Check 4G Boundary */
4184 start_addr = cpu_to_le64(dma_addr);
4185 end_addr = (start_addr + sata_cmd.enc_len) - 1;
4186 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4187 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4188 if (end_addr_high != sata_cmd.enc_addr_high) {
4189 PM8001_FAIL_DBG(pm8001_ha,
4190 pm8001_printk("The sg list address "
4191 "start_addr=0x%016llx data_len=0x%x "
4192 "end_addr_high=0x%08x end_addr_low"
4193 "=0x%08x has crossed 4G boundary\n",
4194 start_addr, sata_cmd.enc_len,
4195 end_addr_high, end_addr_low));
4196 pm8001_chip_make_sg(task->scatter, 1,
4197 ccb->buf_prd);
4198 phys_addr = ccb->ccb_dma_handle +
4199 offsetof(struct pm8001_ccb_info,
4200 buf_prd[0]);
4201 sata_cmd.enc_addr_low =
4202 lower_32_bits(phys_addr);
4203 sata_cmd.enc_addr_high =
4204 upper_32_bits(phys_addr);
4205 sata_cmd.enc_esgl =
4206 cpu_to_le32(1 << 31);
4207 }
4208 } else if (task->num_scatter == 0) {
4209 sata_cmd.enc_addr_low = 0;
4210 sata_cmd.enc_addr_high = 0;
4211 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4212 sata_cmd.enc_esgl = 0;
4213 }
4214 /* XTS mode. All other fields are 0 */
4215 sata_cmd.key_index_mode = 0x6 << 4;
4216 /* set tweak values. Should be the start lba */
4217 sata_cmd.twk_val0 =
4218 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4219 (sata_cmd.sata_fis.lbah << 16) |
4220 (sata_cmd.sata_fis.lbam << 8) |
4221 (sata_cmd.sata_fis.lbal));
4222 sata_cmd.twk_val1 =
4223 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4224 (sata_cmd.sata_fis.lbam_exp));
4225 } else {
4226 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4227 "Sending Normal SATA command 0x%x inb %x\n",
4228 sata_cmd.sata_fis.command, q_index));
4229 /* dad (bit 0-1) is 0 */
4230 sata_cmd.ncqtag_atap_dir_m_dad =
4231 cpu_to_le32(((ncg_tag & 0xff)<<16) |
4232 ((ATAP & 0x3f) << 10) | dir);
4233
4234 /* fill in PRD (scatter/gather) table, if any */
4235 if (task->num_scatter > 1) {
4236 pm8001_chip_make_sg(task->scatter,
4237 ccb->n_elem, ccb->buf_prd);
4238 phys_addr = ccb->ccb_dma_handle +
4239 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4240 sata_cmd.addr_low = lower_32_bits(phys_addr);
4241 sata_cmd.addr_high = upper_32_bits(phys_addr);
4242 sata_cmd.esgl = cpu_to_le32(1 << 31);
4243 } else if (task->num_scatter == 1) {
4244 u64 dma_addr = sg_dma_address(task->scatter);
4245 sata_cmd.addr_low = lower_32_bits(dma_addr);
4246 sata_cmd.addr_high = upper_32_bits(dma_addr);
4247 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4248 sata_cmd.esgl = 0;
4249 /* Check 4G Boundary */
4250 start_addr = cpu_to_le64(dma_addr);
4251 end_addr = (start_addr + sata_cmd.len) - 1;
4252 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4253 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4254 if (end_addr_high != sata_cmd.addr_high) {
4255 PM8001_FAIL_DBG(pm8001_ha,
4256 pm8001_printk("The sg list address "
4257 "start_addr=0x%016llx data_len=0x%x"
4258 "end_addr_high=0x%08x end_addr_low="
4259 "0x%08x has crossed 4G boundary\n",
4260 start_addr, sata_cmd.len,
4261 end_addr_high, end_addr_low));
4262 pm8001_chip_make_sg(task->scatter, 1,
4263 ccb->buf_prd);
4264 phys_addr = ccb->ccb_dma_handle +
4265 offsetof(struct pm8001_ccb_info,
4266 buf_prd[0]);
4267 sata_cmd.addr_low =
4268 lower_32_bits(phys_addr);
4269 sata_cmd.addr_high =
4270 upper_32_bits(phys_addr);
4271 sata_cmd.esgl = cpu_to_le32(1 << 31);
4272 }
4273 } else if (task->num_scatter == 0) {
4274 sata_cmd.addr_low = 0;
4275 sata_cmd.addr_high = 0;
4276 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4277 sata_cmd.esgl = 0;
4278 }
4279 /* scsi cdb */
4280 sata_cmd.atapi_scsi_cdb[0] =
4281 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4282 (task->ata_task.atapi_packet[1] << 8) |
4283 (task->ata_task.atapi_packet[2] << 16) |
4284 (task->ata_task.atapi_packet[3] << 24)));
4285 sata_cmd.atapi_scsi_cdb[1] =
4286 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4287 (task->ata_task.atapi_packet[5] << 8) |
4288 (task->ata_task.atapi_packet[6] << 16) |
4289 (task->ata_task.atapi_packet[7] << 24)));
4290 sata_cmd.atapi_scsi_cdb[2] =
4291 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4292 (task->ata_task.atapi_packet[9] << 8) |
4293 (task->ata_task.atapi_packet[10] << 16) |
4294 (task->ata_task.atapi_packet[11] << 24)));
4295 sata_cmd.atapi_scsi_cdb[3] =
4296 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4297 (task->ata_task.atapi_packet[13] << 8) |
4298 (task->ata_task.atapi_packet[14] << 16) |
4299 (task->ata_task.atapi_packet[15] << 24)));
4300 }
4301
4302 /* Check for read log for failed drive and return */
4303 if (sata_cmd.sata_fis.command == 0x2f) {
4304 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4305 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4306 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4307 struct task_status_struct *ts;
4308
4309 pm8001_ha_dev->id &= 0xDFFFFFFF;
4310 ts = &task->task_status;
4311
4312 spin_lock_irqsave(&task->task_state_lock, flags);
4313 ts->resp = SAS_TASK_COMPLETE;
4314 ts->stat = SAM_STAT_GOOD;
4315 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4316 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4317 task->task_state_flags |= SAS_TASK_STATE_DONE;
4318 if (unlikely((task->task_state_flags &
4319 SAS_TASK_STATE_ABORTED))) {
4320 spin_unlock_irqrestore(&task->task_state_lock,
4321 flags);
4322 PM8001_FAIL_DBG(pm8001_ha,
4323 pm8001_printk("task 0x%p resp 0x%x "
4324 " stat 0x%x but aborted by upper layer "
4325 "\n", task, ts->resp, ts->stat));
4326 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4327 return 0;
4328 } else {
4329 spin_unlock_irqrestore(&task->task_state_lock,
4330 flags);
4331 pm8001_ccb_task_free_done(pm8001_ha, task,
4332 ccb, tag);
4333 return 0;
4334 }
4335 }
4336 }
4337 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4338 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4339 &sata_cmd, q_index);
4340 return ret;
4341 }
4342
4343 /**
4344 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4345 * @pm8001_ha: our hba card information.
4346 * @num: the inbound queue number
4347 * @phy_id: the phy id which we wanted to start up.
4348 */
4349 static int
4350 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4351 {
4352 struct phy_start_req payload;
4353 struct inbound_queue_table *circularQ;
4354 int ret;
4355 u32 tag = 0x01;
4356 u32 opcode = OPC_INB_PHYSTART;
4357 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4358 memset(&payload, 0, sizeof(payload));
4359 payload.tag = cpu_to_le32(tag);
4360
4361 PM8001_INIT_DBG(pm8001_ha,
4362 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
4363 /*
4364 ** [0:7] PHY Identifier
4365 ** [8:11] link rate 1.5G, 3G, 6G
4366 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode
4367 ** [14] 0b disable spin up hold; 1b enable spin up hold
4368 ** [15] ob no change in current PHY analig setup 1b enable using SPAST
4369 */
4370 if (!IS_SPCV_12G(pm8001_ha->pdev))
4371 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4372 LINKMODE_AUTO | LINKRATE_15 |
4373 LINKRATE_30 | LINKRATE_60 | phy_id);
4374 else
4375 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4376 LINKMODE_AUTO | LINKRATE_15 |
4377 LINKRATE_30 | LINKRATE_60 | LINKRATE_120 |
4378 phy_id);
4379
4380 /* SSC Disable and SAS Analog ST configuration */
4381 /**
4382 payload.ase_sh_lm_slr_phyid =
4383 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4384 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4385 phy_id);
4386 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4387 **/
4388
4389 payload.sas_identify.dev_type = SAS_END_DEVICE;
4390 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4391 memcpy(payload.sas_identify.sas_addr,
4392 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4393 payload.sas_identify.phy_id = phy_id;
4394 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4395 return ret;
4396 }
4397
4398 /**
4399 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4400 * @pm8001_ha: our hba card information.
4401 * @num: the inbound queue number
4402 * @phy_id: the phy id which we wanted to start up.
4403 */
4404 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4405 u8 phy_id)
4406 {
4407 struct phy_stop_req payload;
4408 struct inbound_queue_table *circularQ;
4409 int ret;
4410 u32 tag = 0x01;
4411 u32 opcode = OPC_INB_PHYSTOP;
4412 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4413 memset(&payload, 0, sizeof(payload));
4414 payload.tag = cpu_to_le32(tag);
4415 payload.phy_id = cpu_to_le32(phy_id);
4416 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4417 return ret;
4418 }
4419
4420 /**
4421 * see comments on pm8001_mpi_reg_resp.
4422 */
4423 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4424 struct pm8001_device *pm8001_dev, u32 flag)
4425 {
4426 struct reg_dev_req payload;
4427 u32 opc;
4428 u32 stp_sspsmp_sata = 0x4;
4429 struct inbound_queue_table *circularQ;
4430 u32 linkrate, phy_id;
4431 int rc, tag = 0xdeadbeef;
4432 struct pm8001_ccb_info *ccb;
4433 u8 retryFlag = 0x1;
4434 u16 firstBurstSize = 0;
4435 u16 ITNT = 2000;
4436 struct domain_device *dev = pm8001_dev->sas_device;
4437 struct domain_device *parent_dev = dev->parent;
4438 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4439
4440 memset(&payload, 0, sizeof(payload));
4441 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4442 if (rc)
4443 return rc;
4444 ccb = &pm8001_ha->ccb_info[tag];
4445 ccb->device = pm8001_dev;
4446 ccb->ccb_tag = tag;
4447 payload.tag = cpu_to_le32(tag);
4448
4449 if (flag == 1) {
4450 stp_sspsmp_sata = 0x02; /*direct attached sata */
4451 } else {
4452 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4453 stp_sspsmp_sata = 0x00; /* stp*/
4454 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4455 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4456 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4457 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4458 }
4459 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4460 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4461 else
4462 phy_id = pm8001_dev->attached_phy;
4463
4464 opc = OPC_INB_REG_DEV;
4465
4466 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4467 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4468
4469 payload.phyid_portid =
4470 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4471 ((phy_id & 0xFF) << 8));
4472
4473 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4474 ((linkrate & 0x0F) << 24) |
4475 ((stp_sspsmp_sata & 0x03) << 28));
4476 payload.firstburstsize_ITNexustimeout =
4477 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4478
4479 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4480 SAS_ADDR_SIZE);
4481
4482 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4483 if (rc)
4484 pm8001_tag_free(pm8001_ha, tag);
4485
4486 return rc;
4487 }
4488
4489 /**
4490 * pm80xx_chip_phy_ctl_req - support the local phy operation
4491 * @pm8001_ha: our hba card information.
4492 * @num: the inbound queue number
4493 * @phy_id: the phy id which we wanted to operate
4494 * @phy_op:
4495 */
4496 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4497 u32 phyId, u32 phy_op)
4498 {
4499 struct local_phy_ctl_req payload;
4500 struct inbound_queue_table *circularQ;
4501 int ret;
4502 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4503 memset(&payload, 0, sizeof(payload));
4504 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4505 payload.tag = cpu_to_le32(1);
4506 payload.phyop_phyid =
4507 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4508 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4509 return ret;
4510 }
4511
4512 static u32 pm80xx_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4513 {
4514 u32 value;
4515 #ifdef PM8001_USE_MSIX
4516 return 1;
4517 #endif
4518 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4519 if (value)
4520 return 1;
4521 return 0;
4522
4523 }
4524
4525 /**
4526 * pm8001_chip_isr - PM8001 isr handler.
4527 * @pm8001_ha: our hba card information.
4528 * @irq: irq number.
4529 * @stat: stat.
4530 */
4531 static irqreturn_t
4532 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4533 {
4534 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4535 process_oq(pm8001_ha, vec);
4536 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4537 return IRQ_HANDLED;
4538 }
4539
4540 void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4541 u32 operation, u32 phyid, u32 length, u32 *buf)
4542 {
4543 u32 tag , i, j = 0;
4544 int rc;
4545 struct set_phy_profile_req payload;
4546 struct inbound_queue_table *circularQ;
4547 u32 opc = OPC_INB_SET_PHY_PROFILE;
4548
4549 memset(&payload, 0, sizeof(payload));
4550 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4551 if (rc)
4552 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n"));
4553 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4554 payload.tag = cpu_to_le32(tag);
4555 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF));
4556 PM8001_INIT_DBG(pm8001_ha,
4557 pm8001_printk(" phy profile command for phy %x ,length is %d\n",
4558 payload.ppc_phyid, length));
4559 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4560 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
4561 j++;
4562 }
4563 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4564 if (rc)
4565 pm8001_tag_free(pm8001_ha, tag);
4566 }
4567
4568 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4569 u32 length, u8 *buf)
4570 {
4571 u32 page_code, i;
4572
4573 page_code = SAS_PHY_ANALOG_SETTINGS_PAGE;
4574 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4575 mpi_set_phy_profile_req(pm8001_ha,
4576 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4577 length = length + PHY_DWORD_LENGTH;
4578 }
4579 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
4580 }
4581
4582 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
4583 u32 phy, u32 length, u32 *buf)
4584 {
4585 u32 tag, opc;
4586 int rc, i;
4587 struct set_phy_profile_req payload;
4588 struct inbound_queue_table *circularQ;
4589
4590 memset(&payload, 0, sizeof(payload));
4591
4592 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4593 if (rc)
4594 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("Invalid tag"));
4595
4596 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4597 opc = OPC_INB_SET_PHY_PROFILE;
4598
4599 payload.tag = cpu_to_le32(tag);
4600 payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
4601 | (phy & 0xFF));
4602
4603 for (i = 0; i < length; i++)
4604 payload.reserved[i] = cpu_to_le32(*(buf + i));
4605
4606 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4607 if (rc)
4608 pm8001_tag_free(pm8001_ha, tag);
4609
4610 PM8001_INIT_DBG(pm8001_ha,
4611 pm8001_printk("PHY %d settings applied", phy));
4612 }
4613 const struct pm8001_dispatch pm8001_80xx_dispatch = {
4614 .name = "pmc80xx",
4615 .chip_init = pm80xx_chip_init,
4616 .chip_soft_rst = pm80xx_chip_soft_rst,
4617 .chip_rst = pm80xx_hw_chip_rst,
4618 .chip_iounmap = pm8001_chip_iounmap,
4619 .isr = pm80xx_chip_isr,
4620 .is_our_interupt = pm80xx_chip_is_our_interupt,
4621 .isr_process_oq = process_oq,
4622 .interrupt_enable = pm80xx_chip_interrupt_enable,
4623 .interrupt_disable = pm80xx_chip_interrupt_disable,
4624 .make_prd = pm8001_chip_make_sg,
4625 .smp_req = pm80xx_chip_smp_req,
4626 .ssp_io_req = pm80xx_chip_ssp_io_req,
4627 .sata_req = pm80xx_chip_sata_req,
4628 .phy_start_req = pm80xx_chip_phy_start_req,
4629 .phy_stop_req = pm80xx_chip_phy_stop_req,
4630 .reg_dev_req = pm80xx_chip_reg_dev_req,
4631 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4632 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
4633 .task_abort = pm8001_chip_abort_task,
4634 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4635 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4636 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4637 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4638 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4639 };
Linux kernel - Deliverables
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