drivers/scsi/pm8001/pm80xx_hwi.h

   1 /*
   2  * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions, and the following disclaimer,
  12  *      without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *      substantially similar to the "NO WARRANTY" disclaimer below
  15  *      ("Disclaimer") and any redistribution must be conditioned upon
  16  *      including a substantially similar Disclaimer requirement for further
  17  *      binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *      of any contributors may be used to endorse or promote products derived
  20  *      from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40
  41 #ifndef _PMC8001_REG_H_
  42 #define _PMC8001_REG_H_
  43
  44 #include <linux/types.h>
  45 #include <scsi/libsas.h>
  46
  47 /* for Request Opcode of IOMB */
  48 #define OPC_INB_ECHO                            1       /* 0x000 */
  49 #define OPC_INB_PHYSTART                        4       /* 0x004 */
  50 #define OPC_INB_PHYSTOP                         5       /* 0x005 */
  51 #define OPC_INB_SSPINIIOSTART                   6       /* 0x006 */
  52 #define OPC_INB_SSPINITMSTART                   7       /* 0x007 */
  53 /* 0x8 RESV IN SPCv */
  54 #define OPC_INB_RSVD                            8       /* 0x008 */
  55 #define OPC_INB_DEV_HANDLE_ACCEPT               9       /* 0x009 */
  56 #define OPC_INB_SSPTGTIOSTART                   10      /* 0x00A */
  57 #define OPC_INB_SSPTGTRSPSTART                  11      /* 0x00B */
  58 /* 0xC, 0xD, 0xE removed in SPCv */
  59 #define OPC_INB_SSP_ABORT                       15      /* 0x00F */
  60 #define OPC_INB_DEREG_DEV_HANDLE                16      /* 0x010 */
  61 #define OPC_INB_GET_DEV_HANDLE                  17      /* 0x011 */
  62 #define OPC_INB_SMP_REQUEST                     18      /* 0x012 */
  63 /* 0x13 SMP_RESPONSE is removed in SPCv */
  64 #define OPC_INB_SMP_ABORT                       20      /* 0x014 */
  65 /* 0x16 RESV IN SPCv */
  66 #define OPC_INB_RSVD1                           22      /* 0x016 */
  67 #define OPC_INB_SATA_HOST_OPSTART               23      /* 0x017 */
  68 #define OPC_INB_SATA_ABORT                      24      /* 0x018 */
  69 #define OPC_INB_LOCAL_PHY_CONTROL               25      /* 0x019 */
  70 /* 0x1A RESV IN SPCv */
  71 #define OPC_INB_RSVD2                           26      /* 0x01A */
  72 #define OPC_INB_FW_FLASH_UPDATE                 32      /* 0x020 */
  73 #define OPC_INB_GPIO                            34      /* 0x022 */
  74 #define OPC_INB_SAS_DIAG_MODE_START_END         35      /* 0x023 */
  75 #define OPC_INB_SAS_DIAG_EXECUTE                36      /* 0x024 */
  76 /* 0x25 RESV IN SPCv */
  77 #define OPC_INB_RSVD3                           37      /* 0x025 */
  78 #define OPC_INB_GET_TIME_STAMP                  38      /* 0x026 */
  79 #define OPC_INB_PORT_CONTROL                    39      /* 0x027 */
  80 #define OPC_INB_GET_NVMD_DATA                   40      /* 0x028 */
  81 #define OPC_INB_SET_NVMD_DATA                   41      /* 0x029 */
  82 #define OPC_INB_SET_DEVICE_STATE                42      /* 0x02A */
  83 #define OPC_INB_GET_DEVICE_STATE                43      /* 0x02B */
  84 #define OPC_INB_SET_DEV_INFO                    44      /* 0x02C */
  85 /* 0x2D RESV IN SPCv */
  86 #define OPC_INB_RSVD4                           45      /* 0x02D */
  87 #define OPC_INB_SGPIO_REGISTER                  46      /* 0x02E */
  88 #define OPC_INB_PCIE_DIAG_EXEC                  47      /* 0x02F */
  89 #define OPC_INB_SET_CONTROLLER_CONFIG           48      /* 0x030 */
  90 #define OPC_INB_GET_CONTROLLER_CONFIG           49      /* 0x031 */
  91 #define OPC_INB_REG_DEV                         50      /* 0x032 */
  92 #define OPC_INB_SAS_HW_EVENT_ACK                51      /* 0x033 */
  93 #define OPC_INB_GET_DEVICE_INFO                 52      /* 0x034 */
  94 #define OPC_INB_GET_PHY_PROFILE                 53      /* 0x035 */
  95 #define OPC_INB_FLASH_OP_EXT                    54      /* 0x036 */
  96 #define OPC_INB_SET_PHY_PROFILE                 55      /* 0x037 */
  97 #define OPC_INB_KEK_MANAGEMENT                  256     /* 0x100 */
  98 #define OPC_INB_DEK_MANAGEMENT                  257     /* 0x101 */
  99 #define OPC_INB_SSP_INI_DIF_ENC_IO              258     /* 0x102 */
 100 #define OPC_INB_SATA_DIF_ENC_IO                 259     /* 0x103 */
 101
 102 /* for Response Opcode of IOMB */
 103 #define OPC_OUB_ECHO                                    1       /* 0x001 */
 104 #define OPC_OUB_RSVD                                    4       /* 0x004 */
 105 #define OPC_OUB_SSP_COMP                                5       /* 0x005 */
 106 #define OPC_OUB_SMP_COMP                                6       /* 0x006 */
 107 #define OPC_OUB_LOCAL_PHY_CNTRL                         7       /* 0x007 */
 108 #define OPC_OUB_RSVD1                                   10      /* 0x00A */
 109 #define OPC_OUB_DEREG_DEV                               11      /* 0x00B */
 110 #define OPC_OUB_GET_DEV_HANDLE                          12      /* 0x00C */
 111 #define OPC_OUB_SATA_COMP                               13      /* 0x00D */
 112 #define OPC_OUB_SATA_EVENT                              14      /* 0x00E */
 113 #define OPC_OUB_SSP_EVENT                               15      /* 0x00F */
 114 #define OPC_OUB_RSVD2                                   16      /* 0x010 */
 115 /* 0x11 - SMP_RECEIVED Notification removed in SPCv*/
 116 #define OPC_OUB_SSP_RECV_EVENT                          18      /* 0x012 */
 117 #define OPC_OUB_RSVD3                                   19      /* 0x013 */
 118 #define OPC_OUB_FW_FLASH_UPDATE                         20      /* 0x014 */
 119 #define OPC_OUB_GPIO_RESPONSE                           22      /* 0x016 */
 120 #define OPC_OUB_GPIO_EVENT                              23      /* 0x017 */
 121 #define OPC_OUB_GENERAL_EVENT                           24      /* 0x018 */
 122 #define OPC_OUB_SSP_ABORT_RSP                           26      /* 0x01A */
 123 #define OPC_OUB_SATA_ABORT_RSP                          27      /* 0x01B */
 124 #define OPC_OUB_SAS_DIAG_MODE_START_END                 28      /* 0x01C */
 125 #define OPC_OUB_SAS_DIAG_EXECUTE                        29      /* 0x01D */
 126 #define OPC_OUB_GET_TIME_STAMP                          30      /* 0x01E */
 127 #define OPC_OUB_RSVD4                                   31      /* 0x01F */
 128 #define OPC_OUB_PORT_CONTROL                            32      /* 0x020 */
 129 #define OPC_OUB_SKIP_ENTRY                              33      /* 0x021 */
 130 #define OPC_OUB_SMP_ABORT_RSP                           34      /* 0x022 */
 131 #define OPC_OUB_GET_NVMD_DATA                           35      /* 0x023 */
 132 #define OPC_OUB_SET_NVMD_DATA                           36      /* 0x024 */
 133 #define OPC_OUB_DEVICE_HANDLE_REMOVAL                   37      /* 0x025 */
 134 #define OPC_OUB_SET_DEVICE_STATE                        38      /* 0x026 */
 135 #define OPC_OUB_GET_DEVICE_STATE                        39      /* 0x027 */
 136 #define OPC_OUB_SET_DEV_INFO                            40      /* 0x028 */
 137 #define OPC_OUB_RSVD5                                   41      /* 0x029 */
 138 #define OPC_OUB_HW_EVENT                                1792    /* 0x700 */
 139 #define OPC_OUB_DEV_HANDLE_ARRIV                        1824    /* 0x720 */
 140 #define OPC_OUB_THERM_HW_EVENT                          1840    /* 0x730 */
 141 #define OPC_OUB_SGPIO_RESP                              2094    /* 0x82E */
 142 #define OPC_OUB_PCIE_DIAG_EXECUTE                       2095    /* 0x82F */
 143 #define OPC_OUB_DEV_REGIST                              2098    /* 0x832 */
 144 #define OPC_OUB_SAS_HW_EVENT_ACK                        2099    /* 0x833 */
 145 #define OPC_OUB_GET_DEVICE_INFO                         2100    /* 0x834 */
 146 /* spcv specific commands */
 147 #define OPC_OUB_PHY_START_RESP                          2052    /* 0x804 */
 148 #define OPC_OUB_PHY_STOP_RESP                           2053    /* 0x805 */
 149 #define OPC_OUB_SET_CONTROLLER_CONFIG                   2096    /* 0x830 */
 150 #define OPC_OUB_GET_CONTROLLER_CONFIG                   2097    /* 0x831 */
 151 #define OPC_OUB_GET_PHY_PROFILE                         2101    /* 0x835 */
 152 #define OPC_OUB_FLASH_OP_EXT                            2102    /* 0x836 */
 153 #define OPC_OUB_SET_PHY_PROFILE                         2103    /* 0x837 */
 154 #define OPC_OUB_KEK_MANAGEMENT_RESP                     2304    /* 0x900 */
 155 #define OPC_OUB_DEK_MANAGEMENT_RESP                     2305    /* 0x901 */
 156 #define OPC_OUB_SSP_COALESCED_COMP_RESP                 2306    /* 0x902 */
 157
 158 /* for phy start*/
 159 #define SSC_DISABLE_15                  (0x01 << 16)
 160 #define SSC_DISABLE_30                  (0x02 << 16)
 161 #define SSC_DISABLE_60                  (0x04 << 16)
 162 #define SAS_ASE                         (0x01 << 15)
 163 #define SPINHOLD_DISABLE                (0x00 << 14)
 164 #define SPINHOLD_ENABLE                 (0x01 << 14)
 165 #define LINKMODE_SAS                    (0x01 << 12)
 166 #define LINKMODE_DSATA                  (0x02 << 12)
 167 #define LINKMODE_AUTO                   (0x03 << 12)
 168 #define LINKRATE_15                     (0x01 << 8)
 169 #define LINKRATE_30                     (0x02 << 8)
 170 #define LINKRATE_60                     (0x06 << 8)
 171 #define LINKRATE_120                    (0x08 << 8)
 172
 173 /* phy_profile */
 174 #define SAS_PHY_ANALOG_SETTINGS_PAGE    0x04
 175 #define PHY_DWORD_LENGTH                0xC
 176
 177 /* Thermal related */
 178 #define THERMAL_ENABLE                  0x1
 179 #define THERMAL_LOG_ENABLE              0x1
 180 #define THERMAL_PAGE_CODE_7H            0x6
 181 #define THERMAL_PAGE_CODE_8H            0x7
 182 #define LTEMPHIL                         70
 183 #define RTEMPHIL                        100
 184
 185 /* Encryption info */
 186 #define SCRATCH_PAD3_ENC_DISABLED       0x00000000
 187 #define SCRATCH_PAD3_ENC_DIS_ERR        0x00000001
 188 #define SCRATCH_PAD3_ENC_ENA_ERR        0x00000002
 189 #define SCRATCH_PAD3_ENC_READY          0x00000003
 190 #define SCRATCH_PAD3_ENC_MASK           SCRATCH_PAD3_ENC_READY
 191
 192 #define SCRATCH_PAD3_XTS_ENABLED                (1 << 14)
 193 #define SCRATCH_PAD3_SMA_ENABLED                (1 << 4)
 194 #define SCRATCH_PAD3_SMB_ENABLED                (1 << 5)
 195 #define SCRATCH_PAD3_SMF_ENABLED                0
 196 #define SCRATCH_PAD3_SM_MASK                    0x000000F0
 197 #define SCRATCH_PAD3_ERR_CODE                   0x00FF0000
 198
 199 #define SEC_MODE_SMF                            0x0
 200 #define SEC_MODE_SMA                            0x100
 201 #define SEC_MODE_SMB                            0x200
 202 #define CIPHER_MODE_ECB                         0x00000001
 203 #define CIPHER_MODE_XTS                         0x00000002
 204 #define KEK_MGMT_SUBOP_KEYCARDUPDATE            0x4
 205
 206 /* SAS protocol timer configuration page */
 207 #define SAS_PROTOCOL_TIMER_CONFIG_PAGE  0x04
 208 #define STP_MCT_TMO                     32
 209 #define SSP_MCT_TMO                     32
 210 #define SAS_MAX_OPEN_TIME                               5
 211 #define SMP_MAX_CONN_TIMER              0xFF
 212 #define STP_FRM_TIMER                   0
 213 #define STP_IDLE_TIME                   5 /* 5 us; controller default */
 214 #define SAS_MFD                         0
 215 #define SAS_OPNRJT_RTRY_INTVL           2
 216 #define SAS_DOPNRJT_RTRY_TMO            128
 217 #define SAS_COPNRJT_RTRY_TMO            128
 218
 219 /* for phy state */
 220 #define PHY_STATE_LINK_UP_SPCV          0x2
 221 /*
 222   Making ORR bigger than IT NEXUS LOSS which is 2000000us = 2 second.
 223   Assuming a bigger value 3 second, 3000000/128 = 23437.5 where 128
 224   is DOPNRJT_RTRY_TMO
 225 */
 226 #define SAS_DOPNRJT_RTRY_THR            23438
 227 #define SAS_COPNRJT_RTRY_THR            23438
 228 #define SAS_MAX_AIP                     0x200000
 229 #define IT_NEXUS_TIMEOUT       0x7D0
 230 #define PORT_RECOVERY_TIMEOUT  ((IT_NEXUS_TIMEOUT/100) + 30)
 231
 232 struct mpi_msg_hdr {
 233         __le32  header; /* Bits [11:0] - Message operation code */
 234         /* Bits [15:12] - Message Category */
 235         /* Bits [21:16] - Outboundqueue ID for the
 236         operation completion message */
 237         /* Bits [23:22] - Reserved */
 238         /* Bits [28:24] - Buffer Count, indicates how
 239         many buffer are allocated for the massage */
 240         /* Bits [30:29] - Reserved */
 241         /* Bits [31] - Message Valid bit */
 242 } __attribute__((packed, aligned(4)));
 243
 244 /*
 245  * brief the data structure of PHY Start Command
 246  * use to describe enable the phy (128 bytes)
 247  */
 248 struct phy_start_req {
 249         __le32  tag;
 250         __le32  ase_sh_lm_slr_phyid;
 251         struct sas_identify_frame sas_identify; /* 28 Bytes */
 252         __le32 spasti;
 253         u32     reserved[21];
 254 } __attribute__((packed, aligned(4)));
 255
 256 /*
 257  * brief the data structure of PHY Start Command
 258  * use to disable the phy (128 bytes)
 259  */
 260 struct phy_stop_req {
 261         __le32  tag;
 262         __le32  phy_id;
 263         u32     reserved[29];
 264 } __attribute__((packed, aligned(4)));
 265
 266 /* set device bits fis - device to host */
 267 struct set_dev_bits_fis {
 268         u8      fis_type;       /* 0xA1*/
 269         u8      n_i_pmport;
 270         /* b7 : n Bit. Notification bit. If set device needs attention. */
 271         /* b6 : i Bit. Interrupt Bit */
 272         /* b5-b4: reserved2 */
 273         /* b3-b0: PM Port */
 274         u8      status;
 275         u8      error;
 276         u32     _r_a;
 277 } __attribute__ ((packed));
 278 /* PIO setup FIS - device to host */
 279 struct pio_setup_fis {
 280         u8      fis_type;       /* 0x5f */
 281         u8      i_d_pmPort;
 282         /* b7 : reserved */
 283         /* b6 : i bit. Interrupt bit */
 284         /* b5 : d bit. data transfer direction. set to 1 for device to host
 285         xfer */
 286         /* b4 : reserved */
 287         /* b3-b0: PM Port */
 288         u8      status;
 289         u8      error;
 290         u8      lbal;
 291         u8      lbam;
 292         u8      lbah;
 293         u8      device;
 294         u8      lbal_exp;
 295         u8      lbam_exp;
 296         u8      lbah_exp;
 297         u8      _r_a;
 298         u8      sector_count;
 299         u8      sector_count_exp;
 300         u8      _r_b;
 301         u8      e_status;
 302         u8      _r_c[2];
 303         u8      transfer_count;
 304 } __attribute__ ((packed));
 305
 306 /*
 307  * brief the data structure of SATA Completion Response
 308  * use to describe the sata task response (64 bytes)
 309  */
 310 struct sata_completion_resp {
 311         __le32  tag;
 312         __le32  status;
 313         __le32  param;
 314         u32     sata_resp[12];
 315 } __attribute__((packed, aligned(4)));
 316
 317 /*
 318  * brief the data structure of SAS HW Event Notification
 319  * use to alert the host about the hardware event(64 bytes)
 320  */
 321 /* updated outbound struct for spcv */
 322
 323 struct hw_event_resp {
 324         __le32  lr_status_evt_portid;
 325         __le32  evt_param;
 326         __le32  phyid_npip_portstate;
 327         struct sas_identify_frame       sas_identify;
 328         struct dev_to_host_fis  sata_fis;
 329 } __attribute__((packed, aligned(4)));
 330
 331 /*
 332  * brief the data structure for thermal event notification
 333  */
 334
 335 struct thermal_hw_event {
 336         __le32  thermal_event;
 337         __le32  rht_lht;
 338 } __attribute__((packed, aligned(4)));
 339
 340 /*
 341  * brief the data structure of REGISTER DEVICE Command
 342  * use to describe MPI REGISTER DEVICE Command (64 bytes)
 343  */
 344
 345 struct reg_dev_req {
 346         __le32  tag;
 347         __le32  phyid_portid;
 348         __le32  dtype_dlr_mcn_ir_retry;
 349         __le32  firstburstsize_ITNexustimeout;
 350         u8      sas_addr[SAS_ADDR_SIZE];
 351         __le32  upper_device_id;
 352         u32     reserved[24];
 353 } __attribute__((packed, aligned(4)));
 354
 355 /*
 356  * brief the data structure of DEREGISTER DEVICE Command
 357  * use to request spc to remove all internal resources associated
 358  * with the device id (64 bytes)
 359  */
 360
 361 struct dereg_dev_req {
 362         __le32  tag;
 363         __le32  device_id;
 364         u32     reserved[29];
 365 } __attribute__((packed, aligned(4)));
 366
 367 /*
 368  * brief the data structure of DEVICE_REGISTRATION Response
 369  * use to notify the completion of the device registration (64 bytes)
 370  */
 371 struct dev_reg_resp {
 372         __le32  tag;
 373         __le32  status;
 374         __le32  device_id;
 375         u32     reserved[12];
 376 } __attribute__((packed, aligned(4)));
 377
 378 /*
 379  * brief the data structure of Local PHY Control Command
 380  * use to issue PHY CONTROL to local phy (64 bytes)
 381  */
 382 struct local_phy_ctl_req {
 383         __le32  tag;
 384         __le32  phyop_phyid;
 385         u32     reserved1[29];
 386 } __attribute__((packed, aligned(4)));
 387
 388 /**
 389  * brief the data structure of Local Phy Control Response
 390  * use to describe MPI Local Phy Control Response (64 bytes)
 391  */
 392  struct local_phy_ctl_resp {
 393         __le32  tag;
 394         __le32  phyop_phyid;
 395         __le32  status;
 396         u32     reserved[12];
 397 } __attribute__((packed, aligned(4)));
 398
 399 #define OP_BITS 0x0000FF00
 400 #define ID_BITS 0x000000FF
 401
 402 /*
 403  * brief the data structure of PORT Control Command
 404  * use to control port properties (64 bytes)
 405  */
 406
 407 struct port_ctl_req {
 408         __le32  tag;
 409         __le32  portop_portid;
 410         __le32  param0;
 411         __le32  param1;
 412         u32     reserved1[27];
 413 } __attribute__((packed, aligned(4)));
 414
 415 /*
 416  * brief the data structure of HW Event Ack Command
 417  * use to acknowledge receive HW event (64 bytes)
 418  */
 419 struct hw_event_ack_req {
 420         __le32  tag;
 421         __le32  phyid_sea_portid;
 422         __le32  param0;
 423         __le32  param1;
 424         u32     reserved1[27];
 425 } __attribute__((packed, aligned(4)));
 426
 427 /*
 428  * brief the data structure of PHY_START Response Command
 429  * indicates the completion of PHY_START command (64 bytes)
 430  */
 431 struct phy_start_resp {
 432         __le32  tag;
 433         __le32  status;
 434         __le32  phyid;
 435         u32     reserved[12];
 436 } __attribute__((packed, aligned(4)));
 437
 438 /*
 439  * brief the data structure of PHY_STOP Response Command
 440  * indicates the completion of PHY_STOP command (64 bytes)
 441  */
 442 struct phy_stop_resp {
 443         __le32  tag;
 444         __le32  status;
 445         __le32  phyid;
 446         u32     reserved[12];
 447 } __attribute__((packed, aligned(4)));
 448
 449 /*
 450  * brief the data structure of SSP Completion Response
 451  * use to indicate a SSP Completion (n bytes)
 452  */
 453 struct ssp_completion_resp {
 454         __le32  tag;
 455         __le32  status;
 456         __le32  param;
 457         __le32  ssptag_rescv_rescpad;
 458         struct ssp_response_iu ssp_resp_iu;
 459         __le32  residual_count;
 460 } __attribute__((packed, aligned(4)));
 461
 462 #define SSP_RESCV_BIT   0x00010000
 463
 464 /*
 465  * brief the data structure of SATA EVNET response
 466  * use to indicate a SATA Completion (64 bytes)
 467  */
 468 struct sata_event_resp {
 469         __le32 tag;
 470         __le32 event;
 471         __le32 port_id;
 472         __le32 device_id;
 473         u32 reserved;
 474         __le32 event_param0;
 475         __le32 event_param1;
 476         __le32 sata_addr_h32;
 477         __le32 sata_addr_l32;
 478         __le32 e_udt1_udt0_crc;
 479         __le32 e_udt5_udt4_udt3_udt2;
 480         __le32 a_udt1_udt0_crc;
 481         __le32 a_udt5_udt4_udt3_udt2;
 482         __le32 hwdevid_diferr;
 483         __le32 err_framelen_byteoffset;
 484         __le32 err_dataframe;
 485 } __attribute__((packed, aligned(4)));
 486
 487 /*
 488  * brief the data structure of SSP EVNET esponse
 489  * use to indicate a SSP Completion (64 bytes)
 490  */
 491 struct ssp_event_resp {
 492         __le32 tag;
 493         __le32 event;
 494         __le32 port_id;
 495         __le32 device_id;
 496         __le32 ssp_tag;
 497         __le32 event_param0;
 498         __le32 event_param1;
 499         __le32 sas_addr_h32;
 500         __le32 sas_addr_l32;
 501         __le32 e_udt1_udt0_crc;
 502         __le32 e_udt5_udt4_udt3_udt2;
 503         __le32 a_udt1_udt0_crc;
 504         __le32 a_udt5_udt4_udt3_udt2;
 505         __le32 hwdevid_diferr;
 506         __le32 err_framelen_byteoffset;
 507         __le32 err_dataframe;
 508 } __attribute__((packed, aligned(4)));
 509
 510 /**
 511  * brief the data structure of General Event Notification Response
 512  * use to describe MPI General Event Notification Response (64 bytes)
 513  */
 514 struct general_event_resp {
 515         __le32  status;
 516         __le32  inb_IOMB_payload[14];
 517 } __attribute__((packed, aligned(4)));
 518
 519 #define GENERAL_EVENT_PAYLOAD   14
 520 #define OPCODE_BITS     0x00000fff
 521
 522 /*
 523  * brief the data structure of SMP Request Command
 524  * use to describe MPI SMP REQUEST Command (64 bytes)
 525  */
 526 struct smp_req {
 527         __le32  tag;
 528         __le32  device_id;
 529         __le32  len_ip_ir;
 530         /* Bits [0] - Indirect response */
 531         /* Bits [1] - Indirect Payload */
 532         /* Bits [15:2] - Reserved */
 533         /* Bits [23:16] - direct payload Len */
 534         /* Bits [31:24] - Reserved */
 535         u8      smp_req16[16];
 536         union {
 537                 u8      smp_req[32];
 538                 struct {
 539                         __le64 long_req_addr;/* sg dma address, LE */
 540                         __le32 long_req_size;/* LE */
 541                         u32     _r_a;
 542                         __le64 long_resp_addr;/* sg dma address, LE */
 543                         __le32 long_resp_size;/* LE */
 544                         u32     _r_b;
 545                         } long_smp_req;/* sequencer extension */
 546         };
 547         __le32  rsvd[16];
 548 } __attribute__((packed, aligned(4)));
 549 /*
 550  * brief the data structure of SMP Completion Response
 551  * use to describe MPI SMP Completion Response (64 bytes)
 552  */
 553 struct smp_completion_resp {
 554         __le32  tag;
 555         __le32  status;
 556         __le32  param;
 557         u8      _r_a[252];
 558 } __attribute__((packed, aligned(4)));
 559
 560 /*
 561  *brief the data structure of SSP SMP SATA Abort Command
 562  * use to describe MPI SSP SMP & SATA Abort Command (64 bytes)
 563  */
 564 struct task_abort_req {
 565         __le32  tag;
 566         __le32  device_id;
 567         __le32  tag_to_abort;
 568         __le32  abort_all;
 569         u32     reserved[27];
 570 } __attribute__((packed, aligned(4)));
 571
 572 /* These flags used for SSP SMP & SATA Abort */
 573 #define ABORT_MASK              0x3
 574 #define ABORT_SINGLE            0x0
 575 #define ABORT_ALL               0x1
 576
 577 /**
 578  * brief the data structure of SSP SATA SMP Abort Response
 579  * use to describe SSP SMP & SATA Abort Response ( 64 bytes)
 580  */
 581 struct task_abort_resp {
 582         __le32  tag;
 583         __le32  status;
 584         __le32  scp;
 585         u32     reserved[12];
 586 } __attribute__((packed, aligned(4)));
 587
 588 /**
 589  * brief the data structure of SAS Diagnostic Start/End Command
 590  * use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
 591  */
 592 struct sas_diag_start_end_req {
 593         __le32  tag;
 594         __le32  operation_phyid;
 595         u32     reserved[29];
 596 } __attribute__((packed, aligned(4)));
 597
 598 /**
 599  * brief the data structure of SAS Diagnostic Execute Command
 600  * use to describe MPI SAS Diagnostic Execute Command (64 bytes)
 601  */
 602 struct sas_diag_execute_req {
 603         __le32  tag;
 604         __le32  cmdtype_cmddesc_phyid;
 605         __le32  pat1_pat2;
 606         __le32  threshold;
 607         __le32  codepat_errmsk;
 608         __le32  pmon;
 609         __le32  pERF1CTL;
 610         u32     reserved[24];
 611 } __attribute__((packed, aligned(4)));
 612
 613 #define SAS_DIAG_PARAM_BYTES 24
 614
 615 /*
 616  * brief the data structure of Set Device State Command
 617  * use to describe MPI Set Device State Command (64 bytes)
 618  */
 619 struct set_dev_state_req {
 620         __le32  tag;
 621         __le32  device_id;
 622         __le32  nds;
 623         u32     reserved[28];
 624 } __attribute__((packed, aligned(4)));
 625
 626 /*
 627  * brief the data structure of SATA Start Command
 628  * use to describe MPI SATA IO Start Command (64 bytes)
 629  * Note: This structure is common for normal / encryption I/O
 630  */
 631
 632 struct sata_start_req {
 633         __le32  tag;
 634         __le32  device_id;
 635         __le32  data_len;
 636         __le32  ncqtag_atap_dir_m_dad;
 637         struct host_to_dev_fis  sata_fis;
 638         u32     reserved1;
 639         u32     reserved2;      /* dword 11. rsvd for normal I/O. */
 640                                 /* EPLE Descl for enc I/O */
 641         u32     addr_low;       /* dword 12. rsvd for enc I/O */
 642         u32     addr_high;      /* dword 13. reserved for enc I/O */
 643         __le32  len;            /* dword 14: length for normal I/O. */
 644                                 /* EPLE Desch for enc I/O */
 645         __le32  esgl;           /* dword 15. rsvd for enc I/O */
 646         __le32  atapi_scsi_cdb[4];      /* dword 16-19. rsvd for enc I/O */
 647         /* The below fields are reserved for normal I/O */
 648         __le32  key_index_mode; /* dword 20 */
 649         __le32  sector_cnt_enss;/* dword 21 */
 650         __le32  keytagl;        /* dword 22 */
 651         __le32  keytagh;        /* dword 23 */
 652         __le32  twk_val0;       /* dword 24 */
 653         __le32  twk_val1;       /* dword 25 */
 654         __le32  twk_val2;       /* dword 26 */
 655         __le32  twk_val3;       /* dword 27 */
 656         __le32  enc_addr_low;   /* dword 28. Encryption SGL address high */
 657         __le32  enc_addr_high;  /* dword 29. Encryption SGL address low */
 658         __le32  enc_len;        /* dword 30. Encryption length */
 659         __le32  enc_esgl;       /* dword 31. Encryption esgl bit */
 660 } __attribute__((packed, aligned(4)));
 661
 662 /**
 663  * brief the data structure of SSP INI TM Start Command
 664  * use to describe MPI SSP INI TM Start Command (64 bytes)
 665  */
 666 struct ssp_ini_tm_start_req {
 667         __le32  tag;
 668         __le32  device_id;
 669         __le32  relate_tag;
 670         __le32  tmf;
 671         u8      lun[8];
 672         __le32  ds_ads_m;
 673         u32     reserved[24];
 674 } __attribute__((packed, aligned(4)));
 675
 676 struct ssp_info_unit {
 677         u8      lun[8];/* SCSI Logical Unit Number */
 678         u8      reserved1;/* reserved */
 679         u8      efb_prio_attr;
 680         /* B7 : enabledFirstBurst */
 681         /* B6-3 : taskPriority */
 682         /* B2-0 : taskAttribute */
 683         u8      reserved2;      /* reserved */
 684         u8      additional_cdb_len;
 685         /* B7-2 : additional_cdb_len */
 686         /* B1-0 : reserved */
 687         u8      cdb[16];/* The SCSI CDB up to 16 bytes length */
 688 } __attribute__((packed, aligned(4)));
 689
 690 /**
 691  * brief the data structure of SSP INI IO Start Command
 692  * use to describe MPI SSP INI IO Start Command (64 bytes)
 693  * Note: This structure is common for normal / encryption I/O
 694  */
 695 struct ssp_ini_io_start_req {
 696         __le32  tag;
 697         __le32  device_id;
 698         __le32  data_len;
 699         __le32  dad_dir_m_tlr;
 700         struct ssp_info_unit    ssp_iu;
 701         __le32  addr_low;       /* dword 12: sgl low for normal I/O. */
 702                                 /* epl_descl for encryption I/O */
 703         __le32  addr_high;      /* dword 13: sgl hi for normal I/O */
 704                                 /* dpl_descl for encryption I/O */
 705         __le32  len;            /* dword 14: len for normal I/O. */
 706                                 /* edpl_desch for encryption I/O */
 707         __le32  esgl;           /* dword 15: ESGL bit for normal I/O. */
 708                                 /* user defined tag mask for enc I/O */
 709         /* The below fields are reserved for normal I/O */
 710         u8      udt[12];        /* dword 16-18 */
 711         __le32  sectcnt_ios;    /* dword 19 */
 712         __le32  key_cmode;      /* dword 20 */
 713         __le32  ks_enss;        /* dword 21 */
 714         __le32  keytagl;        /* dword 22 */
 715         __le32  keytagh;        /* dword 23 */
 716         __le32  twk_val0;       /* dword 24 */
 717         __le32  twk_val1;       /* dword 25 */
 718         __le32  twk_val2;       /* dword 26 */
 719         __le32  twk_val3;       /* dword 27 */
 720         __le32  enc_addr_low;   /* dword 28: Encryption sgl addr low */
 721         __le32  enc_addr_high;  /* dword 29: Encryption sgl addr hi */
 722         __le32  enc_len;        /* dword 30: Encryption length */
 723         __le32  enc_esgl;       /* dword 31: ESGL bit for encryption */
 724 } __attribute__((packed, aligned(4)));
 725
 726 /**
 727  * brief the data structure for SSP_INI_DIF_ENC_IO COMMAND
 728  * use to initiate SSP I/O operation with optional DIF/ENC
 729  */
 730 struct ssp_dif_enc_io_req {
 731         __le32  tag;
 732         __le32  device_id;
 733         __le32  data_len;
 734         __le32  dirMTlr;
 735         __le32  sspiu0;
 736         __le32  sspiu1;
 737         __le32  sspiu2;
 738         __le32  sspiu3;
 739         __le32  sspiu4;
 740         __le32  sspiu5;
 741         __le32  sspiu6;
 742         __le32  epl_des;
 743         __le32  dpl_desl_ndplr;
 744         __le32  dpl_desh;
 745         __le32  uum_uuv_bss_difbits;
 746         u8      udt[12];
 747         __le32  sectcnt_ios;
 748         __le32  key_cmode;
 749         __le32  ks_enss;
 750         __le32  keytagl;
 751         __le32  keytagh;
 752         __le32  twk_val0;
 753         __le32  twk_val1;
 754         __le32  twk_val2;
 755         __le32  twk_val3;
 756         __le32  addr_low;
 757         __le32  addr_high;
 758         __le32  len;
 759         __le32  esgl;
 760 } __attribute__((packed, aligned(4)));
 761
 762 /**
 763  * brief the data structure of Firmware download
 764  * use to describe MPI FW DOWNLOAD Command (64 bytes)
 765  */
 766 struct fw_flash_Update_req {
 767         __le32  tag;
 768         __le32  cur_image_offset;
 769         __le32  cur_image_len;
 770         __le32  total_image_len;
 771         u32     reserved0[7];
 772         __le32  sgl_addr_lo;
 773         __le32  sgl_addr_hi;
 774         __le32  len;
 775         __le32  ext_reserved;
 776         u32     reserved1[16];
 777 } __attribute__((packed, aligned(4)));
 778
 779 #define FWFLASH_IOMB_RESERVED_LEN 0x07
 780 /**
 781  * brief the data structure of FW_FLASH_UPDATE Response
 782  * use to describe MPI FW_FLASH_UPDATE Response (64 bytes)
 783  *
 784  */
 785  struct fw_flash_Update_resp {
 786         __le32  tag;
 787         __le32  status;
 788         u32     reserved[13];
 789 } __attribute__((packed, aligned(4)));
 790
 791 /**
 792  * brief the data structure of Get NVM Data Command
 793  * use to get data from NVM in HBA(64 bytes)
 794  */
 795 struct get_nvm_data_req {
 796         __le32  tag;
 797         __le32  len_ir_vpdd;
 798         __le32  vpd_offset;
 799         u32     reserved[8];
 800         __le32  resp_addr_lo;
 801         __le32  resp_addr_hi;
 802         __le32  resp_len;
 803         u32     reserved1[17];
 804 } __attribute__((packed, aligned(4)));
 805
 806 struct set_nvm_data_req {
 807         __le32  tag;
 808         __le32  len_ir_vpdd;
 809         __le32  vpd_offset;
 810         u32     reserved[8];
 811         __le32  resp_addr_lo;
 812         __le32  resp_addr_hi;
 813         __le32  resp_len;
 814         u32     reserved1[17];
 815 } __attribute__((packed, aligned(4)));
 816
 817 /**
 818  * brief the data structure for SET CONTROLLER CONFIG COMMAND
 819  * use to modify controller configuration
 820  */
 821 struct set_ctrl_cfg_req {
 822         __le32  tag;
 823         __le32  cfg_pg[14];
 824         u32     reserved[16];
 825 } __attribute__((packed, aligned(4)));
 826
 827 /**
 828  * brief the data structure for GET CONTROLLER CONFIG COMMAND
 829  * use to get controller configuration page
 830  */
 831 struct get_ctrl_cfg_req {
 832         __le32  tag;
 833         __le32  pgcd;
 834         __le32  int_vec;
 835         u32     reserved[28];
 836 } __attribute__((packed, aligned(4)));
 837
 838 /**
 839  * brief the data structure for KEK_MANAGEMENT COMMAND
 840  * use for KEK management
 841  */
 842 struct kek_mgmt_req {
 843         __le32  tag;
 844         __le32  new_curidx_ksop;
 845         u32     reserved;
 846         __le32  kblob[12];
 847         u32     reserved1[16];
 848 } __attribute__((packed, aligned(4)));
 849
 850 /**
 851  * brief the data structure for DEK_MANAGEMENT COMMAND
 852  * use for DEK management
 853  */
 854 struct dek_mgmt_req {
 855         __le32  tag;
 856         __le32  kidx_dsop;
 857         __le32  dekidx;
 858         __le32  addr_l;
 859         __le32  addr_h;
 860         __le32  nent;
 861         __le32  dbf_tblsize;
 862         u32     reserved[24];
 863 } __attribute__((packed, aligned(4)));
 864
 865 /**
 866  * brief the data structure for SET PHY PROFILE COMMAND
 867  * use to retrive phy specific information
 868  */
 869 struct set_phy_profile_req {
 870         __le32  tag;
 871         __le32  ppc_phyid;
 872         u32     reserved[29];
 873 } __attribute__((packed, aligned(4)));
 874
 875 /**
 876  * brief the data structure for GET PHY PROFILE COMMAND
 877  * use to retrive phy specific information
 878  */
 879 struct get_phy_profile_req {
 880         __le32  tag;
 881         __le32  ppc_phyid;
 882         __le32  profile[29];
 883 } __attribute__((packed, aligned(4)));
 884
 885 /**
 886  * brief the data structure for EXT FLASH PARTITION
 887  * use to manage ext flash partition
 888  */
 889 struct ext_flash_partition_req {
 890         __le32  tag;
 891         __le32  cmd;
 892         __le32  offset;
 893         __le32  len;
 894         u32     reserved[7];
 895         __le32  addr_low;
 896         __le32  addr_high;
 897         __le32  len1;
 898         __le32  ext;
 899         u32     reserved1[16];
 900 } __attribute__((packed, aligned(4)));
 901
 902 #define TWI_DEVICE      0x0
 903 #define C_SEEPROM       0x1
 904 #define VPD_FLASH       0x4
 905 #define AAP1_RDUMP      0x5
 906 #define IOP_RDUMP       0x6
 907 #define EXPAN_ROM       0x7
 908
 909 #define IPMode          0x80000000
 910 #define NVMD_TYPE       0x0000000F
 911 #define NVMD_STAT       0x0000FFFF
 912 #define NVMD_LEN        0xFF000000
 913 /**
 914  * brief the data structure of Get NVMD Data Response
 915  * use to describe MPI Get NVMD Data Response (64 bytes)
 916  */
 917 struct get_nvm_data_resp {
 918         __le32          tag;
 919         __le32          ir_tda_bn_dps_das_nvm;
 920         __le32          dlen_status;
 921         __le32          nvm_data[12];
 922 } __attribute__((packed, aligned(4)));
 923
 924 /**
 925  * brief the data structure of SAS Diagnostic Start/End Response
 926  * use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
 927  *
 928  */
 929 struct sas_diag_start_end_resp {
 930         __le32          tag;
 931         __le32          status;
 932         u32             reserved[13];
 933 } __attribute__((packed, aligned(4)));
 934
 935 /**
 936  * brief the data structure of SAS Diagnostic Execute Response
 937  * use to describe MPI SAS Diagnostic Execute Response (64 bytes)
 938  *
 939  */
 940 struct sas_diag_execute_resp {
 941         __le32          tag;
 942         __le32          cmdtype_cmddesc_phyid;
 943         __le32          Status;
 944         __le32          ReportData;
 945         u32             reserved[11];
 946 } __attribute__((packed, aligned(4)));
 947
 948 /**
 949  * brief the data structure of Set Device State Response
 950  * use to describe MPI Set Device State Response (64 bytes)
 951  *
 952  */
 953 struct set_dev_state_resp {
 954         __le32          tag;
 955         __le32          status;
 956         __le32          device_id;
 957         __le32          pds_nds;
 958         u32             reserved[11];
 959 } __attribute__((packed, aligned(4)));
 960
 961 /* new outbound structure for spcv - begins */
 962 /**
 963  * brief the data structure for SET CONTROLLER CONFIG COMMAND
 964  * use to modify controller configuration
 965  */
 966 struct set_ctrl_cfg_resp {
 967         __le32 tag;
 968         __le32 status;
 969         __le32 err_qlfr_pgcd;
 970         u32 reserved[12];
 971 } __attribute__((packed, aligned(4)));
 972
 973 struct get_ctrl_cfg_resp {
 974         __le32 tag;
 975         __le32 status;
 976         __le32 err_qlfr;
 977         __le32 confg_page[12];
 978 } __attribute__((packed, aligned(4)));
 979
 980 struct kek_mgmt_resp {
 981         __le32 tag;
 982         __le32 status;
 983         __le32 kidx_new_curr_ksop;
 984         __le32 err_qlfr;
 985         u32 reserved[11];
 986 } __attribute__((packed, aligned(4)));
 987
 988 struct dek_mgmt_resp {
 989         __le32 tag;
 990         __le32 status;
 991         __le32 kekidx_tbls_dsop;
 992         __le32 dekidx;
 993         __le32 err_qlfr;
 994         u32 reserved[10];
 995 } __attribute__((packed, aligned(4)));
 996
 997 struct get_phy_profile_resp {
 998         __le32 tag;
 999         __le32 status;
1000         __le32 ppc_phyid;
1001         __le32 ppc_specific_rsp[12];
1002 } __attribute__((packed, aligned(4)));
1003
1004 struct flash_op_ext_resp {
1005         __le32 tag;
1006         __le32 cmd;
1007         __le32 status;
1008         __le32 epart_size;
1009         __le32 epart_sect_size;
1010         u32 reserved[10];
1011 } __attribute__((packed, aligned(4)));
1012
1013 struct set_phy_profile_resp {
1014         __le32 tag;
1015         __le32 status;
1016         __le32 ppc_phyid;
1017         __le32 ppc_specific_rsp[12];
1018 } __attribute__((packed, aligned(4)));
1019
1020 struct ssp_coalesced_comp_resp {
1021         __le32 coal_cnt;
1022         __le32 tag0;
1023         __le32 ssp_tag0;
1024         __le32 tag1;
1025         __le32 ssp_tag1;
1026         __le32 add_tag_ssp_tag[10];
1027 } __attribute__((packed, aligned(4)));
1028
1029 /* new outbound structure for spcv - ends */
1030
1031 /* brief data structure for SAS protocol timer configuration page.
1032  *
1033  */
1034 struct SASProtocolTimerConfig {
1035         __le32 pageCode;                        /* 0 */
1036         __le32 MST_MSI;                         /* 1 */
1037         __le32 STP_SSP_MCT_TMO;                 /* 2 */
1038         __le32 STP_FRM_TMO;                     /* 3 */
1039         __le32 STP_IDLE_TMO;                    /* 4 */
1040         __le32 OPNRJT_RTRY_INTVL;               /* 5 */
1041         __le32 Data_Cmd_OPNRJT_RTRY_TMO;        /* 6 */
1042         __le32 Data_Cmd_OPNRJT_RTRY_THR;        /* 7 */
1043         __le32 MAX_AIP;                         /* 8 */
1044 } __attribute__((packed, aligned(4)));
1045
1046 typedef struct SASProtocolTimerConfig SASProtocolTimerConfig_t;
1047
1048 #define NDS_BITS 0x0F
1049 #define PDS_BITS 0xF0
1050
1051 /*
1052  * HW Events type
1053  */
1054
1055 #define HW_EVENT_RESET_START                    0x01
1056 #define HW_EVENT_CHIP_RESET_COMPLETE            0x02
1057 #define HW_EVENT_PHY_STOP_STATUS                0x03
1058 #define HW_EVENT_SAS_PHY_UP                     0x04
1059 #define HW_EVENT_SATA_PHY_UP                    0x05
1060 #define HW_EVENT_SATA_SPINUP_HOLD               0x06
1061 #define HW_EVENT_PHY_DOWN                       0x07
1062 #define HW_EVENT_PORT_INVALID                   0x08
1063 #define HW_EVENT_BROADCAST_CHANGE               0x09
1064 #define HW_EVENT_PHY_ERROR                      0x0A
1065 #define HW_EVENT_BROADCAST_SES                  0x0B
1066 #define HW_EVENT_INBOUND_CRC_ERROR              0x0C
1067 #define HW_EVENT_HARD_RESET_RECEIVED            0x0D
1068 #define HW_EVENT_MALFUNCTION                    0x0E
1069 #define HW_EVENT_ID_FRAME_TIMEOUT               0x0F
1070 #define HW_EVENT_BROADCAST_EXP                  0x10
1071 #define HW_EVENT_PHY_START_STATUS               0x11
1072 #define HW_EVENT_LINK_ERR_INVALID_DWORD         0x12
1073 #define HW_EVENT_LINK_ERR_DISPARITY_ERROR       0x13
1074 #define HW_EVENT_LINK_ERR_CODE_VIOLATION        0x14
1075 #define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH   0x15
1076 #define HW_EVENT_LINK_ERR_PHY_RESET_FAILED      0x16
1077 #define HW_EVENT_PORT_RECOVERY_TIMER_TMO        0x17
1078 #define HW_EVENT_PORT_RECOVER                   0x18
1079 #define HW_EVENT_PORT_RESET_TIMER_TMO           0x19
1080 #define HW_EVENT_PORT_RESET_COMPLETE            0x20
1081 #define EVENT_BROADCAST_ASYNCH_EVENT            0x21
1082
1083 /* port state */
1084 #define PORT_NOT_ESTABLISHED                    0x00
1085 #define PORT_VALID                              0x01
1086 #define PORT_LOSTCOMM                           0x02
1087 #define PORT_IN_RESET                           0x04
1088 #define PORT_3RD_PARTY_RESET                    0x07
1089 #define PORT_INVALID                            0x08
1090
1091 /*
1092  * SSP/SMP/SATA IO Completion Status values
1093  */
1094
1095 #define IO_SUCCESS                              0x00
1096 #define IO_ABORTED                              0x01
1097 #define IO_OVERFLOW                             0x02
1098 #define IO_UNDERFLOW                            0x03
1099 #define IO_FAILED                               0x04
1100 #define IO_ABORT_RESET                          0x05
1101 #define IO_NOT_VALID                            0x06
1102 #define IO_NO_DEVICE                            0x07
1103 #define IO_ILLEGAL_PARAMETER                    0x08
1104 #define IO_LINK_FAILURE                         0x09
1105 #define IO_PROG_ERROR                           0x0A
1106
1107 #define IO_EDC_IN_ERROR                         0x0B
1108 #define IO_EDC_OUT_ERROR                        0x0C
1109 #define IO_ERROR_HW_TIMEOUT                     0x0D
1110 #define IO_XFER_ERROR_BREAK                     0x0E
1111 #define IO_XFER_ERROR_PHY_NOT_READY             0x0F
1112 #define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED        0x10
1113 #define IO_OPEN_CNX_ERROR_ZONE_VIOLATION                0x11
1114 #define IO_OPEN_CNX_ERROR_BREAK                         0x12
1115 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS                 0x13
1116 #define IO_OPEN_CNX_ERROR_BAD_DESTINATION               0x14
1117 #define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
1118 #define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY            0x16
1119 #define IO_OPEN_CNX_ERROR_WRONG_DESTINATION             0x17
1120 /* This error code 0x18 is not used on SPCv */
1121 #define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR                 0x18
1122 #define IO_XFER_ERROR_NAK_RECEIVED                      0x19
1123 #define IO_XFER_ERROR_ACK_NAK_TIMEOUT                   0x1A
1124 #define IO_XFER_ERROR_PEER_ABORTED                      0x1B
1125 #define IO_XFER_ERROR_RX_FRAME                          0x1C
1126 #define IO_XFER_ERROR_DMA                               0x1D
1127 #define IO_XFER_ERROR_CREDIT_TIMEOUT                    0x1E
1128 #define IO_XFER_ERROR_SATA_LINK_TIMEOUT                 0x1F
1129 #define IO_XFER_ERROR_SATA                              0x20
1130
1131 /* This error code 0x22 is not used on SPCv */
1132 #define IO_XFER_ERROR_ABORTED_DUE_TO_SRST               0x22
1133 #define IO_XFER_ERROR_REJECTED_NCQ_MODE                 0x21
1134 #define IO_XFER_ERROR_ABORTED_NCQ_MODE                  0x23
1135 #define IO_XFER_OPEN_RETRY_TIMEOUT                      0x24
1136 /* This error code 0x25 is not used on SPCv */
1137 #define IO_XFER_SMP_RESP_CONNECTION_ERROR               0x25
1138 #define IO_XFER_ERROR_UNEXPECTED_PHASE                  0x26
1139 #define IO_XFER_ERROR_XFER_RDY_OVERRUN                  0x27
1140 #define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED             0x28
1141 #define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT         0x30
1142
1143 /* The following error code 0x31 and 0x32 are not using (obsolete) */
1144 #define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK    0x31
1145 #define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
1146
1147 #define IO_XFER_ERROR_OFFSET_MISMATCH                   0x34
1148 #define IO_XFER_ERROR_XFER_ZERO_DATA_LEN                0x35
1149 #define IO_XFER_CMD_FRAME_ISSUED                        0x36
1150 #define IO_ERROR_INTERNAL_SMP_RESOURCE                  0x37
1151 #define IO_PORT_IN_RESET                                0x38
1152 #define IO_DS_NON_OPERATIONAL                           0x39
1153 #define IO_DS_IN_RECOVERY                               0x3A
1154 #define IO_TM_TAG_NOT_FOUND                             0x3B
1155 #define IO_XFER_PIO_SETUP_ERROR                         0x3C
1156 #define IO_SSP_EXT_IU_ZERO_LEN_ERROR                    0x3D
1157 #define IO_DS_IN_ERROR                                  0x3E
1158 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY              0x3F
1159 #define IO_ABORT_IN_PROGRESS                            0x40
1160 #define IO_ABORT_DELAYED                                0x41
1161 #define IO_INVALID_LENGTH                               0x42
1162
1163 /********** additional response event values *****************/
1164
1165 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT          0x43
1166 #define IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED    0x44
1167 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO        0x45
1168 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST         0x46
1169 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE    0x47
1170 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED 0x48
1171 #define IO_DS_INVALID                                   0x49
1172 /* WARNING: the value is not contiguous from here */
1173 #define IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR     0x52
1174 #define IO_XFER_DMA_ACTIVATE_TIMEOUT            0x53
1175 #define IO_XFER_ERROR_INTERNAL_CRC_ERROR        0x54
1176 #define MPI_IO_RQE_BUSY_FULL                    0x55
1177 #define IO_XFER_ERR_EOB_DATA_OVERRUN            0x56
1178 #define IO_XFER_ERROR_INVALID_SSP_RSP_FRAME     0x57
1179 #define IO_OPEN_CNX_ERROR_OPEN_PREEMPTED        0x58
1180
1181 #define MPI_ERR_IO_RESOURCE_UNAVAILABLE         0x1004
1182 #define MPI_ERR_ATAPI_DEVICE_BUSY               0x1024
1183
1184 #define IO_XFR_ERROR_DEK_KEY_CACHE_MISS         0x2040
1185 /*
1186  * An encryption IO request failed due to DEK Key Tag mismatch.
1187  * The key tag supplied in the encryption IOMB does not match with
1188  * the Key Tag in the referenced DEK Entry.
1189  */
1190 #define IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH       0x2041
1191 #define IO_XFR_ERROR_CIPHER_MODE_INVALID        0x2042
1192 /*
1193  * An encryption I/O request failed because the initial value (IV)
1194  * in the unwrapped DEK blob didn't match the IV used to unwrap it.
1195  */
1196 #define IO_XFR_ERROR_DEK_IV_MISMATCH            0x2043
1197 /* An encryption I/O request failed due to an internal RAM ECC or
1198  * interface error while unwrapping the DEK. */
1199 #define IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR    0x2044
1200 /* An encryption I/O request failed due to an internal RAM ECC or
1201  * interface error while unwrapping the DEK. */
1202 #define IO_XFR_ERROR_INTERNAL_RAM               0x2045
1203 /*
1204  * An encryption I/O request failed
1205  * because the DEK index specified in the I/O was outside the bounds of
1206  * the total number of entries in the host DEK table.
1207  */
1208 #define IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS0x2046
1209
1210 /* define DIF IO response error status code */
1211 #define IO_XFR_ERROR_DIF_MISMATCH                       0x3000
1212 #define IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH       0x3001
1213 #define IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH         0x3002
1214 #define IO_XFR_ERROR_DIF_CRC_MISMATCH                   0x3003
1215
1216 /* define operator management response status and error qualifier code */
1217 #define OPR_MGMT_OP_NOT_SUPPORTED                       0x2060
1218 #define OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL          0x2061
1219 #define OPR_MGMT_MPI_ENC_ERR_OPR_ID_NOT_FOUND           0x2062
1220 #define OPR_MGMT_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH         0x2063
1221 #define OPR_MGMT_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED       0x2064
1222 #define OPR_MGMT_MPI_ENC_ERR_KEK_UNWRAP_FAIL            0x2022
1223 #define OPR_MGMT_MPI_ENC_ERR_NVRAM_OPERATION_FAILURE    0x2023
1224 /***************** additional response event values ***************/
1225
1226 /* WARNING: This error code must always be the last number.
1227  * If you add error code, modify this code also
1228  * It is used as an index
1229  */
1230 #define IO_ERROR_UNKNOWN_GENERIC                        0x2023
1231
1232 /* MSGU CONFIGURATION TABLE*/
1233
1234 #define SPCv_MSGU_CFG_TABLE_UPDATE              0x001
1235 #define SPCv_MSGU_CFG_TABLE_RESET               0x002
1236 #define SPCv_MSGU_CFG_TABLE_FREEZE              0x004
1237 #define SPCv_MSGU_CFG_TABLE_UNFREEZE            0x008
1238 #define MSGU_IBDB_SET                           0x00
1239 #define MSGU_HOST_INT_STATUS                    0x08
1240 #define MSGU_HOST_INT_MASK                      0x0C
1241 #define MSGU_IOPIB_INT_STATUS                   0x18
1242 #define MSGU_IOPIB_INT_MASK                     0x1C
1243 #define MSGU_IBDB_CLEAR                         0x20
1244
1245 #define MSGU_MSGU_CONTROL                       0x24
1246 #define MSGU_ODR                                0x20
1247 #define MSGU_ODCR                               0x28
1248
1249 #define MSGU_ODMR                               0x30
1250 #define MSGU_ODMR_U                             0x34
1251 #define MSGU_ODMR_CLR                           0x38
1252 #define MSGU_ODMR_CLR_U                         0x3C
1253 #define MSGU_OD_RSVD                            0x40
1254
1255 #define MSGU_SCRATCH_PAD_0                      0x44
1256 #define MSGU_SCRATCH_PAD_1                      0x48
1257 #define MSGU_SCRATCH_PAD_2                      0x4C
1258 #define MSGU_SCRATCH_PAD_3                      0x50
1259 #define MSGU_HOST_SCRATCH_PAD_0                 0x54
1260 #define MSGU_HOST_SCRATCH_PAD_1                 0x58
1261 #define MSGU_HOST_SCRATCH_PAD_2                 0x5C
1262 #define MSGU_HOST_SCRATCH_PAD_3                 0x60
1263 #define MSGU_HOST_SCRATCH_PAD_4                 0x64
1264 #define MSGU_HOST_SCRATCH_PAD_5                 0x68
1265 #define MSGU_HOST_SCRATCH_PAD_6                 0x6C
1266 #define MSGU_HOST_SCRATCH_PAD_7                 0x70
1267
1268 /* bit definition for ODMR register */
1269 #define ODMR_MASK_ALL                   0xFFFFFFFF/* mask all
1270                                         interrupt vector */
1271 #define ODMR_CLEAR_ALL                  0       /* clear all
1272                                         interrupt vector */
1273 /* bit definition for ODCR register */
1274 #define ODCR_CLEAR_ALL                  0xFFFFFFFF /* mask all
1275                                         interrupt vector*/
1276 /* MSIX Interupts */
1277 #define MSIX_TABLE_OFFSET               0x2000
1278 #define MSIX_TABLE_ELEMENT_SIZE         0x10
1279 #define MSIX_INTERRUPT_CONTROL_OFFSET   0xC
1280 #define MSIX_TABLE_BASE                 (MSIX_TABLE_OFFSET + \
1281                                         MSIX_INTERRUPT_CONTROL_OFFSET)
1282 #define MSIX_INTERRUPT_DISABLE          0x1
1283 #define MSIX_INTERRUPT_ENABLE           0x0
1284
1285 /* state definition for Scratch Pad1 register */
1286 #define SCRATCH_PAD_RAAE_READY          0x3
1287 #define SCRATCH_PAD_ILA_READY           0xC
1288 #define SCRATCH_PAD_BOOT_LOAD_SUCCESS   0x0
1289 #define SCRATCH_PAD_IOP0_READY          0xC00
1290 #define SCRATCH_PAD_IOP1_READY          0x3000
1291
1292 /* boot loader state */
1293 #define SCRATCH_PAD1_BOOTSTATE_MASK             0x70    /* Bit 4-6 */
1294 #define SCRATCH_PAD1_BOOTSTATE_SUCESS           0x0     /* Load successful */
1295 #define SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM      0x10    /* HDA SEEPROM */
1296 #define SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP    0x20    /* HDA BootStrap Pins */
1297 #define SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET    0x30    /* HDA Soft Reset */
1298 #define SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR       0x40    /* HDA critical error */
1299 #define SCRATCH_PAD1_BOOTSTATE_R1               0x50    /* Reserved */
1300 #define SCRATCH_PAD1_BOOTSTATE_R2               0x60    /* Reserved */
1301 #define SCRATCH_PAD1_BOOTSTATE_FATAL            0x70    /* Fatal Error */
1302
1303  /* state definition for Scratch Pad2 register */
1304 #define SCRATCH_PAD2_POR                0x00    /* power on state */
1305 #define SCRATCH_PAD2_SFR                0x01    /* soft reset state */
1306 #define SCRATCH_PAD2_ERR                0x02    /* error state */
1307 #define SCRATCH_PAD2_RDY                0x03    /* ready state */
1308 #define SCRATCH_PAD2_FWRDY_RST          0x04    /* FW rdy for soft reset flag */
1309 #define SCRATCH_PAD2_IOPRDY_RST         0x08    /* IOP ready for soft reset */
1310 #define SCRATCH_PAD2_STATE_MASK         0xFFFFFFF4 /* ScratchPad 2
1311  Mask, bit1-0 State */
1312 #define SCRATCH_PAD2_RESERVED           0x000003FC/* Scratch Pad1
1313  Reserved bit 2 to 9 */
1314
1315 #define SCRATCH_PAD_ERROR_MASK          0xFFFFFC00 /* Error mask bits */
1316 #define SCRATCH_PAD_STATE_MASK          0x00000003 /* State Mask bits */
1317
1318 /* main configuration offset - byte offset */
1319 #define MAIN_SIGNATURE_OFFSET           0x00 /* DWORD 0x00 */
1320 #define MAIN_INTERFACE_REVISION         0x04 /* DWORD 0x01 */
1321 #define MAIN_FW_REVISION                0x08 /* DWORD 0x02 */
1322 #define MAIN_MAX_OUTSTANDING_IO_OFFSET  0x0C /* DWORD 0x03 */
1323 #define MAIN_MAX_SGL_OFFSET             0x10 /* DWORD 0x04 */
1324 #define MAIN_CNTRL_CAP_OFFSET           0x14 /* DWORD 0x05 */
1325 #define MAIN_GST_OFFSET                 0x18 /* DWORD 0x06 */
1326 #define MAIN_IBQ_OFFSET                 0x1C /* DWORD 0x07 */
1327 #define MAIN_OBQ_OFFSET                 0x20 /* DWORD 0x08 */
1328 #define MAIN_IQNPPD_HPPD_OFFSET         0x24 /* DWORD 0x09 */
1329
1330 /* 0x28 - 0x4C - RSVD */
1331 #define MAIN_EVENT_CRC_CHECK            0x48 /* DWORD 0x12 */
1332 #define MAIN_EVENT_LOG_ADDR_HI          0x50 /* DWORD 0x14 */
1333 #define MAIN_EVENT_LOG_ADDR_LO          0x54 /* DWORD 0x15 */
1334 #define MAIN_EVENT_LOG_BUFF_SIZE        0x58 /* DWORD 0x16 */
1335 #define MAIN_EVENT_LOG_OPTION           0x5C /* DWORD 0x17 */
1336 #define MAIN_PCS_EVENT_LOG_ADDR_HI      0x60 /* DWORD 0x18 */
1337 #define MAIN_PCS_EVENT_LOG_ADDR_LO      0x64 /* DWORD 0x19 */
1338 #define MAIN_PCS_EVENT_LOG_BUFF_SIZE    0x68 /* DWORD 0x1A */
1339 #define MAIN_PCS_EVENT_LOG_OPTION       0x6C /* DWORD 0x1B */
1340 #define MAIN_FATAL_ERROR_INTERRUPT      0x70 /* DWORD 0x1C */
1341 #define MAIN_FATAL_ERROR_RDUMP0_OFFSET  0x74 /* DWORD 0x1D */
1342 #define MAIN_FATAL_ERROR_RDUMP0_LENGTH  0x78 /* DWORD 0x1E */
1343 #define MAIN_FATAL_ERROR_RDUMP1_OFFSET  0x7C /* DWORD 0x1F */
1344 #define MAIN_FATAL_ERROR_RDUMP1_LENGTH  0x80 /* DWORD 0x20 */
1345 #define MAIN_GPIO_LED_FLAGS_OFFSET      0x84 /* DWORD 0x21 */
1346 #define MAIN_ANALOG_SETUP_OFFSET        0x88 /* DWORD 0x22 */
1347
1348 #define MAIN_INT_VECTOR_TABLE_OFFSET    0x8C /* DWORD 0x23 */
1349 #define MAIN_SAS_PHY_ATTR_TABLE_OFFSET  0x90 /* DWORD 0x24 */
1350 #define MAIN_PORT_RECOVERY_TIMER        0x94 /* DWORD 0x25 */
1351 #define MAIN_INT_REASSERTION_DELAY      0x98 /* DWORD 0x26 */
1352
1353 /* Gereral Status Table offset - byte offset */
1354 #define GST_GSTLEN_MPIS_OFFSET          0x00
1355 #define GST_IQ_FREEZE_STATE0_OFFSET     0x04
1356 #define GST_IQ_FREEZE_STATE1_OFFSET     0x08
1357 #define GST_MSGUTCNT_OFFSET             0x0C
1358 #define GST_IOPTCNT_OFFSET              0x10
1359 /* 0x14 - 0x34 - RSVD */
1360 #define GST_GPIO_INPUT_VAL              0x38
1361 /* 0x3c - 0x40 - RSVD */
1362 #define GST_RERRINFO_OFFSET0            0x44
1363 #define GST_RERRINFO_OFFSET1            0x48
1364 #define GST_RERRINFO_OFFSET2            0x4c
1365 #define GST_RERRINFO_OFFSET3            0x50
1366 #define GST_RERRINFO_OFFSET4            0x54
1367 #define GST_RERRINFO_OFFSET5            0x58
1368 #define GST_RERRINFO_OFFSET6            0x5c
1369 #define GST_RERRINFO_OFFSET7            0x60
1370
1371 /* General Status Table - MPI state */
1372 #define GST_MPI_STATE_UNINIT            0x00
1373 #define GST_MPI_STATE_INIT              0x01
1374 #define GST_MPI_STATE_TERMINATION       0x02
1375 #define GST_MPI_STATE_ERROR             0x03
1376 #define GST_MPI_STATE_MASK              0x07
1377
1378 /* Per SAS PHY Attributes */
1379
1380 #define PSPA_PHYSTATE0_OFFSET           0x00 /* Dword V */
1381 #define PSPA_OB_HW_EVENT_PID0_OFFSET    0x04 /* DWORD V+1 */
1382 #define PSPA_PHYSTATE1_OFFSET           0x08 /* Dword V+2 */
1383 #define PSPA_OB_HW_EVENT_PID1_OFFSET    0x0C /* DWORD V+3 */
1384 #define PSPA_PHYSTATE2_OFFSET           0x10 /* Dword V+4 */
1385 #define PSPA_OB_HW_EVENT_PID2_OFFSET    0x14 /* DWORD V+5 */
1386 #define PSPA_PHYSTATE3_OFFSET           0x18 /* Dword V+6 */
1387 #define PSPA_OB_HW_EVENT_PID3_OFFSET    0x1C /* DWORD V+7 */
1388 #define PSPA_PHYSTATE4_OFFSET           0x20 /* Dword V+8 */
1389 #define PSPA_OB_HW_EVENT_PID4_OFFSET    0x24 /* DWORD V+9 */
1390 #define PSPA_PHYSTATE5_OFFSET           0x28 /* Dword V+10 */
1391 #define PSPA_OB_HW_EVENT_PID5_OFFSET    0x2C /* DWORD V+11 */
1392 #define PSPA_PHYSTATE6_OFFSET           0x30 /* Dword V+12 */
1393 #define PSPA_OB_HW_EVENT_PID6_OFFSET    0x34 /* DWORD V+13 */
1394 #define PSPA_PHYSTATE7_OFFSET           0x38 /* Dword V+14 */
1395 #define PSPA_OB_HW_EVENT_PID7_OFFSET    0x3C /* DWORD V+15 */
1396 #define PSPA_PHYSTATE8_OFFSET           0x40 /* DWORD V+16 */
1397 #define PSPA_OB_HW_EVENT_PID8_OFFSET    0x44 /* DWORD V+17 */
1398 #define PSPA_PHYSTATE9_OFFSET           0x48 /* DWORD V+18 */
1399 #define PSPA_OB_HW_EVENT_PID9_OFFSET    0x4C /* DWORD V+19 */
1400 #define PSPA_PHYSTATE10_OFFSET          0x50 /* DWORD V+20 */
1401 #define PSPA_OB_HW_EVENT_PID10_OFFSET   0x54 /* DWORD V+21 */
1402 #define PSPA_PHYSTATE11_OFFSET          0x58 /* DWORD V+22 */
1403 #define PSPA_OB_HW_EVENT_PID11_OFFSET   0x5C /* DWORD V+23 */
1404 #define PSPA_PHYSTATE12_OFFSET          0x60 /* DWORD V+24 */
1405 #define PSPA_OB_HW_EVENT_PID12_OFFSET   0x64 /* DWORD V+25 */
1406 #define PSPA_PHYSTATE13_OFFSET          0x68 /* DWORD V+26 */
1407 #define PSPA_OB_HW_EVENT_PID13_OFFSET   0x6c /* DWORD V+27 */
1408 #define PSPA_PHYSTATE14_OFFSET          0x70 /* DWORD V+28 */
1409 #define PSPA_OB_HW_EVENT_PID14_OFFSET   0x74 /* DWORD V+29 */
1410 #define PSPA_PHYSTATE15_OFFSET          0x78 /* DWORD V+30 */
1411 #define PSPA_OB_HW_EVENT_PID15_OFFSET   0x7c /* DWORD V+31 */
1412 /* end PSPA */
1413
1414 /* inbound queue configuration offset - byte offset */
1415 #define IB_PROPERITY_OFFSET             0x00
1416 #define IB_BASE_ADDR_HI_OFFSET          0x04
1417 #define IB_BASE_ADDR_LO_OFFSET          0x08
1418 #define IB_CI_BASE_ADDR_HI_OFFSET       0x0C
1419 #define IB_CI_BASE_ADDR_LO_OFFSET       0x10
1420 #define IB_PIPCI_BAR                    0x14
1421 #define IB_PIPCI_BAR_OFFSET             0x18
1422 #define IB_RESERVED_OFFSET              0x1C
1423
1424 /* outbound queue configuration offset - byte offset */
1425 #define OB_PROPERITY_OFFSET             0x00
1426 #define OB_BASE_ADDR_HI_OFFSET          0x04
1427 #define OB_BASE_ADDR_LO_OFFSET          0x08
1428 #define OB_PI_BASE_ADDR_HI_OFFSET       0x0C
1429 #define OB_PI_BASE_ADDR_LO_OFFSET       0x10
1430 #define OB_CIPCI_BAR                    0x14
1431 #define OB_CIPCI_BAR_OFFSET             0x18
1432 #define OB_INTERRUPT_COALES_OFFSET      0x1C
1433 #define OB_DYNAMIC_COALES_OFFSET        0x20
1434 #define OB_PROPERTY_INT_ENABLE          0x40000000
1435
1436 #define MBIC_NMI_ENABLE_VPE0_IOP        0x000418
1437 #define MBIC_NMI_ENABLE_VPE0_AAP1       0x000418
1438 /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
1439 #define PCIE_EVENT_INTERRUPT_ENABLE     0x003040
1440 #define PCIE_EVENT_INTERRUPT            0x003044
1441 #define PCIE_ERROR_INTERRUPT_ENABLE     0x003048
1442 #define PCIE_ERROR_INTERRUPT            0x00304C
1443
1444 /* SPCV soft reset */
1445 #define SPC_REG_SOFT_RESET 0x00001000
1446 #define SPCv_NORMAL_RESET_VALUE         0x1
1447
1448 #define SPCv_SOFT_RESET_READ_MASK               0xC0
1449 #define SPCv_SOFT_RESET_NO_RESET                0x0
1450 #define SPCv_SOFT_RESET_NORMAL_RESET_OCCURED    0x40
1451 #define SPCv_SOFT_RESET_HDA_MODE_OCCURED        0x80
1452 #define SPCv_SOFT_RESET_CHIP_RESET_OCCURED      0xC0
1453
1454 /* signature definition for host scratch pad0 register */
1455 #define SPC_SOFT_RESET_SIGNATURE        0x252acbcd
1456 /* Signature for Soft Reset */
1457
1458 /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
1459 #define SPC_REG_RESET                   0x000000/* reset register */
1460
1461 /* bit definition for SPC_RESET register */
1462 #define SPC_REG_RESET_OSSP              0x00000001
1463 #define SPC_REG_RESET_RAAE              0x00000002
1464 #define SPC_REG_RESET_PCS_SPBC          0x00000004
1465 #define SPC_REG_RESET_PCS_IOP_SS        0x00000008
1466 #define SPC_REG_RESET_PCS_AAP1_SS       0x00000010
1467 #define SPC_REG_RESET_PCS_AAP2_SS       0x00000020
1468 #define SPC_REG_RESET_PCS_LM            0x00000040
1469 #define SPC_REG_RESET_PCS               0x00000080
1470 #define SPC_REG_RESET_GSM               0x00000100
1471 #define SPC_REG_RESET_DDR2              0x00010000
1472 #define SPC_REG_RESET_BDMA_CORE         0x00020000
1473 #define SPC_REG_RESET_BDMA_SXCBI        0x00040000
1474 #define SPC_REG_RESET_PCIE_AL_SXCBI     0x00080000
1475 #define SPC_REG_RESET_PCIE_PWR          0x00100000
1476 #define SPC_REG_RESET_PCIE_SFT          0x00200000
1477 #define SPC_REG_RESET_PCS_SXCBI         0x00400000
1478 #define SPC_REG_RESET_LMS_SXCBI         0x00800000
1479 #define SPC_REG_RESET_PMIC_SXCBI        0x01000000
1480 #define SPC_REG_RESET_PMIC_CORE         0x02000000
1481 #define SPC_REG_RESET_PCIE_PC_SXCBI     0x04000000
1482 #define SPC_REG_RESET_DEVICE            0x80000000
1483
1484 /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
1485 #define SPCV_IBW_AXI_TRANSLATION_LOW    0x001010
1486
1487 #define MBIC_AAP1_ADDR_BASE             0x060000
1488 #define MBIC_IOP_ADDR_BASE              0x070000
1489 #define GSM_ADDR_BASE                   0x0700000
1490 /* Dynamic map through Bar4 - 0x00700000 */
1491 #define GSM_CONFIG_RESET                0x00000000
1492 #define RAM_ECC_DB_ERR                  0x00000018
1493 #define GSM_READ_ADDR_PARITY_INDIC      0x00000058
1494 #define GSM_WRITE_ADDR_PARITY_INDIC     0x00000060
1495 #define GSM_WRITE_DATA_PARITY_INDIC     0x00000068
1496 #define GSM_READ_ADDR_PARITY_CHECK      0x00000038
1497 #define GSM_WRITE_ADDR_PARITY_CHECK     0x00000040
1498 #define GSM_WRITE_DATA_PARITY_CHECK     0x00000048
1499
1500 #define RB6_ACCESS_REG                  0x6A0000
1501 #define HDAC_EXEC_CMD                   0x0002
1502 #define HDA_C_PA                        0xcb
1503 #define HDA_SEQ_ID_BITS                 0x00ff0000
1504 #define HDA_GSM_OFFSET_BITS             0x00FFFFFF
1505 #define HDA_GSM_CMD_OFFSET_BITS         0x42C0
1506 #define HDA_GSM_RSP_OFFSET_BITS         0x42E0
1507
1508 #define MBIC_AAP1_ADDR_BASE             0x060000
1509 #define MBIC_IOP_ADDR_BASE              0x070000
1510 #define GSM_ADDR_BASE                   0x0700000
1511 #define SPC_TOP_LEVEL_ADDR_BASE         0x000000
1512 #define GSM_CONFIG_RESET_VALUE          0x00003b00
1513 #define GPIO_ADDR_BASE                  0x00090000
1514 #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET   0x0000010c
1515
1516 /* RB6 offset */
1517 #define SPC_RB6_OFFSET                  0x80C0
1518 /* Magic number of soft reset for RB6 */
1519 #define RB6_MAGIC_NUMBER_RST            0x1234
1520
1521 /* Device Register status */
1522 #define DEVREG_SUCCESS                                  0x00
1523 #define DEVREG_FAILURE_OUT_OF_RESOURCE                  0x01
1524 #define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED        0x02
1525 #define DEVREG_FAILURE_INVALID_PHY_ID                   0x03
1526 #define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED        0x04
1527 #define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE             0x05
1528 #define DEVREG_FAILURE_PORT_NOT_VALID_STATE             0x06
1529 #define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID            0x07
1530
1531
1532 #define MEMBASE_II_SHIFT_REGISTER       0x1010
1533 #endif