2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 #include <linux/delay.h>
12 qla2xxx_prep_dump(scsi_qla_host_t
*ha
, struct qla2xxx_fw_dump
*fw_dump
)
14 fw_dump
->fw_major_version
= htonl(ha
->fw_major_version
);
15 fw_dump
->fw_minor_version
= htonl(ha
->fw_minor_version
);
16 fw_dump
->fw_subminor_version
= htonl(ha
->fw_subminor_version
);
17 fw_dump
->fw_attributes
= htonl(ha
->fw_attributes
);
19 fw_dump
->vendor
= htonl(ha
->pdev
->vendor
);
20 fw_dump
->device
= htonl(ha
->pdev
->device
);
21 fw_dump
->subsystem_vendor
= htonl(ha
->pdev
->subsystem_vendor
);
22 fw_dump
->subsystem_device
= htonl(ha
->pdev
->subsystem_device
);
26 qla2xxx_copy_queues(scsi_qla_host_t
*ha
, void *ptr
)
29 memcpy(ptr
, ha
->request_ring
, ha
->request_q_length
*
33 ptr
+= ha
->request_q_length
* sizeof(request_t
);
34 memcpy(ptr
, ha
->response_ring
, ha
->response_q_length
*
37 return ptr
+ (ha
->response_q_length
* sizeof(response_t
));
41 qla2xxx_dump_memory(scsi_qla_host_t
*ha
, uint32_t *code_ram
,
42 uint32_t cram_size
, uint32_t *ext_mem
, void **nxt
)
45 uint32_t cnt
, stat
, timer
, risc_address
, ext_mem_cnt
;
47 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
50 risc_address
= ext_mem_cnt
= 0;
51 memset(mb
, 0, sizeof(mb
));
54 risc_address
= 0x20000;
55 WRT_REG_WORD(®
->mailbox0
, MBC_READ_RAM_EXTENDED
);
56 clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
);
58 for (cnt
= 0; cnt
< cram_size
/ 4 && rval
== QLA_SUCCESS
;
59 cnt
++, risc_address
++) {
60 WRT_REG_WORD(®
->mailbox1
, LSW(risc_address
));
61 WRT_REG_WORD(®
->mailbox8
, MSW(risc_address
));
62 RD_REG_WORD(®
->mailbox8
);
63 WRT_REG_DWORD(®
->hccr
, HCCRX_SET_HOST_INT
);
65 for (timer
= 6000000; timer
; timer
--) {
66 /* Check for pending interrupts. */
67 stat
= RD_REG_DWORD(®
->host_status
);
68 if (stat
& HSRX_RISC_INT
) {
71 if (stat
== 0x1 || stat
== 0x2 ||
72 stat
== 0x10 || stat
== 0x11) {
73 set_bit(MBX_INTERRUPT
,
76 mb
[0] = RD_REG_WORD(®
->mailbox0
);
77 mb
[2] = RD_REG_WORD(®
->mailbox2
);
78 mb
[3] = RD_REG_WORD(®
->mailbox3
);
80 WRT_REG_DWORD(®
->hccr
,
82 RD_REG_DWORD(®
->hccr
);
86 /* Clear this intr; it wasn't a mailbox intr */
87 WRT_REG_DWORD(®
->hccr
, HCCRX_CLR_RISC_INT
);
88 RD_REG_DWORD(®
->hccr
);
93 if (test_and_clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
)) {
94 rval
= mb
[0] & MBS_MASK
;
95 code_ram
[cnt
] = htonl((mb
[3] << 16) | mb
[2]);
97 rval
= QLA_FUNCTION_FAILED
;
101 if (rval
== QLA_SUCCESS
) {
102 /* External Memory. */
103 risc_address
= 0x100000;
104 ext_mem_cnt
= ha
->fw_memory_size
- 0x100000 + 1;
105 WRT_REG_WORD(®
->mailbox0
, MBC_READ_RAM_EXTENDED
);
106 clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
);
108 for (cnt
= 0; cnt
< ext_mem_cnt
&& rval
== QLA_SUCCESS
;
109 cnt
++, risc_address
++) {
110 WRT_REG_WORD(®
->mailbox1
, LSW(risc_address
));
111 WRT_REG_WORD(®
->mailbox8
, MSW(risc_address
));
112 RD_REG_WORD(®
->mailbox8
);
113 WRT_REG_DWORD(®
->hccr
, HCCRX_SET_HOST_INT
);
115 for (timer
= 6000000; timer
; timer
--) {
116 /* Check for pending interrupts. */
117 stat
= RD_REG_DWORD(®
->host_status
);
118 if (stat
& HSRX_RISC_INT
) {
121 if (stat
== 0x1 || stat
== 0x2 ||
122 stat
== 0x10 || stat
== 0x11) {
123 set_bit(MBX_INTERRUPT
,
126 mb
[0] = RD_REG_WORD(®
->mailbox0
);
127 mb
[2] = RD_REG_WORD(®
->mailbox2
);
128 mb
[3] = RD_REG_WORD(®
->mailbox3
);
130 WRT_REG_DWORD(®
->hccr
,
132 RD_REG_DWORD(®
->hccr
);
136 /* Clear this intr; it wasn't a mailbox intr */
137 WRT_REG_DWORD(®
->hccr
, HCCRX_CLR_RISC_INT
);
138 RD_REG_DWORD(®
->hccr
);
143 if (test_and_clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
)) {
144 rval
= mb
[0] & MBS_MASK
;
145 ext_mem
[cnt
] = htonl((mb
[3] << 16) | mb
[2]);
147 rval
= QLA_FUNCTION_FAILED
;
151 *nxt
= rval
== QLA_SUCCESS
? &ext_mem
[cnt
]: NULL
;
156 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
158 * @hardware_locked: Called with the hardware_lock
161 qla2300_fw_dump(scsi_qla_host_t
*ha
, int hardware_locked
)
165 uint32_t risc_address
;
169 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
170 uint16_t __iomem
*dmp_reg
;
172 struct qla2300_fw_dump
*fw
;
173 uint32_t data_ram_cnt
;
175 risc_address
= data_ram_cnt
= 0;
179 if (!hardware_locked
)
180 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
183 qla_printk(KERN_WARNING
, ha
,
184 "No buffer available for dump!!!\n");
185 goto qla2300_fw_dump_failed
;
189 qla_printk(KERN_WARNING
, ha
,
190 "Firmware has been previously dumped (%p) -- ignoring "
191 "request...\n", ha
->fw_dump
);
192 goto qla2300_fw_dump_failed
;
194 fw
= &ha
->fw_dump
->isp
.isp23
;
195 qla2xxx_prep_dump(ha
, ha
->fw_dump
);
198 fw
->hccr
= htons(RD_REG_WORD(®
->hccr
));
201 WRT_REG_WORD(®
->hccr
, HCCR_PAUSE_RISC
);
202 if (IS_QLA2300(ha
)) {
204 (RD_REG_WORD(®
->hccr
) & HCCR_RISC_PAUSE
) == 0 &&
205 rval
== QLA_SUCCESS
; cnt
--) {
209 rval
= QLA_FUNCTION_TIMEOUT
;
212 RD_REG_WORD(®
->hccr
); /* PCI Posting. */
216 if (rval
== QLA_SUCCESS
) {
217 dmp_reg
= (uint16_t __iomem
*)(reg
+ 0);
218 for (cnt
= 0; cnt
< sizeof(fw
->pbiu_reg
) / 2; cnt
++)
219 fw
->pbiu_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
221 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x10);
222 for (cnt
= 0; cnt
< sizeof(fw
->risc_host_reg
) / 2; cnt
++)
223 fw
->risc_host_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
225 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x40);
226 for (cnt
= 0; cnt
< sizeof(fw
->mailbox_reg
) / 2; cnt
++)
227 fw
->mailbox_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
229 WRT_REG_WORD(®
->ctrl_status
, 0x40);
230 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
231 for (cnt
= 0; cnt
< sizeof(fw
->resp_dma_reg
) / 2; cnt
++)
232 fw
->resp_dma_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
234 WRT_REG_WORD(®
->ctrl_status
, 0x50);
235 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
236 for (cnt
= 0; cnt
< sizeof(fw
->dma_reg
) / 2; cnt
++)
237 fw
->dma_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
239 WRT_REG_WORD(®
->ctrl_status
, 0x00);
240 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0xA0);
241 for (cnt
= 0; cnt
< sizeof(fw
->risc_hdw_reg
) / 2; cnt
++)
242 fw
->risc_hdw_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
244 WRT_REG_WORD(®
->pcr
, 0x2000);
245 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
246 for (cnt
= 0; cnt
< sizeof(fw
->risc_gp0_reg
) / 2; cnt
++)
247 fw
->risc_gp0_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
249 WRT_REG_WORD(®
->pcr
, 0x2200);
250 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
251 for (cnt
= 0; cnt
< sizeof(fw
->risc_gp1_reg
) / 2; cnt
++)
252 fw
->risc_gp1_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
254 WRT_REG_WORD(®
->pcr
, 0x2400);
255 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
256 for (cnt
= 0; cnt
< sizeof(fw
->risc_gp2_reg
) / 2; cnt
++)
257 fw
->risc_gp2_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
259 WRT_REG_WORD(®
->pcr
, 0x2600);
260 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
261 for (cnt
= 0; cnt
< sizeof(fw
->risc_gp3_reg
) / 2; cnt
++)
262 fw
->risc_gp3_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
264 WRT_REG_WORD(®
->pcr
, 0x2800);
265 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
266 for (cnt
= 0; cnt
< sizeof(fw
->risc_gp4_reg
) / 2; cnt
++)
267 fw
->risc_gp4_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
269 WRT_REG_WORD(®
->pcr
, 0x2A00);
270 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
271 for (cnt
= 0; cnt
< sizeof(fw
->risc_gp5_reg
) / 2; cnt
++)
272 fw
->risc_gp5_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
274 WRT_REG_WORD(®
->pcr
, 0x2C00);
275 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
276 for (cnt
= 0; cnt
< sizeof(fw
->risc_gp6_reg
) / 2; cnt
++)
277 fw
->risc_gp6_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
279 WRT_REG_WORD(®
->pcr
, 0x2E00);
280 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
281 for (cnt
= 0; cnt
< sizeof(fw
->risc_gp7_reg
) / 2; cnt
++)
282 fw
->risc_gp7_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
284 WRT_REG_WORD(®
->ctrl_status
, 0x10);
285 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
286 for (cnt
= 0; cnt
< sizeof(fw
->frame_buf_hdw_reg
) / 2; cnt
++)
287 fw
->frame_buf_hdw_reg
[cnt
] =
288 htons(RD_REG_WORD(dmp_reg
++));
290 WRT_REG_WORD(®
->ctrl_status
, 0x20);
291 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
292 for (cnt
= 0; cnt
< sizeof(fw
->fpm_b0_reg
) / 2; cnt
++)
293 fw
->fpm_b0_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
295 WRT_REG_WORD(®
->ctrl_status
, 0x30);
296 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
297 for (cnt
= 0; cnt
< sizeof(fw
->fpm_b1_reg
) / 2; cnt
++)
298 fw
->fpm_b1_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
301 WRT_REG_WORD(®
->ctrl_status
, CSR_ISP_SOFT_RESET
);
302 for (cnt
= 0; cnt
< 30000; cnt
++) {
303 if ((RD_REG_WORD(®
->ctrl_status
) &
304 CSR_ISP_SOFT_RESET
) == 0)
311 if (!IS_QLA2300(ha
)) {
312 for (cnt
= 30000; RD_MAILBOX_REG(ha
, reg
, 0) != 0 &&
313 rval
== QLA_SUCCESS
; cnt
--) {
317 rval
= QLA_FUNCTION_TIMEOUT
;
321 if (rval
== QLA_SUCCESS
) {
323 risc_address
= 0x800;
324 WRT_MAILBOX_REG(ha
, reg
, 0, MBC_READ_RAM_WORD
);
325 clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
);
327 for (cnt
= 0; cnt
< sizeof(fw
->risc_ram
) / 2 && rval
== QLA_SUCCESS
;
328 cnt
++, risc_address
++) {
329 WRT_MAILBOX_REG(ha
, reg
, 1, (uint16_t)risc_address
);
330 WRT_REG_WORD(®
->hccr
, HCCR_SET_HOST_INT
);
332 for (timer
= 6000000; timer
; timer
--) {
333 /* Check for pending interrupts. */
334 stat
= RD_REG_DWORD(®
->u
.isp2300
.host_status
);
335 if (stat
& HSR_RISC_INT
) {
338 if (stat
== 0x1 || stat
== 0x2) {
339 set_bit(MBX_INTERRUPT
,
342 mb0
= RD_MAILBOX_REG(ha
, reg
, 0);
343 mb2
= RD_MAILBOX_REG(ha
, reg
, 2);
345 /* Release mailbox registers. */
346 WRT_REG_WORD(®
->semaphore
, 0);
347 WRT_REG_WORD(®
->hccr
,
349 RD_REG_WORD(®
->hccr
);
351 } else if (stat
== 0x10 || stat
== 0x11) {
352 set_bit(MBX_INTERRUPT
,
355 mb0
= RD_MAILBOX_REG(ha
, reg
, 0);
356 mb2
= RD_MAILBOX_REG(ha
, reg
, 2);
358 WRT_REG_WORD(®
->hccr
,
360 RD_REG_WORD(®
->hccr
);
364 /* clear this intr; it wasn't a mailbox intr */
365 WRT_REG_WORD(®
->hccr
, HCCR_CLR_RISC_INT
);
366 RD_REG_WORD(®
->hccr
);
371 if (test_and_clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
)) {
372 rval
= mb0
& MBS_MASK
;
373 fw
->risc_ram
[cnt
] = htons(mb2
);
375 rval
= QLA_FUNCTION_FAILED
;
379 if (rval
== QLA_SUCCESS
) {
380 /* Get stack SRAM. */
381 risc_address
= 0x10000;
382 WRT_MAILBOX_REG(ha
, reg
, 0, MBC_READ_RAM_EXTENDED
);
383 clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
);
385 for (cnt
= 0; cnt
< sizeof(fw
->stack_ram
) / 2 && rval
== QLA_SUCCESS
;
386 cnt
++, risc_address
++) {
387 WRT_MAILBOX_REG(ha
, reg
, 1, LSW(risc_address
));
388 WRT_MAILBOX_REG(ha
, reg
, 8, MSW(risc_address
));
389 WRT_REG_WORD(®
->hccr
, HCCR_SET_HOST_INT
);
391 for (timer
= 6000000; timer
; timer
--) {
392 /* Check for pending interrupts. */
393 stat
= RD_REG_DWORD(®
->u
.isp2300
.host_status
);
394 if (stat
& HSR_RISC_INT
) {
397 if (stat
== 0x1 || stat
== 0x2) {
398 set_bit(MBX_INTERRUPT
,
401 mb0
= RD_MAILBOX_REG(ha
, reg
, 0);
402 mb2
= RD_MAILBOX_REG(ha
, reg
, 2);
404 /* Release mailbox registers. */
405 WRT_REG_WORD(®
->semaphore
, 0);
406 WRT_REG_WORD(®
->hccr
,
408 RD_REG_WORD(®
->hccr
);
410 } else if (stat
== 0x10 || stat
== 0x11) {
411 set_bit(MBX_INTERRUPT
,
414 mb0
= RD_MAILBOX_REG(ha
, reg
, 0);
415 mb2
= RD_MAILBOX_REG(ha
, reg
, 2);
417 WRT_REG_WORD(®
->hccr
,
419 RD_REG_WORD(®
->hccr
);
423 /* clear this intr; it wasn't a mailbox intr */
424 WRT_REG_WORD(®
->hccr
, HCCR_CLR_RISC_INT
);
425 RD_REG_WORD(®
->hccr
);
430 if (test_and_clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
)) {
431 rval
= mb0
& MBS_MASK
;
432 fw
->stack_ram
[cnt
] = htons(mb2
);
434 rval
= QLA_FUNCTION_FAILED
;
438 if (rval
== QLA_SUCCESS
) {
440 risc_address
= 0x11000;
441 data_ram_cnt
= ha
->fw_memory_size
- risc_address
+ 1;
442 WRT_MAILBOX_REG(ha
, reg
, 0, MBC_READ_RAM_EXTENDED
);
443 clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
);
445 for (cnt
= 0; cnt
< data_ram_cnt
&& rval
== QLA_SUCCESS
;
446 cnt
++, risc_address
++) {
447 WRT_MAILBOX_REG(ha
, reg
, 1, LSW(risc_address
));
448 WRT_MAILBOX_REG(ha
, reg
, 8, MSW(risc_address
));
449 WRT_REG_WORD(®
->hccr
, HCCR_SET_HOST_INT
);
451 for (timer
= 6000000; timer
; timer
--) {
452 /* Check for pending interrupts. */
453 stat
= RD_REG_DWORD(®
->u
.isp2300
.host_status
);
454 if (stat
& HSR_RISC_INT
) {
457 if (stat
== 0x1 || stat
== 0x2) {
458 set_bit(MBX_INTERRUPT
,
461 mb0
= RD_MAILBOX_REG(ha
, reg
, 0);
462 mb2
= RD_MAILBOX_REG(ha
, reg
, 2);
464 /* Release mailbox registers. */
465 WRT_REG_WORD(®
->semaphore
, 0);
466 WRT_REG_WORD(®
->hccr
,
468 RD_REG_WORD(®
->hccr
);
470 } else if (stat
== 0x10 || stat
== 0x11) {
471 set_bit(MBX_INTERRUPT
,
474 mb0
= RD_MAILBOX_REG(ha
, reg
, 0);
475 mb2
= RD_MAILBOX_REG(ha
, reg
, 2);
477 WRT_REG_WORD(®
->hccr
,
479 RD_REG_WORD(®
->hccr
);
483 /* clear this intr; it wasn't a mailbox intr */
484 WRT_REG_WORD(®
->hccr
, HCCR_CLR_RISC_INT
);
485 RD_REG_WORD(®
->hccr
);
490 if (test_and_clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
)) {
491 rval
= mb0
& MBS_MASK
;
492 fw
->data_ram
[cnt
] = htons(mb2
);
494 rval
= QLA_FUNCTION_FAILED
;
498 if (rval
== QLA_SUCCESS
)
499 qla2xxx_copy_queues(ha
, &fw
->data_ram
[cnt
]);
501 if (rval
!= QLA_SUCCESS
) {
502 qla_printk(KERN_WARNING
, ha
,
503 "Failed to dump firmware (%x)!!!\n", rval
);
507 qla_printk(KERN_INFO
, ha
,
508 "Firmware dump saved to temp buffer (%ld/%p).\n",
509 ha
->host_no
, ha
->fw_dump
);
513 qla2300_fw_dump_failed
:
514 if (!hardware_locked
)
515 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
519 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
521 * @hardware_locked: Called with the hardware_lock
524 qla2100_fw_dump(scsi_qla_host_t
*ha
, int hardware_locked
)
528 uint16_t risc_address
;
530 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
531 uint16_t __iomem
*dmp_reg
;
533 struct qla2100_fw_dump
*fw
;
539 if (!hardware_locked
)
540 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
543 qla_printk(KERN_WARNING
, ha
,
544 "No buffer available for dump!!!\n");
545 goto qla2100_fw_dump_failed
;
549 qla_printk(KERN_WARNING
, ha
,
550 "Firmware has been previously dumped (%p) -- ignoring "
551 "request...\n", ha
->fw_dump
);
552 goto qla2100_fw_dump_failed
;
554 fw
= &ha
->fw_dump
->isp
.isp21
;
555 qla2xxx_prep_dump(ha
, ha
->fw_dump
);
558 fw
->hccr
= htons(RD_REG_WORD(®
->hccr
));
561 WRT_REG_WORD(®
->hccr
, HCCR_PAUSE_RISC
);
562 for (cnt
= 30000; (RD_REG_WORD(®
->hccr
) & HCCR_RISC_PAUSE
) == 0 &&
563 rval
== QLA_SUCCESS
; cnt
--) {
567 rval
= QLA_FUNCTION_TIMEOUT
;
569 if (rval
== QLA_SUCCESS
) {
570 dmp_reg
= (uint16_t __iomem
*)(reg
+ 0);
571 for (cnt
= 0; cnt
< sizeof(fw
->pbiu_reg
) / 2; cnt
++)
572 fw
->pbiu_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
574 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x10);
575 for (cnt
= 0; cnt
< ha
->mbx_count
; cnt
++) {
577 dmp_reg
= (uint16_t __iomem
*)
578 ((uint8_t __iomem
*)reg
+ 0xe0);
580 fw
->mailbox_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
583 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x20);
584 for (cnt
= 0; cnt
< sizeof(fw
->dma_reg
) / 2; cnt
++)
585 fw
->dma_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
587 WRT_REG_WORD(®
->ctrl_status
, 0x00);
588 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0xA0);
589 for (cnt
= 0; cnt
< sizeof(fw
->risc_hdw_reg
) / 2; cnt
++)
590 fw
->risc_hdw_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
592 WRT_REG_WORD(®
->pcr
, 0x2000);
593 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
594 for (cnt
= 0; cnt
< sizeof(fw
->risc_gp0_reg
) / 2; cnt
++)
595 fw
->risc_gp0_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
597 WRT_REG_WORD(®
->pcr
, 0x2100);
598 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
599 for (cnt
= 0; cnt
< sizeof(fw
->risc_gp1_reg
) / 2; cnt
++)
600 fw
->risc_gp1_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
602 WRT_REG_WORD(®
->pcr
, 0x2200);
603 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
604 for (cnt
= 0; cnt
< sizeof(fw
->risc_gp2_reg
) / 2; cnt
++)
605 fw
->risc_gp2_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
607 WRT_REG_WORD(®
->pcr
, 0x2300);
608 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
609 for (cnt
= 0; cnt
< sizeof(fw
->risc_gp3_reg
) / 2; cnt
++)
610 fw
->risc_gp3_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
612 WRT_REG_WORD(®
->pcr
, 0x2400);
613 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
614 for (cnt
= 0; cnt
< sizeof(fw
->risc_gp4_reg
) / 2; cnt
++)
615 fw
->risc_gp4_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
617 WRT_REG_WORD(®
->pcr
, 0x2500);
618 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
619 for (cnt
= 0; cnt
< sizeof(fw
->risc_gp5_reg
) / 2; cnt
++)
620 fw
->risc_gp5_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
622 WRT_REG_WORD(®
->pcr
, 0x2600);
623 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
624 for (cnt
= 0; cnt
< sizeof(fw
->risc_gp6_reg
) / 2; cnt
++)
625 fw
->risc_gp6_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
627 WRT_REG_WORD(®
->pcr
, 0x2700);
628 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
629 for (cnt
= 0; cnt
< sizeof(fw
->risc_gp7_reg
) / 2; cnt
++)
630 fw
->risc_gp7_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
632 WRT_REG_WORD(®
->ctrl_status
, 0x10);
633 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
634 for (cnt
= 0; cnt
< sizeof(fw
->frame_buf_hdw_reg
) / 2; cnt
++)
635 fw
->frame_buf_hdw_reg
[cnt
] =
636 htons(RD_REG_WORD(dmp_reg
++));
638 WRT_REG_WORD(®
->ctrl_status
, 0x20);
639 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
640 for (cnt
= 0; cnt
< sizeof(fw
->fpm_b0_reg
) / 2; cnt
++)
641 fw
->fpm_b0_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
643 WRT_REG_WORD(®
->ctrl_status
, 0x30);
644 dmp_reg
= (uint16_t __iomem
*)((uint8_t __iomem
*)reg
+ 0x80);
645 for (cnt
= 0; cnt
< sizeof(fw
->fpm_b1_reg
) / 2; cnt
++)
646 fw
->fpm_b1_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
649 WRT_REG_WORD(®
->ctrl_status
, CSR_ISP_SOFT_RESET
);
652 for (cnt
= 30000; RD_MAILBOX_REG(ha
, reg
, 0) != 0 &&
653 rval
== QLA_SUCCESS
; cnt
--) {
657 rval
= QLA_FUNCTION_TIMEOUT
;
661 if (rval
== QLA_SUCCESS
&& (IS_QLA2200(ha
) || (IS_QLA2100(ha
) &&
662 (RD_REG_WORD(®
->mctr
) & (BIT_1
| BIT_0
)) != 0))) {
664 WRT_REG_WORD(®
->hccr
, HCCR_PAUSE_RISC
);
666 (RD_REG_WORD(®
->hccr
) & HCCR_RISC_PAUSE
) == 0 &&
667 rval
== QLA_SUCCESS
; cnt
--) {
671 rval
= QLA_FUNCTION_TIMEOUT
;
673 if (rval
== QLA_SUCCESS
) {
674 /* Set memory configuration and timing. */
676 WRT_REG_WORD(®
->mctr
, 0xf1);
678 WRT_REG_WORD(®
->mctr
, 0xf2);
679 RD_REG_WORD(®
->mctr
); /* PCI Posting. */
682 WRT_REG_WORD(®
->hccr
, HCCR_RELEASE_RISC
);
686 if (rval
== QLA_SUCCESS
) {
688 risc_address
= 0x1000;
689 WRT_MAILBOX_REG(ha
, reg
, 0, MBC_READ_RAM_WORD
);
690 clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
);
692 for (cnt
= 0; cnt
< sizeof(fw
->risc_ram
) / 2 && rval
== QLA_SUCCESS
;
693 cnt
++, risc_address
++) {
694 WRT_MAILBOX_REG(ha
, reg
, 1, risc_address
);
695 WRT_REG_WORD(®
->hccr
, HCCR_SET_HOST_INT
);
697 for (timer
= 6000000; timer
!= 0; timer
--) {
698 /* Check for pending interrupts. */
699 if (RD_REG_WORD(®
->istatus
) & ISR_RISC_INT
) {
700 if (RD_REG_WORD(®
->semaphore
) & BIT_0
) {
701 set_bit(MBX_INTERRUPT
,
704 mb0
= RD_MAILBOX_REG(ha
, reg
, 0);
705 mb2
= RD_MAILBOX_REG(ha
, reg
, 2);
707 WRT_REG_WORD(®
->semaphore
, 0);
708 WRT_REG_WORD(®
->hccr
,
710 RD_REG_WORD(®
->hccr
);
713 WRT_REG_WORD(®
->hccr
, HCCR_CLR_RISC_INT
);
714 RD_REG_WORD(®
->hccr
);
719 if (test_and_clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
)) {
720 rval
= mb0
& MBS_MASK
;
721 fw
->risc_ram
[cnt
] = htons(mb2
);
723 rval
= QLA_FUNCTION_FAILED
;
727 if (rval
== QLA_SUCCESS
)
728 qla2xxx_copy_queues(ha
, &fw
->risc_ram
[cnt
]);
730 if (rval
!= QLA_SUCCESS
) {
731 qla_printk(KERN_WARNING
, ha
,
732 "Failed to dump firmware (%x)!!!\n", rval
);
736 qla_printk(KERN_INFO
, ha
,
737 "Firmware dump saved to temp buffer (%ld/%p).\n",
738 ha
->host_no
, ha
->fw_dump
);
742 qla2100_fw_dump_failed
:
743 if (!hardware_locked
)
744 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
748 qla24xx_fw_dump(scsi_qla_host_t
*ha
, int hardware_locked
)
752 uint32_t risc_address
;
755 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
756 uint32_t __iomem
*dmp_reg
;
758 uint16_t __iomem
*mbx_reg
;
760 struct qla24xx_fw_dump
*fw
;
761 uint32_t ext_mem_cnt
;
764 risc_address
= ext_mem_cnt
= 0;
767 if (!hardware_locked
)
768 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
771 qla_printk(KERN_WARNING
, ha
,
772 "No buffer available for dump!!!\n");
773 goto qla24xx_fw_dump_failed
;
777 qla_printk(KERN_WARNING
, ha
,
778 "Firmware has been previously dumped (%p) -- ignoring "
779 "request...\n", ha
->fw_dump
);
780 goto qla24xx_fw_dump_failed
;
782 fw
= &ha
->fw_dump
->isp
.isp24
;
783 qla2xxx_prep_dump(ha
, ha
->fw_dump
);
786 fw
->host_status
= htonl(RD_REG_DWORD(®
->host_status
));
789 if ((RD_REG_DWORD(®
->hccr
) & HCCRX_RISC_PAUSE
) == 0) {
790 WRT_REG_DWORD(®
->hccr
, HCCRX_SET_RISC_RESET
|
792 RD_REG_DWORD(®
->hccr
); /* PCI Posting. */
793 WRT_REG_DWORD(®
->hccr
, HCCRX_SET_RISC_PAUSE
);
795 (RD_REG_DWORD(®
->hccr
) & HCCRX_RISC_PAUSE
) == 0 &&
796 rval
== QLA_SUCCESS
; cnt
--) {
800 rval
= QLA_FUNCTION_TIMEOUT
;
804 if (rval
== QLA_SUCCESS
) {
805 /* Host interface registers. */
806 dmp_reg
= (uint32_t __iomem
*)(reg
+ 0);
807 for (cnt
= 0; cnt
< sizeof(fw
->host_reg
) / 4; cnt
++)
808 fw
->host_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
810 /* Disable interrupts. */
811 WRT_REG_DWORD(®
->ictrl
, 0);
812 RD_REG_DWORD(®
->ictrl
);
814 /* Shadow registers. */
815 WRT_REG_DWORD(®
->iobase_addr
, 0x0F70);
816 RD_REG_DWORD(®
->iobase_addr
);
817 WRT_REG_DWORD(®
->iobase_select
, 0xB0000000);
818 fw
->shadow_reg
[0] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
820 WRT_REG_DWORD(®
->iobase_select
, 0xB0100000);
821 fw
->shadow_reg
[1] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
823 WRT_REG_DWORD(®
->iobase_select
, 0xB0200000);
824 fw
->shadow_reg
[2] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
826 WRT_REG_DWORD(®
->iobase_select
, 0xB0300000);
827 fw
->shadow_reg
[3] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
829 WRT_REG_DWORD(®
->iobase_select
, 0xB0400000);
830 fw
->shadow_reg
[4] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
832 WRT_REG_DWORD(®
->iobase_select
, 0xB0500000);
833 fw
->shadow_reg
[5] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
835 WRT_REG_DWORD(®
->iobase_select
, 0xB0600000);
836 fw
->shadow_reg
[6] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
838 /* Mailbox registers. */
839 mbx_reg
= ®
->mailbox0
;
840 for (cnt
= 0; cnt
< sizeof(fw
->mailbox_reg
) / 2; cnt
++)
841 fw
->mailbox_reg
[cnt
] = htons(RD_REG_WORD(mbx_reg
++));
843 /* Transfer sequence registers. */
844 iter_reg
= fw
->xseq_gp_reg
;
845 WRT_REG_DWORD(®
->iobase_addr
, 0xBF00);
846 dmp_reg
= ®
->iobase_window
;
847 for (cnt
= 0; cnt
< 16; cnt
++)
848 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
850 WRT_REG_DWORD(®
->iobase_addr
, 0xBF10);
851 dmp_reg
= ®
->iobase_window
;
852 for (cnt
= 0; cnt
< 16; cnt
++)
853 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
855 WRT_REG_DWORD(®
->iobase_addr
, 0xBF20);
856 dmp_reg
= ®
->iobase_window
;
857 for (cnt
= 0; cnt
< 16; cnt
++)
858 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
860 WRT_REG_DWORD(®
->iobase_addr
, 0xBF30);
861 dmp_reg
= ®
->iobase_window
;
862 for (cnt
= 0; cnt
< 16; cnt
++)
863 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
865 WRT_REG_DWORD(®
->iobase_addr
, 0xBF40);
866 dmp_reg
= ®
->iobase_window
;
867 for (cnt
= 0; cnt
< 16; cnt
++)
868 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
870 WRT_REG_DWORD(®
->iobase_addr
, 0xBF50);
871 dmp_reg
= ®
->iobase_window
;
872 for (cnt
= 0; cnt
< 16; cnt
++)
873 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
875 WRT_REG_DWORD(®
->iobase_addr
, 0xBF60);
876 dmp_reg
= ®
->iobase_window
;
877 for (cnt
= 0; cnt
< 16; cnt
++)
878 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
880 WRT_REG_DWORD(®
->iobase_addr
, 0xBF70);
881 dmp_reg
= ®
->iobase_window
;
882 for (cnt
= 0; cnt
< 16; cnt
++)
883 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
885 WRT_REG_DWORD(®
->iobase_addr
, 0xBFE0);
886 dmp_reg
= ®
->iobase_window
;
887 for (cnt
= 0; cnt
< sizeof(fw
->xseq_0_reg
) / 4; cnt
++)
888 fw
->xseq_0_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
890 WRT_REG_DWORD(®
->iobase_addr
, 0xBFF0);
891 dmp_reg
= ®
->iobase_window
;
892 for (cnt
= 0; cnt
< sizeof(fw
->xseq_1_reg
) / 4; cnt
++)
893 fw
->xseq_1_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
895 /* Receive sequence registers. */
896 iter_reg
= fw
->rseq_gp_reg
;
897 WRT_REG_DWORD(®
->iobase_addr
, 0xFF00);
898 dmp_reg
= ®
->iobase_window
;
899 for (cnt
= 0; cnt
< 16; cnt
++)
900 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
902 WRT_REG_DWORD(®
->iobase_addr
, 0xFF10);
903 dmp_reg
= ®
->iobase_window
;
904 for (cnt
= 0; cnt
< 16; cnt
++)
905 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
907 WRT_REG_DWORD(®
->iobase_addr
, 0xFF20);
908 dmp_reg
= ®
->iobase_window
;
909 for (cnt
= 0; cnt
< 16; cnt
++)
910 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
912 WRT_REG_DWORD(®
->iobase_addr
, 0xFF30);
913 dmp_reg
= ®
->iobase_window
;
914 for (cnt
= 0; cnt
< 16; cnt
++)
915 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
917 WRT_REG_DWORD(®
->iobase_addr
, 0xFF40);
918 dmp_reg
= ®
->iobase_window
;
919 for (cnt
= 0; cnt
< 16; cnt
++)
920 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
922 WRT_REG_DWORD(®
->iobase_addr
, 0xFF50);
923 dmp_reg
= ®
->iobase_window
;
924 for (cnt
= 0; cnt
< 16; cnt
++)
925 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
927 WRT_REG_DWORD(®
->iobase_addr
, 0xFF60);
928 dmp_reg
= ®
->iobase_window
;
929 for (cnt
= 0; cnt
< 16; cnt
++)
930 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
932 WRT_REG_DWORD(®
->iobase_addr
, 0xFF70);
933 dmp_reg
= ®
->iobase_window
;
934 for (cnt
= 0; cnt
< 16; cnt
++)
935 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
937 WRT_REG_DWORD(®
->iobase_addr
, 0xFFD0);
938 dmp_reg
= ®
->iobase_window
;
939 for (cnt
= 0; cnt
< sizeof(fw
->rseq_0_reg
) / 4; cnt
++)
940 fw
->rseq_0_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
942 WRT_REG_DWORD(®
->iobase_addr
, 0xFFE0);
943 dmp_reg
= ®
->iobase_window
;
944 for (cnt
= 0; cnt
< sizeof(fw
->rseq_1_reg
) / 4; cnt
++)
945 fw
->rseq_1_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
947 WRT_REG_DWORD(®
->iobase_addr
, 0xFFF0);
948 dmp_reg
= ®
->iobase_window
;
949 for (cnt
= 0; cnt
< sizeof(fw
->rseq_2_reg
) / 4; cnt
++)
950 fw
->rseq_2_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
952 /* Command DMA registers. */
953 WRT_REG_DWORD(®
->iobase_addr
, 0x7100);
954 dmp_reg
= ®
->iobase_window
;
955 for (cnt
= 0; cnt
< sizeof(fw
->cmd_dma_reg
) / 4; cnt
++)
956 fw
->cmd_dma_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
959 iter_reg
= fw
->req0_dma_reg
;
960 WRT_REG_DWORD(®
->iobase_addr
, 0x7200);
961 dmp_reg
= ®
->iobase_window
;
962 for (cnt
= 0; cnt
< 8; cnt
++)
963 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
965 dmp_reg
= ®
->iobase_q
;
966 for (cnt
= 0; cnt
< 7; cnt
++)
967 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
969 iter_reg
= fw
->resp0_dma_reg
;
970 WRT_REG_DWORD(®
->iobase_addr
, 0x7300);
971 dmp_reg
= ®
->iobase_window
;
972 for (cnt
= 0; cnt
< 8; cnt
++)
973 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
975 dmp_reg
= ®
->iobase_q
;
976 for (cnt
= 0; cnt
< 7; cnt
++)
977 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
979 iter_reg
= fw
->req1_dma_reg
;
980 WRT_REG_DWORD(®
->iobase_addr
, 0x7400);
981 dmp_reg
= ®
->iobase_window
;
982 for (cnt
= 0; cnt
< 8; cnt
++)
983 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
985 dmp_reg
= ®
->iobase_q
;
986 for (cnt
= 0; cnt
< 7; cnt
++)
987 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
989 /* Transmit DMA registers. */
990 iter_reg
= fw
->xmt0_dma_reg
;
991 WRT_REG_DWORD(®
->iobase_addr
, 0x7600);
992 dmp_reg
= ®
->iobase_window
;
993 for (cnt
= 0; cnt
< 16; cnt
++)
994 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
996 WRT_REG_DWORD(®
->iobase_addr
, 0x7610);
997 dmp_reg
= ®
->iobase_window
;
998 for (cnt
= 0; cnt
< 16; cnt
++)
999 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1001 iter_reg
= fw
->xmt1_dma_reg
;
1002 WRT_REG_DWORD(®
->iobase_addr
, 0x7620);
1003 dmp_reg
= ®
->iobase_window
;
1004 for (cnt
= 0; cnt
< 16; cnt
++)
1005 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1007 WRT_REG_DWORD(®
->iobase_addr
, 0x7630);
1008 dmp_reg
= ®
->iobase_window
;
1009 for (cnt
= 0; cnt
< 16; cnt
++)
1010 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1012 iter_reg
= fw
->xmt2_dma_reg
;
1013 WRT_REG_DWORD(®
->iobase_addr
, 0x7640);
1014 dmp_reg
= ®
->iobase_window
;
1015 for (cnt
= 0; cnt
< 16; cnt
++)
1016 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1018 WRT_REG_DWORD(®
->iobase_addr
, 0x7650);
1019 dmp_reg
= ®
->iobase_window
;
1020 for (cnt
= 0; cnt
< 16; cnt
++)
1021 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1023 iter_reg
= fw
->xmt3_dma_reg
;
1024 WRT_REG_DWORD(®
->iobase_addr
, 0x7660);
1025 dmp_reg
= ®
->iobase_window
;
1026 for (cnt
= 0; cnt
< 16; cnt
++)
1027 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1029 WRT_REG_DWORD(®
->iobase_addr
, 0x7670);
1030 dmp_reg
= ®
->iobase_window
;
1031 for (cnt
= 0; cnt
< 16; cnt
++)
1032 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1034 iter_reg
= fw
->xmt4_dma_reg
;
1035 WRT_REG_DWORD(®
->iobase_addr
, 0x7680);
1036 dmp_reg
= ®
->iobase_window
;
1037 for (cnt
= 0; cnt
< 16; cnt
++)
1038 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1040 WRT_REG_DWORD(®
->iobase_addr
, 0x7690);
1041 dmp_reg
= ®
->iobase_window
;
1042 for (cnt
= 0; cnt
< 16; cnt
++)
1043 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1045 WRT_REG_DWORD(®
->iobase_addr
, 0x76A0);
1046 dmp_reg
= ®
->iobase_window
;
1047 for (cnt
= 0; cnt
< sizeof(fw
->xmt_data_dma_reg
) / 4; cnt
++)
1048 fw
->xmt_data_dma_reg
[cnt
] =
1049 htonl(RD_REG_DWORD(dmp_reg
++));
1051 /* Receive DMA registers. */
1052 iter_reg
= fw
->rcvt0_data_dma_reg
;
1053 WRT_REG_DWORD(®
->iobase_addr
, 0x7700);
1054 dmp_reg
= ®
->iobase_window
;
1055 for (cnt
= 0; cnt
< 16; cnt
++)
1056 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1058 WRT_REG_DWORD(®
->iobase_addr
, 0x7710);
1059 dmp_reg
= ®
->iobase_window
;
1060 for (cnt
= 0; cnt
< 16; cnt
++)
1061 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1063 iter_reg
= fw
->rcvt1_data_dma_reg
;
1064 WRT_REG_DWORD(®
->iobase_addr
, 0x7720);
1065 dmp_reg
= ®
->iobase_window
;
1066 for (cnt
= 0; cnt
< 16; cnt
++)
1067 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1069 WRT_REG_DWORD(®
->iobase_addr
, 0x7730);
1070 dmp_reg
= ®
->iobase_window
;
1071 for (cnt
= 0; cnt
< 16; cnt
++)
1072 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1074 /* RISC registers. */
1075 iter_reg
= fw
->risc_gp_reg
;
1076 WRT_REG_DWORD(®
->iobase_addr
, 0x0F00);
1077 dmp_reg
= ®
->iobase_window
;
1078 for (cnt
= 0; cnt
< 16; cnt
++)
1079 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1081 WRT_REG_DWORD(®
->iobase_addr
, 0x0F10);
1082 dmp_reg
= ®
->iobase_window
;
1083 for (cnt
= 0; cnt
< 16; cnt
++)
1084 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1086 WRT_REG_DWORD(®
->iobase_addr
, 0x0F20);
1087 dmp_reg
= ®
->iobase_window
;
1088 for (cnt
= 0; cnt
< 16; cnt
++)
1089 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1091 WRT_REG_DWORD(®
->iobase_addr
, 0x0F30);
1092 dmp_reg
= ®
->iobase_window
;
1093 for (cnt
= 0; cnt
< 16; cnt
++)
1094 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1096 WRT_REG_DWORD(®
->iobase_addr
, 0x0F40);
1097 dmp_reg
= ®
->iobase_window
;
1098 for (cnt
= 0; cnt
< 16; cnt
++)
1099 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1101 WRT_REG_DWORD(®
->iobase_addr
, 0x0F50);
1102 dmp_reg
= ®
->iobase_window
;
1103 for (cnt
= 0; cnt
< 16; cnt
++)
1104 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1106 WRT_REG_DWORD(®
->iobase_addr
, 0x0F60);
1107 dmp_reg
= ®
->iobase_window
;
1108 for (cnt
= 0; cnt
< 16; cnt
++)
1109 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1111 WRT_REG_DWORD(®
->iobase_addr
, 0x0F70);
1112 dmp_reg
= ®
->iobase_window
;
1113 for (cnt
= 0; cnt
< 16; cnt
++)
1114 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1116 /* Local memory controller registers. */
1117 iter_reg
= fw
->lmc_reg
;
1118 WRT_REG_DWORD(®
->iobase_addr
, 0x3000);
1119 dmp_reg
= ®
->iobase_window
;
1120 for (cnt
= 0; cnt
< 16; cnt
++)
1121 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1123 WRT_REG_DWORD(®
->iobase_addr
, 0x3010);
1124 dmp_reg
= ®
->iobase_window
;
1125 for (cnt
= 0; cnt
< 16; cnt
++)
1126 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1128 WRT_REG_DWORD(®
->iobase_addr
, 0x3020);
1129 dmp_reg
= ®
->iobase_window
;
1130 for (cnt
= 0; cnt
< 16; cnt
++)
1131 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1133 WRT_REG_DWORD(®
->iobase_addr
, 0x3030);
1134 dmp_reg
= ®
->iobase_window
;
1135 for (cnt
= 0; cnt
< 16; cnt
++)
1136 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1138 WRT_REG_DWORD(®
->iobase_addr
, 0x3040);
1139 dmp_reg
= ®
->iobase_window
;
1140 for (cnt
= 0; cnt
< 16; cnt
++)
1141 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1143 WRT_REG_DWORD(®
->iobase_addr
, 0x3050);
1144 dmp_reg
= ®
->iobase_window
;
1145 for (cnt
= 0; cnt
< 16; cnt
++)
1146 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1148 WRT_REG_DWORD(®
->iobase_addr
, 0x3060);
1149 dmp_reg
= ®
->iobase_window
;
1150 for (cnt
= 0; cnt
< 16; cnt
++)
1151 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1153 /* Fibre Protocol Module registers. */
1154 iter_reg
= fw
->fpm_hdw_reg
;
1155 WRT_REG_DWORD(®
->iobase_addr
, 0x4000);
1156 dmp_reg
= ®
->iobase_window
;
1157 for (cnt
= 0; cnt
< 16; cnt
++)
1158 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1160 WRT_REG_DWORD(®
->iobase_addr
, 0x4010);
1161 dmp_reg
= ®
->iobase_window
;
1162 for (cnt
= 0; cnt
< 16; cnt
++)
1163 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1165 WRT_REG_DWORD(®
->iobase_addr
, 0x4020);
1166 dmp_reg
= ®
->iobase_window
;
1167 for (cnt
= 0; cnt
< 16; cnt
++)
1168 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1170 WRT_REG_DWORD(®
->iobase_addr
, 0x4030);
1171 dmp_reg
= ®
->iobase_window
;
1172 for (cnt
= 0; cnt
< 16; cnt
++)
1173 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1175 WRT_REG_DWORD(®
->iobase_addr
, 0x4040);
1176 dmp_reg
= ®
->iobase_window
;
1177 for (cnt
= 0; cnt
< 16; cnt
++)
1178 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1180 WRT_REG_DWORD(®
->iobase_addr
, 0x4050);
1181 dmp_reg
= ®
->iobase_window
;
1182 for (cnt
= 0; cnt
< 16; cnt
++)
1183 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1185 WRT_REG_DWORD(®
->iobase_addr
, 0x4060);
1186 dmp_reg
= ®
->iobase_window
;
1187 for (cnt
= 0; cnt
< 16; cnt
++)
1188 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1190 WRT_REG_DWORD(®
->iobase_addr
, 0x4070);
1191 dmp_reg
= ®
->iobase_window
;
1192 for (cnt
= 0; cnt
< 16; cnt
++)
1193 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1195 WRT_REG_DWORD(®
->iobase_addr
, 0x4080);
1196 dmp_reg
= ®
->iobase_window
;
1197 for (cnt
= 0; cnt
< 16; cnt
++)
1198 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1200 WRT_REG_DWORD(®
->iobase_addr
, 0x4090);
1201 dmp_reg
= ®
->iobase_window
;
1202 for (cnt
= 0; cnt
< 16; cnt
++)
1203 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1205 WRT_REG_DWORD(®
->iobase_addr
, 0x40A0);
1206 dmp_reg
= ®
->iobase_window
;
1207 for (cnt
= 0; cnt
< 16; cnt
++)
1208 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1210 WRT_REG_DWORD(®
->iobase_addr
, 0x40B0);
1211 dmp_reg
= ®
->iobase_window
;
1212 for (cnt
= 0; cnt
< 16; cnt
++)
1213 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1215 /* Frame Buffer registers. */
1216 iter_reg
= fw
->fb_hdw_reg
;
1217 WRT_REG_DWORD(®
->iobase_addr
, 0x6000);
1218 dmp_reg
= ®
->iobase_window
;
1219 for (cnt
= 0; cnt
< 16; cnt
++)
1220 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1222 WRT_REG_DWORD(®
->iobase_addr
, 0x6010);
1223 dmp_reg
= ®
->iobase_window
;
1224 for (cnt
= 0; cnt
< 16; cnt
++)
1225 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1227 WRT_REG_DWORD(®
->iobase_addr
, 0x6020);
1228 dmp_reg
= ®
->iobase_window
;
1229 for (cnt
= 0; cnt
< 16; cnt
++)
1230 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1232 WRT_REG_DWORD(®
->iobase_addr
, 0x6030);
1233 dmp_reg
= ®
->iobase_window
;
1234 for (cnt
= 0; cnt
< 16; cnt
++)
1235 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1237 WRT_REG_DWORD(®
->iobase_addr
, 0x6040);
1238 dmp_reg
= ®
->iobase_window
;
1239 for (cnt
= 0; cnt
< 16; cnt
++)
1240 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1242 WRT_REG_DWORD(®
->iobase_addr
, 0x6100);
1243 dmp_reg
= ®
->iobase_window
;
1244 for (cnt
= 0; cnt
< 16; cnt
++)
1245 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1247 WRT_REG_DWORD(®
->iobase_addr
, 0x6130);
1248 dmp_reg
= ®
->iobase_window
;
1249 for (cnt
= 0; cnt
< 16; cnt
++)
1250 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1252 WRT_REG_DWORD(®
->iobase_addr
, 0x6150);
1253 dmp_reg
= ®
->iobase_window
;
1254 for (cnt
= 0; cnt
< 16; cnt
++)
1255 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1257 WRT_REG_DWORD(®
->iobase_addr
, 0x6170);
1258 dmp_reg
= ®
->iobase_window
;
1259 for (cnt
= 0; cnt
< 16; cnt
++)
1260 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1262 WRT_REG_DWORD(®
->iobase_addr
, 0x6190);
1263 dmp_reg
= ®
->iobase_window
;
1264 for (cnt
= 0; cnt
< 16; cnt
++)
1265 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1267 WRT_REG_DWORD(®
->iobase_addr
, 0x61B0);
1268 dmp_reg
= ®
->iobase_window
;
1269 for (cnt
= 0; cnt
< 16; cnt
++)
1270 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1273 WRT_REG_DWORD(®
->ctrl_status
,
1274 CSRX_DMA_SHUTDOWN
|MWB_4096_BYTES
);
1275 for (cnt
= 0; cnt
< 30000; cnt
++) {
1276 if ((RD_REG_DWORD(®
->ctrl_status
) &
1277 CSRX_DMA_ACTIVE
) == 0)
1283 WRT_REG_DWORD(®
->ctrl_status
,
1284 CSRX_ISP_SOFT_RESET
|CSRX_DMA_SHUTDOWN
|MWB_4096_BYTES
);
1285 pci_read_config_word(ha
->pdev
, PCI_COMMAND
, &wd
);
1288 /* Wait for firmware to complete NVRAM accesses. */
1289 mb0
= (uint32_t) RD_REG_WORD(®
->mailbox0
);
1290 for (cnt
= 10000 ; cnt
&& mb0
; cnt
--) {
1292 mb0
= (uint32_t) RD_REG_WORD(®
->mailbox0
);
1296 /* Wait for soft-reset to complete. */
1297 for (cnt
= 0; cnt
< 30000; cnt
++) {
1298 if ((RD_REG_DWORD(®
->ctrl_status
) &
1299 CSRX_ISP_SOFT_RESET
) == 0)
1304 WRT_REG_DWORD(®
->hccr
, HCCRX_CLR_RISC_RESET
);
1305 RD_REG_DWORD(®
->hccr
); /* PCI Posting. */
1308 for (cnt
= 30000; RD_REG_WORD(®
->mailbox0
) != 0 &&
1309 rval
== QLA_SUCCESS
; cnt
--) {
1313 rval
= QLA_FUNCTION_TIMEOUT
;
1316 if (rval
== QLA_SUCCESS
)
1317 rval
= qla2xxx_dump_memory(ha
, fw
->code_ram
,
1318 sizeof(fw
->code_ram
), fw
->ext_mem
, &nxt
);
1320 if (rval
== QLA_SUCCESS
) {
1321 nxt
= qla2xxx_copy_queues(ha
, nxt
);
1323 memcpy(nxt
, ha
->eft
, ntohl(ha
->fw_dump
->eft_size
));
1326 if (rval
!= QLA_SUCCESS
) {
1327 qla_printk(KERN_WARNING
, ha
,
1328 "Failed to dump firmware (%x)!!!\n", rval
);
1332 qla_printk(KERN_INFO
, ha
,
1333 "Firmware dump saved to temp buffer (%ld/%p).\n",
1334 ha
->host_no
, ha
->fw_dump
);
1338 qla24xx_fw_dump_failed
:
1339 if (!hardware_locked
)
1340 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1344 qla25xx_fw_dump(scsi_qla_host_t
*ha
, int hardware_locked
)
1348 uint32_t risc_address
;
1351 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1352 uint32_t __iomem
*dmp_reg
;
1354 uint16_t __iomem
*mbx_reg
;
1355 unsigned long flags
;
1356 struct qla25xx_fw_dump
*fw
;
1357 uint32_t ext_mem_cnt
;
1360 risc_address
= ext_mem_cnt
= 0;
1363 if (!hardware_locked
)
1364 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1367 qla_printk(KERN_WARNING
, ha
,
1368 "No buffer available for dump!!!\n");
1369 goto qla25xx_fw_dump_failed
;
1372 if (ha
->fw_dumped
) {
1373 qla_printk(KERN_WARNING
, ha
,
1374 "Firmware has been previously dumped (%p) -- ignoring "
1375 "request...\n", ha
->fw_dump
);
1376 goto qla25xx_fw_dump_failed
;
1378 fw
= &ha
->fw_dump
->isp
.isp25
;
1379 qla2xxx_prep_dump(ha
, ha
->fw_dump
);
1382 fw
->host_status
= htonl(RD_REG_DWORD(®
->host_status
));
1385 if ((RD_REG_DWORD(®
->hccr
) & HCCRX_RISC_PAUSE
) == 0) {
1386 WRT_REG_DWORD(®
->hccr
, HCCRX_SET_RISC_RESET
|
1387 HCCRX_CLR_HOST_INT
);
1388 RD_REG_DWORD(®
->hccr
); /* PCI Posting. */
1389 WRT_REG_DWORD(®
->hccr
, HCCRX_SET_RISC_PAUSE
);
1391 (RD_REG_DWORD(®
->hccr
) & HCCRX_RISC_PAUSE
) == 0 &&
1392 rval
== QLA_SUCCESS
; cnt
--) {
1396 rval
= QLA_FUNCTION_TIMEOUT
;
1400 if (rval
== QLA_SUCCESS
) {
1401 /* Host interface registers. */
1402 dmp_reg
= (uint32_t __iomem
*)(reg
+ 0);
1403 for (cnt
= 0; cnt
< sizeof(fw
->host_reg
) / 4; cnt
++)
1404 fw
->host_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
1406 /* Disable interrupts. */
1407 WRT_REG_DWORD(®
->ictrl
, 0);
1408 RD_REG_DWORD(®
->ictrl
);
1410 /* Shadow registers. */
1411 WRT_REG_DWORD(®
->iobase_addr
, 0x0F70);
1412 RD_REG_DWORD(®
->iobase_addr
);
1413 WRT_REG_DWORD(®
->iobase_select
, 0xB0000000);
1414 fw
->shadow_reg
[0] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1416 WRT_REG_DWORD(®
->iobase_select
, 0xB0100000);
1417 fw
->shadow_reg
[1] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1419 WRT_REG_DWORD(®
->iobase_select
, 0xB0200000);
1420 fw
->shadow_reg
[2] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1422 WRT_REG_DWORD(®
->iobase_select
, 0xB0300000);
1423 fw
->shadow_reg
[3] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1425 WRT_REG_DWORD(®
->iobase_select
, 0xB0400000);
1426 fw
->shadow_reg
[4] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1428 WRT_REG_DWORD(®
->iobase_select
, 0xB0500000);
1429 fw
->shadow_reg
[5] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1431 WRT_REG_DWORD(®
->iobase_select
, 0xB0600000);
1432 fw
->shadow_reg
[6] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1434 WRT_REG_DWORD(®
->iobase_select
, 0xB0700000);
1435 fw
->shadow_reg
[7] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1437 WRT_REG_DWORD(®
->iobase_select
, 0xB0800000);
1438 fw
->shadow_reg
[8] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1440 WRT_REG_DWORD(®
->iobase_select
, 0xB0900000);
1441 fw
->shadow_reg
[9] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1443 WRT_REG_DWORD(®
->iobase_select
, 0xB0A00000);
1444 fw
->shadow_reg
[10] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1446 /* RISC I/O register. */
1447 WRT_REG_DWORD(®
->iobase_addr
, 0x0010);
1448 RD_REG_DWORD(®
->iobase_addr
);
1449 fw
->risc_io_reg
= htonl(RD_REG_DWORD(®
->iobase_window
));
1451 /* Mailbox registers. */
1452 mbx_reg
= ®
->mailbox0
;
1453 for (cnt
= 0; cnt
< sizeof(fw
->mailbox_reg
) / 2; cnt
++)
1454 fw
->mailbox_reg
[cnt
] = htons(RD_REG_WORD(mbx_reg
++));
1456 /* Transfer sequence registers. */
1457 iter_reg
= fw
->xseq_gp_reg
;
1458 WRT_REG_DWORD(®
->iobase_addr
, 0xBF00);
1459 dmp_reg
= ®
->iobase_window
;
1460 for (cnt
= 0; cnt
< 16; cnt
++)
1461 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1463 WRT_REG_DWORD(®
->iobase_addr
, 0xBF10);
1464 dmp_reg
= ®
->iobase_window
;
1465 for (cnt
= 0; cnt
< 16; cnt
++)
1466 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1468 WRT_REG_DWORD(®
->iobase_addr
, 0xBF20);
1469 dmp_reg
= ®
->iobase_window
;
1470 for (cnt
= 0; cnt
< 16; cnt
++)
1471 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1473 WRT_REG_DWORD(®
->iobase_addr
, 0xBF30);
1474 dmp_reg
= ®
->iobase_window
;
1475 for (cnt
= 0; cnt
< 16; cnt
++)
1476 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1478 WRT_REG_DWORD(®
->iobase_addr
, 0xBF40);
1479 dmp_reg
= ®
->iobase_window
;
1480 for (cnt
= 0; cnt
< 16; cnt
++)
1481 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1483 WRT_REG_DWORD(®
->iobase_addr
, 0xBF50);
1484 dmp_reg
= ®
->iobase_window
;
1485 for (cnt
= 0; cnt
< 16; cnt
++)
1486 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1488 WRT_REG_DWORD(®
->iobase_addr
, 0xBF60);
1489 dmp_reg
= ®
->iobase_window
;
1490 for (cnt
= 0; cnt
< 16; cnt
++)
1491 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1493 WRT_REG_DWORD(®
->iobase_addr
, 0xBF70);
1494 dmp_reg
= ®
->iobase_window
;
1495 for (cnt
= 0; cnt
< 16; cnt
++)
1496 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1498 iter_reg
= fw
->xseq_0_reg
;
1499 WRT_REG_DWORD(®
->iobase_addr
, 0xBFC0);
1500 dmp_reg
= ®
->iobase_window
;
1501 for (cnt
= 0; cnt
< 16; cnt
++)
1502 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1504 WRT_REG_DWORD(®
->iobase_addr
, 0xBFD0);
1505 dmp_reg
= ®
->iobase_window
;
1506 for (cnt
= 0; cnt
< 16; cnt
++)
1507 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1509 WRT_REG_DWORD(®
->iobase_addr
, 0xBFE0);
1510 dmp_reg
= ®
->iobase_window
;
1511 for (cnt
= 0; cnt
< 16; cnt
++)
1512 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1514 WRT_REG_DWORD(®
->iobase_addr
, 0xBFF0);
1515 dmp_reg
= ®
->iobase_window
;
1516 for (cnt
= 0; cnt
< sizeof(fw
->xseq_1_reg
) / 4; cnt
++)
1517 fw
->xseq_1_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
1519 /* Receive sequence registers. */
1520 iter_reg
= fw
->rseq_gp_reg
;
1521 WRT_REG_DWORD(®
->iobase_addr
, 0xFF00);
1522 dmp_reg
= ®
->iobase_window
;
1523 for (cnt
= 0; cnt
< 16; cnt
++)
1524 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1526 WRT_REG_DWORD(®
->iobase_addr
, 0xFF10);
1527 dmp_reg
= ®
->iobase_window
;
1528 for (cnt
= 0; cnt
< 16; cnt
++)
1529 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1531 WRT_REG_DWORD(®
->iobase_addr
, 0xFF20);
1532 dmp_reg
= ®
->iobase_window
;
1533 for (cnt
= 0; cnt
< 16; cnt
++)
1534 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1536 WRT_REG_DWORD(®
->iobase_addr
, 0xFF30);
1537 dmp_reg
= ®
->iobase_window
;
1538 for (cnt
= 0; cnt
< 16; cnt
++)
1539 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1541 WRT_REG_DWORD(®
->iobase_addr
, 0xFF40);
1542 dmp_reg
= ®
->iobase_window
;
1543 for (cnt
= 0; cnt
< 16; cnt
++)
1544 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1546 WRT_REG_DWORD(®
->iobase_addr
, 0xFF50);
1547 dmp_reg
= ®
->iobase_window
;
1548 for (cnt
= 0; cnt
< 16; cnt
++)
1549 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1551 WRT_REG_DWORD(®
->iobase_addr
, 0xFF60);
1552 dmp_reg
= ®
->iobase_window
;
1553 for (cnt
= 0; cnt
< 16; cnt
++)
1554 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1556 WRT_REG_DWORD(®
->iobase_addr
, 0xFF70);
1557 dmp_reg
= ®
->iobase_window
;
1558 for (cnt
= 0; cnt
< 16; cnt
++)
1559 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1561 iter_reg
= fw
->rseq_0_reg
;
1562 WRT_REG_DWORD(®
->iobase_addr
, 0xFFC0);
1563 dmp_reg
= ®
->iobase_window
;
1564 for (cnt
= 0; cnt
< 16; cnt
++)
1565 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1567 WRT_REG_DWORD(®
->iobase_addr
, 0xFFD0);
1568 dmp_reg
= ®
->iobase_window
;
1569 for (cnt
= 0; cnt
< 16; cnt
++)
1570 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1572 WRT_REG_DWORD(®
->iobase_addr
, 0xFFE0);
1573 dmp_reg
= ®
->iobase_window
;
1574 for (cnt
= 0; cnt
< sizeof(fw
->rseq_1_reg
) / 4; cnt
++)
1575 fw
->rseq_1_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
1577 WRT_REG_DWORD(®
->iobase_addr
, 0xFFF0);
1578 dmp_reg
= ®
->iobase_window
;
1579 for (cnt
= 0; cnt
< sizeof(fw
->rseq_2_reg
) / 4; cnt
++)
1580 fw
->rseq_2_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
1582 /* Auxiliary sequence registers. */
1583 iter_reg
= fw
->aseq_gp_reg
;
1584 WRT_REG_DWORD(®
->iobase_addr
, 0xB000);
1585 dmp_reg
= ®
->iobase_window
;
1586 for (cnt
= 0; cnt
< 16; cnt
++)
1587 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1589 WRT_REG_DWORD(®
->iobase_addr
, 0xB010);
1590 dmp_reg
= ®
->iobase_window
;
1591 for (cnt
= 0; cnt
< 16; cnt
++)
1592 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1594 WRT_REG_DWORD(®
->iobase_addr
, 0xB020);
1595 dmp_reg
= ®
->iobase_window
;
1596 for (cnt
= 0; cnt
< 16; cnt
++)
1597 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1599 WRT_REG_DWORD(®
->iobase_addr
, 0xB030);
1600 dmp_reg
= ®
->iobase_window
;
1601 for (cnt
= 0; cnt
< 16; cnt
++)
1602 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1604 WRT_REG_DWORD(®
->iobase_addr
, 0xB040);
1605 dmp_reg
= ®
->iobase_window
;
1606 for (cnt
= 0; cnt
< 16; cnt
++)
1607 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1609 WRT_REG_DWORD(®
->iobase_addr
, 0xB050);
1610 dmp_reg
= ®
->iobase_window
;
1611 for (cnt
= 0; cnt
< 16; cnt
++)
1612 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1614 WRT_REG_DWORD(®
->iobase_addr
, 0xB060);
1615 dmp_reg
= ®
->iobase_window
;
1616 for (cnt
= 0; cnt
< 16; cnt
++)
1617 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1619 WRT_REG_DWORD(®
->iobase_addr
, 0xB070);
1620 dmp_reg
= ®
->iobase_window
;
1621 for (cnt
= 0; cnt
< 16; cnt
++)
1622 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1624 iter_reg
= fw
->aseq_0_reg
;
1625 WRT_REG_DWORD(®
->iobase_addr
, 0xB0C0);
1626 dmp_reg
= ®
->iobase_window
;
1627 for (cnt
= 0; cnt
< 16; cnt
++)
1628 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1630 WRT_REG_DWORD(®
->iobase_addr
, 0xB0D0);
1631 dmp_reg
= ®
->iobase_window
;
1632 for (cnt
= 0; cnt
< 16; cnt
++)
1633 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1635 WRT_REG_DWORD(®
->iobase_addr
, 0xB0E0);
1636 dmp_reg
= ®
->iobase_window
;
1637 for (cnt
= 0; cnt
< sizeof(fw
->aseq_1_reg
) / 4; cnt
++)
1638 fw
->aseq_1_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
1640 WRT_REG_DWORD(®
->iobase_addr
, 0xB0F0);
1641 dmp_reg
= ®
->iobase_window
;
1642 for (cnt
= 0; cnt
< sizeof(fw
->aseq_2_reg
) / 4; cnt
++)
1643 fw
->aseq_2_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
1645 /* Command DMA registers. */
1646 WRT_REG_DWORD(®
->iobase_addr
, 0x7100);
1647 dmp_reg
= ®
->iobase_window
;
1648 for (cnt
= 0; cnt
< sizeof(fw
->cmd_dma_reg
) / 4; cnt
++)
1649 fw
->cmd_dma_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
1652 iter_reg
= fw
->req0_dma_reg
;
1653 WRT_REG_DWORD(®
->iobase_addr
, 0x7200);
1654 dmp_reg
= ®
->iobase_window
;
1655 for (cnt
= 0; cnt
< 8; cnt
++)
1656 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1658 dmp_reg
= ®
->iobase_q
;
1659 for (cnt
= 0; cnt
< 7; cnt
++)
1660 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1662 iter_reg
= fw
->resp0_dma_reg
;
1663 WRT_REG_DWORD(®
->iobase_addr
, 0x7300);
1664 dmp_reg
= ®
->iobase_window
;
1665 for (cnt
= 0; cnt
< 8; cnt
++)
1666 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1668 dmp_reg
= ®
->iobase_q
;
1669 for (cnt
= 0; cnt
< 7; cnt
++)
1670 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1672 iter_reg
= fw
->req1_dma_reg
;
1673 WRT_REG_DWORD(®
->iobase_addr
, 0x7400);
1674 dmp_reg
= ®
->iobase_window
;
1675 for (cnt
= 0; cnt
< 8; cnt
++)
1676 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1678 dmp_reg
= ®
->iobase_q
;
1679 for (cnt
= 0; cnt
< 7; cnt
++)
1680 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1682 /* Transmit DMA registers. */
1683 iter_reg
= fw
->xmt0_dma_reg
;
1684 WRT_REG_DWORD(®
->iobase_addr
, 0x7600);
1685 dmp_reg
= ®
->iobase_window
;
1686 for (cnt
= 0; cnt
< 16; cnt
++)
1687 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1689 WRT_REG_DWORD(®
->iobase_addr
, 0x7610);
1690 dmp_reg
= ®
->iobase_window
;
1691 for (cnt
= 0; cnt
< 16; cnt
++)
1692 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1694 iter_reg
= fw
->xmt1_dma_reg
;
1695 WRT_REG_DWORD(®
->iobase_addr
, 0x7620);
1696 dmp_reg
= ®
->iobase_window
;
1697 for (cnt
= 0; cnt
< 16; cnt
++)
1698 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1700 WRT_REG_DWORD(®
->iobase_addr
, 0x7630);
1701 dmp_reg
= ®
->iobase_window
;
1702 for (cnt
= 0; cnt
< 16; cnt
++)
1703 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1705 iter_reg
= fw
->xmt2_dma_reg
;
1706 WRT_REG_DWORD(®
->iobase_addr
, 0x7640);
1707 dmp_reg
= ®
->iobase_window
;
1708 for (cnt
= 0; cnt
< 16; cnt
++)
1709 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1711 WRT_REG_DWORD(®
->iobase_addr
, 0x7650);
1712 dmp_reg
= ®
->iobase_window
;
1713 for (cnt
= 0; cnt
< 16; cnt
++)
1714 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1716 iter_reg
= fw
->xmt3_dma_reg
;
1717 WRT_REG_DWORD(®
->iobase_addr
, 0x7660);
1718 dmp_reg
= ®
->iobase_window
;
1719 for (cnt
= 0; cnt
< 16; cnt
++)
1720 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1722 WRT_REG_DWORD(®
->iobase_addr
, 0x7670);
1723 dmp_reg
= ®
->iobase_window
;
1724 for (cnt
= 0; cnt
< 16; cnt
++)
1725 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1727 iter_reg
= fw
->xmt4_dma_reg
;
1728 WRT_REG_DWORD(®
->iobase_addr
, 0x7680);
1729 dmp_reg
= ®
->iobase_window
;
1730 for (cnt
= 0; cnt
< 16; cnt
++)
1731 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1733 WRT_REG_DWORD(®
->iobase_addr
, 0x7690);
1734 dmp_reg
= ®
->iobase_window
;
1735 for (cnt
= 0; cnt
< 16; cnt
++)
1736 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1738 WRT_REG_DWORD(®
->iobase_addr
, 0x76A0);
1739 dmp_reg
= ®
->iobase_window
;
1740 for (cnt
= 0; cnt
< sizeof(fw
->xmt_data_dma_reg
) / 4; cnt
++)
1741 fw
->xmt_data_dma_reg
[cnt
] =
1742 htonl(RD_REG_DWORD(dmp_reg
++));
1744 /* Receive DMA registers. */
1745 iter_reg
= fw
->rcvt0_data_dma_reg
;
1746 WRT_REG_DWORD(®
->iobase_addr
, 0x7700);
1747 dmp_reg
= ®
->iobase_window
;
1748 for (cnt
= 0; cnt
< 16; cnt
++)
1749 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1751 WRT_REG_DWORD(®
->iobase_addr
, 0x7710);
1752 dmp_reg
= ®
->iobase_window
;
1753 for (cnt
= 0; cnt
< 16; cnt
++)
1754 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1756 iter_reg
= fw
->rcvt1_data_dma_reg
;
1757 WRT_REG_DWORD(®
->iobase_addr
, 0x7720);
1758 dmp_reg
= ®
->iobase_window
;
1759 for (cnt
= 0; cnt
< 16; cnt
++)
1760 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1762 WRT_REG_DWORD(®
->iobase_addr
, 0x7730);
1763 dmp_reg
= ®
->iobase_window
;
1764 for (cnt
= 0; cnt
< 16; cnt
++)
1765 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1767 /* RISC registers. */
1768 iter_reg
= fw
->risc_gp_reg
;
1769 WRT_REG_DWORD(®
->iobase_addr
, 0x0F00);
1770 dmp_reg
= ®
->iobase_window
;
1771 for (cnt
= 0; cnt
< 16; cnt
++)
1772 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1774 WRT_REG_DWORD(®
->iobase_addr
, 0x0F10);
1775 dmp_reg
= ®
->iobase_window
;
1776 for (cnt
= 0; cnt
< 16; cnt
++)
1777 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1779 WRT_REG_DWORD(®
->iobase_addr
, 0x0F20);
1780 dmp_reg
= ®
->iobase_window
;
1781 for (cnt
= 0; cnt
< 16; cnt
++)
1782 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1784 WRT_REG_DWORD(®
->iobase_addr
, 0x0F30);
1785 dmp_reg
= ®
->iobase_window
;
1786 for (cnt
= 0; cnt
< 16; cnt
++)
1787 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1789 WRT_REG_DWORD(®
->iobase_addr
, 0x0F40);
1790 dmp_reg
= ®
->iobase_window
;
1791 for (cnt
= 0; cnt
< 16; cnt
++)
1792 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1794 WRT_REG_DWORD(®
->iobase_addr
, 0x0F50);
1795 dmp_reg
= ®
->iobase_window
;
1796 for (cnt
= 0; cnt
< 16; cnt
++)
1797 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1799 WRT_REG_DWORD(®
->iobase_addr
, 0x0F60);
1800 dmp_reg
= ®
->iobase_window
;
1801 for (cnt
= 0; cnt
< 16; cnt
++)
1802 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1804 WRT_REG_DWORD(®
->iobase_addr
, 0x0F70);
1805 dmp_reg
= ®
->iobase_window
;
1806 for (cnt
= 0; cnt
< 16; cnt
++)
1807 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1809 /* Local memory controller registers. */
1810 iter_reg
= fw
->lmc_reg
;
1811 WRT_REG_DWORD(®
->iobase_addr
, 0x3000);
1812 dmp_reg
= ®
->iobase_window
;
1813 for (cnt
= 0; cnt
< 16; cnt
++)
1814 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1816 WRT_REG_DWORD(®
->iobase_addr
, 0x3010);
1817 dmp_reg
= ®
->iobase_window
;
1818 for (cnt
= 0; cnt
< 16; cnt
++)
1819 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1821 WRT_REG_DWORD(®
->iobase_addr
, 0x3020);
1822 dmp_reg
= ®
->iobase_window
;
1823 for (cnt
= 0; cnt
< 16; cnt
++)
1824 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1826 WRT_REG_DWORD(®
->iobase_addr
, 0x3030);
1827 dmp_reg
= ®
->iobase_window
;
1828 for (cnt
= 0; cnt
< 16; cnt
++)
1829 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1831 WRT_REG_DWORD(®
->iobase_addr
, 0x3040);
1832 dmp_reg
= ®
->iobase_window
;
1833 for (cnt
= 0; cnt
< 16; cnt
++)
1834 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1836 WRT_REG_DWORD(®
->iobase_addr
, 0x3050);
1837 dmp_reg
= ®
->iobase_window
;
1838 for (cnt
= 0; cnt
< 16; cnt
++)
1839 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1841 WRT_REG_DWORD(®
->iobase_addr
, 0x3060);
1842 dmp_reg
= ®
->iobase_window
;
1843 for (cnt
= 0; cnt
< 16; cnt
++)
1844 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1846 WRT_REG_DWORD(®
->iobase_addr
, 0x3070);
1847 dmp_reg
= ®
->iobase_window
;
1848 for (cnt
= 0; cnt
< 16; cnt
++)
1849 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1851 /* Fibre Protocol Module registers. */
1852 iter_reg
= fw
->fpm_hdw_reg
;
1853 WRT_REG_DWORD(®
->iobase_addr
, 0x4000);
1854 dmp_reg
= ®
->iobase_window
;
1855 for (cnt
= 0; cnt
< 16; cnt
++)
1856 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1858 WRT_REG_DWORD(®
->iobase_addr
, 0x4010);
1859 dmp_reg
= ®
->iobase_window
;
1860 for (cnt
= 0; cnt
< 16; cnt
++)
1861 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1863 WRT_REG_DWORD(®
->iobase_addr
, 0x4020);
1864 dmp_reg
= ®
->iobase_window
;
1865 for (cnt
= 0; cnt
< 16; cnt
++)
1866 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1868 WRT_REG_DWORD(®
->iobase_addr
, 0x4030);
1869 dmp_reg
= ®
->iobase_window
;
1870 for (cnt
= 0; cnt
< 16; cnt
++)
1871 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1873 WRT_REG_DWORD(®
->iobase_addr
, 0x4040);
1874 dmp_reg
= ®
->iobase_window
;
1875 for (cnt
= 0; cnt
< 16; cnt
++)
1876 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1878 WRT_REG_DWORD(®
->iobase_addr
, 0x4050);
1879 dmp_reg
= ®
->iobase_window
;
1880 for (cnt
= 0; cnt
< 16; cnt
++)
1881 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1883 WRT_REG_DWORD(®
->iobase_addr
, 0x4060);
1884 dmp_reg
= ®
->iobase_window
;
1885 for (cnt
= 0; cnt
< 16; cnt
++)
1886 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1888 WRT_REG_DWORD(®
->iobase_addr
, 0x4070);
1889 dmp_reg
= ®
->iobase_window
;
1890 for (cnt
= 0; cnt
< 16; cnt
++)
1891 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1893 WRT_REG_DWORD(®
->iobase_addr
, 0x4080);
1894 dmp_reg
= ®
->iobase_window
;
1895 for (cnt
= 0; cnt
< 16; cnt
++)
1896 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1898 WRT_REG_DWORD(®
->iobase_addr
, 0x4090);
1899 dmp_reg
= ®
->iobase_window
;
1900 for (cnt
= 0; cnt
< 16; cnt
++)
1901 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1903 WRT_REG_DWORD(®
->iobase_addr
, 0x40A0);
1904 dmp_reg
= ®
->iobase_window
;
1905 for (cnt
= 0; cnt
< 16; cnt
++)
1906 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1908 WRT_REG_DWORD(®
->iobase_addr
, 0x40B0);
1909 dmp_reg
= ®
->iobase_window
;
1910 for (cnt
= 0; cnt
< 16; cnt
++)
1911 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1913 /* Frame Buffer registers. */
1914 iter_reg
= fw
->fb_hdw_reg
;
1915 WRT_REG_DWORD(®
->iobase_addr
, 0x6000);
1916 dmp_reg
= ®
->iobase_window
;
1917 for (cnt
= 0; cnt
< 16; cnt
++)
1918 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1920 WRT_REG_DWORD(®
->iobase_addr
, 0x6010);
1921 dmp_reg
= ®
->iobase_window
;
1922 for (cnt
= 0; cnt
< 16; cnt
++)
1923 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1925 WRT_REG_DWORD(®
->iobase_addr
, 0x6020);
1926 dmp_reg
= ®
->iobase_window
;
1927 for (cnt
= 0; cnt
< 16; cnt
++)
1928 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1930 WRT_REG_DWORD(®
->iobase_addr
, 0x6030);
1931 dmp_reg
= ®
->iobase_window
;
1932 for (cnt
= 0; cnt
< 16; cnt
++)
1933 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1935 WRT_REG_DWORD(®
->iobase_addr
, 0x6040);
1936 dmp_reg
= ®
->iobase_window
;
1937 for (cnt
= 0; cnt
< 16; cnt
++)
1938 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1940 WRT_REG_DWORD(®
->iobase_addr
, 0x6100);
1941 dmp_reg
= ®
->iobase_window
;
1942 for (cnt
= 0; cnt
< 16; cnt
++)
1943 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1945 WRT_REG_DWORD(®
->iobase_addr
, 0x6130);
1946 dmp_reg
= ®
->iobase_window
;
1947 for (cnt
= 0; cnt
< 16; cnt
++)
1948 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1950 WRT_REG_DWORD(®
->iobase_addr
, 0x6150);
1951 dmp_reg
= ®
->iobase_window
;
1952 for (cnt
= 0; cnt
< 16; cnt
++)
1953 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1955 WRT_REG_DWORD(®
->iobase_addr
, 0x6170);
1956 dmp_reg
= ®
->iobase_window
;
1957 for (cnt
= 0; cnt
< 16; cnt
++)
1958 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1960 WRT_REG_DWORD(®
->iobase_addr
, 0x6190);
1961 dmp_reg
= ®
->iobase_window
;
1962 for (cnt
= 0; cnt
< 16; cnt
++)
1963 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1965 WRT_REG_DWORD(®
->iobase_addr
, 0x61B0);
1966 dmp_reg
= ®
->iobase_window
;
1967 for (cnt
= 0; cnt
< 16; cnt
++)
1968 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1970 WRT_REG_DWORD(®
->iobase_addr
, 0x6F00);
1971 dmp_reg
= ®
->iobase_window
;
1972 for (cnt
= 0; cnt
< 16; cnt
++)
1973 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1976 WRT_REG_DWORD(®
->ctrl_status
,
1977 CSRX_DMA_SHUTDOWN
|MWB_4096_BYTES
);
1978 for (cnt
= 0; cnt
< 30000; cnt
++) {
1979 if ((RD_REG_DWORD(®
->ctrl_status
) &
1980 CSRX_DMA_ACTIVE
) == 0)
1986 WRT_REG_DWORD(®
->ctrl_status
,
1987 CSRX_ISP_SOFT_RESET
|CSRX_DMA_SHUTDOWN
|MWB_4096_BYTES
);
1988 pci_read_config_word(ha
->pdev
, PCI_COMMAND
, &wd
);
1991 /* Wait for firmware to complete NVRAM accesses. */
1992 mb0
= (uint32_t) RD_REG_WORD(®
->mailbox0
);
1993 for (cnt
= 10000 ; cnt
&& mb0
; cnt
--) {
1995 mb0
= (uint32_t) RD_REG_WORD(®
->mailbox0
);
1999 /* Wait for soft-reset to complete. */
2000 for (cnt
= 0; cnt
< 30000; cnt
++) {
2001 if ((RD_REG_DWORD(®
->ctrl_status
) &
2002 CSRX_ISP_SOFT_RESET
) == 0)
2007 WRT_REG_DWORD(®
->hccr
, HCCRX_CLR_RISC_RESET
);
2008 RD_REG_DWORD(®
->hccr
); /* PCI Posting. */
2011 for (cnt
= 30000; RD_REG_WORD(®
->mailbox0
) != 0 &&
2012 rval
== QLA_SUCCESS
; cnt
--) {
2016 rval
= QLA_FUNCTION_TIMEOUT
;
2019 if (rval
== QLA_SUCCESS
)
2020 rval
= qla2xxx_dump_memory(ha
, fw
->code_ram
,
2021 sizeof(fw
->code_ram
), fw
->ext_mem
, &nxt
);
2023 if (rval
== QLA_SUCCESS
) {
2024 nxt
= qla2xxx_copy_queues(ha
, nxt
);
2026 memcpy(nxt
, ha
->eft
, ntohl(ha
->fw_dump
->eft_size
));
2029 if (rval
!= QLA_SUCCESS
) {
2030 qla_printk(KERN_WARNING
, ha
,
2031 "Failed to dump firmware (%x)!!!\n", rval
);
2035 qla_printk(KERN_INFO
, ha
,
2036 "Firmware dump saved to temp buffer (%ld/%p).\n",
2037 ha
->host_no
, ha
->fw_dump
);
2041 qla25xx_fw_dump_failed
:
2042 if (!hardware_locked
)
2043 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
2046 /****************************************************************************/
2047 /* Driver Debug Functions. */
2048 /****************************************************************************/
2051 qla2x00_dump_regs(scsi_qla_host_t
*ha
)
2053 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
2055 printk("Mailbox registers:\n");
2056 printk("scsi(%ld): mbox 0 0x%04x \n",
2057 ha
->host_no
, RD_MAILBOX_REG(ha
, reg
, 0));
2058 printk("scsi(%ld): mbox 1 0x%04x \n",
2059 ha
->host_no
, RD_MAILBOX_REG(ha
, reg
, 1));
2060 printk("scsi(%ld): mbox 2 0x%04x \n",
2061 ha
->host_no
, RD_MAILBOX_REG(ha
, reg
, 2));
2062 printk("scsi(%ld): mbox 3 0x%04x \n",
2063 ha
->host_no
, RD_MAILBOX_REG(ha
, reg
, 3));
2064 printk("scsi(%ld): mbox 4 0x%04x \n",
2065 ha
->host_no
, RD_MAILBOX_REG(ha
, reg
, 4));
2066 printk("scsi(%ld): mbox 5 0x%04x \n",
2067 ha
->host_no
, RD_MAILBOX_REG(ha
, reg
, 5));
2072 qla2x00_dump_buffer(uint8_t * b
, uint32_t size
)
2077 printk(" 0 1 2 3 4 5 6 7 8 9 "
2078 "Ah Bh Ch Dh Eh Fh\n");
2079 printk("----------------------------------------"
2080 "----------------------\n");
2082 for (cnt
= 0; cnt
< size
;) {
2084 printk("%02x",(uint32_t) c
);
2095 /**************************************************************************
2096 * qla2x00_print_scsi_cmd
2097 * Dumps out info about the scsi cmd and srb.
2099 * cmd : struct scsi_cmnd
2100 **************************************************************************/
2102 qla2x00_print_scsi_cmd(struct scsi_cmnd
* cmd
)
2105 struct scsi_qla_host
*ha
;
2108 ha
= (struct scsi_qla_host
*)cmd
->device
->host
->hostdata
;
2110 sp
= (srb_t
*) cmd
->SCp
.ptr
;
2111 printk("SCSI Command @=0x%p, Handle=0x%p\n", cmd
, cmd
->host_scribble
);
2112 printk(" chan=0x%02x, target=0x%02x, lun=0x%02x, cmd_len=0x%02x\n",
2113 cmd
->device
->channel
, cmd
->device
->id
, cmd
->device
->lun
,
2116 for (i
= 0; i
< cmd
->cmd_len
; i
++) {
2117 printk("0x%02x ", cmd
->cmnd
[i
]);
2119 printk("\n seg_cnt=%d, allowed=%d, retries=%d\n",
2120 scsi_sg_count(cmd
), cmd
->allowed
, cmd
->retries
);
2121 printk(" request buffer=0x%p, request buffer len=0x%x\n",
2122 scsi_sglist(cmd
), scsi_bufflen(cmd
));
2123 printk(" tag=%d, transfersize=0x%x\n",
2124 cmd
->tag
, cmd
->transfersize
);
2125 printk(" serial_number=%lx, SP=%p\n", cmd
->serial_number
, sp
);
2126 printk(" data direction=%d\n", cmd
->sc_data_direction
);
2131 printk(" sp flags=0x%x\n", sp
->flags
);
2135 qla2x00_dump_pkt(void *pkt
)
2138 uint8_t *data
= (uint8_t *) pkt
;
2140 for (i
= 0; i
< 64; i
++) {
2142 printk("\n%02x: ", i
);
2144 printk("%02x ", data
[i
]);
2149 #if defined(QL_DEBUG_ROUTINES)
2151 * qla2x00_formatted_dump_buffer
2152 * Prints string plus buffer.
2155 * string = Null terminated string (no newline at end).
2156 * buffer = buffer address.
2157 * wd_size = word size 8, 16, 32 or 64 bits
2158 * count = number of words.
2161 qla2x00_formatted_dump_buffer(char *string
, uint8_t * buffer
,
2162 uint8_t wd_size
, uint32_t count
)
2168 if (strcmp(string
, "") != 0)
2169 printk("%s\n",string
);
2173 printk(" 0 1 2 3 4 5 6 7 "
2174 "8 9 Ah Bh Ch Dh Eh Fh\n");
2175 printk("-----------------------------------------"
2176 "-------------------------------------\n");
2178 for (cnt
= 1; cnt
<= count
; cnt
++, buffer
++) {
2179 printk("%02x",*buffer
);
2189 printk(" 0 2 4 6 8 Ah "
2191 printk("-----------------------------------------"
2194 buf16
= (uint16_t *) buffer
;
2195 for (cnt
= 1; cnt
<= count
; cnt
++, buf16
++) {
2196 printk("%4x",*buf16
);
2200 else if (*buf16
< 10)
2209 printk(" 0 4 8 Ch\n");
2210 printk("------------------------------------------\n");
2212 buf32
= (uint32_t *) buffer
;
2213 for (cnt
= 1; cnt
<= count
; cnt
++, buf32
++) {
2214 printk("%8x", *buf32
);
2218 else if (*buf32
< 10)
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