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[SCSI] qla2xxx: Basic infrastructure for dynamic logging.
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_dbg.c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2011 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7
8 /*
9 * Table for showing the current message id in use for particular level
10 * Change this table for addition of log/debug messages.
11 * -----------------------------------------------------
12 * | Level | Last Value Used |
13 * -----------------------------------------------------
14 * | Module Init and Probe | 0x0109 |
15 * | Mailbox commands | 0x1120 |
16 * | Device Discovery | 0x207d |
17 * | Queue Command and IO tracing | 0x304f |
18 * | DPC Thread | 0x401c |
19 * | Async Events | 0x5058 |
20 * | Timer Routines | 0x600d |
21 * | User Space Interactions | 0x70a1 |
22 * | Task Management | 0x8032 |
23 * | AER/EEH | 0x9010 |
24 * | Virtual Port | 0xa007 |
25 * | ISP82XX Specific | 0xb028 |
26 * | MultiQ | 0xc00b |
27 * | Misc | 0xd00b |
28 * -----------------------------------------------------
29 */
30
31 #include "qla_def.h"
32
33 #include <linux/delay.h>
34
35 static uint32_t ql_dbg_offset = 0x800;
36
37 static inline void
38 qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
39 {
40 fw_dump->fw_major_version = htonl(ha->fw_major_version);
41 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
42 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
43 fw_dump->fw_attributes = htonl(ha->fw_attributes);
44
45 fw_dump->vendor = htonl(ha->pdev->vendor);
46 fw_dump->device = htonl(ha->pdev->device);
47 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
48 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
49 }
50
51 static inline void *
52 qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
53 {
54 struct req_que *req = ha->req_q_map[0];
55 struct rsp_que *rsp = ha->rsp_q_map[0];
56 /* Request queue. */
57 memcpy(ptr, req->ring, req->length *
58 sizeof(request_t));
59
60 /* Response queue. */
61 ptr += req->length * sizeof(request_t);
62 memcpy(ptr, rsp->ring, rsp->length *
63 sizeof(response_t));
64
65 return ptr + (rsp->length * sizeof(response_t));
66 }
67
68 static int
69 qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
70 uint32_t ram_dwords, void **nxt)
71 {
72 int rval;
73 uint32_t cnt, stat, timer, dwords, idx;
74 uint16_t mb0;
75 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
76 dma_addr_t dump_dma = ha->gid_list_dma;
77 uint32_t *dump = (uint32_t *)ha->gid_list;
78
79 rval = QLA_SUCCESS;
80 mb0 = 0;
81
82 WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
83 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
84
85 dwords = GID_LIST_SIZE / 4;
86 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
87 cnt += dwords, addr += dwords) {
88 if (cnt + dwords > ram_dwords)
89 dwords = ram_dwords - cnt;
90
91 WRT_REG_WORD(&reg->mailbox1, LSW(addr));
92 WRT_REG_WORD(&reg->mailbox8, MSW(addr));
93
94 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
95 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
96 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
97 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
98
99 WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
100 WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
101 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
102
103 for (timer = 6000000; timer; timer--) {
104 /* Check for pending interrupts. */
105 stat = RD_REG_DWORD(&reg->host_status);
106 if (stat & HSRX_RISC_INT) {
107 stat &= 0xff;
108
109 if (stat == 0x1 || stat == 0x2 ||
110 stat == 0x10 || stat == 0x11) {
111 set_bit(MBX_INTERRUPT,
112 &ha->mbx_cmd_flags);
113
114 mb0 = RD_REG_WORD(&reg->mailbox0);
115
116 WRT_REG_DWORD(&reg->hccr,
117 HCCRX_CLR_RISC_INT);
118 RD_REG_DWORD(&reg->hccr);
119 break;
120 }
121
122 /* Clear this intr; it wasn't a mailbox intr */
123 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
124 RD_REG_DWORD(&reg->hccr);
125 }
126 udelay(5);
127 }
128
129 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
130 rval = mb0 & MBS_MASK;
131 for (idx = 0; idx < dwords; idx++)
132 ram[cnt + idx] = swab32(dump[idx]);
133 } else {
134 rval = QLA_FUNCTION_FAILED;
135 }
136 }
137
138 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
139 return rval;
140 }
141
142 static int
143 qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram,
144 uint32_t cram_size, void **nxt)
145 {
146 int rval;
147
148 /* Code RAM. */
149 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
150 if (rval != QLA_SUCCESS)
151 return rval;
152
153 /* External Memory. */
154 return qla24xx_dump_ram(ha, 0x100000, *nxt,
155 ha->fw_memory_size - 0x100000 + 1, nxt);
156 }
157
158 static uint32_t *
159 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
160 uint32_t count, uint32_t *buf)
161 {
162 uint32_t __iomem *dmp_reg;
163
164 WRT_REG_DWORD(&reg->iobase_addr, iobase);
165 dmp_reg = &reg->iobase_window;
166 while (count--)
167 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
168
169 return buf;
170 }
171
172 static inline int
173 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
174 {
175 int rval = QLA_SUCCESS;
176 uint32_t cnt;
177
178 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
179 for (cnt = 30000;
180 ((RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED) == 0) &&
181 rval == QLA_SUCCESS; cnt--) {
182 if (cnt)
183 udelay(100);
184 else
185 rval = QLA_FUNCTION_TIMEOUT;
186 }
187
188 return rval;
189 }
190
191 static int
192 qla24xx_soft_reset(struct qla_hw_data *ha)
193 {
194 int rval = QLA_SUCCESS;
195 uint32_t cnt;
196 uint16_t mb0, wd;
197 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
198
199 /* Reset RISC. */
200 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
201 for (cnt = 0; cnt < 30000; cnt++) {
202 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
203 break;
204
205 udelay(10);
206 }
207
208 WRT_REG_DWORD(&reg->ctrl_status,
209 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
210 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
211
212 udelay(100);
213 /* Wait for firmware to complete NVRAM accesses. */
214 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
215 for (cnt = 10000 ; cnt && mb0; cnt--) {
216 udelay(5);
217 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
218 barrier();
219 }
220
221 /* Wait for soft-reset to complete. */
222 for (cnt = 0; cnt < 30000; cnt++) {
223 if ((RD_REG_DWORD(&reg->ctrl_status) &
224 CSRX_ISP_SOFT_RESET) == 0)
225 break;
226
227 udelay(10);
228 }
229 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
230 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
231
232 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
233 rval == QLA_SUCCESS; cnt--) {
234 if (cnt)
235 udelay(100);
236 else
237 rval = QLA_FUNCTION_TIMEOUT;
238 }
239
240 return rval;
241 }
242
243 static int
244 qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram,
245 uint32_t ram_words, void **nxt)
246 {
247 int rval;
248 uint32_t cnt, stat, timer, words, idx;
249 uint16_t mb0;
250 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
251 dma_addr_t dump_dma = ha->gid_list_dma;
252 uint16_t *dump = (uint16_t *)ha->gid_list;
253
254 rval = QLA_SUCCESS;
255 mb0 = 0;
256
257 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
258 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
259
260 words = GID_LIST_SIZE / 2;
261 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
262 cnt += words, addr += words) {
263 if (cnt + words > ram_words)
264 words = ram_words - cnt;
265
266 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
267 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
268
269 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
270 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
271 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
272 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
273
274 WRT_MAILBOX_REG(ha, reg, 4, words);
275 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
276
277 for (timer = 6000000; timer; timer--) {
278 /* Check for pending interrupts. */
279 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
280 if (stat & HSR_RISC_INT) {
281 stat &= 0xff;
282
283 if (stat == 0x1 || stat == 0x2) {
284 set_bit(MBX_INTERRUPT,
285 &ha->mbx_cmd_flags);
286
287 mb0 = RD_MAILBOX_REG(ha, reg, 0);
288
289 /* Release mailbox registers. */
290 WRT_REG_WORD(&reg->semaphore, 0);
291 WRT_REG_WORD(&reg->hccr,
292 HCCR_CLR_RISC_INT);
293 RD_REG_WORD(&reg->hccr);
294 break;
295 } else if (stat == 0x10 || stat == 0x11) {
296 set_bit(MBX_INTERRUPT,
297 &ha->mbx_cmd_flags);
298
299 mb0 = RD_MAILBOX_REG(ha, reg, 0);
300
301 WRT_REG_WORD(&reg->hccr,
302 HCCR_CLR_RISC_INT);
303 RD_REG_WORD(&reg->hccr);
304 break;
305 }
306
307 /* clear this intr; it wasn't a mailbox intr */
308 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
309 RD_REG_WORD(&reg->hccr);
310 }
311 udelay(5);
312 }
313
314 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
315 rval = mb0 & MBS_MASK;
316 for (idx = 0; idx < words; idx++)
317 ram[cnt + idx] = swab16(dump[idx]);
318 } else {
319 rval = QLA_FUNCTION_FAILED;
320 }
321 }
322
323 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
324 return rval;
325 }
326
327 static inline void
328 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
329 uint16_t *buf)
330 {
331 uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
332
333 while (count--)
334 *buf++ = htons(RD_REG_WORD(dmp_reg++));
335 }
336
337 static inline void *
338 qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr)
339 {
340 if (!ha->eft)
341 return ptr;
342
343 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
344 return ptr + ntohl(ha->fw_dump->eft_size);
345 }
346
347 static inline void *
348 qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
349 {
350 uint32_t cnt;
351 uint32_t *iter_reg;
352 struct qla2xxx_fce_chain *fcec = ptr;
353
354 if (!ha->fce)
355 return ptr;
356
357 *last_chain = &fcec->type;
358 fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
359 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
360 fce_calc_size(ha->fce_bufs));
361 fcec->size = htonl(fce_calc_size(ha->fce_bufs));
362 fcec->addr_l = htonl(LSD(ha->fce_dma));
363 fcec->addr_h = htonl(MSD(ha->fce_dma));
364
365 iter_reg = fcec->eregs;
366 for (cnt = 0; cnt < 8; cnt++)
367 *iter_reg++ = htonl(ha->fce_mb[cnt]);
368
369 memcpy(iter_reg, ha->fce, ntohl(fcec->size));
370
371 return iter_reg;
372 }
373
374 static inline void *
375 qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
376 {
377 uint32_t cnt, que_idx;
378 uint8_t que_cnt;
379 struct qla2xxx_mq_chain *mq = ptr;
380 struct device_reg_25xxmq __iomem *reg;
381
382 if (!ha->mqenable)
383 return ptr;
384
385 mq = ptr;
386 *last_chain = &mq->type;
387 mq->type = __constant_htonl(DUMP_CHAIN_MQ);
388 mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
389
390 que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
391 ha->max_req_queues : ha->max_rsp_queues;
392 mq->count = htonl(que_cnt);
393 for (cnt = 0; cnt < que_cnt; cnt++) {
394 reg = (struct device_reg_25xxmq *) ((void *)
395 ha->mqiobase + cnt * QLA_QUE_PAGE);
396 que_idx = cnt * 4;
397 mq->qregs[que_idx] = htonl(RD_REG_DWORD(&reg->req_q_in));
398 mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(&reg->req_q_out));
399 mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(&reg->rsp_q_in));
400 mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(&reg->rsp_q_out));
401 }
402
403 return ptr + sizeof(struct qla2xxx_mq_chain);
404 }
405
406 static void
407 qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
408 {
409 struct qla_hw_data *ha = vha->hw;
410
411 if (rval != QLA_SUCCESS) {
412 qla_printk(KERN_WARNING, ha,
413 "Failed to dump firmware (%x)!!!\n", rval);
414 ha->fw_dumped = 0;
415 } else {
416 qla_printk(KERN_INFO, ha,
417 "Firmware dump saved to temp buffer (%ld/%p).\n",
418 vha->host_no, ha->fw_dump);
419 ha->fw_dumped = 1;
420 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
421 }
422 }
423
424 /**
425 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
426 * @ha: HA context
427 * @hardware_locked: Called with the hardware_lock
428 */
429 void
430 qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
431 {
432 int rval;
433 uint32_t cnt;
434 struct qla_hw_data *ha = vha->hw;
435 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
436 uint16_t __iomem *dmp_reg;
437 unsigned long flags;
438 struct qla2300_fw_dump *fw;
439 void *nxt;
440 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
441
442 flags = 0;
443
444 if (!hardware_locked)
445 spin_lock_irqsave(&ha->hardware_lock, flags);
446
447 if (!ha->fw_dump) {
448 qla_printk(KERN_WARNING, ha,
449 "No buffer available for dump!!!\n");
450 goto qla2300_fw_dump_failed;
451 }
452
453 if (ha->fw_dumped) {
454 qla_printk(KERN_WARNING, ha,
455 "Firmware has been previously dumped (%p) -- ignoring "
456 "request...\n", ha->fw_dump);
457 goto qla2300_fw_dump_failed;
458 }
459 fw = &ha->fw_dump->isp.isp23;
460 qla2xxx_prep_dump(ha, ha->fw_dump);
461
462 rval = QLA_SUCCESS;
463 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
464
465 /* Pause RISC. */
466 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
467 if (IS_QLA2300(ha)) {
468 for (cnt = 30000;
469 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
470 rval == QLA_SUCCESS; cnt--) {
471 if (cnt)
472 udelay(100);
473 else
474 rval = QLA_FUNCTION_TIMEOUT;
475 }
476 } else {
477 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
478 udelay(10);
479 }
480
481 if (rval == QLA_SUCCESS) {
482 dmp_reg = &reg->flash_address;
483 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
484 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
485
486 dmp_reg = &reg->u.isp2300.req_q_in;
487 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
488 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
489
490 dmp_reg = &reg->u.isp2300.mailbox0;
491 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
492 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
493
494 WRT_REG_WORD(&reg->ctrl_status, 0x40);
495 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
496
497 WRT_REG_WORD(&reg->ctrl_status, 0x50);
498 qla2xxx_read_window(reg, 48, fw->dma_reg);
499
500 WRT_REG_WORD(&reg->ctrl_status, 0x00);
501 dmp_reg = &reg->risc_hw;
502 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
503 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
504
505 WRT_REG_WORD(&reg->pcr, 0x2000);
506 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
507
508 WRT_REG_WORD(&reg->pcr, 0x2200);
509 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
510
511 WRT_REG_WORD(&reg->pcr, 0x2400);
512 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
513
514 WRT_REG_WORD(&reg->pcr, 0x2600);
515 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
516
517 WRT_REG_WORD(&reg->pcr, 0x2800);
518 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
519
520 WRT_REG_WORD(&reg->pcr, 0x2A00);
521 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
522
523 WRT_REG_WORD(&reg->pcr, 0x2C00);
524 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
525
526 WRT_REG_WORD(&reg->pcr, 0x2E00);
527 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
528
529 WRT_REG_WORD(&reg->ctrl_status, 0x10);
530 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
531
532 WRT_REG_WORD(&reg->ctrl_status, 0x20);
533 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
534
535 WRT_REG_WORD(&reg->ctrl_status, 0x30);
536 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
537
538 /* Reset RISC. */
539 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
540 for (cnt = 0; cnt < 30000; cnt++) {
541 if ((RD_REG_WORD(&reg->ctrl_status) &
542 CSR_ISP_SOFT_RESET) == 0)
543 break;
544
545 udelay(10);
546 }
547 }
548
549 if (!IS_QLA2300(ha)) {
550 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
551 rval == QLA_SUCCESS; cnt--) {
552 if (cnt)
553 udelay(100);
554 else
555 rval = QLA_FUNCTION_TIMEOUT;
556 }
557 }
558
559 /* Get RISC SRAM. */
560 if (rval == QLA_SUCCESS)
561 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
562 sizeof(fw->risc_ram) / 2, &nxt);
563
564 /* Get stack SRAM. */
565 if (rval == QLA_SUCCESS)
566 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
567 sizeof(fw->stack_ram) / 2, &nxt);
568
569 /* Get data SRAM. */
570 if (rval == QLA_SUCCESS)
571 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
572 ha->fw_memory_size - 0x11000 + 1, &nxt);
573
574 if (rval == QLA_SUCCESS)
575 qla2xxx_copy_queues(ha, nxt);
576
577 qla2xxx_dump_post_process(base_vha, rval);
578
579 qla2300_fw_dump_failed:
580 if (!hardware_locked)
581 spin_unlock_irqrestore(&ha->hardware_lock, flags);
582 }
583
584 /**
585 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
586 * @ha: HA context
587 * @hardware_locked: Called with the hardware_lock
588 */
589 void
590 qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
591 {
592 int rval;
593 uint32_t cnt, timer;
594 uint16_t risc_address;
595 uint16_t mb0, mb2;
596 struct qla_hw_data *ha = vha->hw;
597 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
598 uint16_t __iomem *dmp_reg;
599 unsigned long flags;
600 struct qla2100_fw_dump *fw;
601 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
602
603 risc_address = 0;
604 mb0 = mb2 = 0;
605 flags = 0;
606
607 if (!hardware_locked)
608 spin_lock_irqsave(&ha->hardware_lock, flags);
609
610 if (!ha->fw_dump) {
611 qla_printk(KERN_WARNING, ha,
612 "No buffer available for dump!!!\n");
613 goto qla2100_fw_dump_failed;
614 }
615
616 if (ha->fw_dumped) {
617 qla_printk(KERN_WARNING, ha,
618 "Firmware has been previously dumped (%p) -- ignoring "
619 "request...\n", ha->fw_dump);
620 goto qla2100_fw_dump_failed;
621 }
622 fw = &ha->fw_dump->isp.isp21;
623 qla2xxx_prep_dump(ha, ha->fw_dump);
624
625 rval = QLA_SUCCESS;
626 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
627
628 /* Pause RISC. */
629 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
630 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
631 rval == QLA_SUCCESS; cnt--) {
632 if (cnt)
633 udelay(100);
634 else
635 rval = QLA_FUNCTION_TIMEOUT;
636 }
637 if (rval == QLA_SUCCESS) {
638 dmp_reg = &reg->flash_address;
639 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
640 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
641
642 dmp_reg = &reg->u.isp2100.mailbox0;
643 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
644 if (cnt == 8)
645 dmp_reg = &reg->u_end.isp2200.mailbox8;
646
647 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
648 }
649
650 dmp_reg = &reg->u.isp2100.unused_2[0];
651 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
652 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
653
654 WRT_REG_WORD(&reg->ctrl_status, 0x00);
655 dmp_reg = &reg->risc_hw;
656 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
657 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
658
659 WRT_REG_WORD(&reg->pcr, 0x2000);
660 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
661
662 WRT_REG_WORD(&reg->pcr, 0x2100);
663 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
664
665 WRT_REG_WORD(&reg->pcr, 0x2200);
666 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
667
668 WRT_REG_WORD(&reg->pcr, 0x2300);
669 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
670
671 WRT_REG_WORD(&reg->pcr, 0x2400);
672 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
673
674 WRT_REG_WORD(&reg->pcr, 0x2500);
675 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
676
677 WRT_REG_WORD(&reg->pcr, 0x2600);
678 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
679
680 WRT_REG_WORD(&reg->pcr, 0x2700);
681 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
682
683 WRT_REG_WORD(&reg->ctrl_status, 0x10);
684 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
685
686 WRT_REG_WORD(&reg->ctrl_status, 0x20);
687 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
688
689 WRT_REG_WORD(&reg->ctrl_status, 0x30);
690 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
691
692 /* Reset the ISP. */
693 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
694 }
695
696 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
697 rval == QLA_SUCCESS; cnt--) {
698 if (cnt)
699 udelay(100);
700 else
701 rval = QLA_FUNCTION_TIMEOUT;
702 }
703
704 /* Pause RISC. */
705 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
706 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
707
708 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
709 for (cnt = 30000;
710 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
711 rval == QLA_SUCCESS; cnt--) {
712 if (cnt)
713 udelay(100);
714 else
715 rval = QLA_FUNCTION_TIMEOUT;
716 }
717 if (rval == QLA_SUCCESS) {
718 /* Set memory configuration and timing. */
719 if (IS_QLA2100(ha))
720 WRT_REG_WORD(&reg->mctr, 0xf1);
721 else
722 WRT_REG_WORD(&reg->mctr, 0xf2);
723 RD_REG_WORD(&reg->mctr); /* PCI Posting. */
724
725 /* Release RISC. */
726 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
727 }
728 }
729
730 if (rval == QLA_SUCCESS) {
731 /* Get RISC SRAM. */
732 risc_address = 0x1000;
733 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
734 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
735 }
736 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
737 cnt++, risc_address++) {
738 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
739 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
740
741 for (timer = 6000000; timer != 0; timer--) {
742 /* Check for pending interrupts. */
743 if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
744 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
745 set_bit(MBX_INTERRUPT,
746 &ha->mbx_cmd_flags);
747
748 mb0 = RD_MAILBOX_REG(ha, reg, 0);
749 mb2 = RD_MAILBOX_REG(ha, reg, 2);
750
751 WRT_REG_WORD(&reg->semaphore, 0);
752 WRT_REG_WORD(&reg->hccr,
753 HCCR_CLR_RISC_INT);
754 RD_REG_WORD(&reg->hccr);
755 break;
756 }
757 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
758 RD_REG_WORD(&reg->hccr);
759 }
760 udelay(5);
761 }
762
763 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
764 rval = mb0 & MBS_MASK;
765 fw->risc_ram[cnt] = htons(mb2);
766 } else {
767 rval = QLA_FUNCTION_FAILED;
768 }
769 }
770
771 if (rval == QLA_SUCCESS)
772 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
773
774 qla2xxx_dump_post_process(base_vha, rval);
775
776 qla2100_fw_dump_failed:
777 if (!hardware_locked)
778 spin_unlock_irqrestore(&ha->hardware_lock, flags);
779 }
780
781 void
782 qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
783 {
784 int rval;
785 uint32_t cnt;
786 uint32_t risc_address;
787 struct qla_hw_data *ha = vha->hw;
788 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
789 uint32_t __iomem *dmp_reg;
790 uint32_t *iter_reg;
791 uint16_t __iomem *mbx_reg;
792 unsigned long flags;
793 struct qla24xx_fw_dump *fw;
794 uint32_t ext_mem_cnt;
795 void *nxt;
796 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
797
798 if (IS_QLA82XX(ha))
799 return;
800
801 risc_address = ext_mem_cnt = 0;
802 flags = 0;
803
804 if (!hardware_locked)
805 spin_lock_irqsave(&ha->hardware_lock, flags);
806
807 if (!ha->fw_dump) {
808 qla_printk(KERN_WARNING, ha,
809 "No buffer available for dump!!!\n");
810 goto qla24xx_fw_dump_failed;
811 }
812
813 if (ha->fw_dumped) {
814 qla_printk(KERN_WARNING, ha,
815 "Firmware has been previously dumped (%p) -- ignoring "
816 "request...\n", ha->fw_dump);
817 goto qla24xx_fw_dump_failed;
818 }
819 fw = &ha->fw_dump->isp.isp24;
820 qla2xxx_prep_dump(ha, ha->fw_dump);
821
822 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
823
824 /* Pause RISC. */
825 rval = qla24xx_pause_risc(reg);
826 if (rval != QLA_SUCCESS)
827 goto qla24xx_fw_dump_failed_0;
828
829 /* Host interface registers. */
830 dmp_reg = &reg->flash_addr;
831 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
832 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
833
834 /* Disable interrupts. */
835 WRT_REG_DWORD(&reg->ictrl, 0);
836 RD_REG_DWORD(&reg->ictrl);
837
838 /* Shadow registers. */
839 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
840 RD_REG_DWORD(&reg->iobase_addr);
841 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
842 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
843
844 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
845 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
846
847 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
848 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
849
850 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
851 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
852
853 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
854 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
855
856 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
857 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
858
859 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
860 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
861
862 /* Mailbox registers. */
863 mbx_reg = &reg->mailbox0;
864 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
865 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
866
867 /* Transfer sequence registers. */
868 iter_reg = fw->xseq_gp_reg;
869 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
870 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
871 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
872 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
873 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
874 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
875 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
876 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
877
878 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
879 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
880
881 /* Receive sequence registers. */
882 iter_reg = fw->rseq_gp_reg;
883 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
884 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
885 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
886 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
887 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
888 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
889 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
890 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
891
892 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
893 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
894 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
895
896 /* Command DMA registers. */
897 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
898
899 /* Queues. */
900 iter_reg = fw->req0_dma_reg;
901 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
902 dmp_reg = &reg->iobase_q;
903 for (cnt = 0; cnt < 7; cnt++)
904 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
905
906 iter_reg = fw->resp0_dma_reg;
907 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
908 dmp_reg = &reg->iobase_q;
909 for (cnt = 0; cnt < 7; cnt++)
910 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
911
912 iter_reg = fw->req1_dma_reg;
913 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
914 dmp_reg = &reg->iobase_q;
915 for (cnt = 0; cnt < 7; cnt++)
916 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
917
918 /* Transmit DMA registers. */
919 iter_reg = fw->xmt0_dma_reg;
920 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
921 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
922
923 iter_reg = fw->xmt1_dma_reg;
924 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
925 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
926
927 iter_reg = fw->xmt2_dma_reg;
928 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
929 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
930
931 iter_reg = fw->xmt3_dma_reg;
932 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
933 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
934
935 iter_reg = fw->xmt4_dma_reg;
936 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
937 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
938
939 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
940
941 /* Receive DMA registers. */
942 iter_reg = fw->rcvt0_data_dma_reg;
943 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
944 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
945
946 iter_reg = fw->rcvt1_data_dma_reg;
947 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
948 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
949
950 /* RISC registers. */
951 iter_reg = fw->risc_gp_reg;
952 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
953 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
954 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
955 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
956 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
957 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
958 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
959 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
960
961 /* Local memory controller registers. */
962 iter_reg = fw->lmc_reg;
963 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
964 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
965 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
966 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
967 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
968 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
969 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
970
971 /* Fibre Protocol Module registers. */
972 iter_reg = fw->fpm_hdw_reg;
973 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
974 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
975 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
976 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
977 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
978 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
979 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
980 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
981 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
982 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
983 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
984 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
985
986 /* Frame Buffer registers. */
987 iter_reg = fw->fb_hdw_reg;
988 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
989 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
990 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
991 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
992 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
993 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
994 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
995 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
996 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
997 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
998 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
999
1000 rval = qla24xx_soft_reset(ha);
1001 if (rval != QLA_SUCCESS)
1002 goto qla24xx_fw_dump_failed_0;
1003
1004 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1005 &nxt);
1006 if (rval != QLA_SUCCESS)
1007 goto qla24xx_fw_dump_failed_0;
1008
1009 nxt = qla2xxx_copy_queues(ha, nxt);
1010
1011 qla24xx_copy_eft(ha, nxt);
1012
1013 qla24xx_fw_dump_failed_0:
1014 qla2xxx_dump_post_process(base_vha, rval);
1015
1016 qla24xx_fw_dump_failed:
1017 if (!hardware_locked)
1018 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1019 }
1020
1021 void
1022 qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1023 {
1024 int rval;
1025 uint32_t cnt;
1026 uint32_t risc_address;
1027 struct qla_hw_data *ha = vha->hw;
1028 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1029 uint32_t __iomem *dmp_reg;
1030 uint32_t *iter_reg;
1031 uint16_t __iomem *mbx_reg;
1032 unsigned long flags;
1033 struct qla25xx_fw_dump *fw;
1034 uint32_t ext_mem_cnt;
1035 void *nxt, *nxt_chain;
1036 uint32_t *last_chain = NULL;
1037 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1038
1039 risc_address = ext_mem_cnt = 0;
1040 flags = 0;
1041
1042 if (!hardware_locked)
1043 spin_lock_irqsave(&ha->hardware_lock, flags);
1044
1045 if (!ha->fw_dump) {
1046 qla_printk(KERN_WARNING, ha,
1047 "No buffer available for dump!!!\n");
1048 goto qla25xx_fw_dump_failed;
1049 }
1050
1051 if (ha->fw_dumped) {
1052 qla_printk(KERN_WARNING, ha,
1053 "Firmware has been previously dumped (%p) -- ignoring "
1054 "request...\n", ha->fw_dump);
1055 goto qla25xx_fw_dump_failed;
1056 }
1057 fw = &ha->fw_dump->isp.isp25;
1058 qla2xxx_prep_dump(ha, ha->fw_dump);
1059 ha->fw_dump->version = __constant_htonl(2);
1060
1061 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1062
1063 /* Pause RISC. */
1064 rval = qla24xx_pause_risc(reg);
1065 if (rval != QLA_SUCCESS)
1066 goto qla25xx_fw_dump_failed_0;
1067
1068 /* Host/Risc registers. */
1069 iter_reg = fw->host_risc_reg;
1070 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1071 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1072
1073 /* PCIe registers. */
1074 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1075 RD_REG_DWORD(&reg->iobase_addr);
1076 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1077 dmp_reg = &reg->iobase_c4;
1078 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1079 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1080 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1081 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1082
1083 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1084 RD_REG_DWORD(&reg->iobase_window);
1085
1086 /* Host interface registers. */
1087 dmp_reg = &reg->flash_addr;
1088 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1089 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1090
1091 /* Disable interrupts. */
1092 WRT_REG_DWORD(&reg->ictrl, 0);
1093 RD_REG_DWORD(&reg->ictrl);
1094
1095 /* Shadow registers. */
1096 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1097 RD_REG_DWORD(&reg->iobase_addr);
1098 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1099 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1100
1101 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1102 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1103
1104 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1105 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1106
1107 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1108 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1109
1110 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1111 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1112
1113 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1114 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1115
1116 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1117 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1118
1119 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1120 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1121
1122 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1123 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1124
1125 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1126 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1127
1128 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1129 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1130
1131 /* RISC I/O register. */
1132 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1133 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1134
1135 /* Mailbox registers. */
1136 mbx_reg = &reg->mailbox0;
1137 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1138 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1139
1140 /* Transfer sequence registers. */
1141 iter_reg = fw->xseq_gp_reg;
1142 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1143 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1144 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1145 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1146 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1147 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1148 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1149 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1150
1151 iter_reg = fw->xseq_0_reg;
1152 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1153 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1154 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1155
1156 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1157
1158 /* Receive sequence registers. */
1159 iter_reg = fw->rseq_gp_reg;
1160 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1161 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1162 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1163 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1164 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1165 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1166 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1167 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1168
1169 iter_reg = fw->rseq_0_reg;
1170 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1171 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1172
1173 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1174 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1175
1176 /* Auxiliary sequence registers. */
1177 iter_reg = fw->aseq_gp_reg;
1178 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1179 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1180 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1181 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1182 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1183 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1184 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1185 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1186
1187 iter_reg = fw->aseq_0_reg;
1188 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1189 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1190
1191 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1192 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1193
1194 /* Command DMA registers. */
1195 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1196
1197 /* Queues. */
1198 iter_reg = fw->req0_dma_reg;
1199 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1200 dmp_reg = &reg->iobase_q;
1201 for (cnt = 0; cnt < 7; cnt++)
1202 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1203
1204 iter_reg = fw->resp0_dma_reg;
1205 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1206 dmp_reg = &reg->iobase_q;
1207 for (cnt = 0; cnt < 7; cnt++)
1208 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1209
1210 iter_reg = fw->req1_dma_reg;
1211 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1212 dmp_reg = &reg->iobase_q;
1213 for (cnt = 0; cnt < 7; cnt++)
1214 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1215
1216 /* Transmit DMA registers. */
1217 iter_reg = fw->xmt0_dma_reg;
1218 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1219 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1220
1221 iter_reg = fw->xmt1_dma_reg;
1222 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1223 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1224
1225 iter_reg = fw->xmt2_dma_reg;
1226 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1227 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1228
1229 iter_reg = fw->xmt3_dma_reg;
1230 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1231 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1232
1233 iter_reg = fw->xmt4_dma_reg;
1234 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1235 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1236
1237 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1238
1239 /* Receive DMA registers. */
1240 iter_reg = fw->rcvt0_data_dma_reg;
1241 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1242 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1243
1244 iter_reg = fw->rcvt1_data_dma_reg;
1245 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1246 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1247
1248 /* RISC registers. */
1249 iter_reg = fw->risc_gp_reg;
1250 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1251 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1252 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1253 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1254 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1255 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1256 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1257 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1258
1259 /* Local memory controller registers. */
1260 iter_reg = fw->lmc_reg;
1261 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1262 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1263 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1264 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1265 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1266 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1267 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1268 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1269
1270 /* Fibre Protocol Module registers. */
1271 iter_reg = fw->fpm_hdw_reg;
1272 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1273 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1274 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1275 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1276 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1277 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1278 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1279 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1280 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1281 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1282 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1283 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1284
1285 /* Frame Buffer registers. */
1286 iter_reg = fw->fb_hdw_reg;
1287 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1288 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1289 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1290 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1291 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1292 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1293 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1294 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1295 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1296 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1297 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1298 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1299
1300 /* Multi queue registers */
1301 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1302 &last_chain);
1303
1304 rval = qla24xx_soft_reset(ha);
1305 if (rval != QLA_SUCCESS)
1306 goto qla25xx_fw_dump_failed_0;
1307
1308 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1309 &nxt);
1310 if (rval != QLA_SUCCESS)
1311 goto qla25xx_fw_dump_failed_0;
1312
1313 nxt = qla2xxx_copy_queues(ha, nxt);
1314
1315 nxt = qla24xx_copy_eft(ha, nxt);
1316
1317 /* Chain entries -- started with MQ. */
1318 qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1319 if (last_chain) {
1320 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1321 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1322 }
1323
1324 qla25xx_fw_dump_failed_0:
1325 qla2xxx_dump_post_process(base_vha, rval);
1326
1327 qla25xx_fw_dump_failed:
1328 if (!hardware_locked)
1329 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1330 }
1331
1332 void
1333 qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1334 {
1335 int rval;
1336 uint32_t cnt;
1337 uint32_t risc_address;
1338 struct qla_hw_data *ha = vha->hw;
1339 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1340 uint32_t __iomem *dmp_reg;
1341 uint32_t *iter_reg;
1342 uint16_t __iomem *mbx_reg;
1343 unsigned long flags;
1344 struct qla81xx_fw_dump *fw;
1345 uint32_t ext_mem_cnt;
1346 void *nxt, *nxt_chain;
1347 uint32_t *last_chain = NULL;
1348 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1349
1350 risc_address = ext_mem_cnt = 0;
1351 flags = 0;
1352
1353 if (!hardware_locked)
1354 spin_lock_irqsave(&ha->hardware_lock, flags);
1355
1356 if (!ha->fw_dump) {
1357 qla_printk(KERN_WARNING, ha,
1358 "No buffer available for dump!!!\n");
1359 goto qla81xx_fw_dump_failed;
1360 }
1361
1362 if (ha->fw_dumped) {
1363 qla_printk(KERN_WARNING, ha,
1364 "Firmware has been previously dumped (%p) -- ignoring "
1365 "request...\n", ha->fw_dump);
1366 goto qla81xx_fw_dump_failed;
1367 }
1368 fw = &ha->fw_dump->isp.isp81;
1369 qla2xxx_prep_dump(ha, ha->fw_dump);
1370
1371 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1372
1373 /* Pause RISC. */
1374 rval = qla24xx_pause_risc(reg);
1375 if (rval != QLA_SUCCESS)
1376 goto qla81xx_fw_dump_failed_0;
1377
1378 /* Host/Risc registers. */
1379 iter_reg = fw->host_risc_reg;
1380 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1381 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1382
1383 /* PCIe registers. */
1384 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1385 RD_REG_DWORD(&reg->iobase_addr);
1386 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1387 dmp_reg = &reg->iobase_c4;
1388 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1389 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1390 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1391 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1392
1393 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1394 RD_REG_DWORD(&reg->iobase_window);
1395
1396 /* Host interface registers. */
1397 dmp_reg = &reg->flash_addr;
1398 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1399 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1400
1401 /* Disable interrupts. */
1402 WRT_REG_DWORD(&reg->ictrl, 0);
1403 RD_REG_DWORD(&reg->ictrl);
1404
1405 /* Shadow registers. */
1406 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1407 RD_REG_DWORD(&reg->iobase_addr);
1408 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1409 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1410
1411 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1412 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1413
1414 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1415 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1416
1417 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1418 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1419
1420 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1421 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1422
1423 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1424 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1425
1426 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1427 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1428
1429 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1430 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1431
1432 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1433 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1434
1435 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1436 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1437
1438 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1439 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1440
1441 /* RISC I/O register. */
1442 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1443 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1444
1445 /* Mailbox registers. */
1446 mbx_reg = &reg->mailbox0;
1447 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1448 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1449
1450 /* Transfer sequence registers. */
1451 iter_reg = fw->xseq_gp_reg;
1452 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1453 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1454 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1455 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1456 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1457 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1458 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1459 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1460
1461 iter_reg = fw->xseq_0_reg;
1462 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1463 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1464 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1465
1466 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1467
1468 /* Receive sequence registers. */
1469 iter_reg = fw->rseq_gp_reg;
1470 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1471 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1472 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1473 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1474 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1475 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1476 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1477 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1478
1479 iter_reg = fw->rseq_0_reg;
1480 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1481 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1482
1483 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1484 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1485
1486 /* Auxiliary sequence registers. */
1487 iter_reg = fw->aseq_gp_reg;
1488 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1489 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1490 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1491 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1492 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1493 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1494 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1495 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1496
1497 iter_reg = fw->aseq_0_reg;
1498 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1499 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1500
1501 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1502 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1503
1504 /* Command DMA registers. */
1505 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1506
1507 /* Queues. */
1508 iter_reg = fw->req0_dma_reg;
1509 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1510 dmp_reg = &reg->iobase_q;
1511 for (cnt = 0; cnt < 7; cnt++)
1512 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1513
1514 iter_reg = fw->resp0_dma_reg;
1515 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1516 dmp_reg = &reg->iobase_q;
1517 for (cnt = 0; cnt < 7; cnt++)
1518 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1519
1520 iter_reg = fw->req1_dma_reg;
1521 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1522 dmp_reg = &reg->iobase_q;
1523 for (cnt = 0; cnt < 7; cnt++)
1524 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1525
1526 /* Transmit DMA registers. */
1527 iter_reg = fw->xmt0_dma_reg;
1528 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1529 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1530
1531 iter_reg = fw->xmt1_dma_reg;
1532 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1533 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1534
1535 iter_reg = fw->xmt2_dma_reg;
1536 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1537 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1538
1539 iter_reg = fw->xmt3_dma_reg;
1540 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1541 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1542
1543 iter_reg = fw->xmt4_dma_reg;
1544 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1545 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1546
1547 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1548
1549 /* Receive DMA registers. */
1550 iter_reg = fw->rcvt0_data_dma_reg;
1551 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1552 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1553
1554 iter_reg = fw->rcvt1_data_dma_reg;
1555 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1556 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1557
1558 /* RISC registers. */
1559 iter_reg = fw->risc_gp_reg;
1560 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1561 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1562 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1563 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1564 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1565 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1566 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1567 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1568
1569 /* Local memory controller registers. */
1570 iter_reg = fw->lmc_reg;
1571 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1572 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1573 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1574 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1575 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1576 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1577 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1578 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1579
1580 /* Fibre Protocol Module registers. */
1581 iter_reg = fw->fpm_hdw_reg;
1582 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1583 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1584 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1585 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1586 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1587 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1588 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1589 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1590 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1591 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1592 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1593 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1594 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
1595 qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
1596
1597 /* Frame Buffer registers. */
1598 iter_reg = fw->fb_hdw_reg;
1599 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1600 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1601 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1602 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1603 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1604 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1605 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1606 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1607 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1608 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1609 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1610 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
1611 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1612
1613 /* Multi queue registers */
1614 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1615 &last_chain);
1616
1617 rval = qla24xx_soft_reset(ha);
1618 if (rval != QLA_SUCCESS)
1619 goto qla81xx_fw_dump_failed_0;
1620
1621 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1622 &nxt);
1623 if (rval != QLA_SUCCESS)
1624 goto qla81xx_fw_dump_failed_0;
1625
1626 nxt = qla2xxx_copy_queues(ha, nxt);
1627
1628 nxt = qla24xx_copy_eft(ha, nxt);
1629
1630 /* Chain entries -- started with MQ. */
1631 qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1632 if (last_chain) {
1633 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1634 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1635 }
1636
1637 qla81xx_fw_dump_failed_0:
1638 qla2xxx_dump_post_process(base_vha, rval);
1639
1640 qla81xx_fw_dump_failed:
1641 if (!hardware_locked)
1642 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1643 }
1644
1645 /****************************************************************************/
1646 /* Driver Debug Functions. */
1647 /****************************************************************************/
1648
1649 void
1650 qla2x00_dump_regs(scsi_qla_host_t *vha)
1651 {
1652 int i;
1653 struct qla_hw_data *ha = vha->hw;
1654 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1655 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
1656 uint16_t __iomem *mbx_reg;
1657
1658 mbx_reg = IS_FWI2_CAPABLE(ha) ? &reg24->mailbox0:
1659 MAILBOX_REG(ha, reg, 0);
1660
1661 printk("Mailbox registers:\n");
1662 for (i = 0; i < 6; i++)
1663 printk("scsi(%ld): mbox %d 0x%04x \n", vha->host_no, i,
1664 RD_REG_WORD(mbx_reg++));
1665 }
1666
1667
1668 void
1669 qla2x00_dump_buffer(uint8_t * b, uint32_t size)
1670 {
1671 uint32_t cnt;
1672 uint8_t c;
1673
1674 printk(" 0 1 2 3 4 5 6 7 8 9 "
1675 "Ah Bh Ch Dh Eh Fh\n");
1676 printk("----------------------------------------"
1677 "----------------------\n");
1678
1679 for (cnt = 0; cnt < size;) {
1680 c = *b++;
1681 printk("%02x",(uint32_t) c);
1682 cnt++;
1683 if (!(cnt % 16))
1684 printk("\n");
1685 else
1686 printk(" ");
1687 }
1688 if (cnt % 16)
1689 printk("\n");
1690 }
1691
1692 void
1693 qla2x00_dump_buffer_zipped(uint8_t *b, uint32_t size)
1694 {
1695 uint32_t cnt;
1696 uint8_t c;
1697 uint8_t last16[16], cur16[16];
1698 uint32_t lc = 0, num_same16 = 0, j;
1699
1700 printk(KERN_DEBUG " 0 1 2 3 4 5 6 7 8 9 "
1701 "Ah Bh Ch Dh Eh Fh\n");
1702 printk(KERN_DEBUG "----------------------------------------"
1703 "----------------------\n");
1704
1705 for (cnt = 0; cnt < size;) {
1706 c = *b++;
1707
1708 cur16[lc++] = c;
1709
1710 cnt++;
1711 if (cnt % 16)
1712 continue;
1713
1714 /* We have 16 now */
1715 lc = 0;
1716 if (num_same16 == 0) {
1717 memcpy(last16, cur16, 16);
1718 num_same16++;
1719 continue;
1720 }
1721 if (memcmp(cur16, last16, 16) == 0) {
1722 num_same16++;
1723 continue;
1724 }
1725 for (j = 0; j < 16; j++)
1726 printk(KERN_DEBUG "%02x ", (uint32_t)last16[j]);
1727 printk(KERN_DEBUG "\n");
1728
1729 if (num_same16 > 1)
1730 printk(KERN_DEBUG "> prev pattern repeats (%u)"
1731 "more times\n", num_same16-1);
1732 memcpy(last16, cur16, 16);
1733 num_same16 = 1;
1734 }
1735
1736 if (num_same16) {
1737 for (j = 0; j < 16; j++)
1738 printk(KERN_DEBUG "%02x ", (uint32_t)last16[j]);
1739 printk(KERN_DEBUG "\n");
1740
1741 if (num_same16 > 1)
1742 printk(KERN_DEBUG "> prev pattern repeats (%u)"
1743 "more times\n", num_same16-1);
1744 }
1745 if (lc) {
1746 for (j = 0; j < lc; j++)
1747 printk(KERN_DEBUG "%02x ", (uint32_t)cur16[j]);
1748 printk(KERN_DEBUG "\n");
1749 }
1750 }
1751 /*
1752 * This function is for formatting and logging debug information.
1753 * It is to be used when vha is available. It formats the message
1754 * and logs it to the messages file.
1755 * parameters:
1756 * level: The level of the debug messages to be printed.
1757 * If ql2xextended_error_logging value is correctly set,
1758 * this message will appear in the messages file.
1759 * vha: Pointer to the scsi_qla_host_t.
1760 * id: This is a unique identifier for the level. It identifies the
1761 * part of the code from where the message originated.
1762 * msg: The message to be displayed.
1763 */
1764 void
1765 ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, char *msg, ...) {
1766
1767 char pbuf[QL_DBG_BUF_LEN];
1768 va_list ap;
1769 uint32_t len;
1770 struct pci_dev *pdev = NULL;
1771
1772 memset(pbuf, 0, QL_DBG_BUF_LEN);
1773
1774 va_start(ap, msg);
1775
1776 if ((level & ql2xextended_error_logging) == level) {
1777 if (vha != NULL) {
1778 pdev = vha->hw->pdev;
1779 /* <module-name> <pci-name> <msg-id>:<host> Message */
1780 sprintf(pbuf, "%s [%s]-%04x:%ld: ", QL_MSGHDR,
1781 dev_name(&(pdev->dev)), id + ql_dbg_offset,
1782 vha->host_no);
1783 } else
1784 sprintf(pbuf, "%s [%s]-%04x: : ", QL_MSGHDR,
1785 "0000:00:00.0", id + ql_dbg_offset);
1786
1787 len = strlen(pbuf);
1788 vsprintf(pbuf+len, msg, ap);
1789 pr_warning("%s", pbuf);
1790 }
1791
1792 va_end(ap);
1793
1794 }
1795
1796 /*
1797 * This function is for formatting and logging debug information.
1798 * It is to be used when vha is not available and pci is availble,
1799 * i.e., before host allocation. It formats the message and logs it
1800 * to the messages file.
1801 * parameters:
1802 * level: The level of the debug messages to be printed.
1803 * If ql2xextended_error_logging value is correctly set,
1804 * this message will appear in the messages file.
1805 * pdev: Pointer to the struct pci_dev.
1806 * id: This is a unique id for the level. It identifies the part
1807 * of the code from where the message originated.
1808 * msg: The message to be displayed.
1809 */
1810 void
1811 ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id, char *msg, ...) {
1812
1813 char pbuf[QL_DBG_BUF_LEN];
1814 va_list ap;
1815 uint32_t len;
1816
1817 if (pdev == NULL)
1818 return;
1819
1820 memset(pbuf, 0, QL_DBG_BUF_LEN);
1821
1822 va_start(ap, msg);
1823
1824 if ((level & ql2xextended_error_logging) == level) {
1825 /* <module-name> <dev-name>:<msg-id> Message */
1826 sprintf(pbuf, "%s [%s]-%04x: : ", QL_MSGHDR,
1827 dev_name(&(pdev->dev)), id + ql_dbg_offset);
1828
1829 len = strlen(pbuf);
1830 vsprintf(pbuf+len, msg, ap);
1831 pr_warning("%s", pbuf);
1832 }
1833
1834 va_end(ap);
1835
1836 }
1837
1838 /*
1839 * This function is for formatting and logging log messages.
1840 * It is to be used when vha is available. It formats the message
1841 * and logs it to the messages file. All the messages will be logged
1842 * irrespective of value of ql2xextended_error_logging.
1843 * parameters:
1844 * level: The level of the log messages to be printed in the
1845 * messages file.
1846 * vha: Pointer to the scsi_qla_host_t
1847 * id: This is a unique id for the level. It identifies the
1848 * part of the code from where the message originated.
1849 * msg: The message to be displayed.
1850 */
1851 void
1852 ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, char *msg, ...) {
1853
1854 char pbuf[QL_DBG_BUF_LEN];
1855 va_list ap;
1856 uint32_t len;
1857 struct pci_dev *pdev = NULL;
1858
1859 memset(pbuf, 0, QL_DBG_BUF_LEN);
1860
1861 va_start(ap, msg);
1862
1863 if (level <= ql_errlev) {
1864 if (vha != NULL) {
1865 pdev = vha->hw->pdev;
1866 /* <module-name> <msg-id>:<host> Message */
1867 sprintf(pbuf, "%s [%s]-%04x:%ld: ", QL_MSGHDR,
1868 dev_name(&(pdev->dev)), id, vha->host_no);
1869 } else
1870 sprintf(pbuf, "%s [%s]-%04x: : ", QL_MSGHDR,
1871 "0000:00:00.0", id);
1872
1873 len = strlen(pbuf);
1874 vsprintf(pbuf+len, msg, ap);
1875
1876 switch (level) {
1877 case 0: /* FATAL LOG */
1878 pr_crit("%s", pbuf);
1879 break;
1880 case 1:
1881 pr_err("%s", pbuf);
1882 break;
1883 case 2:
1884 pr_warn("%s", pbuf);
1885 break;
1886 default:
1887 pr_info("%s", pbuf);
1888 break;
1889 }
1890 }
1891
1892 va_end(ap);
1893 }
1894
1895 /*
1896 * This function is for formatting and logging log messages.
1897 * It is to be used when vha is not available and pci is availble,
1898 * i.e., before host allocation. It formats the message and logs
1899 * it to the messages file. All the messages are logged irrespective
1900 * of the value of ql2xextended_error_logging.
1901 * parameters:
1902 * level: The level of the log messages to be printed in the
1903 * messages file.
1904 * pdev: Pointer to the struct pci_dev.
1905 * id: This is a unique id for the level. It identifies the
1906 * part of the code from where the message originated.
1907 * msg: The message to be displayed.
1908 */
1909 void
1910 ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id, char *msg, ...) {
1911
1912 char pbuf[QL_DBG_BUF_LEN];
1913 va_list ap;
1914 uint32_t len;
1915
1916 if (pdev == NULL)
1917 return;
1918
1919 memset(pbuf, 0, QL_DBG_BUF_LEN);
1920
1921 va_start(ap, msg);
1922
1923 if (level <= ql_errlev) {
1924 /* <module-name> <dev-name>:<msg-id> Message */
1925 sprintf(pbuf, "%s [%s]-%04x: : ", QL_MSGHDR,
1926 dev_name(&(pdev->dev)), id);
1927
1928 len = strlen(pbuf);
1929 vsprintf(pbuf+len, msg, ap);
1930 switch (level) {
1931 case 0: /* FATAL LOG */
1932 pr_crit("%s", pbuf);
1933 break;
1934 case 1:
1935 pr_err("%s", pbuf);
1936 break;
1937 case 2:
1938 pr_warn("%s", pbuf);
1939 break;
1940 default:
1941 pr_info("%s", pbuf);
1942 break;
1943 }
1944 }
1945
1946 va_end(ap);
1947 }
1948
1949 void
1950 ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
1951 {
1952 int i;
1953 struct qla_hw_data *ha = vha->hw;
1954 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1955 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
1956 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
1957 uint16_t __iomem *mbx_reg;
1958
1959 if ((level & ql2xextended_error_logging) == level) {
1960
1961 if (IS_QLA82XX(ha))
1962 mbx_reg = &reg82->mailbox_in[0];
1963 else if (IS_FWI2_CAPABLE(ha))
1964 mbx_reg = &reg24->mailbox0;
1965 else
1966 mbx_reg = MAILBOX_REG(ha, reg, 0);
1967
1968 ql_dbg(level, vha, id, "Mailbox registers:\n");
1969 for (i = 0; i < 6; i++)
1970 ql_dbg(level, vha, id,
1971 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
1972 }
1973 }
1974
1975
1976 void
1977 ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
1978 uint8_t *b, uint32_t size)
1979 {
1980 uint32_t cnt;
1981 uint8_t c;
1982 if ((level & ql2xextended_error_logging) == level) {
1983
1984 ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
1985 "9 Ah Bh Ch Dh Eh Fh\n");
1986 ql_dbg(level, vha, id, "----------------------------------"
1987 "----------------------------\n");
1988
1989 ql_dbg(level, vha, id, "");
1990 for (cnt = 0; cnt < size;) {
1991 c = *b++;
1992 printk("%02x", (uint32_t) c);
1993 cnt++;
1994 if (!(cnt % 16))
1995 printk("\n");
1996 else
1997 printk(" ");
1998 }
1999 if (cnt % 16)
2000 ql_dbg(level, vha, id, "\n");
2001 }
2002 }
Linux kernel - Deliverables
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