2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 #include <linux/delay.h>
12 qla2xxx_prep_dump(scsi_qla_host_t
*ha
, struct qla2xxx_fw_dump
*fw_dump
)
14 fw_dump
->fw_major_version
= htonl(ha
->fw_major_version
);
15 fw_dump
->fw_minor_version
= htonl(ha
->fw_minor_version
);
16 fw_dump
->fw_subminor_version
= htonl(ha
->fw_subminor_version
);
17 fw_dump
->fw_attributes
= htonl(ha
->fw_attributes
);
19 fw_dump
->vendor
= htonl(ha
->pdev
->vendor
);
20 fw_dump
->device
= htonl(ha
->pdev
->device
);
21 fw_dump
->subsystem_vendor
= htonl(ha
->pdev
->subsystem_vendor
);
22 fw_dump
->subsystem_device
= htonl(ha
->pdev
->subsystem_device
);
26 qla2xxx_copy_queues(scsi_qla_host_t
*ha
, void *ptr
)
29 memcpy(ptr
, ha
->request_ring
, ha
->request_q_length
*
33 ptr
+= ha
->request_q_length
* sizeof(request_t
);
34 memcpy(ptr
, ha
->response_ring
, ha
->response_q_length
*
37 return ptr
+ (ha
->response_q_length
* sizeof(response_t
));
41 qla24xx_dump_ram(scsi_qla_host_t
*ha
, uint32_t addr
, uint32_t *ram
,
42 uint32_t ram_dwords
, void **nxt
)
45 uint32_t cnt
, stat
, timer
, dwords
, idx
;
47 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
48 dma_addr_t dump_dma
= ha
->gid_list_dma
;
49 uint32_t *dump
= (uint32_t *)ha
->gid_list
;
54 WRT_REG_WORD(®
->mailbox0
, MBC_DUMP_RISC_RAM_EXTENDED
);
55 clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
);
57 dwords
= GID_LIST_SIZE
/ 4;
58 for (cnt
= 0; cnt
< ram_dwords
&& rval
== QLA_SUCCESS
;
59 cnt
+= dwords
, addr
+= dwords
) {
60 if (cnt
+ dwords
> ram_dwords
)
61 dwords
= ram_dwords
- cnt
;
63 WRT_REG_WORD(®
->mailbox1
, LSW(addr
));
64 WRT_REG_WORD(®
->mailbox8
, MSW(addr
));
66 WRT_REG_WORD(®
->mailbox2
, MSW(dump_dma
));
67 WRT_REG_WORD(®
->mailbox3
, LSW(dump_dma
));
68 WRT_REG_WORD(®
->mailbox6
, MSW(MSD(dump_dma
)));
69 WRT_REG_WORD(®
->mailbox7
, LSW(MSD(dump_dma
)));
71 WRT_REG_WORD(®
->mailbox4
, MSW(dwords
));
72 WRT_REG_WORD(®
->mailbox5
, LSW(dwords
));
73 WRT_REG_DWORD(®
->hccr
, HCCRX_SET_HOST_INT
);
75 for (timer
= 6000000; timer
; timer
--) {
76 /* Check for pending interrupts. */
77 stat
= RD_REG_DWORD(®
->host_status
);
78 if (stat
& HSRX_RISC_INT
) {
81 if (stat
== 0x1 || stat
== 0x2 ||
82 stat
== 0x10 || stat
== 0x11) {
83 set_bit(MBX_INTERRUPT
,
86 mb0
= RD_REG_WORD(®
->mailbox0
);
88 WRT_REG_DWORD(®
->hccr
,
90 RD_REG_DWORD(®
->hccr
);
94 /* Clear this intr; it wasn't a mailbox intr */
95 WRT_REG_DWORD(®
->hccr
, HCCRX_CLR_RISC_INT
);
96 RD_REG_DWORD(®
->hccr
);
101 if (test_and_clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
)) {
102 rval
= mb0
& MBS_MASK
;
103 for (idx
= 0; idx
< dwords
; idx
++)
104 ram
[cnt
+ idx
] = swab32(dump
[idx
]);
106 rval
= QLA_FUNCTION_FAILED
;
110 *nxt
= rval
== QLA_SUCCESS
? &ram
[cnt
]: NULL
;
115 qla24xx_dump_memory(scsi_qla_host_t
*ha
, uint32_t *code_ram
,
116 uint32_t cram_size
, void **nxt
)
121 rval
= qla24xx_dump_ram(ha
, 0x20000, code_ram
, cram_size
/ 4, nxt
);
122 if (rval
!= QLA_SUCCESS
)
125 /* External Memory. */
126 return qla24xx_dump_ram(ha
, 0x100000, *nxt
,
127 ha
->fw_memory_size
- 0x100000 + 1, nxt
);
131 qla24xx_read_window(struct device_reg_24xx __iomem
*reg
, uint32_t iobase
,
132 uint32_t count
, uint32_t *buf
)
134 uint32_t __iomem
*dmp_reg
;
136 WRT_REG_DWORD(®
->iobase_addr
, iobase
);
137 dmp_reg
= ®
->iobase_window
;
139 *buf
++ = htonl(RD_REG_DWORD(dmp_reg
++));
145 qla24xx_pause_risc(struct device_reg_24xx __iomem
*reg
)
147 int rval
= QLA_SUCCESS
;
150 if (RD_REG_DWORD(®
->hccr
) & HCCRX_RISC_PAUSE
)
153 WRT_REG_DWORD(®
->hccr
, HCCRX_SET_RISC_PAUSE
);
154 for (cnt
= 30000; (RD_REG_DWORD(®
->hccr
) & HCCRX_RISC_PAUSE
) == 0 &&
155 rval
== QLA_SUCCESS
; cnt
--) {
159 rval
= QLA_FUNCTION_TIMEOUT
;
166 qla24xx_soft_reset(scsi_qla_host_t
*ha
)
168 int rval
= QLA_SUCCESS
;
171 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
174 WRT_REG_DWORD(®
->ctrl_status
, CSRX_DMA_SHUTDOWN
|MWB_4096_BYTES
);
175 for (cnt
= 0; cnt
< 30000; cnt
++) {
176 if ((RD_REG_DWORD(®
->ctrl_status
) & CSRX_DMA_ACTIVE
) == 0)
182 WRT_REG_DWORD(®
->ctrl_status
,
183 CSRX_ISP_SOFT_RESET
|CSRX_DMA_SHUTDOWN
|MWB_4096_BYTES
);
184 pci_read_config_word(ha
->pdev
, PCI_COMMAND
, &wd
);
187 /* Wait for firmware to complete NVRAM accesses. */
188 mb0
= (uint32_t) RD_REG_WORD(®
->mailbox0
);
189 for (cnt
= 10000 ; cnt
&& mb0
; cnt
--) {
191 mb0
= (uint32_t) RD_REG_WORD(®
->mailbox0
);
195 /* Wait for soft-reset to complete. */
196 for (cnt
= 0; cnt
< 30000; cnt
++) {
197 if ((RD_REG_DWORD(®
->ctrl_status
) &
198 CSRX_ISP_SOFT_RESET
) == 0)
203 WRT_REG_DWORD(®
->hccr
, HCCRX_CLR_RISC_RESET
);
204 RD_REG_DWORD(®
->hccr
); /* PCI Posting. */
206 for (cnt
= 30000; RD_REG_WORD(®
->mailbox0
) != 0 &&
207 rval
== QLA_SUCCESS
; cnt
--) {
211 rval
= QLA_FUNCTION_TIMEOUT
;
218 qla2xxx_dump_ram(scsi_qla_host_t
*ha
, uint32_t addr
, uint16_t *ram
,
219 uint32_t ram_words
, void **nxt
)
222 uint32_t cnt
, stat
, timer
, words
, idx
;
224 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
225 dma_addr_t dump_dma
= ha
->gid_list_dma
;
226 uint16_t *dump
= (uint16_t *)ha
->gid_list
;
231 WRT_MAILBOX_REG(ha
, reg
, 0, MBC_DUMP_RISC_RAM_EXTENDED
);
232 clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
);
234 words
= GID_LIST_SIZE
/ 2;
235 for (cnt
= 0; cnt
< ram_words
&& rval
== QLA_SUCCESS
;
236 cnt
+= words
, addr
+= words
) {
237 if (cnt
+ words
> ram_words
)
238 words
= ram_words
- cnt
;
240 WRT_MAILBOX_REG(ha
, reg
, 1, LSW(addr
));
241 WRT_MAILBOX_REG(ha
, reg
, 8, MSW(addr
));
243 WRT_MAILBOX_REG(ha
, reg
, 2, MSW(dump_dma
));
244 WRT_MAILBOX_REG(ha
, reg
, 3, LSW(dump_dma
));
245 WRT_MAILBOX_REG(ha
, reg
, 6, MSW(MSD(dump_dma
)));
246 WRT_MAILBOX_REG(ha
, reg
, 7, LSW(MSD(dump_dma
)));
248 WRT_MAILBOX_REG(ha
, reg
, 4, words
);
249 WRT_REG_WORD(®
->hccr
, HCCR_SET_HOST_INT
);
251 for (timer
= 6000000; timer
; timer
--) {
252 /* Check for pending interrupts. */
253 stat
= RD_REG_DWORD(®
->u
.isp2300
.host_status
);
254 if (stat
& HSR_RISC_INT
) {
257 if (stat
== 0x1 || stat
== 0x2) {
258 set_bit(MBX_INTERRUPT
,
261 mb0
= RD_MAILBOX_REG(ha
, reg
, 0);
263 /* Release mailbox registers. */
264 WRT_REG_WORD(®
->semaphore
, 0);
265 WRT_REG_WORD(®
->hccr
,
267 RD_REG_WORD(®
->hccr
);
269 } else if (stat
== 0x10 || stat
== 0x11) {
270 set_bit(MBX_INTERRUPT
,
273 mb0
= RD_MAILBOX_REG(ha
, reg
, 0);
275 WRT_REG_WORD(®
->hccr
,
277 RD_REG_WORD(®
->hccr
);
281 /* clear this intr; it wasn't a mailbox intr */
282 WRT_REG_WORD(®
->hccr
, HCCR_CLR_RISC_INT
);
283 RD_REG_WORD(®
->hccr
);
288 if (test_and_clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
)) {
289 rval
= mb0
& MBS_MASK
;
290 for (idx
= 0; idx
< words
; idx
++)
291 ram
[cnt
+ idx
] = swab16(dump
[idx
]);
293 rval
= QLA_FUNCTION_FAILED
;
297 *nxt
= rval
== QLA_SUCCESS
? &ram
[cnt
]: NULL
;
302 qla2xxx_read_window(struct device_reg_2xxx __iomem
*reg
, uint32_t count
,
305 uint16_t __iomem
*dmp_reg
= ®
->u
.isp2300
.fb_cmd
;
308 *buf
++ = htons(RD_REG_WORD(dmp_reg
++));
312 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
314 * @hardware_locked: Called with the hardware_lock
317 qla2300_fw_dump(scsi_qla_host_t
*ha
, int hardware_locked
)
322 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
323 uint16_t __iomem
*dmp_reg
;
325 struct qla2300_fw_dump
*fw
;
330 if (!hardware_locked
)
331 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
334 qla_printk(KERN_WARNING
, ha
,
335 "No buffer available for dump!!!\n");
336 goto qla2300_fw_dump_failed
;
340 qla_printk(KERN_WARNING
, ha
,
341 "Firmware has been previously dumped (%p) -- ignoring "
342 "request...\n", ha
->fw_dump
);
343 goto qla2300_fw_dump_failed
;
345 fw
= &ha
->fw_dump
->isp
.isp23
;
346 qla2xxx_prep_dump(ha
, ha
->fw_dump
);
349 fw
->hccr
= htons(RD_REG_WORD(®
->hccr
));
352 WRT_REG_WORD(®
->hccr
, HCCR_PAUSE_RISC
);
353 if (IS_QLA2300(ha
)) {
355 (RD_REG_WORD(®
->hccr
) & HCCR_RISC_PAUSE
) == 0 &&
356 rval
== QLA_SUCCESS
; cnt
--) {
360 rval
= QLA_FUNCTION_TIMEOUT
;
363 RD_REG_WORD(®
->hccr
); /* PCI Posting. */
367 if (rval
== QLA_SUCCESS
) {
368 dmp_reg
= ®
->flash_address
;
369 for (cnt
= 0; cnt
< sizeof(fw
->pbiu_reg
) / 2; cnt
++)
370 fw
->pbiu_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
372 dmp_reg
= ®
->u
.isp2300
.req_q_in
;
373 for (cnt
= 0; cnt
< sizeof(fw
->risc_host_reg
) / 2; cnt
++)
374 fw
->risc_host_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
376 dmp_reg
= ®
->u
.isp2300
.mailbox0
;
377 for (cnt
= 0; cnt
< sizeof(fw
->mailbox_reg
) / 2; cnt
++)
378 fw
->mailbox_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
380 WRT_REG_WORD(®
->ctrl_status
, 0x40);
381 qla2xxx_read_window(reg
, 32, fw
->resp_dma_reg
);
383 WRT_REG_WORD(®
->ctrl_status
, 0x50);
384 qla2xxx_read_window(reg
, 48, fw
->dma_reg
);
386 WRT_REG_WORD(®
->ctrl_status
, 0x00);
387 dmp_reg
= ®
->risc_hw
;
388 for (cnt
= 0; cnt
< sizeof(fw
->risc_hdw_reg
) / 2; cnt
++)
389 fw
->risc_hdw_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
391 WRT_REG_WORD(®
->pcr
, 0x2000);
392 qla2xxx_read_window(reg
, 16, fw
->risc_gp0_reg
);
394 WRT_REG_WORD(®
->pcr
, 0x2200);
395 qla2xxx_read_window(reg
, 16, fw
->risc_gp1_reg
);
397 WRT_REG_WORD(®
->pcr
, 0x2400);
398 qla2xxx_read_window(reg
, 16, fw
->risc_gp2_reg
);
400 WRT_REG_WORD(®
->pcr
, 0x2600);
401 qla2xxx_read_window(reg
, 16, fw
->risc_gp3_reg
);
403 WRT_REG_WORD(®
->pcr
, 0x2800);
404 qla2xxx_read_window(reg
, 16, fw
->risc_gp4_reg
);
406 WRT_REG_WORD(®
->pcr
, 0x2A00);
407 qla2xxx_read_window(reg
, 16, fw
->risc_gp5_reg
);
409 WRT_REG_WORD(®
->pcr
, 0x2C00);
410 qla2xxx_read_window(reg
, 16, fw
->risc_gp6_reg
);
412 WRT_REG_WORD(®
->pcr
, 0x2E00);
413 qla2xxx_read_window(reg
, 16, fw
->risc_gp7_reg
);
415 WRT_REG_WORD(®
->ctrl_status
, 0x10);
416 qla2xxx_read_window(reg
, 64, fw
->frame_buf_hdw_reg
);
418 WRT_REG_WORD(®
->ctrl_status
, 0x20);
419 qla2xxx_read_window(reg
, 64, fw
->fpm_b0_reg
);
421 WRT_REG_WORD(®
->ctrl_status
, 0x30);
422 qla2xxx_read_window(reg
, 64, fw
->fpm_b1_reg
);
425 WRT_REG_WORD(®
->ctrl_status
, CSR_ISP_SOFT_RESET
);
426 for (cnt
= 0; cnt
< 30000; cnt
++) {
427 if ((RD_REG_WORD(®
->ctrl_status
) &
428 CSR_ISP_SOFT_RESET
) == 0)
435 if (!IS_QLA2300(ha
)) {
436 for (cnt
= 30000; RD_MAILBOX_REG(ha
, reg
, 0) != 0 &&
437 rval
== QLA_SUCCESS
; cnt
--) {
441 rval
= QLA_FUNCTION_TIMEOUT
;
446 if (rval
== QLA_SUCCESS
)
447 rval
= qla2xxx_dump_ram(ha
, 0x800, fw
->risc_ram
,
448 sizeof(fw
->risc_ram
) / 2, &nxt
);
450 /* Get stack SRAM. */
451 if (rval
== QLA_SUCCESS
)
452 rval
= qla2xxx_dump_ram(ha
, 0x10000, fw
->stack_ram
,
453 sizeof(fw
->stack_ram
) / 2, &nxt
);
456 if (rval
== QLA_SUCCESS
)
457 rval
= qla2xxx_dump_ram(ha
, 0x11000, fw
->data_ram
,
458 ha
->fw_memory_size
- 0x11000 + 1, &nxt
);
460 if (rval
== QLA_SUCCESS
)
461 qla2xxx_copy_queues(ha
, nxt
);
463 if (rval
!= QLA_SUCCESS
) {
464 qla_printk(KERN_WARNING
, ha
,
465 "Failed to dump firmware (%x)!!!\n", rval
);
469 qla_printk(KERN_INFO
, ha
,
470 "Firmware dump saved to temp buffer (%ld/%p).\n",
471 ha
->host_no
, ha
->fw_dump
);
475 qla2300_fw_dump_failed
:
476 if (!hardware_locked
)
477 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
481 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
483 * @hardware_locked: Called with the hardware_lock
486 qla2100_fw_dump(scsi_qla_host_t
*ha
, int hardware_locked
)
490 uint16_t risc_address
;
492 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
493 uint16_t __iomem
*dmp_reg
;
495 struct qla2100_fw_dump
*fw
;
501 if (!hardware_locked
)
502 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
505 qla_printk(KERN_WARNING
, ha
,
506 "No buffer available for dump!!!\n");
507 goto qla2100_fw_dump_failed
;
511 qla_printk(KERN_WARNING
, ha
,
512 "Firmware has been previously dumped (%p) -- ignoring "
513 "request...\n", ha
->fw_dump
);
514 goto qla2100_fw_dump_failed
;
516 fw
= &ha
->fw_dump
->isp
.isp21
;
517 qla2xxx_prep_dump(ha
, ha
->fw_dump
);
520 fw
->hccr
= htons(RD_REG_WORD(®
->hccr
));
523 WRT_REG_WORD(®
->hccr
, HCCR_PAUSE_RISC
);
524 for (cnt
= 30000; (RD_REG_WORD(®
->hccr
) & HCCR_RISC_PAUSE
) == 0 &&
525 rval
== QLA_SUCCESS
; cnt
--) {
529 rval
= QLA_FUNCTION_TIMEOUT
;
531 if (rval
== QLA_SUCCESS
) {
532 dmp_reg
= ®
->flash_address
;
533 for (cnt
= 0; cnt
< sizeof(fw
->pbiu_reg
) / 2; cnt
++)
534 fw
->pbiu_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
536 dmp_reg
= ®
->u
.isp2100
.mailbox0
;
537 for (cnt
= 0; cnt
< ha
->mbx_count
; cnt
++) {
539 dmp_reg
= ®
->u_end
.isp2200
.mailbox8
;
541 fw
->mailbox_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
544 dmp_reg
= ®
->u
.isp2100
.unused_2
[0];
545 for (cnt
= 0; cnt
< sizeof(fw
->dma_reg
) / 2; cnt
++)
546 fw
->dma_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
548 WRT_REG_WORD(®
->ctrl_status
, 0x00);
549 dmp_reg
= ®
->risc_hw
;
550 for (cnt
= 0; cnt
< sizeof(fw
->risc_hdw_reg
) / 2; cnt
++)
551 fw
->risc_hdw_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
553 WRT_REG_WORD(®
->pcr
, 0x2000);
554 qla2xxx_read_window(reg
, 16, fw
->risc_gp0_reg
);
556 WRT_REG_WORD(®
->pcr
, 0x2100);
557 qla2xxx_read_window(reg
, 16, fw
->risc_gp1_reg
);
559 WRT_REG_WORD(®
->pcr
, 0x2200);
560 qla2xxx_read_window(reg
, 16, fw
->risc_gp2_reg
);
562 WRT_REG_WORD(®
->pcr
, 0x2300);
563 qla2xxx_read_window(reg
, 16, fw
->risc_gp3_reg
);
565 WRT_REG_WORD(®
->pcr
, 0x2400);
566 qla2xxx_read_window(reg
, 16, fw
->risc_gp4_reg
);
568 WRT_REG_WORD(®
->pcr
, 0x2500);
569 qla2xxx_read_window(reg
, 16, fw
->risc_gp5_reg
);
571 WRT_REG_WORD(®
->pcr
, 0x2600);
572 qla2xxx_read_window(reg
, 16, fw
->risc_gp6_reg
);
574 WRT_REG_WORD(®
->pcr
, 0x2700);
575 qla2xxx_read_window(reg
, 16, fw
->risc_gp7_reg
);
577 WRT_REG_WORD(®
->ctrl_status
, 0x10);
578 qla2xxx_read_window(reg
, 16, fw
->frame_buf_hdw_reg
);
580 WRT_REG_WORD(®
->ctrl_status
, 0x20);
581 qla2xxx_read_window(reg
, 64, fw
->fpm_b0_reg
);
583 WRT_REG_WORD(®
->ctrl_status
, 0x30);
584 qla2xxx_read_window(reg
, 64, fw
->fpm_b1_reg
);
587 WRT_REG_WORD(®
->ctrl_status
, CSR_ISP_SOFT_RESET
);
590 for (cnt
= 30000; RD_MAILBOX_REG(ha
, reg
, 0) != 0 &&
591 rval
== QLA_SUCCESS
; cnt
--) {
595 rval
= QLA_FUNCTION_TIMEOUT
;
599 if (rval
== QLA_SUCCESS
&& (IS_QLA2200(ha
) || (IS_QLA2100(ha
) &&
600 (RD_REG_WORD(®
->mctr
) & (BIT_1
| BIT_0
)) != 0))) {
602 WRT_REG_WORD(®
->hccr
, HCCR_PAUSE_RISC
);
604 (RD_REG_WORD(®
->hccr
) & HCCR_RISC_PAUSE
) == 0 &&
605 rval
== QLA_SUCCESS
; cnt
--) {
609 rval
= QLA_FUNCTION_TIMEOUT
;
611 if (rval
== QLA_SUCCESS
) {
612 /* Set memory configuration and timing. */
614 WRT_REG_WORD(®
->mctr
, 0xf1);
616 WRT_REG_WORD(®
->mctr
, 0xf2);
617 RD_REG_WORD(®
->mctr
); /* PCI Posting. */
620 WRT_REG_WORD(®
->hccr
, HCCR_RELEASE_RISC
);
624 if (rval
== QLA_SUCCESS
) {
626 risc_address
= 0x1000;
627 WRT_MAILBOX_REG(ha
, reg
, 0, MBC_READ_RAM_WORD
);
628 clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
);
630 for (cnt
= 0; cnt
< sizeof(fw
->risc_ram
) / 2 && rval
== QLA_SUCCESS
;
631 cnt
++, risc_address
++) {
632 WRT_MAILBOX_REG(ha
, reg
, 1, risc_address
);
633 WRT_REG_WORD(®
->hccr
, HCCR_SET_HOST_INT
);
635 for (timer
= 6000000; timer
!= 0; timer
--) {
636 /* Check for pending interrupts. */
637 if (RD_REG_WORD(®
->istatus
) & ISR_RISC_INT
) {
638 if (RD_REG_WORD(®
->semaphore
) & BIT_0
) {
639 set_bit(MBX_INTERRUPT
,
642 mb0
= RD_MAILBOX_REG(ha
, reg
, 0);
643 mb2
= RD_MAILBOX_REG(ha
, reg
, 2);
645 WRT_REG_WORD(®
->semaphore
, 0);
646 WRT_REG_WORD(®
->hccr
,
648 RD_REG_WORD(®
->hccr
);
651 WRT_REG_WORD(®
->hccr
, HCCR_CLR_RISC_INT
);
652 RD_REG_WORD(®
->hccr
);
657 if (test_and_clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
)) {
658 rval
= mb0
& MBS_MASK
;
659 fw
->risc_ram
[cnt
] = htons(mb2
);
661 rval
= QLA_FUNCTION_FAILED
;
665 if (rval
== QLA_SUCCESS
)
666 qla2xxx_copy_queues(ha
, &fw
->risc_ram
[cnt
]);
668 if (rval
!= QLA_SUCCESS
) {
669 qla_printk(KERN_WARNING
, ha
,
670 "Failed to dump firmware (%x)!!!\n", rval
);
674 qla_printk(KERN_INFO
, ha
,
675 "Firmware dump saved to temp buffer (%ld/%p).\n",
676 ha
->host_no
, ha
->fw_dump
);
680 qla2100_fw_dump_failed
:
681 if (!hardware_locked
)
682 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
686 qla24xx_fw_dump(scsi_qla_host_t
*ha
, int hardware_locked
)
690 uint32_t risc_address
;
692 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
693 uint32_t __iomem
*dmp_reg
;
695 uint16_t __iomem
*mbx_reg
;
697 struct qla24xx_fw_dump
*fw
;
698 uint32_t ext_mem_cnt
;
701 risc_address
= ext_mem_cnt
= 0;
704 if (!hardware_locked
)
705 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
708 qla_printk(KERN_WARNING
, ha
,
709 "No buffer available for dump!!!\n");
710 goto qla24xx_fw_dump_failed
;
714 qla_printk(KERN_WARNING
, ha
,
715 "Firmware has been previously dumped (%p) -- ignoring "
716 "request...\n", ha
->fw_dump
);
717 goto qla24xx_fw_dump_failed
;
719 fw
= &ha
->fw_dump
->isp
.isp24
;
720 qla2xxx_prep_dump(ha
, ha
->fw_dump
);
722 fw
->host_status
= htonl(RD_REG_DWORD(®
->host_status
));
725 rval
= qla24xx_pause_risc(reg
);
726 if (rval
!= QLA_SUCCESS
)
727 goto qla24xx_fw_dump_failed_0
;
729 /* Host interface registers. */
730 dmp_reg
= ®
->flash_addr
;
731 for (cnt
= 0; cnt
< sizeof(fw
->host_reg
) / 4; cnt
++)
732 fw
->host_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
734 /* Disable interrupts. */
735 WRT_REG_DWORD(®
->ictrl
, 0);
736 RD_REG_DWORD(®
->ictrl
);
738 /* Shadow registers. */
739 WRT_REG_DWORD(®
->iobase_addr
, 0x0F70);
740 RD_REG_DWORD(®
->iobase_addr
);
741 WRT_REG_DWORD(®
->iobase_select
, 0xB0000000);
742 fw
->shadow_reg
[0] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
744 WRT_REG_DWORD(®
->iobase_select
, 0xB0100000);
745 fw
->shadow_reg
[1] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
747 WRT_REG_DWORD(®
->iobase_select
, 0xB0200000);
748 fw
->shadow_reg
[2] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
750 WRT_REG_DWORD(®
->iobase_select
, 0xB0300000);
751 fw
->shadow_reg
[3] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
753 WRT_REG_DWORD(®
->iobase_select
, 0xB0400000);
754 fw
->shadow_reg
[4] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
756 WRT_REG_DWORD(®
->iobase_select
, 0xB0500000);
757 fw
->shadow_reg
[5] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
759 WRT_REG_DWORD(®
->iobase_select
, 0xB0600000);
760 fw
->shadow_reg
[6] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
762 /* Mailbox registers. */
763 mbx_reg
= ®
->mailbox0
;
764 for (cnt
= 0; cnt
< sizeof(fw
->mailbox_reg
) / 2; cnt
++)
765 fw
->mailbox_reg
[cnt
] = htons(RD_REG_WORD(mbx_reg
++));
767 /* Transfer sequence registers. */
768 iter_reg
= fw
->xseq_gp_reg
;
769 iter_reg
= qla24xx_read_window(reg
, 0xBF00, 16, iter_reg
);
770 iter_reg
= qla24xx_read_window(reg
, 0xBF10, 16, iter_reg
);
771 iter_reg
= qla24xx_read_window(reg
, 0xBF20, 16, iter_reg
);
772 iter_reg
= qla24xx_read_window(reg
, 0xBF30, 16, iter_reg
);
773 iter_reg
= qla24xx_read_window(reg
, 0xBF40, 16, iter_reg
);
774 iter_reg
= qla24xx_read_window(reg
, 0xBF50, 16, iter_reg
);
775 iter_reg
= qla24xx_read_window(reg
, 0xBF60, 16, iter_reg
);
776 qla24xx_read_window(reg
, 0xBF70, 16, iter_reg
);
778 qla24xx_read_window(reg
, 0xBFE0, 16, fw
->xseq_0_reg
);
779 qla24xx_read_window(reg
, 0xBFF0, 16, fw
->xseq_1_reg
);
781 /* Receive sequence registers. */
782 iter_reg
= fw
->rseq_gp_reg
;
783 iter_reg
= qla24xx_read_window(reg
, 0xFF00, 16, iter_reg
);
784 iter_reg
= qla24xx_read_window(reg
, 0xFF10, 16, iter_reg
);
785 iter_reg
= qla24xx_read_window(reg
, 0xFF20, 16, iter_reg
);
786 iter_reg
= qla24xx_read_window(reg
, 0xFF30, 16, iter_reg
);
787 iter_reg
= qla24xx_read_window(reg
, 0xFF40, 16, iter_reg
);
788 iter_reg
= qla24xx_read_window(reg
, 0xFF50, 16, iter_reg
);
789 iter_reg
= qla24xx_read_window(reg
, 0xFF60, 16, iter_reg
);
790 qla24xx_read_window(reg
, 0xFF70, 16, iter_reg
);
792 qla24xx_read_window(reg
, 0xFFD0, 16, fw
->rseq_0_reg
);
793 qla24xx_read_window(reg
, 0xFFE0, 16, fw
->rseq_1_reg
);
794 qla24xx_read_window(reg
, 0xFFF0, 16, fw
->rseq_2_reg
);
796 /* Command DMA registers. */
797 qla24xx_read_window(reg
, 0x7100, 16, fw
->cmd_dma_reg
);
800 iter_reg
= fw
->req0_dma_reg
;
801 iter_reg
= qla24xx_read_window(reg
, 0x7200, 8, iter_reg
);
802 dmp_reg
= ®
->iobase_q
;
803 for (cnt
= 0; cnt
< 7; cnt
++)
804 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
806 iter_reg
= fw
->resp0_dma_reg
;
807 iter_reg
= qla24xx_read_window(reg
, 0x7300, 8, iter_reg
);
808 dmp_reg
= ®
->iobase_q
;
809 for (cnt
= 0; cnt
< 7; cnt
++)
810 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
812 iter_reg
= fw
->req1_dma_reg
;
813 iter_reg
= qla24xx_read_window(reg
, 0x7400, 8, iter_reg
);
814 dmp_reg
= ®
->iobase_q
;
815 for (cnt
= 0; cnt
< 7; cnt
++)
816 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
818 /* Transmit DMA registers. */
819 iter_reg
= fw
->xmt0_dma_reg
;
820 iter_reg
= qla24xx_read_window(reg
, 0x7600, 16, iter_reg
);
821 qla24xx_read_window(reg
, 0x7610, 16, iter_reg
);
823 iter_reg
= fw
->xmt1_dma_reg
;
824 iter_reg
= qla24xx_read_window(reg
, 0x7620, 16, iter_reg
);
825 qla24xx_read_window(reg
, 0x7630, 16, iter_reg
);
827 iter_reg
= fw
->xmt2_dma_reg
;
828 iter_reg
= qla24xx_read_window(reg
, 0x7640, 16, iter_reg
);
829 qla24xx_read_window(reg
, 0x7650, 16, iter_reg
);
831 iter_reg
= fw
->xmt3_dma_reg
;
832 iter_reg
= qla24xx_read_window(reg
, 0x7660, 16, iter_reg
);
833 qla24xx_read_window(reg
, 0x7670, 16, iter_reg
);
835 iter_reg
= fw
->xmt4_dma_reg
;
836 iter_reg
= qla24xx_read_window(reg
, 0x7680, 16, iter_reg
);
837 qla24xx_read_window(reg
, 0x7690, 16, iter_reg
);
839 qla24xx_read_window(reg
, 0x76A0, 16, fw
->xmt_data_dma_reg
);
841 /* Receive DMA registers. */
842 iter_reg
= fw
->rcvt0_data_dma_reg
;
843 iter_reg
= qla24xx_read_window(reg
, 0x7700, 16, iter_reg
);
844 qla24xx_read_window(reg
, 0x7710, 16, iter_reg
);
846 iter_reg
= fw
->rcvt1_data_dma_reg
;
847 iter_reg
= qla24xx_read_window(reg
, 0x7720, 16, iter_reg
);
848 qla24xx_read_window(reg
, 0x7730, 16, iter_reg
);
850 /* RISC registers. */
851 iter_reg
= fw
->risc_gp_reg
;
852 iter_reg
= qla24xx_read_window(reg
, 0x0F00, 16, iter_reg
);
853 iter_reg
= qla24xx_read_window(reg
, 0x0F10, 16, iter_reg
);
854 iter_reg
= qla24xx_read_window(reg
, 0x0F20, 16, iter_reg
);
855 iter_reg
= qla24xx_read_window(reg
, 0x0F30, 16, iter_reg
);
856 iter_reg
= qla24xx_read_window(reg
, 0x0F40, 16, iter_reg
);
857 iter_reg
= qla24xx_read_window(reg
, 0x0F50, 16, iter_reg
);
858 iter_reg
= qla24xx_read_window(reg
, 0x0F60, 16, iter_reg
);
859 qla24xx_read_window(reg
, 0x0F70, 16, iter_reg
);
861 /* Local memory controller registers. */
862 iter_reg
= fw
->lmc_reg
;
863 iter_reg
= qla24xx_read_window(reg
, 0x3000, 16, iter_reg
);
864 iter_reg
= qla24xx_read_window(reg
, 0x3010, 16, iter_reg
);
865 iter_reg
= qla24xx_read_window(reg
, 0x3020, 16, iter_reg
);
866 iter_reg
= qla24xx_read_window(reg
, 0x3030, 16, iter_reg
);
867 iter_reg
= qla24xx_read_window(reg
, 0x3040, 16, iter_reg
);
868 iter_reg
= qla24xx_read_window(reg
, 0x3050, 16, iter_reg
);
869 qla24xx_read_window(reg
, 0x3060, 16, iter_reg
);
871 /* Fibre Protocol Module registers. */
872 iter_reg
= fw
->fpm_hdw_reg
;
873 iter_reg
= qla24xx_read_window(reg
, 0x4000, 16, iter_reg
);
874 iter_reg
= qla24xx_read_window(reg
, 0x4010, 16, iter_reg
);
875 iter_reg
= qla24xx_read_window(reg
, 0x4020, 16, iter_reg
);
876 iter_reg
= qla24xx_read_window(reg
, 0x4030, 16, iter_reg
);
877 iter_reg
= qla24xx_read_window(reg
, 0x4040, 16, iter_reg
);
878 iter_reg
= qla24xx_read_window(reg
, 0x4050, 16, iter_reg
);
879 iter_reg
= qla24xx_read_window(reg
, 0x4060, 16, iter_reg
);
880 iter_reg
= qla24xx_read_window(reg
, 0x4070, 16, iter_reg
);
881 iter_reg
= qla24xx_read_window(reg
, 0x4080, 16, iter_reg
);
882 iter_reg
= qla24xx_read_window(reg
, 0x4090, 16, iter_reg
);
883 iter_reg
= qla24xx_read_window(reg
, 0x40A0, 16, iter_reg
);
884 qla24xx_read_window(reg
, 0x40B0, 16, iter_reg
);
886 /* Frame Buffer registers. */
887 iter_reg
= fw
->fb_hdw_reg
;
888 iter_reg
= qla24xx_read_window(reg
, 0x6000, 16, iter_reg
);
889 iter_reg
= qla24xx_read_window(reg
, 0x6010, 16, iter_reg
);
890 iter_reg
= qla24xx_read_window(reg
, 0x6020, 16, iter_reg
);
891 iter_reg
= qla24xx_read_window(reg
, 0x6030, 16, iter_reg
);
892 iter_reg
= qla24xx_read_window(reg
, 0x6040, 16, iter_reg
);
893 iter_reg
= qla24xx_read_window(reg
, 0x6100, 16, iter_reg
);
894 iter_reg
= qla24xx_read_window(reg
, 0x6130, 16, iter_reg
);
895 iter_reg
= qla24xx_read_window(reg
, 0x6150, 16, iter_reg
);
896 iter_reg
= qla24xx_read_window(reg
, 0x6170, 16, iter_reg
);
897 iter_reg
= qla24xx_read_window(reg
, 0x6190, 16, iter_reg
);
898 qla24xx_read_window(reg
, 0x61B0, 16, iter_reg
);
900 rval
= qla24xx_soft_reset(ha
);
901 if (rval
!= QLA_SUCCESS
)
902 goto qla24xx_fw_dump_failed_0
;
904 rval
= qla24xx_dump_memory(ha
, fw
->code_ram
, sizeof(fw
->code_ram
),
906 if (rval
!= QLA_SUCCESS
)
907 goto qla24xx_fw_dump_failed_0
;
909 nxt
= qla2xxx_copy_queues(ha
, nxt
);
911 memcpy(nxt
, ha
->eft
, ntohl(ha
->fw_dump
->eft_size
));
913 qla24xx_fw_dump_failed_0
:
914 if (rval
!= QLA_SUCCESS
) {
915 qla_printk(KERN_WARNING
, ha
,
916 "Failed to dump firmware (%x)!!!\n", rval
);
920 qla_printk(KERN_INFO
, ha
,
921 "Firmware dump saved to temp buffer (%ld/%p).\n",
922 ha
->host_no
, ha
->fw_dump
);
926 qla24xx_fw_dump_failed
:
927 if (!hardware_locked
)
928 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
932 qla25xx_fw_dump(scsi_qla_host_t
*ha
, int hardware_locked
)
936 uint32_t risc_address
;
938 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
939 uint32_t __iomem
*dmp_reg
;
941 uint16_t __iomem
*mbx_reg
;
943 struct qla25xx_fw_dump
*fw
;
944 uint32_t ext_mem_cnt
;
946 struct qla2xxx_fce_chain
*fcec
;
948 risc_address
= ext_mem_cnt
= 0;
951 if (!hardware_locked
)
952 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
955 qla_printk(KERN_WARNING
, ha
,
956 "No buffer available for dump!!!\n");
957 goto qla25xx_fw_dump_failed
;
961 qla_printk(KERN_WARNING
, ha
,
962 "Firmware has been previously dumped (%p) -- ignoring "
963 "request...\n", ha
->fw_dump
);
964 goto qla25xx_fw_dump_failed
;
966 fw
= &ha
->fw_dump
->isp
.isp25
;
967 qla2xxx_prep_dump(ha
, ha
->fw_dump
);
968 ha
->fw_dump
->version
= __constant_htonl(2);
970 fw
->host_status
= htonl(RD_REG_DWORD(®
->host_status
));
973 rval
= qla24xx_pause_risc(reg
);
974 if (rval
!= QLA_SUCCESS
)
975 goto qla25xx_fw_dump_failed_0
;
977 /* Host/Risc registers. */
978 iter_reg
= fw
->host_risc_reg
;
979 iter_reg
= qla24xx_read_window(reg
, 0x7000, 16, iter_reg
);
980 qla24xx_read_window(reg
, 0x7010, 16, iter_reg
);
982 /* PCIe registers. */
983 WRT_REG_DWORD(®
->iobase_addr
, 0x7C00);
984 RD_REG_DWORD(®
->iobase_addr
);
985 WRT_REG_DWORD(®
->iobase_window
, 0x01);
986 dmp_reg
= ®
->iobase_c4
;
987 fw
->pcie_regs
[0] = htonl(RD_REG_DWORD(dmp_reg
++));
988 fw
->pcie_regs
[1] = htonl(RD_REG_DWORD(dmp_reg
++));
989 fw
->pcie_regs
[2] = htonl(RD_REG_DWORD(dmp_reg
));
990 fw
->pcie_regs
[3] = htonl(RD_REG_DWORD(®
->iobase_window
));
991 WRT_REG_DWORD(®
->iobase_window
, 0x00);
992 RD_REG_DWORD(®
->iobase_window
);
994 /* Host interface registers. */
995 dmp_reg
= ®
->flash_addr
;
996 for (cnt
= 0; cnt
< sizeof(fw
->host_reg
) / 4; cnt
++)
997 fw
->host_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
999 /* Disable interrupts. */
1000 WRT_REG_DWORD(®
->ictrl
, 0);
1001 RD_REG_DWORD(®
->ictrl
);
1003 /* Shadow registers. */
1004 WRT_REG_DWORD(®
->iobase_addr
, 0x0F70);
1005 RD_REG_DWORD(®
->iobase_addr
);
1006 WRT_REG_DWORD(®
->iobase_select
, 0xB0000000);
1007 fw
->shadow_reg
[0] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1009 WRT_REG_DWORD(®
->iobase_select
, 0xB0100000);
1010 fw
->shadow_reg
[1] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1012 WRT_REG_DWORD(®
->iobase_select
, 0xB0200000);
1013 fw
->shadow_reg
[2] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1015 WRT_REG_DWORD(®
->iobase_select
, 0xB0300000);
1016 fw
->shadow_reg
[3] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1018 WRT_REG_DWORD(®
->iobase_select
, 0xB0400000);
1019 fw
->shadow_reg
[4] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1021 WRT_REG_DWORD(®
->iobase_select
, 0xB0500000);
1022 fw
->shadow_reg
[5] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1024 WRT_REG_DWORD(®
->iobase_select
, 0xB0600000);
1025 fw
->shadow_reg
[6] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1027 WRT_REG_DWORD(®
->iobase_select
, 0xB0700000);
1028 fw
->shadow_reg
[7] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1030 WRT_REG_DWORD(®
->iobase_select
, 0xB0800000);
1031 fw
->shadow_reg
[8] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1033 WRT_REG_DWORD(®
->iobase_select
, 0xB0900000);
1034 fw
->shadow_reg
[9] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1036 WRT_REG_DWORD(®
->iobase_select
, 0xB0A00000);
1037 fw
->shadow_reg
[10] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1039 /* RISC I/O register. */
1040 WRT_REG_DWORD(®
->iobase_addr
, 0x0010);
1041 fw
->risc_io_reg
= htonl(RD_REG_DWORD(®
->iobase_window
));
1043 /* Mailbox registers. */
1044 mbx_reg
= ®
->mailbox0
;
1045 for (cnt
= 0; cnt
< sizeof(fw
->mailbox_reg
) / 2; cnt
++)
1046 fw
->mailbox_reg
[cnt
] = htons(RD_REG_WORD(mbx_reg
++));
1048 /* Transfer sequence registers. */
1049 iter_reg
= fw
->xseq_gp_reg
;
1050 iter_reg
= qla24xx_read_window(reg
, 0xBF00, 16, iter_reg
);
1051 iter_reg
= qla24xx_read_window(reg
, 0xBF10, 16, iter_reg
);
1052 iter_reg
= qla24xx_read_window(reg
, 0xBF20, 16, iter_reg
);
1053 iter_reg
= qla24xx_read_window(reg
, 0xBF30, 16, iter_reg
);
1054 iter_reg
= qla24xx_read_window(reg
, 0xBF40, 16, iter_reg
);
1055 iter_reg
= qla24xx_read_window(reg
, 0xBF50, 16, iter_reg
);
1056 iter_reg
= qla24xx_read_window(reg
, 0xBF60, 16, iter_reg
);
1057 qla24xx_read_window(reg
, 0xBF70, 16, iter_reg
);
1059 iter_reg
= fw
->xseq_0_reg
;
1060 iter_reg
= qla24xx_read_window(reg
, 0xBFC0, 16, iter_reg
);
1061 iter_reg
= qla24xx_read_window(reg
, 0xBFD0, 16, iter_reg
);
1062 qla24xx_read_window(reg
, 0xBFE0, 16, iter_reg
);
1064 qla24xx_read_window(reg
, 0xBFF0, 16, fw
->xseq_1_reg
);
1066 /* Receive sequence registers. */
1067 iter_reg
= fw
->rseq_gp_reg
;
1068 iter_reg
= qla24xx_read_window(reg
, 0xFF00, 16, iter_reg
);
1069 iter_reg
= qla24xx_read_window(reg
, 0xFF10, 16, iter_reg
);
1070 iter_reg
= qla24xx_read_window(reg
, 0xFF20, 16, iter_reg
);
1071 iter_reg
= qla24xx_read_window(reg
, 0xFF30, 16, iter_reg
);
1072 iter_reg
= qla24xx_read_window(reg
, 0xFF40, 16, iter_reg
);
1073 iter_reg
= qla24xx_read_window(reg
, 0xFF50, 16, iter_reg
);
1074 iter_reg
= qla24xx_read_window(reg
, 0xFF60, 16, iter_reg
);
1075 qla24xx_read_window(reg
, 0xFF70, 16, iter_reg
);
1077 iter_reg
= fw
->rseq_0_reg
;
1078 iter_reg
= qla24xx_read_window(reg
, 0xFFC0, 16, iter_reg
);
1079 qla24xx_read_window(reg
, 0xFFD0, 16, iter_reg
);
1081 qla24xx_read_window(reg
, 0xFFE0, 16, fw
->rseq_1_reg
);
1082 qla24xx_read_window(reg
, 0xFFF0, 16, fw
->rseq_2_reg
);
1084 /* Auxiliary sequence registers. */
1085 iter_reg
= fw
->aseq_gp_reg
;
1086 iter_reg
= qla24xx_read_window(reg
, 0xB000, 16, iter_reg
);
1087 iter_reg
= qla24xx_read_window(reg
, 0xB010, 16, iter_reg
);
1088 iter_reg
= qla24xx_read_window(reg
, 0xB020, 16, iter_reg
);
1089 iter_reg
= qla24xx_read_window(reg
, 0xB030, 16, iter_reg
);
1090 iter_reg
= qla24xx_read_window(reg
, 0xB040, 16, iter_reg
);
1091 iter_reg
= qla24xx_read_window(reg
, 0xB050, 16, iter_reg
);
1092 iter_reg
= qla24xx_read_window(reg
, 0xB060, 16, iter_reg
);
1093 qla24xx_read_window(reg
, 0xB070, 16, iter_reg
);
1095 iter_reg
= fw
->aseq_0_reg
;
1096 iter_reg
= qla24xx_read_window(reg
, 0xB0C0, 16, iter_reg
);
1097 qla24xx_read_window(reg
, 0xB0D0, 16, iter_reg
);
1099 qla24xx_read_window(reg
, 0xB0E0, 16, fw
->aseq_1_reg
);
1100 qla24xx_read_window(reg
, 0xB0F0, 16, fw
->aseq_2_reg
);
1102 /* Command DMA registers. */
1103 qla24xx_read_window(reg
, 0x7100, 16, fw
->cmd_dma_reg
);
1106 iter_reg
= fw
->req0_dma_reg
;
1107 iter_reg
= qla24xx_read_window(reg
, 0x7200, 8, iter_reg
);
1108 dmp_reg
= ®
->iobase_q
;
1109 for (cnt
= 0; cnt
< 7; cnt
++)
1110 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1112 iter_reg
= fw
->resp0_dma_reg
;
1113 iter_reg
= qla24xx_read_window(reg
, 0x7300, 8, iter_reg
);
1114 dmp_reg
= ®
->iobase_q
;
1115 for (cnt
= 0; cnt
< 7; cnt
++)
1116 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1118 iter_reg
= fw
->req1_dma_reg
;
1119 iter_reg
= qla24xx_read_window(reg
, 0x7400, 8, iter_reg
);
1120 dmp_reg
= ®
->iobase_q
;
1121 for (cnt
= 0; cnt
< 7; cnt
++)
1122 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1124 /* Transmit DMA registers. */
1125 iter_reg
= fw
->xmt0_dma_reg
;
1126 iter_reg
= qla24xx_read_window(reg
, 0x7600, 16, iter_reg
);
1127 qla24xx_read_window(reg
, 0x7610, 16, iter_reg
);
1129 iter_reg
= fw
->xmt1_dma_reg
;
1130 iter_reg
= qla24xx_read_window(reg
, 0x7620, 16, iter_reg
);
1131 qla24xx_read_window(reg
, 0x7630, 16, iter_reg
);
1133 iter_reg
= fw
->xmt2_dma_reg
;
1134 iter_reg
= qla24xx_read_window(reg
, 0x7640, 16, iter_reg
);
1135 qla24xx_read_window(reg
, 0x7650, 16, iter_reg
);
1137 iter_reg
= fw
->xmt3_dma_reg
;
1138 iter_reg
= qla24xx_read_window(reg
, 0x7660, 16, iter_reg
);
1139 qla24xx_read_window(reg
, 0x7670, 16, iter_reg
);
1141 iter_reg
= fw
->xmt4_dma_reg
;
1142 iter_reg
= qla24xx_read_window(reg
, 0x7680, 16, iter_reg
);
1143 qla24xx_read_window(reg
, 0x7690, 16, iter_reg
);
1145 qla24xx_read_window(reg
, 0x76A0, 16, fw
->xmt_data_dma_reg
);
1147 /* Receive DMA registers. */
1148 iter_reg
= fw
->rcvt0_data_dma_reg
;
1149 iter_reg
= qla24xx_read_window(reg
, 0x7700, 16, iter_reg
);
1150 qla24xx_read_window(reg
, 0x7710, 16, iter_reg
);
1152 iter_reg
= fw
->rcvt1_data_dma_reg
;
1153 iter_reg
= qla24xx_read_window(reg
, 0x7720, 16, iter_reg
);
1154 qla24xx_read_window(reg
, 0x7730, 16, iter_reg
);
1156 /* RISC registers. */
1157 iter_reg
= fw
->risc_gp_reg
;
1158 iter_reg
= qla24xx_read_window(reg
, 0x0F00, 16, iter_reg
);
1159 iter_reg
= qla24xx_read_window(reg
, 0x0F10, 16, iter_reg
);
1160 iter_reg
= qla24xx_read_window(reg
, 0x0F20, 16, iter_reg
);
1161 iter_reg
= qla24xx_read_window(reg
, 0x0F30, 16, iter_reg
);
1162 iter_reg
= qla24xx_read_window(reg
, 0x0F40, 16, iter_reg
);
1163 iter_reg
= qla24xx_read_window(reg
, 0x0F50, 16, iter_reg
);
1164 iter_reg
= qla24xx_read_window(reg
, 0x0F60, 16, iter_reg
);
1165 qla24xx_read_window(reg
, 0x0F70, 16, iter_reg
);
1167 /* Local memory controller registers. */
1168 iter_reg
= fw
->lmc_reg
;
1169 iter_reg
= qla24xx_read_window(reg
, 0x3000, 16, iter_reg
);
1170 iter_reg
= qla24xx_read_window(reg
, 0x3010, 16, iter_reg
);
1171 iter_reg
= qla24xx_read_window(reg
, 0x3020, 16, iter_reg
);
1172 iter_reg
= qla24xx_read_window(reg
, 0x3030, 16, iter_reg
);
1173 iter_reg
= qla24xx_read_window(reg
, 0x3040, 16, iter_reg
);
1174 iter_reg
= qla24xx_read_window(reg
, 0x3050, 16, iter_reg
);
1175 iter_reg
= qla24xx_read_window(reg
, 0x3060, 16, iter_reg
);
1176 qla24xx_read_window(reg
, 0x3070, 16, iter_reg
);
1178 /* Fibre Protocol Module registers. */
1179 iter_reg
= fw
->fpm_hdw_reg
;
1180 iter_reg
= qla24xx_read_window(reg
, 0x4000, 16, iter_reg
);
1181 iter_reg
= qla24xx_read_window(reg
, 0x4010, 16, iter_reg
);
1182 iter_reg
= qla24xx_read_window(reg
, 0x4020, 16, iter_reg
);
1183 iter_reg
= qla24xx_read_window(reg
, 0x4030, 16, iter_reg
);
1184 iter_reg
= qla24xx_read_window(reg
, 0x4040, 16, iter_reg
);
1185 iter_reg
= qla24xx_read_window(reg
, 0x4050, 16, iter_reg
);
1186 iter_reg
= qla24xx_read_window(reg
, 0x4060, 16, iter_reg
);
1187 iter_reg
= qla24xx_read_window(reg
, 0x4070, 16, iter_reg
);
1188 iter_reg
= qla24xx_read_window(reg
, 0x4080, 16, iter_reg
);
1189 iter_reg
= qla24xx_read_window(reg
, 0x4090, 16, iter_reg
);
1190 iter_reg
= qla24xx_read_window(reg
, 0x40A0, 16, iter_reg
);
1191 qla24xx_read_window(reg
, 0x40B0, 16, iter_reg
);
1193 /* Frame Buffer registers. */
1194 iter_reg
= fw
->fb_hdw_reg
;
1195 iter_reg
= qla24xx_read_window(reg
, 0x6000, 16, iter_reg
);
1196 iter_reg
= qla24xx_read_window(reg
, 0x6010, 16, iter_reg
);
1197 iter_reg
= qla24xx_read_window(reg
, 0x6020, 16, iter_reg
);
1198 iter_reg
= qla24xx_read_window(reg
, 0x6030, 16, iter_reg
);
1199 iter_reg
= qla24xx_read_window(reg
, 0x6040, 16, iter_reg
);
1200 iter_reg
= qla24xx_read_window(reg
, 0x6100, 16, iter_reg
);
1201 iter_reg
= qla24xx_read_window(reg
, 0x6130, 16, iter_reg
);
1202 iter_reg
= qla24xx_read_window(reg
, 0x6150, 16, iter_reg
);
1203 iter_reg
= qla24xx_read_window(reg
, 0x6170, 16, iter_reg
);
1204 iter_reg
= qla24xx_read_window(reg
, 0x6190, 16, iter_reg
);
1205 iter_reg
= qla24xx_read_window(reg
, 0x61B0, 16, iter_reg
);
1206 qla24xx_read_window(reg
, 0x6F00, 16, iter_reg
);
1208 rval
= qla24xx_soft_reset(ha
);
1209 if (rval
!= QLA_SUCCESS
)
1210 goto qla25xx_fw_dump_failed_0
;
1212 rval
= qla24xx_dump_memory(ha
, fw
->code_ram
, sizeof(fw
->code_ram
),
1214 if (rval
!= QLA_SUCCESS
)
1215 goto qla25xx_fw_dump_failed_0
;
1217 /* Fibre Channel Trace Buffer. */
1218 nxt
= qla2xxx_copy_queues(ha
, nxt
);
1220 memcpy(nxt
, ha
->eft
, ntohl(ha
->fw_dump
->eft_size
));
1222 /* Fibre Channel Event Buffer. */
1224 goto qla25xx_fw_dump_failed_0
;
1226 ha
->fw_dump
->version
|= __constant_htonl(DUMP_CHAIN_VARIANT
);
1228 fcec
= nxt
+ ntohl(ha
->fw_dump
->eft_size
);
1229 fcec
->type
= __constant_htonl(DUMP_CHAIN_FCE
| DUMP_CHAIN_LAST
);
1230 fcec
->chain_size
= htonl(sizeof(struct qla2xxx_fce_chain
) +
1231 fce_calc_size(ha
->fce_bufs
));
1232 fcec
->size
= htonl(fce_calc_size(ha
->fce_bufs
));
1233 fcec
->addr_l
= htonl(LSD(ha
->fce_dma
));
1234 fcec
->addr_h
= htonl(MSD(ha
->fce_dma
));
1236 iter_reg
= fcec
->eregs
;
1237 for (cnt
= 0; cnt
< 8; cnt
++)
1238 *iter_reg
++ = htonl(ha
->fce_mb
[cnt
]);
1240 memcpy(iter_reg
, ha
->fce
, ntohl(fcec
->size
));
1242 qla25xx_fw_dump_failed_0
:
1243 if (rval
!= QLA_SUCCESS
) {
1244 qla_printk(KERN_WARNING
, ha
,
1245 "Failed to dump firmware (%x)!!!\n", rval
);
1249 qla_printk(KERN_INFO
, ha
,
1250 "Firmware dump saved to temp buffer (%ld/%p).\n",
1251 ha
->host_no
, ha
->fw_dump
);
1255 qla25xx_fw_dump_failed
:
1256 if (!hardware_locked
)
1257 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1260 /****************************************************************************/
1261 /* Driver Debug Functions. */
1262 /****************************************************************************/
1265 qla2x00_dump_regs(scsi_qla_host_t
*ha
)
1268 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1269 struct device_reg_24xx __iomem
*reg24
= &ha
->iobase
->isp24
;
1270 uint16_t __iomem
*mbx_reg
;
1272 mbx_reg
= IS_FWI2_CAPABLE(ha
) ? ®24
->mailbox0
:
1273 MAILBOX_REG(ha
, reg
, 0);
1275 printk("Mailbox registers:\n");
1276 for (i
= 0; i
< 6; i
++)
1277 printk("scsi(%ld): mbox %d 0x%04x \n", ha
->host_no
, i
,
1278 RD_REG_WORD(mbx_reg
++));
1283 qla2x00_dump_buffer(uint8_t * b
, uint32_t size
)
1288 printk(" 0 1 2 3 4 5 6 7 8 9 "
1289 "Ah Bh Ch Dh Eh Fh\n");
1290 printk("----------------------------------------"
1291 "----------------------\n");
1293 for (cnt
= 0; cnt
< size
;) {
1295 printk("%02x",(uint32_t) c
);