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Merge commit '63cc8c75156462d4b42cbdd76c293b7eee7ddbfe':
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_dbg.c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/delay.h>
10
11 static inline void
12 qla2xxx_prep_dump(scsi_qla_host_t *ha, struct qla2xxx_fw_dump *fw_dump)
13 {
14 fw_dump->fw_major_version = htonl(ha->fw_major_version);
15 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
16 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
17 fw_dump->fw_attributes = htonl(ha->fw_attributes);
18
19 fw_dump->vendor = htonl(ha->pdev->vendor);
20 fw_dump->device = htonl(ha->pdev->device);
21 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
22 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
23 }
24
25 static inline void *
26 qla2xxx_copy_queues(scsi_qla_host_t *ha, void *ptr)
27 {
28 /* Request queue. */
29 memcpy(ptr, ha->request_ring, ha->request_q_length *
30 sizeof(request_t));
31
32 /* Response queue. */
33 ptr += ha->request_q_length * sizeof(request_t);
34 memcpy(ptr, ha->response_ring, ha->response_q_length *
35 sizeof(response_t));
36
37 return ptr + (ha->response_q_length * sizeof(response_t));
38 }
39
40 static int
41 qla24xx_dump_ram(scsi_qla_host_t *ha, uint32_t addr, uint32_t *ram,
42 uint32_t ram_dwords, void **nxt)
43 {
44 int rval;
45 uint32_t cnt, stat, timer, dwords, idx;
46 uint16_t mb0;
47 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
48 dma_addr_t dump_dma = ha->gid_list_dma;
49 uint32_t *dump = (uint32_t *)ha->gid_list;
50
51 rval = QLA_SUCCESS;
52 mb0 = 0;
53
54 WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
55 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
56
57 dwords = GID_LIST_SIZE / 4;
58 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
59 cnt += dwords, addr += dwords) {
60 if (cnt + dwords > ram_dwords)
61 dwords = ram_dwords - cnt;
62
63 WRT_REG_WORD(&reg->mailbox1, LSW(addr));
64 WRT_REG_WORD(&reg->mailbox8, MSW(addr));
65
66 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
67 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
68 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
69 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
70
71 WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
72 WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
73 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
74
75 for (timer = 6000000; timer; timer--) {
76 /* Check for pending interrupts. */
77 stat = RD_REG_DWORD(&reg->host_status);
78 if (stat & HSRX_RISC_INT) {
79 stat &= 0xff;
80
81 if (stat == 0x1 || stat == 0x2 ||
82 stat == 0x10 || stat == 0x11) {
83 set_bit(MBX_INTERRUPT,
84 &ha->mbx_cmd_flags);
85
86 mb0 = RD_REG_WORD(&reg->mailbox0);
87
88 WRT_REG_DWORD(&reg->hccr,
89 HCCRX_CLR_RISC_INT);
90 RD_REG_DWORD(&reg->hccr);
91 break;
92 }
93
94 /* Clear this intr; it wasn't a mailbox intr */
95 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
96 RD_REG_DWORD(&reg->hccr);
97 }
98 udelay(5);
99 }
100
101 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
102 rval = mb0 & MBS_MASK;
103 for (idx = 0; idx < dwords; idx++)
104 ram[cnt + idx] = swab32(dump[idx]);
105 } else {
106 rval = QLA_FUNCTION_FAILED;
107 }
108 }
109
110 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
111 return rval;
112 }
113
114 static int
115 qla24xx_dump_memory(scsi_qla_host_t *ha, uint32_t *code_ram,
116 uint32_t cram_size, void **nxt)
117 {
118 int rval;
119
120 /* Code RAM. */
121 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
122 if (rval != QLA_SUCCESS)
123 return rval;
124
125 /* External Memory. */
126 return qla24xx_dump_ram(ha, 0x100000, *nxt,
127 ha->fw_memory_size - 0x100000 + 1, nxt);
128 }
129
130 static uint32_t *
131 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
132 uint32_t count, uint32_t *buf)
133 {
134 uint32_t __iomem *dmp_reg;
135
136 WRT_REG_DWORD(&reg->iobase_addr, iobase);
137 dmp_reg = &reg->iobase_window;
138 while (count--)
139 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
140
141 return buf;
142 }
143
144 static inline int
145 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
146 {
147 int rval = QLA_SUCCESS;
148 uint32_t cnt;
149
150 if (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE)
151 return rval;
152
153 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
154 for (cnt = 30000; (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0 &&
155 rval == QLA_SUCCESS; cnt--) {
156 if (cnt)
157 udelay(100);
158 else
159 rval = QLA_FUNCTION_TIMEOUT;
160 }
161
162 return rval;
163 }
164
165 static int
166 qla24xx_soft_reset(scsi_qla_host_t *ha)
167 {
168 int rval = QLA_SUCCESS;
169 uint32_t cnt;
170 uint16_t mb0, wd;
171 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
172
173 /* Reset RISC. */
174 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
175 for (cnt = 0; cnt < 30000; cnt++) {
176 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
177 break;
178
179 udelay(10);
180 }
181
182 WRT_REG_DWORD(&reg->ctrl_status,
183 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
184 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
185
186 udelay(100);
187 /* Wait for firmware to complete NVRAM accesses. */
188 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
189 for (cnt = 10000 ; cnt && mb0; cnt--) {
190 udelay(5);
191 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
192 barrier();
193 }
194
195 /* Wait for soft-reset to complete. */
196 for (cnt = 0; cnt < 30000; cnt++) {
197 if ((RD_REG_DWORD(&reg->ctrl_status) &
198 CSRX_ISP_SOFT_RESET) == 0)
199 break;
200
201 udelay(10);
202 }
203 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
204 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
205
206 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
207 rval == QLA_SUCCESS; cnt--) {
208 if (cnt)
209 udelay(100);
210 else
211 rval = QLA_FUNCTION_TIMEOUT;
212 }
213
214 return rval;
215 }
216
217 static int
218 qla2xxx_dump_ram(scsi_qla_host_t *ha, uint32_t addr, uint16_t *ram,
219 uint32_t ram_words, void **nxt)
220 {
221 int rval;
222 uint32_t cnt, stat, timer, words, idx;
223 uint16_t mb0;
224 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
225 dma_addr_t dump_dma = ha->gid_list_dma;
226 uint16_t *dump = (uint16_t *)ha->gid_list;
227
228 rval = QLA_SUCCESS;
229 mb0 = 0;
230
231 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
232 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
233
234 words = GID_LIST_SIZE / 2;
235 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
236 cnt += words, addr += words) {
237 if (cnt + words > ram_words)
238 words = ram_words - cnt;
239
240 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
241 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
242
243 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
244 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
245 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
246 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
247
248 WRT_MAILBOX_REG(ha, reg, 4, words);
249 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
250
251 for (timer = 6000000; timer; timer--) {
252 /* Check for pending interrupts. */
253 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
254 if (stat & HSR_RISC_INT) {
255 stat &= 0xff;
256
257 if (stat == 0x1 || stat == 0x2) {
258 set_bit(MBX_INTERRUPT,
259 &ha->mbx_cmd_flags);
260
261 mb0 = RD_MAILBOX_REG(ha, reg, 0);
262
263 /* Release mailbox registers. */
264 WRT_REG_WORD(&reg->semaphore, 0);
265 WRT_REG_WORD(&reg->hccr,
266 HCCR_CLR_RISC_INT);
267 RD_REG_WORD(&reg->hccr);
268 break;
269 } else if (stat == 0x10 || stat == 0x11) {
270 set_bit(MBX_INTERRUPT,
271 &ha->mbx_cmd_flags);
272
273 mb0 = RD_MAILBOX_REG(ha, reg, 0);
274
275 WRT_REG_WORD(&reg->hccr,
276 HCCR_CLR_RISC_INT);
277 RD_REG_WORD(&reg->hccr);
278 break;
279 }
280
281 /* clear this intr; it wasn't a mailbox intr */
282 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
283 RD_REG_WORD(&reg->hccr);
284 }
285 udelay(5);
286 }
287
288 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
289 rval = mb0 & MBS_MASK;
290 for (idx = 0; idx < words; idx++)
291 ram[cnt + idx] = swab16(dump[idx]);
292 } else {
293 rval = QLA_FUNCTION_FAILED;
294 }
295 }
296
297 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
298 return rval;
299 }
300
301 static inline void
302 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
303 uint16_t *buf)
304 {
305 uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
306
307 while (count--)
308 *buf++ = htons(RD_REG_WORD(dmp_reg++));
309 }
310
311 /**
312 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
313 * @ha: HA context
314 * @hardware_locked: Called with the hardware_lock
315 */
316 void
317 qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
318 {
319 int rval;
320 uint32_t cnt;
321
322 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
323 uint16_t __iomem *dmp_reg;
324 unsigned long flags;
325 struct qla2300_fw_dump *fw;
326 void *nxt;
327
328 flags = 0;
329
330 if (!hardware_locked)
331 spin_lock_irqsave(&ha->hardware_lock, flags);
332
333 if (!ha->fw_dump) {
334 qla_printk(KERN_WARNING, ha,
335 "No buffer available for dump!!!\n");
336 goto qla2300_fw_dump_failed;
337 }
338
339 if (ha->fw_dumped) {
340 qla_printk(KERN_WARNING, ha,
341 "Firmware has been previously dumped (%p) -- ignoring "
342 "request...\n", ha->fw_dump);
343 goto qla2300_fw_dump_failed;
344 }
345 fw = &ha->fw_dump->isp.isp23;
346 qla2xxx_prep_dump(ha, ha->fw_dump);
347
348 rval = QLA_SUCCESS;
349 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
350
351 /* Pause RISC. */
352 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
353 if (IS_QLA2300(ha)) {
354 for (cnt = 30000;
355 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
356 rval == QLA_SUCCESS; cnt--) {
357 if (cnt)
358 udelay(100);
359 else
360 rval = QLA_FUNCTION_TIMEOUT;
361 }
362 } else {
363 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
364 udelay(10);
365 }
366
367 if (rval == QLA_SUCCESS) {
368 dmp_reg = &reg->flash_address;
369 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
370 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
371
372 dmp_reg = &reg->u.isp2300.req_q_in;
373 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
374 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
375
376 dmp_reg = &reg->u.isp2300.mailbox0;
377 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
378 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
379
380 WRT_REG_WORD(&reg->ctrl_status, 0x40);
381 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
382
383 WRT_REG_WORD(&reg->ctrl_status, 0x50);
384 qla2xxx_read_window(reg, 48, fw->dma_reg);
385
386 WRT_REG_WORD(&reg->ctrl_status, 0x00);
387 dmp_reg = &reg->risc_hw;
388 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
389 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
390
391 WRT_REG_WORD(&reg->pcr, 0x2000);
392 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
393
394 WRT_REG_WORD(&reg->pcr, 0x2200);
395 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
396
397 WRT_REG_WORD(&reg->pcr, 0x2400);
398 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
399
400 WRT_REG_WORD(&reg->pcr, 0x2600);
401 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
402
403 WRT_REG_WORD(&reg->pcr, 0x2800);
404 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
405
406 WRT_REG_WORD(&reg->pcr, 0x2A00);
407 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
408
409 WRT_REG_WORD(&reg->pcr, 0x2C00);
410 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
411
412 WRT_REG_WORD(&reg->pcr, 0x2E00);
413 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
414
415 WRT_REG_WORD(&reg->ctrl_status, 0x10);
416 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
417
418 WRT_REG_WORD(&reg->ctrl_status, 0x20);
419 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
420
421 WRT_REG_WORD(&reg->ctrl_status, 0x30);
422 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
423
424 /* Reset RISC. */
425 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
426 for (cnt = 0; cnt < 30000; cnt++) {
427 if ((RD_REG_WORD(&reg->ctrl_status) &
428 CSR_ISP_SOFT_RESET) == 0)
429 break;
430
431 udelay(10);
432 }
433 }
434
435 if (!IS_QLA2300(ha)) {
436 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
437 rval == QLA_SUCCESS; cnt--) {
438 if (cnt)
439 udelay(100);
440 else
441 rval = QLA_FUNCTION_TIMEOUT;
442 }
443 }
444
445 /* Get RISC SRAM. */
446 if (rval == QLA_SUCCESS)
447 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
448 sizeof(fw->risc_ram) / 2, &nxt);
449
450 /* Get stack SRAM. */
451 if (rval == QLA_SUCCESS)
452 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
453 sizeof(fw->stack_ram) / 2, &nxt);
454
455 /* Get data SRAM. */
456 if (rval == QLA_SUCCESS)
457 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
458 ha->fw_memory_size - 0x11000 + 1, &nxt);
459
460 if (rval == QLA_SUCCESS)
461 qla2xxx_copy_queues(ha, nxt);
462
463 if (rval != QLA_SUCCESS) {
464 qla_printk(KERN_WARNING, ha,
465 "Failed to dump firmware (%x)!!!\n", rval);
466 ha->fw_dumped = 0;
467
468 } else {
469 qla_printk(KERN_INFO, ha,
470 "Firmware dump saved to temp buffer (%ld/%p).\n",
471 ha->host_no, ha->fw_dump);
472 ha->fw_dumped = 1;
473 }
474
475 qla2300_fw_dump_failed:
476 if (!hardware_locked)
477 spin_unlock_irqrestore(&ha->hardware_lock, flags);
478 }
479
480 /**
481 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
482 * @ha: HA context
483 * @hardware_locked: Called with the hardware_lock
484 */
485 void
486 qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
487 {
488 int rval;
489 uint32_t cnt, timer;
490 uint16_t risc_address;
491 uint16_t mb0, mb2;
492 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
493 uint16_t __iomem *dmp_reg;
494 unsigned long flags;
495 struct qla2100_fw_dump *fw;
496
497 risc_address = 0;
498 mb0 = mb2 = 0;
499 flags = 0;
500
501 if (!hardware_locked)
502 spin_lock_irqsave(&ha->hardware_lock, flags);
503
504 if (!ha->fw_dump) {
505 qla_printk(KERN_WARNING, ha,
506 "No buffer available for dump!!!\n");
507 goto qla2100_fw_dump_failed;
508 }
509
510 if (ha->fw_dumped) {
511 qla_printk(KERN_WARNING, ha,
512 "Firmware has been previously dumped (%p) -- ignoring "
513 "request...\n", ha->fw_dump);
514 goto qla2100_fw_dump_failed;
515 }
516 fw = &ha->fw_dump->isp.isp21;
517 qla2xxx_prep_dump(ha, ha->fw_dump);
518
519 rval = QLA_SUCCESS;
520 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
521
522 /* Pause RISC. */
523 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
524 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
525 rval == QLA_SUCCESS; cnt--) {
526 if (cnt)
527 udelay(100);
528 else
529 rval = QLA_FUNCTION_TIMEOUT;
530 }
531 if (rval == QLA_SUCCESS) {
532 dmp_reg = &reg->flash_address;
533 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
534 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
535
536 dmp_reg = &reg->u.isp2100.mailbox0;
537 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
538 if (cnt == 8)
539 dmp_reg = &reg->u_end.isp2200.mailbox8;
540
541 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
542 }
543
544 dmp_reg = &reg->u.isp2100.unused_2[0];
545 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
546 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
547
548 WRT_REG_WORD(&reg->ctrl_status, 0x00);
549 dmp_reg = &reg->risc_hw;
550 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
551 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
552
553 WRT_REG_WORD(&reg->pcr, 0x2000);
554 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
555
556 WRT_REG_WORD(&reg->pcr, 0x2100);
557 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
558
559 WRT_REG_WORD(&reg->pcr, 0x2200);
560 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
561
562 WRT_REG_WORD(&reg->pcr, 0x2300);
563 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
564
565 WRT_REG_WORD(&reg->pcr, 0x2400);
566 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
567
568 WRT_REG_WORD(&reg->pcr, 0x2500);
569 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
570
571 WRT_REG_WORD(&reg->pcr, 0x2600);
572 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
573
574 WRT_REG_WORD(&reg->pcr, 0x2700);
575 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
576
577 WRT_REG_WORD(&reg->ctrl_status, 0x10);
578 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
579
580 WRT_REG_WORD(&reg->ctrl_status, 0x20);
581 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
582
583 WRT_REG_WORD(&reg->ctrl_status, 0x30);
584 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
585
586 /* Reset the ISP. */
587 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
588 }
589
590 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
591 rval == QLA_SUCCESS; cnt--) {
592 if (cnt)
593 udelay(100);
594 else
595 rval = QLA_FUNCTION_TIMEOUT;
596 }
597
598 /* Pause RISC. */
599 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
600 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
601
602 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
603 for (cnt = 30000;
604 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
605 rval == QLA_SUCCESS; cnt--) {
606 if (cnt)
607 udelay(100);
608 else
609 rval = QLA_FUNCTION_TIMEOUT;
610 }
611 if (rval == QLA_SUCCESS) {
612 /* Set memory configuration and timing. */
613 if (IS_QLA2100(ha))
614 WRT_REG_WORD(&reg->mctr, 0xf1);
615 else
616 WRT_REG_WORD(&reg->mctr, 0xf2);
617 RD_REG_WORD(&reg->mctr); /* PCI Posting. */
618
619 /* Release RISC. */
620 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
621 }
622 }
623
624 if (rval == QLA_SUCCESS) {
625 /* Get RISC SRAM. */
626 risc_address = 0x1000;
627 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
628 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
629 }
630 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
631 cnt++, risc_address++) {
632 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
633 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
634
635 for (timer = 6000000; timer != 0; timer--) {
636 /* Check for pending interrupts. */
637 if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
638 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
639 set_bit(MBX_INTERRUPT,
640 &ha->mbx_cmd_flags);
641
642 mb0 = RD_MAILBOX_REG(ha, reg, 0);
643 mb2 = RD_MAILBOX_REG(ha, reg, 2);
644
645 WRT_REG_WORD(&reg->semaphore, 0);
646 WRT_REG_WORD(&reg->hccr,
647 HCCR_CLR_RISC_INT);
648 RD_REG_WORD(&reg->hccr);
649 break;
650 }
651 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
652 RD_REG_WORD(&reg->hccr);
653 }
654 udelay(5);
655 }
656
657 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
658 rval = mb0 & MBS_MASK;
659 fw->risc_ram[cnt] = htons(mb2);
660 } else {
661 rval = QLA_FUNCTION_FAILED;
662 }
663 }
664
665 if (rval == QLA_SUCCESS)
666 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
667
668 if (rval != QLA_SUCCESS) {
669 qla_printk(KERN_WARNING, ha,
670 "Failed to dump firmware (%x)!!!\n", rval);
671 ha->fw_dumped = 0;
672
673 } else {
674 qla_printk(KERN_INFO, ha,
675 "Firmware dump saved to temp buffer (%ld/%p).\n",
676 ha->host_no, ha->fw_dump);
677 ha->fw_dumped = 1;
678 }
679
680 qla2100_fw_dump_failed:
681 if (!hardware_locked)
682 spin_unlock_irqrestore(&ha->hardware_lock, flags);
683 }
684
685 void
686 qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
687 {
688 int rval;
689 uint32_t cnt;
690 uint32_t risc_address;
691
692 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
693 uint32_t __iomem *dmp_reg;
694 uint32_t *iter_reg;
695 uint16_t __iomem *mbx_reg;
696 unsigned long flags;
697 struct qla24xx_fw_dump *fw;
698 uint32_t ext_mem_cnt;
699 void *nxt;
700
701 risc_address = ext_mem_cnt = 0;
702 flags = 0;
703
704 if (!hardware_locked)
705 spin_lock_irqsave(&ha->hardware_lock, flags);
706
707 if (!ha->fw_dump) {
708 qla_printk(KERN_WARNING, ha,
709 "No buffer available for dump!!!\n");
710 goto qla24xx_fw_dump_failed;
711 }
712
713 if (ha->fw_dumped) {
714 qla_printk(KERN_WARNING, ha,
715 "Firmware has been previously dumped (%p) -- ignoring "
716 "request...\n", ha->fw_dump);
717 goto qla24xx_fw_dump_failed;
718 }
719 fw = &ha->fw_dump->isp.isp24;
720 qla2xxx_prep_dump(ha, ha->fw_dump);
721
722 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
723
724 /* Pause RISC. */
725 rval = qla24xx_pause_risc(reg);
726 if (rval != QLA_SUCCESS)
727 goto qla24xx_fw_dump_failed_0;
728
729 /* Host interface registers. */
730 dmp_reg = &reg->flash_addr;
731 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
732 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
733
734 /* Disable interrupts. */
735 WRT_REG_DWORD(&reg->ictrl, 0);
736 RD_REG_DWORD(&reg->ictrl);
737
738 /* Shadow registers. */
739 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
740 RD_REG_DWORD(&reg->iobase_addr);
741 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
742 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
743
744 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
745 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
746
747 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
748 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
749
750 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
751 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
752
753 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
754 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
755
756 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
757 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
758
759 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
760 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
761
762 /* Mailbox registers. */
763 mbx_reg = &reg->mailbox0;
764 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
765 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
766
767 /* Transfer sequence registers. */
768 iter_reg = fw->xseq_gp_reg;
769 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
770 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
771 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
772 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
773 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
774 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
775 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
776 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
777
778 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
779 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
780
781 /* Receive sequence registers. */
782 iter_reg = fw->rseq_gp_reg;
783 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
784 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
785 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
786 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
787 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
788 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
789 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
790 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
791
792 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
793 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
794 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
795
796 /* Command DMA registers. */
797 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
798
799 /* Queues. */
800 iter_reg = fw->req0_dma_reg;
801 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
802 dmp_reg = &reg->iobase_q;
803 for (cnt = 0; cnt < 7; cnt++)
804 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
805
806 iter_reg = fw->resp0_dma_reg;
807 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
808 dmp_reg = &reg->iobase_q;
809 for (cnt = 0; cnt < 7; cnt++)
810 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
811
812 iter_reg = fw->req1_dma_reg;
813 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
814 dmp_reg = &reg->iobase_q;
815 for (cnt = 0; cnt < 7; cnt++)
816 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
817
818 /* Transmit DMA registers. */
819 iter_reg = fw->xmt0_dma_reg;
820 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
821 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
822
823 iter_reg = fw->xmt1_dma_reg;
824 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
825 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
826
827 iter_reg = fw->xmt2_dma_reg;
828 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
829 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
830
831 iter_reg = fw->xmt3_dma_reg;
832 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
833 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
834
835 iter_reg = fw->xmt4_dma_reg;
836 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
837 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
838
839 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
840
841 /* Receive DMA registers. */
842 iter_reg = fw->rcvt0_data_dma_reg;
843 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
844 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
845
846 iter_reg = fw->rcvt1_data_dma_reg;
847 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
848 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
849
850 /* RISC registers. */
851 iter_reg = fw->risc_gp_reg;
852 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
853 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
854 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
855 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
856 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
857 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
858 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
859 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
860
861 /* Local memory controller registers. */
862 iter_reg = fw->lmc_reg;
863 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
864 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
865 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
866 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
867 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
868 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
869 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
870
871 /* Fibre Protocol Module registers. */
872 iter_reg = fw->fpm_hdw_reg;
873 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
874 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
875 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
876 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
877 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
878 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
879 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
880 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
881 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
882 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
883 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
884 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
885
886 /* Frame Buffer registers. */
887 iter_reg = fw->fb_hdw_reg;
888 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
889 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
890 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
891 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
892 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
893 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
894 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
895 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
896 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
897 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
898 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
899
900 rval = qla24xx_soft_reset(ha);
901 if (rval != QLA_SUCCESS)
902 goto qla24xx_fw_dump_failed_0;
903
904 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
905 &nxt);
906 if (rval != QLA_SUCCESS)
907 goto qla24xx_fw_dump_failed_0;
908
909 nxt = qla2xxx_copy_queues(ha, nxt);
910 if (ha->eft)
911 memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size));
912
913 qla24xx_fw_dump_failed_0:
914 if (rval != QLA_SUCCESS) {
915 qla_printk(KERN_WARNING, ha,
916 "Failed to dump firmware (%x)!!!\n", rval);
917 ha->fw_dumped = 0;
918
919 } else {
920 qla_printk(KERN_INFO, ha,
921 "Firmware dump saved to temp buffer (%ld/%p).\n",
922 ha->host_no, ha->fw_dump);
923 ha->fw_dumped = 1;
924 }
925
926 qla24xx_fw_dump_failed:
927 if (!hardware_locked)
928 spin_unlock_irqrestore(&ha->hardware_lock, flags);
929 }
930
931 void
932 qla25xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
933 {
934 int rval;
935 uint32_t cnt;
936 uint32_t risc_address;
937
938 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
939 uint32_t __iomem *dmp_reg;
940 uint32_t *iter_reg;
941 uint16_t __iomem *mbx_reg;
942 unsigned long flags;
943 struct qla25xx_fw_dump *fw;
944 uint32_t ext_mem_cnt;
945 void *nxt;
946 struct qla2xxx_fce_chain *fcec;
947
948 risc_address = ext_mem_cnt = 0;
949 flags = 0;
950
951 if (!hardware_locked)
952 spin_lock_irqsave(&ha->hardware_lock, flags);
953
954 if (!ha->fw_dump) {
955 qla_printk(KERN_WARNING, ha,
956 "No buffer available for dump!!!\n");
957 goto qla25xx_fw_dump_failed;
958 }
959
960 if (ha->fw_dumped) {
961 qla_printk(KERN_WARNING, ha,
962 "Firmware has been previously dumped (%p) -- ignoring "
963 "request...\n", ha->fw_dump);
964 goto qla25xx_fw_dump_failed;
965 }
966 fw = &ha->fw_dump->isp.isp25;
967 qla2xxx_prep_dump(ha, ha->fw_dump);
968 ha->fw_dump->version = __constant_htonl(2);
969
970 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
971
972 /* Pause RISC. */
973 rval = qla24xx_pause_risc(reg);
974 if (rval != QLA_SUCCESS)
975 goto qla25xx_fw_dump_failed_0;
976
977 /* Host/Risc registers. */
978 iter_reg = fw->host_risc_reg;
979 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
980 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
981
982 /* PCIe registers. */
983 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
984 RD_REG_DWORD(&reg->iobase_addr);
985 WRT_REG_DWORD(&reg->iobase_window, 0x01);
986 dmp_reg = &reg->iobase_c4;
987 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
988 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
989 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
990 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
991 WRT_REG_DWORD(&reg->iobase_window, 0x00);
992 RD_REG_DWORD(&reg->iobase_window);
993
994 /* Host interface registers. */
995 dmp_reg = &reg->flash_addr;
996 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
997 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
998
999 /* Disable interrupts. */
1000 WRT_REG_DWORD(&reg->ictrl, 0);
1001 RD_REG_DWORD(&reg->ictrl);
1002
1003 /* Shadow registers. */
1004 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1005 RD_REG_DWORD(&reg->iobase_addr);
1006 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1007 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1008
1009 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1010 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1011
1012 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1013 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1014
1015 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1016 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1017
1018 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1019 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1020
1021 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1022 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1023
1024 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1025 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1026
1027 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1028 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1029
1030 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1031 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1032
1033 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1034 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1035
1036 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1037 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1038
1039 /* RISC I/O register. */
1040 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1041 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1042
1043 /* Mailbox registers. */
1044 mbx_reg = &reg->mailbox0;
1045 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1046 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1047
1048 /* Transfer sequence registers. */
1049 iter_reg = fw->xseq_gp_reg;
1050 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1051 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1052 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1053 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1054 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1055 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1056 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1057 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1058
1059 iter_reg = fw->xseq_0_reg;
1060 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1061 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1062 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1063
1064 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1065
1066 /* Receive sequence registers. */
1067 iter_reg = fw->rseq_gp_reg;
1068 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1069 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1070 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1071 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1072 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1073 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1074 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1075 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1076
1077 iter_reg = fw->rseq_0_reg;
1078 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1079 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1080
1081 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1082 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1083
1084 /* Auxiliary sequence registers. */
1085 iter_reg = fw->aseq_gp_reg;
1086 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1087 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1088 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1089 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1090 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1091 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1092 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1093 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1094
1095 iter_reg = fw->aseq_0_reg;
1096 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1097 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1098
1099 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1100 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1101
1102 /* Command DMA registers. */
1103 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1104
1105 /* Queues. */
1106 iter_reg = fw->req0_dma_reg;
1107 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1108 dmp_reg = &reg->iobase_q;
1109 for (cnt = 0; cnt < 7; cnt++)
1110 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1111
1112 iter_reg = fw->resp0_dma_reg;
1113 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1114 dmp_reg = &reg->iobase_q;
1115 for (cnt = 0; cnt < 7; cnt++)
1116 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1117
1118 iter_reg = fw->req1_dma_reg;
1119 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1120 dmp_reg = &reg->iobase_q;
1121 for (cnt = 0; cnt < 7; cnt++)
1122 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1123
1124 /* Transmit DMA registers. */
1125 iter_reg = fw->xmt0_dma_reg;
1126 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1127 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1128
1129 iter_reg = fw->xmt1_dma_reg;
1130 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1131 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1132
1133 iter_reg = fw->xmt2_dma_reg;
1134 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1135 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1136
1137 iter_reg = fw->xmt3_dma_reg;
1138 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1139 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1140
1141 iter_reg = fw->xmt4_dma_reg;
1142 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1143 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1144
1145 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1146
1147 /* Receive DMA registers. */
1148 iter_reg = fw->rcvt0_data_dma_reg;
1149 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1150 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1151
1152 iter_reg = fw->rcvt1_data_dma_reg;
1153 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1154 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1155
1156 /* RISC registers. */
1157 iter_reg = fw->risc_gp_reg;
1158 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1159 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1160 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1161 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1162 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1163 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1164 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1165 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1166
1167 /* Local memory controller registers. */
1168 iter_reg = fw->lmc_reg;
1169 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1170 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1171 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1172 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1173 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1174 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1175 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1176 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1177
1178 /* Fibre Protocol Module registers. */
1179 iter_reg = fw->fpm_hdw_reg;
1180 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1181 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1182 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1183 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1184 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1185 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1186 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1187 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1188 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1189 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1190 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1191 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1192
1193 /* Frame Buffer registers. */
1194 iter_reg = fw->fb_hdw_reg;
1195 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1196 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1197 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1198 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1199 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1200 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1201 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1202 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1203 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1204 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1205 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1206 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1207
1208 rval = qla24xx_soft_reset(ha);
1209 if (rval != QLA_SUCCESS)
1210 goto qla25xx_fw_dump_failed_0;
1211
1212 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1213 &nxt);
1214 if (rval != QLA_SUCCESS)
1215 goto qla25xx_fw_dump_failed_0;
1216
1217 /* Fibre Channel Trace Buffer. */
1218 nxt = qla2xxx_copy_queues(ha, nxt);
1219 if (ha->eft)
1220 memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size));
1221
1222 /* Fibre Channel Event Buffer. */
1223 if (!ha->fce)
1224 goto qla25xx_fw_dump_failed_0;
1225
1226 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1227
1228 fcec = nxt + ntohl(ha->fw_dump->eft_size);
1229 fcec->type = __constant_htonl(DUMP_CHAIN_FCE | DUMP_CHAIN_LAST);
1230 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
1231 fce_calc_size(ha->fce_bufs));
1232 fcec->size = htonl(fce_calc_size(ha->fce_bufs));
1233 fcec->addr_l = htonl(LSD(ha->fce_dma));
1234 fcec->addr_h = htonl(MSD(ha->fce_dma));
1235
1236 iter_reg = fcec->eregs;
1237 for (cnt = 0; cnt < 8; cnt++)
1238 *iter_reg++ = htonl(ha->fce_mb[cnt]);
1239
1240 memcpy(iter_reg, ha->fce, ntohl(fcec->size));
1241
1242 qla25xx_fw_dump_failed_0:
1243 if (rval != QLA_SUCCESS) {
1244 qla_printk(KERN_WARNING, ha,
1245 "Failed to dump firmware (%x)!!!\n", rval);
1246 ha->fw_dumped = 0;
1247
1248 } else {
1249 qla_printk(KERN_INFO, ha,
1250 "Firmware dump saved to temp buffer (%ld/%p).\n",
1251 ha->host_no, ha->fw_dump);
1252 ha->fw_dumped = 1;
1253 }
1254
1255 qla25xx_fw_dump_failed:
1256 if (!hardware_locked)
1257 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1258 }
1259
1260 /****************************************************************************/
1261 /* Driver Debug Functions. */
1262 /****************************************************************************/
1263
1264 void
1265 qla2x00_dump_regs(scsi_qla_host_t *ha)
1266 {
1267 int i;
1268 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1269 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
1270 uint16_t __iomem *mbx_reg;
1271
1272 mbx_reg = IS_FWI2_CAPABLE(ha) ? &reg24->mailbox0:
1273 MAILBOX_REG(ha, reg, 0);
1274
1275 printk("Mailbox registers:\n");
1276 for (i = 0; i < 6; i++)
1277 printk("scsi(%ld): mbox %d 0x%04x \n", ha->host_no, i,
1278 RD_REG_WORD(mbx_reg++));
1279 }
1280
1281
1282 void
1283 qla2x00_dump_buffer(uint8_t * b, uint32_t size)
1284 {
1285 uint32_t cnt;
1286 uint8_t c;
1287
1288 printk(" 0 1 2 3 4 5 6 7 8 9 "
1289 "Ah Bh Ch Dh Eh Fh\n");
1290 printk("----------------------------------------"
1291 "----------------------\n");
1292
1293 for (cnt = 0; cnt < size;) {
1294 c = *b++;
1295 printk("%02x",(uint32_t) c);
1296 cnt++;
1297 if (!(cnt % 16))
1298 printk("\n");
1299 else
1300 printk(" ");
1301 }
1302 if (cnt % 16)
1303 printk("\n");
1304 }
Linux kernel - Deliverables
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