projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge master.kernel.org:/pub/scm/linux/kernel/git/jejb/scsi-for-linus-2.6
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_dbg.c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/delay.h>
10
11 static int qla_uprintf(char **, char *, ...);
12
13 /**
14 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
15 * @ha: HA context
16 * @hardware_locked: Called with the hardware_lock
17 */
18 void
19 qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
20 {
21 int rval;
22 uint32_t cnt, timer;
23 uint32_t risc_address;
24 uint16_t mb0, mb2;
25
26 uint32_t stat;
27 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
28 uint16_t __iomem *dmp_reg;
29 unsigned long flags;
30 struct qla2300_fw_dump *fw;
31 uint32_t dump_size, data_ram_cnt;
32
33 risc_address = data_ram_cnt = 0;
34 mb0 = mb2 = 0;
35 flags = 0;
36
37 if (!hardware_locked)
38 spin_lock_irqsave(&ha->hardware_lock, flags);
39
40 if (ha->fw_dump != NULL) {
41 qla_printk(KERN_WARNING, ha,
42 "Firmware has been previously dumped (%p) -- ignoring "
43 "request...\n", ha->fw_dump);
44 goto qla2300_fw_dump_failed;
45 }
46
47 /* Allocate (large) dump buffer. */
48 dump_size = sizeof(struct qla2300_fw_dump);
49 dump_size += (ha->fw_memory_size - 0x11000) * sizeof(uint16_t);
50 ha->fw_dump_order = get_order(dump_size);
51 ha->fw_dump = (struct qla2300_fw_dump *) __get_free_pages(GFP_ATOMIC,
52 ha->fw_dump_order);
53 if (ha->fw_dump == NULL) {
54 qla_printk(KERN_WARNING, ha,
55 "Unable to allocated memory for firmware dump (%d/%d).\n",
56 ha->fw_dump_order, dump_size);
57 goto qla2300_fw_dump_failed;
58 }
59 fw = ha->fw_dump;
60
61 rval = QLA_SUCCESS;
62 fw->hccr = RD_REG_WORD(&reg->hccr);
63
64 /* Pause RISC. */
65 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
66 if (IS_QLA2300(ha)) {
67 for (cnt = 30000;
68 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
69 rval == QLA_SUCCESS; cnt--) {
70 if (cnt)
71 udelay(100);
72 else
73 rval = QLA_FUNCTION_TIMEOUT;
74 }
75 } else {
76 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
77 udelay(10);
78 }
79
80 if (rval == QLA_SUCCESS) {
81 dmp_reg = (uint16_t __iomem *)(reg + 0);
82 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
83 fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
84
85 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10);
86 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
87 fw->risc_host_reg[cnt] = RD_REG_WORD(dmp_reg++);
88
89 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x40);
90 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
91 fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++);
92
93 WRT_REG_WORD(&reg->ctrl_status, 0x40);
94 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
95 for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++)
96 fw->resp_dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
97
98 WRT_REG_WORD(&reg->ctrl_status, 0x50);
99 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
100 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
101 fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
102
103 WRT_REG_WORD(&reg->ctrl_status, 0x00);
104 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0);
105 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
106 fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
107
108 WRT_REG_WORD(&reg->pcr, 0x2000);
109 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
110 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
111 fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
112
113 WRT_REG_WORD(&reg->pcr, 0x2200);
114 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
115 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
116 fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
117
118 WRT_REG_WORD(&reg->pcr, 0x2400);
119 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
120 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
121 fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
122
123 WRT_REG_WORD(&reg->pcr, 0x2600);
124 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
125 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
126 fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
127
128 WRT_REG_WORD(&reg->pcr, 0x2800);
129 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
130 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
131 fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
132
133 WRT_REG_WORD(&reg->pcr, 0x2A00);
134 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
135 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
136 fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
137
138 WRT_REG_WORD(&reg->pcr, 0x2C00);
139 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
140 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
141 fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
142
143 WRT_REG_WORD(&reg->pcr, 0x2E00);
144 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
145 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
146 fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
147
148 WRT_REG_WORD(&reg->ctrl_status, 0x10);
149 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
150 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
151 fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
152
153 WRT_REG_WORD(&reg->ctrl_status, 0x20);
154 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
155 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
156 fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
157
158 WRT_REG_WORD(&reg->ctrl_status, 0x30);
159 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
160 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
161 fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
162
163 /* Reset RISC. */
164 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
165 for (cnt = 0; cnt < 30000; cnt++) {
166 if ((RD_REG_WORD(&reg->ctrl_status) &
167 CSR_ISP_SOFT_RESET) == 0)
168 break;
169
170 udelay(10);
171 }
172 }
173
174 if (!IS_QLA2300(ha)) {
175 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
176 rval == QLA_SUCCESS; cnt--) {
177 if (cnt)
178 udelay(100);
179 else
180 rval = QLA_FUNCTION_TIMEOUT;
181 }
182 }
183
184 if (rval == QLA_SUCCESS) {
185 /* Get RISC SRAM. */
186 risc_address = 0x800;
187 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
188 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
189 }
190 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
191 cnt++, risc_address++) {
192 WRT_MAILBOX_REG(ha, reg, 1, (uint16_t)risc_address);
193 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
194
195 for (timer = 6000000; timer; timer--) {
196 /* Check for pending interrupts. */
197 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
198 if (stat & HSR_RISC_INT) {
199 stat &= 0xff;
200
201 if (stat == 0x1 || stat == 0x2) {
202 set_bit(MBX_INTERRUPT,
203 &ha->mbx_cmd_flags);
204
205 mb0 = RD_MAILBOX_REG(ha, reg, 0);
206 mb2 = RD_MAILBOX_REG(ha, reg, 2);
207
208 /* Release mailbox registers. */
209 WRT_REG_WORD(&reg->semaphore, 0);
210 WRT_REG_WORD(&reg->hccr,
211 HCCR_CLR_RISC_INT);
212 RD_REG_WORD(&reg->hccr);
213 break;
214 } else if (stat == 0x10 || stat == 0x11) {
215 set_bit(MBX_INTERRUPT,
216 &ha->mbx_cmd_flags);
217
218 mb0 = RD_MAILBOX_REG(ha, reg, 0);
219 mb2 = RD_MAILBOX_REG(ha, reg, 2);
220
221 WRT_REG_WORD(&reg->hccr,
222 HCCR_CLR_RISC_INT);
223 RD_REG_WORD(&reg->hccr);
224 break;
225 }
226
227 /* clear this intr; it wasn't a mailbox intr */
228 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
229 RD_REG_WORD(&reg->hccr);
230 }
231 udelay(5);
232 }
233
234 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
235 rval = mb0 & MBS_MASK;
236 fw->risc_ram[cnt] = mb2;
237 } else {
238 rval = QLA_FUNCTION_FAILED;
239 }
240 }
241
242 if (rval == QLA_SUCCESS) {
243 /* Get stack SRAM. */
244 risc_address = 0x10000;
245 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED);
246 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
247 }
248 for (cnt = 0; cnt < sizeof(fw->stack_ram) / 2 && rval == QLA_SUCCESS;
249 cnt++, risc_address++) {
250 WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address));
251 WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address));
252 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
253
254 for (timer = 6000000; timer; timer--) {
255 /* Check for pending interrupts. */
256 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
257 if (stat & HSR_RISC_INT) {
258 stat &= 0xff;
259
260 if (stat == 0x1 || stat == 0x2) {
261 set_bit(MBX_INTERRUPT,
262 &ha->mbx_cmd_flags);
263
264 mb0 = RD_MAILBOX_REG(ha, reg, 0);
265 mb2 = RD_MAILBOX_REG(ha, reg, 2);
266
267 /* Release mailbox registers. */
268 WRT_REG_WORD(&reg->semaphore, 0);
269 WRT_REG_WORD(&reg->hccr,
270 HCCR_CLR_RISC_INT);
271 RD_REG_WORD(&reg->hccr);
272 break;
273 } else if (stat == 0x10 || stat == 0x11) {
274 set_bit(MBX_INTERRUPT,
275 &ha->mbx_cmd_flags);
276
277 mb0 = RD_MAILBOX_REG(ha, reg, 0);
278 mb2 = RD_MAILBOX_REG(ha, reg, 2);
279
280 WRT_REG_WORD(&reg->hccr,
281 HCCR_CLR_RISC_INT);
282 RD_REG_WORD(&reg->hccr);
283 break;
284 }
285
286 /* clear this intr; it wasn't a mailbox intr */
287 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
288 RD_REG_WORD(&reg->hccr);
289 }
290 udelay(5);
291 }
292
293 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
294 rval = mb0 & MBS_MASK;
295 fw->stack_ram[cnt] = mb2;
296 } else {
297 rval = QLA_FUNCTION_FAILED;
298 }
299 }
300
301 if (rval == QLA_SUCCESS) {
302 /* Get data SRAM. */
303 risc_address = 0x11000;
304 data_ram_cnt = ha->fw_memory_size - risc_address + 1;
305 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED);
306 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
307 }
308 for (cnt = 0; cnt < data_ram_cnt && rval == QLA_SUCCESS;
309 cnt++, risc_address++) {
310 WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address));
311 WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address));
312 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
313
314 for (timer = 6000000; timer; timer--) {
315 /* Check for pending interrupts. */
316 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
317 if (stat & HSR_RISC_INT) {
318 stat &= 0xff;
319
320 if (stat == 0x1 || stat == 0x2) {
321 set_bit(MBX_INTERRUPT,
322 &ha->mbx_cmd_flags);
323
324 mb0 = RD_MAILBOX_REG(ha, reg, 0);
325 mb2 = RD_MAILBOX_REG(ha, reg, 2);
326
327 /* Release mailbox registers. */
328 WRT_REG_WORD(&reg->semaphore, 0);
329 WRT_REG_WORD(&reg->hccr,
330 HCCR_CLR_RISC_INT);
331 RD_REG_WORD(&reg->hccr);
332 break;
333 } else if (stat == 0x10 || stat == 0x11) {
334 set_bit(MBX_INTERRUPT,
335 &ha->mbx_cmd_flags);
336
337 mb0 = RD_MAILBOX_REG(ha, reg, 0);
338 mb2 = RD_MAILBOX_REG(ha, reg, 2);
339
340 WRT_REG_WORD(&reg->hccr,
341 HCCR_CLR_RISC_INT);
342 RD_REG_WORD(&reg->hccr);
343 break;
344 }
345
346 /* clear this intr; it wasn't a mailbox intr */
347 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
348 RD_REG_WORD(&reg->hccr);
349 }
350 udelay(5);
351 }
352
353 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
354 rval = mb0 & MBS_MASK;
355 fw->data_ram[cnt] = mb2;
356 } else {
357 rval = QLA_FUNCTION_FAILED;
358 }
359 }
360
361
362 if (rval != QLA_SUCCESS) {
363 qla_printk(KERN_WARNING, ha,
364 "Failed to dump firmware (%x)!!!\n", rval);
365
366 free_pages((unsigned long)ha->fw_dump, ha->fw_dump_order);
367 ha->fw_dump = NULL;
368 } else {
369 qla_printk(KERN_INFO, ha,
370 "Firmware dump saved to temp buffer (%ld/%p).\n",
371 ha->host_no, ha->fw_dump);
372 }
373
374 qla2300_fw_dump_failed:
375 if (!hardware_locked)
376 spin_unlock_irqrestore(&ha->hardware_lock, flags);
377 }
378
379 /**
380 * qla2300_ascii_fw_dump() - Converts a binary firmware dump to ASCII.
381 * @ha: HA context
382 */
383 void
384 qla2300_ascii_fw_dump(scsi_qla_host_t *ha)
385 {
386 uint32_t cnt;
387 char *uiter;
388 char fw_info[30];
389 struct qla2300_fw_dump *fw;
390 uint32_t data_ram_cnt;
391
392 uiter = ha->fw_dump_buffer;
393 fw = ha->fw_dump;
394
395 qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
396 ha->isp_ops.fw_version_str(ha, fw_info));
397
398 qla_uprintf(&uiter, "\n[==>BEG]\n");
399
400 qla_uprintf(&uiter, "HCCR Register:\n%04x\n\n", fw->hccr);
401
402 qla_uprintf(&uiter, "PBIU Registers:");
403 for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
404 if (cnt % 8 == 0) {
405 qla_uprintf(&uiter, "\n");
406 }
407 qla_uprintf(&uiter, "%04x ", fw->pbiu_reg[cnt]);
408 }
409
410 qla_uprintf(&uiter, "\n\nReqQ-RspQ-Risc2Host Status registers:");
411 for (cnt = 0; cnt < sizeof (fw->risc_host_reg) / 2; cnt++) {
412 if (cnt % 8 == 0) {
413 qla_uprintf(&uiter, "\n");
414 }
415 qla_uprintf(&uiter, "%04x ", fw->risc_host_reg[cnt]);
416 }
417
418 qla_uprintf(&uiter, "\n\nMailbox Registers:");
419 for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
420 if (cnt % 8 == 0) {
421 qla_uprintf(&uiter, "\n");
422 }
423 qla_uprintf(&uiter, "%04x ", fw->mailbox_reg[cnt]);
424 }
425
426 qla_uprintf(&uiter, "\n\nAuto Request Response DMA Registers:");
427 for (cnt = 0; cnt < sizeof (fw->resp_dma_reg) / 2; cnt++) {
428 if (cnt % 8 == 0) {
429 qla_uprintf(&uiter, "\n");
430 }
431 qla_uprintf(&uiter, "%04x ", fw->resp_dma_reg[cnt]);
432 }
433
434 qla_uprintf(&uiter, "\n\nDMA Registers:");
435 for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
436 if (cnt % 8 == 0) {
437 qla_uprintf(&uiter, "\n");
438 }
439 qla_uprintf(&uiter, "%04x ", fw->dma_reg[cnt]);
440 }
441
442 qla_uprintf(&uiter, "\n\nRISC Hardware Registers:");
443 for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
444 if (cnt % 8 == 0) {
445 qla_uprintf(&uiter, "\n");
446 }
447 qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]);
448 }
449
450 qla_uprintf(&uiter, "\n\nRISC GP0 Registers:");
451 for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) {
452 if (cnt % 8 == 0) {
453 qla_uprintf(&uiter, "\n");
454 }
455 qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]);
456 }
457
458 qla_uprintf(&uiter, "\n\nRISC GP1 Registers:");
459 for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) {
460 if (cnt % 8 == 0) {
461 qla_uprintf(&uiter, "\n");
462 }
463 qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]);
464 }
465
466 qla_uprintf(&uiter, "\n\nRISC GP2 Registers:");
467 for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) {
468 if (cnt % 8 == 0) {
469 qla_uprintf(&uiter, "\n");
470 }
471 qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]);
472 }
473
474 qla_uprintf(&uiter, "\n\nRISC GP3 Registers:");
475 for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) {
476 if (cnt % 8 == 0) {
477 qla_uprintf(&uiter, "\n");
478 }
479 qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]);
480 }
481
482 qla_uprintf(&uiter, "\n\nRISC GP4 Registers:");
483 for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) {
484 if (cnt % 8 == 0) {
485 qla_uprintf(&uiter, "\n");
486 }
487 qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]);
488 }
489
490 qla_uprintf(&uiter, "\n\nRISC GP5 Registers:");
491 for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) {
492 if (cnt % 8 == 0) {
493 qla_uprintf(&uiter, "\n");
494 }
495 qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]);
496 }
497
498 qla_uprintf(&uiter, "\n\nRISC GP6 Registers:");
499 for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
500 if (cnt % 8 == 0) {
501 qla_uprintf(&uiter, "\n");
502 }
503 qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]);
504 }
505
506 qla_uprintf(&uiter, "\n\nRISC GP7 Registers:");
507 for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
508 if (cnt % 8 == 0) {
509 qla_uprintf(&uiter, "\n");
510 }
511 qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]);
512 }
513
514 qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:");
515 for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
516 if (cnt % 8 == 0) {
517 qla_uprintf(&uiter, "\n");
518 }
519 qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]);
520 }
521
522 qla_uprintf(&uiter, "\n\nFPM B0 Registers:");
523 for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
524 if (cnt % 8 == 0) {
525 qla_uprintf(&uiter, "\n");
526 }
527 qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]);
528 }
529
530 qla_uprintf(&uiter, "\n\nFPM B1 Registers:");
531 for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
532 if (cnt % 8 == 0) {
533 qla_uprintf(&uiter, "\n");
534 }
535 qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]);
536 }
537
538 qla_uprintf(&uiter, "\n\nCode RAM Dump:");
539 for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
540 if (cnt % 8 == 0) {
541 qla_uprintf(&uiter, "\n%04x: ", cnt + 0x0800);
542 }
543 qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]);
544 }
545
546 qla_uprintf(&uiter, "\n\nStack RAM Dump:");
547 for (cnt = 0; cnt < sizeof (fw->stack_ram) / 2; cnt++) {
548 if (cnt % 8 == 0) {
549 qla_uprintf(&uiter, "\n%05x: ", cnt + 0x10000);
550 }
551 qla_uprintf(&uiter, "%04x ", fw->stack_ram[cnt]);
552 }
553
554 qla_uprintf(&uiter, "\n\nData RAM Dump:");
555 data_ram_cnt = ha->fw_memory_size - 0x11000 + 1;
556 for (cnt = 0; cnt < data_ram_cnt; cnt++) {
557 if (cnt % 8 == 0) {
558 qla_uprintf(&uiter, "\n%05x: ", cnt + 0x11000);
559 }
560 qla_uprintf(&uiter, "%04x ", fw->data_ram[cnt]);
561 }
562
563 qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump.");
564 }
565
566 /**
567 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
568 * @ha: HA context
569 * @hardware_locked: Called with the hardware_lock
570 */
571 void
572 qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
573 {
574 int rval;
575 uint32_t cnt, timer;
576 uint16_t risc_address;
577 uint16_t mb0, mb2;
578 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
579 uint16_t __iomem *dmp_reg;
580 unsigned long flags;
581 struct qla2100_fw_dump *fw;
582
583 risc_address = 0;
584 mb0 = mb2 = 0;
585 flags = 0;
586
587 if (!hardware_locked)
588 spin_lock_irqsave(&ha->hardware_lock, flags);
589
590 if (ha->fw_dump != NULL) {
591 qla_printk(KERN_WARNING, ha,
592 "Firmware has been previously dumped (%p) -- ignoring "
593 "request...\n", ha->fw_dump);
594 goto qla2100_fw_dump_failed;
595 }
596
597 /* Allocate (large) dump buffer. */
598 ha->fw_dump_order = get_order(sizeof(struct qla2100_fw_dump));
599 ha->fw_dump = (struct qla2100_fw_dump *) __get_free_pages(GFP_ATOMIC,
600 ha->fw_dump_order);
601 if (ha->fw_dump == NULL) {
602 qla_printk(KERN_WARNING, ha,
603 "Unable to allocated memory for firmware dump (%d/%Zd).\n",
604 ha->fw_dump_order, sizeof(struct qla2100_fw_dump));
605 goto qla2100_fw_dump_failed;
606 }
607 fw = ha->fw_dump;
608
609 rval = QLA_SUCCESS;
610 fw->hccr = RD_REG_WORD(&reg->hccr);
611
612 /* Pause RISC. */
613 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
614 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
615 rval == QLA_SUCCESS; cnt--) {
616 if (cnt)
617 udelay(100);
618 else
619 rval = QLA_FUNCTION_TIMEOUT;
620 }
621 if (rval == QLA_SUCCESS) {
622 dmp_reg = (uint16_t __iomem *)(reg + 0);
623 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
624 fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
625
626 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10);
627 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
628 if (cnt == 8) {
629 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xe0);
630 }
631 fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++);
632 }
633
634 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x20);
635 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
636 fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
637
638 WRT_REG_WORD(&reg->ctrl_status, 0x00);
639 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0);
640 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
641 fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
642
643 WRT_REG_WORD(&reg->pcr, 0x2000);
644 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
645 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
646 fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
647
648 WRT_REG_WORD(&reg->pcr, 0x2100);
649 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
650 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
651 fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
652
653 WRT_REG_WORD(&reg->pcr, 0x2200);
654 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
655 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
656 fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
657
658 WRT_REG_WORD(&reg->pcr, 0x2300);
659 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
660 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
661 fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
662
663 WRT_REG_WORD(&reg->pcr, 0x2400);
664 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
665 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
666 fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
667
668 WRT_REG_WORD(&reg->pcr, 0x2500);
669 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
670 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
671 fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
672
673 WRT_REG_WORD(&reg->pcr, 0x2600);
674 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
675 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
676 fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
677
678 WRT_REG_WORD(&reg->pcr, 0x2700);
679 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
680 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
681 fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
682
683 WRT_REG_WORD(&reg->ctrl_status, 0x10);
684 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
685 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
686 fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
687
688 WRT_REG_WORD(&reg->ctrl_status, 0x20);
689 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
690 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
691 fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
692
693 WRT_REG_WORD(&reg->ctrl_status, 0x30);
694 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
695 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
696 fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
697
698 /* Reset the ISP. */
699 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
700 }
701
702 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
703 rval == QLA_SUCCESS; cnt--) {
704 if (cnt)
705 udelay(100);
706 else
707 rval = QLA_FUNCTION_TIMEOUT;
708 }
709
710 /* Pause RISC. */
711 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
712 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
713
714 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
715 for (cnt = 30000;
716 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
717 rval == QLA_SUCCESS; cnt--) {
718 if (cnt)
719 udelay(100);
720 else
721 rval = QLA_FUNCTION_TIMEOUT;
722 }
723 if (rval == QLA_SUCCESS) {
724 /* Set memory configuration and timing. */
725 if (IS_QLA2100(ha))
726 WRT_REG_WORD(&reg->mctr, 0xf1);
727 else
728 WRT_REG_WORD(&reg->mctr, 0xf2);
729 RD_REG_WORD(&reg->mctr); /* PCI Posting. */
730
731 /* Release RISC. */
732 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
733 }
734 }
735
736 if (rval == QLA_SUCCESS) {
737 /* Get RISC SRAM. */
738 risc_address = 0x1000;
739 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
740 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
741 }
742 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
743 cnt++, risc_address++) {
744 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
745 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
746
747 for (timer = 6000000; timer != 0; timer--) {
748 /* Check for pending interrupts. */
749 if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
750 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
751 set_bit(MBX_INTERRUPT,
752 &ha->mbx_cmd_flags);
753
754 mb0 = RD_MAILBOX_REG(ha, reg, 0);
755 mb2 = RD_MAILBOX_REG(ha, reg, 2);
756
757 WRT_REG_WORD(&reg->semaphore, 0);
758 WRT_REG_WORD(&reg->hccr,
759 HCCR_CLR_RISC_INT);
760 RD_REG_WORD(&reg->hccr);
761 break;
762 }
763 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
764 RD_REG_WORD(&reg->hccr);
765 }
766 udelay(5);
767 }
768
769 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
770 rval = mb0 & MBS_MASK;
771 fw->risc_ram[cnt] = mb2;
772 } else {
773 rval = QLA_FUNCTION_FAILED;
774 }
775 }
776
777 if (rval != QLA_SUCCESS) {
778 qla_printk(KERN_WARNING, ha,
779 "Failed to dump firmware (%x)!!!\n", rval);
780
781 free_pages((unsigned long)ha->fw_dump, ha->fw_dump_order);
782 ha->fw_dump = NULL;
783 } else {
784 qla_printk(KERN_INFO, ha,
785 "Firmware dump saved to temp buffer (%ld/%p).\n",
786 ha->host_no, ha->fw_dump);
787 }
788
789 qla2100_fw_dump_failed:
790 if (!hardware_locked)
791 spin_unlock_irqrestore(&ha->hardware_lock, flags);
792 }
793
794 /**
795 * qla2100_ascii_fw_dump() - Converts a binary firmware dump to ASCII.
796 * @ha: HA context
797 */
798 void
799 qla2100_ascii_fw_dump(scsi_qla_host_t *ha)
800 {
801 uint32_t cnt;
802 char *uiter;
803 char fw_info[30];
804 struct qla2100_fw_dump *fw;
805
806 uiter = ha->fw_dump_buffer;
807 fw = ha->fw_dump;
808
809 qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
810 ha->isp_ops.fw_version_str(ha, fw_info));
811
812 qla_uprintf(&uiter, "\n[==>BEG]\n");
813
814 qla_uprintf(&uiter, "HCCR Register:\n%04x\n\n", fw->hccr);
815
816 qla_uprintf(&uiter, "PBIU Registers:");
817 for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
818 if (cnt % 8 == 0) {
819 qla_uprintf(&uiter, "\n");
820 }
821 qla_uprintf(&uiter, "%04x ", fw->pbiu_reg[cnt]);
822 }
823
824 qla_uprintf(&uiter, "\n\nMailbox Registers:");
825 for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
826 if (cnt % 8 == 0) {
827 qla_uprintf(&uiter, "\n");
828 }
829 qla_uprintf(&uiter, "%04x ", fw->mailbox_reg[cnt]);
830 }
831
832 qla_uprintf(&uiter, "\n\nDMA Registers:");
833 for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
834 if (cnt % 8 == 0) {
835 qla_uprintf(&uiter, "\n");
836 }
837 qla_uprintf(&uiter, "%04x ", fw->dma_reg[cnt]);
838 }
839
840 qla_uprintf(&uiter, "\n\nRISC Hardware Registers:");
841 for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
842 if (cnt % 8 == 0) {
843 qla_uprintf(&uiter, "\n");
844 }
845 qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]);
846 }
847
848 qla_uprintf(&uiter, "\n\nRISC GP0 Registers:");
849 for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) {
850 if (cnt % 8 == 0) {
851 qla_uprintf(&uiter, "\n");
852 }
853 qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]);
854 }
855
856 qla_uprintf(&uiter, "\n\nRISC GP1 Registers:");
857 for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) {
858 if (cnt % 8 == 0) {
859 qla_uprintf(&uiter, "\n");
860 }
861 qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]);
862 }
863
864 qla_uprintf(&uiter, "\n\nRISC GP2 Registers:");
865 for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) {
866 if (cnt % 8 == 0) {
867 qla_uprintf(&uiter, "\n");
868 }
869 qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]);
870 }
871
872 qla_uprintf(&uiter, "\n\nRISC GP3 Registers:");
873 for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) {
874 if (cnt % 8 == 0) {
875 qla_uprintf(&uiter, "\n");
876 }
877 qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]);
878 }
879
880 qla_uprintf(&uiter, "\n\nRISC GP4 Registers:");
881 for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) {
882 if (cnt % 8 == 0) {
883 qla_uprintf(&uiter, "\n");
884 }
885 qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]);
886 }
887
888 qla_uprintf(&uiter, "\n\nRISC GP5 Registers:");
889 for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) {
890 if (cnt % 8 == 0) {
891 qla_uprintf(&uiter, "\n");
892 }
893 qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]);
894 }
895
896 qla_uprintf(&uiter, "\n\nRISC GP6 Registers:");
897 for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
898 if (cnt % 8 == 0) {
899 qla_uprintf(&uiter, "\n");
900 }
901 qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]);
902 }
903
904 qla_uprintf(&uiter, "\n\nRISC GP7 Registers:");
905 for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
906 if (cnt % 8 == 0) {
907 qla_uprintf(&uiter, "\n");
908 }
909 qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]);
910 }
911
912 qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:");
913 for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
914 if (cnt % 8 == 0) {
915 qla_uprintf(&uiter, "\n");
916 }
917 qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]);
918 }
919
920 qla_uprintf(&uiter, "\n\nFPM B0 Registers:");
921 for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
922 if (cnt % 8 == 0) {
923 qla_uprintf(&uiter, "\n");
924 }
925 qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]);
926 }
927
928 qla_uprintf(&uiter, "\n\nFPM B1 Registers:");
929 for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
930 if (cnt % 8 == 0) {
931 qla_uprintf(&uiter, "\n");
932 }
933 qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]);
934 }
935
936 qla_uprintf(&uiter, "\n\nRISC SRAM:");
937 for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
938 if (cnt % 8 == 0) {
939 qla_uprintf(&uiter, "\n%04x: ", cnt + 0x1000);
940 }
941 qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]);
942 }
943
944 qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump.");
945
946 return;
947 }
948
949 static int
950 qla_uprintf(char **uiter, char *fmt, ...)
951 {
952 int iter, len;
953 char buf[128];
954 va_list args;
955
956 va_start(args, fmt);
957 len = vsprintf(buf, fmt, args);
958 va_end(args);
959
960 for (iter = 0; iter < len; iter++, *uiter += 1)
961 *uiter[0] = buf[iter];
962
963 return (len);
964 }
965
966
967 void
968 qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
969 {
970 int rval;
971 uint32_t cnt, timer;
972 uint32_t risc_address;
973 uint16_t mb[4], wd;
974
975 uint32_t stat;
976 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
977 uint32_t __iomem *dmp_reg;
978 uint32_t *iter_reg;
979 uint16_t __iomem *mbx_reg;
980 unsigned long flags;
981 struct qla24xx_fw_dump *fw;
982 uint32_t ext_mem_cnt;
983
984 risc_address = ext_mem_cnt = 0;
985 memset(mb, 0, sizeof(mb));
986 flags = 0;
987
988 if (!hardware_locked)
989 spin_lock_irqsave(&ha->hardware_lock, flags);
990
991 if (!ha->fw_dump24) {
992 qla_printk(KERN_WARNING, ha,
993 "No buffer available for dump!!!\n");
994 goto qla24xx_fw_dump_failed;
995 }
996
997 if (ha->fw_dumped) {
998 qla_printk(KERN_WARNING, ha,
999 "Firmware has been previously dumped (%p) -- ignoring "
1000 "request...\n", ha->fw_dump24);
1001 goto qla24xx_fw_dump_failed;
1002 }
1003 fw = (struct qla24xx_fw_dump *) ha->fw_dump24;
1004
1005 rval = QLA_SUCCESS;
1006 fw->hccr = RD_REG_DWORD(&reg->hccr);
1007
1008 /* Pause RISC. */
1009 if ((fw->hccr & HCCRX_RISC_PAUSE) == 0) {
1010 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET |
1011 HCCRX_CLR_HOST_INT);
1012 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
1013 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
1014 for (cnt = 30000;
1015 (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0 &&
1016 rval == QLA_SUCCESS; cnt--) {
1017 if (cnt)
1018 udelay(100);
1019 else
1020 rval = QLA_FUNCTION_TIMEOUT;
1021 }
1022 }
1023
1024 /* Disable interrupts. */
1025 WRT_REG_DWORD(&reg->ictrl, 0);
1026 RD_REG_DWORD(&reg->ictrl);
1027
1028 if (rval == QLA_SUCCESS) {
1029 /* Host interface registers. */
1030 dmp_reg = (uint32_t __iomem *)(reg + 0);
1031 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1032 fw->host_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1033
1034 /* Mailbox registers. */
1035 mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
1036 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1037 fw->mailbox_reg[cnt] = RD_REG_WORD(mbx_reg++);
1038
1039 /* Transfer sequence registers. */
1040 iter_reg = fw->xseq_gp_reg;
1041 WRT_REG_DWORD(&reg->iobase_addr, 0xBF00);
1042 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1043 for (cnt = 0; cnt < 16; cnt++)
1044 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1045
1046 WRT_REG_DWORD(&reg->iobase_addr, 0xBF10);
1047 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1048 for (cnt = 0; cnt < 16; cnt++)
1049 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1050
1051 WRT_REG_DWORD(&reg->iobase_addr, 0xBF20);
1052 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1053 for (cnt = 0; cnt < 16; cnt++)
1054 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1055
1056 WRT_REG_DWORD(&reg->iobase_addr, 0xBF30);
1057 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1058 for (cnt = 0; cnt < 16; cnt++)
1059 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1060
1061 WRT_REG_DWORD(&reg->iobase_addr, 0xBF40);
1062 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1063 for (cnt = 0; cnt < 16; cnt++)
1064 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1065
1066 WRT_REG_DWORD(&reg->iobase_addr, 0xBF50);
1067 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1068 for (cnt = 0; cnt < 16; cnt++)
1069 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1070
1071 WRT_REG_DWORD(&reg->iobase_addr, 0xBF60);
1072 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1073 for (cnt = 0; cnt < 16; cnt++)
1074 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1075
1076 WRT_REG_DWORD(&reg->iobase_addr, 0xBF70);
1077 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1078 for (cnt = 0; cnt < 16; cnt++)
1079 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1080
1081 WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0);
1082 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1083 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++)
1084 fw->xseq_0_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1085
1086 WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0);
1087 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1088 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++)
1089 fw->xseq_1_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1090
1091 /* Receive sequence registers. */
1092 iter_reg = fw->rseq_gp_reg;
1093 WRT_REG_DWORD(&reg->iobase_addr, 0xFF00);
1094 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1095 for (cnt = 0; cnt < 16; cnt++)
1096 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1097
1098 WRT_REG_DWORD(&reg->iobase_addr, 0xFF10);
1099 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1100 for (cnt = 0; cnt < 16; cnt++)
1101 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1102
1103 WRT_REG_DWORD(&reg->iobase_addr, 0xFF20);
1104 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1105 for (cnt = 0; cnt < 16; cnt++)
1106 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1107
1108 WRT_REG_DWORD(&reg->iobase_addr, 0xFF30);
1109 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1110 for (cnt = 0; cnt < 16; cnt++)
1111 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1112
1113 WRT_REG_DWORD(&reg->iobase_addr, 0xFF40);
1114 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1115 for (cnt = 0; cnt < 16; cnt++)
1116 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1117
1118 WRT_REG_DWORD(&reg->iobase_addr, 0xFF50);
1119 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1120 for (cnt = 0; cnt < 16; cnt++)
1121 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1122
1123 WRT_REG_DWORD(&reg->iobase_addr, 0xFF60);
1124 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1125 for (cnt = 0; cnt < 16; cnt++)
1126 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1127
1128 WRT_REG_DWORD(&reg->iobase_addr, 0xFF70);
1129 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1130 for (cnt = 0; cnt < 16; cnt++)
1131 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1132
1133 WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0);
1134 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1135 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++)
1136 fw->rseq_0_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1137
1138 WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0);
1139 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1140 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++)
1141 fw->rseq_1_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1142
1143 WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0);
1144 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1145 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++)
1146 fw->rseq_2_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1147
1148 /* Command DMA registers. */
1149 WRT_REG_DWORD(&reg->iobase_addr, 0x7100);
1150 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1151 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++)
1152 fw->cmd_dma_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1153
1154 /* Queues. */
1155 iter_reg = fw->req0_dma_reg;
1156 WRT_REG_DWORD(&reg->iobase_addr, 0x7200);
1157 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1158 for (cnt = 0; cnt < 8; cnt++)
1159 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1160
1161 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
1162 for (cnt = 0; cnt < 7; cnt++)
1163 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1164
1165 iter_reg = fw->resp0_dma_reg;
1166 WRT_REG_DWORD(&reg->iobase_addr, 0x7300);
1167 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1168 for (cnt = 0; cnt < 8; cnt++)
1169 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1170
1171 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
1172 for (cnt = 0; cnt < 7; cnt++)
1173 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1174
1175 iter_reg = fw->req1_dma_reg;
1176 WRT_REG_DWORD(&reg->iobase_addr, 0x7400);
1177 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1178 for (cnt = 0; cnt < 8; cnt++)
1179 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1180
1181 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
1182 for (cnt = 0; cnt < 7; cnt++)
1183 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1184
1185 /* Transmit DMA registers. */
1186 iter_reg = fw->xmt0_dma_reg;
1187 WRT_REG_DWORD(&reg->iobase_addr, 0x7600);
1188 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1189 for (cnt = 0; cnt < 16; cnt++)
1190 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1191
1192 WRT_REG_DWORD(&reg->iobase_addr, 0x7610);
1193 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1194 for (cnt = 0; cnt < 16; cnt++)
1195 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1196
1197 iter_reg = fw->xmt1_dma_reg;
1198 WRT_REG_DWORD(&reg->iobase_addr, 0x7620);
1199 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1200 for (cnt = 0; cnt < 16; cnt++)
1201 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1202
1203 WRT_REG_DWORD(&reg->iobase_addr, 0x7630);
1204 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1205 for (cnt = 0; cnt < 16; cnt++)
1206 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1207
1208 iter_reg = fw->xmt2_dma_reg;
1209 WRT_REG_DWORD(&reg->iobase_addr, 0x7640);
1210 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1211 for (cnt = 0; cnt < 16; cnt++)
1212 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1213
1214 WRT_REG_DWORD(&reg->iobase_addr, 0x7650);
1215 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1216 for (cnt = 0; cnt < 16; cnt++)
1217 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1218
1219 iter_reg = fw->xmt3_dma_reg;
1220 WRT_REG_DWORD(&reg->iobase_addr, 0x7660);
1221 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1222 for (cnt = 0; cnt < 16; cnt++)
1223 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1224
1225 WRT_REG_DWORD(&reg->iobase_addr, 0x7670);
1226 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1227 for (cnt = 0; cnt < 16; cnt++)
1228 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1229
1230 iter_reg = fw->xmt4_dma_reg;
1231 WRT_REG_DWORD(&reg->iobase_addr, 0x7680);
1232 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1233 for (cnt = 0; cnt < 16; cnt++)
1234 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1235
1236 WRT_REG_DWORD(&reg->iobase_addr, 0x7690);
1237 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1238 for (cnt = 0; cnt < 16; cnt++)
1239 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1240
1241 WRT_REG_DWORD(&reg->iobase_addr, 0x76A0);
1242 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1243 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++)
1244 fw->xmt_data_dma_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1245
1246 /* Receive DMA registers. */
1247 iter_reg = fw->rcvt0_data_dma_reg;
1248 WRT_REG_DWORD(&reg->iobase_addr, 0x7700);
1249 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1250 for (cnt = 0; cnt < 16; cnt++)
1251 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1252
1253 WRT_REG_DWORD(&reg->iobase_addr, 0x7710);
1254 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1255 for (cnt = 0; cnt < 16; cnt++)
1256 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1257
1258 iter_reg = fw->rcvt1_data_dma_reg;
1259 WRT_REG_DWORD(&reg->iobase_addr, 0x7720);
1260 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1261 for (cnt = 0; cnt < 16; cnt++)
1262 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1263
1264 WRT_REG_DWORD(&reg->iobase_addr, 0x7730);
1265 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1266 for (cnt = 0; cnt < 16; cnt++)
1267 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1268
1269 /* RISC registers. */
1270 iter_reg = fw->risc_gp_reg;
1271 WRT_REG_DWORD(&reg->iobase_addr, 0x0F00);
1272 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1273 for (cnt = 0; cnt < 16; cnt++)
1274 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1275
1276 WRT_REG_DWORD(&reg->iobase_addr, 0x0F10);
1277 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1278 for (cnt = 0; cnt < 16; cnt++)
1279 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1280
1281 WRT_REG_DWORD(&reg->iobase_addr, 0x0F20);
1282 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1283 for (cnt = 0; cnt < 16; cnt++)
1284 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1285
1286 WRT_REG_DWORD(&reg->iobase_addr, 0x0F30);
1287 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1288 for (cnt = 0; cnt < 16; cnt++)
1289 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1290
1291 WRT_REG_DWORD(&reg->iobase_addr, 0x0F40);
1292 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1293 for (cnt = 0; cnt < 16; cnt++)
1294 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1295
1296 WRT_REG_DWORD(&reg->iobase_addr, 0x0F50);
1297 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1298 for (cnt = 0; cnt < 16; cnt++)
1299 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1300
1301 WRT_REG_DWORD(&reg->iobase_addr, 0x0F60);
1302 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1303 for (cnt = 0; cnt < 16; cnt++)
1304 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1305
1306 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1307 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1308 for (cnt = 0; cnt < 16; cnt++)
1309 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1310
1311 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1312 RD_REG_DWORD(&reg->iobase_addr);
1313 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1314 WRT_REG_DWORD(dmp_reg, 0xB0000000);
1315 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1316 fw->shadow_reg[0] = RD_REG_DWORD(dmp_reg);
1317
1318 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1319 WRT_REG_DWORD(dmp_reg, 0xB0100000);
1320 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1321 fw->shadow_reg[1] = RD_REG_DWORD(dmp_reg);
1322
1323 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1324 WRT_REG_DWORD(dmp_reg, 0xB0200000);
1325 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1326 fw->shadow_reg[2] = RD_REG_DWORD(dmp_reg);
1327
1328 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1329 WRT_REG_DWORD(dmp_reg, 0xB0300000);
1330 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1331 fw->shadow_reg[3] = RD_REG_DWORD(dmp_reg);
1332
1333 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1334 WRT_REG_DWORD(dmp_reg, 0xB0400000);
1335 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1336 fw->shadow_reg[4] = RD_REG_DWORD(dmp_reg);
1337
1338 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1339 WRT_REG_DWORD(dmp_reg, 0xB0500000);
1340 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1341 fw->shadow_reg[5] = RD_REG_DWORD(dmp_reg);
1342
1343 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1344 WRT_REG_DWORD(dmp_reg, 0xB0600000);
1345 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1346 fw->shadow_reg[6] = RD_REG_DWORD(dmp_reg);
1347
1348 /* Local memory controller registers. */
1349 iter_reg = fw->lmc_reg;
1350 WRT_REG_DWORD(&reg->iobase_addr, 0x3000);
1351 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1352 for (cnt = 0; cnt < 16; cnt++)
1353 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1354
1355 WRT_REG_DWORD(&reg->iobase_addr, 0x3010);
1356 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1357 for (cnt = 0; cnt < 16; cnt++)
1358 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1359
1360 WRT_REG_DWORD(&reg->iobase_addr, 0x3020);
1361 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1362 for (cnt = 0; cnt < 16; cnt++)
1363 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1364
1365 WRT_REG_DWORD(&reg->iobase_addr, 0x3030);
1366 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1367 for (cnt = 0; cnt < 16; cnt++)
1368 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1369
1370 WRT_REG_DWORD(&reg->iobase_addr, 0x3040);
1371 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1372 for (cnt = 0; cnt < 16; cnt++)
1373 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1374
1375 WRT_REG_DWORD(&reg->iobase_addr, 0x3050);
1376 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1377 for (cnt = 0; cnt < 16; cnt++)
1378 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1379
1380 WRT_REG_DWORD(&reg->iobase_addr, 0x3060);
1381 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1382 for (cnt = 0; cnt < 16; cnt++)
1383 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1384
1385 /* Fibre Protocol Module registers. */
1386 iter_reg = fw->fpm_hdw_reg;
1387 WRT_REG_DWORD(&reg->iobase_addr, 0x4000);
1388 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1389 for (cnt = 0; cnt < 16; cnt++)
1390 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1391
1392 WRT_REG_DWORD(&reg->iobase_addr, 0x4010);
1393 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1394 for (cnt = 0; cnt < 16; cnt++)
1395 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1396
1397 WRT_REG_DWORD(&reg->iobase_addr, 0x4020);
1398 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1399 for (cnt = 0; cnt < 16; cnt++)
1400 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1401
1402 WRT_REG_DWORD(&reg->iobase_addr, 0x4030);
1403 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1404 for (cnt = 0; cnt < 16; cnt++)
1405 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1406
1407 WRT_REG_DWORD(&reg->iobase_addr, 0x4040);
1408 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1409 for (cnt = 0; cnt < 16; cnt++)
1410 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1411
1412 WRT_REG_DWORD(&reg->iobase_addr, 0x4050);
1413 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1414 for (cnt = 0; cnt < 16; cnt++)
1415 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1416
1417 WRT_REG_DWORD(&reg->iobase_addr, 0x4060);
1418 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1419 for (cnt = 0; cnt < 16; cnt++)
1420 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1421
1422 WRT_REG_DWORD(&reg->iobase_addr, 0x4070);
1423 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1424 for (cnt = 0; cnt < 16; cnt++)
1425 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1426
1427 WRT_REG_DWORD(&reg->iobase_addr, 0x4080);
1428 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1429 for (cnt = 0; cnt < 16; cnt++)
1430 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1431
1432 WRT_REG_DWORD(&reg->iobase_addr, 0x4090);
1433 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1434 for (cnt = 0; cnt < 16; cnt++)
1435 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1436
1437 WRT_REG_DWORD(&reg->iobase_addr, 0x40A0);
1438 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1439 for (cnt = 0; cnt < 16; cnt++)
1440 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1441
1442 WRT_REG_DWORD(&reg->iobase_addr, 0x40B0);
1443 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1444 for (cnt = 0; cnt < 16; cnt++)
1445 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1446
1447 /* Frame Buffer registers. */
1448 iter_reg = fw->fb_hdw_reg;
1449 WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1450 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1451 for (cnt = 0; cnt < 16; cnt++)
1452 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1453
1454 WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1455 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1456 for (cnt = 0; cnt < 16; cnt++)
1457 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1458
1459 WRT_REG_DWORD(&reg->iobase_addr, 0x6020);
1460 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1461 for (cnt = 0; cnt < 16; cnt++)
1462 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1463
1464 WRT_REG_DWORD(&reg->iobase_addr, 0x6030);
1465 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1466 for (cnt = 0; cnt < 16; cnt++)
1467 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1468
1469 WRT_REG_DWORD(&reg->iobase_addr, 0x6040);
1470 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1471 for (cnt = 0; cnt < 16; cnt++)
1472 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1473
1474 WRT_REG_DWORD(&reg->iobase_addr, 0x6100);
1475 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1476 for (cnt = 0; cnt < 16; cnt++)
1477 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1478
1479 WRT_REG_DWORD(&reg->iobase_addr, 0x6130);
1480 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1481 for (cnt = 0; cnt < 16; cnt++)
1482 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1483
1484 WRT_REG_DWORD(&reg->iobase_addr, 0x6150);
1485 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1486 for (cnt = 0; cnt < 16; cnt++)
1487 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1488
1489 WRT_REG_DWORD(&reg->iobase_addr, 0x6170);
1490 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1491 for (cnt = 0; cnt < 16; cnt++)
1492 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1493
1494 WRT_REG_DWORD(&reg->iobase_addr, 0x6190);
1495 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1496 for (cnt = 0; cnt < 16; cnt++)
1497 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1498
1499 WRT_REG_DWORD(&reg->iobase_addr, 0x61B0);
1500 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1501 for (cnt = 0; cnt < 16; cnt++)
1502 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1503
1504 /* Reset RISC. */
1505 WRT_REG_DWORD(&reg->ctrl_status,
1506 CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1507 for (cnt = 0; cnt < 30000; cnt++) {
1508 if ((RD_REG_DWORD(&reg->ctrl_status) &
1509 CSRX_DMA_ACTIVE) == 0)
1510 break;
1511
1512 udelay(10);
1513 }
1514
1515 WRT_REG_DWORD(&reg->ctrl_status,
1516 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1517 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1518
1519 udelay(100);
1520 /* Wait for firmware to complete NVRAM accesses. */
1521 mb[0] = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1522 for (cnt = 10000 ; cnt && mb[0]; cnt--) {
1523 udelay(5);
1524 mb[0] = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1525 barrier();
1526 }
1527
1528 /* Wait for soft-reset to complete. */
1529 for (cnt = 0; cnt < 30000; cnt++) {
1530 if ((RD_REG_DWORD(&reg->ctrl_status) &
1531 CSRX_ISP_SOFT_RESET) == 0)
1532 break;
1533
1534 udelay(10);
1535 }
1536 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1537 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
1538 }
1539
1540 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
1541 rval == QLA_SUCCESS; cnt--) {
1542 if (cnt)
1543 udelay(100);
1544 else
1545 rval = QLA_FUNCTION_TIMEOUT;
1546 }
1547
1548 /* Memory. */
1549 if (rval == QLA_SUCCESS) {
1550 /* Code RAM. */
1551 risc_address = 0x20000;
1552 WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED);
1553 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
1554 }
1555 for (cnt = 0; cnt < sizeof(fw->code_ram) / 4 && rval == QLA_SUCCESS;
1556 cnt++, risc_address++) {
1557 WRT_REG_WORD(&reg->mailbox1, LSW(risc_address));
1558 WRT_REG_WORD(&reg->mailbox8, MSW(risc_address));
1559 RD_REG_WORD(&reg->mailbox8);
1560 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
1561
1562 for (timer = 6000000; timer; timer--) {
1563 /* Check for pending interrupts. */
1564 stat = RD_REG_DWORD(&reg->host_status);
1565 if (stat & HSRX_RISC_INT) {
1566 stat &= 0xff;
1567
1568 if (stat == 0x1 || stat == 0x2 ||
1569 stat == 0x10 || stat == 0x11) {
1570 set_bit(MBX_INTERRUPT,
1571 &ha->mbx_cmd_flags);
1572
1573 mb[0] = RD_REG_WORD(&reg->mailbox0);
1574 mb[2] = RD_REG_WORD(&reg->mailbox2);
1575 mb[3] = RD_REG_WORD(&reg->mailbox3);
1576
1577 WRT_REG_DWORD(&reg->hccr,
1578 HCCRX_CLR_RISC_INT);
1579 RD_REG_DWORD(&reg->hccr);
1580 break;
1581 }
1582
1583 /* Clear this intr; it wasn't a mailbox intr */
1584 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
1585 RD_REG_DWORD(&reg->hccr);
1586 }
1587 udelay(5);
1588 }
1589
1590 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
1591 rval = mb[0] & MBS_MASK;
1592 fw->code_ram[cnt] = (mb[3] << 16) | mb[2];
1593 } else {
1594 rval = QLA_FUNCTION_FAILED;
1595 }
1596 }
1597
1598 if (rval == QLA_SUCCESS) {
1599 /* External Memory. */
1600 risc_address = 0x100000;
1601 ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
1602 WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED);
1603 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
1604 }
1605 for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS;
1606 cnt++, risc_address++) {
1607 WRT_REG_WORD(&reg->mailbox1, LSW(risc_address));
1608 WRT_REG_WORD(&reg->mailbox8, MSW(risc_address));
1609 RD_REG_WORD(&reg->mailbox8);
1610 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
1611
1612 for (timer = 6000000; timer; timer--) {
1613 /* Check for pending interrupts. */
1614 stat = RD_REG_DWORD(&reg->host_status);
1615 if (stat & HSRX_RISC_INT) {
1616 stat &= 0xff;
1617
1618 if (stat == 0x1 || stat == 0x2 ||
1619 stat == 0x10 || stat == 0x11) {
1620 set_bit(MBX_INTERRUPT,
1621 &ha->mbx_cmd_flags);
1622
1623 mb[0] = RD_REG_WORD(&reg->mailbox0);
1624 mb[2] = RD_REG_WORD(&reg->mailbox2);
1625 mb[3] = RD_REG_WORD(&reg->mailbox3);
1626
1627 WRT_REG_DWORD(&reg->hccr,
1628 HCCRX_CLR_RISC_INT);
1629 RD_REG_DWORD(&reg->hccr);
1630 break;
1631 }
1632
1633 /* Clear this intr; it wasn't a mailbox intr */
1634 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
1635 RD_REG_DWORD(&reg->hccr);
1636 }
1637 udelay(5);
1638 }
1639
1640 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
1641 rval = mb[0] & MBS_MASK;
1642 fw->ext_mem[cnt] = (mb[3] << 16) | mb[2];
1643 } else {
1644 rval = QLA_FUNCTION_FAILED;
1645 }
1646 }
1647
1648 if (rval != QLA_SUCCESS) {
1649 qla_printk(KERN_WARNING, ha,
1650 "Failed to dump firmware (%x)!!!\n", rval);
1651 ha->fw_dumped = 0;
1652
1653 } else {
1654 qla_printk(KERN_INFO, ha,
1655 "Firmware dump saved to temp buffer (%ld/%p).\n",
1656 ha->host_no, ha->fw_dump24);
1657 ha->fw_dumped = 1;
1658 }
1659
1660 qla24xx_fw_dump_failed:
1661 if (!hardware_locked)
1662 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1663 }
1664
1665 void
1666 qla24xx_ascii_fw_dump(scsi_qla_host_t *ha)
1667 {
1668 uint32_t cnt;
1669 char *uiter;
1670 struct qla24xx_fw_dump *fw;
1671 uint32_t ext_mem_cnt;
1672
1673 uiter = ha->fw_dump_buffer;
1674 fw = ha->fw_dump24;
1675
1676 qla_uprintf(&uiter, "ISP FW Version %d.%02d.%02d Attributes %04x\n",
1677 ha->fw_major_version, ha->fw_minor_version,
1678 ha->fw_subminor_version, ha->fw_attributes);
1679
1680 qla_uprintf(&uiter, "\nHCCR Register\n%04x\n", fw->hccr);
1681
1682 qla_uprintf(&uiter, "\nHost Interface Registers");
1683 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) {
1684 if (cnt % 8 == 0)
1685 qla_uprintf(&uiter, "\n");
1686
1687 qla_uprintf(&uiter, "%08x ", fw->host_reg[cnt]);
1688 }
1689
1690 qla_uprintf(&uiter, "\n\nMailbox Registers");
1691 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) {
1692 if (cnt % 8 == 0)
1693 qla_uprintf(&uiter, "\n");
1694
1695 qla_uprintf(&uiter, "%08x ", fw->mailbox_reg[cnt]);
1696 }
1697
1698 qla_uprintf(&uiter, "\n\nXSEQ GP Registers");
1699 for (cnt = 0; cnt < sizeof(fw->xseq_gp_reg) / 4; cnt++) {
1700 if (cnt % 8 == 0)
1701 qla_uprintf(&uiter, "\n");
1702
1703 qla_uprintf(&uiter, "%08x ", fw->xseq_gp_reg[cnt]);
1704 }
1705
1706 qla_uprintf(&uiter, "\n\nXSEQ-0 Registers");
1707 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) {
1708 if (cnt % 8 == 0)
1709 qla_uprintf(&uiter, "\n");
1710
1711 qla_uprintf(&uiter, "%08x ", fw->xseq_0_reg[cnt]);
1712 }
1713
1714 qla_uprintf(&uiter, "\n\nXSEQ-1 Registers");
1715 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) {
1716 if (cnt % 8 == 0)
1717 qla_uprintf(&uiter, "\n");
1718
1719 qla_uprintf(&uiter, "%08x ", fw->xseq_1_reg[cnt]);
1720 }
1721
1722 qla_uprintf(&uiter, "\n\nRSEQ GP Registers");
1723 for (cnt = 0; cnt < sizeof(fw->rseq_gp_reg) / 4; cnt++) {
1724 if (cnt % 8 == 0)
1725 qla_uprintf(&uiter, "\n");
1726
1727 qla_uprintf(&uiter, "%08x ", fw->rseq_gp_reg[cnt]);
1728 }
1729
1730 qla_uprintf(&uiter, "\n\nRSEQ-0 Registers");
1731 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) {
1732 if (cnt % 8 == 0)
1733 qla_uprintf(&uiter, "\n");
1734
1735 qla_uprintf(&uiter, "%08x ", fw->rseq_0_reg[cnt]);
1736 }
1737
1738 qla_uprintf(&uiter, "\n\nRSEQ-1 Registers");
1739 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) {
1740 if (cnt % 8 == 0)
1741 qla_uprintf(&uiter, "\n");
1742
1743 qla_uprintf(&uiter, "%08x ", fw->rseq_1_reg[cnt]);
1744 }
1745
1746 qla_uprintf(&uiter, "\n\nRSEQ-2 Registers");
1747 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) {
1748 if (cnt % 8 == 0)
1749 qla_uprintf(&uiter, "\n");
1750
1751 qla_uprintf(&uiter, "%08x ", fw->rseq_2_reg[cnt]);
1752 }
1753
1754 qla_uprintf(&uiter, "\n\nCommand DMA Registers");
1755 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) {
1756 if (cnt % 8 == 0)
1757 qla_uprintf(&uiter, "\n");
1758
1759 qla_uprintf(&uiter, "%08x ", fw->cmd_dma_reg[cnt]);
1760 }
1761
1762 qla_uprintf(&uiter, "\n\nRequest0 Queue DMA Channel Registers");
1763 for (cnt = 0; cnt < sizeof(fw->req0_dma_reg) / 4; cnt++) {
1764 if (cnt % 8 == 0)
1765 qla_uprintf(&uiter, "\n");
1766
1767 qla_uprintf(&uiter, "%08x ", fw->req0_dma_reg[cnt]);
1768 }
1769
1770 qla_uprintf(&uiter, "\n\nResponse0 Queue DMA Channel Registers");
1771 for (cnt = 0; cnt < sizeof(fw->resp0_dma_reg) / 4; cnt++) {
1772 if (cnt % 8 == 0)
1773 qla_uprintf(&uiter, "\n");
1774
1775 qla_uprintf(&uiter, "%08x ", fw->resp0_dma_reg[cnt]);
1776 }
1777
1778 qla_uprintf(&uiter, "\n\nRequest1 Queue DMA Channel Registers");
1779 for (cnt = 0; cnt < sizeof(fw->req1_dma_reg) / 4; cnt++) {
1780 if (cnt % 8 == 0)
1781 qla_uprintf(&uiter, "\n");
1782
1783 qla_uprintf(&uiter, "%08x ", fw->req1_dma_reg[cnt]);
1784 }
1785
1786 qla_uprintf(&uiter, "\n\nXMT0 Data DMA Registers");
1787 for (cnt = 0; cnt < sizeof(fw->xmt0_dma_reg) / 4; cnt++) {
1788 if (cnt % 8 == 0)
1789 qla_uprintf(&uiter, "\n");
1790
1791 qla_uprintf(&uiter, "%08x ", fw->xmt0_dma_reg[cnt]);
1792 }
1793
1794 qla_uprintf(&uiter, "\n\nXMT1 Data DMA Registers");
1795 for (cnt = 0; cnt < sizeof(fw->xmt1_dma_reg) / 4; cnt++) {
1796 if (cnt % 8 == 0)
1797 qla_uprintf(&uiter, "\n");
1798
1799 qla_uprintf(&uiter, "%08x ", fw->xmt1_dma_reg[cnt]);
1800 }
1801
1802 qla_uprintf(&uiter, "\n\nXMT2 Data DMA Registers");
1803 for (cnt = 0; cnt < sizeof(fw->xmt2_dma_reg) / 4; cnt++) {
1804 if (cnt % 8 == 0)
1805 qla_uprintf(&uiter, "\n");
1806
1807 qla_uprintf(&uiter, "%08x ", fw->xmt2_dma_reg[cnt]);
1808 }
1809
1810 qla_uprintf(&uiter, "\n\nXMT3 Data DMA Registers");
1811 for (cnt = 0; cnt < sizeof(fw->xmt3_dma_reg) / 4; cnt++) {
1812 if (cnt % 8 == 0)
1813 qla_uprintf(&uiter, "\n");
1814
1815 qla_uprintf(&uiter, "%08x ", fw->xmt3_dma_reg[cnt]);
1816 }
1817
1818 qla_uprintf(&uiter, "\n\nXMT4 Data DMA Registers");
1819 for (cnt = 0; cnt < sizeof(fw->xmt4_dma_reg) / 4; cnt++) {
1820 if (cnt % 8 == 0)
1821 qla_uprintf(&uiter, "\n");
1822
1823 qla_uprintf(&uiter, "%08x ", fw->xmt4_dma_reg[cnt]);
1824 }
1825
1826 qla_uprintf(&uiter, "\n\nXMT Data DMA Common Registers");
1827 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) {
1828 if (cnt % 8 == 0)
1829 qla_uprintf(&uiter, "\n");
1830
1831 qla_uprintf(&uiter, "%08x ", fw->xmt_data_dma_reg[cnt]);
1832 }
1833
1834 qla_uprintf(&uiter, "\n\nRCV Thread 0 Data DMA Registers");
1835 for (cnt = 0; cnt < sizeof(fw->rcvt0_data_dma_reg) / 4; cnt++) {
1836 if (cnt % 8 == 0)
1837 qla_uprintf(&uiter, "\n");
1838
1839 qla_uprintf(&uiter, "%08x ", fw->rcvt0_data_dma_reg[cnt]);
1840 }
1841
1842 qla_uprintf(&uiter, "\n\nRCV Thread 1 Data DMA Registers");
1843 for (cnt = 0; cnt < sizeof(fw->rcvt1_data_dma_reg) / 4; cnt++) {
1844 if (cnt % 8 == 0)
1845 qla_uprintf(&uiter, "\n");
1846
1847 qla_uprintf(&uiter, "%08x ", fw->rcvt1_data_dma_reg[cnt]);
1848 }
1849
1850 qla_uprintf(&uiter, "\n\nRISC GP Registers");
1851 for (cnt = 0; cnt < sizeof(fw->risc_gp_reg) / 4; cnt++) {
1852 if (cnt % 8 == 0)
1853 qla_uprintf(&uiter, "\n");
1854
1855 qla_uprintf(&uiter, "%08x ", fw->risc_gp_reg[cnt]);
1856 }
1857
1858 qla_uprintf(&uiter, "\n\nShadow Registers");
1859 for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) {
1860 if (cnt % 8 == 0)
1861 qla_uprintf(&uiter, "\n");
1862
1863 qla_uprintf(&uiter, "%08x ", fw->shadow_reg[cnt]);
1864 }
1865
1866 qla_uprintf(&uiter, "\n\nLMC Registers");
1867 for (cnt = 0; cnt < sizeof(fw->lmc_reg) / 4; cnt++) {
1868 if (cnt % 8 == 0)
1869 qla_uprintf(&uiter, "\n");
1870
1871 qla_uprintf(&uiter, "%08x ", fw->lmc_reg[cnt]);
1872 }
1873
1874 qla_uprintf(&uiter, "\n\nFPM Hardware Registers");
1875 for (cnt = 0; cnt < sizeof(fw->fpm_hdw_reg) / 4; cnt++) {
1876 if (cnt % 8 == 0)
1877 qla_uprintf(&uiter, "\n");
1878
1879 qla_uprintf(&uiter, "%08x ", fw->fpm_hdw_reg[cnt]);
1880 }
1881
1882 qla_uprintf(&uiter, "\n\nFB Hardware Registers");
1883 for (cnt = 0; cnt < sizeof(fw->fb_hdw_reg) / 4; cnt++) {
1884 if (cnt % 8 == 0)
1885 qla_uprintf(&uiter, "\n");
1886
1887 qla_uprintf(&uiter, "%08x ", fw->fb_hdw_reg[cnt]);
1888 }
1889
1890 qla_uprintf(&uiter, "\n\nCode RAM");
1891 for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
1892 if (cnt % 8 == 0) {
1893 qla_uprintf(&uiter, "\n%08x: ", cnt + 0x20000);
1894 }
1895 qla_uprintf(&uiter, "%08x ", fw->code_ram[cnt]);
1896 }
1897
1898 qla_uprintf(&uiter, "\n\nExternal Memory");
1899 ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
1900 for (cnt = 0; cnt < ext_mem_cnt; cnt++) {
1901 if (cnt % 8 == 0) {
1902 qla_uprintf(&uiter, "\n%08x: ", cnt + 0x100000);
1903 }
1904 qla_uprintf(&uiter, "%08x ", fw->ext_mem[cnt]);
1905 }
1906
1907 qla_uprintf(&uiter, "\n[<==END] ISP Debug Dump");
1908 }
1909
1910
1911 /****************************************************************************/
1912 /* Driver Debug Functions. */
1913 /****************************************************************************/
1914
1915 void
1916 qla2x00_dump_regs(scsi_qla_host_t *ha)
1917 {
1918 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1919
1920 printk("Mailbox registers:\n");
1921 printk("scsi(%ld): mbox 0 0x%04x \n",
1922 ha->host_no, RD_MAILBOX_REG(ha, reg, 0));
1923 printk("scsi(%ld): mbox 1 0x%04x \n",
1924 ha->host_no, RD_MAILBOX_REG(ha, reg, 1));
1925 printk("scsi(%ld): mbox 2 0x%04x \n",
1926 ha->host_no, RD_MAILBOX_REG(ha, reg, 2));
1927 printk("scsi(%ld): mbox 3 0x%04x \n",
1928 ha->host_no, RD_MAILBOX_REG(ha, reg, 3));
1929 printk("scsi(%ld): mbox 4 0x%04x \n",
1930 ha->host_no, RD_MAILBOX_REG(ha, reg, 4));
1931 printk("scsi(%ld): mbox 5 0x%04x \n",
1932 ha->host_no, RD_MAILBOX_REG(ha, reg, 5));
1933 }
1934
1935
1936 void
1937 qla2x00_dump_buffer(uint8_t * b, uint32_t size)
1938 {
1939 uint32_t cnt;
1940 uint8_t c;
1941
1942 printk(" 0 1 2 3 4 5 6 7 8 9 "
1943 "Ah Bh Ch Dh Eh Fh\n");
1944 printk("----------------------------------------"
1945 "----------------------\n");
1946
1947 for (cnt = 0; cnt < size;) {
1948 c = *b++;
1949 printk("%02x",(uint32_t) c);
1950 cnt++;
1951 if (!(cnt % 16))
1952 printk("\n");
1953 else
1954 printk(" ");
1955 }
1956 if (cnt % 16)
1957 printk("\n");
1958 }
1959
1960 /**************************************************************************
1961 * qla2x00_print_scsi_cmd
1962 * Dumps out info about the scsi cmd and srb.
1963 * Input
1964 * cmd : struct scsi_cmnd
1965 **************************************************************************/
1966 void
1967 qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd)
1968 {
1969 int i;
1970 struct scsi_qla_host *ha;
1971 srb_t *sp;
1972
1973 ha = (struct scsi_qla_host *)cmd->device->host->hostdata;
1974
1975 sp = (srb_t *) cmd->SCp.ptr;
1976 printk("SCSI Command @=0x%p, Handle=0x%p\n", cmd, cmd->host_scribble);
1977 printk(" chan=0x%02x, target=0x%02x, lun=0x%02x, cmd_len=0x%02x\n",
1978 cmd->device->channel, cmd->device->id, cmd->device->lun,
1979 cmd->cmd_len);
1980 printk(" CDB: ");
1981 for (i = 0; i < cmd->cmd_len; i++) {
1982 printk("0x%02x ", cmd->cmnd[i]);
1983 }
1984 printk("\n seg_cnt=%d, allowed=%d, retries=%d\n",
1985 cmd->use_sg, cmd->allowed, cmd->retries);
1986 printk(" request buffer=0x%p, request buffer len=0x%x\n",
1987 cmd->request_buffer, cmd->request_bufflen);
1988 printk(" tag=%d, transfersize=0x%x\n",
1989 cmd->tag, cmd->transfersize);
1990 printk(" serial_number=%lx, SP=%p\n", cmd->serial_number, sp);
1991 printk(" data direction=%d\n", cmd->sc_data_direction);
1992
1993 if (!sp)
1994 return;
1995
1996 printk(" sp flags=0x%x\n", sp->flags);
1997 printk(" state=%d\n", sp->state);
1998 }
1999
2000 void
2001 qla2x00_dump_pkt(void *pkt)
2002 {
2003 uint32_t i;
2004 uint8_t *data = (uint8_t *) pkt;
2005
2006 for (i = 0; i < 64; i++) {
2007 if (!(i % 4))
2008 printk("\n%02x: ", i);
2009
2010 printk("%02x ", data[i]);
2011 }
2012 printk("\n");
2013 }
2014
2015 #if defined(QL_DEBUG_ROUTINES)
2016 /*
2017 * qla2x00_formatted_dump_buffer
2018 * Prints string plus buffer.
2019 *
2020 * Input:
2021 * string = Null terminated string (no newline at end).
2022 * buffer = buffer address.
2023 * wd_size = word size 8, 16, 32 or 64 bits
2024 * count = number of words.
2025 */
2026 void
2027 qla2x00_formatted_dump_buffer(char *string, uint8_t * buffer,
2028 uint8_t wd_size, uint32_t count)
2029 {
2030 uint32_t cnt;
2031 uint16_t *buf16;
2032 uint32_t *buf32;
2033
2034 if (strcmp(string, "") != 0)
2035 printk("%s\n",string);
2036
2037 switch (wd_size) {
2038 case 8:
2039 printk(" 0 1 2 3 4 5 6 7 "
2040 "8 9 Ah Bh Ch Dh Eh Fh\n");
2041 printk("-----------------------------------------"
2042 "-------------------------------------\n");
2043
2044 for (cnt = 1; cnt <= count; cnt++, buffer++) {
2045 printk("%02x",*buffer);
2046 if (cnt % 16 == 0)
2047 printk("\n");
2048 else
2049 printk(" ");
2050 }
2051 if (cnt % 16 != 0)
2052 printk("\n");
2053 break;
2054 case 16:
2055 printk(" 0 2 4 6 8 Ah "
2056 " Ch Eh\n");
2057 printk("-----------------------------------------"
2058 "-------------\n");
2059
2060 buf16 = (uint16_t *) buffer;
2061 for (cnt = 1; cnt <= count; cnt++, buf16++) {
2062 printk("%4x",*buf16);
2063
2064 if (cnt % 8 == 0)
2065 printk("\n");
2066 else if (*buf16 < 10)
2067 printk(" ");
2068 else
2069 printk(" ");
2070 }
2071 if (cnt % 8 != 0)
2072 printk("\n");
2073 break;
2074 case 32:
2075 printk(" 0 4 8 Ch\n");
2076 printk("------------------------------------------\n");
2077
2078 buf32 = (uint32_t *) buffer;
2079 for (cnt = 1; cnt <= count; cnt++, buf32++) {
2080 printk("%8x", *buf32);
2081
2082 if (cnt % 4 == 0)
2083 printk("\n");
2084 else if (*buf32 < 10)
2085 printk(" ");
2086 else
2087 printk(" ");
2088 }
2089 if (cnt % 4 != 0)
2090 printk("\n");
2091 break;
2092 default:
2093 break;
2094 }
2095 }
2096 #endif
Linux kernel - Deliverables
This page took 0.084425 seconds and 6 git commands to generate.