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Merge branch 'irq-fixes-for-linus-4' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_dbg.c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/delay.h>
10
11 static inline void
12 qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
13 {
14 fw_dump->fw_major_version = htonl(ha->fw_major_version);
15 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
16 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
17 fw_dump->fw_attributes = htonl(ha->fw_attributes);
18
19 fw_dump->vendor = htonl(ha->pdev->vendor);
20 fw_dump->device = htonl(ha->pdev->device);
21 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
22 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
23 }
24
25 static inline void *
26 qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
27 {
28 struct req_que *req = ha->req_q_map[0];
29 struct rsp_que *rsp = ha->rsp_q_map[0];
30 /* Request queue. */
31 memcpy(ptr, req->ring, req->length *
32 sizeof(request_t));
33
34 /* Response queue. */
35 ptr += req->length * sizeof(request_t);
36 memcpy(ptr, rsp->ring, rsp->length *
37 sizeof(response_t));
38
39 return ptr + (rsp->length * sizeof(response_t));
40 }
41
42 static int
43 qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
44 uint32_t ram_dwords, void **nxt)
45 {
46 int rval;
47 uint32_t cnt, stat, timer, dwords, idx;
48 uint16_t mb0;
49 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
50 dma_addr_t dump_dma = ha->gid_list_dma;
51 uint32_t *dump = (uint32_t *)ha->gid_list;
52
53 rval = QLA_SUCCESS;
54 mb0 = 0;
55
56 WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
57 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
58
59 dwords = GID_LIST_SIZE / 4;
60 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
61 cnt += dwords, addr += dwords) {
62 if (cnt + dwords > ram_dwords)
63 dwords = ram_dwords - cnt;
64
65 WRT_REG_WORD(&reg->mailbox1, LSW(addr));
66 WRT_REG_WORD(&reg->mailbox8, MSW(addr));
67
68 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
69 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
70 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
71 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
72
73 WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
74 WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
75 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
76
77 for (timer = 6000000; timer; timer--) {
78 /* Check for pending interrupts. */
79 stat = RD_REG_DWORD(&reg->host_status);
80 if (stat & HSRX_RISC_INT) {
81 stat &= 0xff;
82
83 if (stat == 0x1 || stat == 0x2 ||
84 stat == 0x10 || stat == 0x11) {
85 set_bit(MBX_INTERRUPT,
86 &ha->mbx_cmd_flags);
87
88 mb0 = RD_REG_WORD(&reg->mailbox0);
89
90 WRT_REG_DWORD(&reg->hccr,
91 HCCRX_CLR_RISC_INT);
92 RD_REG_DWORD(&reg->hccr);
93 break;
94 }
95
96 /* Clear this intr; it wasn't a mailbox intr */
97 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
98 RD_REG_DWORD(&reg->hccr);
99 }
100 udelay(5);
101 }
102
103 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
104 rval = mb0 & MBS_MASK;
105 for (idx = 0; idx < dwords; idx++)
106 ram[cnt + idx] = swab32(dump[idx]);
107 } else {
108 rval = QLA_FUNCTION_FAILED;
109 }
110 }
111
112 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
113 return rval;
114 }
115
116 static int
117 qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram,
118 uint32_t cram_size, void **nxt)
119 {
120 int rval;
121
122 /* Code RAM. */
123 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
124 if (rval != QLA_SUCCESS)
125 return rval;
126
127 /* External Memory. */
128 return qla24xx_dump_ram(ha, 0x100000, *nxt,
129 ha->fw_memory_size - 0x100000 + 1, nxt);
130 }
131
132 static uint32_t *
133 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
134 uint32_t count, uint32_t *buf)
135 {
136 uint32_t __iomem *dmp_reg;
137
138 WRT_REG_DWORD(&reg->iobase_addr, iobase);
139 dmp_reg = &reg->iobase_window;
140 while (count--)
141 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
142
143 return buf;
144 }
145
146 static inline int
147 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
148 {
149 int rval = QLA_SUCCESS;
150 uint32_t cnt;
151
152 if (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE)
153 return rval;
154
155 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
156 for (cnt = 30000; (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0 &&
157 rval == QLA_SUCCESS; cnt--) {
158 if (cnt)
159 udelay(100);
160 else
161 rval = QLA_FUNCTION_TIMEOUT;
162 }
163
164 return rval;
165 }
166
167 static int
168 qla24xx_soft_reset(struct qla_hw_data *ha)
169 {
170 int rval = QLA_SUCCESS;
171 uint32_t cnt;
172 uint16_t mb0, wd;
173 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
174
175 /* Reset RISC. */
176 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
177 for (cnt = 0; cnt < 30000; cnt++) {
178 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
179 break;
180
181 udelay(10);
182 }
183
184 WRT_REG_DWORD(&reg->ctrl_status,
185 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
186 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
187
188 udelay(100);
189 /* Wait for firmware to complete NVRAM accesses. */
190 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
191 for (cnt = 10000 ; cnt && mb0; cnt--) {
192 udelay(5);
193 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
194 barrier();
195 }
196
197 /* Wait for soft-reset to complete. */
198 for (cnt = 0; cnt < 30000; cnt++) {
199 if ((RD_REG_DWORD(&reg->ctrl_status) &
200 CSRX_ISP_SOFT_RESET) == 0)
201 break;
202
203 udelay(10);
204 }
205 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
206 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
207
208 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
209 rval == QLA_SUCCESS; cnt--) {
210 if (cnt)
211 udelay(100);
212 else
213 rval = QLA_FUNCTION_TIMEOUT;
214 }
215
216 return rval;
217 }
218
219 static int
220 qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram,
221 uint16_t ram_words, void **nxt)
222 {
223 int rval;
224 uint32_t cnt, stat, timer, words, idx;
225 uint16_t mb0;
226 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
227 dma_addr_t dump_dma = ha->gid_list_dma;
228 uint16_t *dump = (uint16_t *)ha->gid_list;
229
230 rval = QLA_SUCCESS;
231 mb0 = 0;
232
233 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
234 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
235
236 words = GID_LIST_SIZE / 2;
237 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
238 cnt += words, addr += words) {
239 if (cnt + words > ram_words)
240 words = ram_words - cnt;
241
242 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
243 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
244
245 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
246 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
247 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
248 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
249
250 WRT_MAILBOX_REG(ha, reg, 4, words);
251 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
252
253 for (timer = 6000000; timer; timer--) {
254 /* Check for pending interrupts. */
255 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
256 if (stat & HSR_RISC_INT) {
257 stat &= 0xff;
258
259 if (stat == 0x1 || stat == 0x2) {
260 set_bit(MBX_INTERRUPT,
261 &ha->mbx_cmd_flags);
262
263 mb0 = RD_MAILBOX_REG(ha, reg, 0);
264
265 /* Release mailbox registers. */
266 WRT_REG_WORD(&reg->semaphore, 0);
267 WRT_REG_WORD(&reg->hccr,
268 HCCR_CLR_RISC_INT);
269 RD_REG_WORD(&reg->hccr);
270 break;
271 } else if (stat == 0x10 || stat == 0x11) {
272 set_bit(MBX_INTERRUPT,
273 &ha->mbx_cmd_flags);
274
275 mb0 = RD_MAILBOX_REG(ha, reg, 0);
276
277 WRT_REG_WORD(&reg->hccr,
278 HCCR_CLR_RISC_INT);
279 RD_REG_WORD(&reg->hccr);
280 break;
281 }
282
283 /* clear this intr; it wasn't a mailbox intr */
284 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
285 RD_REG_WORD(&reg->hccr);
286 }
287 udelay(5);
288 }
289
290 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
291 rval = mb0 & MBS_MASK;
292 for (idx = 0; idx < words; idx++)
293 ram[cnt + idx] = swab16(dump[idx]);
294 } else {
295 rval = QLA_FUNCTION_FAILED;
296 }
297 }
298
299 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
300 return rval;
301 }
302
303 static inline void
304 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
305 uint16_t *buf)
306 {
307 uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
308
309 while (count--)
310 *buf++ = htons(RD_REG_WORD(dmp_reg++));
311 }
312
313 /**
314 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
315 * @ha: HA context
316 * @hardware_locked: Called with the hardware_lock
317 */
318 void
319 qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
320 {
321 int rval;
322 uint32_t cnt;
323 struct qla_hw_data *ha = vha->hw;
324 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
325 uint16_t __iomem *dmp_reg;
326 unsigned long flags;
327 struct qla2300_fw_dump *fw;
328 void *nxt;
329 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
330
331 flags = 0;
332
333 if (!hardware_locked)
334 spin_lock_irqsave(&ha->hardware_lock, flags);
335
336 if (!ha->fw_dump) {
337 qla_printk(KERN_WARNING, ha,
338 "No buffer available for dump!!!\n");
339 goto qla2300_fw_dump_failed;
340 }
341
342 if (ha->fw_dumped) {
343 qla_printk(KERN_WARNING, ha,
344 "Firmware has been previously dumped (%p) -- ignoring "
345 "request...\n", ha->fw_dump);
346 goto qla2300_fw_dump_failed;
347 }
348 fw = &ha->fw_dump->isp.isp23;
349 qla2xxx_prep_dump(ha, ha->fw_dump);
350
351 rval = QLA_SUCCESS;
352 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
353
354 /* Pause RISC. */
355 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
356 if (IS_QLA2300(ha)) {
357 for (cnt = 30000;
358 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
359 rval == QLA_SUCCESS; cnt--) {
360 if (cnt)
361 udelay(100);
362 else
363 rval = QLA_FUNCTION_TIMEOUT;
364 }
365 } else {
366 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
367 udelay(10);
368 }
369
370 if (rval == QLA_SUCCESS) {
371 dmp_reg = &reg->flash_address;
372 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
373 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
374
375 dmp_reg = &reg->u.isp2300.req_q_in;
376 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
377 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
378
379 dmp_reg = &reg->u.isp2300.mailbox0;
380 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
381 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
382
383 WRT_REG_WORD(&reg->ctrl_status, 0x40);
384 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
385
386 WRT_REG_WORD(&reg->ctrl_status, 0x50);
387 qla2xxx_read_window(reg, 48, fw->dma_reg);
388
389 WRT_REG_WORD(&reg->ctrl_status, 0x00);
390 dmp_reg = &reg->risc_hw;
391 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
392 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
393
394 WRT_REG_WORD(&reg->pcr, 0x2000);
395 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
396
397 WRT_REG_WORD(&reg->pcr, 0x2200);
398 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
399
400 WRT_REG_WORD(&reg->pcr, 0x2400);
401 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
402
403 WRT_REG_WORD(&reg->pcr, 0x2600);
404 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
405
406 WRT_REG_WORD(&reg->pcr, 0x2800);
407 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
408
409 WRT_REG_WORD(&reg->pcr, 0x2A00);
410 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
411
412 WRT_REG_WORD(&reg->pcr, 0x2C00);
413 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
414
415 WRT_REG_WORD(&reg->pcr, 0x2E00);
416 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
417
418 WRT_REG_WORD(&reg->ctrl_status, 0x10);
419 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
420
421 WRT_REG_WORD(&reg->ctrl_status, 0x20);
422 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
423
424 WRT_REG_WORD(&reg->ctrl_status, 0x30);
425 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
426
427 /* Reset RISC. */
428 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
429 for (cnt = 0; cnt < 30000; cnt++) {
430 if ((RD_REG_WORD(&reg->ctrl_status) &
431 CSR_ISP_SOFT_RESET) == 0)
432 break;
433
434 udelay(10);
435 }
436 }
437
438 if (!IS_QLA2300(ha)) {
439 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
440 rval == QLA_SUCCESS; cnt--) {
441 if (cnt)
442 udelay(100);
443 else
444 rval = QLA_FUNCTION_TIMEOUT;
445 }
446 }
447
448 /* Get RISC SRAM. */
449 if (rval == QLA_SUCCESS)
450 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
451 sizeof(fw->risc_ram) / 2, &nxt);
452
453 /* Get stack SRAM. */
454 if (rval == QLA_SUCCESS)
455 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
456 sizeof(fw->stack_ram) / 2, &nxt);
457
458 /* Get data SRAM. */
459 if (rval == QLA_SUCCESS)
460 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
461 ha->fw_memory_size - 0x11000 + 1, &nxt);
462
463 if (rval == QLA_SUCCESS)
464 qla2xxx_copy_queues(ha, nxt);
465
466 if (rval != QLA_SUCCESS) {
467 qla_printk(KERN_WARNING, ha,
468 "Failed to dump firmware (%x)!!!\n", rval);
469 ha->fw_dumped = 0;
470
471 } else {
472 qla_printk(KERN_INFO, ha,
473 "Firmware dump saved to temp buffer (%ld/%p).\n",
474 base_vha->host_no, ha->fw_dump);
475 ha->fw_dumped = 1;
476 }
477
478 qla2300_fw_dump_failed:
479 if (!hardware_locked)
480 spin_unlock_irqrestore(&ha->hardware_lock, flags);
481 }
482
483 /**
484 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
485 * @ha: HA context
486 * @hardware_locked: Called with the hardware_lock
487 */
488 void
489 qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
490 {
491 int rval;
492 uint32_t cnt, timer;
493 uint16_t risc_address;
494 uint16_t mb0, mb2;
495 struct qla_hw_data *ha = vha->hw;
496 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
497 uint16_t __iomem *dmp_reg;
498 unsigned long flags;
499 struct qla2100_fw_dump *fw;
500 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
501
502 risc_address = 0;
503 mb0 = mb2 = 0;
504 flags = 0;
505
506 if (!hardware_locked)
507 spin_lock_irqsave(&ha->hardware_lock, flags);
508
509 if (!ha->fw_dump) {
510 qla_printk(KERN_WARNING, ha,
511 "No buffer available for dump!!!\n");
512 goto qla2100_fw_dump_failed;
513 }
514
515 if (ha->fw_dumped) {
516 qla_printk(KERN_WARNING, ha,
517 "Firmware has been previously dumped (%p) -- ignoring "
518 "request...\n", ha->fw_dump);
519 goto qla2100_fw_dump_failed;
520 }
521 fw = &ha->fw_dump->isp.isp21;
522 qla2xxx_prep_dump(ha, ha->fw_dump);
523
524 rval = QLA_SUCCESS;
525 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
526
527 /* Pause RISC. */
528 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
529 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
530 rval == QLA_SUCCESS; cnt--) {
531 if (cnt)
532 udelay(100);
533 else
534 rval = QLA_FUNCTION_TIMEOUT;
535 }
536 if (rval == QLA_SUCCESS) {
537 dmp_reg = &reg->flash_address;
538 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
539 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
540
541 dmp_reg = &reg->u.isp2100.mailbox0;
542 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
543 if (cnt == 8)
544 dmp_reg = &reg->u_end.isp2200.mailbox8;
545
546 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
547 }
548
549 dmp_reg = &reg->u.isp2100.unused_2[0];
550 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
551 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
552
553 WRT_REG_WORD(&reg->ctrl_status, 0x00);
554 dmp_reg = &reg->risc_hw;
555 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
556 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
557
558 WRT_REG_WORD(&reg->pcr, 0x2000);
559 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
560
561 WRT_REG_WORD(&reg->pcr, 0x2100);
562 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
563
564 WRT_REG_WORD(&reg->pcr, 0x2200);
565 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
566
567 WRT_REG_WORD(&reg->pcr, 0x2300);
568 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
569
570 WRT_REG_WORD(&reg->pcr, 0x2400);
571 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
572
573 WRT_REG_WORD(&reg->pcr, 0x2500);
574 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
575
576 WRT_REG_WORD(&reg->pcr, 0x2600);
577 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
578
579 WRT_REG_WORD(&reg->pcr, 0x2700);
580 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
581
582 WRT_REG_WORD(&reg->ctrl_status, 0x10);
583 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
584
585 WRT_REG_WORD(&reg->ctrl_status, 0x20);
586 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
587
588 WRT_REG_WORD(&reg->ctrl_status, 0x30);
589 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
590
591 /* Reset the ISP. */
592 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
593 }
594
595 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
596 rval == QLA_SUCCESS; cnt--) {
597 if (cnt)
598 udelay(100);
599 else
600 rval = QLA_FUNCTION_TIMEOUT;
601 }
602
603 /* Pause RISC. */
604 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
605 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
606
607 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
608 for (cnt = 30000;
609 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
610 rval == QLA_SUCCESS; cnt--) {
611 if (cnt)
612 udelay(100);
613 else
614 rval = QLA_FUNCTION_TIMEOUT;
615 }
616 if (rval == QLA_SUCCESS) {
617 /* Set memory configuration and timing. */
618 if (IS_QLA2100(ha))
619 WRT_REG_WORD(&reg->mctr, 0xf1);
620 else
621 WRT_REG_WORD(&reg->mctr, 0xf2);
622 RD_REG_WORD(&reg->mctr); /* PCI Posting. */
623
624 /* Release RISC. */
625 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
626 }
627 }
628
629 if (rval == QLA_SUCCESS) {
630 /* Get RISC SRAM. */
631 risc_address = 0x1000;
632 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
633 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
634 }
635 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
636 cnt++, risc_address++) {
637 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
638 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
639
640 for (timer = 6000000; timer != 0; timer--) {
641 /* Check for pending interrupts. */
642 if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
643 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
644 set_bit(MBX_INTERRUPT,
645 &ha->mbx_cmd_flags);
646
647 mb0 = RD_MAILBOX_REG(ha, reg, 0);
648 mb2 = RD_MAILBOX_REG(ha, reg, 2);
649
650 WRT_REG_WORD(&reg->semaphore, 0);
651 WRT_REG_WORD(&reg->hccr,
652 HCCR_CLR_RISC_INT);
653 RD_REG_WORD(&reg->hccr);
654 break;
655 }
656 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
657 RD_REG_WORD(&reg->hccr);
658 }
659 udelay(5);
660 }
661
662 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
663 rval = mb0 & MBS_MASK;
664 fw->risc_ram[cnt] = htons(mb2);
665 } else {
666 rval = QLA_FUNCTION_FAILED;
667 }
668 }
669
670 if (rval == QLA_SUCCESS)
671 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
672
673 if (rval != QLA_SUCCESS) {
674 qla_printk(KERN_WARNING, ha,
675 "Failed to dump firmware (%x)!!!\n", rval);
676 ha->fw_dumped = 0;
677
678 } else {
679 qla_printk(KERN_INFO, ha,
680 "Firmware dump saved to temp buffer (%ld/%p).\n",
681 base_vha->host_no, ha->fw_dump);
682 ha->fw_dumped = 1;
683 }
684
685 qla2100_fw_dump_failed:
686 if (!hardware_locked)
687 spin_unlock_irqrestore(&ha->hardware_lock, flags);
688 }
689
690 void
691 qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
692 {
693 int rval;
694 uint32_t cnt;
695 uint32_t risc_address;
696 struct qla_hw_data *ha = vha->hw;
697 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
698 uint32_t __iomem *dmp_reg;
699 uint32_t *iter_reg;
700 uint16_t __iomem *mbx_reg;
701 unsigned long flags;
702 struct qla24xx_fw_dump *fw;
703 uint32_t ext_mem_cnt;
704 void *nxt;
705 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
706
707 risc_address = ext_mem_cnt = 0;
708 flags = 0;
709
710 if (!hardware_locked)
711 spin_lock_irqsave(&ha->hardware_lock, flags);
712
713 if (!ha->fw_dump) {
714 qla_printk(KERN_WARNING, ha,
715 "No buffer available for dump!!!\n");
716 goto qla24xx_fw_dump_failed;
717 }
718
719 if (ha->fw_dumped) {
720 qla_printk(KERN_WARNING, ha,
721 "Firmware has been previously dumped (%p) -- ignoring "
722 "request...\n", ha->fw_dump);
723 goto qla24xx_fw_dump_failed;
724 }
725 fw = &ha->fw_dump->isp.isp24;
726 qla2xxx_prep_dump(ha, ha->fw_dump);
727
728 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
729
730 /* Pause RISC. */
731 rval = qla24xx_pause_risc(reg);
732 if (rval != QLA_SUCCESS)
733 goto qla24xx_fw_dump_failed_0;
734
735 /* Host interface registers. */
736 dmp_reg = &reg->flash_addr;
737 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
738 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
739
740 /* Disable interrupts. */
741 WRT_REG_DWORD(&reg->ictrl, 0);
742 RD_REG_DWORD(&reg->ictrl);
743
744 /* Shadow registers. */
745 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
746 RD_REG_DWORD(&reg->iobase_addr);
747 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
748 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
749
750 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
751 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
752
753 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
754 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
755
756 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
757 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
758
759 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
760 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
761
762 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
763 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
764
765 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
766 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
767
768 /* Mailbox registers. */
769 mbx_reg = &reg->mailbox0;
770 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
771 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
772
773 /* Transfer sequence registers. */
774 iter_reg = fw->xseq_gp_reg;
775 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
776 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
777 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
778 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
779 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
780 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
781 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
782 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
783
784 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
785 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
786
787 /* Receive sequence registers. */
788 iter_reg = fw->rseq_gp_reg;
789 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
790 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
791 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
792 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
793 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
794 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
795 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
796 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
797
798 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
799 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
800 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
801
802 /* Command DMA registers. */
803 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
804
805 /* Queues. */
806 iter_reg = fw->req0_dma_reg;
807 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
808 dmp_reg = &reg->iobase_q;
809 for (cnt = 0; cnt < 7; cnt++)
810 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
811
812 iter_reg = fw->resp0_dma_reg;
813 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
814 dmp_reg = &reg->iobase_q;
815 for (cnt = 0; cnt < 7; cnt++)
816 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
817
818 iter_reg = fw->req1_dma_reg;
819 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
820 dmp_reg = &reg->iobase_q;
821 for (cnt = 0; cnt < 7; cnt++)
822 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
823
824 /* Transmit DMA registers. */
825 iter_reg = fw->xmt0_dma_reg;
826 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
827 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
828
829 iter_reg = fw->xmt1_dma_reg;
830 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
831 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
832
833 iter_reg = fw->xmt2_dma_reg;
834 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
835 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
836
837 iter_reg = fw->xmt3_dma_reg;
838 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
839 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
840
841 iter_reg = fw->xmt4_dma_reg;
842 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
843 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
844
845 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
846
847 /* Receive DMA registers. */
848 iter_reg = fw->rcvt0_data_dma_reg;
849 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
850 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
851
852 iter_reg = fw->rcvt1_data_dma_reg;
853 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
854 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
855
856 /* RISC registers. */
857 iter_reg = fw->risc_gp_reg;
858 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
859 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
860 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
861 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
862 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
863 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
864 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
865 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
866
867 /* Local memory controller registers. */
868 iter_reg = fw->lmc_reg;
869 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
870 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
871 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
872 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
873 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
874 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
875 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
876
877 /* Fibre Protocol Module registers. */
878 iter_reg = fw->fpm_hdw_reg;
879 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
880 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
881 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
882 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
883 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
884 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
885 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
886 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
887 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
888 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
889 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
890 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
891
892 /* Frame Buffer registers. */
893 iter_reg = fw->fb_hdw_reg;
894 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
895 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
896 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
897 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
898 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
899 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
900 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
901 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
902 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
903 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
904 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
905
906 rval = qla24xx_soft_reset(ha);
907 if (rval != QLA_SUCCESS)
908 goto qla24xx_fw_dump_failed_0;
909
910 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
911 &nxt);
912 if (rval != QLA_SUCCESS)
913 goto qla24xx_fw_dump_failed_0;
914
915 nxt = qla2xxx_copy_queues(ha, nxt);
916 if (ha->eft)
917 memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size));
918
919 qla24xx_fw_dump_failed_0:
920 if (rval != QLA_SUCCESS) {
921 qla_printk(KERN_WARNING, ha,
922 "Failed to dump firmware (%x)!!!\n", rval);
923 ha->fw_dumped = 0;
924
925 } else {
926 qla_printk(KERN_INFO, ha,
927 "Firmware dump saved to temp buffer (%ld/%p).\n",
928 base_vha->host_no, ha->fw_dump);
929 ha->fw_dumped = 1;
930 }
931
932 qla24xx_fw_dump_failed:
933 if (!hardware_locked)
934 spin_unlock_irqrestore(&ha->hardware_lock, flags);
935 }
936
937 void
938 qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
939 {
940 int rval;
941 uint32_t cnt;
942 uint32_t risc_address;
943 struct qla_hw_data *ha = vha->hw;
944 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
945 struct device_reg_25xxmq __iomem *reg25;
946 uint32_t __iomem *dmp_reg;
947 uint32_t *iter_reg;
948 uint16_t __iomem *mbx_reg;
949 unsigned long flags;
950 struct qla25xx_fw_dump *fw;
951 uint32_t ext_mem_cnt;
952 void *nxt;
953 struct qla2xxx_fce_chain *fcec;
954 struct qla2xxx_mq_chain *mq = NULL;
955 uint32_t qreg_size;
956 uint8_t req_cnt, rsp_cnt, que_cnt;
957 uint32_t que_idx;
958 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
959
960 risc_address = ext_mem_cnt = 0;
961 flags = 0;
962
963 if (!hardware_locked)
964 spin_lock_irqsave(&ha->hardware_lock, flags);
965
966 if (!ha->fw_dump) {
967 qla_printk(KERN_WARNING, ha,
968 "No buffer available for dump!!!\n");
969 goto qla25xx_fw_dump_failed;
970 }
971
972 if (ha->fw_dumped) {
973 qla_printk(KERN_WARNING, ha,
974 "Firmware has been previously dumped (%p) -- ignoring "
975 "request...\n", ha->fw_dump);
976 goto qla25xx_fw_dump_failed;
977 }
978 fw = &ha->fw_dump->isp.isp25;
979 qla2xxx_prep_dump(ha, ha->fw_dump);
980 ha->fw_dump->version = __constant_htonl(2);
981
982 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
983
984 /* Pause RISC. */
985 rval = qla24xx_pause_risc(reg);
986 if (rval != QLA_SUCCESS)
987 goto qla25xx_fw_dump_failed_0;
988
989 /* Host/Risc registers. */
990 iter_reg = fw->host_risc_reg;
991 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
992 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
993
994 /* PCIe registers. */
995 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
996 RD_REG_DWORD(&reg->iobase_addr);
997 WRT_REG_DWORD(&reg->iobase_window, 0x01);
998 dmp_reg = &reg->iobase_c4;
999 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1000 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1001 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1002 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1003
1004 /* Multi queue registers */
1005 if (ha->mqenable) {
1006 qreg_size = sizeof(struct qla2xxx_mq_chain);
1007 mq = kzalloc(qreg_size, GFP_KERNEL);
1008 if (!mq)
1009 goto qla25xx_fw_dump_failed_0;
1010 req_cnt = find_first_zero_bit(ha->req_qid_map, ha->max_queues);
1011 rsp_cnt = find_first_zero_bit(ha->rsp_qid_map, ha->max_queues);
1012 que_cnt = req_cnt > rsp_cnt ? req_cnt : rsp_cnt;
1013 mq->count = htonl(que_cnt);
1014 mq->chain_size = htonl(qreg_size);
1015 mq->type = __constant_htonl(DUMP_CHAIN_MQ);
1016 for (cnt = 0; cnt < que_cnt; cnt++) {
1017 reg25 = (struct device_reg_25xxmq *) ((void *)
1018 ha->mqiobase + cnt * QLA_QUE_PAGE);
1019 que_idx = cnt * 4;
1020 mq->qregs[que_idx] = htonl(reg25->req_q_in);
1021 mq->qregs[que_idx+1] = htonl(reg25->req_q_out);
1022 mq->qregs[que_idx+2] = htonl(reg25->rsp_q_in);
1023 mq->qregs[que_idx+3] = htonl(reg25->rsp_q_out);
1024 }
1025 }
1026 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1027 RD_REG_DWORD(&reg->iobase_window);
1028
1029 /* Host interface registers. */
1030 dmp_reg = &reg->flash_addr;
1031 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1032 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1033
1034 /* Disable interrupts. */
1035 WRT_REG_DWORD(&reg->ictrl, 0);
1036 RD_REG_DWORD(&reg->ictrl);
1037
1038 /* Shadow registers. */
1039 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1040 RD_REG_DWORD(&reg->iobase_addr);
1041 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1042 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1043
1044 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1045 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1046
1047 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1048 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1049
1050 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1051 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1052
1053 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1054 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1055
1056 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1057 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1058
1059 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1060 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1061
1062 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1063 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1064
1065 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1066 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1067
1068 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1069 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1070
1071 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1072 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1073
1074 /* RISC I/O register. */
1075 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1076 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1077
1078 /* Mailbox registers. */
1079 mbx_reg = &reg->mailbox0;
1080 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1081 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1082
1083 /* Transfer sequence registers. */
1084 iter_reg = fw->xseq_gp_reg;
1085 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1086 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1087 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1088 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1089 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1090 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1091 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1092 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1093
1094 iter_reg = fw->xseq_0_reg;
1095 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1096 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1097 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1098
1099 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1100
1101 /* Receive sequence registers. */
1102 iter_reg = fw->rseq_gp_reg;
1103 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1104 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1105 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1106 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1107 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1108 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1109 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1110 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1111
1112 iter_reg = fw->rseq_0_reg;
1113 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1114 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1115
1116 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1117 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1118
1119 /* Auxiliary sequence registers. */
1120 iter_reg = fw->aseq_gp_reg;
1121 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1122 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1123 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1124 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1125 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1126 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1127 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1128 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1129
1130 iter_reg = fw->aseq_0_reg;
1131 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1132 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1133
1134 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1135 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1136
1137 /* Command DMA registers. */
1138 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1139
1140 /* Queues. */
1141 iter_reg = fw->req0_dma_reg;
1142 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1143 dmp_reg = &reg->iobase_q;
1144 for (cnt = 0; cnt < 7; cnt++)
1145 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1146
1147 iter_reg = fw->resp0_dma_reg;
1148 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1149 dmp_reg = &reg->iobase_q;
1150 for (cnt = 0; cnt < 7; cnt++)
1151 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1152
1153 iter_reg = fw->req1_dma_reg;
1154 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1155 dmp_reg = &reg->iobase_q;
1156 for (cnt = 0; cnt < 7; cnt++)
1157 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1158
1159 /* Transmit DMA registers. */
1160 iter_reg = fw->xmt0_dma_reg;
1161 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1162 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1163
1164 iter_reg = fw->xmt1_dma_reg;
1165 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1166 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1167
1168 iter_reg = fw->xmt2_dma_reg;
1169 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1170 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1171
1172 iter_reg = fw->xmt3_dma_reg;
1173 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1174 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1175
1176 iter_reg = fw->xmt4_dma_reg;
1177 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1178 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1179
1180 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1181
1182 /* Receive DMA registers. */
1183 iter_reg = fw->rcvt0_data_dma_reg;
1184 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1185 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1186
1187 iter_reg = fw->rcvt1_data_dma_reg;
1188 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1189 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1190
1191 /* RISC registers. */
1192 iter_reg = fw->risc_gp_reg;
1193 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1194 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1195 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1196 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1197 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1198 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1199 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1200 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1201
1202 /* Local memory controller registers. */
1203 iter_reg = fw->lmc_reg;
1204 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1205 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1206 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1207 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1208 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1209 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1210 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1211 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1212
1213 /* Fibre Protocol Module registers. */
1214 iter_reg = fw->fpm_hdw_reg;
1215 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1216 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1217 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1218 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1219 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1220 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1221 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1222 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1223 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1224 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1225 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1226 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1227
1228 /* Frame Buffer registers. */
1229 iter_reg = fw->fb_hdw_reg;
1230 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1231 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1232 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1233 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1234 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1235 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1236 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1237 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1238 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1239 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1240 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1241 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1242
1243 rval = qla24xx_soft_reset(ha);
1244 if (rval != QLA_SUCCESS)
1245 goto qla25xx_fw_dump_failed_0;
1246
1247 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1248 &nxt);
1249 if (rval != QLA_SUCCESS)
1250 goto qla25xx_fw_dump_failed_0;
1251
1252 /* Fibre Channel Trace Buffer. */
1253 nxt = qla2xxx_copy_queues(ha, nxt);
1254 if (ha->eft)
1255 memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size));
1256
1257 /* Fibre Channel Event Buffer. */
1258 if (!ha->fce)
1259 goto qla25xx_fw_dump_failed_0;
1260
1261 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1262
1263 if (ha->mqenable) {
1264 nxt = nxt + ntohl(ha->fw_dump->eft_size);
1265 memcpy(nxt, mq, qreg_size);
1266 kfree(mq);
1267 fcec = nxt + qreg_size;
1268 } else {
1269 fcec = nxt + ntohl(ha->fw_dump->eft_size);
1270 }
1271 fcec->type = __constant_htonl(DUMP_CHAIN_FCE | DUMP_CHAIN_LAST);
1272 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
1273 fce_calc_size(ha->fce_bufs));
1274 fcec->size = htonl(fce_calc_size(ha->fce_bufs));
1275 fcec->addr_l = htonl(LSD(ha->fce_dma));
1276 fcec->addr_h = htonl(MSD(ha->fce_dma));
1277
1278 iter_reg = fcec->eregs;
1279 for (cnt = 0; cnt < 8; cnt++)
1280 *iter_reg++ = htonl(ha->fce_mb[cnt]);
1281
1282 memcpy(iter_reg, ha->fce, ntohl(fcec->size));
1283
1284 qla25xx_fw_dump_failed_0:
1285 if (rval != QLA_SUCCESS) {
1286 qla_printk(KERN_WARNING, ha,
1287 "Failed to dump firmware (%x)!!!\n", rval);
1288 ha->fw_dumped = 0;
1289
1290 } else {
1291 qla_printk(KERN_INFO, ha,
1292 "Firmware dump saved to temp buffer (%ld/%p).\n",
1293 base_vha->host_no, ha->fw_dump);
1294 ha->fw_dumped = 1;
1295 }
1296
1297 qla25xx_fw_dump_failed:
1298 if (!hardware_locked)
1299 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1300 }
1301 /****************************************************************************/
1302 /* Driver Debug Functions. */
1303 /****************************************************************************/
1304
1305 void
1306 qla2x00_dump_regs(scsi_qla_host_t *vha)
1307 {
1308 int i;
1309 struct qla_hw_data *ha = vha->hw;
1310 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1311 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
1312 uint16_t __iomem *mbx_reg;
1313
1314 mbx_reg = IS_FWI2_CAPABLE(ha) ? &reg24->mailbox0:
1315 MAILBOX_REG(ha, reg, 0);
1316
1317 printk("Mailbox registers:\n");
1318 for (i = 0; i < 6; i++)
1319 printk("scsi(%ld): mbox %d 0x%04x \n", vha->host_no, i,
1320 RD_REG_WORD(mbx_reg++));
1321 }
1322
1323
1324 void
1325 qla2x00_dump_buffer(uint8_t * b, uint32_t size)
1326 {
1327 uint32_t cnt;
1328 uint8_t c;
1329
1330 printk(" 0 1 2 3 4 5 6 7 8 9 "
1331 "Ah Bh Ch Dh Eh Fh\n");
1332 printk("----------------------------------------"
1333 "----------------------\n");
1334
1335 for (cnt = 0; cnt < size;) {
1336 c = *b++;
1337 printk("%02x",(uint32_t) c);
1338 cnt++;
1339 if (!(cnt % 16))
1340 printk("\n");
1341 else
1342 printk(" ");
1343 }
1344 if (cnt % 16)
1345 printk("\n");
1346 }
1347
1348
Linux kernel - Deliverables
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