projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'master' into upstream
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_dbg.c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/delay.h>
10
11 static int qla_uprintf(char **, char *, ...);
12
13 /**
14 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
15 * @ha: HA context
16 * @hardware_locked: Called with the hardware_lock
17 */
18 void
19 qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
20 {
21 int rval;
22 uint32_t cnt, timer;
23 uint32_t risc_address;
24 uint16_t mb0, mb2;
25
26 uint32_t stat;
27 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
28 uint16_t __iomem *dmp_reg;
29 unsigned long flags;
30 struct qla2300_fw_dump *fw;
31 uint32_t data_ram_cnt;
32
33 risc_address = data_ram_cnt = 0;
34 mb0 = mb2 = 0;
35 flags = 0;
36
37 if (!hardware_locked)
38 spin_lock_irqsave(&ha->hardware_lock, flags);
39
40 if (!ha->fw_dump) {
41 qla_printk(KERN_WARNING, ha,
42 "No buffer available for dump!!!\n");
43 goto qla2300_fw_dump_failed;
44 }
45
46 if (ha->fw_dumped) {
47 qla_printk(KERN_WARNING, ha,
48 "Firmware has been previously dumped (%p) -- ignoring "
49 "request...\n", ha->fw_dump);
50 goto qla2300_fw_dump_failed;
51 }
52 fw = ha->fw_dump;
53
54 rval = QLA_SUCCESS;
55 fw->hccr = RD_REG_WORD(&reg->hccr);
56
57 /* Pause RISC. */
58 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
59 if (IS_QLA2300(ha)) {
60 for (cnt = 30000;
61 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
62 rval == QLA_SUCCESS; cnt--) {
63 if (cnt)
64 udelay(100);
65 else
66 rval = QLA_FUNCTION_TIMEOUT;
67 }
68 } else {
69 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
70 udelay(10);
71 }
72
73 if (rval == QLA_SUCCESS) {
74 dmp_reg = (uint16_t __iomem *)(reg + 0);
75 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
76 fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
77
78 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10);
79 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
80 fw->risc_host_reg[cnt] = RD_REG_WORD(dmp_reg++);
81
82 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x40);
83 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
84 fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++);
85
86 WRT_REG_WORD(&reg->ctrl_status, 0x40);
87 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
88 for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++)
89 fw->resp_dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
90
91 WRT_REG_WORD(&reg->ctrl_status, 0x50);
92 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
93 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
94 fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
95
96 WRT_REG_WORD(&reg->ctrl_status, 0x00);
97 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0);
98 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
99 fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
100
101 WRT_REG_WORD(&reg->pcr, 0x2000);
102 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
103 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
104 fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
105
106 WRT_REG_WORD(&reg->pcr, 0x2200);
107 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
108 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
109 fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
110
111 WRT_REG_WORD(&reg->pcr, 0x2400);
112 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
113 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
114 fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
115
116 WRT_REG_WORD(&reg->pcr, 0x2600);
117 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
118 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
119 fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
120
121 WRT_REG_WORD(&reg->pcr, 0x2800);
122 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
123 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
124 fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
125
126 WRT_REG_WORD(&reg->pcr, 0x2A00);
127 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
128 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
129 fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
130
131 WRT_REG_WORD(&reg->pcr, 0x2C00);
132 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
133 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
134 fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
135
136 WRT_REG_WORD(&reg->pcr, 0x2E00);
137 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
138 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
139 fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
140
141 WRT_REG_WORD(&reg->ctrl_status, 0x10);
142 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
143 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
144 fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
145
146 WRT_REG_WORD(&reg->ctrl_status, 0x20);
147 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
148 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
149 fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
150
151 WRT_REG_WORD(&reg->ctrl_status, 0x30);
152 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
153 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
154 fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
155
156 /* Reset RISC. */
157 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
158 for (cnt = 0; cnt < 30000; cnt++) {
159 if ((RD_REG_WORD(&reg->ctrl_status) &
160 CSR_ISP_SOFT_RESET) == 0)
161 break;
162
163 udelay(10);
164 }
165 }
166
167 if (!IS_QLA2300(ha)) {
168 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
169 rval == QLA_SUCCESS; cnt--) {
170 if (cnt)
171 udelay(100);
172 else
173 rval = QLA_FUNCTION_TIMEOUT;
174 }
175 }
176
177 if (rval == QLA_SUCCESS) {
178 /* Get RISC SRAM. */
179 risc_address = 0x800;
180 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
181 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
182 }
183 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
184 cnt++, risc_address++) {
185 WRT_MAILBOX_REG(ha, reg, 1, (uint16_t)risc_address);
186 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
187
188 for (timer = 6000000; timer; timer--) {
189 /* Check for pending interrupts. */
190 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
191 if (stat & HSR_RISC_INT) {
192 stat &= 0xff;
193
194 if (stat == 0x1 || stat == 0x2) {
195 set_bit(MBX_INTERRUPT,
196 &ha->mbx_cmd_flags);
197
198 mb0 = RD_MAILBOX_REG(ha, reg, 0);
199 mb2 = RD_MAILBOX_REG(ha, reg, 2);
200
201 /* Release mailbox registers. */
202 WRT_REG_WORD(&reg->semaphore, 0);
203 WRT_REG_WORD(&reg->hccr,
204 HCCR_CLR_RISC_INT);
205 RD_REG_WORD(&reg->hccr);
206 break;
207 } else if (stat == 0x10 || stat == 0x11) {
208 set_bit(MBX_INTERRUPT,
209 &ha->mbx_cmd_flags);
210
211 mb0 = RD_MAILBOX_REG(ha, reg, 0);
212 mb2 = RD_MAILBOX_REG(ha, reg, 2);
213
214 WRT_REG_WORD(&reg->hccr,
215 HCCR_CLR_RISC_INT);
216 RD_REG_WORD(&reg->hccr);
217 break;
218 }
219
220 /* clear this intr; it wasn't a mailbox intr */
221 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
222 RD_REG_WORD(&reg->hccr);
223 }
224 udelay(5);
225 }
226
227 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
228 rval = mb0 & MBS_MASK;
229 fw->risc_ram[cnt] = mb2;
230 } else {
231 rval = QLA_FUNCTION_FAILED;
232 }
233 }
234
235 if (rval == QLA_SUCCESS) {
236 /* Get stack SRAM. */
237 risc_address = 0x10000;
238 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED);
239 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
240 }
241 for (cnt = 0; cnt < sizeof(fw->stack_ram) / 2 && rval == QLA_SUCCESS;
242 cnt++, risc_address++) {
243 WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address));
244 WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address));
245 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
246
247 for (timer = 6000000; timer; timer--) {
248 /* Check for pending interrupts. */
249 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
250 if (stat & HSR_RISC_INT) {
251 stat &= 0xff;
252
253 if (stat == 0x1 || stat == 0x2) {
254 set_bit(MBX_INTERRUPT,
255 &ha->mbx_cmd_flags);
256
257 mb0 = RD_MAILBOX_REG(ha, reg, 0);
258 mb2 = RD_MAILBOX_REG(ha, reg, 2);
259
260 /* Release mailbox registers. */
261 WRT_REG_WORD(&reg->semaphore, 0);
262 WRT_REG_WORD(&reg->hccr,
263 HCCR_CLR_RISC_INT);
264 RD_REG_WORD(&reg->hccr);
265 break;
266 } else if (stat == 0x10 || stat == 0x11) {
267 set_bit(MBX_INTERRUPT,
268 &ha->mbx_cmd_flags);
269
270 mb0 = RD_MAILBOX_REG(ha, reg, 0);
271 mb2 = RD_MAILBOX_REG(ha, reg, 2);
272
273 WRT_REG_WORD(&reg->hccr,
274 HCCR_CLR_RISC_INT);
275 RD_REG_WORD(&reg->hccr);
276 break;
277 }
278
279 /* clear this intr; it wasn't a mailbox intr */
280 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
281 RD_REG_WORD(&reg->hccr);
282 }
283 udelay(5);
284 }
285
286 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
287 rval = mb0 & MBS_MASK;
288 fw->stack_ram[cnt] = mb2;
289 } else {
290 rval = QLA_FUNCTION_FAILED;
291 }
292 }
293
294 if (rval == QLA_SUCCESS) {
295 /* Get data SRAM. */
296 risc_address = 0x11000;
297 data_ram_cnt = ha->fw_memory_size - risc_address + 1;
298 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED);
299 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
300 }
301 for (cnt = 0; cnt < data_ram_cnt && rval == QLA_SUCCESS;
302 cnt++, risc_address++) {
303 WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address));
304 WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address));
305 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
306
307 for (timer = 6000000; timer; timer--) {
308 /* Check for pending interrupts. */
309 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
310 if (stat & HSR_RISC_INT) {
311 stat &= 0xff;
312
313 if (stat == 0x1 || stat == 0x2) {
314 set_bit(MBX_INTERRUPT,
315 &ha->mbx_cmd_flags);
316
317 mb0 = RD_MAILBOX_REG(ha, reg, 0);
318 mb2 = RD_MAILBOX_REG(ha, reg, 2);
319
320 /* Release mailbox registers. */
321 WRT_REG_WORD(&reg->semaphore, 0);
322 WRT_REG_WORD(&reg->hccr,
323 HCCR_CLR_RISC_INT);
324 RD_REG_WORD(&reg->hccr);
325 break;
326 } else if (stat == 0x10 || stat == 0x11) {
327 set_bit(MBX_INTERRUPT,
328 &ha->mbx_cmd_flags);
329
330 mb0 = RD_MAILBOX_REG(ha, reg, 0);
331 mb2 = RD_MAILBOX_REG(ha, reg, 2);
332
333 WRT_REG_WORD(&reg->hccr,
334 HCCR_CLR_RISC_INT);
335 RD_REG_WORD(&reg->hccr);
336 break;
337 }
338
339 /* clear this intr; it wasn't a mailbox intr */
340 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
341 RD_REG_WORD(&reg->hccr);
342 }
343 udelay(5);
344 }
345
346 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
347 rval = mb0 & MBS_MASK;
348 fw->data_ram[cnt] = mb2;
349 } else {
350 rval = QLA_FUNCTION_FAILED;
351 }
352 }
353
354 if (rval != QLA_SUCCESS) {
355 qla_printk(KERN_WARNING, ha,
356 "Failed to dump firmware (%x)!!!\n", rval);
357 ha->fw_dumped = 0;
358
359 } else {
360 qla_printk(KERN_INFO, ha,
361 "Firmware dump saved to temp buffer (%ld/%p).\n",
362 ha->host_no, ha->fw_dump);
363 ha->fw_dumped = 1;
364 }
365
366 qla2300_fw_dump_failed:
367 if (!hardware_locked)
368 spin_unlock_irqrestore(&ha->hardware_lock, flags);
369 }
370
371 /**
372 * qla2300_ascii_fw_dump() - Converts a binary firmware dump to ASCII.
373 * @ha: HA context
374 */
375 void
376 qla2300_ascii_fw_dump(scsi_qla_host_t *ha)
377 {
378 uint32_t cnt;
379 char *uiter;
380 char fw_info[30];
381 struct qla2300_fw_dump *fw;
382 uint32_t data_ram_cnt;
383
384 uiter = ha->fw_dump_buffer;
385 fw = ha->fw_dump;
386
387 qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
388 ha->isp_ops.fw_version_str(ha, fw_info));
389
390 qla_uprintf(&uiter, "\n[==>BEG]\n");
391
392 qla_uprintf(&uiter, "HCCR Register:\n%04x\n\n", fw->hccr);
393
394 qla_uprintf(&uiter, "PBIU Registers:");
395 for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
396 if (cnt % 8 == 0) {
397 qla_uprintf(&uiter, "\n");
398 }
399 qla_uprintf(&uiter, "%04x ", fw->pbiu_reg[cnt]);
400 }
401
402 qla_uprintf(&uiter, "\n\nReqQ-RspQ-Risc2Host Status registers:");
403 for (cnt = 0; cnt < sizeof (fw->risc_host_reg) / 2; cnt++) {
404 if (cnt % 8 == 0) {
405 qla_uprintf(&uiter, "\n");
406 }
407 qla_uprintf(&uiter, "%04x ", fw->risc_host_reg[cnt]);
408 }
409
410 qla_uprintf(&uiter, "\n\nMailbox Registers:");
411 for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
412 if (cnt % 8 == 0) {
413 qla_uprintf(&uiter, "\n");
414 }
415 qla_uprintf(&uiter, "%04x ", fw->mailbox_reg[cnt]);
416 }
417
418 qla_uprintf(&uiter, "\n\nAuto Request Response DMA Registers:");
419 for (cnt = 0; cnt < sizeof (fw->resp_dma_reg) / 2; cnt++) {
420 if (cnt % 8 == 0) {
421 qla_uprintf(&uiter, "\n");
422 }
423 qla_uprintf(&uiter, "%04x ", fw->resp_dma_reg[cnt]);
424 }
425
426 qla_uprintf(&uiter, "\n\nDMA Registers:");
427 for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
428 if (cnt % 8 == 0) {
429 qla_uprintf(&uiter, "\n");
430 }
431 qla_uprintf(&uiter, "%04x ", fw->dma_reg[cnt]);
432 }
433
434 qla_uprintf(&uiter, "\n\nRISC Hardware Registers:");
435 for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
436 if (cnt % 8 == 0) {
437 qla_uprintf(&uiter, "\n");
438 }
439 qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]);
440 }
441
442 qla_uprintf(&uiter, "\n\nRISC GP0 Registers:");
443 for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) {
444 if (cnt % 8 == 0) {
445 qla_uprintf(&uiter, "\n");
446 }
447 qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]);
448 }
449
450 qla_uprintf(&uiter, "\n\nRISC GP1 Registers:");
451 for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) {
452 if (cnt % 8 == 0) {
453 qla_uprintf(&uiter, "\n");
454 }
455 qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]);
456 }
457
458 qla_uprintf(&uiter, "\n\nRISC GP2 Registers:");
459 for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) {
460 if (cnt % 8 == 0) {
461 qla_uprintf(&uiter, "\n");
462 }
463 qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]);
464 }
465
466 qla_uprintf(&uiter, "\n\nRISC GP3 Registers:");
467 for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) {
468 if (cnt % 8 == 0) {
469 qla_uprintf(&uiter, "\n");
470 }
471 qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]);
472 }
473
474 qla_uprintf(&uiter, "\n\nRISC GP4 Registers:");
475 for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) {
476 if (cnt % 8 == 0) {
477 qla_uprintf(&uiter, "\n");
478 }
479 qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]);
480 }
481
482 qla_uprintf(&uiter, "\n\nRISC GP5 Registers:");
483 for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) {
484 if (cnt % 8 == 0) {
485 qla_uprintf(&uiter, "\n");
486 }
487 qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]);
488 }
489
490 qla_uprintf(&uiter, "\n\nRISC GP6 Registers:");
491 for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
492 if (cnt % 8 == 0) {
493 qla_uprintf(&uiter, "\n");
494 }
495 qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]);
496 }
497
498 qla_uprintf(&uiter, "\n\nRISC GP7 Registers:");
499 for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
500 if (cnt % 8 == 0) {
501 qla_uprintf(&uiter, "\n");
502 }
503 qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]);
504 }
505
506 qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:");
507 for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
508 if (cnt % 8 == 0) {
509 qla_uprintf(&uiter, "\n");
510 }
511 qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]);
512 }
513
514 qla_uprintf(&uiter, "\n\nFPM B0 Registers:");
515 for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
516 if (cnt % 8 == 0) {
517 qla_uprintf(&uiter, "\n");
518 }
519 qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]);
520 }
521
522 qla_uprintf(&uiter, "\n\nFPM B1 Registers:");
523 for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
524 if (cnt % 8 == 0) {
525 qla_uprintf(&uiter, "\n");
526 }
527 qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]);
528 }
529
530 qla_uprintf(&uiter, "\n\nCode RAM Dump:");
531 for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
532 if (cnt % 8 == 0) {
533 qla_uprintf(&uiter, "\n%04x: ", cnt + 0x0800);
534 }
535 qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]);
536 }
537
538 qla_uprintf(&uiter, "\n\nStack RAM Dump:");
539 for (cnt = 0; cnt < sizeof (fw->stack_ram) / 2; cnt++) {
540 if (cnt % 8 == 0) {
541 qla_uprintf(&uiter, "\n%05x: ", cnt + 0x10000);
542 }
543 qla_uprintf(&uiter, "%04x ", fw->stack_ram[cnt]);
544 }
545
546 qla_uprintf(&uiter, "\n\nData RAM Dump:");
547 data_ram_cnt = ha->fw_memory_size - 0x11000 + 1;
548 for (cnt = 0; cnt < data_ram_cnt; cnt++) {
549 if (cnt % 8 == 0) {
550 qla_uprintf(&uiter, "\n%05x: ", cnt + 0x11000);
551 }
552 qla_uprintf(&uiter, "%04x ", fw->data_ram[cnt]);
553 }
554
555 qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump.");
556 }
557
558 /**
559 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
560 * @ha: HA context
561 * @hardware_locked: Called with the hardware_lock
562 */
563 void
564 qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
565 {
566 int rval;
567 uint32_t cnt, timer;
568 uint16_t risc_address;
569 uint16_t mb0, mb2;
570 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
571 uint16_t __iomem *dmp_reg;
572 unsigned long flags;
573 struct qla2100_fw_dump *fw;
574
575 risc_address = 0;
576 mb0 = mb2 = 0;
577 flags = 0;
578
579 if (!hardware_locked)
580 spin_lock_irqsave(&ha->hardware_lock, flags);
581
582 if (!ha->fw_dump) {
583 qla_printk(KERN_WARNING, ha,
584 "No buffer available for dump!!!\n");
585 goto qla2100_fw_dump_failed;
586 }
587
588 if (ha->fw_dumped) {
589 qla_printk(KERN_WARNING, ha,
590 "Firmware has been previously dumped (%p) -- ignoring "
591 "request...\n", ha->fw_dump);
592 goto qla2100_fw_dump_failed;
593 }
594 fw = ha->fw_dump;
595
596 rval = QLA_SUCCESS;
597 fw->hccr = RD_REG_WORD(&reg->hccr);
598
599 /* Pause RISC. */
600 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
601 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
602 rval == QLA_SUCCESS; cnt--) {
603 if (cnt)
604 udelay(100);
605 else
606 rval = QLA_FUNCTION_TIMEOUT;
607 }
608 if (rval == QLA_SUCCESS) {
609 dmp_reg = (uint16_t __iomem *)(reg + 0);
610 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
611 fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
612
613 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10);
614 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
615 if (cnt == 8) {
616 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xe0);
617 }
618 fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++);
619 }
620
621 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x20);
622 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
623 fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
624
625 WRT_REG_WORD(&reg->ctrl_status, 0x00);
626 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0);
627 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
628 fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
629
630 WRT_REG_WORD(&reg->pcr, 0x2000);
631 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
632 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
633 fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
634
635 WRT_REG_WORD(&reg->pcr, 0x2100);
636 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
637 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
638 fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
639
640 WRT_REG_WORD(&reg->pcr, 0x2200);
641 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
642 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
643 fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
644
645 WRT_REG_WORD(&reg->pcr, 0x2300);
646 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
647 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
648 fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
649
650 WRT_REG_WORD(&reg->pcr, 0x2400);
651 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
652 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
653 fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
654
655 WRT_REG_WORD(&reg->pcr, 0x2500);
656 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
657 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
658 fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
659
660 WRT_REG_WORD(&reg->pcr, 0x2600);
661 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
662 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
663 fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
664
665 WRT_REG_WORD(&reg->pcr, 0x2700);
666 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
667 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
668 fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
669
670 WRT_REG_WORD(&reg->ctrl_status, 0x10);
671 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
672 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
673 fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
674
675 WRT_REG_WORD(&reg->ctrl_status, 0x20);
676 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
677 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
678 fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
679
680 WRT_REG_WORD(&reg->ctrl_status, 0x30);
681 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
682 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
683 fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
684
685 /* Reset the ISP. */
686 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
687 }
688
689 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
690 rval == QLA_SUCCESS; cnt--) {
691 if (cnt)
692 udelay(100);
693 else
694 rval = QLA_FUNCTION_TIMEOUT;
695 }
696
697 /* Pause RISC. */
698 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
699 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
700
701 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
702 for (cnt = 30000;
703 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
704 rval == QLA_SUCCESS; cnt--) {
705 if (cnt)
706 udelay(100);
707 else
708 rval = QLA_FUNCTION_TIMEOUT;
709 }
710 if (rval == QLA_SUCCESS) {
711 /* Set memory configuration and timing. */
712 if (IS_QLA2100(ha))
713 WRT_REG_WORD(&reg->mctr, 0xf1);
714 else
715 WRT_REG_WORD(&reg->mctr, 0xf2);
716 RD_REG_WORD(&reg->mctr); /* PCI Posting. */
717
718 /* Release RISC. */
719 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
720 }
721 }
722
723 if (rval == QLA_SUCCESS) {
724 /* Get RISC SRAM. */
725 risc_address = 0x1000;
726 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
727 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
728 }
729 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
730 cnt++, risc_address++) {
731 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
732 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
733
734 for (timer = 6000000; timer != 0; timer--) {
735 /* Check for pending interrupts. */
736 if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
737 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
738 set_bit(MBX_INTERRUPT,
739 &ha->mbx_cmd_flags);
740
741 mb0 = RD_MAILBOX_REG(ha, reg, 0);
742 mb2 = RD_MAILBOX_REG(ha, reg, 2);
743
744 WRT_REG_WORD(&reg->semaphore, 0);
745 WRT_REG_WORD(&reg->hccr,
746 HCCR_CLR_RISC_INT);
747 RD_REG_WORD(&reg->hccr);
748 break;
749 }
750 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
751 RD_REG_WORD(&reg->hccr);
752 }
753 udelay(5);
754 }
755
756 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
757 rval = mb0 & MBS_MASK;
758 fw->risc_ram[cnt] = mb2;
759 } else {
760 rval = QLA_FUNCTION_FAILED;
761 }
762 }
763
764 if (rval != QLA_SUCCESS) {
765 qla_printk(KERN_WARNING, ha,
766 "Failed to dump firmware (%x)!!!\n", rval);
767 ha->fw_dumped = 0;
768
769 } else {
770 qla_printk(KERN_INFO, ha,
771 "Firmware dump saved to temp buffer (%ld/%p).\n",
772 ha->host_no, ha->fw_dump);
773 ha->fw_dumped = 1;
774 }
775
776 qla2100_fw_dump_failed:
777 if (!hardware_locked)
778 spin_unlock_irqrestore(&ha->hardware_lock, flags);
779 }
780
781 /**
782 * qla2100_ascii_fw_dump() - Converts a binary firmware dump to ASCII.
783 * @ha: HA context
784 */
785 void
786 qla2100_ascii_fw_dump(scsi_qla_host_t *ha)
787 {
788 uint32_t cnt;
789 char *uiter;
790 char fw_info[30];
791 struct qla2100_fw_dump *fw;
792
793 uiter = ha->fw_dump_buffer;
794 fw = ha->fw_dump;
795
796 qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
797 ha->isp_ops.fw_version_str(ha, fw_info));
798
799 qla_uprintf(&uiter, "\n[==>BEG]\n");
800
801 qla_uprintf(&uiter, "HCCR Register:\n%04x\n\n", fw->hccr);
802
803 qla_uprintf(&uiter, "PBIU Registers:");
804 for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
805 if (cnt % 8 == 0) {
806 qla_uprintf(&uiter, "\n");
807 }
808 qla_uprintf(&uiter, "%04x ", fw->pbiu_reg[cnt]);
809 }
810
811 qla_uprintf(&uiter, "\n\nMailbox Registers:");
812 for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
813 if (cnt % 8 == 0) {
814 qla_uprintf(&uiter, "\n");
815 }
816 qla_uprintf(&uiter, "%04x ", fw->mailbox_reg[cnt]);
817 }
818
819 qla_uprintf(&uiter, "\n\nDMA Registers:");
820 for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
821 if (cnt % 8 == 0) {
822 qla_uprintf(&uiter, "\n");
823 }
824 qla_uprintf(&uiter, "%04x ", fw->dma_reg[cnt]);
825 }
826
827 qla_uprintf(&uiter, "\n\nRISC Hardware Registers:");
828 for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
829 if (cnt % 8 == 0) {
830 qla_uprintf(&uiter, "\n");
831 }
832 qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]);
833 }
834
835 qla_uprintf(&uiter, "\n\nRISC GP0 Registers:");
836 for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) {
837 if (cnt % 8 == 0) {
838 qla_uprintf(&uiter, "\n");
839 }
840 qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]);
841 }
842
843 qla_uprintf(&uiter, "\n\nRISC GP1 Registers:");
844 for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) {
845 if (cnt % 8 == 0) {
846 qla_uprintf(&uiter, "\n");
847 }
848 qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]);
849 }
850
851 qla_uprintf(&uiter, "\n\nRISC GP2 Registers:");
852 for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) {
853 if (cnt % 8 == 0) {
854 qla_uprintf(&uiter, "\n");
855 }
856 qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]);
857 }
858
859 qla_uprintf(&uiter, "\n\nRISC GP3 Registers:");
860 for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) {
861 if (cnt % 8 == 0) {
862 qla_uprintf(&uiter, "\n");
863 }
864 qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]);
865 }
866
867 qla_uprintf(&uiter, "\n\nRISC GP4 Registers:");
868 for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) {
869 if (cnt % 8 == 0) {
870 qla_uprintf(&uiter, "\n");
871 }
872 qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]);
873 }
874
875 qla_uprintf(&uiter, "\n\nRISC GP5 Registers:");
876 for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) {
877 if (cnt % 8 == 0) {
878 qla_uprintf(&uiter, "\n");
879 }
880 qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]);
881 }
882
883 qla_uprintf(&uiter, "\n\nRISC GP6 Registers:");
884 for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
885 if (cnt % 8 == 0) {
886 qla_uprintf(&uiter, "\n");
887 }
888 qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]);
889 }
890
891 qla_uprintf(&uiter, "\n\nRISC GP7 Registers:");
892 for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
893 if (cnt % 8 == 0) {
894 qla_uprintf(&uiter, "\n");
895 }
896 qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]);
897 }
898
899 qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:");
900 for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
901 if (cnt % 8 == 0) {
902 qla_uprintf(&uiter, "\n");
903 }
904 qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]);
905 }
906
907 qla_uprintf(&uiter, "\n\nFPM B0 Registers:");
908 for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
909 if (cnt % 8 == 0) {
910 qla_uprintf(&uiter, "\n");
911 }
912 qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]);
913 }
914
915 qla_uprintf(&uiter, "\n\nFPM B1 Registers:");
916 for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
917 if (cnt % 8 == 0) {
918 qla_uprintf(&uiter, "\n");
919 }
920 qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]);
921 }
922
923 qla_uprintf(&uiter, "\n\nRISC SRAM:");
924 for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
925 if (cnt % 8 == 0) {
926 qla_uprintf(&uiter, "\n%04x: ", cnt + 0x1000);
927 }
928 qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]);
929 }
930
931 qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump.");
932
933 return;
934 }
935
936 static int
937 qla_uprintf(char **uiter, char *fmt, ...)
938 {
939 int iter, len;
940 char buf[128];
941 va_list args;
942
943 va_start(args, fmt);
944 len = vsprintf(buf, fmt, args);
945 va_end(args);
946
947 for (iter = 0; iter < len; iter++, *uiter += 1)
948 *uiter[0] = buf[iter];
949
950 return (len);
951 }
952
953
954 void
955 qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
956 {
957 int rval;
958 uint32_t cnt, timer;
959 uint32_t risc_address;
960 uint16_t mb[4], wd;
961
962 uint32_t stat;
963 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
964 uint32_t __iomem *dmp_reg;
965 uint32_t *iter_reg;
966 uint16_t __iomem *mbx_reg;
967 unsigned long flags;
968 struct qla24xx_fw_dump *fw;
969 uint32_t ext_mem_cnt;
970
971 risc_address = ext_mem_cnt = 0;
972 memset(mb, 0, sizeof(mb));
973 flags = 0;
974
975 if (!hardware_locked)
976 spin_lock_irqsave(&ha->hardware_lock, flags);
977
978 if (!ha->fw_dump) {
979 qla_printk(KERN_WARNING, ha,
980 "No buffer available for dump!!!\n");
981 goto qla24xx_fw_dump_failed;
982 }
983
984 if (ha->fw_dumped) {
985 qla_printk(KERN_WARNING, ha,
986 "Firmware has been previously dumped (%p) -- ignoring "
987 "request...\n", ha->fw_dump);
988 goto qla24xx_fw_dump_failed;
989 }
990 fw = ha->fw_dump;
991
992 rval = QLA_SUCCESS;
993 fw->host_status = RD_REG_DWORD(&reg->host_status);
994
995 /* Pause RISC. */
996 if ((RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0) {
997 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET |
998 HCCRX_CLR_HOST_INT);
999 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
1000 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
1001 for (cnt = 30000;
1002 (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0 &&
1003 rval == QLA_SUCCESS; cnt--) {
1004 if (cnt)
1005 udelay(100);
1006 else
1007 rval = QLA_FUNCTION_TIMEOUT;
1008 }
1009 }
1010
1011 if (rval == QLA_SUCCESS) {
1012 /* Host interface registers. */
1013 dmp_reg = (uint32_t __iomem *)(reg + 0);
1014 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1015 fw->host_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1016
1017 /* Disable interrupts. */
1018 WRT_REG_DWORD(&reg->ictrl, 0);
1019 RD_REG_DWORD(&reg->ictrl);
1020
1021 /* Shadow registers. */
1022 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1023 RD_REG_DWORD(&reg->iobase_addr);
1024 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1025 WRT_REG_DWORD(dmp_reg, 0xB0000000);
1026 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1027 fw->shadow_reg[0] = RD_REG_DWORD(dmp_reg);
1028
1029 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1030 WRT_REG_DWORD(dmp_reg, 0xB0100000);
1031 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1032 fw->shadow_reg[1] = RD_REG_DWORD(dmp_reg);
1033
1034 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1035 WRT_REG_DWORD(dmp_reg, 0xB0200000);
1036 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1037 fw->shadow_reg[2] = RD_REG_DWORD(dmp_reg);
1038
1039 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1040 WRT_REG_DWORD(dmp_reg, 0xB0300000);
1041 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1042 fw->shadow_reg[3] = RD_REG_DWORD(dmp_reg);
1043
1044 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1045 WRT_REG_DWORD(dmp_reg, 0xB0400000);
1046 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1047 fw->shadow_reg[4] = RD_REG_DWORD(dmp_reg);
1048
1049 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1050 WRT_REG_DWORD(dmp_reg, 0xB0500000);
1051 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1052 fw->shadow_reg[5] = RD_REG_DWORD(dmp_reg);
1053
1054 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1055 WRT_REG_DWORD(dmp_reg, 0xB0600000);
1056 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1057 fw->shadow_reg[6] = RD_REG_DWORD(dmp_reg);
1058
1059 /* Mailbox registers. */
1060 mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
1061 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1062 fw->mailbox_reg[cnt] = RD_REG_WORD(mbx_reg++);
1063
1064 /* Transfer sequence registers. */
1065 iter_reg = fw->xseq_gp_reg;
1066 WRT_REG_DWORD(&reg->iobase_addr, 0xBF00);
1067 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1068 for (cnt = 0; cnt < 16; cnt++)
1069 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1070
1071 WRT_REG_DWORD(&reg->iobase_addr, 0xBF10);
1072 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1073 for (cnt = 0; cnt < 16; cnt++)
1074 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1075
1076 WRT_REG_DWORD(&reg->iobase_addr, 0xBF20);
1077 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1078 for (cnt = 0; cnt < 16; cnt++)
1079 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1080
1081 WRT_REG_DWORD(&reg->iobase_addr, 0xBF30);
1082 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1083 for (cnt = 0; cnt < 16; cnt++)
1084 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1085
1086 WRT_REG_DWORD(&reg->iobase_addr, 0xBF40);
1087 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1088 for (cnt = 0; cnt < 16; cnt++)
1089 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1090
1091 WRT_REG_DWORD(&reg->iobase_addr, 0xBF50);
1092 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1093 for (cnt = 0; cnt < 16; cnt++)
1094 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1095
1096 WRT_REG_DWORD(&reg->iobase_addr, 0xBF60);
1097 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1098 for (cnt = 0; cnt < 16; cnt++)
1099 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1100
1101 WRT_REG_DWORD(&reg->iobase_addr, 0xBF70);
1102 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1103 for (cnt = 0; cnt < 16; cnt++)
1104 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1105
1106 WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0);
1107 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1108 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++)
1109 fw->xseq_0_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1110
1111 WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0);
1112 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1113 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++)
1114 fw->xseq_1_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1115
1116 /* Receive sequence registers. */
1117 iter_reg = fw->rseq_gp_reg;
1118 WRT_REG_DWORD(&reg->iobase_addr, 0xFF00);
1119 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1120 for (cnt = 0; cnt < 16; cnt++)
1121 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1122
1123 WRT_REG_DWORD(&reg->iobase_addr, 0xFF10);
1124 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1125 for (cnt = 0; cnt < 16; cnt++)
1126 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1127
1128 WRT_REG_DWORD(&reg->iobase_addr, 0xFF20);
1129 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1130 for (cnt = 0; cnt < 16; cnt++)
1131 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1132
1133 WRT_REG_DWORD(&reg->iobase_addr, 0xFF30);
1134 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1135 for (cnt = 0; cnt < 16; cnt++)
1136 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1137
1138 WRT_REG_DWORD(&reg->iobase_addr, 0xFF40);
1139 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1140 for (cnt = 0; cnt < 16; cnt++)
1141 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1142
1143 WRT_REG_DWORD(&reg->iobase_addr, 0xFF50);
1144 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1145 for (cnt = 0; cnt < 16; cnt++)
1146 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1147
1148 WRT_REG_DWORD(&reg->iobase_addr, 0xFF60);
1149 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1150 for (cnt = 0; cnt < 16; cnt++)
1151 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1152
1153 WRT_REG_DWORD(&reg->iobase_addr, 0xFF70);
1154 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1155 for (cnt = 0; cnt < 16; cnt++)
1156 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1157
1158 WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0);
1159 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1160 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++)
1161 fw->rseq_0_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1162
1163 WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0);
1164 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1165 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++)
1166 fw->rseq_1_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1167
1168 WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0);
1169 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1170 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++)
1171 fw->rseq_2_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1172
1173 /* Command DMA registers. */
1174 WRT_REG_DWORD(&reg->iobase_addr, 0x7100);
1175 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1176 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++)
1177 fw->cmd_dma_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1178
1179 /* Queues. */
1180 iter_reg = fw->req0_dma_reg;
1181 WRT_REG_DWORD(&reg->iobase_addr, 0x7200);
1182 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1183 for (cnt = 0; cnt < 8; cnt++)
1184 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1185
1186 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
1187 for (cnt = 0; cnt < 7; cnt++)
1188 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1189
1190 iter_reg = fw->resp0_dma_reg;
1191 WRT_REG_DWORD(&reg->iobase_addr, 0x7300);
1192 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1193 for (cnt = 0; cnt < 8; cnt++)
1194 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1195
1196 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
1197 for (cnt = 0; cnt < 7; cnt++)
1198 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1199
1200 iter_reg = fw->req1_dma_reg;
1201 WRT_REG_DWORD(&reg->iobase_addr, 0x7400);
1202 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1203 for (cnt = 0; cnt < 8; cnt++)
1204 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1205
1206 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
1207 for (cnt = 0; cnt < 7; cnt++)
1208 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1209
1210 /* Transmit DMA registers. */
1211 iter_reg = fw->xmt0_dma_reg;
1212 WRT_REG_DWORD(&reg->iobase_addr, 0x7600);
1213 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1214 for (cnt = 0; cnt < 16; cnt++)
1215 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1216
1217 WRT_REG_DWORD(&reg->iobase_addr, 0x7610);
1218 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1219 for (cnt = 0; cnt < 16; cnt++)
1220 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1221
1222 iter_reg = fw->xmt1_dma_reg;
1223 WRT_REG_DWORD(&reg->iobase_addr, 0x7620);
1224 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1225 for (cnt = 0; cnt < 16; cnt++)
1226 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1227
1228 WRT_REG_DWORD(&reg->iobase_addr, 0x7630);
1229 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1230 for (cnt = 0; cnt < 16; cnt++)
1231 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1232
1233 iter_reg = fw->xmt2_dma_reg;
1234 WRT_REG_DWORD(&reg->iobase_addr, 0x7640);
1235 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1236 for (cnt = 0; cnt < 16; cnt++)
1237 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1238
1239 WRT_REG_DWORD(&reg->iobase_addr, 0x7650);
1240 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1241 for (cnt = 0; cnt < 16; cnt++)
1242 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1243
1244 iter_reg = fw->xmt3_dma_reg;
1245 WRT_REG_DWORD(&reg->iobase_addr, 0x7660);
1246 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1247 for (cnt = 0; cnt < 16; cnt++)
1248 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1249
1250 WRT_REG_DWORD(&reg->iobase_addr, 0x7670);
1251 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1252 for (cnt = 0; cnt < 16; cnt++)
1253 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1254
1255 iter_reg = fw->xmt4_dma_reg;
1256 WRT_REG_DWORD(&reg->iobase_addr, 0x7680);
1257 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1258 for (cnt = 0; cnt < 16; cnt++)
1259 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1260
1261 WRT_REG_DWORD(&reg->iobase_addr, 0x7690);
1262 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1263 for (cnt = 0; cnt < 16; cnt++)
1264 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1265
1266 WRT_REG_DWORD(&reg->iobase_addr, 0x76A0);
1267 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1268 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++)
1269 fw->xmt_data_dma_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1270
1271 /* Receive DMA registers. */
1272 iter_reg = fw->rcvt0_data_dma_reg;
1273 WRT_REG_DWORD(&reg->iobase_addr, 0x7700);
1274 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1275 for (cnt = 0; cnt < 16; cnt++)
1276 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1277
1278 WRT_REG_DWORD(&reg->iobase_addr, 0x7710);
1279 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1280 for (cnt = 0; cnt < 16; cnt++)
1281 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1282
1283 iter_reg = fw->rcvt1_data_dma_reg;
1284 WRT_REG_DWORD(&reg->iobase_addr, 0x7720);
1285 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1286 for (cnt = 0; cnt < 16; cnt++)
1287 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1288
1289 WRT_REG_DWORD(&reg->iobase_addr, 0x7730);
1290 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1291 for (cnt = 0; cnt < 16; cnt++)
1292 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1293
1294 /* RISC registers. */
1295 iter_reg = fw->risc_gp_reg;
1296 WRT_REG_DWORD(&reg->iobase_addr, 0x0F00);
1297 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1298 for (cnt = 0; cnt < 16; cnt++)
1299 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1300
1301 WRT_REG_DWORD(&reg->iobase_addr, 0x0F10);
1302 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1303 for (cnt = 0; cnt < 16; cnt++)
1304 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1305
1306 WRT_REG_DWORD(&reg->iobase_addr, 0x0F20);
1307 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1308 for (cnt = 0; cnt < 16; cnt++)
1309 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1310
1311 WRT_REG_DWORD(&reg->iobase_addr, 0x0F30);
1312 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1313 for (cnt = 0; cnt < 16; cnt++)
1314 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1315
1316 WRT_REG_DWORD(&reg->iobase_addr, 0x0F40);
1317 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1318 for (cnt = 0; cnt < 16; cnt++)
1319 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1320
1321 WRT_REG_DWORD(&reg->iobase_addr, 0x0F50);
1322 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1323 for (cnt = 0; cnt < 16; cnt++)
1324 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1325
1326 WRT_REG_DWORD(&reg->iobase_addr, 0x0F60);
1327 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1328 for (cnt = 0; cnt < 16; cnt++)
1329 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1330
1331 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1332 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1333 for (cnt = 0; cnt < 16; cnt++)
1334 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1335
1336 /* Local memory controller registers. */
1337 iter_reg = fw->lmc_reg;
1338 WRT_REG_DWORD(&reg->iobase_addr, 0x3000);
1339 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1340 for (cnt = 0; cnt < 16; cnt++)
1341 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1342
1343 WRT_REG_DWORD(&reg->iobase_addr, 0x3010);
1344 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1345 for (cnt = 0; cnt < 16; cnt++)
1346 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1347
1348 WRT_REG_DWORD(&reg->iobase_addr, 0x3020);
1349 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1350 for (cnt = 0; cnt < 16; cnt++)
1351 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1352
1353 WRT_REG_DWORD(&reg->iobase_addr, 0x3030);
1354 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1355 for (cnt = 0; cnt < 16; cnt++)
1356 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1357
1358 WRT_REG_DWORD(&reg->iobase_addr, 0x3040);
1359 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1360 for (cnt = 0; cnt < 16; cnt++)
1361 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1362
1363 WRT_REG_DWORD(&reg->iobase_addr, 0x3050);
1364 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1365 for (cnt = 0; cnt < 16; cnt++)
1366 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1367
1368 WRT_REG_DWORD(&reg->iobase_addr, 0x3060);
1369 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1370 for (cnt = 0; cnt < 16; cnt++)
1371 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1372
1373 /* Fibre Protocol Module registers. */
1374 iter_reg = fw->fpm_hdw_reg;
1375 WRT_REG_DWORD(&reg->iobase_addr, 0x4000);
1376 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1377 for (cnt = 0; cnt < 16; cnt++)
1378 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1379
1380 WRT_REG_DWORD(&reg->iobase_addr, 0x4010);
1381 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1382 for (cnt = 0; cnt < 16; cnt++)
1383 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1384
1385 WRT_REG_DWORD(&reg->iobase_addr, 0x4020);
1386 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1387 for (cnt = 0; cnt < 16; cnt++)
1388 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1389
1390 WRT_REG_DWORD(&reg->iobase_addr, 0x4030);
1391 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1392 for (cnt = 0; cnt < 16; cnt++)
1393 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1394
1395 WRT_REG_DWORD(&reg->iobase_addr, 0x4040);
1396 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1397 for (cnt = 0; cnt < 16; cnt++)
1398 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1399
1400 WRT_REG_DWORD(&reg->iobase_addr, 0x4050);
1401 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1402 for (cnt = 0; cnt < 16; cnt++)
1403 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1404
1405 WRT_REG_DWORD(&reg->iobase_addr, 0x4060);
1406 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1407 for (cnt = 0; cnt < 16; cnt++)
1408 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1409
1410 WRT_REG_DWORD(&reg->iobase_addr, 0x4070);
1411 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1412 for (cnt = 0; cnt < 16; cnt++)
1413 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1414
1415 WRT_REG_DWORD(&reg->iobase_addr, 0x4080);
1416 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1417 for (cnt = 0; cnt < 16; cnt++)
1418 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1419
1420 WRT_REG_DWORD(&reg->iobase_addr, 0x4090);
1421 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1422 for (cnt = 0; cnt < 16; cnt++)
1423 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1424
1425 WRT_REG_DWORD(&reg->iobase_addr, 0x40A0);
1426 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1427 for (cnt = 0; cnt < 16; cnt++)
1428 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1429
1430 WRT_REG_DWORD(&reg->iobase_addr, 0x40B0);
1431 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1432 for (cnt = 0; cnt < 16; cnt++)
1433 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1434
1435 /* Frame Buffer registers. */
1436 iter_reg = fw->fb_hdw_reg;
1437 WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1438 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1439 for (cnt = 0; cnt < 16; cnt++)
1440 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1441
1442 WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1443 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1444 for (cnt = 0; cnt < 16; cnt++)
1445 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1446
1447 WRT_REG_DWORD(&reg->iobase_addr, 0x6020);
1448 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1449 for (cnt = 0; cnt < 16; cnt++)
1450 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1451
1452 WRT_REG_DWORD(&reg->iobase_addr, 0x6030);
1453 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1454 for (cnt = 0; cnt < 16; cnt++)
1455 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1456
1457 WRT_REG_DWORD(&reg->iobase_addr, 0x6040);
1458 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1459 for (cnt = 0; cnt < 16; cnt++)
1460 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1461
1462 WRT_REG_DWORD(&reg->iobase_addr, 0x6100);
1463 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1464 for (cnt = 0; cnt < 16; cnt++)
1465 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1466
1467 WRT_REG_DWORD(&reg->iobase_addr, 0x6130);
1468 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1469 for (cnt = 0; cnt < 16; cnt++)
1470 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1471
1472 WRT_REG_DWORD(&reg->iobase_addr, 0x6150);
1473 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1474 for (cnt = 0; cnt < 16; cnt++)
1475 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1476
1477 WRT_REG_DWORD(&reg->iobase_addr, 0x6170);
1478 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1479 for (cnt = 0; cnt < 16; cnt++)
1480 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1481
1482 WRT_REG_DWORD(&reg->iobase_addr, 0x6190);
1483 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1484 for (cnt = 0; cnt < 16; cnt++)
1485 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1486
1487 WRT_REG_DWORD(&reg->iobase_addr, 0x61B0);
1488 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1489 for (cnt = 0; cnt < 16; cnt++)
1490 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1491
1492 /* Reset RISC. */
1493 WRT_REG_DWORD(&reg->ctrl_status,
1494 CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1495 for (cnt = 0; cnt < 30000; cnt++) {
1496 if ((RD_REG_DWORD(&reg->ctrl_status) &
1497 CSRX_DMA_ACTIVE) == 0)
1498 break;
1499
1500 udelay(10);
1501 }
1502
1503 WRT_REG_DWORD(&reg->ctrl_status,
1504 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1505 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1506
1507 udelay(100);
1508 /* Wait for firmware to complete NVRAM accesses. */
1509 mb[0] = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1510 for (cnt = 10000 ; cnt && mb[0]; cnt--) {
1511 udelay(5);
1512 mb[0] = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1513 barrier();
1514 }
1515
1516 /* Wait for soft-reset to complete. */
1517 for (cnt = 0; cnt < 30000; cnt++) {
1518 if ((RD_REG_DWORD(&reg->ctrl_status) &
1519 CSRX_ISP_SOFT_RESET) == 0)
1520 break;
1521
1522 udelay(10);
1523 }
1524 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1525 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
1526 }
1527
1528 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
1529 rval == QLA_SUCCESS; cnt--) {
1530 if (cnt)
1531 udelay(100);
1532 else
1533 rval = QLA_FUNCTION_TIMEOUT;
1534 }
1535
1536 /* Memory. */
1537 if (rval == QLA_SUCCESS) {
1538 /* Code RAM. */
1539 risc_address = 0x20000;
1540 WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED);
1541 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
1542 }
1543 for (cnt = 0; cnt < sizeof(fw->code_ram) / 4 && rval == QLA_SUCCESS;
1544 cnt++, risc_address++) {
1545 WRT_REG_WORD(&reg->mailbox1, LSW(risc_address));
1546 WRT_REG_WORD(&reg->mailbox8, MSW(risc_address));
1547 RD_REG_WORD(&reg->mailbox8);
1548 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
1549
1550 for (timer = 6000000; timer; timer--) {
1551 /* Check for pending interrupts. */
1552 stat = RD_REG_DWORD(&reg->host_status);
1553 if (stat & HSRX_RISC_INT) {
1554 stat &= 0xff;
1555
1556 if (stat == 0x1 || stat == 0x2 ||
1557 stat == 0x10 || stat == 0x11) {
1558 set_bit(MBX_INTERRUPT,
1559 &ha->mbx_cmd_flags);
1560
1561 mb[0] = RD_REG_WORD(&reg->mailbox0);
1562 mb[2] = RD_REG_WORD(&reg->mailbox2);
1563 mb[3] = RD_REG_WORD(&reg->mailbox3);
1564
1565 WRT_REG_DWORD(&reg->hccr,
1566 HCCRX_CLR_RISC_INT);
1567 RD_REG_DWORD(&reg->hccr);
1568 break;
1569 }
1570
1571 /* Clear this intr; it wasn't a mailbox intr */
1572 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
1573 RD_REG_DWORD(&reg->hccr);
1574 }
1575 udelay(5);
1576 }
1577
1578 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
1579 rval = mb[0] & MBS_MASK;
1580 fw->code_ram[cnt] = (mb[3] << 16) | mb[2];
1581 } else {
1582 rval = QLA_FUNCTION_FAILED;
1583 }
1584 }
1585
1586 if (rval == QLA_SUCCESS) {
1587 /* External Memory. */
1588 risc_address = 0x100000;
1589 ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
1590 WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED);
1591 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
1592 }
1593 for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS;
1594 cnt++, risc_address++) {
1595 WRT_REG_WORD(&reg->mailbox1, LSW(risc_address));
1596 WRT_REG_WORD(&reg->mailbox8, MSW(risc_address));
1597 RD_REG_WORD(&reg->mailbox8);
1598 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
1599
1600 for (timer = 6000000; timer; timer--) {
1601 /* Check for pending interrupts. */
1602 stat = RD_REG_DWORD(&reg->host_status);
1603 if (stat & HSRX_RISC_INT) {
1604 stat &= 0xff;
1605
1606 if (stat == 0x1 || stat == 0x2 ||
1607 stat == 0x10 || stat == 0x11) {
1608 set_bit(MBX_INTERRUPT,
1609 &ha->mbx_cmd_flags);
1610
1611 mb[0] = RD_REG_WORD(&reg->mailbox0);
1612 mb[2] = RD_REG_WORD(&reg->mailbox2);
1613 mb[3] = RD_REG_WORD(&reg->mailbox3);
1614
1615 WRT_REG_DWORD(&reg->hccr,
1616 HCCRX_CLR_RISC_INT);
1617 RD_REG_DWORD(&reg->hccr);
1618 break;
1619 }
1620
1621 /* Clear this intr; it wasn't a mailbox intr */
1622 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
1623 RD_REG_DWORD(&reg->hccr);
1624 }
1625 udelay(5);
1626 }
1627
1628 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
1629 rval = mb[0] & MBS_MASK;
1630 fw->ext_mem[cnt] = (mb[3] << 16) | mb[2];
1631 } else {
1632 rval = QLA_FUNCTION_FAILED;
1633 }
1634 }
1635
1636 if (rval != QLA_SUCCESS) {
1637 qla_printk(KERN_WARNING, ha,
1638 "Failed to dump firmware (%x)!!!\n", rval);
1639 ha->fw_dumped = 0;
1640
1641 } else {
1642 qla_printk(KERN_INFO, ha,
1643 "Firmware dump saved to temp buffer (%ld/%p).\n",
1644 ha->host_no, ha->fw_dump);
1645 ha->fw_dumped = 1;
1646 }
1647
1648 qla24xx_fw_dump_failed:
1649 if (!hardware_locked)
1650 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1651 }
1652
1653 void
1654 qla24xx_ascii_fw_dump(scsi_qla_host_t *ha)
1655 {
1656 uint32_t cnt;
1657 char *uiter;
1658 struct qla24xx_fw_dump *fw;
1659 uint32_t ext_mem_cnt;
1660
1661 uiter = ha->fw_dump_buffer;
1662 fw = ha->fw_dump;
1663
1664 qla_uprintf(&uiter, "ISP FW Version %d.%02d.%02d Attributes %04x\n",
1665 ha->fw_major_version, ha->fw_minor_version,
1666 ha->fw_subminor_version, ha->fw_attributes);
1667
1668 qla_uprintf(&uiter, "\nR2H Status Register\n%04x\n", fw->host_status);
1669
1670 qla_uprintf(&uiter, "\nHost Interface Registers");
1671 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) {
1672 if (cnt % 8 == 0)
1673 qla_uprintf(&uiter, "\n");
1674
1675 qla_uprintf(&uiter, "%08x ", fw->host_reg[cnt]);
1676 }
1677
1678 qla_uprintf(&uiter, "\n\nShadow Registers");
1679 for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) {
1680 if (cnt % 8 == 0)
1681 qla_uprintf(&uiter, "\n");
1682
1683 qla_uprintf(&uiter, "%08x ", fw->shadow_reg[cnt]);
1684 }
1685
1686 qla_uprintf(&uiter, "\n\nMailbox Registers");
1687 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) {
1688 if (cnt % 8 == 0)
1689 qla_uprintf(&uiter, "\n");
1690
1691 qla_uprintf(&uiter, "%08x ", fw->mailbox_reg[cnt]);
1692 }
1693
1694 qla_uprintf(&uiter, "\n\nXSEQ GP Registers");
1695 for (cnt = 0; cnt < sizeof(fw->xseq_gp_reg) / 4; cnt++) {
1696 if (cnt % 8 == 0)
1697 qla_uprintf(&uiter, "\n");
1698
1699 qla_uprintf(&uiter, "%08x ", fw->xseq_gp_reg[cnt]);
1700 }
1701
1702 qla_uprintf(&uiter, "\n\nXSEQ-0 Registers");
1703 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) {
1704 if (cnt % 8 == 0)
1705 qla_uprintf(&uiter, "\n");
1706
1707 qla_uprintf(&uiter, "%08x ", fw->xseq_0_reg[cnt]);
1708 }
1709
1710 qla_uprintf(&uiter, "\n\nXSEQ-1 Registers");
1711 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) {
1712 if (cnt % 8 == 0)
1713 qla_uprintf(&uiter, "\n");
1714
1715 qla_uprintf(&uiter, "%08x ", fw->xseq_1_reg[cnt]);
1716 }
1717
1718 qla_uprintf(&uiter, "\n\nRSEQ GP Registers");
1719 for (cnt = 0; cnt < sizeof(fw->rseq_gp_reg) / 4; cnt++) {
1720 if (cnt % 8 == 0)
1721 qla_uprintf(&uiter, "\n");
1722
1723 qla_uprintf(&uiter, "%08x ", fw->rseq_gp_reg[cnt]);
1724 }
1725
1726 qla_uprintf(&uiter, "\n\nRSEQ-0 Registers");
1727 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) {
1728 if (cnt % 8 == 0)
1729 qla_uprintf(&uiter, "\n");
1730
1731 qla_uprintf(&uiter, "%08x ", fw->rseq_0_reg[cnt]);
1732 }
1733
1734 qla_uprintf(&uiter, "\n\nRSEQ-1 Registers");
1735 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) {
1736 if (cnt % 8 == 0)
1737 qla_uprintf(&uiter, "\n");
1738
1739 qla_uprintf(&uiter, "%08x ", fw->rseq_1_reg[cnt]);
1740 }
1741
1742 qla_uprintf(&uiter, "\n\nRSEQ-2 Registers");
1743 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) {
1744 if (cnt % 8 == 0)
1745 qla_uprintf(&uiter, "\n");
1746
1747 qla_uprintf(&uiter, "%08x ", fw->rseq_2_reg[cnt]);
1748 }
1749
1750 qla_uprintf(&uiter, "\n\nCommand DMA Registers");
1751 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) {
1752 if (cnt % 8 == 0)
1753 qla_uprintf(&uiter, "\n");
1754
1755 qla_uprintf(&uiter, "%08x ", fw->cmd_dma_reg[cnt]);
1756 }
1757
1758 qla_uprintf(&uiter, "\n\nRequest0 Queue DMA Channel Registers");
1759 for (cnt = 0; cnt < sizeof(fw->req0_dma_reg) / 4; cnt++) {
1760 if (cnt % 8 == 0)
1761 qla_uprintf(&uiter, "\n");
1762
1763 qla_uprintf(&uiter, "%08x ", fw->req0_dma_reg[cnt]);
1764 }
1765
1766 qla_uprintf(&uiter, "\n\nResponse0 Queue DMA Channel Registers");
1767 for (cnt = 0; cnt < sizeof(fw->resp0_dma_reg) / 4; cnt++) {
1768 if (cnt % 8 == 0)
1769 qla_uprintf(&uiter, "\n");
1770
1771 qla_uprintf(&uiter, "%08x ", fw->resp0_dma_reg[cnt]);
1772 }
1773
1774 qla_uprintf(&uiter, "\n\nRequest1 Queue DMA Channel Registers");
1775 for (cnt = 0; cnt < sizeof(fw->req1_dma_reg) / 4; cnt++) {
1776 if (cnt % 8 == 0)
1777 qla_uprintf(&uiter, "\n");
1778
1779 qla_uprintf(&uiter, "%08x ", fw->req1_dma_reg[cnt]);
1780 }
1781
1782 qla_uprintf(&uiter, "\n\nXMT0 Data DMA Registers");
1783 for (cnt = 0; cnt < sizeof(fw->xmt0_dma_reg) / 4; cnt++) {
1784 if (cnt % 8 == 0)
1785 qla_uprintf(&uiter, "\n");
1786
1787 qla_uprintf(&uiter, "%08x ", fw->xmt0_dma_reg[cnt]);
1788 }
1789
1790 qla_uprintf(&uiter, "\n\nXMT1 Data DMA Registers");
1791 for (cnt = 0; cnt < sizeof(fw->xmt1_dma_reg) / 4; cnt++) {
1792 if (cnt % 8 == 0)
1793 qla_uprintf(&uiter, "\n");
1794
1795 qla_uprintf(&uiter, "%08x ", fw->xmt1_dma_reg[cnt]);
1796 }
1797
1798 qla_uprintf(&uiter, "\n\nXMT2 Data DMA Registers");
1799 for (cnt = 0; cnt < sizeof(fw->xmt2_dma_reg) / 4; cnt++) {
1800 if (cnt % 8 == 0)
1801 qla_uprintf(&uiter, "\n");
1802
1803 qla_uprintf(&uiter, "%08x ", fw->xmt2_dma_reg[cnt]);
1804 }
1805
1806 qla_uprintf(&uiter, "\n\nXMT3 Data DMA Registers");
1807 for (cnt = 0; cnt < sizeof(fw->xmt3_dma_reg) / 4; cnt++) {
1808 if (cnt % 8 == 0)
1809 qla_uprintf(&uiter, "\n");
1810
1811 qla_uprintf(&uiter, "%08x ", fw->xmt3_dma_reg[cnt]);
1812 }
1813
1814 qla_uprintf(&uiter, "\n\nXMT4 Data DMA Registers");
1815 for (cnt = 0; cnt < sizeof(fw->xmt4_dma_reg) / 4; cnt++) {
1816 if (cnt % 8 == 0)
1817 qla_uprintf(&uiter, "\n");
1818
1819 qla_uprintf(&uiter, "%08x ", fw->xmt4_dma_reg[cnt]);
1820 }
1821
1822 qla_uprintf(&uiter, "\n\nXMT Data DMA Common Registers");
1823 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) {
1824 if (cnt % 8 == 0)
1825 qla_uprintf(&uiter, "\n");
1826
1827 qla_uprintf(&uiter, "%08x ", fw->xmt_data_dma_reg[cnt]);
1828 }
1829
1830 qla_uprintf(&uiter, "\n\nRCV Thread 0 Data DMA Registers");
1831 for (cnt = 0; cnt < sizeof(fw->rcvt0_data_dma_reg) / 4; cnt++) {
1832 if (cnt % 8 == 0)
1833 qla_uprintf(&uiter, "\n");
1834
1835 qla_uprintf(&uiter, "%08x ", fw->rcvt0_data_dma_reg[cnt]);
1836 }
1837
1838 qla_uprintf(&uiter, "\n\nRCV Thread 1 Data DMA Registers");
1839 for (cnt = 0; cnt < sizeof(fw->rcvt1_data_dma_reg) / 4; cnt++) {
1840 if (cnt % 8 == 0)
1841 qla_uprintf(&uiter, "\n");
1842
1843 qla_uprintf(&uiter, "%08x ", fw->rcvt1_data_dma_reg[cnt]);
1844 }
1845
1846 qla_uprintf(&uiter, "\n\nRISC GP Registers");
1847 for (cnt = 0; cnt < sizeof(fw->risc_gp_reg) / 4; cnt++) {
1848 if (cnt % 8 == 0)
1849 qla_uprintf(&uiter, "\n");
1850
1851 qla_uprintf(&uiter, "%08x ", fw->risc_gp_reg[cnt]);
1852 }
1853
1854 qla_uprintf(&uiter, "\n\nLMC Registers");
1855 for (cnt = 0; cnt < sizeof(fw->lmc_reg) / 4; cnt++) {
1856 if (cnt % 8 == 0)
1857 qla_uprintf(&uiter, "\n");
1858
1859 qla_uprintf(&uiter, "%08x ", fw->lmc_reg[cnt]);
1860 }
1861
1862 qla_uprintf(&uiter, "\n\nFPM Hardware Registers");
1863 for (cnt = 0; cnt < sizeof(fw->fpm_hdw_reg) / 4; cnt++) {
1864 if (cnt % 8 == 0)
1865 qla_uprintf(&uiter, "\n");
1866
1867 qla_uprintf(&uiter, "%08x ", fw->fpm_hdw_reg[cnt]);
1868 }
1869
1870 qla_uprintf(&uiter, "\n\nFB Hardware Registers");
1871 for (cnt = 0; cnt < sizeof(fw->fb_hdw_reg) / 4; cnt++) {
1872 if (cnt % 8 == 0)
1873 qla_uprintf(&uiter, "\n");
1874
1875 qla_uprintf(&uiter, "%08x ", fw->fb_hdw_reg[cnt]);
1876 }
1877
1878 qla_uprintf(&uiter, "\n\nCode RAM");
1879 for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
1880 if (cnt % 8 == 0) {
1881 qla_uprintf(&uiter, "\n%08x: ", cnt + 0x20000);
1882 }
1883 qla_uprintf(&uiter, "%08x ", fw->code_ram[cnt]);
1884 }
1885
1886 qla_uprintf(&uiter, "\n\nExternal Memory");
1887 ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
1888 for (cnt = 0; cnt < ext_mem_cnt; cnt++) {
1889 if (cnt % 8 == 0) {
1890 qla_uprintf(&uiter, "\n%08x: ", cnt + 0x100000);
1891 }
1892 qla_uprintf(&uiter, "%08x ", fw->ext_mem[cnt]);
1893 }
1894
1895 qla_uprintf(&uiter, "\n[<==END] ISP Debug Dump");
1896 }
1897
1898
1899 /****************************************************************************/
1900 /* Driver Debug Functions. */
1901 /****************************************************************************/
1902
1903 void
1904 qla2x00_dump_regs(scsi_qla_host_t *ha)
1905 {
1906 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1907
1908 printk("Mailbox registers:\n");
1909 printk("scsi(%ld): mbox 0 0x%04x \n",
1910 ha->host_no, RD_MAILBOX_REG(ha, reg, 0));
1911 printk("scsi(%ld): mbox 1 0x%04x \n",
1912 ha->host_no, RD_MAILBOX_REG(ha, reg, 1));
1913 printk("scsi(%ld): mbox 2 0x%04x \n",
1914 ha->host_no, RD_MAILBOX_REG(ha, reg, 2));
1915 printk("scsi(%ld): mbox 3 0x%04x \n",
1916 ha->host_no, RD_MAILBOX_REG(ha, reg, 3));
1917 printk("scsi(%ld): mbox 4 0x%04x \n",
1918 ha->host_no, RD_MAILBOX_REG(ha, reg, 4));
1919 printk("scsi(%ld): mbox 5 0x%04x \n",
1920 ha->host_no, RD_MAILBOX_REG(ha, reg, 5));
1921 }
1922
1923
1924 void
1925 qla2x00_dump_buffer(uint8_t * b, uint32_t size)
1926 {
1927 uint32_t cnt;
1928 uint8_t c;
1929
1930 printk(" 0 1 2 3 4 5 6 7 8 9 "
1931 "Ah Bh Ch Dh Eh Fh\n");
1932 printk("----------------------------------------"
1933 "----------------------\n");
1934
1935 for (cnt = 0; cnt < size;) {
1936 c = *b++;
1937 printk("%02x",(uint32_t) c);
1938 cnt++;
1939 if (!(cnt % 16))
1940 printk("\n");
1941 else
1942 printk(" ");
1943 }
1944 if (cnt % 16)
1945 printk("\n");
1946 }
1947
1948 /**************************************************************************
1949 * qla2x00_print_scsi_cmd
1950 * Dumps out info about the scsi cmd and srb.
1951 * Input
1952 * cmd : struct scsi_cmnd
1953 **************************************************************************/
1954 void
1955 qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd)
1956 {
1957 int i;
1958 struct scsi_qla_host *ha;
1959 srb_t *sp;
1960
1961 ha = (struct scsi_qla_host *)cmd->device->host->hostdata;
1962
1963 sp = (srb_t *) cmd->SCp.ptr;
1964 printk("SCSI Command @=0x%p, Handle=0x%p\n", cmd, cmd->host_scribble);
1965 printk(" chan=0x%02x, target=0x%02x, lun=0x%02x, cmd_len=0x%02x\n",
1966 cmd->device->channel, cmd->device->id, cmd->device->lun,
1967 cmd->cmd_len);
1968 printk(" CDB: ");
1969 for (i = 0; i < cmd->cmd_len; i++) {
1970 printk("0x%02x ", cmd->cmnd[i]);
1971 }
1972 printk("\n seg_cnt=%d, allowed=%d, retries=%d\n",
1973 cmd->use_sg, cmd->allowed, cmd->retries);
1974 printk(" request buffer=0x%p, request buffer len=0x%x\n",
1975 cmd->request_buffer, cmd->request_bufflen);
1976 printk(" tag=%d, transfersize=0x%x\n",
1977 cmd->tag, cmd->transfersize);
1978 printk(" serial_number=%lx, SP=%p\n", cmd->serial_number, sp);
1979 printk(" data direction=%d\n", cmd->sc_data_direction);
1980
1981 if (!sp)
1982 return;
1983
1984 printk(" sp flags=0x%x\n", sp->flags);
1985 }
1986
1987 void
1988 qla2x00_dump_pkt(void *pkt)
1989 {
1990 uint32_t i;
1991 uint8_t *data = (uint8_t *) pkt;
1992
1993 for (i = 0; i < 64; i++) {
1994 if (!(i % 4))
1995 printk("\n%02x: ", i);
1996
1997 printk("%02x ", data[i]);
1998 }
1999 printk("\n");
2000 }
2001
2002 #if defined(QL_DEBUG_ROUTINES)
2003 /*
2004 * qla2x00_formatted_dump_buffer
2005 * Prints string plus buffer.
2006 *
2007 * Input:
2008 * string = Null terminated string (no newline at end).
2009 * buffer = buffer address.
2010 * wd_size = word size 8, 16, 32 or 64 bits
2011 * count = number of words.
2012 */
2013 void
2014 qla2x00_formatted_dump_buffer(char *string, uint8_t * buffer,
2015 uint8_t wd_size, uint32_t count)
2016 {
2017 uint32_t cnt;
2018 uint16_t *buf16;
2019 uint32_t *buf32;
2020
2021 if (strcmp(string, "") != 0)
2022 printk("%s\n",string);
2023
2024 switch (wd_size) {
2025 case 8:
2026 printk(" 0 1 2 3 4 5 6 7 "
2027 "8 9 Ah Bh Ch Dh Eh Fh\n");
2028 printk("-----------------------------------------"
2029 "-------------------------------------\n");
2030
2031 for (cnt = 1; cnt <= count; cnt++, buffer++) {
2032 printk("%02x",*buffer);
2033 if (cnt % 16 == 0)
2034 printk("\n");
2035 else
2036 printk(" ");
2037 }
2038 if (cnt % 16 != 0)
2039 printk("\n");
2040 break;
2041 case 16:
2042 printk(" 0 2 4 6 8 Ah "
2043 " Ch Eh\n");
2044 printk("-----------------------------------------"
2045 "-------------\n");
2046
2047 buf16 = (uint16_t *) buffer;
2048 for (cnt = 1; cnt <= count; cnt++, buf16++) {
2049 printk("%4x",*buf16);
2050
2051 if (cnt % 8 == 0)
2052 printk("\n");
2053 else if (*buf16 < 10)
2054 printk(" ");
2055 else
2056 printk(" ");
2057 }
2058 if (cnt % 8 != 0)
2059 printk("\n");
2060 break;
2061 case 32:
2062 printk(" 0 4 8 Ch\n");
2063 printk("------------------------------------------\n");
2064
2065 buf32 = (uint32_t *) buffer;
2066 for (cnt = 1; cnt <= count; cnt++, buf32++) {
2067 printk("%8x", *buf32);
2068
2069 if (cnt % 4 == 0)
2070 printk("\n");
2071 else if (*buf32 < 10)
2072 printk(" ");
2073 else
2074 printk(" ");
2075 }
2076 if (cnt % 4 != 0)
2077 printk("\n");
2078 break;
2079 default:
2080 break;
2081 }
2082 }
2083 #endif
Linux kernel - Deliverables
This page took 0.080459 seconds and 6 git commands to generate.