drivers/scsi/qla2xxx/qla_dbg.h

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2005 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 /*
   8  * Driver debug definitions.
   9  */
  10 /* #define QL_DEBUG_LEVEL_1  */ /* Output register accesses to COM1 */
  11 /* #define QL_DEBUG_LEVEL_2  */ /* Output error msgs to COM1 */
  12 /* #define QL_DEBUG_LEVEL_3  */ /* Output function trace msgs to COM1 */
  13 /* #define QL_DEBUG_LEVEL_4  */ /* Output NVRAM trace msgs to COM1 */
  14 /* #define QL_DEBUG_LEVEL_5  */ /* Output ring trace msgs to COM1 */
  15 /* #define QL_DEBUG_LEVEL_6  */ /* Output WATCHDOG timer trace to COM1 */
  16 /* #define QL_DEBUG_LEVEL_7  */ /* Output RISC load trace msgs to COM1 */
  17 /* #define QL_DEBUG_LEVEL_8  */ /* Output ring saturation msgs to COM1 */
  18 /* #define QL_DEBUG_LEVEL_9  */ /* Output IOCTL trace msgs */
  19 /* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */
  20 /* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */
  21 /* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */
  22 /* #define QL_DEBUG_LEVEL_13 */ /* Output fdmi function trace msgs */
  23 /* #define QL_DEBUG_LEVEL_14 */ /* Output RSCN trace msgs */
  24 /*
  25  *  Local Macro Definitions.
  26  */
  27 #if defined(QL_DEBUG_LEVEL_1)  || defined(QL_DEBUG_LEVEL_2) || \
  28     defined(QL_DEBUG_LEVEL_3)  || defined(QL_DEBUG_LEVEL_4) || \
  29     defined(QL_DEBUG_LEVEL_5)  || defined(QL_DEBUG_LEVEL_6) || \
  30     defined(QL_DEBUG_LEVEL_7)  || defined(QL_DEBUG_LEVEL_8) || \
  31     defined(QL_DEBUG_LEVEL_9)  || defined(QL_DEBUG_LEVEL_10) || \
  32     defined(QL_DEBUG_LEVEL_11) || defined(QL_DEBUG_LEVEL_12) || \
  33     defined(QL_DEBUG_LEVEL_13) || defined(QL_DEBUG_LEVEL_14)
  34     #define QL_DEBUG_ROUTINES
  35 #endif
  36
  37 /*
  38 * Macros use for debugging the driver.
  39 */
  40
  41 #if  DEBUG_QLA2100
  42 #define DEBUG(x)        do {x;} while (0)
  43 #else
  44 #define DEBUG(x)        do {} while (0)
  45 #endif
  46
  47 #if defined(QL_DEBUG_LEVEL_1)
  48 #define DEBUG1(x)       do {x;} while (0)
  49 #else
  50 #define DEBUG1(x)       do {} while (0)
  51 #endif
  52
  53 #if defined(QL_DEBUG_LEVEL_2)
  54 #define DEBUG2(x)       do {x;} while (0)
  55 #define DEBUG2_3(x)     do {x;} while (0)
  56 #define DEBUG2_3_11(x)  do {x;} while (0)
  57 #define DEBUG2_9_10(x)    do {x;} while (0)
  58 #define DEBUG2_11(x)    do {x;} while (0)
  59 #define DEBUG2_13(x)    do {x;} while (0)
  60 #else
  61 #define DEBUG2(x)       do {} while (0)
  62 #endif
  63
  64 #if defined(QL_DEBUG_LEVEL_3)
  65 #define DEBUG3(x)       do {x;} while (0)
  66 #define DEBUG2_3(x)     do {x;} while (0)
  67 #define DEBUG2_3_11(x)  do {x;} while (0)
  68 #define DEBUG3_11(x)    do {x;} while (0)
  69 #else
  70 #define DEBUG3(x)       do {} while (0)
  71   #if !defined(QL_DEBUG_LEVEL_2)
  72   #define DEBUG2_3(x)   do {} while (0)
  73   #endif
  74 #endif
  75
  76 #if defined(QL_DEBUG_LEVEL_4)
  77 #define DEBUG4(x)       do {x;} while (0)
  78 #else
  79 #define DEBUG4(x)       do {} while (0)
  80 #endif
  81
  82 #if defined(QL_DEBUG_LEVEL_5)
  83 #define DEBUG5(x)          do {x;} while (0)
  84 #else
  85 #define DEBUG5(x)       do {} while (0)
  86 #endif
  87
  88 #if defined(QL_DEBUG_LEVEL_7)
  89 #define DEBUG7(x)          do {x;} while (0)
  90 #else
  91 #define DEBUG7(x)          do {} while (0)
  92 #endif
  93
  94 #if defined(QL_DEBUG_LEVEL_9)
  95 #define DEBUG9(x)       do {x;} while (0)
  96 #define DEBUG9_10(x)    do {x;} while (0)
  97 #define DEBUG2_9_10(x)  do {x;} while (0)
  98 #else
  99 #define DEBUG9(x)       do {} while (0)
 100 #endif
 101
 102 #if defined(QL_DEBUG_LEVEL_10)
 103 #define DEBUG10(x)      do {x;} while (0)
 104 #define DEBUG2_9_10(x)  do {x;} while (0)
 105 #define DEBUG9_10(x)    do {x;} while (0)
 106 #else
 107 #define DEBUG10(x)      do {} while (0)
 108   #if !defined(DEBUG2_9_10)
 109   #define DEBUG2_9_10(x)        do {} while (0)
 110   #endif
 111   #if !defined(DEBUG9_10)
 112   #define DEBUG9_10(x)  do {} while (0)
 113   #endif
 114 #endif
 115
 116 #if defined(QL_DEBUG_LEVEL_11)
 117 #define DEBUG11(x)      do{x;} while(0)
 118 #if !defined(DEBUG2_11)
 119 #define DEBUG2_11(x)    do{x;} while(0)
 120 #endif
 121 #if !defined(DEBUG2_3_11)
 122 #define DEBUG2_3_11(x)  do{x;} while(0)
 123 #endif
 124 #if !defined(DEBUG3_11)
 125 #define DEBUG3_11(x)    do{x;} while(0)
 126 #endif
 127 #else
 128 #define DEBUG11(x)      do{} while(0)
 129   #if !defined(QL_DEBUG_LEVEL_2)
 130   #define DEBUG2_11(x)  do{} while(0)
 131     #if !defined(QL_DEBUG_LEVEL_3)
 132     #define DEBUG2_3_11(x) do{} while(0)
 133     #endif
 134   #endif
 135   #if !defined(QL_DEBUG_LEVEL_3)
 136   #define DEBUG3_11(x)  do{} while(0)
 137   #endif
 138 #endif
 139
 140 #if defined(QL_DEBUG_LEVEL_12)
 141 #define DEBUG12(x)      do {x;} while (0)
 142 #else
 143 #define DEBUG12(x)      do {} while (0)
 144 #endif
 145
 146 #if defined(QL_DEBUG_LEVEL_13)
 147 #define DEBUG13(x)      do {x;} while (0)
 148 #if !defined(DEBUG2_13)
 149 #define DEBUG2_13(x)    do {x;} while(0)
 150 #endif
 151 #else
 152 #define DEBUG13(x)      do {} while (0)
 153 #if !defined(QL_DEBUG_LEVEL_2)
 154 #define DEBUG2_13(x)    do {} while(0)
 155 #endif
 156 #endif
 157
 158 #if defined(QL_DEBUG_LEVEL_14)
 159 #define DEBUG14(x)      do {x;} while (0)
 160 #else
 161 #define DEBUG14(x)      do {} while (0)
 162 #endif
 163
 164 /*
 165  * Firmware Dump structure definition
 166  */
 167
 168 struct qla2300_fw_dump {
 169         uint16_t hccr;
 170         uint16_t pbiu_reg[8];
 171         uint16_t risc_host_reg[8];
 172         uint16_t mailbox_reg[32];
 173         uint16_t resp_dma_reg[32];
 174         uint16_t dma_reg[48];
 175         uint16_t risc_hdw_reg[16];
 176         uint16_t risc_gp0_reg[16];
 177         uint16_t risc_gp1_reg[16];
 178         uint16_t risc_gp2_reg[16];
 179         uint16_t risc_gp3_reg[16];
 180         uint16_t risc_gp4_reg[16];
 181         uint16_t risc_gp5_reg[16];
 182         uint16_t risc_gp6_reg[16];
 183         uint16_t risc_gp7_reg[16];
 184         uint16_t frame_buf_hdw_reg[64];
 185         uint16_t fpm_b0_reg[64];
 186         uint16_t fpm_b1_reg[64];
 187         uint16_t risc_ram[0xf800];
 188         uint16_t stack_ram[0x1000];
 189         uint16_t data_ram[1];
 190 };
 191
 192 struct qla2100_fw_dump {
 193         uint16_t hccr;
 194         uint16_t pbiu_reg[8];
 195         uint16_t mailbox_reg[32];
 196         uint16_t dma_reg[48];
 197         uint16_t risc_hdw_reg[16];
 198         uint16_t risc_gp0_reg[16];
 199         uint16_t risc_gp1_reg[16];
 200         uint16_t risc_gp2_reg[16];
 201         uint16_t risc_gp3_reg[16];
 202         uint16_t risc_gp4_reg[16];
 203         uint16_t risc_gp5_reg[16];
 204         uint16_t risc_gp6_reg[16];
 205         uint16_t risc_gp7_reg[16];
 206         uint16_t frame_buf_hdw_reg[16];
 207         uint16_t fpm_b0_reg[64];
 208         uint16_t fpm_b1_reg[64];
 209         uint16_t risc_ram[0xf000];
 210 };
 211
 212 struct qla24xx_fw_dump {
 213         uint32_t host_status;
 214         uint32_t host_reg[32];
 215         uint32_t shadow_reg[7];
 216         uint16_t mailbox_reg[32];
 217         uint32_t xseq_gp_reg[128];
 218         uint32_t xseq_0_reg[16];
 219         uint32_t xseq_1_reg[16];
 220         uint32_t rseq_gp_reg[128];
 221         uint32_t rseq_0_reg[16];
 222         uint32_t rseq_1_reg[16];
 223         uint32_t rseq_2_reg[16];
 224         uint32_t cmd_dma_reg[16];
 225         uint32_t req0_dma_reg[15];
 226         uint32_t resp0_dma_reg[15];
 227         uint32_t req1_dma_reg[15];
 228         uint32_t xmt0_dma_reg[32];
 229         uint32_t xmt1_dma_reg[32];
 230         uint32_t xmt2_dma_reg[32];
 231         uint32_t xmt3_dma_reg[32];
 232         uint32_t xmt4_dma_reg[32];
 233         uint32_t xmt_data_dma_reg[16];
 234         uint32_t rcvt0_data_dma_reg[32];
 235         uint32_t rcvt1_data_dma_reg[32];
 236         uint32_t risc_gp_reg[128];
 237         uint32_t lmc_reg[112];
 238         uint32_t fpm_hdw_reg[192];
 239         uint32_t fb_hdw_reg[176];
 240         uint32_t code_ram[0x2000];
 241         uint32_t ext_mem[1];
 242 };
 243
 244 #define EFT_NUM_BUFFERS         4
 245 #define EFT_BYTES_PER_BUFFER    0x4000
 246 #define EFT_SIZE                ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
 247
 248 struct qla2xxx_fw_dump {
 249         uint8_t signature[4];
 250         uint32_t version;
 251
 252         uint32_t fw_major_version;
 253         uint32_t fw_minor_version;
 254         uint32_t fw_subminor_version;
 255         uint32_t fw_attributes;
 256
 257         uint32_t vendor;
 258         uint32_t device;
 259         uint32_t subsystem_vendor;
 260         uint32_t subsystem_device;
 261
 262         uint32_t fixed_size;
 263         uint32_t mem_size;
 264         uint32_t req_q_size;
 265         uint32_t rsp_q_size;
 266
 267         uint32_t eft_size;
 268         uint32_t eft_addr_l;
 269         uint32_t eft_addr_h;
 270
 271         uint32_t header_size;
 272
 273         union {
 274                 struct qla2100_fw_dump isp21;
 275                 struct qla2300_fw_dump isp23;
 276                 struct qla24xx_fw_dump isp24;
 277         } isp;
 278 };