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[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_def.h
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_transport_fc.h>
34
35 #define QLA2XXX_DRIVER_NAME "qla2xxx"
36
37 /*
38 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
39 * but that's fine as we don't look at the last 24 ones for
40 * ISP2100 HBAs.
41 */
42 #define MAILBOX_REGISTER_COUNT_2100 8
43 #define MAILBOX_REGISTER_COUNT 32
44
45 #define QLA2200A_RISC_ROM_VER 4
46 #define FPM_2300 6
47 #define FPM_2310 7
48
49 #include "qla_settings.h"
50
51 /*
52 * Data bit definitions
53 */
54 #define BIT_0 0x1
55 #define BIT_1 0x2
56 #define BIT_2 0x4
57 #define BIT_3 0x8
58 #define BIT_4 0x10
59 #define BIT_5 0x20
60 #define BIT_6 0x40
61 #define BIT_7 0x80
62 #define BIT_8 0x100
63 #define BIT_9 0x200
64 #define BIT_10 0x400
65 #define BIT_11 0x800
66 #define BIT_12 0x1000
67 #define BIT_13 0x2000
68 #define BIT_14 0x4000
69 #define BIT_15 0x8000
70 #define BIT_16 0x10000
71 #define BIT_17 0x20000
72 #define BIT_18 0x40000
73 #define BIT_19 0x80000
74 #define BIT_20 0x100000
75 #define BIT_21 0x200000
76 #define BIT_22 0x400000
77 #define BIT_23 0x800000
78 #define BIT_24 0x1000000
79 #define BIT_25 0x2000000
80 #define BIT_26 0x4000000
81 #define BIT_27 0x8000000
82 #define BIT_28 0x10000000
83 #define BIT_29 0x20000000
84 #define BIT_30 0x40000000
85 #define BIT_31 0x80000000
86
87 #define LSB(x) ((uint8_t)(x))
88 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
89
90 #define LSW(x) ((uint16_t)(x))
91 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
92
93 #define LSD(x) ((uint32_t)((uint64_t)(x)))
94 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
95
96
97 /*
98 * I/O register
99 */
100
101 #define RD_REG_BYTE(addr) readb(addr)
102 #define RD_REG_WORD(addr) readw(addr)
103 #define RD_REG_DWORD(addr) readl(addr)
104 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
105 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
106 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
107 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
108 #define WRT_REG_WORD(addr, data) writew(data,addr)
109 #define WRT_REG_DWORD(addr, data) writel(data,addr)
110
111 /*
112 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
113 * 133Mhz slot.
114 */
115 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
116 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
117
118 /*
119 * Fibre Channel device definitions.
120 */
121 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
122 #define MAX_FIBRE_DEVICES 512
123 #define MAX_FIBRE_LUNS 0xFFFF
124 #define MAX_RSCN_COUNT 32
125 #define MAX_HOST_COUNT 16
126
127 /*
128 * Host adapter default definitions.
129 */
130 #define MAX_BUSES 1 /* We only have one bus today */
131 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
132 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
133 #define MIN_LUNS 8
134 #define MAX_LUNS MAX_FIBRE_LUNS
135 #define MAX_CMDS_PER_LUN 255
136
137 /*
138 * Fibre Channel device definitions.
139 */
140 #define SNS_LAST_LOOP_ID_2100 0xfe
141 #define SNS_LAST_LOOP_ID_2300 0x7ff
142
143 #define LAST_LOCAL_LOOP_ID 0x7d
144 #define SNS_FL_PORT 0x7e
145 #define FABRIC_CONTROLLER 0x7f
146 #define SIMPLE_NAME_SERVER 0x80
147 #define SNS_FIRST_LOOP_ID 0x81
148 #define MANAGEMENT_SERVER 0xfe
149 #define BROADCAST 0xff
150
151 /*
152 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
153 * valid range of an N-PORT id is 0 through 0x7ef.
154 */
155 #define NPH_LAST_HANDLE 0x7ef
156 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
157 #define NPH_SNS 0x7fc /* FFFFFC */
158 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
159 #define NPH_F_PORT 0x7fe /* FFFFFE */
160 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
161
162 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
163 #include "qla_fw.h"
164
165 /*
166 * Timeout timer counts in seconds
167 */
168 #define PORT_RETRY_TIME 1
169 #define LOOP_DOWN_TIMEOUT 60
170 #define LOOP_DOWN_TIME 255 /* 240 */
171 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
172
173 /* Maximum outstanding commands in ISP queues (1-65535) */
174 #define MAX_OUTSTANDING_COMMANDS 1024
175
176 /* ISP request and response entry counts (37-65535) */
177 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
178 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
179 #define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
180 #define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
181 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
182 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
183
184 struct req_que;
185
186 /*
187 * SCSI Request Block
188 */
189 typedef struct srb {
190 struct req_que *que;
191 struct fc_port *fcport;
192
193 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
194
195 uint16_t flags;
196
197 uint32_t request_sense_length;
198 uint8_t *request_sense_ptr;
199 } srb_t;
200
201 /*
202 * SRB flag definitions
203 */
204 #define SRB_TIMEOUT BIT_0 /* Command timed out */
205 #define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
206 #define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
207 #define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
208
209 #define SRB_ABORTED BIT_4 /* Command aborted command already */
210 #define SRB_RETRY BIT_5 /* Command needs retrying */
211 #define SRB_GOT_SENSE BIT_6 /* Command has sense data */
212 #define SRB_FAILOVER BIT_7 /* Command in failover state */
213
214 #define SRB_BUSY BIT_8 /* Command is in busy retry state */
215 #define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
216 #define SRB_IOCTL BIT_10 /* IOCTL command. */
217 #define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
218
219 /*
220 * ISP I/O Register Set structure definitions.
221 */
222 struct device_reg_2xxx {
223 uint16_t flash_address; /* Flash BIOS address */
224 uint16_t flash_data; /* Flash BIOS data */
225 uint16_t unused_1[1]; /* Gap */
226 uint16_t ctrl_status; /* Control/Status */
227 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
228 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
229 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
230
231 uint16_t ictrl; /* Interrupt control */
232 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
233 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
234
235 uint16_t istatus; /* Interrupt status */
236 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
237
238 uint16_t semaphore; /* Semaphore */
239 uint16_t nvram; /* NVRAM register. */
240 #define NVR_DESELECT 0
241 #define NVR_BUSY BIT_15
242 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
243 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
244 #define NVR_DATA_IN BIT_3
245 #define NVR_DATA_OUT BIT_2
246 #define NVR_SELECT BIT_1
247 #define NVR_CLOCK BIT_0
248
249 #define NVR_WAIT_CNT 20000
250
251 union {
252 struct {
253 uint16_t mailbox0;
254 uint16_t mailbox1;
255 uint16_t mailbox2;
256 uint16_t mailbox3;
257 uint16_t mailbox4;
258 uint16_t mailbox5;
259 uint16_t mailbox6;
260 uint16_t mailbox7;
261 uint16_t unused_2[59]; /* Gap */
262 } __attribute__((packed)) isp2100;
263 struct {
264 /* Request Queue */
265 uint16_t req_q_in; /* In-Pointer */
266 uint16_t req_q_out; /* Out-Pointer */
267 /* Response Queue */
268 uint16_t rsp_q_in; /* In-Pointer */
269 uint16_t rsp_q_out; /* Out-Pointer */
270
271 /* RISC to Host Status */
272 uint32_t host_status;
273 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
274 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
275
276 /* Host to Host Semaphore */
277 uint16_t host_semaphore;
278 uint16_t unused_3[17]; /* Gap */
279 uint16_t mailbox0;
280 uint16_t mailbox1;
281 uint16_t mailbox2;
282 uint16_t mailbox3;
283 uint16_t mailbox4;
284 uint16_t mailbox5;
285 uint16_t mailbox6;
286 uint16_t mailbox7;
287 uint16_t mailbox8;
288 uint16_t mailbox9;
289 uint16_t mailbox10;
290 uint16_t mailbox11;
291 uint16_t mailbox12;
292 uint16_t mailbox13;
293 uint16_t mailbox14;
294 uint16_t mailbox15;
295 uint16_t mailbox16;
296 uint16_t mailbox17;
297 uint16_t mailbox18;
298 uint16_t mailbox19;
299 uint16_t mailbox20;
300 uint16_t mailbox21;
301 uint16_t mailbox22;
302 uint16_t mailbox23;
303 uint16_t mailbox24;
304 uint16_t mailbox25;
305 uint16_t mailbox26;
306 uint16_t mailbox27;
307 uint16_t mailbox28;
308 uint16_t mailbox29;
309 uint16_t mailbox30;
310 uint16_t mailbox31;
311 uint16_t fb_cmd;
312 uint16_t unused_4[10]; /* Gap */
313 } __attribute__((packed)) isp2300;
314 } u;
315
316 uint16_t fpm_diag_config;
317 uint16_t unused_5[0x4]; /* Gap */
318 uint16_t risc_hw;
319 uint16_t unused_5_1; /* Gap */
320 uint16_t pcr; /* Processor Control Register. */
321 uint16_t unused_6[0x5]; /* Gap */
322 uint16_t mctr; /* Memory Configuration and Timing. */
323 uint16_t unused_7[0x3]; /* Gap */
324 uint16_t fb_cmd_2100; /* Unused on 23XX */
325 uint16_t unused_8[0x3]; /* Gap */
326 uint16_t hccr; /* Host command & control register. */
327 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
328 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
329 /* HCCR commands */
330 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
331 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
332 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
333 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
334 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
335 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
336 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
337 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
338
339 uint16_t unused_9[5]; /* Gap */
340 uint16_t gpiod; /* GPIO Data register. */
341 uint16_t gpioe; /* GPIO Enable register. */
342 #define GPIO_LED_MASK 0x00C0
343 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
344 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
345 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
346 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
347 #define GPIO_LED_ALL_OFF 0x0000
348 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
349 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
350
351 union {
352 struct {
353 uint16_t unused_10[8]; /* Gap */
354 uint16_t mailbox8;
355 uint16_t mailbox9;
356 uint16_t mailbox10;
357 uint16_t mailbox11;
358 uint16_t mailbox12;
359 uint16_t mailbox13;
360 uint16_t mailbox14;
361 uint16_t mailbox15;
362 uint16_t mailbox16;
363 uint16_t mailbox17;
364 uint16_t mailbox18;
365 uint16_t mailbox19;
366 uint16_t mailbox20;
367 uint16_t mailbox21;
368 uint16_t mailbox22;
369 uint16_t mailbox23; /* Also probe reg. */
370 } __attribute__((packed)) isp2200;
371 } u_end;
372 };
373
374 struct device_reg_25xxmq {
375 volatile uint32_t req_q_in;
376 volatile uint32_t req_q_out;
377 volatile uint32_t rsp_q_in;
378 volatile uint32_t rsp_q_out;
379 };
380
381 typedef union {
382 struct device_reg_2xxx isp;
383 struct device_reg_24xx isp24;
384 struct device_reg_25xxmq isp25mq;
385 } device_reg_t;
386
387 #define ISP_REQ_Q_IN(ha, reg) \
388 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
389 &(reg)->u.isp2100.mailbox4 : \
390 &(reg)->u.isp2300.req_q_in)
391 #define ISP_REQ_Q_OUT(ha, reg) \
392 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
393 &(reg)->u.isp2100.mailbox4 : \
394 &(reg)->u.isp2300.req_q_out)
395 #define ISP_RSP_Q_IN(ha, reg) \
396 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
397 &(reg)->u.isp2100.mailbox5 : \
398 &(reg)->u.isp2300.rsp_q_in)
399 #define ISP_RSP_Q_OUT(ha, reg) \
400 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
401 &(reg)->u.isp2100.mailbox5 : \
402 &(reg)->u.isp2300.rsp_q_out)
403
404 #define MAILBOX_REG(ha, reg, num) \
405 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
406 (num < 8 ? \
407 &(reg)->u.isp2100.mailbox0 + (num) : \
408 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
409 &(reg)->u.isp2300.mailbox0 + (num))
410 #define RD_MAILBOX_REG(ha, reg, num) \
411 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
412 #define WRT_MAILBOX_REG(ha, reg, num, data) \
413 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
414
415 #define FB_CMD_REG(ha, reg) \
416 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
417 &(reg)->fb_cmd_2100 : \
418 &(reg)->u.isp2300.fb_cmd)
419 #define RD_FB_CMD_REG(ha, reg) \
420 RD_REG_WORD(FB_CMD_REG(ha, reg))
421 #define WRT_FB_CMD_REG(ha, reg, data) \
422 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
423
424 typedef struct {
425 uint32_t out_mb; /* outbound from driver */
426 uint32_t in_mb; /* Incoming from RISC */
427 uint16_t mb[MAILBOX_REGISTER_COUNT];
428 long buf_size;
429 void *bufp;
430 uint32_t tov;
431 uint8_t flags;
432 #define MBX_DMA_IN BIT_0
433 #define MBX_DMA_OUT BIT_1
434 #define IOCTL_CMD BIT_2
435 } mbx_cmd_t;
436
437 #define MBX_TOV_SECONDS 30
438
439 /*
440 * ISP product identification definitions in mailboxes after reset.
441 */
442 #define PROD_ID_1 0x4953
443 #define PROD_ID_2 0x0000
444 #define PROD_ID_2a 0x5020
445 #define PROD_ID_3 0x2020
446
447 /*
448 * ISP mailbox Self-Test status codes
449 */
450 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
451 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
452 #define MBS_BUSY 4 /* Busy. */
453
454 /*
455 * ISP mailbox command complete status codes
456 */
457 #define MBS_COMMAND_COMPLETE 0x4000
458 #define MBS_INVALID_COMMAND 0x4001
459 #define MBS_HOST_INTERFACE_ERROR 0x4002
460 #define MBS_TEST_FAILED 0x4003
461 #define MBS_COMMAND_ERROR 0x4005
462 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
463 #define MBS_PORT_ID_USED 0x4007
464 #define MBS_LOOP_ID_USED 0x4008
465 #define MBS_ALL_IDS_IN_USE 0x4009
466 #define MBS_NOT_LOGGED_IN 0x400A
467 #define MBS_LINK_DOWN_ERROR 0x400B
468 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
469
470 /*
471 * ISP mailbox asynchronous event status codes
472 */
473 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
474 #define MBA_RESET 0x8001 /* Reset Detected. */
475 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
476 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
477 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
478 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
479 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
480 /* occurred. */
481 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
482 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
483 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
484 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
485 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
486 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
487 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
488 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
489 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
490 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
491 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
492 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
493 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
494 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
495 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
496 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
497 /* used. */
498 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
499 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
500 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
501 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
502 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
503 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
504 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
505 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
506 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
507 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
508 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
509 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
510 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
511 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
512
513 /*
514 * Firmware options 1, 2, 3.
515 */
516 #define FO1_AE_ON_LIPF8 BIT_0
517 #define FO1_AE_ALL_LIP_RESET BIT_1
518 #define FO1_CTIO_RETRY BIT_3
519 #define FO1_DISABLE_LIP_F7_SW BIT_4
520 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
521 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
522 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
523 #define FO1_SET_EMPHASIS_SWING BIT_8
524 #define FO1_AE_AUTO_BYPASS BIT_9
525 #define FO1_ENABLE_PURE_IOCB BIT_10
526 #define FO1_AE_PLOGI_RJT BIT_11
527 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
528 #define FO1_AE_QUEUE_FULL BIT_13
529
530 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
531 #define FO2_REV_LOOPBACK BIT_1
532
533 #define FO3_ENABLE_EMERG_IOCB BIT_0
534 #define FO3_AE_RND_ERROR BIT_1
535
536 /* 24XX additional firmware options */
537 #define ADD_FO_COUNT 3
538 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
539 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
540
541 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
542
543 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
544
545 /*
546 * ISP mailbox commands
547 */
548 #define MBC_LOAD_RAM 1 /* Load RAM. */
549 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
550 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
551 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
552 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
553 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
554 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
555 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
556 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
557 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
558 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
559 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
560 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
561 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
562 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
563 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
564 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
565 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
566 #define MBC_RESET 0x18 /* Reset. */
567 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
568 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
569 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
570 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
571 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
572 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
573 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
574 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
575 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
576 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
577 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
578 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
579 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
580 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
581 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
582 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
583 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
584 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
585 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
586 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
587 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
588 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
589 /* Initialization Procedure */
590 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
591 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
592 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
593 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
594 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
595 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
596 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
597 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
598 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
599 #define MBC_LIP_RESET 0x6c /* LIP reset. */
600 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
601 /* commandd. */
602 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
603 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
604 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
605 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
606 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
607 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
608 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
609 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
610 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
611 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
612 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
613
614 /*
615 * ISP24xx mailbox commands
616 */
617 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
618 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
619 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
620 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
621 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
622 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
623 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
624 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
625 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
626 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
627 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
628 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
629 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
630 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
631 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
632
633 /* Firmware return data sizes */
634 #define FCAL_MAP_SIZE 128
635
636 /* Mailbox bit definitions for out_mb and in_mb */
637 #define MBX_31 BIT_31
638 #define MBX_30 BIT_30
639 #define MBX_29 BIT_29
640 #define MBX_28 BIT_28
641 #define MBX_27 BIT_27
642 #define MBX_26 BIT_26
643 #define MBX_25 BIT_25
644 #define MBX_24 BIT_24
645 #define MBX_23 BIT_23
646 #define MBX_22 BIT_22
647 #define MBX_21 BIT_21
648 #define MBX_20 BIT_20
649 #define MBX_19 BIT_19
650 #define MBX_18 BIT_18
651 #define MBX_17 BIT_17
652 #define MBX_16 BIT_16
653 #define MBX_15 BIT_15
654 #define MBX_14 BIT_14
655 #define MBX_13 BIT_13
656 #define MBX_12 BIT_12
657 #define MBX_11 BIT_11
658 #define MBX_10 BIT_10
659 #define MBX_9 BIT_9
660 #define MBX_8 BIT_8
661 #define MBX_7 BIT_7
662 #define MBX_6 BIT_6
663 #define MBX_5 BIT_5
664 #define MBX_4 BIT_4
665 #define MBX_3 BIT_3
666 #define MBX_2 BIT_2
667 #define MBX_1 BIT_1
668 #define MBX_0 BIT_0
669
670 /*
671 * Firmware state codes from get firmware state mailbox command
672 */
673 #define FSTATE_CONFIG_WAIT 0
674 #define FSTATE_WAIT_AL_PA 1
675 #define FSTATE_WAIT_LOGIN 2
676 #define FSTATE_READY 3
677 #define FSTATE_LOSS_OF_SYNC 4
678 #define FSTATE_ERROR 5
679 #define FSTATE_REINIT 6
680 #define FSTATE_NON_PART 7
681
682 #define FSTATE_CONFIG_CORRECT 0
683 #define FSTATE_P2P_RCV_LIP 1
684 #define FSTATE_P2P_CHOOSE_LOOP 2
685 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
686 #define FSTATE_FATAL_ERROR 4
687 #define FSTATE_LOOP_BACK_CONN 5
688
689 /*
690 * Port Database structure definition
691 * Little endian except where noted.
692 */
693 #define PORT_DATABASE_SIZE 128 /* bytes */
694 typedef struct {
695 uint8_t options;
696 uint8_t control;
697 uint8_t master_state;
698 uint8_t slave_state;
699 uint8_t reserved[2];
700 uint8_t hard_address;
701 uint8_t reserved_1;
702 uint8_t port_id[4];
703 uint8_t node_name[WWN_SIZE];
704 uint8_t port_name[WWN_SIZE];
705 uint16_t execution_throttle;
706 uint16_t execution_count;
707 uint8_t reset_count;
708 uint8_t reserved_2;
709 uint16_t resource_allocation;
710 uint16_t current_allocation;
711 uint16_t queue_head;
712 uint16_t queue_tail;
713 uint16_t transmit_execution_list_next;
714 uint16_t transmit_execution_list_previous;
715 uint16_t common_features;
716 uint16_t total_concurrent_sequences;
717 uint16_t RO_by_information_category;
718 uint8_t recipient;
719 uint8_t initiator;
720 uint16_t receive_data_size;
721 uint16_t concurrent_sequences;
722 uint16_t open_sequences_per_exchange;
723 uint16_t lun_abort_flags;
724 uint16_t lun_stop_flags;
725 uint16_t stop_queue_head;
726 uint16_t stop_queue_tail;
727 uint16_t port_retry_timer;
728 uint16_t next_sequence_id;
729 uint16_t frame_count;
730 uint16_t PRLI_payload_length;
731 uint8_t prli_svc_param_word_0[2]; /* Big endian */
732 /* Bits 15-0 of word 0 */
733 uint8_t prli_svc_param_word_3[2]; /* Big endian */
734 /* Bits 15-0 of word 3 */
735 uint16_t loop_id;
736 uint16_t extended_lun_info_list_pointer;
737 uint16_t extended_lun_stop_list_pointer;
738 } port_database_t;
739
740 /*
741 * Port database slave/master states
742 */
743 #define PD_STATE_DISCOVERY 0
744 #define PD_STATE_WAIT_DISCOVERY_ACK 1
745 #define PD_STATE_PORT_LOGIN 2
746 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
747 #define PD_STATE_PROCESS_LOGIN 4
748 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
749 #define PD_STATE_PORT_LOGGED_IN 6
750 #define PD_STATE_PORT_UNAVAILABLE 7
751 #define PD_STATE_PROCESS_LOGOUT 8
752 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
753 #define PD_STATE_PORT_LOGOUT 10
754 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
755
756
757 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
758 #define QLA_ZIO_DISABLED 0
759 #define QLA_ZIO_DEFAULT_TIMER 2
760
761 /*
762 * ISP Initialization Control Block.
763 * Little endian except where noted.
764 */
765 #define ICB_VERSION 1
766 typedef struct {
767 uint8_t version;
768 uint8_t reserved_1;
769
770 /*
771 * LSB BIT 0 = Enable Hard Loop Id
772 * LSB BIT 1 = Enable Fairness
773 * LSB BIT 2 = Enable Full-Duplex
774 * LSB BIT 3 = Enable Fast Posting
775 * LSB BIT 4 = Enable Target Mode
776 * LSB BIT 5 = Disable Initiator Mode
777 * LSB BIT 6 = Enable ADISC
778 * LSB BIT 7 = Enable Target Inquiry Data
779 *
780 * MSB BIT 0 = Enable PDBC Notify
781 * MSB BIT 1 = Non Participating LIP
782 * MSB BIT 2 = Descending Loop ID Search
783 * MSB BIT 3 = Acquire Loop ID in LIPA
784 * MSB BIT 4 = Stop PortQ on Full Status
785 * MSB BIT 5 = Full Login after LIP
786 * MSB BIT 6 = Node Name Option
787 * MSB BIT 7 = Ext IFWCB enable bit
788 */
789 uint8_t firmware_options[2];
790
791 uint16_t frame_payload_size;
792 uint16_t max_iocb_allocation;
793 uint16_t execution_throttle;
794 uint8_t retry_count;
795 uint8_t retry_delay; /* unused */
796 uint8_t port_name[WWN_SIZE]; /* Big endian. */
797 uint16_t hard_address;
798 uint8_t inquiry_data;
799 uint8_t login_timeout;
800 uint8_t node_name[WWN_SIZE]; /* Big endian. */
801
802 uint16_t request_q_outpointer;
803 uint16_t response_q_inpointer;
804 uint16_t request_q_length;
805 uint16_t response_q_length;
806 uint32_t request_q_address[2];
807 uint32_t response_q_address[2];
808
809 uint16_t lun_enables;
810 uint8_t command_resource_count;
811 uint8_t immediate_notify_resource_count;
812 uint16_t timeout;
813 uint8_t reserved_2[2];
814
815 /*
816 * LSB BIT 0 = Timer Operation mode bit 0
817 * LSB BIT 1 = Timer Operation mode bit 1
818 * LSB BIT 2 = Timer Operation mode bit 2
819 * LSB BIT 3 = Timer Operation mode bit 3
820 * LSB BIT 4 = Init Config Mode bit 0
821 * LSB BIT 5 = Init Config Mode bit 1
822 * LSB BIT 6 = Init Config Mode bit 2
823 * LSB BIT 7 = Enable Non part on LIHA failure
824 *
825 * MSB BIT 0 = Enable class 2
826 * MSB BIT 1 = Enable ACK0
827 * MSB BIT 2 =
828 * MSB BIT 3 =
829 * MSB BIT 4 = FC Tape Enable
830 * MSB BIT 5 = Enable FC Confirm
831 * MSB BIT 6 = Enable command queuing in target mode
832 * MSB BIT 7 = No Logo On Link Down
833 */
834 uint8_t add_firmware_options[2];
835
836 uint8_t response_accumulation_timer;
837 uint8_t interrupt_delay_timer;
838
839 /*
840 * LSB BIT 0 = Enable Read xfr_rdy
841 * LSB BIT 1 = Soft ID only
842 * LSB BIT 2 =
843 * LSB BIT 3 =
844 * LSB BIT 4 = FCP RSP Payload [0]
845 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
846 * LSB BIT 6 = Enable Out-of-Order frame handling
847 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
848 *
849 * MSB BIT 0 = Sbus enable - 2300
850 * MSB BIT 1 =
851 * MSB BIT 2 =
852 * MSB BIT 3 =
853 * MSB BIT 4 = LED mode
854 * MSB BIT 5 = enable 50 ohm termination
855 * MSB BIT 6 = Data Rate (2300 only)
856 * MSB BIT 7 = Data Rate (2300 only)
857 */
858 uint8_t special_options[2];
859
860 uint8_t reserved_3[26];
861 } init_cb_t;
862
863 /*
864 * Get Link Status mailbox command return buffer.
865 */
866 #define GLSO_SEND_RPS BIT_0
867 #define GLSO_USE_DID BIT_3
868
869 struct link_statistics {
870 uint32_t link_fail_cnt;
871 uint32_t loss_sync_cnt;
872 uint32_t loss_sig_cnt;
873 uint32_t prim_seq_err_cnt;
874 uint32_t inval_xmit_word_cnt;
875 uint32_t inval_crc_cnt;
876 uint32_t lip_cnt;
877 uint32_t unused1[0x1a];
878 uint32_t tx_frames;
879 uint32_t rx_frames;
880 uint32_t dumped_frames;
881 uint32_t unused2[2];
882 uint32_t nos_rcvd;
883 };
884
885 /*
886 * NVRAM Command values.
887 */
888 #define NV_START_BIT BIT_2
889 #define NV_WRITE_OP (BIT_26+BIT_24)
890 #define NV_READ_OP (BIT_26+BIT_25)
891 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
892 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
893 #define NV_DELAY_COUNT 10
894
895 /*
896 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
897 */
898 typedef struct {
899 /*
900 * NVRAM header
901 */
902 uint8_t id[4];
903 uint8_t nvram_version;
904 uint8_t reserved_0;
905
906 /*
907 * NVRAM RISC parameter block
908 */
909 uint8_t parameter_block_version;
910 uint8_t reserved_1;
911
912 /*
913 * LSB BIT 0 = Enable Hard Loop Id
914 * LSB BIT 1 = Enable Fairness
915 * LSB BIT 2 = Enable Full-Duplex
916 * LSB BIT 3 = Enable Fast Posting
917 * LSB BIT 4 = Enable Target Mode
918 * LSB BIT 5 = Disable Initiator Mode
919 * LSB BIT 6 = Enable ADISC
920 * LSB BIT 7 = Enable Target Inquiry Data
921 *
922 * MSB BIT 0 = Enable PDBC Notify
923 * MSB BIT 1 = Non Participating LIP
924 * MSB BIT 2 = Descending Loop ID Search
925 * MSB BIT 3 = Acquire Loop ID in LIPA
926 * MSB BIT 4 = Stop PortQ on Full Status
927 * MSB BIT 5 = Full Login after LIP
928 * MSB BIT 6 = Node Name Option
929 * MSB BIT 7 = Ext IFWCB enable bit
930 */
931 uint8_t firmware_options[2];
932
933 uint16_t frame_payload_size;
934 uint16_t max_iocb_allocation;
935 uint16_t execution_throttle;
936 uint8_t retry_count;
937 uint8_t retry_delay; /* unused */
938 uint8_t port_name[WWN_SIZE]; /* Big endian. */
939 uint16_t hard_address;
940 uint8_t inquiry_data;
941 uint8_t login_timeout;
942 uint8_t node_name[WWN_SIZE]; /* Big endian. */
943
944 /*
945 * LSB BIT 0 = Timer Operation mode bit 0
946 * LSB BIT 1 = Timer Operation mode bit 1
947 * LSB BIT 2 = Timer Operation mode bit 2
948 * LSB BIT 3 = Timer Operation mode bit 3
949 * LSB BIT 4 = Init Config Mode bit 0
950 * LSB BIT 5 = Init Config Mode bit 1
951 * LSB BIT 6 = Init Config Mode bit 2
952 * LSB BIT 7 = Enable Non part on LIHA failure
953 *
954 * MSB BIT 0 = Enable class 2
955 * MSB BIT 1 = Enable ACK0
956 * MSB BIT 2 =
957 * MSB BIT 3 =
958 * MSB BIT 4 = FC Tape Enable
959 * MSB BIT 5 = Enable FC Confirm
960 * MSB BIT 6 = Enable command queuing in target mode
961 * MSB BIT 7 = No Logo On Link Down
962 */
963 uint8_t add_firmware_options[2];
964
965 uint8_t response_accumulation_timer;
966 uint8_t interrupt_delay_timer;
967
968 /*
969 * LSB BIT 0 = Enable Read xfr_rdy
970 * LSB BIT 1 = Soft ID only
971 * LSB BIT 2 =
972 * LSB BIT 3 =
973 * LSB BIT 4 = FCP RSP Payload [0]
974 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
975 * LSB BIT 6 = Enable Out-of-Order frame handling
976 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
977 *
978 * MSB BIT 0 = Sbus enable - 2300
979 * MSB BIT 1 =
980 * MSB BIT 2 =
981 * MSB BIT 3 =
982 * MSB BIT 4 = LED mode
983 * MSB BIT 5 = enable 50 ohm termination
984 * MSB BIT 6 = Data Rate (2300 only)
985 * MSB BIT 7 = Data Rate (2300 only)
986 */
987 uint8_t special_options[2];
988
989 /* Reserved for expanded RISC parameter block */
990 uint8_t reserved_2[22];
991
992 /*
993 * LSB BIT 0 = Tx Sensitivity 1G bit 0
994 * LSB BIT 1 = Tx Sensitivity 1G bit 1
995 * LSB BIT 2 = Tx Sensitivity 1G bit 2
996 * LSB BIT 3 = Tx Sensitivity 1G bit 3
997 * LSB BIT 4 = Rx Sensitivity 1G bit 0
998 * LSB BIT 5 = Rx Sensitivity 1G bit 1
999 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1000 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1001 *
1002 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1003 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1004 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1005 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1006 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1007 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1008 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1009 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1010 *
1011 * LSB BIT 0 = Output Swing 1G bit 0
1012 * LSB BIT 1 = Output Swing 1G bit 1
1013 * LSB BIT 2 = Output Swing 1G bit 2
1014 * LSB BIT 3 = Output Emphasis 1G bit 0
1015 * LSB BIT 4 = Output Emphasis 1G bit 1
1016 * LSB BIT 5 = Output Swing 2G bit 0
1017 * LSB BIT 6 = Output Swing 2G bit 1
1018 * LSB BIT 7 = Output Swing 2G bit 2
1019 *
1020 * MSB BIT 0 = Output Emphasis 2G bit 0
1021 * MSB BIT 1 = Output Emphasis 2G bit 1
1022 * MSB BIT 2 = Output Enable
1023 * MSB BIT 3 =
1024 * MSB BIT 4 =
1025 * MSB BIT 5 =
1026 * MSB BIT 6 =
1027 * MSB BIT 7 =
1028 */
1029 uint8_t seriallink_options[4];
1030
1031 /*
1032 * NVRAM host parameter block
1033 *
1034 * LSB BIT 0 = Enable spinup delay
1035 * LSB BIT 1 = Disable BIOS
1036 * LSB BIT 2 = Enable Memory Map BIOS
1037 * LSB BIT 3 = Enable Selectable Boot
1038 * LSB BIT 4 = Disable RISC code load
1039 * LSB BIT 5 = Set cache line size 1
1040 * LSB BIT 6 = PCI Parity Disable
1041 * LSB BIT 7 = Enable extended logging
1042 *
1043 * MSB BIT 0 = Enable 64bit addressing
1044 * MSB BIT 1 = Enable lip reset
1045 * MSB BIT 2 = Enable lip full login
1046 * MSB BIT 3 = Enable target reset
1047 * MSB BIT 4 = Enable database storage
1048 * MSB BIT 5 = Enable cache flush read
1049 * MSB BIT 6 = Enable database load
1050 * MSB BIT 7 = Enable alternate WWN
1051 */
1052 uint8_t host_p[2];
1053
1054 uint8_t boot_node_name[WWN_SIZE];
1055 uint8_t boot_lun_number;
1056 uint8_t reset_delay;
1057 uint8_t port_down_retry_count;
1058 uint8_t boot_id_number;
1059 uint16_t max_luns_per_target;
1060 uint8_t fcode_boot_port_name[WWN_SIZE];
1061 uint8_t alternate_port_name[WWN_SIZE];
1062 uint8_t alternate_node_name[WWN_SIZE];
1063
1064 /*
1065 * BIT 0 = Selective Login
1066 * BIT 1 = Alt-Boot Enable
1067 * BIT 2 =
1068 * BIT 3 = Boot Order List
1069 * BIT 4 =
1070 * BIT 5 = Selective LUN
1071 * BIT 6 =
1072 * BIT 7 = unused
1073 */
1074 uint8_t efi_parameters;
1075
1076 uint8_t link_down_timeout;
1077
1078 uint8_t adapter_id[16];
1079
1080 uint8_t alt1_boot_node_name[WWN_SIZE];
1081 uint16_t alt1_boot_lun_number;
1082 uint8_t alt2_boot_node_name[WWN_SIZE];
1083 uint16_t alt2_boot_lun_number;
1084 uint8_t alt3_boot_node_name[WWN_SIZE];
1085 uint16_t alt3_boot_lun_number;
1086 uint8_t alt4_boot_node_name[WWN_SIZE];
1087 uint16_t alt4_boot_lun_number;
1088 uint8_t alt5_boot_node_name[WWN_SIZE];
1089 uint16_t alt5_boot_lun_number;
1090 uint8_t alt6_boot_node_name[WWN_SIZE];
1091 uint16_t alt6_boot_lun_number;
1092 uint8_t alt7_boot_node_name[WWN_SIZE];
1093 uint16_t alt7_boot_lun_number;
1094
1095 uint8_t reserved_3[2];
1096
1097 /* Offset 200-215 : Model Number */
1098 uint8_t model_number[16];
1099
1100 /* OEM related items */
1101 uint8_t oem_specific[16];
1102
1103 /*
1104 * NVRAM Adapter Features offset 232-239
1105 *
1106 * LSB BIT 0 = External GBIC
1107 * LSB BIT 1 = Risc RAM parity
1108 * LSB BIT 2 = Buffer Plus Module
1109 * LSB BIT 3 = Multi Chip Adapter
1110 * LSB BIT 4 = Internal connector
1111 * LSB BIT 5 =
1112 * LSB BIT 6 =
1113 * LSB BIT 7 =
1114 *
1115 * MSB BIT 0 =
1116 * MSB BIT 1 =
1117 * MSB BIT 2 =
1118 * MSB BIT 3 =
1119 * MSB BIT 4 =
1120 * MSB BIT 5 =
1121 * MSB BIT 6 =
1122 * MSB BIT 7 =
1123 */
1124 uint8_t adapter_features[2];
1125
1126 uint8_t reserved_4[16];
1127
1128 /* Subsystem vendor ID for ISP2200 */
1129 uint16_t subsystem_vendor_id_2200;
1130
1131 /* Subsystem device ID for ISP2200 */
1132 uint16_t subsystem_device_id_2200;
1133
1134 uint8_t reserved_5;
1135 uint8_t checksum;
1136 } nvram_t;
1137
1138 /*
1139 * ISP queue - response queue entry definition.
1140 */
1141 typedef struct {
1142 uint8_t data[60];
1143 uint32_t signature;
1144 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1145 } response_t;
1146
1147 typedef union {
1148 uint16_t extended;
1149 struct {
1150 uint8_t reserved;
1151 uint8_t standard;
1152 } id;
1153 } target_id_t;
1154
1155 #define SET_TARGET_ID(ha, to, from) \
1156 do { \
1157 if (HAS_EXTENDED_IDS(ha)) \
1158 to.extended = cpu_to_le16(from); \
1159 else \
1160 to.id.standard = (uint8_t)from; \
1161 } while (0)
1162
1163 /*
1164 * ISP queue - command entry structure definition.
1165 */
1166 #define COMMAND_TYPE 0x11 /* Command entry */
1167 typedef struct {
1168 uint8_t entry_type; /* Entry type. */
1169 uint8_t entry_count; /* Entry count. */
1170 uint8_t sys_define; /* System defined. */
1171 uint8_t entry_status; /* Entry Status. */
1172 uint32_t handle; /* System handle. */
1173 target_id_t target; /* SCSI ID */
1174 uint16_t lun; /* SCSI LUN */
1175 uint16_t control_flags; /* Control flags. */
1176 #define CF_WRITE BIT_6
1177 #define CF_READ BIT_5
1178 #define CF_SIMPLE_TAG BIT_3
1179 #define CF_ORDERED_TAG BIT_2
1180 #define CF_HEAD_TAG BIT_1
1181 uint16_t reserved_1;
1182 uint16_t timeout; /* Command timeout. */
1183 uint16_t dseg_count; /* Data segment count. */
1184 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1185 uint32_t byte_count; /* Total byte count. */
1186 uint32_t dseg_0_address; /* Data segment 0 address. */
1187 uint32_t dseg_0_length; /* Data segment 0 length. */
1188 uint32_t dseg_1_address; /* Data segment 1 address. */
1189 uint32_t dseg_1_length; /* Data segment 1 length. */
1190 uint32_t dseg_2_address; /* Data segment 2 address. */
1191 uint32_t dseg_2_length; /* Data segment 2 length. */
1192 } cmd_entry_t;
1193
1194 /*
1195 * ISP queue - 64-Bit addressing, command entry structure definition.
1196 */
1197 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1198 typedef struct {
1199 uint8_t entry_type; /* Entry type. */
1200 uint8_t entry_count; /* Entry count. */
1201 uint8_t sys_define; /* System defined. */
1202 uint8_t entry_status; /* Entry Status. */
1203 uint32_t handle; /* System handle. */
1204 target_id_t target; /* SCSI ID */
1205 uint16_t lun; /* SCSI LUN */
1206 uint16_t control_flags; /* Control flags. */
1207 uint16_t reserved_1;
1208 uint16_t timeout; /* Command timeout. */
1209 uint16_t dseg_count; /* Data segment count. */
1210 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1211 uint32_t byte_count; /* Total byte count. */
1212 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1213 uint32_t dseg_0_length; /* Data segment 0 length. */
1214 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1215 uint32_t dseg_1_length; /* Data segment 1 length. */
1216 } cmd_a64_entry_t, request_t;
1217
1218 /*
1219 * ISP queue - continuation entry structure definition.
1220 */
1221 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1222 typedef struct {
1223 uint8_t entry_type; /* Entry type. */
1224 uint8_t entry_count; /* Entry count. */
1225 uint8_t sys_define; /* System defined. */
1226 uint8_t entry_status; /* Entry Status. */
1227 uint32_t reserved;
1228 uint32_t dseg_0_address; /* Data segment 0 address. */
1229 uint32_t dseg_0_length; /* Data segment 0 length. */
1230 uint32_t dseg_1_address; /* Data segment 1 address. */
1231 uint32_t dseg_1_length; /* Data segment 1 length. */
1232 uint32_t dseg_2_address; /* Data segment 2 address. */
1233 uint32_t dseg_2_length; /* Data segment 2 length. */
1234 uint32_t dseg_3_address; /* Data segment 3 address. */
1235 uint32_t dseg_3_length; /* Data segment 3 length. */
1236 uint32_t dseg_4_address; /* Data segment 4 address. */
1237 uint32_t dseg_4_length; /* Data segment 4 length. */
1238 uint32_t dseg_5_address; /* Data segment 5 address. */
1239 uint32_t dseg_5_length; /* Data segment 5 length. */
1240 uint32_t dseg_6_address; /* Data segment 6 address. */
1241 uint32_t dseg_6_length; /* Data segment 6 length. */
1242 } cont_entry_t;
1243
1244 /*
1245 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1246 */
1247 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1248 typedef struct {
1249 uint8_t entry_type; /* Entry type. */
1250 uint8_t entry_count; /* Entry count. */
1251 uint8_t sys_define; /* System defined. */
1252 uint8_t entry_status; /* Entry Status. */
1253 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1254 uint32_t dseg_0_length; /* Data segment 0 length. */
1255 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1256 uint32_t dseg_1_length; /* Data segment 1 length. */
1257 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1258 uint32_t dseg_2_length; /* Data segment 2 length. */
1259 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1260 uint32_t dseg_3_length; /* Data segment 3 length. */
1261 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1262 uint32_t dseg_4_length; /* Data segment 4 length. */
1263 } cont_a64_entry_t;
1264
1265 /*
1266 * ISP queue - status entry structure definition.
1267 */
1268 #define STATUS_TYPE 0x03 /* Status entry. */
1269 typedef struct {
1270 uint8_t entry_type; /* Entry type. */
1271 uint8_t entry_count; /* Entry count. */
1272 uint8_t sys_define; /* System defined. */
1273 uint8_t entry_status; /* Entry Status. */
1274 uint32_t handle; /* System handle. */
1275 uint16_t scsi_status; /* SCSI status. */
1276 uint16_t comp_status; /* Completion status. */
1277 uint16_t state_flags; /* State flags. */
1278 uint16_t status_flags; /* Status flags. */
1279 uint16_t rsp_info_len; /* Response Info Length. */
1280 uint16_t req_sense_length; /* Request sense data length. */
1281 uint32_t residual_length; /* Residual transfer length. */
1282 uint8_t rsp_info[8]; /* FCP response information. */
1283 uint8_t req_sense_data[32]; /* Request sense data. */
1284 } sts_entry_t;
1285
1286 /*
1287 * Status entry entry status
1288 */
1289 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1290 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1291 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1292 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1293 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1294 #define RF_BUSY BIT_1 /* Busy */
1295 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1296 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1297 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1298 RF_INV_E_TYPE)
1299
1300 /*
1301 * Status entry SCSI status bit definitions.
1302 */
1303 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1304 #define SS_RESIDUAL_UNDER BIT_11
1305 #define SS_RESIDUAL_OVER BIT_10
1306 #define SS_SENSE_LEN_VALID BIT_9
1307 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1308
1309 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1310 #define SS_BUSY_CONDITION BIT_3
1311 #define SS_CONDITION_MET BIT_2
1312 #define SS_CHECK_CONDITION BIT_1
1313
1314 /*
1315 * Status entry completion status
1316 */
1317 #define CS_COMPLETE 0x0 /* No errors */
1318 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1319 #define CS_DMA 0x2 /* A DMA direction error. */
1320 #define CS_TRANSPORT 0x3 /* Transport error. */
1321 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1322 #define CS_ABORTED 0x5 /* System aborted command. */
1323 #define CS_TIMEOUT 0x6 /* Timeout error. */
1324 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1325
1326 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1327 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1328 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1329 /* (selection timeout) */
1330 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1331 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1332 #define CS_PORT_BUSY 0x2B /* Port Busy */
1333 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1334 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1335 #define CS_UNKNOWN 0x81 /* Driver defined */
1336 #define CS_RETRY 0x82 /* Driver defined */
1337 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1338
1339 /*
1340 * Status entry status flags
1341 */
1342 #define SF_ABTS_TERMINATED BIT_10
1343 #define SF_LOGOUT_SENT BIT_13
1344
1345 /*
1346 * ISP queue - status continuation entry structure definition.
1347 */
1348 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1349 typedef struct {
1350 uint8_t entry_type; /* Entry type. */
1351 uint8_t entry_count; /* Entry count. */
1352 uint8_t sys_define; /* System defined. */
1353 uint8_t entry_status; /* Entry Status. */
1354 uint8_t data[60]; /* data */
1355 } sts_cont_entry_t;
1356
1357 /*
1358 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1359 * structure definition.
1360 */
1361 #define STATUS_TYPE_21 0x21 /* Status entry. */
1362 typedef struct {
1363 uint8_t entry_type; /* Entry type. */
1364 uint8_t entry_count; /* Entry count. */
1365 uint8_t handle_count; /* Handle count. */
1366 uint8_t entry_status; /* Entry Status. */
1367 uint32_t handle[15]; /* System handles. */
1368 } sts21_entry_t;
1369
1370 /*
1371 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1372 * structure definition.
1373 */
1374 #define STATUS_TYPE_22 0x22 /* Status entry. */
1375 typedef struct {
1376 uint8_t entry_type; /* Entry type. */
1377 uint8_t entry_count; /* Entry count. */
1378 uint8_t handle_count; /* Handle count. */
1379 uint8_t entry_status; /* Entry Status. */
1380 uint16_t handle[30]; /* System handles. */
1381 } sts22_entry_t;
1382
1383 /*
1384 * ISP queue - marker entry structure definition.
1385 */
1386 #define MARKER_TYPE 0x04 /* Marker entry. */
1387 typedef struct {
1388 uint8_t entry_type; /* Entry type. */
1389 uint8_t entry_count; /* Entry count. */
1390 uint8_t handle_count; /* Handle count. */
1391 uint8_t entry_status; /* Entry Status. */
1392 uint32_t sys_define_2; /* System defined. */
1393 target_id_t target; /* SCSI ID */
1394 uint8_t modifier; /* Modifier (7-0). */
1395 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1396 #define MK_SYNC_ID 1 /* Synchronize ID */
1397 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1398 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1399 /* clear port changed, */
1400 /* use sequence number. */
1401 uint8_t reserved_1;
1402 uint16_t sequence_number; /* Sequence number of event */
1403 uint16_t lun; /* SCSI LUN */
1404 uint8_t reserved_2[48];
1405 } mrk_entry_t;
1406
1407 /*
1408 * ISP queue - Management Server entry structure definition.
1409 */
1410 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1411 typedef struct {
1412 uint8_t entry_type; /* Entry type. */
1413 uint8_t entry_count; /* Entry count. */
1414 uint8_t handle_count; /* Handle count. */
1415 uint8_t entry_status; /* Entry Status. */
1416 uint32_t handle1; /* System handle. */
1417 target_id_t loop_id;
1418 uint16_t status;
1419 uint16_t control_flags; /* Control flags. */
1420 uint16_t reserved2;
1421 uint16_t timeout;
1422 uint16_t cmd_dsd_count;
1423 uint16_t total_dsd_count;
1424 uint8_t type;
1425 uint8_t r_ctl;
1426 uint16_t rx_id;
1427 uint16_t reserved3;
1428 uint32_t handle2;
1429 uint32_t rsp_bytecount;
1430 uint32_t req_bytecount;
1431 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1432 uint32_t dseg_req_length; /* Data segment 0 length. */
1433 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1434 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1435 } ms_iocb_entry_t;
1436
1437
1438 /*
1439 * ISP queue - Mailbox Command entry structure definition.
1440 */
1441 #define MBX_IOCB_TYPE 0x39
1442 struct mbx_entry {
1443 uint8_t entry_type;
1444 uint8_t entry_count;
1445 uint8_t sys_define1;
1446 /* Use sys_define1 for source type */
1447 #define SOURCE_SCSI 0x00
1448 #define SOURCE_IP 0x01
1449 #define SOURCE_VI 0x02
1450 #define SOURCE_SCTP 0x03
1451 #define SOURCE_MP 0x04
1452 #define SOURCE_MPIOCTL 0x05
1453 #define SOURCE_ASYNC_IOCB 0x07
1454
1455 uint8_t entry_status;
1456
1457 uint32_t handle;
1458 target_id_t loop_id;
1459
1460 uint16_t status;
1461 uint16_t state_flags;
1462 uint16_t status_flags;
1463
1464 uint32_t sys_define2[2];
1465
1466 uint16_t mb0;
1467 uint16_t mb1;
1468 uint16_t mb2;
1469 uint16_t mb3;
1470 uint16_t mb6;
1471 uint16_t mb7;
1472 uint16_t mb9;
1473 uint16_t mb10;
1474 uint32_t reserved_2[2];
1475 uint8_t node_name[WWN_SIZE];
1476 uint8_t port_name[WWN_SIZE];
1477 };
1478
1479 /*
1480 * ISP request and response queue entry sizes
1481 */
1482 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1483 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1484
1485
1486 /*
1487 * 24 bit port ID type definition.
1488 */
1489 typedef union {
1490 uint32_t b24 : 24;
1491
1492 struct {
1493 #ifdef __BIG_ENDIAN
1494 uint8_t domain;
1495 uint8_t area;
1496 uint8_t al_pa;
1497 #elif __LITTLE_ENDIAN
1498 uint8_t al_pa;
1499 uint8_t area;
1500 uint8_t domain;
1501 #else
1502 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1503 #endif
1504 uint8_t rsvd_1;
1505 } b;
1506 } port_id_t;
1507 #define INVALID_PORT_ID 0xFFFFFF
1508
1509 /*
1510 * Switch info gathering structure.
1511 */
1512 typedef struct {
1513 port_id_t d_id;
1514 uint8_t node_name[WWN_SIZE];
1515 uint8_t port_name[WWN_SIZE];
1516 uint8_t fabric_port_name[WWN_SIZE];
1517 uint16_t fp_speed;
1518 } sw_info_t;
1519
1520 /*
1521 * Fibre channel port type.
1522 */
1523 typedef enum {
1524 FCT_UNKNOWN,
1525 FCT_RSCN,
1526 FCT_SWITCH,
1527 FCT_BROADCAST,
1528 FCT_INITIATOR,
1529 FCT_TARGET
1530 } fc_port_type_t;
1531
1532 /*
1533 * Fibre channel port structure.
1534 */
1535 typedef struct fc_port {
1536 struct list_head list;
1537 struct scsi_qla_host *vha;
1538
1539 uint8_t node_name[WWN_SIZE];
1540 uint8_t port_name[WWN_SIZE];
1541 port_id_t d_id;
1542 uint16_t loop_id;
1543 uint16_t old_loop_id;
1544
1545 uint8_t fabric_port_name[WWN_SIZE];
1546 uint16_t fp_speed;
1547
1548 fc_port_type_t port_type;
1549
1550 atomic_t state;
1551 uint32_t flags;
1552
1553 int port_login_retry_count;
1554 int login_retry;
1555 atomic_t port_down_timer;
1556
1557 struct fc_rport *rport, *drport;
1558 u32 supported_classes;
1559
1560 unsigned long last_queue_full;
1561 unsigned long last_ramp_up;
1562
1563 uint16_t vp_idx;
1564 } fc_port_t;
1565
1566 /*
1567 * Fibre channel port/lun states.
1568 */
1569 #define FCS_UNCONFIGURED 1
1570 #define FCS_DEVICE_DEAD 2
1571 #define FCS_DEVICE_LOST 3
1572 #define FCS_ONLINE 4
1573 #define FCS_NOT_SUPPORTED 5
1574 #define FCS_FAILOVER 6
1575 #define FCS_FAILOVER_FAILED 7
1576
1577 /*
1578 * FC port flags.
1579 */
1580 #define FCF_FABRIC_DEVICE BIT_0
1581 #define FCF_LOGIN_NEEDED BIT_1
1582 #define FCF_FO_MASKED BIT_2
1583 #define FCF_FAILOVER_NEEDED BIT_3
1584 #define FCF_RESET_NEEDED BIT_4
1585 #define FCF_PERSISTENT_BOUND BIT_5
1586 #define FCF_TAPE_PRESENT BIT_6
1587 #define FCF_FARP_DONE BIT_7
1588 #define FCF_FARP_FAILED BIT_8
1589 #define FCF_FARP_REPLY_NEEDED BIT_9
1590 #define FCF_AUTH_REQ BIT_10
1591 #define FCF_SEND_AUTH_REQ BIT_11
1592 #define FCF_RECEIVE_AUTH_REQ BIT_12
1593 #define FCF_AUTH_SUCCESS BIT_13
1594 #define FCF_RLC_SUPPORT BIT_14
1595 #define FCF_CONFIG BIT_15 /* Needed? */
1596 #define FCF_RESCAN_NEEDED BIT_16
1597 #define FCF_XP_DEVICE BIT_17
1598 #define FCF_MSA_DEVICE BIT_18
1599 #define FCF_EVA_DEVICE BIT_19
1600 #define FCF_MSA_PORT_ACTIVE BIT_20
1601 #define FCF_FAILBACK_DISABLE BIT_21
1602 #define FCF_FAILOVER_DISABLE BIT_22
1603 #define FCF_DSXXX_DEVICE BIT_23
1604 #define FCF_AA_EVA_DEVICE BIT_24
1605 #define FCF_AA_MSA_DEVICE BIT_25
1606
1607 /* No loop ID flag. */
1608 #define FC_NO_LOOP_ID 0x1000
1609
1610 /*
1611 * FC-CT interface
1612 *
1613 * NOTE: All structures are big-endian in form.
1614 */
1615
1616 #define CT_REJECT_RESPONSE 0x8001
1617 #define CT_ACCEPT_RESPONSE 0x8002
1618 #define CT_REASON_INVALID_COMMAND_CODE 0x01
1619 #define CT_REASON_CANNOT_PERFORM 0x09
1620 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
1621 #define CT_EXPL_ALREADY_REGISTERED 0x10
1622
1623 #define NS_N_PORT_TYPE 0x01
1624 #define NS_NL_PORT_TYPE 0x02
1625 #define NS_NX_PORT_TYPE 0x7F
1626
1627 #define GA_NXT_CMD 0x100
1628 #define GA_NXT_REQ_SIZE (16 + 4)
1629 #define GA_NXT_RSP_SIZE (16 + 620)
1630
1631 #define GID_PT_CMD 0x1A1
1632 #define GID_PT_REQ_SIZE (16 + 4)
1633 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1634
1635 #define GPN_ID_CMD 0x112
1636 #define GPN_ID_REQ_SIZE (16 + 4)
1637 #define GPN_ID_RSP_SIZE (16 + 8)
1638
1639 #define GNN_ID_CMD 0x113
1640 #define GNN_ID_REQ_SIZE (16 + 4)
1641 #define GNN_ID_RSP_SIZE (16 + 8)
1642
1643 #define GFT_ID_CMD 0x117
1644 #define GFT_ID_REQ_SIZE (16 + 4)
1645 #define GFT_ID_RSP_SIZE (16 + 32)
1646
1647 #define RFT_ID_CMD 0x217
1648 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1649 #define RFT_ID_RSP_SIZE 16
1650
1651 #define RFF_ID_CMD 0x21F
1652 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1653 #define RFF_ID_RSP_SIZE 16
1654
1655 #define RNN_ID_CMD 0x213
1656 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1657 #define RNN_ID_RSP_SIZE 16
1658
1659 #define RSNN_NN_CMD 0x239
1660 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1661 #define RSNN_NN_RSP_SIZE 16
1662
1663 #define GFPN_ID_CMD 0x11C
1664 #define GFPN_ID_REQ_SIZE (16 + 4)
1665 #define GFPN_ID_RSP_SIZE (16 + 8)
1666
1667 #define GPSC_CMD 0x127
1668 #define GPSC_REQ_SIZE (16 + 8)
1669 #define GPSC_RSP_SIZE (16 + 2 + 2)
1670
1671
1672 /*
1673 * HBA attribute types.
1674 */
1675 #define FDMI_HBA_ATTR_COUNT 9
1676 #define FDMI_HBA_NODE_NAME 1
1677 #define FDMI_HBA_MANUFACTURER 2
1678 #define FDMI_HBA_SERIAL_NUMBER 3
1679 #define FDMI_HBA_MODEL 4
1680 #define FDMI_HBA_MODEL_DESCRIPTION 5
1681 #define FDMI_HBA_HARDWARE_VERSION 6
1682 #define FDMI_HBA_DRIVER_VERSION 7
1683 #define FDMI_HBA_OPTION_ROM_VERSION 8
1684 #define FDMI_HBA_FIRMWARE_VERSION 9
1685 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1686 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1687
1688 struct ct_fdmi_hba_attr {
1689 uint16_t type;
1690 uint16_t len;
1691 union {
1692 uint8_t node_name[WWN_SIZE];
1693 uint8_t manufacturer[32];
1694 uint8_t serial_num[8];
1695 uint8_t model[16];
1696 uint8_t model_desc[80];
1697 uint8_t hw_version[16];
1698 uint8_t driver_version[32];
1699 uint8_t orom_version[16];
1700 uint8_t fw_version[16];
1701 uint8_t os_version[128];
1702 uint8_t max_ct_len[4];
1703 } a;
1704 };
1705
1706 struct ct_fdmi_hba_attributes {
1707 uint32_t count;
1708 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1709 };
1710
1711 /*
1712 * Port attribute types.
1713 */
1714 #define FDMI_PORT_ATTR_COUNT 6
1715 #define FDMI_PORT_FC4_TYPES 1
1716 #define FDMI_PORT_SUPPORT_SPEED 2
1717 #define FDMI_PORT_CURRENT_SPEED 3
1718 #define FDMI_PORT_MAX_FRAME_SIZE 4
1719 #define FDMI_PORT_OS_DEVICE_NAME 5
1720 #define FDMI_PORT_HOST_NAME 6
1721
1722 #define FDMI_PORT_SPEED_1GB 0x1
1723 #define FDMI_PORT_SPEED_2GB 0x2
1724 #define FDMI_PORT_SPEED_10GB 0x4
1725 #define FDMI_PORT_SPEED_4GB 0x8
1726 #define FDMI_PORT_SPEED_8GB 0x10
1727 #define FDMI_PORT_SPEED_16GB 0x20
1728 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
1729
1730 struct ct_fdmi_port_attr {
1731 uint16_t type;
1732 uint16_t len;
1733 union {
1734 uint8_t fc4_types[32];
1735 uint32_t sup_speed;
1736 uint32_t cur_speed;
1737 uint32_t max_frame_size;
1738 uint8_t os_dev_name[32];
1739 uint8_t host_name[32];
1740 } a;
1741 };
1742
1743 /*
1744 * Port Attribute Block.
1745 */
1746 struct ct_fdmi_port_attributes {
1747 uint32_t count;
1748 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1749 };
1750
1751 /* FDMI definitions. */
1752 #define GRHL_CMD 0x100
1753 #define GHAT_CMD 0x101
1754 #define GRPL_CMD 0x102
1755 #define GPAT_CMD 0x110
1756
1757 #define RHBA_CMD 0x200
1758 #define RHBA_RSP_SIZE 16
1759
1760 #define RHAT_CMD 0x201
1761 #define RPRT_CMD 0x210
1762
1763 #define RPA_CMD 0x211
1764 #define RPA_RSP_SIZE 16
1765
1766 #define DHBA_CMD 0x300
1767 #define DHBA_REQ_SIZE (16 + 8)
1768 #define DHBA_RSP_SIZE 16
1769
1770 #define DHAT_CMD 0x301
1771 #define DPRT_CMD 0x310
1772 #define DPA_CMD 0x311
1773
1774 /* CT command header -- request/response common fields */
1775 struct ct_cmd_hdr {
1776 uint8_t revision;
1777 uint8_t in_id[3];
1778 uint8_t gs_type;
1779 uint8_t gs_subtype;
1780 uint8_t options;
1781 uint8_t reserved;
1782 };
1783
1784 /* CT command request */
1785 struct ct_sns_req {
1786 struct ct_cmd_hdr header;
1787 uint16_t command;
1788 uint16_t max_rsp_size;
1789 uint8_t fragment_id;
1790 uint8_t reserved[3];
1791
1792 union {
1793 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
1794 struct {
1795 uint8_t reserved;
1796 uint8_t port_id[3];
1797 } port_id;
1798
1799 struct {
1800 uint8_t port_type;
1801 uint8_t domain;
1802 uint8_t area;
1803 uint8_t reserved;
1804 } gid_pt;
1805
1806 struct {
1807 uint8_t reserved;
1808 uint8_t port_id[3];
1809 uint8_t fc4_types[32];
1810 } rft_id;
1811
1812 struct {
1813 uint8_t reserved;
1814 uint8_t port_id[3];
1815 uint16_t reserved2;
1816 uint8_t fc4_feature;
1817 uint8_t fc4_type;
1818 } rff_id;
1819
1820 struct {
1821 uint8_t reserved;
1822 uint8_t port_id[3];
1823 uint8_t node_name[8];
1824 } rnn_id;
1825
1826 struct {
1827 uint8_t node_name[8];
1828 uint8_t name_len;
1829 uint8_t sym_node_name[255];
1830 } rsnn_nn;
1831
1832 struct {
1833 uint8_t hba_indentifier[8];
1834 } ghat;
1835
1836 struct {
1837 uint8_t hba_identifier[8];
1838 uint32_t entry_count;
1839 uint8_t port_name[8];
1840 struct ct_fdmi_hba_attributes attrs;
1841 } rhba;
1842
1843 struct {
1844 uint8_t hba_identifier[8];
1845 struct ct_fdmi_hba_attributes attrs;
1846 } rhat;
1847
1848 struct {
1849 uint8_t port_name[8];
1850 struct ct_fdmi_port_attributes attrs;
1851 } rpa;
1852
1853 struct {
1854 uint8_t port_name[8];
1855 } dhba;
1856
1857 struct {
1858 uint8_t port_name[8];
1859 } dhat;
1860
1861 struct {
1862 uint8_t port_name[8];
1863 } dprt;
1864
1865 struct {
1866 uint8_t port_name[8];
1867 } dpa;
1868
1869 struct {
1870 uint8_t port_name[8];
1871 } gpsc;
1872 } req;
1873 };
1874
1875 /* CT command response header */
1876 struct ct_rsp_hdr {
1877 struct ct_cmd_hdr header;
1878 uint16_t response;
1879 uint16_t residual;
1880 uint8_t fragment_id;
1881 uint8_t reason_code;
1882 uint8_t explanation_code;
1883 uint8_t vendor_unique;
1884 };
1885
1886 struct ct_sns_gid_pt_data {
1887 uint8_t control_byte;
1888 uint8_t port_id[3];
1889 };
1890
1891 struct ct_sns_rsp {
1892 struct ct_rsp_hdr header;
1893
1894 union {
1895 struct {
1896 uint8_t port_type;
1897 uint8_t port_id[3];
1898 uint8_t port_name[8];
1899 uint8_t sym_port_name_len;
1900 uint8_t sym_port_name[255];
1901 uint8_t node_name[8];
1902 uint8_t sym_node_name_len;
1903 uint8_t sym_node_name[255];
1904 uint8_t init_proc_assoc[8];
1905 uint8_t node_ip_addr[16];
1906 uint8_t class_of_service[4];
1907 uint8_t fc4_types[32];
1908 uint8_t ip_address[16];
1909 uint8_t fabric_port_name[8];
1910 uint8_t reserved;
1911 uint8_t hard_address[3];
1912 } ga_nxt;
1913
1914 struct {
1915 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1916 } gid_pt;
1917
1918 struct {
1919 uint8_t port_name[8];
1920 } gpn_id;
1921
1922 struct {
1923 uint8_t node_name[8];
1924 } gnn_id;
1925
1926 struct {
1927 uint8_t fc4_types[32];
1928 } gft_id;
1929
1930 struct {
1931 uint32_t entry_count;
1932 uint8_t port_name[8];
1933 struct ct_fdmi_hba_attributes attrs;
1934 } ghat;
1935
1936 struct {
1937 uint8_t port_name[8];
1938 } gfpn_id;
1939
1940 struct {
1941 uint16_t speeds;
1942 uint16_t speed;
1943 } gpsc;
1944 } rsp;
1945 };
1946
1947 struct ct_sns_pkt {
1948 union {
1949 struct ct_sns_req req;
1950 struct ct_sns_rsp rsp;
1951 } p;
1952 };
1953
1954 /*
1955 * SNS command structures -- for 2200 compatability.
1956 */
1957 #define RFT_ID_SNS_SCMD_LEN 22
1958 #define RFT_ID_SNS_CMD_SIZE 60
1959 #define RFT_ID_SNS_DATA_SIZE 16
1960
1961 #define RNN_ID_SNS_SCMD_LEN 10
1962 #define RNN_ID_SNS_CMD_SIZE 36
1963 #define RNN_ID_SNS_DATA_SIZE 16
1964
1965 #define GA_NXT_SNS_SCMD_LEN 6
1966 #define GA_NXT_SNS_CMD_SIZE 28
1967 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
1968
1969 #define GID_PT_SNS_SCMD_LEN 6
1970 #define GID_PT_SNS_CMD_SIZE 28
1971 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1972
1973 #define GPN_ID_SNS_SCMD_LEN 6
1974 #define GPN_ID_SNS_CMD_SIZE 28
1975 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
1976
1977 #define GNN_ID_SNS_SCMD_LEN 6
1978 #define GNN_ID_SNS_CMD_SIZE 28
1979 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
1980
1981 struct sns_cmd_pkt {
1982 union {
1983 struct {
1984 uint16_t buffer_length;
1985 uint16_t reserved_1;
1986 uint32_t buffer_address[2];
1987 uint16_t subcommand_length;
1988 uint16_t reserved_2;
1989 uint16_t subcommand;
1990 uint16_t size;
1991 uint32_t reserved_3;
1992 uint8_t param[36];
1993 } cmd;
1994
1995 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
1996 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
1997 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
1998 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
1999 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2000 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2001 } p;
2002 };
2003
2004 struct fw_blob {
2005 char *name;
2006 uint32_t segs[4];
2007 const struct firmware *fw;
2008 };
2009
2010 /* Return data from MBC_GET_ID_LIST call. */
2011 struct gid_list_info {
2012 uint8_t al_pa;
2013 uint8_t area;
2014 uint8_t domain;
2015 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2016 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2017 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2018 };
2019 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2020
2021 /* NPIV */
2022 typedef struct vport_info {
2023 uint8_t port_name[WWN_SIZE];
2024 uint8_t node_name[WWN_SIZE];
2025 int vp_id;
2026 uint16_t loop_id;
2027 unsigned long host_no;
2028 uint8_t port_id[3];
2029 int loop_state;
2030 } vport_info_t;
2031
2032 typedef struct vport_params {
2033 uint8_t port_name[WWN_SIZE];
2034 uint8_t node_name[WWN_SIZE];
2035 uint32_t options;
2036 #define VP_OPTS_RETRY_ENABLE BIT_0
2037 #define VP_OPTS_VP_DISABLE BIT_1
2038 } vport_params_t;
2039
2040 /* NPIV - return codes of VP create and modify */
2041 #define VP_RET_CODE_OK 0
2042 #define VP_RET_CODE_FATAL 1
2043 #define VP_RET_CODE_WRONG_ID 2
2044 #define VP_RET_CODE_WWPN 3
2045 #define VP_RET_CODE_RESOURCES 4
2046 #define VP_RET_CODE_NO_MEM 5
2047 #define VP_RET_CODE_NOT_FOUND 6
2048
2049 struct qla_hw_data;
2050
2051 /*
2052 * ISP operations
2053 */
2054 struct isp_operations {
2055
2056 int (*pci_config) (struct scsi_qla_host *);
2057 void (*reset_chip) (struct scsi_qla_host *);
2058 int (*chip_diag) (struct scsi_qla_host *);
2059 void (*config_rings) (struct scsi_qla_host *);
2060 void (*reset_adapter) (struct scsi_qla_host *);
2061 int (*nvram_config) (struct scsi_qla_host *);
2062 void (*update_fw_options) (struct scsi_qla_host *);
2063 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2064
2065 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2066 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2067
2068 irq_handler_t intr_handler;
2069 void (*enable_intrs) (struct qla_hw_data *);
2070 void (*disable_intrs) (struct qla_hw_data *);
2071
2072 int (*abort_command) (struct scsi_qla_host *, srb_t *,
2073 struct req_que *);
2074 int (*target_reset) (struct fc_port *, unsigned int);
2075 int (*lun_reset) (struct fc_port *, unsigned int);
2076 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2077 uint8_t, uint8_t, uint16_t *, uint8_t);
2078 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2079 uint8_t, uint8_t);
2080
2081 uint16_t (*calc_req_entries) (uint16_t);
2082 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2083 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2084 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2085 uint32_t);
2086
2087 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2088 uint32_t, uint32_t);
2089 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2090 uint32_t);
2091
2092 void (*fw_dump) (struct scsi_qla_host *, int);
2093
2094 int (*beacon_on) (struct scsi_qla_host *);
2095 int (*beacon_off) (struct scsi_qla_host *);
2096 void (*beacon_blink) (struct scsi_qla_host *);
2097
2098 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2099 uint32_t, uint32_t);
2100 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2101 uint32_t);
2102
2103 int (*get_flash_version) (struct scsi_qla_host *, void *);
2104 int (*start_scsi) (srb_t *);
2105 void (*wrt_req_reg) (struct qla_hw_data *, uint16_t, uint16_t);
2106 void (*wrt_rsp_reg) (struct qla_hw_data *, uint16_t, uint16_t);
2107 uint16_t (*rd_req_reg) (struct qla_hw_data *, uint16_t);
2108 };
2109
2110 /* MSI-X Support *************************************************************/
2111
2112 #define QLA_MSIX_CHIP_REV_24XX 3
2113 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2114 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2115
2116 #define QLA_MSIX_DEFAULT 0x00
2117 #define QLA_MSIX_RSP_Q 0x01
2118
2119 #define QLA_MIDX_DEFAULT 0
2120 #define QLA_MIDX_RSP_Q 1
2121 #define QLA_PCI_MSIX_CONTROL 0xa2
2122
2123 struct scsi_qla_host;
2124 struct rsp_que;
2125
2126 struct qla_msix_entry {
2127 int have_irq;
2128 uint32_t vector;
2129 uint16_t entry;
2130 struct rsp_que *rsp;
2131 };
2132
2133 #define WATCH_INTERVAL 1 /* number of seconds */
2134
2135 /* Work events. */
2136 enum qla_work_type {
2137 QLA_EVT_AEN,
2138 QLA_EVT_IDC_ACK,
2139 };
2140
2141
2142 struct qla_work_evt {
2143 struct list_head list;
2144 enum qla_work_type type;
2145 u32 flags;
2146 #define QLA_EVT_FLAG_FREE 0x1
2147
2148 union {
2149 struct {
2150 enum fc_host_event_code code;
2151 u32 data;
2152 } aen;
2153 struct {
2154 #define QLA_IDC_ACK_REGS 7
2155 uint16_t mb[QLA_IDC_ACK_REGS];
2156 } idc_ack;
2157 } u;
2158 };
2159
2160 struct qla_chip_state_84xx {
2161 struct list_head list;
2162 struct kref kref;
2163
2164 void *bus;
2165 spinlock_t access_lock;
2166 struct mutex fw_update_mutex;
2167 uint32_t fw_update;
2168 uint32_t op_fw_version;
2169 uint32_t op_fw_size;
2170 uint32_t op_fw_seq_size;
2171 uint32_t diag_fw_version;
2172 uint32_t gold_fw_version;
2173 };
2174
2175 struct qla_statistics {
2176 uint32_t total_isp_aborts;
2177 uint64_t input_bytes;
2178 uint64_t output_bytes;
2179 };
2180
2181 /* Multi queue support */
2182 #define MBC_INITIALIZE_MULTIQ 0x1f
2183 #define QLA_QUE_PAGE 0X1000
2184 #define QLA_MQ_SIZE 32
2185 #define QLA_MAX_HOST_QUES 16
2186 #define QLA_MAX_QUEUES 256
2187 #define ISP_QUE_REG(ha, id) \
2188 ((ha->mqenable) ? \
2189 ((void *)(ha->mqiobase) +\
2190 (QLA_QUE_PAGE * id)) :\
2191 ((void *)(ha->iobase)))
2192 #define QLA_REQ_QUE_ID(tag) \
2193 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2194 #define QLA_DEFAULT_QUE_QOS 5
2195 #define QLA_PRECONFIG_VPORTS 32
2196 #define QLA_MAX_VPORTS_QLA24XX 128
2197 #define QLA_MAX_VPORTS_QLA25XX 256
2198 /* Response queue data structure */
2199 struct rsp_que {
2200 dma_addr_t dma;
2201 response_t *ring;
2202 response_t *ring_ptr;
2203 uint16_t ring_index;
2204 uint16_t out_ptr;
2205 uint16_t length;
2206 uint16_t options;
2207 uint16_t rid;
2208 uint16_t id;
2209 uint16_t vp_idx;
2210 struct qla_hw_data *hw;
2211 struct qla_msix_entry *msix;
2212 struct req_que *req;
2213 };
2214
2215 /* Request queue data structure */
2216 struct req_que {
2217 dma_addr_t dma;
2218 request_t *ring;
2219 request_t *ring_ptr;
2220 uint16_t ring_index;
2221 uint16_t in_ptr;
2222 uint16_t cnt;
2223 uint16_t length;
2224 uint16_t options;
2225 uint16_t rid;
2226 uint16_t id;
2227 uint16_t qos;
2228 uint16_t vp_idx;
2229 struct rsp_que *rsp;
2230 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2231 uint32_t current_outstanding_cmd;
2232 int max_q_depth;
2233 };
2234
2235 /*
2236 * Qlogic host adapter specific data structure.
2237 */
2238 struct qla_hw_data {
2239 struct pci_dev *pdev;
2240 /* SRB cache. */
2241 #define SRB_MIN_REQ 128
2242 mempool_t *srb_mempool;
2243
2244 volatile struct {
2245 uint32_t mbox_int :1;
2246 uint32_t mbox_busy :1;
2247
2248 uint32_t disable_risc_code_load :1;
2249 uint32_t enable_64bit_addressing :1;
2250 uint32_t enable_lip_reset :1;
2251 uint32_t enable_target_reset :1;
2252 uint32_t enable_lip_full_login :1;
2253 uint32_t enable_led_scheme :1;
2254 uint32_t inta_enabled :1;
2255 uint32_t msi_enabled :1;
2256 uint32_t msix_enabled :1;
2257 uint32_t disable_serdes :1;
2258 uint32_t gpsc_supported :1;
2259 uint32_t vsan_enabled :1;
2260 uint32_t npiv_supported :1;
2261 uint32_t fce_enabled :1;
2262 uint32_t hw_event_marker_found:1;
2263 } flags;
2264
2265 /* This spinlock is used to protect "io transactions", you must
2266 * acquire it before doing any IO to the card, eg with RD_REG*() and
2267 * WRT_REG*() for the duration of your entire commandtransaction.
2268 *
2269 * This spinlock is of lower priority than the io request lock.
2270 */
2271
2272 spinlock_t hardware_lock ____cacheline_aligned;
2273 int bars;
2274 int mem_only;
2275 device_reg_t __iomem *iobase; /* Base I/O address */
2276 resource_size_t pio_address;
2277
2278 #define MIN_IOBASE_LEN 0x100
2279 /* Multi queue data structs */
2280 device_reg_t *mqiobase;
2281 uint16_t msix_count;
2282 uint8_t mqenable;
2283 struct req_que **req_q_map;
2284 struct rsp_que **rsp_q_map;
2285 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2286 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2287 uint16_t max_queues;
2288 struct qla_npiv_entry *npiv_info;
2289 uint16_t nvram_npiv_size;
2290
2291 uint16_t switch_cap;
2292 #define FLOGI_SEQ_DEL BIT_8
2293 #define FLOGI_MID_SUPPORT BIT_10
2294 #define FLOGI_VSAN_SUPPORT BIT_12
2295 #define FLOGI_SP_SUPPORT BIT_13
2296 /* Timeout timers. */
2297 uint8_t loop_down_abort_time; /* port down timer */
2298 atomic_t loop_down_timer; /* loop down timer */
2299 uint8_t link_down_timeout; /* link down timeout */
2300 uint16_t max_loop_id;
2301
2302 uint16_t fb_rev;
2303 uint16_t max_public_loop_ids;
2304 uint16_t min_external_loopid; /* First external loop Id */
2305
2306 #define PORT_SPEED_UNKNOWN 0xFFFF
2307 #define PORT_SPEED_1GB 0x00
2308 #define PORT_SPEED_2GB 0x01
2309 #define PORT_SPEED_4GB 0x03
2310 #define PORT_SPEED_8GB 0x04
2311 #define PORT_SPEED_10GB 0x13
2312 uint16_t link_data_rate; /* F/W operating speed */
2313
2314 uint8_t current_topology;
2315 uint8_t prev_topology;
2316 #define ISP_CFG_NL 1
2317 #define ISP_CFG_N 2
2318 #define ISP_CFG_FL 4
2319 #define ISP_CFG_F 8
2320
2321 uint8_t operating_mode; /* F/W operating mode */
2322 #define LOOP 0
2323 #define P2P 1
2324 #define LOOP_P2P 2
2325 #define P2P_LOOP 3
2326 uint8_t interrupts_on;
2327 uint32_t isp_abort_cnt;
2328
2329 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2330 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
2331 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
2332 uint32_t device_type;
2333 #define DT_ISP2100 BIT_0
2334 #define DT_ISP2200 BIT_1
2335 #define DT_ISP2300 BIT_2
2336 #define DT_ISP2312 BIT_3
2337 #define DT_ISP2322 BIT_4
2338 #define DT_ISP6312 BIT_5
2339 #define DT_ISP6322 BIT_6
2340 #define DT_ISP2422 BIT_7
2341 #define DT_ISP2432 BIT_8
2342 #define DT_ISP5422 BIT_9
2343 #define DT_ISP5432 BIT_10
2344 #define DT_ISP2532 BIT_11
2345 #define DT_ISP8432 BIT_12
2346 #define DT_ISP8001 BIT_13
2347 #define DT_ISP_LAST (DT_ISP8001 << 1)
2348
2349 #define DT_IIDMA BIT_26
2350 #define DT_FWI2 BIT_27
2351 #define DT_ZIO_SUPPORTED BIT_28
2352 #define DT_OEM_001 BIT_29
2353 #define DT_ISP2200A BIT_30
2354 #define DT_EXTENDED_IDS BIT_31
2355 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2356 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2357 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2358 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2359 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2360 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2361 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2362 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2363 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2364 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2365 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2366 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2367 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2368 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
2369 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
2370
2371 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2372 IS_QLA6312(ha) || IS_QLA6322(ha))
2373 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2374 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2375 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
2376 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
2377 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2378 IS_QLA84XX(ha))
2379 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
2380 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
2381 IS_QLA25XX(ha) || IS_QLA81XX(ha))
2382 #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && \
2383 (ha)->flags.msix_enabled)
2384
2385 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
2386 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
2387 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2388 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2389 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2390
2391 /* HBA serial number */
2392 uint8_t serial0;
2393 uint8_t serial1;
2394 uint8_t serial2;
2395
2396 /* NVRAM configuration data */
2397 #define MAX_NVRAM_SIZE 4096
2398 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
2399 uint16_t nvram_size;
2400 uint16_t nvram_base;
2401 void *nvram;
2402 uint16_t vpd_size;
2403 uint16_t vpd_base;
2404 void *vpd;
2405
2406 uint16_t loop_reset_delay;
2407 uint8_t retry_count;
2408 uint8_t login_timeout;
2409 uint16_t r_a_tov;
2410 int port_down_retry_count;
2411 uint8_t mbx_count;
2412
2413 uint32_t login_retry_count;
2414 /* SNS command interfaces. */
2415 ms_iocb_entry_t *ms_iocb;
2416 dma_addr_t ms_iocb_dma;
2417 struct ct_sns_pkt *ct_sns;
2418 dma_addr_t ct_sns_dma;
2419 /* SNS command interfaces for 2200. */
2420 struct sns_cmd_pkt *sns_cmd;
2421 dma_addr_t sns_cmd_dma;
2422
2423 #define SFP_DEV_SIZE 256
2424 #define SFP_BLOCK_SIZE 64
2425 void *sfp_data;
2426 dma_addr_t sfp_data_dma;
2427
2428 struct task_struct *dpc_thread;
2429 uint8_t dpc_active; /* DPC routine is active */
2430
2431 dma_addr_t gid_list_dma;
2432 struct gid_list_info *gid_list;
2433 int gid_list_info_size;
2434
2435 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2436 #define DMA_POOL_SIZE 256
2437 struct dma_pool *s_dma_pool;
2438
2439 dma_addr_t init_cb_dma;
2440 init_cb_t *init_cb;
2441 int init_cb_size;
2442
2443 /* These are used by mailbox operations. */
2444 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2445
2446 mbx_cmd_t *mcp;
2447 unsigned long mbx_cmd_flags;
2448 #define MBX_INTERRUPT 1
2449 #define MBX_INTR_WAIT 2
2450 #define MBX_UPDATE_FLASH_ACTIVE 3
2451
2452 struct mutex vport_lock; /* Virtual port synchronization */
2453 struct completion mbx_cmd_comp; /* Serialize mbx access */
2454 struct completion mbx_intr_comp; /* Used for completion notification */
2455
2456 uint32_t mbx_flags;
2457 #define MBX_IN_PROGRESS BIT_0
2458 #define MBX_BUSY BIT_1 /* Got the Access */
2459 #define MBX_SLEEPING_ON_SEM BIT_2
2460 #define MBX_POLLING_FOR_COMP BIT_3
2461 #define MBX_COMPLETED BIT_4
2462 #define MBX_TIMEDOUT BIT_5
2463 #define MBX_ACCESS_TIMEDOUT BIT_6
2464
2465 /* Basic firmware related information. */
2466 uint16_t fw_major_version;
2467 uint16_t fw_minor_version;
2468 uint16_t fw_subminor_version;
2469 uint16_t fw_attributes;
2470 uint32_t fw_memory_size;
2471 uint32_t fw_transfer_size;
2472 uint32_t fw_srisc_address;
2473 #define RISC_START_ADDRESS_2100 0x1000
2474 #define RISC_START_ADDRESS_2300 0x800
2475 #define RISC_START_ADDRESS_2400 0x100000
2476
2477 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2478 uint8_t fw_seriallink_options[4];
2479 uint16_t fw_seriallink_options24[4];
2480
2481 uint8_t mpi_version[4];
2482 uint32_t mpi_capabilities;
2483
2484 /* Firmware dump information. */
2485 struct qla2xxx_fw_dump *fw_dump;
2486 uint32_t fw_dump_len;
2487 int fw_dumped;
2488 int fw_dump_reading;
2489 dma_addr_t eft_dma;
2490 void *eft;
2491
2492 uint32_t chain_offset;
2493 struct dentry *dfs_dir;
2494 struct dentry *dfs_fce;
2495 dma_addr_t fce_dma;
2496 void *fce;
2497 uint32_t fce_bufs;
2498 uint16_t fce_mb[8];
2499 uint64_t fce_wr, fce_rd;
2500 struct mutex fce_mutex;
2501
2502 uint32_t pci_attr;
2503 uint16_t chip_revision;
2504
2505 uint16_t product_id[4];
2506
2507 uint8_t model_number[16+1];
2508 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2509 char model_desc[80];
2510 uint8_t adapter_id[16+1];
2511
2512 /* Option ROM information. */
2513 char *optrom_buffer;
2514 uint32_t optrom_size;
2515 int optrom_state;
2516 #define QLA_SWAITING 0
2517 #define QLA_SREADING 1
2518 #define QLA_SWRITING 2
2519 uint32_t optrom_region_start;
2520 uint32_t optrom_region_size;
2521
2522 /* PCI expansion ROM image information. */
2523 #define ROM_CODE_TYPE_BIOS 0
2524 #define ROM_CODE_TYPE_FCODE 1
2525 #define ROM_CODE_TYPE_EFI 3
2526 uint8_t bios_revision[2];
2527 uint8_t efi_revision[2];
2528 uint8_t fcode_revision[16];
2529 uint32_t fw_revision[4];
2530
2531 /* Offsets for flash/nvram access (set to ~0 if not used). */
2532 uint32_t flash_conf_off;
2533 uint32_t flash_data_off;
2534 uint32_t nvram_conf_off;
2535 uint32_t nvram_data_off;
2536
2537 uint32_t fdt_wrt_disable;
2538 uint32_t fdt_erase_cmd;
2539 uint32_t fdt_block_size;
2540 uint32_t fdt_unprotect_sec_cmd;
2541 uint32_t fdt_protect_sec_cmd;
2542
2543 uint32_t flt_region_flt;
2544 uint32_t flt_region_fdt;
2545 uint32_t flt_region_boot;
2546 uint32_t flt_region_fw;
2547 uint32_t flt_region_vpd_nvram;
2548 uint32_t flt_region_npiv_conf;
2549
2550 /* Needed for BEACON */
2551 uint16_t beacon_blink_led;
2552 uint8_t beacon_color_state;
2553 #define QLA_LED_GRN_ON 0x01
2554 #define QLA_LED_YLW_ON 0x02
2555 #define QLA_LED_ABR_ON 0x04
2556 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2557 /* ISP2322: red, green, amber. */
2558 uint16_t zio_mode;
2559 uint16_t zio_timer;
2560 struct fc_host_statistics fc_host_stat;
2561
2562 struct qla_msix_entry *msix_entries;
2563
2564 struct list_head vp_list; /* list of VP */
2565 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
2566 sizeof(unsigned long)];
2567 uint16_t num_vhosts; /* number of vports created */
2568 uint16_t num_vsans; /* number of vsan created */
2569 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
2570 int cur_vport_count;
2571
2572 struct qla_chip_state_84xx *cs84xx;
2573 struct qla_statistics qla_stats;
2574 struct isp_operations *isp_ops;
2575 };
2576
2577 /*
2578 * Qlogic scsi host structure
2579 */
2580 typedef struct scsi_qla_host {
2581 struct list_head list;
2582 struct list_head vp_fcports; /* list of fcports */
2583 struct list_head work_list;
2584 /* Commonly used flags and state information. */
2585 struct Scsi_Host *host;
2586 unsigned long host_no;
2587 uint8_t host_str[16];
2588
2589 volatile struct {
2590 uint32_t init_done :1;
2591 uint32_t online :1;
2592 uint32_t rscn_queue_overflow :1;
2593 uint32_t reset_active :1;
2594
2595 uint32_t management_server_logged_in :1;
2596 uint32_t process_response_queue :1;
2597 } flags;
2598
2599 atomic_t loop_state;
2600 #define LOOP_TIMEOUT 1
2601 #define LOOP_DOWN 2
2602 #define LOOP_UP 3
2603 #define LOOP_UPDATE 4
2604 #define LOOP_READY 5
2605 #define LOOP_DEAD 6
2606
2607 unsigned long dpc_flags;
2608 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2609 #define RESET_ACTIVE 1
2610 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2611 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2612 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2613 #define LOOP_RESYNC_ACTIVE 5
2614 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2615 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2616 #define MAILBOX_RETRY 8
2617 #define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2618 #define FAILOVER_EVENT_NEEDED 10
2619 #define FAILOVER_EVENT 11
2620 #define FAILOVER_NEEDED 12
2621 #define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2622 #define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2623 #define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2624 #define ABORT_QUEUES_NEEDED 16
2625 #define RELOGIN_NEEDED 17
2626 #define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2627 #define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2628 #define ISP_ABORT_RETRY 20 /* ISP aborted. */
2629 #define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2630 #define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
2631 #define IOCTL_ERROR_RECOVERY 23
2632 #define LOOP_RESET_NEEDED 24
2633 #define BEACON_BLINK_NEEDED 25
2634 #define REGISTER_FDMI_NEEDED 26
2635 #define FCPORT_UPDATE_NEEDED 27
2636 #define VP_DPC_NEEDED 28 /* wake up for VP dpc handling */
2637 #define UNLOADING 29
2638 #define NPIV_CONFIG_NEEDED 30
2639
2640 uint32_t device_flags;
2641 #define DFLG_LOCAL_DEVICES BIT_0
2642 #define DFLG_RETRY_LOCAL_DEVICES BIT_1
2643 #define DFLG_FABRIC_DEVICES BIT_2
2644 #define SWITCH_FOUND BIT_3
2645 #define DFLG_NO_CABLE BIT_4
2646
2647 srb_t *status_srb; /* Status continuation entry. */
2648
2649 /* ISP configuration data. */
2650 uint16_t loop_id; /* Host adapter loop id */
2651
2652 port_id_t d_id; /* Host adapter port id */
2653 uint8_t marker_needed;
2654 uint16_t mgmt_svr_loop_id;
2655
2656
2657
2658 /* RSCN queue. */
2659 uint32_t rscn_queue[MAX_RSCN_COUNT];
2660 uint8_t rscn_in_ptr;
2661 uint8_t rscn_out_ptr;
2662
2663 /* Timeout timers. */
2664 uint8_t loop_down_abort_time; /* port down timer */
2665 atomic_t loop_down_timer; /* loop down timer */
2666 uint8_t link_down_timeout; /* link down timeout */
2667
2668 uint32_t timer_active;
2669 struct timer_list timer;
2670
2671 uint8_t node_name[WWN_SIZE];
2672 uint8_t port_name[WWN_SIZE];
2673 uint8_t fabric_node_name[WWN_SIZE];
2674 uint32_t vp_abort_cnt;
2675
2676 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
2677 uint16_t vp_idx; /* vport ID */
2678
2679 unsigned long vp_flags;
2680 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
2681 #define VP_CREATE_NEEDED 1
2682 #define VP_BIND_NEEDED 2
2683 #define VP_DELETE_NEEDED 3
2684 #define VP_SCR_NEEDED 4 /* State Change Request registration */
2685 atomic_t vp_state;
2686 #define VP_OFFLINE 0
2687 #define VP_ACTIVE 1
2688 #define VP_FAILED 2
2689 // #define VP_DISABLE 3
2690 uint16_t vp_err_state;
2691 uint16_t vp_prev_err_state;
2692 #define VP_ERR_UNKWN 0
2693 #define VP_ERR_PORTDWN 1
2694 #define VP_ERR_FAB_UNSUPPORTED 2
2695 #define VP_ERR_FAB_NORESOURCES 3
2696 #define VP_ERR_FAB_LOGOUT 4
2697 #define VP_ERR_ADAP_NORESOURCES 5
2698 struct qla_hw_data *hw;
2699 int req_ques[QLA_MAX_HOST_QUES];
2700 } scsi_qla_host_t;
2701
2702 /*
2703 * Macros to help code, maintain, etc.
2704 */
2705 #define LOOP_TRANSITION(ha) \
2706 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2707 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2708 atomic_read(&ha->loop_state) == LOOP_DOWN)
2709
2710 #define qla_printk(level, ha, format, arg...) \
2711 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2712
2713 /*
2714 * qla2x00 local function return status codes
2715 */
2716 #define MBS_MASK 0x3fff
2717
2718 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2719 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2720 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2721 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2722 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2723 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2724 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2725 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2726 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2727 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2728
2729 #define QLA_FUNCTION_TIMEOUT 0x100
2730 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2731 #define QLA_FUNCTION_FAILED 0x102
2732 #define QLA_MEMORY_ALLOC_FAILED 0x103
2733 #define QLA_LOCK_TIMEOUT 0x104
2734 #define QLA_ABORTED 0x105
2735 #define QLA_SUSPENDED 0x106
2736 #define QLA_BUSY 0x107
2737 #define QLA_RSCNS_HANDLED 0x108
2738 #define QLA_ALREADY_REGISTERED 0x109
2739
2740 #define NVRAM_DELAY() udelay(10)
2741
2742 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2743
2744 /*
2745 * Flash support definitions
2746 */
2747 #define OPTROM_SIZE_2300 0x20000
2748 #define OPTROM_SIZE_2322 0x100000
2749 #define OPTROM_SIZE_24XX 0x100000
2750 #define OPTROM_SIZE_25XX 0x200000
2751 #define OPTROM_SIZE_81XX 0x400000
2752
2753 #include "qla_gbl.h"
2754 #include "qla_dbg.h"
2755 #include "qla_inline.h"
2756
2757 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2758 #define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2759 #define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2760 #define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2761 #define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2762 #define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2763
2764 #endif
Linux kernel - Deliverables
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