projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_def.h
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_transport_fc.h>
34
35 #define QLA2XXX_DRIVER_NAME "qla2xxx"
36
37 /*
38 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
39 * but that's fine as we don't look at the last 24 ones for
40 * ISP2100 HBAs.
41 */
42 #define MAILBOX_REGISTER_COUNT_2100 8
43 #define MAILBOX_REGISTER_COUNT 32
44
45 #define QLA2200A_RISC_ROM_VER 4
46 #define FPM_2300 6
47 #define FPM_2310 7
48
49 #include "qla_settings.h"
50
51 /*
52 * Data bit definitions
53 */
54 #define BIT_0 0x1
55 #define BIT_1 0x2
56 #define BIT_2 0x4
57 #define BIT_3 0x8
58 #define BIT_4 0x10
59 #define BIT_5 0x20
60 #define BIT_6 0x40
61 #define BIT_7 0x80
62 #define BIT_8 0x100
63 #define BIT_9 0x200
64 #define BIT_10 0x400
65 #define BIT_11 0x800
66 #define BIT_12 0x1000
67 #define BIT_13 0x2000
68 #define BIT_14 0x4000
69 #define BIT_15 0x8000
70 #define BIT_16 0x10000
71 #define BIT_17 0x20000
72 #define BIT_18 0x40000
73 #define BIT_19 0x80000
74 #define BIT_20 0x100000
75 #define BIT_21 0x200000
76 #define BIT_22 0x400000
77 #define BIT_23 0x800000
78 #define BIT_24 0x1000000
79 #define BIT_25 0x2000000
80 #define BIT_26 0x4000000
81 #define BIT_27 0x8000000
82 #define BIT_28 0x10000000
83 #define BIT_29 0x20000000
84 #define BIT_30 0x40000000
85 #define BIT_31 0x80000000
86
87 #define LSB(x) ((uint8_t)(x))
88 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
89
90 #define LSW(x) ((uint16_t)(x))
91 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
92
93 #define LSD(x) ((uint32_t)((uint64_t)(x)))
94 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
95
96
97 /*
98 * I/O register
99 */
100
101 #define RD_REG_BYTE(addr) readb(addr)
102 #define RD_REG_WORD(addr) readw(addr)
103 #define RD_REG_DWORD(addr) readl(addr)
104 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
105 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
106 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
107 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
108 #define WRT_REG_WORD(addr, data) writew(data,addr)
109 #define WRT_REG_DWORD(addr, data) writel(data,addr)
110
111 /*
112 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
113 * 133Mhz slot.
114 */
115 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
116 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
117
118 /*
119 * Fibre Channel device definitions.
120 */
121 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
122 #define MAX_FIBRE_DEVICES 512
123 #define MAX_FIBRE_LUNS 0xFFFF
124 #define MAX_RSCN_COUNT 32
125 #define MAX_HOST_COUNT 16
126
127 /*
128 * Host adapter default definitions.
129 */
130 #define MAX_BUSES 1 /* We only have one bus today */
131 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
132 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
133 #define MIN_LUNS 8
134 #define MAX_LUNS MAX_FIBRE_LUNS
135 #define MAX_CMDS_PER_LUN 255
136
137 /*
138 * Fibre Channel device definitions.
139 */
140 #define SNS_LAST_LOOP_ID_2100 0xfe
141 #define SNS_LAST_LOOP_ID_2300 0x7ff
142
143 #define LAST_LOCAL_LOOP_ID 0x7d
144 #define SNS_FL_PORT 0x7e
145 #define FABRIC_CONTROLLER 0x7f
146 #define SIMPLE_NAME_SERVER 0x80
147 #define SNS_FIRST_LOOP_ID 0x81
148 #define MANAGEMENT_SERVER 0xfe
149 #define BROADCAST 0xff
150
151 /*
152 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
153 * valid range of an N-PORT id is 0 through 0x7ef.
154 */
155 #define NPH_LAST_HANDLE 0x7ef
156 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
157 #define NPH_SNS 0x7fc /* FFFFFC */
158 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
159 #define NPH_F_PORT 0x7fe /* FFFFFE */
160 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
161
162 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
163 #include "qla_fw.h"
164
165 /*
166 * Timeout timer counts in seconds
167 */
168 #define PORT_RETRY_TIME 1
169 #define LOOP_DOWN_TIMEOUT 60
170 #define LOOP_DOWN_TIME 255 /* 240 */
171 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
172
173 /* Maximum outstanding commands in ISP queues (1-65535) */
174 #define MAX_OUTSTANDING_COMMANDS 1024
175
176 /* ISP request and response entry counts (37-65535) */
177 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
178 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
179 #define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
180 #define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
181 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
182 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
183
184 struct req_que;
185
186 /*
187 * SCSI Request Block
188 */
189 typedef struct srb {
190 struct scsi_qla_host *vha; /* HA the SP is queued on */
191 struct req_que *que;
192 struct fc_port *fcport;
193
194 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
195
196 uint16_t flags;
197
198 uint32_t request_sense_length;
199 uint8_t *request_sense_ptr;
200 } srb_t;
201
202 /*
203 * SRB flag definitions
204 */
205 #define SRB_TIMEOUT BIT_0 /* Command timed out */
206 #define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
207 #define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
208 #define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
209
210 #define SRB_ABORTED BIT_4 /* Command aborted command already */
211 #define SRB_RETRY BIT_5 /* Command needs retrying */
212 #define SRB_GOT_SENSE BIT_6 /* Command has sense data */
213 #define SRB_FAILOVER BIT_7 /* Command in failover state */
214
215 #define SRB_BUSY BIT_8 /* Command is in busy retry state */
216 #define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
217 #define SRB_IOCTL BIT_10 /* IOCTL command. */
218 #define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
219
220 /*
221 * ISP I/O Register Set structure definitions.
222 */
223 struct device_reg_2xxx {
224 uint16_t flash_address; /* Flash BIOS address */
225 uint16_t flash_data; /* Flash BIOS data */
226 uint16_t unused_1[1]; /* Gap */
227 uint16_t ctrl_status; /* Control/Status */
228 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
229 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
230 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
231
232 uint16_t ictrl; /* Interrupt control */
233 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
234 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
235
236 uint16_t istatus; /* Interrupt status */
237 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
238
239 uint16_t semaphore; /* Semaphore */
240 uint16_t nvram; /* NVRAM register. */
241 #define NVR_DESELECT 0
242 #define NVR_BUSY BIT_15
243 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
244 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
245 #define NVR_DATA_IN BIT_3
246 #define NVR_DATA_OUT BIT_2
247 #define NVR_SELECT BIT_1
248 #define NVR_CLOCK BIT_0
249
250 #define NVR_WAIT_CNT 20000
251
252 union {
253 struct {
254 uint16_t mailbox0;
255 uint16_t mailbox1;
256 uint16_t mailbox2;
257 uint16_t mailbox3;
258 uint16_t mailbox4;
259 uint16_t mailbox5;
260 uint16_t mailbox6;
261 uint16_t mailbox7;
262 uint16_t unused_2[59]; /* Gap */
263 } __attribute__((packed)) isp2100;
264 struct {
265 /* Request Queue */
266 uint16_t req_q_in; /* In-Pointer */
267 uint16_t req_q_out; /* Out-Pointer */
268 /* Response Queue */
269 uint16_t rsp_q_in; /* In-Pointer */
270 uint16_t rsp_q_out; /* Out-Pointer */
271
272 /* RISC to Host Status */
273 uint32_t host_status;
274 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
275 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
276
277 /* Host to Host Semaphore */
278 uint16_t host_semaphore;
279 uint16_t unused_3[17]; /* Gap */
280 uint16_t mailbox0;
281 uint16_t mailbox1;
282 uint16_t mailbox2;
283 uint16_t mailbox3;
284 uint16_t mailbox4;
285 uint16_t mailbox5;
286 uint16_t mailbox6;
287 uint16_t mailbox7;
288 uint16_t mailbox8;
289 uint16_t mailbox9;
290 uint16_t mailbox10;
291 uint16_t mailbox11;
292 uint16_t mailbox12;
293 uint16_t mailbox13;
294 uint16_t mailbox14;
295 uint16_t mailbox15;
296 uint16_t mailbox16;
297 uint16_t mailbox17;
298 uint16_t mailbox18;
299 uint16_t mailbox19;
300 uint16_t mailbox20;
301 uint16_t mailbox21;
302 uint16_t mailbox22;
303 uint16_t mailbox23;
304 uint16_t mailbox24;
305 uint16_t mailbox25;
306 uint16_t mailbox26;
307 uint16_t mailbox27;
308 uint16_t mailbox28;
309 uint16_t mailbox29;
310 uint16_t mailbox30;
311 uint16_t mailbox31;
312 uint16_t fb_cmd;
313 uint16_t unused_4[10]; /* Gap */
314 } __attribute__((packed)) isp2300;
315 } u;
316
317 uint16_t fpm_diag_config;
318 uint16_t unused_5[0x4]; /* Gap */
319 uint16_t risc_hw;
320 uint16_t unused_5_1; /* Gap */
321 uint16_t pcr; /* Processor Control Register. */
322 uint16_t unused_6[0x5]; /* Gap */
323 uint16_t mctr; /* Memory Configuration and Timing. */
324 uint16_t unused_7[0x3]; /* Gap */
325 uint16_t fb_cmd_2100; /* Unused on 23XX */
326 uint16_t unused_8[0x3]; /* Gap */
327 uint16_t hccr; /* Host command & control register. */
328 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
329 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
330 /* HCCR commands */
331 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
332 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
333 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
334 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
335 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
336 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
337 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
338 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
339
340 uint16_t unused_9[5]; /* Gap */
341 uint16_t gpiod; /* GPIO Data register. */
342 uint16_t gpioe; /* GPIO Enable register. */
343 #define GPIO_LED_MASK 0x00C0
344 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
345 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
346 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
347 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
348 #define GPIO_LED_ALL_OFF 0x0000
349 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
350 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
351
352 union {
353 struct {
354 uint16_t unused_10[8]; /* Gap */
355 uint16_t mailbox8;
356 uint16_t mailbox9;
357 uint16_t mailbox10;
358 uint16_t mailbox11;
359 uint16_t mailbox12;
360 uint16_t mailbox13;
361 uint16_t mailbox14;
362 uint16_t mailbox15;
363 uint16_t mailbox16;
364 uint16_t mailbox17;
365 uint16_t mailbox18;
366 uint16_t mailbox19;
367 uint16_t mailbox20;
368 uint16_t mailbox21;
369 uint16_t mailbox22;
370 uint16_t mailbox23; /* Also probe reg. */
371 } __attribute__((packed)) isp2200;
372 } u_end;
373 };
374
375 struct device_reg_25xxmq {
376 volatile uint32_t req_q_in;
377 volatile uint32_t req_q_out;
378 volatile uint32_t rsp_q_in;
379 volatile uint32_t rsp_q_out;
380 };
381
382 typedef union {
383 struct device_reg_2xxx isp;
384 struct device_reg_24xx isp24;
385 struct device_reg_25xxmq isp25mq;
386 } device_reg_t;
387
388 #define ISP_REQ_Q_IN(ha, reg) \
389 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
390 &(reg)->u.isp2100.mailbox4 : \
391 &(reg)->u.isp2300.req_q_in)
392 #define ISP_REQ_Q_OUT(ha, reg) \
393 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
394 &(reg)->u.isp2100.mailbox4 : \
395 &(reg)->u.isp2300.req_q_out)
396 #define ISP_RSP_Q_IN(ha, reg) \
397 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
398 &(reg)->u.isp2100.mailbox5 : \
399 &(reg)->u.isp2300.rsp_q_in)
400 #define ISP_RSP_Q_OUT(ha, reg) \
401 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
402 &(reg)->u.isp2100.mailbox5 : \
403 &(reg)->u.isp2300.rsp_q_out)
404
405 #define MAILBOX_REG(ha, reg, num) \
406 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
407 (num < 8 ? \
408 &(reg)->u.isp2100.mailbox0 + (num) : \
409 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
410 &(reg)->u.isp2300.mailbox0 + (num))
411 #define RD_MAILBOX_REG(ha, reg, num) \
412 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
413 #define WRT_MAILBOX_REG(ha, reg, num, data) \
414 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
415
416 #define FB_CMD_REG(ha, reg) \
417 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
418 &(reg)->fb_cmd_2100 : \
419 &(reg)->u.isp2300.fb_cmd)
420 #define RD_FB_CMD_REG(ha, reg) \
421 RD_REG_WORD(FB_CMD_REG(ha, reg))
422 #define WRT_FB_CMD_REG(ha, reg, data) \
423 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
424
425 typedef struct {
426 uint32_t out_mb; /* outbound from driver */
427 uint32_t in_mb; /* Incoming from RISC */
428 uint16_t mb[MAILBOX_REGISTER_COUNT];
429 long buf_size;
430 void *bufp;
431 uint32_t tov;
432 uint8_t flags;
433 #define MBX_DMA_IN BIT_0
434 #define MBX_DMA_OUT BIT_1
435 #define IOCTL_CMD BIT_2
436 } mbx_cmd_t;
437
438 #define MBX_TOV_SECONDS 30
439
440 /*
441 * ISP product identification definitions in mailboxes after reset.
442 */
443 #define PROD_ID_1 0x4953
444 #define PROD_ID_2 0x0000
445 #define PROD_ID_2a 0x5020
446 #define PROD_ID_3 0x2020
447
448 /*
449 * ISP mailbox Self-Test status codes
450 */
451 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
452 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
453 #define MBS_BUSY 4 /* Busy. */
454
455 /*
456 * ISP mailbox command complete status codes
457 */
458 #define MBS_COMMAND_COMPLETE 0x4000
459 #define MBS_INVALID_COMMAND 0x4001
460 #define MBS_HOST_INTERFACE_ERROR 0x4002
461 #define MBS_TEST_FAILED 0x4003
462 #define MBS_COMMAND_ERROR 0x4005
463 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
464 #define MBS_PORT_ID_USED 0x4007
465 #define MBS_LOOP_ID_USED 0x4008
466 #define MBS_ALL_IDS_IN_USE 0x4009
467 #define MBS_NOT_LOGGED_IN 0x400A
468 #define MBS_LINK_DOWN_ERROR 0x400B
469 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
470
471 /*
472 * ISP mailbox asynchronous event status codes
473 */
474 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
475 #define MBA_RESET 0x8001 /* Reset Detected. */
476 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
477 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
478 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
479 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
480 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
481 /* occurred. */
482 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
483 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
484 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
485 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
486 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
487 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
488 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
489 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
490 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
491 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
492 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
493 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
494 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
495 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
496 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
497 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
498 /* used. */
499 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
500 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
501 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
502 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
503 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
504 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
505 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
506 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
507 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
508 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
509 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
510 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
511 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
512 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
513
514 /*
515 * Firmware options 1, 2, 3.
516 */
517 #define FO1_AE_ON_LIPF8 BIT_0
518 #define FO1_AE_ALL_LIP_RESET BIT_1
519 #define FO1_CTIO_RETRY BIT_3
520 #define FO1_DISABLE_LIP_F7_SW BIT_4
521 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
522 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
523 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
524 #define FO1_SET_EMPHASIS_SWING BIT_8
525 #define FO1_AE_AUTO_BYPASS BIT_9
526 #define FO1_ENABLE_PURE_IOCB BIT_10
527 #define FO1_AE_PLOGI_RJT BIT_11
528 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
529 #define FO1_AE_QUEUE_FULL BIT_13
530
531 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
532 #define FO2_REV_LOOPBACK BIT_1
533
534 #define FO3_ENABLE_EMERG_IOCB BIT_0
535 #define FO3_AE_RND_ERROR BIT_1
536
537 /* 24XX additional firmware options */
538 #define ADD_FO_COUNT 3
539 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
540 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
541
542 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
543
544 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
545
546 /*
547 * ISP mailbox commands
548 */
549 #define MBC_LOAD_RAM 1 /* Load RAM. */
550 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
551 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
552 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
553 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
554 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
555 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
556 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
557 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
558 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
559 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
560 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
561 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
562 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
563 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
564 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
565 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
566 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
567 #define MBC_RESET 0x18 /* Reset. */
568 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
569 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
570 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
571 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
572 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
573 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
574 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
575 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
576 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
577 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
578 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
579 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
580 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
581 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
582 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
583 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
584 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
585 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
586 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
587 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
588 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
589 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
590 /* Initialization Procedure */
591 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
592 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
593 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
594 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
595 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
596 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
597 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
598 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
599 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
600 #define MBC_LIP_RESET 0x6c /* LIP reset. */
601 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
602 /* commandd. */
603 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
604 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
605 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
606 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
607 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
608 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
609 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
610 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
611 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
612 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
613 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
614
615 /*
616 * ISP24xx mailbox commands
617 */
618 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
619 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
620 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
621 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
622 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
623 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
624 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
625 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
626 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
627 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
628 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
629 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
630 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
631 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
632 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
633
634 /* Firmware return data sizes */
635 #define FCAL_MAP_SIZE 128
636
637 /* Mailbox bit definitions for out_mb and in_mb */
638 #define MBX_31 BIT_31
639 #define MBX_30 BIT_30
640 #define MBX_29 BIT_29
641 #define MBX_28 BIT_28
642 #define MBX_27 BIT_27
643 #define MBX_26 BIT_26
644 #define MBX_25 BIT_25
645 #define MBX_24 BIT_24
646 #define MBX_23 BIT_23
647 #define MBX_22 BIT_22
648 #define MBX_21 BIT_21
649 #define MBX_20 BIT_20
650 #define MBX_19 BIT_19
651 #define MBX_18 BIT_18
652 #define MBX_17 BIT_17
653 #define MBX_16 BIT_16
654 #define MBX_15 BIT_15
655 #define MBX_14 BIT_14
656 #define MBX_13 BIT_13
657 #define MBX_12 BIT_12
658 #define MBX_11 BIT_11
659 #define MBX_10 BIT_10
660 #define MBX_9 BIT_9
661 #define MBX_8 BIT_8
662 #define MBX_7 BIT_7
663 #define MBX_6 BIT_6
664 #define MBX_5 BIT_5
665 #define MBX_4 BIT_4
666 #define MBX_3 BIT_3
667 #define MBX_2 BIT_2
668 #define MBX_1 BIT_1
669 #define MBX_0 BIT_0
670
671 /*
672 * Firmware state codes from get firmware state mailbox command
673 */
674 #define FSTATE_CONFIG_WAIT 0
675 #define FSTATE_WAIT_AL_PA 1
676 #define FSTATE_WAIT_LOGIN 2
677 #define FSTATE_READY 3
678 #define FSTATE_LOSS_OF_SYNC 4
679 #define FSTATE_ERROR 5
680 #define FSTATE_REINIT 6
681 #define FSTATE_NON_PART 7
682
683 #define FSTATE_CONFIG_CORRECT 0
684 #define FSTATE_P2P_RCV_LIP 1
685 #define FSTATE_P2P_CHOOSE_LOOP 2
686 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
687 #define FSTATE_FATAL_ERROR 4
688 #define FSTATE_LOOP_BACK_CONN 5
689
690 /*
691 * Port Database structure definition
692 * Little endian except where noted.
693 */
694 #define PORT_DATABASE_SIZE 128 /* bytes */
695 typedef struct {
696 uint8_t options;
697 uint8_t control;
698 uint8_t master_state;
699 uint8_t slave_state;
700 uint8_t reserved[2];
701 uint8_t hard_address;
702 uint8_t reserved_1;
703 uint8_t port_id[4];
704 uint8_t node_name[WWN_SIZE];
705 uint8_t port_name[WWN_SIZE];
706 uint16_t execution_throttle;
707 uint16_t execution_count;
708 uint8_t reset_count;
709 uint8_t reserved_2;
710 uint16_t resource_allocation;
711 uint16_t current_allocation;
712 uint16_t queue_head;
713 uint16_t queue_tail;
714 uint16_t transmit_execution_list_next;
715 uint16_t transmit_execution_list_previous;
716 uint16_t common_features;
717 uint16_t total_concurrent_sequences;
718 uint16_t RO_by_information_category;
719 uint8_t recipient;
720 uint8_t initiator;
721 uint16_t receive_data_size;
722 uint16_t concurrent_sequences;
723 uint16_t open_sequences_per_exchange;
724 uint16_t lun_abort_flags;
725 uint16_t lun_stop_flags;
726 uint16_t stop_queue_head;
727 uint16_t stop_queue_tail;
728 uint16_t port_retry_timer;
729 uint16_t next_sequence_id;
730 uint16_t frame_count;
731 uint16_t PRLI_payload_length;
732 uint8_t prli_svc_param_word_0[2]; /* Big endian */
733 /* Bits 15-0 of word 0 */
734 uint8_t prli_svc_param_word_3[2]; /* Big endian */
735 /* Bits 15-0 of word 3 */
736 uint16_t loop_id;
737 uint16_t extended_lun_info_list_pointer;
738 uint16_t extended_lun_stop_list_pointer;
739 } port_database_t;
740
741 /*
742 * Port database slave/master states
743 */
744 #define PD_STATE_DISCOVERY 0
745 #define PD_STATE_WAIT_DISCOVERY_ACK 1
746 #define PD_STATE_PORT_LOGIN 2
747 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
748 #define PD_STATE_PROCESS_LOGIN 4
749 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
750 #define PD_STATE_PORT_LOGGED_IN 6
751 #define PD_STATE_PORT_UNAVAILABLE 7
752 #define PD_STATE_PROCESS_LOGOUT 8
753 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
754 #define PD_STATE_PORT_LOGOUT 10
755 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
756
757
758 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
759 #define QLA_ZIO_DISABLED 0
760 #define QLA_ZIO_DEFAULT_TIMER 2
761
762 /*
763 * ISP Initialization Control Block.
764 * Little endian except where noted.
765 */
766 #define ICB_VERSION 1
767 typedef struct {
768 uint8_t version;
769 uint8_t reserved_1;
770
771 /*
772 * LSB BIT 0 = Enable Hard Loop Id
773 * LSB BIT 1 = Enable Fairness
774 * LSB BIT 2 = Enable Full-Duplex
775 * LSB BIT 3 = Enable Fast Posting
776 * LSB BIT 4 = Enable Target Mode
777 * LSB BIT 5 = Disable Initiator Mode
778 * LSB BIT 6 = Enable ADISC
779 * LSB BIT 7 = Enable Target Inquiry Data
780 *
781 * MSB BIT 0 = Enable PDBC Notify
782 * MSB BIT 1 = Non Participating LIP
783 * MSB BIT 2 = Descending Loop ID Search
784 * MSB BIT 3 = Acquire Loop ID in LIPA
785 * MSB BIT 4 = Stop PortQ on Full Status
786 * MSB BIT 5 = Full Login after LIP
787 * MSB BIT 6 = Node Name Option
788 * MSB BIT 7 = Ext IFWCB enable bit
789 */
790 uint8_t firmware_options[2];
791
792 uint16_t frame_payload_size;
793 uint16_t max_iocb_allocation;
794 uint16_t execution_throttle;
795 uint8_t retry_count;
796 uint8_t retry_delay; /* unused */
797 uint8_t port_name[WWN_SIZE]; /* Big endian. */
798 uint16_t hard_address;
799 uint8_t inquiry_data;
800 uint8_t login_timeout;
801 uint8_t node_name[WWN_SIZE]; /* Big endian. */
802
803 uint16_t request_q_outpointer;
804 uint16_t response_q_inpointer;
805 uint16_t request_q_length;
806 uint16_t response_q_length;
807 uint32_t request_q_address[2];
808 uint32_t response_q_address[2];
809
810 uint16_t lun_enables;
811 uint8_t command_resource_count;
812 uint8_t immediate_notify_resource_count;
813 uint16_t timeout;
814 uint8_t reserved_2[2];
815
816 /*
817 * LSB BIT 0 = Timer Operation mode bit 0
818 * LSB BIT 1 = Timer Operation mode bit 1
819 * LSB BIT 2 = Timer Operation mode bit 2
820 * LSB BIT 3 = Timer Operation mode bit 3
821 * LSB BIT 4 = Init Config Mode bit 0
822 * LSB BIT 5 = Init Config Mode bit 1
823 * LSB BIT 6 = Init Config Mode bit 2
824 * LSB BIT 7 = Enable Non part on LIHA failure
825 *
826 * MSB BIT 0 = Enable class 2
827 * MSB BIT 1 = Enable ACK0
828 * MSB BIT 2 =
829 * MSB BIT 3 =
830 * MSB BIT 4 = FC Tape Enable
831 * MSB BIT 5 = Enable FC Confirm
832 * MSB BIT 6 = Enable command queuing in target mode
833 * MSB BIT 7 = No Logo On Link Down
834 */
835 uint8_t add_firmware_options[2];
836
837 uint8_t response_accumulation_timer;
838 uint8_t interrupt_delay_timer;
839
840 /*
841 * LSB BIT 0 = Enable Read xfr_rdy
842 * LSB BIT 1 = Soft ID only
843 * LSB BIT 2 =
844 * LSB BIT 3 =
845 * LSB BIT 4 = FCP RSP Payload [0]
846 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
847 * LSB BIT 6 = Enable Out-of-Order frame handling
848 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
849 *
850 * MSB BIT 0 = Sbus enable - 2300
851 * MSB BIT 1 =
852 * MSB BIT 2 =
853 * MSB BIT 3 =
854 * MSB BIT 4 = LED mode
855 * MSB BIT 5 = enable 50 ohm termination
856 * MSB BIT 6 = Data Rate (2300 only)
857 * MSB BIT 7 = Data Rate (2300 only)
858 */
859 uint8_t special_options[2];
860
861 uint8_t reserved_3[26];
862 } init_cb_t;
863
864 /*
865 * Get Link Status mailbox command return buffer.
866 */
867 #define GLSO_SEND_RPS BIT_0
868 #define GLSO_USE_DID BIT_3
869
870 struct link_statistics {
871 uint32_t link_fail_cnt;
872 uint32_t loss_sync_cnt;
873 uint32_t loss_sig_cnt;
874 uint32_t prim_seq_err_cnt;
875 uint32_t inval_xmit_word_cnt;
876 uint32_t inval_crc_cnt;
877 uint32_t lip_cnt;
878 uint32_t unused1[0x1a];
879 uint32_t tx_frames;
880 uint32_t rx_frames;
881 uint32_t dumped_frames;
882 uint32_t unused2[2];
883 uint32_t nos_rcvd;
884 };
885
886 /*
887 * NVRAM Command values.
888 */
889 #define NV_START_BIT BIT_2
890 #define NV_WRITE_OP (BIT_26+BIT_24)
891 #define NV_READ_OP (BIT_26+BIT_25)
892 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
893 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
894 #define NV_DELAY_COUNT 10
895
896 /*
897 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
898 */
899 typedef struct {
900 /*
901 * NVRAM header
902 */
903 uint8_t id[4];
904 uint8_t nvram_version;
905 uint8_t reserved_0;
906
907 /*
908 * NVRAM RISC parameter block
909 */
910 uint8_t parameter_block_version;
911 uint8_t reserved_1;
912
913 /*
914 * LSB BIT 0 = Enable Hard Loop Id
915 * LSB BIT 1 = Enable Fairness
916 * LSB BIT 2 = Enable Full-Duplex
917 * LSB BIT 3 = Enable Fast Posting
918 * LSB BIT 4 = Enable Target Mode
919 * LSB BIT 5 = Disable Initiator Mode
920 * LSB BIT 6 = Enable ADISC
921 * LSB BIT 7 = Enable Target Inquiry Data
922 *
923 * MSB BIT 0 = Enable PDBC Notify
924 * MSB BIT 1 = Non Participating LIP
925 * MSB BIT 2 = Descending Loop ID Search
926 * MSB BIT 3 = Acquire Loop ID in LIPA
927 * MSB BIT 4 = Stop PortQ on Full Status
928 * MSB BIT 5 = Full Login after LIP
929 * MSB BIT 6 = Node Name Option
930 * MSB BIT 7 = Ext IFWCB enable bit
931 */
932 uint8_t firmware_options[2];
933
934 uint16_t frame_payload_size;
935 uint16_t max_iocb_allocation;
936 uint16_t execution_throttle;
937 uint8_t retry_count;
938 uint8_t retry_delay; /* unused */
939 uint8_t port_name[WWN_SIZE]; /* Big endian. */
940 uint16_t hard_address;
941 uint8_t inquiry_data;
942 uint8_t login_timeout;
943 uint8_t node_name[WWN_SIZE]; /* Big endian. */
944
945 /*
946 * LSB BIT 0 = Timer Operation mode bit 0
947 * LSB BIT 1 = Timer Operation mode bit 1
948 * LSB BIT 2 = Timer Operation mode bit 2
949 * LSB BIT 3 = Timer Operation mode bit 3
950 * LSB BIT 4 = Init Config Mode bit 0
951 * LSB BIT 5 = Init Config Mode bit 1
952 * LSB BIT 6 = Init Config Mode bit 2
953 * LSB BIT 7 = Enable Non part on LIHA failure
954 *
955 * MSB BIT 0 = Enable class 2
956 * MSB BIT 1 = Enable ACK0
957 * MSB BIT 2 =
958 * MSB BIT 3 =
959 * MSB BIT 4 = FC Tape Enable
960 * MSB BIT 5 = Enable FC Confirm
961 * MSB BIT 6 = Enable command queuing in target mode
962 * MSB BIT 7 = No Logo On Link Down
963 */
964 uint8_t add_firmware_options[2];
965
966 uint8_t response_accumulation_timer;
967 uint8_t interrupt_delay_timer;
968
969 /*
970 * LSB BIT 0 = Enable Read xfr_rdy
971 * LSB BIT 1 = Soft ID only
972 * LSB BIT 2 =
973 * LSB BIT 3 =
974 * LSB BIT 4 = FCP RSP Payload [0]
975 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
976 * LSB BIT 6 = Enable Out-of-Order frame handling
977 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
978 *
979 * MSB BIT 0 = Sbus enable - 2300
980 * MSB BIT 1 =
981 * MSB BIT 2 =
982 * MSB BIT 3 =
983 * MSB BIT 4 = LED mode
984 * MSB BIT 5 = enable 50 ohm termination
985 * MSB BIT 6 = Data Rate (2300 only)
986 * MSB BIT 7 = Data Rate (2300 only)
987 */
988 uint8_t special_options[2];
989
990 /* Reserved for expanded RISC parameter block */
991 uint8_t reserved_2[22];
992
993 /*
994 * LSB BIT 0 = Tx Sensitivity 1G bit 0
995 * LSB BIT 1 = Tx Sensitivity 1G bit 1
996 * LSB BIT 2 = Tx Sensitivity 1G bit 2
997 * LSB BIT 3 = Tx Sensitivity 1G bit 3
998 * LSB BIT 4 = Rx Sensitivity 1G bit 0
999 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1000 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1001 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1002 *
1003 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1004 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1005 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1006 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1007 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1008 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1009 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1010 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1011 *
1012 * LSB BIT 0 = Output Swing 1G bit 0
1013 * LSB BIT 1 = Output Swing 1G bit 1
1014 * LSB BIT 2 = Output Swing 1G bit 2
1015 * LSB BIT 3 = Output Emphasis 1G bit 0
1016 * LSB BIT 4 = Output Emphasis 1G bit 1
1017 * LSB BIT 5 = Output Swing 2G bit 0
1018 * LSB BIT 6 = Output Swing 2G bit 1
1019 * LSB BIT 7 = Output Swing 2G bit 2
1020 *
1021 * MSB BIT 0 = Output Emphasis 2G bit 0
1022 * MSB BIT 1 = Output Emphasis 2G bit 1
1023 * MSB BIT 2 = Output Enable
1024 * MSB BIT 3 =
1025 * MSB BIT 4 =
1026 * MSB BIT 5 =
1027 * MSB BIT 6 =
1028 * MSB BIT 7 =
1029 */
1030 uint8_t seriallink_options[4];
1031
1032 /*
1033 * NVRAM host parameter block
1034 *
1035 * LSB BIT 0 = Enable spinup delay
1036 * LSB BIT 1 = Disable BIOS
1037 * LSB BIT 2 = Enable Memory Map BIOS
1038 * LSB BIT 3 = Enable Selectable Boot
1039 * LSB BIT 4 = Disable RISC code load
1040 * LSB BIT 5 = Set cache line size 1
1041 * LSB BIT 6 = PCI Parity Disable
1042 * LSB BIT 7 = Enable extended logging
1043 *
1044 * MSB BIT 0 = Enable 64bit addressing
1045 * MSB BIT 1 = Enable lip reset
1046 * MSB BIT 2 = Enable lip full login
1047 * MSB BIT 3 = Enable target reset
1048 * MSB BIT 4 = Enable database storage
1049 * MSB BIT 5 = Enable cache flush read
1050 * MSB BIT 6 = Enable database load
1051 * MSB BIT 7 = Enable alternate WWN
1052 */
1053 uint8_t host_p[2];
1054
1055 uint8_t boot_node_name[WWN_SIZE];
1056 uint8_t boot_lun_number;
1057 uint8_t reset_delay;
1058 uint8_t port_down_retry_count;
1059 uint8_t boot_id_number;
1060 uint16_t max_luns_per_target;
1061 uint8_t fcode_boot_port_name[WWN_SIZE];
1062 uint8_t alternate_port_name[WWN_SIZE];
1063 uint8_t alternate_node_name[WWN_SIZE];
1064
1065 /*
1066 * BIT 0 = Selective Login
1067 * BIT 1 = Alt-Boot Enable
1068 * BIT 2 =
1069 * BIT 3 = Boot Order List
1070 * BIT 4 =
1071 * BIT 5 = Selective LUN
1072 * BIT 6 =
1073 * BIT 7 = unused
1074 */
1075 uint8_t efi_parameters;
1076
1077 uint8_t link_down_timeout;
1078
1079 uint8_t adapter_id[16];
1080
1081 uint8_t alt1_boot_node_name[WWN_SIZE];
1082 uint16_t alt1_boot_lun_number;
1083 uint8_t alt2_boot_node_name[WWN_SIZE];
1084 uint16_t alt2_boot_lun_number;
1085 uint8_t alt3_boot_node_name[WWN_SIZE];
1086 uint16_t alt3_boot_lun_number;
1087 uint8_t alt4_boot_node_name[WWN_SIZE];
1088 uint16_t alt4_boot_lun_number;
1089 uint8_t alt5_boot_node_name[WWN_SIZE];
1090 uint16_t alt5_boot_lun_number;
1091 uint8_t alt6_boot_node_name[WWN_SIZE];
1092 uint16_t alt6_boot_lun_number;
1093 uint8_t alt7_boot_node_name[WWN_SIZE];
1094 uint16_t alt7_boot_lun_number;
1095
1096 uint8_t reserved_3[2];
1097
1098 /* Offset 200-215 : Model Number */
1099 uint8_t model_number[16];
1100
1101 /* OEM related items */
1102 uint8_t oem_specific[16];
1103
1104 /*
1105 * NVRAM Adapter Features offset 232-239
1106 *
1107 * LSB BIT 0 = External GBIC
1108 * LSB BIT 1 = Risc RAM parity
1109 * LSB BIT 2 = Buffer Plus Module
1110 * LSB BIT 3 = Multi Chip Adapter
1111 * LSB BIT 4 = Internal connector
1112 * LSB BIT 5 =
1113 * LSB BIT 6 =
1114 * LSB BIT 7 =
1115 *
1116 * MSB BIT 0 =
1117 * MSB BIT 1 =
1118 * MSB BIT 2 =
1119 * MSB BIT 3 =
1120 * MSB BIT 4 =
1121 * MSB BIT 5 =
1122 * MSB BIT 6 =
1123 * MSB BIT 7 =
1124 */
1125 uint8_t adapter_features[2];
1126
1127 uint8_t reserved_4[16];
1128
1129 /* Subsystem vendor ID for ISP2200 */
1130 uint16_t subsystem_vendor_id_2200;
1131
1132 /* Subsystem device ID for ISP2200 */
1133 uint16_t subsystem_device_id_2200;
1134
1135 uint8_t reserved_5;
1136 uint8_t checksum;
1137 } nvram_t;
1138
1139 /*
1140 * ISP queue - response queue entry definition.
1141 */
1142 typedef struct {
1143 uint8_t data[60];
1144 uint32_t signature;
1145 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1146 } response_t;
1147
1148 typedef union {
1149 uint16_t extended;
1150 struct {
1151 uint8_t reserved;
1152 uint8_t standard;
1153 } id;
1154 } target_id_t;
1155
1156 #define SET_TARGET_ID(ha, to, from) \
1157 do { \
1158 if (HAS_EXTENDED_IDS(ha)) \
1159 to.extended = cpu_to_le16(from); \
1160 else \
1161 to.id.standard = (uint8_t)from; \
1162 } while (0)
1163
1164 /*
1165 * ISP queue - command entry structure definition.
1166 */
1167 #define COMMAND_TYPE 0x11 /* Command entry */
1168 typedef struct {
1169 uint8_t entry_type; /* Entry type. */
1170 uint8_t entry_count; /* Entry count. */
1171 uint8_t sys_define; /* System defined. */
1172 uint8_t entry_status; /* Entry Status. */
1173 uint32_t handle; /* System handle. */
1174 target_id_t target; /* SCSI ID */
1175 uint16_t lun; /* SCSI LUN */
1176 uint16_t control_flags; /* Control flags. */
1177 #define CF_WRITE BIT_6
1178 #define CF_READ BIT_5
1179 #define CF_SIMPLE_TAG BIT_3
1180 #define CF_ORDERED_TAG BIT_2
1181 #define CF_HEAD_TAG BIT_1
1182 uint16_t reserved_1;
1183 uint16_t timeout; /* Command timeout. */
1184 uint16_t dseg_count; /* Data segment count. */
1185 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1186 uint32_t byte_count; /* Total byte count. */
1187 uint32_t dseg_0_address; /* Data segment 0 address. */
1188 uint32_t dseg_0_length; /* Data segment 0 length. */
1189 uint32_t dseg_1_address; /* Data segment 1 address. */
1190 uint32_t dseg_1_length; /* Data segment 1 length. */
1191 uint32_t dseg_2_address; /* Data segment 2 address. */
1192 uint32_t dseg_2_length; /* Data segment 2 length. */
1193 } cmd_entry_t;
1194
1195 /*
1196 * ISP queue - 64-Bit addressing, command entry structure definition.
1197 */
1198 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1199 typedef struct {
1200 uint8_t entry_type; /* Entry type. */
1201 uint8_t entry_count; /* Entry count. */
1202 uint8_t sys_define; /* System defined. */
1203 uint8_t entry_status; /* Entry Status. */
1204 uint32_t handle; /* System handle. */
1205 target_id_t target; /* SCSI ID */
1206 uint16_t lun; /* SCSI LUN */
1207 uint16_t control_flags; /* Control flags. */
1208 uint16_t reserved_1;
1209 uint16_t timeout; /* Command timeout. */
1210 uint16_t dseg_count; /* Data segment count. */
1211 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1212 uint32_t byte_count; /* Total byte count. */
1213 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1214 uint32_t dseg_0_length; /* Data segment 0 length. */
1215 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1216 uint32_t dseg_1_length; /* Data segment 1 length. */
1217 } cmd_a64_entry_t, request_t;
1218
1219 /*
1220 * ISP queue - continuation entry structure definition.
1221 */
1222 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1223 typedef struct {
1224 uint8_t entry_type; /* Entry type. */
1225 uint8_t entry_count; /* Entry count. */
1226 uint8_t sys_define; /* System defined. */
1227 uint8_t entry_status; /* Entry Status. */
1228 uint32_t reserved;
1229 uint32_t dseg_0_address; /* Data segment 0 address. */
1230 uint32_t dseg_0_length; /* Data segment 0 length. */
1231 uint32_t dseg_1_address; /* Data segment 1 address. */
1232 uint32_t dseg_1_length; /* Data segment 1 length. */
1233 uint32_t dseg_2_address; /* Data segment 2 address. */
1234 uint32_t dseg_2_length; /* Data segment 2 length. */
1235 uint32_t dseg_3_address; /* Data segment 3 address. */
1236 uint32_t dseg_3_length; /* Data segment 3 length. */
1237 uint32_t dseg_4_address; /* Data segment 4 address. */
1238 uint32_t dseg_4_length; /* Data segment 4 length. */
1239 uint32_t dseg_5_address; /* Data segment 5 address. */
1240 uint32_t dseg_5_length; /* Data segment 5 length. */
1241 uint32_t dseg_6_address; /* Data segment 6 address. */
1242 uint32_t dseg_6_length; /* Data segment 6 length. */
1243 } cont_entry_t;
1244
1245 /*
1246 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1247 */
1248 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1249 typedef struct {
1250 uint8_t entry_type; /* Entry type. */
1251 uint8_t entry_count; /* Entry count. */
1252 uint8_t sys_define; /* System defined. */
1253 uint8_t entry_status; /* Entry Status. */
1254 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1255 uint32_t dseg_0_length; /* Data segment 0 length. */
1256 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1257 uint32_t dseg_1_length; /* Data segment 1 length. */
1258 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1259 uint32_t dseg_2_length; /* Data segment 2 length. */
1260 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1261 uint32_t dseg_3_length; /* Data segment 3 length. */
1262 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1263 uint32_t dseg_4_length; /* Data segment 4 length. */
1264 } cont_a64_entry_t;
1265
1266 /*
1267 * ISP queue - status entry structure definition.
1268 */
1269 #define STATUS_TYPE 0x03 /* Status entry. */
1270 typedef struct {
1271 uint8_t entry_type; /* Entry type. */
1272 uint8_t entry_count; /* Entry count. */
1273 uint8_t sys_define; /* System defined. */
1274 uint8_t entry_status; /* Entry Status. */
1275 uint32_t handle; /* System handle. */
1276 uint16_t scsi_status; /* SCSI status. */
1277 uint16_t comp_status; /* Completion status. */
1278 uint16_t state_flags; /* State flags. */
1279 uint16_t status_flags; /* Status flags. */
1280 uint16_t rsp_info_len; /* Response Info Length. */
1281 uint16_t req_sense_length; /* Request sense data length. */
1282 uint32_t residual_length; /* Residual transfer length. */
1283 uint8_t rsp_info[8]; /* FCP response information. */
1284 uint8_t req_sense_data[32]; /* Request sense data. */
1285 } sts_entry_t;
1286
1287 /*
1288 * Status entry entry status
1289 */
1290 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1291 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1292 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1293 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1294 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1295 #define RF_BUSY BIT_1 /* Busy */
1296 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1297 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1298 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1299 RF_INV_E_TYPE)
1300
1301 /*
1302 * Status entry SCSI status bit definitions.
1303 */
1304 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1305 #define SS_RESIDUAL_UNDER BIT_11
1306 #define SS_RESIDUAL_OVER BIT_10
1307 #define SS_SENSE_LEN_VALID BIT_9
1308 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1309
1310 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1311 #define SS_BUSY_CONDITION BIT_3
1312 #define SS_CONDITION_MET BIT_2
1313 #define SS_CHECK_CONDITION BIT_1
1314
1315 /*
1316 * Status entry completion status
1317 */
1318 #define CS_COMPLETE 0x0 /* No errors */
1319 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1320 #define CS_DMA 0x2 /* A DMA direction error. */
1321 #define CS_TRANSPORT 0x3 /* Transport error. */
1322 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1323 #define CS_ABORTED 0x5 /* System aborted command. */
1324 #define CS_TIMEOUT 0x6 /* Timeout error. */
1325 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1326
1327 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1328 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1329 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1330 /* (selection timeout) */
1331 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1332 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1333 #define CS_PORT_BUSY 0x2B /* Port Busy */
1334 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1335 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1336 #define CS_UNKNOWN 0x81 /* Driver defined */
1337 #define CS_RETRY 0x82 /* Driver defined */
1338 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1339
1340 /*
1341 * Status entry status flags
1342 */
1343 #define SF_ABTS_TERMINATED BIT_10
1344 #define SF_LOGOUT_SENT BIT_13
1345
1346 /*
1347 * ISP queue - status continuation entry structure definition.
1348 */
1349 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1350 typedef struct {
1351 uint8_t entry_type; /* Entry type. */
1352 uint8_t entry_count; /* Entry count. */
1353 uint8_t sys_define; /* System defined. */
1354 uint8_t entry_status; /* Entry Status. */
1355 uint8_t data[60]; /* data */
1356 } sts_cont_entry_t;
1357
1358 /*
1359 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1360 * structure definition.
1361 */
1362 #define STATUS_TYPE_21 0x21 /* Status entry. */
1363 typedef struct {
1364 uint8_t entry_type; /* Entry type. */
1365 uint8_t entry_count; /* Entry count. */
1366 uint8_t handle_count; /* Handle count. */
1367 uint8_t entry_status; /* Entry Status. */
1368 uint32_t handle[15]; /* System handles. */
1369 } sts21_entry_t;
1370
1371 /*
1372 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1373 * structure definition.
1374 */
1375 #define STATUS_TYPE_22 0x22 /* Status entry. */
1376 typedef struct {
1377 uint8_t entry_type; /* Entry type. */
1378 uint8_t entry_count; /* Entry count. */
1379 uint8_t handle_count; /* Handle count. */
1380 uint8_t entry_status; /* Entry Status. */
1381 uint16_t handle[30]; /* System handles. */
1382 } sts22_entry_t;
1383
1384 /*
1385 * ISP queue - marker entry structure definition.
1386 */
1387 #define MARKER_TYPE 0x04 /* Marker entry. */
1388 typedef struct {
1389 uint8_t entry_type; /* Entry type. */
1390 uint8_t entry_count; /* Entry count. */
1391 uint8_t handle_count; /* Handle count. */
1392 uint8_t entry_status; /* Entry Status. */
1393 uint32_t sys_define_2; /* System defined. */
1394 target_id_t target; /* SCSI ID */
1395 uint8_t modifier; /* Modifier (7-0). */
1396 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1397 #define MK_SYNC_ID 1 /* Synchronize ID */
1398 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1399 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1400 /* clear port changed, */
1401 /* use sequence number. */
1402 uint8_t reserved_1;
1403 uint16_t sequence_number; /* Sequence number of event */
1404 uint16_t lun; /* SCSI LUN */
1405 uint8_t reserved_2[48];
1406 } mrk_entry_t;
1407
1408 /*
1409 * ISP queue - Management Server entry structure definition.
1410 */
1411 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1412 typedef struct {
1413 uint8_t entry_type; /* Entry type. */
1414 uint8_t entry_count; /* Entry count. */
1415 uint8_t handle_count; /* Handle count. */
1416 uint8_t entry_status; /* Entry Status. */
1417 uint32_t handle1; /* System handle. */
1418 target_id_t loop_id;
1419 uint16_t status;
1420 uint16_t control_flags; /* Control flags. */
1421 uint16_t reserved2;
1422 uint16_t timeout;
1423 uint16_t cmd_dsd_count;
1424 uint16_t total_dsd_count;
1425 uint8_t type;
1426 uint8_t r_ctl;
1427 uint16_t rx_id;
1428 uint16_t reserved3;
1429 uint32_t handle2;
1430 uint32_t rsp_bytecount;
1431 uint32_t req_bytecount;
1432 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1433 uint32_t dseg_req_length; /* Data segment 0 length. */
1434 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1435 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1436 } ms_iocb_entry_t;
1437
1438
1439 /*
1440 * ISP queue - Mailbox Command entry structure definition.
1441 */
1442 #define MBX_IOCB_TYPE 0x39
1443 struct mbx_entry {
1444 uint8_t entry_type;
1445 uint8_t entry_count;
1446 uint8_t sys_define1;
1447 /* Use sys_define1 for source type */
1448 #define SOURCE_SCSI 0x00
1449 #define SOURCE_IP 0x01
1450 #define SOURCE_VI 0x02
1451 #define SOURCE_SCTP 0x03
1452 #define SOURCE_MP 0x04
1453 #define SOURCE_MPIOCTL 0x05
1454 #define SOURCE_ASYNC_IOCB 0x07
1455
1456 uint8_t entry_status;
1457
1458 uint32_t handle;
1459 target_id_t loop_id;
1460
1461 uint16_t status;
1462 uint16_t state_flags;
1463 uint16_t status_flags;
1464
1465 uint32_t sys_define2[2];
1466
1467 uint16_t mb0;
1468 uint16_t mb1;
1469 uint16_t mb2;
1470 uint16_t mb3;
1471 uint16_t mb6;
1472 uint16_t mb7;
1473 uint16_t mb9;
1474 uint16_t mb10;
1475 uint32_t reserved_2[2];
1476 uint8_t node_name[WWN_SIZE];
1477 uint8_t port_name[WWN_SIZE];
1478 };
1479
1480 /*
1481 * ISP request and response queue entry sizes
1482 */
1483 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1484 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1485
1486
1487 /*
1488 * 24 bit port ID type definition.
1489 */
1490 typedef union {
1491 uint32_t b24 : 24;
1492
1493 struct {
1494 #ifdef __BIG_ENDIAN
1495 uint8_t domain;
1496 uint8_t area;
1497 uint8_t al_pa;
1498 #elif __LITTLE_ENDIAN
1499 uint8_t al_pa;
1500 uint8_t area;
1501 uint8_t domain;
1502 #else
1503 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1504 #endif
1505 uint8_t rsvd_1;
1506 } b;
1507 } port_id_t;
1508 #define INVALID_PORT_ID 0xFFFFFF
1509
1510 /*
1511 * Switch info gathering structure.
1512 */
1513 typedef struct {
1514 port_id_t d_id;
1515 uint8_t node_name[WWN_SIZE];
1516 uint8_t port_name[WWN_SIZE];
1517 uint8_t fabric_port_name[WWN_SIZE];
1518 uint16_t fp_speed;
1519 } sw_info_t;
1520
1521 /*
1522 * Fibre channel port type.
1523 */
1524 typedef enum {
1525 FCT_UNKNOWN,
1526 FCT_RSCN,
1527 FCT_SWITCH,
1528 FCT_BROADCAST,
1529 FCT_INITIATOR,
1530 FCT_TARGET
1531 } fc_port_type_t;
1532
1533 /*
1534 * Fibre channel port structure.
1535 */
1536 typedef struct fc_port {
1537 struct list_head list;
1538 struct scsi_qla_host *vha;
1539
1540 uint8_t node_name[WWN_SIZE];
1541 uint8_t port_name[WWN_SIZE];
1542 port_id_t d_id;
1543 uint16_t loop_id;
1544 uint16_t old_loop_id;
1545
1546 uint8_t fabric_port_name[WWN_SIZE];
1547 uint16_t fp_speed;
1548
1549 fc_port_type_t port_type;
1550
1551 atomic_t state;
1552 uint32_t flags;
1553
1554 int port_login_retry_count;
1555 int login_retry;
1556 atomic_t port_down_timer;
1557
1558 struct fc_rport *rport, *drport;
1559 u32 supported_classes;
1560
1561 unsigned long last_queue_full;
1562 unsigned long last_ramp_up;
1563
1564 uint16_t vp_idx;
1565 } fc_port_t;
1566
1567 /*
1568 * Fibre channel port/lun states.
1569 */
1570 #define FCS_UNCONFIGURED 1
1571 #define FCS_DEVICE_DEAD 2
1572 #define FCS_DEVICE_LOST 3
1573 #define FCS_ONLINE 4
1574 #define FCS_NOT_SUPPORTED 5
1575 #define FCS_FAILOVER 6
1576 #define FCS_FAILOVER_FAILED 7
1577
1578 /*
1579 * FC port flags.
1580 */
1581 #define FCF_FABRIC_DEVICE BIT_0
1582 #define FCF_LOGIN_NEEDED BIT_1
1583 #define FCF_FO_MASKED BIT_2
1584 #define FCF_FAILOVER_NEEDED BIT_3
1585 #define FCF_RESET_NEEDED BIT_4
1586 #define FCF_PERSISTENT_BOUND BIT_5
1587 #define FCF_TAPE_PRESENT BIT_6
1588 #define FCF_FARP_DONE BIT_7
1589 #define FCF_FARP_FAILED BIT_8
1590 #define FCF_FARP_REPLY_NEEDED BIT_9
1591 #define FCF_AUTH_REQ BIT_10
1592 #define FCF_SEND_AUTH_REQ BIT_11
1593 #define FCF_RECEIVE_AUTH_REQ BIT_12
1594 #define FCF_AUTH_SUCCESS BIT_13
1595 #define FCF_RLC_SUPPORT BIT_14
1596 #define FCF_CONFIG BIT_15 /* Needed? */
1597 #define FCF_RESCAN_NEEDED BIT_16
1598 #define FCF_XP_DEVICE BIT_17
1599 #define FCF_MSA_DEVICE BIT_18
1600 #define FCF_EVA_DEVICE BIT_19
1601 #define FCF_MSA_PORT_ACTIVE BIT_20
1602 #define FCF_FAILBACK_DISABLE BIT_21
1603 #define FCF_FAILOVER_DISABLE BIT_22
1604 #define FCF_DSXXX_DEVICE BIT_23
1605 #define FCF_AA_EVA_DEVICE BIT_24
1606 #define FCF_AA_MSA_DEVICE BIT_25
1607
1608 /* No loop ID flag. */
1609 #define FC_NO_LOOP_ID 0x1000
1610
1611 /*
1612 * FC-CT interface
1613 *
1614 * NOTE: All structures are big-endian in form.
1615 */
1616
1617 #define CT_REJECT_RESPONSE 0x8001
1618 #define CT_ACCEPT_RESPONSE 0x8002
1619 #define CT_REASON_INVALID_COMMAND_CODE 0x01
1620 #define CT_REASON_CANNOT_PERFORM 0x09
1621 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
1622 #define CT_EXPL_ALREADY_REGISTERED 0x10
1623
1624 #define NS_N_PORT_TYPE 0x01
1625 #define NS_NL_PORT_TYPE 0x02
1626 #define NS_NX_PORT_TYPE 0x7F
1627
1628 #define GA_NXT_CMD 0x100
1629 #define GA_NXT_REQ_SIZE (16 + 4)
1630 #define GA_NXT_RSP_SIZE (16 + 620)
1631
1632 #define GID_PT_CMD 0x1A1
1633 #define GID_PT_REQ_SIZE (16 + 4)
1634 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1635
1636 #define GPN_ID_CMD 0x112
1637 #define GPN_ID_REQ_SIZE (16 + 4)
1638 #define GPN_ID_RSP_SIZE (16 + 8)
1639
1640 #define GNN_ID_CMD 0x113
1641 #define GNN_ID_REQ_SIZE (16 + 4)
1642 #define GNN_ID_RSP_SIZE (16 + 8)
1643
1644 #define GFT_ID_CMD 0x117
1645 #define GFT_ID_REQ_SIZE (16 + 4)
1646 #define GFT_ID_RSP_SIZE (16 + 32)
1647
1648 #define RFT_ID_CMD 0x217
1649 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1650 #define RFT_ID_RSP_SIZE 16
1651
1652 #define RFF_ID_CMD 0x21F
1653 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1654 #define RFF_ID_RSP_SIZE 16
1655
1656 #define RNN_ID_CMD 0x213
1657 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1658 #define RNN_ID_RSP_SIZE 16
1659
1660 #define RSNN_NN_CMD 0x239
1661 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1662 #define RSNN_NN_RSP_SIZE 16
1663
1664 #define GFPN_ID_CMD 0x11C
1665 #define GFPN_ID_REQ_SIZE (16 + 4)
1666 #define GFPN_ID_RSP_SIZE (16 + 8)
1667
1668 #define GPSC_CMD 0x127
1669 #define GPSC_REQ_SIZE (16 + 8)
1670 #define GPSC_RSP_SIZE (16 + 2 + 2)
1671
1672
1673 /*
1674 * HBA attribute types.
1675 */
1676 #define FDMI_HBA_ATTR_COUNT 9
1677 #define FDMI_HBA_NODE_NAME 1
1678 #define FDMI_HBA_MANUFACTURER 2
1679 #define FDMI_HBA_SERIAL_NUMBER 3
1680 #define FDMI_HBA_MODEL 4
1681 #define FDMI_HBA_MODEL_DESCRIPTION 5
1682 #define FDMI_HBA_HARDWARE_VERSION 6
1683 #define FDMI_HBA_DRIVER_VERSION 7
1684 #define FDMI_HBA_OPTION_ROM_VERSION 8
1685 #define FDMI_HBA_FIRMWARE_VERSION 9
1686 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1687 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1688
1689 struct ct_fdmi_hba_attr {
1690 uint16_t type;
1691 uint16_t len;
1692 union {
1693 uint8_t node_name[WWN_SIZE];
1694 uint8_t manufacturer[32];
1695 uint8_t serial_num[8];
1696 uint8_t model[16];
1697 uint8_t model_desc[80];
1698 uint8_t hw_version[16];
1699 uint8_t driver_version[32];
1700 uint8_t orom_version[16];
1701 uint8_t fw_version[16];
1702 uint8_t os_version[128];
1703 uint8_t max_ct_len[4];
1704 } a;
1705 };
1706
1707 struct ct_fdmi_hba_attributes {
1708 uint32_t count;
1709 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1710 };
1711
1712 /*
1713 * Port attribute types.
1714 */
1715 #define FDMI_PORT_ATTR_COUNT 6
1716 #define FDMI_PORT_FC4_TYPES 1
1717 #define FDMI_PORT_SUPPORT_SPEED 2
1718 #define FDMI_PORT_CURRENT_SPEED 3
1719 #define FDMI_PORT_MAX_FRAME_SIZE 4
1720 #define FDMI_PORT_OS_DEVICE_NAME 5
1721 #define FDMI_PORT_HOST_NAME 6
1722
1723 #define FDMI_PORT_SPEED_1GB 0x1
1724 #define FDMI_PORT_SPEED_2GB 0x2
1725 #define FDMI_PORT_SPEED_10GB 0x4
1726 #define FDMI_PORT_SPEED_4GB 0x8
1727 #define FDMI_PORT_SPEED_8GB 0x10
1728 #define FDMI_PORT_SPEED_16GB 0x20
1729 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
1730
1731 struct ct_fdmi_port_attr {
1732 uint16_t type;
1733 uint16_t len;
1734 union {
1735 uint8_t fc4_types[32];
1736 uint32_t sup_speed;
1737 uint32_t cur_speed;
1738 uint32_t max_frame_size;
1739 uint8_t os_dev_name[32];
1740 uint8_t host_name[32];
1741 } a;
1742 };
1743
1744 /*
1745 * Port Attribute Block.
1746 */
1747 struct ct_fdmi_port_attributes {
1748 uint32_t count;
1749 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1750 };
1751
1752 /* FDMI definitions. */
1753 #define GRHL_CMD 0x100
1754 #define GHAT_CMD 0x101
1755 #define GRPL_CMD 0x102
1756 #define GPAT_CMD 0x110
1757
1758 #define RHBA_CMD 0x200
1759 #define RHBA_RSP_SIZE 16
1760
1761 #define RHAT_CMD 0x201
1762 #define RPRT_CMD 0x210
1763
1764 #define RPA_CMD 0x211
1765 #define RPA_RSP_SIZE 16
1766
1767 #define DHBA_CMD 0x300
1768 #define DHBA_REQ_SIZE (16 + 8)
1769 #define DHBA_RSP_SIZE 16
1770
1771 #define DHAT_CMD 0x301
1772 #define DPRT_CMD 0x310
1773 #define DPA_CMD 0x311
1774
1775 /* CT command header -- request/response common fields */
1776 struct ct_cmd_hdr {
1777 uint8_t revision;
1778 uint8_t in_id[3];
1779 uint8_t gs_type;
1780 uint8_t gs_subtype;
1781 uint8_t options;
1782 uint8_t reserved;
1783 };
1784
1785 /* CT command request */
1786 struct ct_sns_req {
1787 struct ct_cmd_hdr header;
1788 uint16_t command;
1789 uint16_t max_rsp_size;
1790 uint8_t fragment_id;
1791 uint8_t reserved[3];
1792
1793 union {
1794 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
1795 struct {
1796 uint8_t reserved;
1797 uint8_t port_id[3];
1798 } port_id;
1799
1800 struct {
1801 uint8_t port_type;
1802 uint8_t domain;
1803 uint8_t area;
1804 uint8_t reserved;
1805 } gid_pt;
1806
1807 struct {
1808 uint8_t reserved;
1809 uint8_t port_id[3];
1810 uint8_t fc4_types[32];
1811 } rft_id;
1812
1813 struct {
1814 uint8_t reserved;
1815 uint8_t port_id[3];
1816 uint16_t reserved2;
1817 uint8_t fc4_feature;
1818 uint8_t fc4_type;
1819 } rff_id;
1820
1821 struct {
1822 uint8_t reserved;
1823 uint8_t port_id[3];
1824 uint8_t node_name[8];
1825 } rnn_id;
1826
1827 struct {
1828 uint8_t node_name[8];
1829 uint8_t name_len;
1830 uint8_t sym_node_name[255];
1831 } rsnn_nn;
1832
1833 struct {
1834 uint8_t hba_indentifier[8];
1835 } ghat;
1836
1837 struct {
1838 uint8_t hba_identifier[8];
1839 uint32_t entry_count;
1840 uint8_t port_name[8];
1841 struct ct_fdmi_hba_attributes attrs;
1842 } rhba;
1843
1844 struct {
1845 uint8_t hba_identifier[8];
1846 struct ct_fdmi_hba_attributes attrs;
1847 } rhat;
1848
1849 struct {
1850 uint8_t port_name[8];
1851 struct ct_fdmi_port_attributes attrs;
1852 } rpa;
1853
1854 struct {
1855 uint8_t port_name[8];
1856 } dhba;
1857
1858 struct {
1859 uint8_t port_name[8];
1860 } dhat;
1861
1862 struct {
1863 uint8_t port_name[8];
1864 } dprt;
1865
1866 struct {
1867 uint8_t port_name[8];
1868 } dpa;
1869
1870 struct {
1871 uint8_t port_name[8];
1872 } gpsc;
1873 } req;
1874 };
1875
1876 /* CT command response header */
1877 struct ct_rsp_hdr {
1878 struct ct_cmd_hdr header;
1879 uint16_t response;
1880 uint16_t residual;
1881 uint8_t fragment_id;
1882 uint8_t reason_code;
1883 uint8_t explanation_code;
1884 uint8_t vendor_unique;
1885 };
1886
1887 struct ct_sns_gid_pt_data {
1888 uint8_t control_byte;
1889 uint8_t port_id[3];
1890 };
1891
1892 struct ct_sns_rsp {
1893 struct ct_rsp_hdr header;
1894
1895 union {
1896 struct {
1897 uint8_t port_type;
1898 uint8_t port_id[3];
1899 uint8_t port_name[8];
1900 uint8_t sym_port_name_len;
1901 uint8_t sym_port_name[255];
1902 uint8_t node_name[8];
1903 uint8_t sym_node_name_len;
1904 uint8_t sym_node_name[255];
1905 uint8_t init_proc_assoc[8];
1906 uint8_t node_ip_addr[16];
1907 uint8_t class_of_service[4];
1908 uint8_t fc4_types[32];
1909 uint8_t ip_address[16];
1910 uint8_t fabric_port_name[8];
1911 uint8_t reserved;
1912 uint8_t hard_address[3];
1913 } ga_nxt;
1914
1915 struct {
1916 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1917 } gid_pt;
1918
1919 struct {
1920 uint8_t port_name[8];
1921 } gpn_id;
1922
1923 struct {
1924 uint8_t node_name[8];
1925 } gnn_id;
1926
1927 struct {
1928 uint8_t fc4_types[32];
1929 } gft_id;
1930
1931 struct {
1932 uint32_t entry_count;
1933 uint8_t port_name[8];
1934 struct ct_fdmi_hba_attributes attrs;
1935 } ghat;
1936
1937 struct {
1938 uint8_t port_name[8];
1939 } gfpn_id;
1940
1941 struct {
1942 uint16_t speeds;
1943 uint16_t speed;
1944 } gpsc;
1945 } rsp;
1946 };
1947
1948 struct ct_sns_pkt {
1949 union {
1950 struct ct_sns_req req;
1951 struct ct_sns_rsp rsp;
1952 } p;
1953 };
1954
1955 /*
1956 * SNS command structures -- for 2200 compatability.
1957 */
1958 #define RFT_ID_SNS_SCMD_LEN 22
1959 #define RFT_ID_SNS_CMD_SIZE 60
1960 #define RFT_ID_SNS_DATA_SIZE 16
1961
1962 #define RNN_ID_SNS_SCMD_LEN 10
1963 #define RNN_ID_SNS_CMD_SIZE 36
1964 #define RNN_ID_SNS_DATA_SIZE 16
1965
1966 #define GA_NXT_SNS_SCMD_LEN 6
1967 #define GA_NXT_SNS_CMD_SIZE 28
1968 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
1969
1970 #define GID_PT_SNS_SCMD_LEN 6
1971 #define GID_PT_SNS_CMD_SIZE 28
1972 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1973
1974 #define GPN_ID_SNS_SCMD_LEN 6
1975 #define GPN_ID_SNS_CMD_SIZE 28
1976 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
1977
1978 #define GNN_ID_SNS_SCMD_LEN 6
1979 #define GNN_ID_SNS_CMD_SIZE 28
1980 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
1981
1982 struct sns_cmd_pkt {
1983 union {
1984 struct {
1985 uint16_t buffer_length;
1986 uint16_t reserved_1;
1987 uint32_t buffer_address[2];
1988 uint16_t subcommand_length;
1989 uint16_t reserved_2;
1990 uint16_t subcommand;
1991 uint16_t size;
1992 uint32_t reserved_3;
1993 uint8_t param[36];
1994 } cmd;
1995
1996 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
1997 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
1998 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
1999 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2000 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2001 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2002 } p;
2003 };
2004
2005 struct fw_blob {
2006 char *name;
2007 uint32_t segs[4];
2008 const struct firmware *fw;
2009 };
2010
2011 /* Return data from MBC_GET_ID_LIST call. */
2012 struct gid_list_info {
2013 uint8_t al_pa;
2014 uint8_t area;
2015 uint8_t domain;
2016 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2017 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2018 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2019 };
2020 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2021
2022 /* NPIV */
2023 typedef struct vport_info {
2024 uint8_t port_name[WWN_SIZE];
2025 uint8_t node_name[WWN_SIZE];
2026 int vp_id;
2027 uint16_t loop_id;
2028 unsigned long host_no;
2029 uint8_t port_id[3];
2030 int loop_state;
2031 } vport_info_t;
2032
2033 typedef struct vport_params {
2034 uint8_t port_name[WWN_SIZE];
2035 uint8_t node_name[WWN_SIZE];
2036 uint32_t options;
2037 #define VP_OPTS_RETRY_ENABLE BIT_0
2038 #define VP_OPTS_VP_DISABLE BIT_1
2039 } vport_params_t;
2040
2041 /* NPIV - return codes of VP create and modify */
2042 #define VP_RET_CODE_OK 0
2043 #define VP_RET_CODE_FATAL 1
2044 #define VP_RET_CODE_WRONG_ID 2
2045 #define VP_RET_CODE_WWPN 3
2046 #define VP_RET_CODE_RESOURCES 4
2047 #define VP_RET_CODE_NO_MEM 5
2048 #define VP_RET_CODE_NOT_FOUND 6
2049
2050 struct qla_hw_data;
2051
2052 /*
2053 * ISP operations
2054 */
2055 struct isp_operations {
2056
2057 int (*pci_config) (struct scsi_qla_host *);
2058 void (*reset_chip) (struct scsi_qla_host *);
2059 int (*chip_diag) (struct scsi_qla_host *);
2060 void (*config_rings) (struct scsi_qla_host *);
2061 void (*reset_adapter) (struct scsi_qla_host *);
2062 int (*nvram_config) (struct scsi_qla_host *);
2063 void (*update_fw_options) (struct scsi_qla_host *);
2064 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2065
2066 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2067 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2068
2069 irq_handler_t intr_handler;
2070 void (*enable_intrs) (struct qla_hw_data *);
2071 void (*disable_intrs) (struct qla_hw_data *);
2072
2073 int (*abort_command) (struct scsi_qla_host *, srb_t *,
2074 struct req_que *);
2075 int (*target_reset) (struct fc_port *, unsigned int);
2076 int (*lun_reset) (struct fc_port *, unsigned int);
2077 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2078 uint8_t, uint8_t, uint16_t *, uint8_t);
2079 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2080 uint8_t, uint8_t);
2081
2082 uint16_t (*calc_req_entries) (uint16_t);
2083 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2084 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2085 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2086 uint32_t);
2087
2088 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2089 uint32_t, uint32_t);
2090 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2091 uint32_t);
2092
2093 void (*fw_dump) (struct scsi_qla_host *, int);
2094
2095 int (*beacon_on) (struct scsi_qla_host *);
2096 int (*beacon_off) (struct scsi_qla_host *);
2097 void (*beacon_blink) (struct scsi_qla_host *);
2098
2099 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2100 uint32_t, uint32_t);
2101 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2102 uint32_t);
2103
2104 int (*get_flash_version) (struct scsi_qla_host *, void *);
2105 int (*start_scsi) (srb_t *);
2106 void (*wrt_req_reg) (struct qla_hw_data *, uint16_t, uint16_t);
2107 void (*wrt_rsp_reg) (struct qla_hw_data *, uint16_t, uint16_t);
2108 uint16_t (*rd_req_reg) (struct qla_hw_data *, uint16_t);
2109 };
2110
2111 /* MSI-X Support *************************************************************/
2112
2113 #define QLA_MSIX_CHIP_REV_24XX 3
2114 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2115 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2116
2117 #define QLA_MSIX_DEFAULT 0x00
2118 #define QLA_MSIX_RSP_Q 0x01
2119
2120 #define QLA_MIDX_DEFAULT 0
2121 #define QLA_MIDX_RSP_Q 1
2122 #define QLA_PCI_MSIX_CONTROL 0xa2
2123
2124 struct scsi_qla_host;
2125 struct rsp_que;
2126
2127 struct qla_msix_entry {
2128 int have_irq;
2129 uint32_t vector;
2130 uint16_t entry;
2131 struct rsp_que *rsp;
2132 };
2133
2134 #define WATCH_INTERVAL 1 /* number of seconds */
2135
2136 /* Work events. */
2137 enum qla_work_type {
2138 QLA_EVT_AEN,
2139 QLA_EVT_HWE_LOG,
2140 };
2141
2142
2143 struct qla_work_evt {
2144 struct list_head list;
2145 enum qla_work_type type;
2146 u32 flags;
2147 #define QLA_EVT_FLAG_FREE 0x1
2148
2149 union {
2150 struct {
2151 enum fc_host_event_code code;
2152 u32 data;
2153 } aen;
2154 struct {
2155 uint16_t code;
2156 uint16_t d1, d2, d3;
2157 } hwe;
2158 } u;
2159 };
2160
2161 struct qla_chip_state_84xx {
2162 struct list_head list;
2163 struct kref kref;
2164
2165 void *bus;
2166 spinlock_t access_lock;
2167 struct mutex fw_update_mutex;
2168 uint32_t fw_update;
2169 uint32_t op_fw_version;
2170 uint32_t op_fw_size;
2171 uint32_t op_fw_seq_size;
2172 uint32_t diag_fw_version;
2173 uint32_t gold_fw_version;
2174 };
2175
2176 struct qla_statistics {
2177 uint32_t total_isp_aborts;
2178 uint64_t input_bytes;
2179 uint64_t output_bytes;
2180 };
2181
2182 /* Multi queue support */
2183 #define MBC_INITIALIZE_MULTIQ 0x1f
2184 #define QLA_QUE_PAGE 0X1000
2185 #define QLA_MQ_SIZE 32
2186 #define QLA_MAX_HOST_QUES 16
2187 #define QLA_MAX_QUEUES 256
2188 #define ISP_QUE_REG(ha, id) \
2189 ((ha->mqenable) ? \
2190 ((void *)(ha->mqiobase) +\
2191 (QLA_QUE_PAGE * id)) :\
2192 ((void *)(ha->iobase)))
2193 #define QLA_REQ_QUE_ID(tag) \
2194 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2195 #define QLA_DEFAULT_QUE_QOS 5
2196 #define QLA_PRECONFIG_VPORTS 32
2197 #define QLA_MAX_VPORTS_QLA24XX 128
2198 #define QLA_MAX_VPORTS_QLA25XX 256
2199 /* Response queue data structure */
2200 struct rsp_que {
2201 dma_addr_t dma;
2202 response_t *ring;
2203 response_t *ring_ptr;
2204 uint16_t ring_index;
2205 uint16_t out_ptr;
2206 uint16_t length;
2207 uint16_t options;
2208 uint16_t rid;
2209 uint16_t id;
2210 uint16_t vp_idx;
2211 struct qla_hw_data *hw;
2212 struct qla_msix_entry *msix;
2213 struct req_que *req;
2214 };
2215
2216 /* Request queue data structure */
2217 struct req_que {
2218 dma_addr_t dma;
2219 request_t *ring;
2220 request_t *ring_ptr;
2221 uint16_t ring_index;
2222 uint16_t in_ptr;
2223 uint16_t cnt;
2224 uint16_t length;
2225 uint16_t options;
2226 uint16_t rid;
2227 uint16_t id;
2228 uint16_t qos;
2229 uint16_t vp_idx;
2230 struct rsp_que *rsp;
2231 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2232 uint32_t current_outstanding_cmd;
2233 int max_q_depth;
2234 };
2235
2236 /*
2237 * Qlogic host adapter specific data structure.
2238 */
2239 struct qla_hw_data {
2240 struct pci_dev *pdev;
2241 /* SRB cache. */
2242 #define SRB_MIN_REQ 128
2243 mempool_t *srb_mempool;
2244
2245 volatile struct {
2246 uint32_t mbox_int :1;
2247 uint32_t mbox_busy :1;
2248
2249 uint32_t disable_risc_code_load :1;
2250 uint32_t enable_64bit_addressing :1;
2251 uint32_t enable_lip_reset :1;
2252 uint32_t enable_target_reset :1;
2253 uint32_t enable_lip_full_login :1;
2254 uint32_t enable_led_scheme :1;
2255 uint32_t inta_enabled :1;
2256 uint32_t msi_enabled :1;
2257 uint32_t msix_enabled :1;
2258 uint32_t disable_serdes :1;
2259 uint32_t gpsc_supported :1;
2260 uint32_t vsan_enabled :1;
2261 uint32_t npiv_supported :1;
2262 uint32_t fce_enabled :1;
2263 uint32_t hw_event_marker_found:1;
2264 } flags;
2265
2266 /* This spinlock is used to protect "io transactions", you must
2267 * acquire it before doing any IO to the card, eg with RD_REG*() and
2268 * WRT_REG*() for the duration of your entire commandtransaction.
2269 *
2270 * This spinlock is of lower priority than the io request lock.
2271 */
2272
2273 spinlock_t hardware_lock ____cacheline_aligned;
2274 int bars;
2275 int mem_only;
2276 device_reg_t __iomem *iobase; /* Base I/O address */
2277 resource_size_t pio_address;
2278
2279 #define MIN_IOBASE_LEN 0x100
2280 /* Multi queue data structs */
2281 device_reg_t *mqiobase;
2282 uint16_t msix_count;
2283 uint8_t mqenable;
2284 struct req_que **req_q_map;
2285 struct rsp_que **rsp_q_map;
2286 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2287 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2288 uint16_t max_queues;
2289 struct qla_npiv_entry *npiv_info;
2290 uint16_t nvram_npiv_size;
2291
2292 uint16_t switch_cap;
2293 #define FLOGI_SEQ_DEL BIT_8
2294 #define FLOGI_MID_SUPPORT BIT_10
2295 #define FLOGI_VSAN_SUPPORT BIT_12
2296 #define FLOGI_SP_SUPPORT BIT_13
2297 /* Timeout timers. */
2298 uint8_t loop_down_abort_time; /* port down timer */
2299 atomic_t loop_down_timer; /* loop down timer */
2300 uint8_t link_down_timeout; /* link down timeout */
2301 uint16_t max_loop_id;
2302
2303 uint16_t fb_rev;
2304 uint16_t max_public_loop_ids;
2305 uint16_t min_external_loopid; /* First external loop Id */
2306
2307 #define PORT_SPEED_UNKNOWN 0xFFFF
2308 #define PORT_SPEED_1GB 0x00
2309 #define PORT_SPEED_2GB 0x01
2310 #define PORT_SPEED_4GB 0x03
2311 #define PORT_SPEED_8GB 0x04
2312 uint16_t link_data_rate; /* F/W operating speed */
2313
2314 uint8_t current_topology;
2315 uint8_t prev_topology;
2316 #define ISP_CFG_NL 1
2317 #define ISP_CFG_N 2
2318 #define ISP_CFG_FL 4
2319 #define ISP_CFG_F 8
2320
2321 uint8_t operating_mode; /* F/W operating mode */
2322 #define LOOP 0
2323 #define P2P 1
2324 #define LOOP_P2P 2
2325 #define P2P_LOOP 3
2326 uint8_t interrupts_on;
2327 uint32_t isp_abort_cnt;
2328
2329 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2330 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
2331 uint32_t device_type;
2332 #define DT_ISP2100 BIT_0
2333 #define DT_ISP2200 BIT_1
2334 #define DT_ISP2300 BIT_2
2335 #define DT_ISP2312 BIT_3
2336 #define DT_ISP2322 BIT_4
2337 #define DT_ISP6312 BIT_5
2338 #define DT_ISP6322 BIT_6
2339 #define DT_ISP2422 BIT_7
2340 #define DT_ISP2432 BIT_8
2341 #define DT_ISP5422 BIT_9
2342 #define DT_ISP5432 BIT_10
2343 #define DT_ISP2532 BIT_11
2344 #define DT_ISP8432 BIT_12
2345 #define DT_ISP_LAST (DT_ISP8432 << 1)
2346
2347 #define DT_IIDMA BIT_26
2348 #define DT_FWI2 BIT_27
2349 #define DT_ZIO_SUPPORTED BIT_28
2350 #define DT_OEM_001 BIT_29
2351 #define DT_ISP2200A BIT_30
2352 #define DT_EXTENDED_IDS BIT_31
2353 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2354 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2355 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2356 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2357 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2358 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2359 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2360 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2361 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2362 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2363 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2364 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2365 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2366 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
2367
2368 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2369 IS_QLA6312(ha) || IS_QLA6322(ha))
2370 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2371 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2372 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
2373 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
2374 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2375 IS_QLA84XX(ha))
2376 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
2377 IS_QLA25XX(ha))
2378
2379 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
2380 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
2381 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2382 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2383 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2384
2385 /* HBA serial number */
2386 uint8_t serial0;
2387 uint8_t serial1;
2388 uint8_t serial2;
2389
2390 /* NVRAM configuration data */
2391 #define MAX_NVRAM_SIZE 4096
2392 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
2393 uint16_t nvram_size;
2394 uint16_t nvram_base;
2395 void *nvram;
2396 uint16_t vpd_size;
2397 uint16_t vpd_base;
2398 void *vpd;
2399
2400 uint16_t loop_reset_delay;
2401 uint8_t retry_count;
2402 uint8_t login_timeout;
2403 uint16_t r_a_tov;
2404 int port_down_retry_count;
2405 uint8_t mbx_count;
2406
2407 uint32_t login_retry_count;
2408 /* SNS command interfaces. */
2409 ms_iocb_entry_t *ms_iocb;
2410 dma_addr_t ms_iocb_dma;
2411 struct ct_sns_pkt *ct_sns;
2412 dma_addr_t ct_sns_dma;
2413 /* SNS command interfaces for 2200. */
2414 struct sns_cmd_pkt *sns_cmd;
2415 dma_addr_t sns_cmd_dma;
2416
2417 #define SFP_DEV_SIZE 256
2418 #define SFP_BLOCK_SIZE 64
2419 void *sfp_data;
2420 dma_addr_t sfp_data_dma;
2421
2422 struct task_struct *dpc_thread;
2423 uint8_t dpc_active; /* DPC routine is active */
2424
2425 dma_addr_t gid_list_dma;
2426 struct gid_list_info *gid_list;
2427 int gid_list_info_size;
2428
2429 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2430 #define DMA_POOL_SIZE 256
2431 struct dma_pool *s_dma_pool;
2432
2433 dma_addr_t init_cb_dma;
2434 init_cb_t *init_cb;
2435 int init_cb_size;
2436
2437 /* These are used by mailbox operations. */
2438 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2439
2440 mbx_cmd_t *mcp;
2441 unsigned long mbx_cmd_flags;
2442 #define MBX_INTERRUPT 1
2443 #define MBX_INTR_WAIT 2
2444 #define MBX_UPDATE_FLASH_ACTIVE 3
2445
2446 struct mutex vport_lock; /* Virtual port synchronization */
2447 struct completion mbx_cmd_comp; /* Serialize mbx access */
2448 struct completion mbx_intr_comp; /* Used for completion notification */
2449
2450 uint32_t mbx_flags;
2451 #define MBX_IN_PROGRESS BIT_0
2452 #define MBX_BUSY BIT_1 /* Got the Access */
2453 #define MBX_SLEEPING_ON_SEM BIT_2
2454 #define MBX_POLLING_FOR_COMP BIT_3
2455 #define MBX_COMPLETED BIT_4
2456 #define MBX_TIMEDOUT BIT_5
2457 #define MBX_ACCESS_TIMEDOUT BIT_6
2458
2459 /* Basic firmware related information. */
2460 uint16_t fw_major_version;
2461 uint16_t fw_minor_version;
2462 uint16_t fw_subminor_version;
2463 uint16_t fw_attributes;
2464 uint32_t fw_memory_size;
2465 uint32_t fw_transfer_size;
2466 uint32_t fw_srisc_address;
2467 #define RISC_START_ADDRESS_2100 0x1000
2468 #define RISC_START_ADDRESS_2300 0x800
2469 #define RISC_START_ADDRESS_2400 0x100000
2470
2471 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2472 uint8_t fw_seriallink_options[4];
2473 uint16_t fw_seriallink_options24[4];
2474
2475 /* Firmware dump information. */
2476 struct qla2xxx_fw_dump *fw_dump;
2477 uint32_t fw_dump_len;
2478 int fw_dumped;
2479 int fw_dump_reading;
2480 dma_addr_t eft_dma;
2481 void *eft;
2482
2483 struct dentry *dfs_dir;
2484 struct dentry *dfs_fce;
2485 dma_addr_t fce_dma;
2486 void *fce;
2487 uint32_t fce_bufs;
2488 uint16_t fce_mb[8];
2489 uint64_t fce_wr, fce_rd;
2490 struct mutex fce_mutex;
2491
2492 uint32_t hw_event_start;
2493 uint32_t hw_event_ptr;
2494 uint32_t hw_event_pause_errors;
2495
2496 uint32_t pci_attr;
2497 uint16_t chip_revision;
2498
2499 uint16_t product_id[4];
2500
2501 uint8_t model_number[16+1];
2502 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2503 char model_desc[80];
2504 uint8_t adapter_id[16+1];
2505
2506 /* Option ROM information. */
2507 char *optrom_buffer;
2508 uint32_t optrom_size;
2509 int optrom_state;
2510 #define QLA_SWAITING 0
2511 #define QLA_SREADING 1
2512 #define QLA_SWRITING 2
2513 uint32_t optrom_region_start;
2514 uint32_t optrom_region_size;
2515
2516 /* PCI expansion ROM image information. */
2517 #define ROM_CODE_TYPE_BIOS 0
2518 #define ROM_CODE_TYPE_FCODE 1
2519 #define ROM_CODE_TYPE_EFI 3
2520 uint8_t bios_revision[2];
2521 uint8_t efi_revision[2];
2522 uint8_t fcode_revision[16];
2523 uint32_t fw_revision[4];
2524
2525 uint32_t fdt_wrt_disable;
2526 uint32_t fdt_erase_cmd;
2527 uint32_t fdt_block_size;
2528 uint32_t fdt_unprotect_sec_cmd;
2529 uint32_t fdt_protect_sec_cmd;
2530
2531 uint32_t flt_region_flt;
2532 uint32_t flt_region_fdt;
2533 uint32_t flt_region_boot;
2534 uint32_t flt_region_fw;
2535 uint32_t flt_region_vpd_nvram;
2536 uint32_t flt_region_hw_event;
2537 uint32_t flt_region_npiv_conf;
2538
2539 /* Needed for BEACON */
2540 uint16_t beacon_blink_led;
2541 uint8_t beacon_color_state;
2542 #define QLA_LED_GRN_ON 0x01
2543 #define QLA_LED_YLW_ON 0x02
2544 #define QLA_LED_ABR_ON 0x04
2545 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2546 /* ISP2322: red, green, amber. */
2547 uint16_t zio_mode;
2548 uint16_t zio_timer;
2549 struct fc_host_statistics fc_host_stat;
2550
2551 struct qla_msix_entry *msix_entries;
2552
2553 struct list_head vp_list; /* list of VP */
2554 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
2555 sizeof(unsigned long)];
2556 uint16_t num_vhosts; /* number of vports created */
2557 uint16_t num_vsans; /* number of vsan created */
2558 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
2559 int cur_vport_count;
2560
2561 struct qla_chip_state_84xx *cs84xx;
2562 struct qla_statistics qla_stats;
2563 struct isp_operations *isp_ops;
2564 };
2565
2566 /*
2567 * Qlogic scsi host structure
2568 */
2569 typedef struct scsi_qla_host {
2570 struct list_head list;
2571 struct list_head vp_fcports; /* list of fcports */
2572 struct list_head work_list;
2573 /* Commonly used flags and state information. */
2574 struct Scsi_Host *host;
2575 unsigned long host_no;
2576 uint8_t host_str[16];
2577
2578 volatile struct {
2579 uint32_t init_done :1;
2580 uint32_t online :1;
2581 uint32_t rscn_queue_overflow :1;
2582 uint32_t reset_active :1;
2583
2584 uint32_t management_server_logged_in :1;
2585 uint32_t process_response_queue :1;
2586 } flags;
2587
2588 atomic_t loop_state;
2589 #define LOOP_TIMEOUT 1
2590 #define LOOP_DOWN 2
2591 #define LOOP_UP 3
2592 #define LOOP_UPDATE 4
2593 #define LOOP_READY 5
2594 #define LOOP_DEAD 6
2595
2596 unsigned long dpc_flags;
2597 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2598 #define RESET_ACTIVE 1
2599 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2600 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2601 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2602 #define LOOP_RESYNC_ACTIVE 5
2603 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2604 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2605 #define MAILBOX_RETRY 8
2606 #define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2607 #define FAILOVER_EVENT_NEEDED 10
2608 #define FAILOVER_EVENT 11
2609 #define FAILOVER_NEEDED 12
2610 #define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2611 #define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2612 #define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2613 #define ABORT_QUEUES_NEEDED 16
2614 #define RELOGIN_NEEDED 17
2615 #define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2616 #define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2617 #define ISP_ABORT_RETRY 20 /* ISP aborted. */
2618 #define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2619 #define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
2620 #define IOCTL_ERROR_RECOVERY 23
2621 #define LOOP_RESET_NEEDED 24
2622 #define BEACON_BLINK_NEEDED 25
2623 #define REGISTER_FDMI_NEEDED 26
2624 #define FCPORT_UPDATE_NEEDED 27
2625 #define VP_DPC_NEEDED 28 /* wake up for VP dpc handling */
2626 #define UNLOADING 29
2627 #define NPIV_CONFIG_NEEDED 30
2628
2629 uint32_t device_flags;
2630 #define DFLG_LOCAL_DEVICES BIT_0
2631 #define DFLG_RETRY_LOCAL_DEVICES BIT_1
2632 #define DFLG_FABRIC_DEVICES BIT_2
2633 #define SWITCH_FOUND BIT_3
2634 #define DFLG_NO_CABLE BIT_4
2635
2636 srb_t *status_srb; /* Status continuation entry. */
2637
2638 /* ISP configuration data. */
2639 uint16_t loop_id; /* Host adapter loop id */
2640
2641 port_id_t d_id; /* Host adapter port id */
2642 uint8_t marker_needed;
2643 uint16_t mgmt_svr_loop_id;
2644
2645
2646
2647 /* RSCN queue. */
2648 uint32_t rscn_queue[MAX_RSCN_COUNT];
2649 uint8_t rscn_in_ptr;
2650 uint8_t rscn_out_ptr;
2651
2652 /* Timeout timers. */
2653 uint8_t loop_down_abort_time; /* port down timer */
2654 atomic_t loop_down_timer; /* loop down timer */
2655 uint8_t link_down_timeout; /* link down timeout */
2656
2657 uint32_t timer_active;
2658 struct timer_list timer;
2659
2660 uint8_t node_name[WWN_SIZE];
2661 uint8_t port_name[WWN_SIZE];
2662 uint8_t fabric_node_name[WWN_SIZE];
2663 uint32_t vp_abort_cnt;
2664
2665 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
2666 uint16_t vp_idx; /* vport ID */
2667
2668 unsigned long vp_flags;
2669 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
2670 #define VP_CREATE_NEEDED 1
2671 #define VP_BIND_NEEDED 2
2672 #define VP_DELETE_NEEDED 3
2673 #define VP_SCR_NEEDED 4 /* State Change Request registration */
2674 atomic_t vp_state;
2675 #define VP_OFFLINE 0
2676 #define VP_ACTIVE 1
2677 #define VP_FAILED 2
2678 // #define VP_DISABLE 3
2679 uint16_t vp_err_state;
2680 uint16_t vp_prev_err_state;
2681 #define VP_ERR_UNKWN 0
2682 #define VP_ERR_PORTDWN 1
2683 #define VP_ERR_FAB_UNSUPPORTED 2
2684 #define VP_ERR_FAB_NORESOURCES 3
2685 #define VP_ERR_FAB_LOGOUT 4
2686 #define VP_ERR_ADAP_NORESOURCES 5
2687 struct qla_hw_data *hw;
2688 int req_ques[QLA_MAX_HOST_QUES];
2689 } scsi_qla_host_t;
2690
2691 /*
2692 * Macros to help code, maintain, etc.
2693 */
2694 #define LOOP_TRANSITION(ha) \
2695 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2696 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2697 atomic_read(&ha->loop_state) == LOOP_DOWN)
2698
2699 #define qla_printk(level, ha, format, arg...) \
2700 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2701
2702 /*
2703 * qla2x00 local function return status codes
2704 */
2705 #define MBS_MASK 0x3fff
2706
2707 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2708 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2709 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2710 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2711 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2712 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2713 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2714 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2715 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2716 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2717
2718 #define QLA_FUNCTION_TIMEOUT 0x100
2719 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2720 #define QLA_FUNCTION_FAILED 0x102
2721 #define QLA_MEMORY_ALLOC_FAILED 0x103
2722 #define QLA_LOCK_TIMEOUT 0x104
2723 #define QLA_ABORTED 0x105
2724 #define QLA_SUSPENDED 0x106
2725 #define QLA_BUSY 0x107
2726 #define QLA_RSCNS_HANDLED 0x108
2727 #define QLA_ALREADY_REGISTERED 0x109
2728
2729 #define NVRAM_DELAY() udelay(10)
2730
2731 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2732
2733 /*
2734 * Flash support definitions
2735 */
2736 #define OPTROM_SIZE_2300 0x20000
2737 #define OPTROM_SIZE_2322 0x100000
2738 #define OPTROM_SIZE_24XX 0x100000
2739 #define OPTROM_SIZE_25XX 0x200000
2740
2741 #include "qla_gbl.h"
2742 #include "qla_dbg.h"
2743 #include "qla_inline.h"
2744
2745 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2746 #define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2747 #define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2748 #define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2749 #define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2750 #define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2751
2752 #endif
Linux kernel - Deliverables
This page took 0.084398 seconds and 6 git commands to generate.