projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge master.kernel.org:/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_fw.h
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_FW_H
8 #define __QLA_FW_H
9
10 #define MBS_CHECKSUM_ERROR 0x4010
11
12 /*
13 * Firmware Options.
14 */
15 #define FO1_ENABLE_PUREX BIT_10
16 #define FO1_DISABLE_LED_CTRL BIT_6
17 #define FO2_ENABLE_SEL_CLASS2 BIT_5
18 #define FO3_NO_ABTS_ON_LINKDOWN BIT_14
19
20 /*
21 * Port Database structure definition for ISP 24xx.
22 */
23 #define PDO_FORCE_ADISC BIT_1
24 #define PDO_FORCE_PLOGI BIT_0
25
26
27 #define PORT_DATABASE_24XX_SIZE 64
28 struct port_database_24xx {
29 uint16_t flags;
30 #define PDF_TASK_RETRY_ID BIT_14
31 #define PDF_FC_TAPE BIT_7
32 #define PDF_ACK0_CAPABLE BIT_6
33 #define PDF_FCP2_CONF BIT_5
34 #define PDF_CLASS_2 BIT_4
35 #define PDF_HARD_ADDR BIT_1
36
37 uint8_t current_login_state;
38 uint8_t last_login_state;
39 #define PDS_PLOGI_PENDING 0x03
40 #define PDS_PLOGI_COMPLETE 0x04
41 #define PDS_PRLI_PENDING 0x05
42 #define PDS_PRLI_COMPLETE 0x06
43 #define PDS_PORT_UNAVAILABLE 0x07
44 #define PDS_PRLO_PENDING 0x09
45 #define PDS_LOGO_PENDING 0x11
46 #define PDS_PRLI2_PENDING 0x12
47
48 uint8_t hard_address[3];
49 uint8_t reserved_1;
50
51 uint8_t port_id[3];
52 uint8_t sequence_id;
53
54 uint16_t port_timer;
55
56 uint16_t nport_handle; /* N_PORT handle. */
57
58 uint16_t receive_data_size;
59 uint16_t reserved_2;
60
61 uint8_t prli_svc_param_word_0[2]; /* Big endian */
62 /* Bits 15-0 of word 0 */
63 uint8_t prli_svc_param_word_3[2]; /* Big endian */
64 /* Bits 15-0 of word 3 */
65
66 uint8_t port_name[WWN_SIZE];
67 uint8_t node_name[WWN_SIZE];
68
69 uint8_t reserved_3[24];
70 };
71
72 struct vp_database_24xx {
73 uint16_t vp_status;
74 uint8_t options;
75 uint8_t id;
76 uint8_t port_name[WWN_SIZE];
77 uint8_t node_name[WWN_SIZE];
78 uint16_t port_id_low;
79 uint16_t port_id_high;
80 };
81
82 struct nvram_24xx {
83 /* NVRAM header. */
84 uint8_t id[4];
85 uint16_t nvram_version;
86 uint16_t reserved_0;
87
88 /* Firmware Initialization Control Block. */
89 uint16_t version;
90 uint16_t reserved_1;
91 uint16_t frame_payload_size;
92 uint16_t execution_throttle;
93 uint16_t exchange_count;
94 uint16_t hard_address;
95
96 uint8_t port_name[WWN_SIZE];
97 uint8_t node_name[WWN_SIZE];
98
99 uint16_t login_retry_count;
100 uint16_t link_down_on_nos;
101 uint16_t interrupt_delay_timer;
102 uint16_t login_timeout;
103
104 uint32_t firmware_options_1;
105 uint32_t firmware_options_2;
106 uint32_t firmware_options_3;
107
108 /* Offset 56. */
109
110 /*
111 * BIT 0 = Control Enable
112 * BIT 1-15 =
113 *
114 * BIT 0-7 = Reserved
115 * BIT 8-10 = Output Swing 1G
116 * BIT 11-13 = Output Emphasis 1G
117 * BIT 14-15 = Reserved
118 *
119 * BIT 0-7 = Reserved
120 * BIT 8-10 = Output Swing 2G
121 * BIT 11-13 = Output Emphasis 2G
122 * BIT 14-15 = Reserved
123 *
124 * BIT 0-7 = Reserved
125 * BIT 8-10 = Output Swing 4G
126 * BIT 11-13 = Output Emphasis 4G
127 * BIT 14-15 = Reserved
128 */
129 uint16_t seriallink_options[4];
130
131 uint16_t reserved_2[16];
132
133 /* Offset 96. */
134 uint16_t reserved_3[16];
135
136 /* PCIe table entries. */
137 uint16_t reserved_4[16];
138
139 /* Offset 160. */
140 uint16_t reserved_5[16];
141
142 /* Offset 192. */
143 uint16_t reserved_6[16];
144
145 /* Offset 224. */
146 uint16_t reserved_7[16];
147
148 /*
149 * BIT 0 = Enable spinup delay
150 * BIT 1 = Disable BIOS
151 * BIT 2 = Enable Memory Map BIOS
152 * BIT 3 = Enable Selectable Boot
153 * BIT 4 = Disable RISC code load
154 * BIT 5 = Disable Serdes
155 * BIT 6 =
156 * BIT 7 =
157 *
158 * BIT 8 =
159 * BIT 9 =
160 * BIT 10 = Enable lip full login
161 * BIT 11 = Enable target reset
162 * BIT 12 =
163 * BIT 13 =
164 * BIT 14 =
165 * BIT 15 = Enable alternate WWN
166 *
167 * BIT 16-31 =
168 */
169 uint32_t host_p;
170
171 uint8_t alternate_port_name[WWN_SIZE];
172 uint8_t alternate_node_name[WWN_SIZE];
173
174 uint8_t boot_port_name[WWN_SIZE];
175 uint16_t boot_lun_number;
176 uint16_t reserved_8;
177
178 uint8_t alt1_boot_port_name[WWN_SIZE];
179 uint16_t alt1_boot_lun_number;
180 uint16_t reserved_9;
181
182 uint8_t alt2_boot_port_name[WWN_SIZE];
183 uint16_t alt2_boot_lun_number;
184 uint16_t reserved_10;
185
186 uint8_t alt3_boot_port_name[WWN_SIZE];
187 uint16_t alt3_boot_lun_number;
188 uint16_t reserved_11;
189
190 /*
191 * BIT 0 = Selective Login
192 * BIT 1 = Alt-Boot Enable
193 * BIT 2 = Reserved
194 * BIT 3 = Boot Order List
195 * BIT 4 = Reserved
196 * BIT 5 = Selective LUN
197 * BIT 6 = Reserved
198 * BIT 7-31 =
199 */
200 uint32_t efi_parameters;
201
202 uint8_t reset_delay;
203 uint8_t reserved_12;
204 uint16_t reserved_13;
205
206 uint16_t boot_id_number;
207 uint16_t reserved_14;
208
209 uint16_t max_luns_per_target;
210 uint16_t reserved_15;
211
212 uint16_t port_down_retry_count;
213 uint16_t link_down_timeout;
214
215 /* FCode parameters. */
216 uint16_t fcode_parameter;
217
218 uint16_t reserved_16[3];
219
220 /* Offset 352. */
221 uint8_t prev_drv_ver_major;
222 uint8_t prev_drv_ver_submajob;
223 uint8_t prev_drv_ver_minor;
224 uint8_t prev_drv_ver_subminor;
225
226 uint16_t prev_bios_ver_major;
227 uint16_t prev_bios_ver_minor;
228
229 uint16_t prev_efi_ver_major;
230 uint16_t prev_efi_ver_minor;
231
232 uint16_t prev_fw_ver_major;
233 uint8_t prev_fw_ver_minor;
234 uint8_t prev_fw_ver_subminor;
235
236 uint16_t reserved_17[8];
237
238 /* Offset 384. */
239 uint16_t reserved_18[16];
240
241 /* Offset 416. */
242 uint16_t reserved_19[16];
243
244 /* Offset 448. */
245 uint16_t reserved_20[16];
246
247 /* Offset 480. */
248 uint8_t model_name[16];
249
250 uint16_t reserved_21[2];
251
252 /* Offset 500. */
253 /* HW Parameter Block. */
254 uint16_t pcie_table_sig;
255 uint16_t pcie_table_offset;
256
257 uint16_t subsystem_vendor_id;
258 uint16_t subsystem_device_id;
259
260 uint32_t checksum;
261 };
262
263 /*
264 * ISP Initialization Control Block.
265 * Little endian except where noted.
266 */
267 #define ICB_VERSION 1
268 struct init_cb_24xx {
269 uint16_t version;
270 uint16_t reserved_1;
271
272 uint16_t frame_payload_size;
273 uint16_t execution_throttle;
274 uint16_t exchange_count;
275
276 uint16_t hard_address;
277
278 uint8_t port_name[WWN_SIZE]; /* Big endian. */
279 uint8_t node_name[WWN_SIZE]; /* Big endian. */
280
281 uint16_t response_q_inpointer;
282 uint16_t request_q_outpointer;
283
284 uint16_t login_retry_count;
285
286 uint16_t prio_request_q_outpointer;
287
288 uint16_t response_q_length;
289 uint16_t request_q_length;
290
291 uint16_t link_down_on_nos; /* Milliseconds. */
292
293 uint16_t prio_request_q_length;
294
295 uint32_t request_q_address[2];
296 uint32_t response_q_address[2];
297 uint32_t prio_request_q_address[2];
298
299 uint8_t reserved_2[8];
300
301 uint16_t atio_q_inpointer;
302 uint16_t atio_q_length;
303 uint32_t atio_q_address[2];
304
305 uint16_t interrupt_delay_timer; /* 100us increments. */
306 uint16_t login_timeout;
307
308 /*
309 * BIT 0 = Enable Hard Loop Id
310 * BIT 1 = Enable Fairness
311 * BIT 2 = Enable Full-Duplex
312 * BIT 3 = Reserved
313 * BIT 4 = Enable Target Mode
314 * BIT 5 = Disable Initiator Mode
315 * BIT 6 = Reserved
316 * BIT 7 = Reserved
317 *
318 * BIT 8 = Reserved
319 * BIT 9 = Non Participating LIP
320 * BIT 10 = Descending Loop ID Search
321 * BIT 11 = Acquire Loop ID in LIPA
322 * BIT 12 = Reserved
323 * BIT 13 = Full Login after LIP
324 * BIT 14 = Node Name Option
325 * BIT 15-31 = Reserved
326 */
327 uint32_t firmware_options_1;
328
329 /*
330 * BIT 0 = Operation Mode bit 0
331 * BIT 1 = Operation Mode bit 1
332 * BIT 2 = Operation Mode bit 2
333 * BIT 3 = Operation Mode bit 3
334 * BIT 4 = Connection Options bit 0
335 * BIT 5 = Connection Options bit 1
336 * BIT 6 = Connection Options bit 2
337 * BIT 7 = Enable Non part on LIHA failure
338 *
339 * BIT 8 = Enable Class 2
340 * BIT 9 = Enable ACK0
341 * BIT 10 = Reserved
342 * BIT 11 = Enable FC-SP Security
343 * BIT 12 = FC Tape Enable
344 * BIT 13-31 = Reserved
345 */
346 uint32_t firmware_options_2;
347
348 /*
349 * BIT 0 = Reserved
350 * BIT 1 = Soft ID only
351 * BIT 2 = Reserved
352 * BIT 3 = Reserved
353 * BIT 4 = FCP RSP Payload bit 0
354 * BIT 5 = FCP RSP Payload bit 1
355 * BIT 6 = Enable Receive Out-of-Order data frame handling
356 * BIT 7 = Disable Automatic PLOGI on Local Loop
357 *
358 * BIT 8 = Reserved
359 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling
360 * BIT 10 = Reserved
361 * BIT 11 = Reserved
362 * BIT 12 = Reserved
363 * BIT 13 = Data Rate bit 0
364 * BIT 14 = Data Rate bit 1
365 * BIT 15 = Data Rate bit 2
366 * BIT 16-31 = Reserved
367 */
368 uint32_t firmware_options_3;
369
370 uint8_t reserved_3[24];
371 };
372
373 /*
374 * ISP queue - command entry structure definition.
375 */
376 #define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */
377 struct cmd_type_6 {
378 uint8_t entry_type; /* Entry type. */
379 uint8_t entry_count; /* Entry count. */
380 uint8_t sys_define; /* System defined. */
381 uint8_t entry_status; /* Entry Status. */
382
383 uint32_t handle; /* System handle. */
384
385 uint16_t nport_handle; /* N_PORT handle. */
386 uint16_t timeout; /* Command timeout. */
387
388 uint16_t dseg_count; /* Data segment count. */
389
390 uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */
391
392 struct scsi_lun lun; /* FCP LUN (BE). */
393
394 uint16_t control_flags; /* Control flags. */
395 #define CF_DATA_SEG_DESCR_ENABLE BIT_2
396 #define CF_READ_DATA BIT_1
397 #define CF_WRITE_DATA BIT_0
398
399 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */
400 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
401
402 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */
403
404 uint32_t byte_count; /* Total byte count. */
405
406 uint8_t port_id[3]; /* PortID of destination port. */
407 uint8_t vp_index;
408
409 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */
410 uint16_t fcp_data_dseg_len; /* Data segment length. */
411 uint16_t reserved_1; /* MUST be set to 0. */
412 };
413
414 #define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */
415 struct cmd_type_7 {
416 uint8_t entry_type; /* Entry type. */
417 uint8_t entry_count; /* Entry count. */
418 uint8_t sys_define; /* System defined. */
419 uint8_t entry_status; /* Entry Status. */
420
421 uint32_t handle; /* System handle. */
422
423 uint16_t nport_handle; /* N_PORT handle. */
424 uint16_t timeout; /* Command timeout. */
425 #define FW_MAX_TIMEOUT 0x1999
426
427 uint16_t dseg_count; /* Data segment count. */
428 uint16_t reserved_1;
429
430 struct scsi_lun lun; /* FCP LUN (BE). */
431
432 uint16_t task_mgmt_flags; /* Task management flags. */
433 #define TMF_CLEAR_ACA BIT_14
434 #define TMF_TARGET_RESET BIT_13
435 #define TMF_LUN_RESET BIT_12
436 #define TMF_CLEAR_TASK_SET BIT_10
437 #define TMF_ABORT_TASK_SET BIT_9
438 #define TMF_READ_DATA BIT_1
439 #define TMF_WRITE_DATA BIT_0
440
441 uint8_t task;
442 #define TSK_SIMPLE 0
443 #define TSK_HEAD_OF_QUEUE 1
444 #define TSK_ORDERED 2
445 #define TSK_ACA 4
446 #define TSK_UNTAGGED 5
447
448 uint8_t crn;
449
450 uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */
451 uint32_t byte_count; /* Total byte count. */
452
453 uint8_t port_id[3]; /* PortID of destination port. */
454 uint8_t vp_index;
455
456 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
457 uint32_t dseg_0_len; /* Data segment 0 length. */
458 };
459
460 /*
461 * ISP queue - status entry structure definition.
462 */
463 #define STATUS_TYPE 0x03 /* Status entry. */
464 struct sts_entry_24xx {
465 uint8_t entry_type; /* Entry type. */
466 uint8_t entry_count; /* Entry count. */
467 uint8_t sys_define; /* System defined. */
468 uint8_t entry_status; /* Entry Status. */
469
470 uint32_t handle; /* System handle. */
471
472 uint16_t comp_status; /* Completion status. */
473 uint16_t ox_id; /* OX_ID used by the firmware. */
474
475 uint32_t residual_len; /* FW calc residual transfer length. */
476
477 uint16_t reserved_1;
478 uint16_t state_flags; /* State flags. */
479 #define SF_TRANSFERRED_DATA BIT_11
480 #define SF_FCP_RSP_DMA BIT_0
481
482 uint16_t reserved_2;
483 uint16_t scsi_status; /* SCSI status. */
484 #define SS_CONFIRMATION_REQ BIT_12
485
486 uint32_t rsp_residual_count; /* FCP RSP residual count. */
487
488 uint32_t sense_len; /* FCP SENSE length. */
489 uint32_t rsp_data_len; /* FCP response data length. */
490
491 uint8_t data[28]; /* FCP response/sense information. */
492 };
493
494 /*
495 * Status entry completion status
496 */
497 #define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */
498 #define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */
499 #define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */
500 #define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */
501 #define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */
502
503 /*
504 * ISP queue - marker entry structure definition.
505 */
506 #define MARKER_TYPE 0x04 /* Marker entry. */
507 struct mrk_entry_24xx {
508 uint8_t entry_type; /* Entry type. */
509 uint8_t entry_count; /* Entry count. */
510 uint8_t handle_count; /* Handle count. */
511 uint8_t entry_status; /* Entry Status. */
512
513 uint32_t handle; /* System handle. */
514
515 uint16_t nport_handle; /* N_PORT handle. */
516
517 uint8_t modifier; /* Modifier (7-0). */
518 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
519 #define MK_SYNC_ID 1 /* Synchronize ID */
520 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
521 uint8_t reserved_1;
522
523 uint8_t reserved_2;
524 uint8_t vp_index;
525
526 uint16_t reserved_3;
527
528 uint8_t lun[8]; /* FCP LUN (BE). */
529 uint8_t reserved_4[40];
530 };
531
532 /*
533 * ISP queue - CT Pass-Through entry structure definition.
534 */
535 #define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */
536 struct ct_entry_24xx {
537 uint8_t entry_type; /* Entry type. */
538 uint8_t entry_count; /* Entry count. */
539 uint8_t sys_define; /* System Defined. */
540 uint8_t entry_status; /* Entry Status. */
541
542 uint32_t handle; /* System handle. */
543
544 uint16_t comp_status; /* Completion status. */
545
546 uint16_t nport_handle; /* N_PORT handle. */
547
548 uint16_t cmd_dsd_count;
549
550 uint8_t vp_index;
551 uint8_t reserved_1;
552
553 uint16_t timeout; /* Command timeout. */
554 uint16_t reserved_2;
555
556 uint16_t rsp_dsd_count;
557
558 uint8_t reserved_3[10];
559
560 uint32_t rsp_byte_count;
561 uint32_t cmd_byte_count;
562
563 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
564 uint32_t dseg_0_len; /* Data segment 0 length. */
565 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
566 uint32_t dseg_1_len; /* Data segment 1 length. */
567 };
568
569 /*
570 * ISP queue - ELS Pass-Through entry structure definition.
571 */
572 #define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */
573 struct els_entry_24xx {
574 uint8_t entry_type; /* Entry type. */
575 uint8_t entry_count; /* Entry count. */
576 uint8_t sys_define; /* System Defined. */
577 uint8_t entry_status; /* Entry Status. */
578
579 uint32_t handle; /* System handle. */
580
581 uint16_t reserved_1;
582
583 uint16_t nport_handle; /* N_PORT handle. */
584
585 uint16_t tx_dsd_count;
586
587 uint8_t vp_index;
588 uint8_t sof_type;
589 #define EST_SOFI3 (1 << 4)
590 #define EST_SOFI2 (3 << 4)
591
592 uint32_t rx_xchg_address[2]; /* Receive exchange address. */
593 uint16_t rx_dsd_count;
594
595 uint8_t opcode;
596 uint8_t reserved_2;
597
598 uint8_t port_id[3];
599 uint8_t reserved_3;
600
601 uint16_t reserved_4;
602
603 uint16_t control_flags; /* Control flags. */
604 #define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13)
605 #define EPD_ELS_COMMAND (0 << 13)
606 #define EPD_ELS_ACC (1 << 13)
607 #define EPD_ELS_RJT (2 << 13)
608 #define EPD_RX_XCHG (3 << 13)
609 #define ECF_CLR_PASSTHRU_PEND BIT_12
610 #define ECF_INCL_FRAME_HDR BIT_11
611
612 uint32_t rx_byte_count;
613 uint32_t tx_byte_count;
614
615 uint32_t tx_address[2]; /* Data segment 0 address. */
616 uint32_t tx_len; /* Data segment 0 length. */
617 uint32_t rx_address[2]; /* Data segment 1 address. */
618 uint32_t rx_len; /* Data segment 1 length. */
619 };
620
621 /*
622 * ISP queue - Mailbox Command entry structure definition.
623 */
624 #define MBX_IOCB_TYPE 0x39
625 struct mbx_entry_24xx {
626 uint8_t entry_type; /* Entry type. */
627 uint8_t entry_count; /* Entry count. */
628 uint8_t handle_count; /* Handle count. */
629 uint8_t entry_status; /* Entry Status. */
630
631 uint32_t handle; /* System handle. */
632
633 uint16_t mbx[28];
634 };
635
636
637 #define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */
638 struct logio_entry_24xx {
639 uint8_t entry_type; /* Entry type. */
640 uint8_t entry_count; /* Entry count. */
641 uint8_t sys_define; /* System defined. */
642 uint8_t entry_status; /* Entry Status. */
643
644 uint32_t handle; /* System handle. */
645
646 uint16_t comp_status; /* Completion status. */
647 #define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */
648
649 uint16_t nport_handle; /* N_PORT handle. */
650
651 uint16_t control_flags; /* Control flags. */
652 /* Modifiers. */
653 #define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */
654 #define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */
655 #define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */
656 #define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */
657 #define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */
658 #define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */
659 #define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */
660 #define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */
661 #define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */
662 /* Commands. */
663 #define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */
664 #define LCF_COMMAND_PRLI 0x01 /* PRLI. */
665 #define LCF_COMMAND_PDISC 0x02 /* PDISC. */
666 #define LCF_COMMAND_ADISC 0x03 /* ADISC. */
667 #define LCF_COMMAND_LOGO 0x08 /* LOGO. */
668 #define LCF_COMMAND_PRLO 0x09 /* PRLO. */
669 #define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */
670
671 uint8_t vp_index;
672 uint8_t reserved_1;
673
674 uint8_t port_id[3]; /* PortID of destination port. */
675
676 uint8_t rsp_size; /* Response size in 32bit words. */
677
678 uint32_t io_parameter[11]; /* General I/O parameters. */
679 #define LSC_SCODE_NOLINK 0x01
680 #define LSC_SCODE_NOIOCB 0x02
681 #define LSC_SCODE_NOXCB 0x03
682 #define LSC_SCODE_CMD_FAILED 0x04
683 #define LSC_SCODE_NOFABRIC 0x05
684 #define LSC_SCODE_FW_NOT_READY 0x07
685 #define LSC_SCODE_NOT_LOGGED_IN 0x09
686 #define LSC_SCODE_NOPCB 0x0A
687
688 #define LSC_SCODE_ELS_REJECT 0x18
689 #define LSC_SCODE_CMD_PARAM_ERR 0x19
690 #define LSC_SCODE_PORTID_USED 0x1A
691 #define LSC_SCODE_NPORT_USED 0x1B
692 #define LSC_SCODE_NONPORT 0x1C
693 #define LSC_SCODE_LOGGED_IN 0x1D
694 #define LSC_SCODE_NOFLOGI_ACC 0x1F
695 };
696
697 #define TSK_MGMT_IOCB_TYPE 0x14
698 struct tsk_mgmt_entry {
699 uint8_t entry_type; /* Entry type. */
700 uint8_t entry_count; /* Entry count. */
701 uint8_t handle_count; /* Handle count. */
702 uint8_t entry_status; /* Entry Status. */
703
704 uint32_t handle; /* System handle. */
705
706 uint16_t nport_handle; /* N_PORT handle. */
707
708 uint16_t reserved_1;
709
710 uint16_t delay; /* Activity delay in seconds. */
711
712 uint16_t timeout; /* Command timeout. */
713
714 uint8_t lun[8]; /* FCP LUN (BE). */
715
716 uint32_t control_flags; /* Control Flags. */
717 #define TCF_NOTMCMD_TO_TARGET BIT_31
718 #define TCF_LUN_RESET BIT_4
719 #define TCF_ABORT_TASK_SET BIT_3
720 #define TCF_CLEAR_TASK_SET BIT_2
721 #define TCF_TARGET_RESET BIT_1
722 #define TCF_CLEAR_ACA BIT_0
723
724 uint8_t reserved_2[20];
725
726 uint8_t port_id[3]; /* PortID of destination port. */
727 uint8_t vp_index;
728
729 uint8_t reserved_3[12];
730 };
731
732 #define ABORT_IOCB_TYPE 0x33
733 struct abort_entry_24xx {
734 uint8_t entry_type; /* Entry type. */
735 uint8_t entry_count; /* Entry count. */
736 uint8_t handle_count; /* Handle count. */
737 uint8_t entry_status; /* Entry Status. */
738
739 uint32_t handle; /* System handle. */
740
741 uint16_t nport_handle; /* N_PORT handle. */
742 /* or Completion status. */
743
744 uint16_t options; /* Options. */
745 #define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */
746
747 uint32_t handle_to_abort; /* System handle to abort. */
748
749 uint8_t reserved_1[32];
750
751 uint8_t port_id[3]; /* PortID of destination port. */
752 uint8_t vp_index;
753
754 uint8_t reserved_2[12];
755 };
756
757 /*
758 * ISP I/O Register Set structure definitions.
759 */
760 struct device_reg_24xx {
761 uint32_t flash_addr; /* Flash/NVRAM BIOS address. */
762 #define FARX_DATA_FLAG BIT_31
763 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000
764 #define FARX_ACCESS_FLASH_DATA 0x7FF00000
765 #define FARX_ACCESS_NVRAM_CONF 0x7FFF0000
766 #define FARX_ACCESS_NVRAM_DATA 0x7FFE0000
767
768 #define FA_NVRAM_FUNC0_ADDR 0x80
769 #define FA_NVRAM_FUNC1_ADDR 0x180
770
771 #define FA_NVRAM_VPD_SIZE 0x200
772 #define FA_NVRAM_VPD0_ADDR 0x00
773 #define FA_NVRAM_VPD1_ADDR 0x100
774 /*
775 * RISC code begins at offset 512KB
776 * within flash. Consisting of two
777 * contiguous RISC code segments.
778 */
779 #define FA_RISC_CODE_ADDR 0x20000
780 #define FA_RISC_CODE_SEGMENTS 2
781
782 uint32_t flash_data; /* Flash/NVRAM BIOS data. */
783
784 uint32_t ctrl_status; /* Control/Status. */
785 #define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */
786 #define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */
787 #define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */
788 #define CSRX_FUNCTION BIT_15 /* Function number. */
789 /* PCI-X Bus Mode. */
790 #define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8)
791 #define PBM_PCI_33MHZ (0 << 8)
792 #define PBM_PCIX_M1_66MHZ (1 << 8)
793 #define PBM_PCIX_M1_100MHZ (2 << 8)
794 #define PBM_PCIX_M1_133MHZ (3 << 8)
795 #define PBM_PCIX_M2_66MHZ (5 << 8)
796 #define PBM_PCIX_M2_100MHZ (6 << 8)
797 #define PBM_PCIX_M2_133MHZ (7 << 8)
798 #define PBM_PCI_66MHZ (8 << 8)
799 /* Max Write Burst byte count. */
800 #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)
801 #define MWB_512_BYTES (0 << 4)
802 #define MWB_1024_BYTES (1 << 4)
803 #define MWB_2048_BYTES (2 << 4)
804 #define MWB_4096_BYTES (3 << 4)
805
806 #define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */
807 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
808 #define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */
809
810 uint32_t ictrl; /* Interrupt control. */
811 #define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */
812
813 uint32_t istatus; /* Interrupt status. */
814 #define ISRX_RISC_INT BIT_3 /* RISC interrupt. */
815
816 uint32_t unused_1[2]; /* Gap. */
817
818 /* Request Queue. */
819 uint32_t req_q_in; /* In-Pointer. */
820 uint32_t req_q_out; /* Out-Pointer. */
821 /* Response Queue. */
822 uint32_t rsp_q_in; /* In-Pointer. */
823 uint32_t rsp_q_out; /* Out-Pointer. */
824 /* Priority Request Queue. */
825 uint32_t preq_q_in; /* In-Pointer. */
826 uint32_t preq_q_out; /* Out-Pointer. */
827
828 uint32_t unused_2[2]; /* Gap. */
829
830 /* ATIO Queue. */
831 uint32_t atio_q_in; /* In-Pointer. */
832 uint32_t atio_q_out; /* Out-Pointer. */
833
834 uint32_t host_status;
835 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
836 #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
837
838 uint32_t hccr; /* Host command & control register. */
839 /* HCCR statuses. */
840 #define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */
841 #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */
842 #define HCCRX_RISC_PAUSE BIT_4 /* RISC Pause mode bit. */
843 /* HCCR commands. */
844 /* NOOP. */
845 #define HCCRX_NOOP 0x00000000
846 /* Set RISC Reset. */
847 #define HCCRX_SET_RISC_RESET 0x10000000
848 /* Clear RISC Reset. */
849 #define HCCRX_CLR_RISC_RESET 0x20000000
850 /* Set RISC Pause. */
851 #define HCCRX_SET_RISC_PAUSE 0x30000000
852 /* Releases RISC Pause. */
853 #define HCCRX_REL_RISC_PAUSE 0x40000000
854 /* Set HOST to RISC interrupt. */
855 #define HCCRX_SET_HOST_INT 0x50000000
856 /* Clear HOST to RISC interrupt. */
857 #define HCCRX_CLR_HOST_INT 0x60000000
858 /* Clear RISC to PCI interrupt. */
859 #define HCCRX_CLR_RISC_INT 0xA0000000
860
861 uint32_t gpiod; /* GPIO Data register. */
862 /* LED update mask. */
863 #define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18)
864 /* Data update mask. */
865 #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16)
866 /* LED control mask. */
867 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)
868 /* LED bit values. Color names as
869 * referenced in fw spec.
870 */
871 #define GPDX_LED_YELLOW_ON BIT_2
872 #define GPDX_LED_GREEN_ON BIT_3
873 #define GPDX_LED_AMBER_ON BIT_4
874 /* Data in/out. */
875 #define GPDX_DATA_INOUT (BIT_1|BIT_0)
876
877 uint32_t gpioe; /* GPIO Enable register. */
878 /* Enable update mask. */
879 #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16)
880 /* Enable. */
881 #define GPEX_ENABLE (BIT_1|BIT_0)
882
883 uint32_t iobase_addr; /* I/O Bus Base Address register. */
884
885 uint32_t unused_3[10]; /* Gap. */
886
887 uint16_t mailbox0;
888 uint16_t mailbox1;
889 uint16_t mailbox2;
890 uint16_t mailbox3;
891 uint16_t mailbox4;
892 uint16_t mailbox5;
893 uint16_t mailbox6;
894 uint16_t mailbox7;
895 uint16_t mailbox8;
896 uint16_t mailbox9;
897 uint16_t mailbox10;
898 uint16_t mailbox11;
899 uint16_t mailbox12;
900 uint16_t mailbox13;
901 uint16_t mailbox14;
902 uint16_t mailbox15;
903 uint16_t mailbox16;
904 uint16_t mailbox17;
905 uint16_t mailbox18;
906 uint16_t mailbox19;
907 uint16_t mailbox20;
908 uint16_t mailbox21;
909 uint16_t mailbox22;
910 uint16_t mailbox23;
911 uint16_t mailbox24;
912 uint16_t mailbox25;
913 uint16_t mailbox26;
914 uint16_t mailbox27;
915 uint16_t mailbox28;
916 uint16_t mailbox29;
917 uint16_t mailbox30;
918 uint16_t mailbox31;
919 };
920
921 /* MID Support ***************************************************************/
922
923 #define MAX_MID_VPS 125
924
925 struct mid_conf_entry_24xx {
926 uint16_t reserved_1;
927
928 /*
929 * BIT 0 = Enable Hard Loop Id
930 * BIT 1 = Acquire Loop ID in LIPA
931 * BIT 2 = ID not Acquired
932 * BIT 3 = Enable VP
933 * BIT 4 = Enable Initiator Mode
934 * BIT 5 = Disable Target Mode
935 * BIT 6-7 = Reserved
936 */
937 uint8_t options;
938
939 uint8_t hard_address;
940
941 uint8_t port_name[WWN_SIZE];
942 uint8_t node_name[WWN_SIZE];
943 };
944
945 struct mid_init_cb_24xx {
946 struct init_cb_24xx init_cb;
947
948 uint16_t count;
949 uint16_t options;
950
951 struct mid_conf_entry_24xx entries[MAX_MID_VPS];
952 };
953
954
955 struct mid_db_entry_24xx {
956 uint16_t status;
957 #define MDBS_NON_PARTIC BIT_3
958 #define MDBS_ID_ACQUIRED BIT_1
959 #define MDBS_ENABLED BIT_0
960
961 uint8_t options;
962 uint8_t hard_address;
963
964 uint8_t port_name[WWN_SIZE];
965 uint8_t node_name[WWN_SIZE];
966
967 uint8_t port_id[3];
968 uint8_t reserved_1;
969 };
970
971 struct mid_db_24xx {
972 struct mid_db_entry_24xx entries[MAX_MID_VPS];
973 };
974
975 /*
976 * Virtual Fabric ID type definition.
977 */
978 typedef struct vf_id {
979 uint16_t id : 12;
980 uint16_t priority : 4;
981 } vf_id_t;
982
983 /*
984 * Virtual Fabric HopCt type definition.
985 */
986 typedef struct vf_hopct {
987 uint16_t reserved : 8;
988 uint16_t hopct : 8;
989 } vf_hopct_t;
990
991 /*
992 * Virtual Port Control IOCB
993 */
994 #define VP_CTRL_IOCB_TYPE 0x30 /* Vitual Port Control entry. */
995 struct vp_ctrl_entry_24xx {
996 uint8_t entry_type; /* Entry type. */
997 uint8_t entry_count; /* Entry count. */
998 uint8_t sys_define; /* System defined. */
999 uint8_t entry_status; /* Entry Status. */
1000
1001 uint32_t handle; /* System handle. */
1002
1003 uint16_t vp_idx_failed;
1004
1005 uint16_t comp_status; /* Completion status. */
1006 #define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */
1007 #define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */
1008 #define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */
1009
1010 uint16_t command;
1011 #define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */
1012 #define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */
1013 #define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */
1014 #define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */
1015 #define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */
1016
1017 uint16_t vp_count;
1018
1019 uint8_t vp_idx_map[16];
1020 uint16_t flags;
1021 struct vf_id id;
1022 uint16_t reserved_4;
1023 struct vf_hopct hopct;
1024 uint8_t reserved_5[8];
1025 };
1026
1027 /*
1028 * Modify Virtual Port Configuration IOCB
1029 */
1030 #define VP_CONFIG_IOCB_TYPE 0x31 /* Vitual Port Config entry. */
1031 struct vp_config_entry_24xx {
1032 uint8_t entry_type; /* Entry type. */
1033 uint8_t entry_count; /* Entry count. */
1034 uint8_t handle_count;
1035 uint8_t entry_status; /* Entry Status. */
1036
1037 uint32_t handle; /* System handle. */
1038
1039 uint16_t flags;
1040 #define CS_VF_BIND_VPORTS_TO_VF BIT_0
1041 #define CS_VF_SET_QOS_OF_VPORTS BIT_1
1042 #define CS_VF_SET_HOPS_OF_VPORTS BIT_2
1043
1044 uint16_t comp_status; /* Completion status. */
1045 #define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */
1046 #define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */
1047 #define CS_VCT_ERROR 0x03 /* Unknown error. */
1048 #define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */
1049 #define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */
1050
1051 uint8_t command;
1052 #define VCT_COMMAND_MOD_VPS 0x00 /* Modify VP configurations. */
1053 #define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */
1054
1055 uint8_t vp_count;
1056
1057 uint8_t vp_index1;
1058 uint8_t vp_index2;
1059
1060 uint8_t options_idx1;
1061 uint8_t hard_address_idx1;
1062 uint16_t reserved_vp1;
1063 uint8_t port_name_idx1[WWN_SIZE];
1064 uint8_t node_name_idx1[WWN_SIZE];
1065
1066 uint8_t options_idx2;
1067 uint8_t hard_address_idx2;
1068 uint16_t reserved_vp2;
1069 uint8_t port_name_idx2[WWN_SIZE];
1070 uint8_t node_name_idx2[WWN_SIZE];
1071 struct vf_id id;
1072 uint16_t reserved_4;
1073 struct vf_hopct hopct;
1074 uint8_t reserved_5;
1075 };
1076
1077 #define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */
1078 struct vp_rpt_id_entry_24xx {
1079 uint8_t entry_type; /* Entry type. */
1080 uint8_t entry_count; /* Entry count. */
1081 uint8_t sys_define; /* System defined. */
1082 uint8_t entry_status; /* Entry Status. */
1083
1084 uint32_t handle; /* System handle. */
1085
1086 uint16_t vp_count; /* Format 0 -- | VP setup | VP acq |. */
1087 /* Format 1 -- | VP count |. */
1088 uint16_t vp_idx; /* Format 0 -- Reserved. */
1089 /* Format 1 -- VP status and index. */
1090
1091 uint8_t port_id[3];
1092 uint8_t format;
1093
1094 uint8_t vp_idx_map[16];
1095
1096 uint8_t reserved_4[32];
1097 };
1098
1099 #define VF_EVFP_IOCB_TYPE 0x26 /* Exchange Virtual Fabric Parameters entry. */
1100 struct vf_evfp_entry_24xx {
1101 uint8_t entry_type; /* Entry type. */
1102 uint8_t entry_count; /* Entry count. */
1103 uint8_t sys_define; /* System defined. */
1104 uint8_t entry_status; /* Entry Status. */
1105
1106 uint32_t handle; /* System handle. */
1107 uint16_t comp_status; /* Completion status. */
1108 uint16_t timeout; /* timeout */
1109 uint16_t adim_tagging_mode;
1110
1111 uint16_t vfport_id;
1112 uint32_t exch_addr;
1113
1114 uint16_t nport_handle; /* N_PORT handle. */
1115 uint16_t control_flags;
1116 uint32_t io_parameter_0;
1117 uint32_t io_parameter_1;
1118 uint32_t tx_address[2]; /* Data segment 0 address. */
1119 uint32_t tx_len; /* Data segment 0 length. */
1120 uint32_t rx_address[2]; /* Data segment 1 address. */
1121 uint32_t rx_len; /* Data segment 1 length. */
1122 };
1123
1124 /* END MID Support ***********************************************************/
1125 #endif
Linux kernel - Deliverables
This page took 0.055153 seconds and 6 git commands to generate.