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97f268433b9f8100fc543d3259cfb19a6acbf4cb
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_init.c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2012 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8 #include "qla_gbl.h"
9
10 #include <linux/delay.h>
11 #include <linux/slab.h>
12 #include <linux/vmalloc.h>
13
14 #include "qla_devtbl.h"
15
16 #ifdef CONFIG_SPARC
17 #include <asm/prom.h>
18 #endif
19
20 #include <target/target_core_base.h>
21 #include "qla_target.h"
22
23 /*
24 * QLogic ISP2x00 Hardware Support Function Prototypes.
25 */
26 static int qla2x00_isp_firmware(scsi_qla_host_t *);
27 static int qla2x00_setup_chip(scsi_qla_host_t *);
28 static int qla2x00_init_rings(scsi_qla_host_t *);
29 static int qla2x00_fw_ready(scsi_qla_host_t *);
30 static int qla2x00_configure_hba(scsi_qla_host_t *);
31 static int qla2x00_configure_loop(scsi_qla_host_t *);
32 static int qla2x00_configure_local_loop(scsi_qla_host_t *);
33 static int qla2x00_configure_fabric(scsi_qla_host_t *);
34 static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
35 static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
36 uint16_t *);
37
38 static int qla2x00_restart_isp(scsi_qla_host_t *);
39
40 static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
41 static int qla84xx_init_chip(scsi_qla_host_t *);
42 static int qla25xx_init_queues(struct qla_hw_data *);
43
44 /* SRB Extensions ---------------------------------------------------------- */
45
46 void
47 qla2x00_sp_timeout(unsigned long __data)
48 {
49 srb_t *sp = (srb_t *)__data;
50 struct srb_iocb *iocb;
51 fc_port_t *fcport = sp->fcport;
52 struct qla_hw_data *ha = fcport->vha->hw;
53 struct req_que *req;
54 unsigned long flags;
55
56 spin_lock_irqsave(&ha->hardware_lock, flags);
57 req = ha->req_q_map[0];
58 req->outstanding_cmds[sp->handle] = NULL;
59 iocb = &sp->u.iocb_cmd;
60 iocb->timeout(sp);
61 sp->free(fcport->vha, sp);
62 spin_unlock_irqrestore(&ha->hardware_lock, flags);
63 }
64
65 void
66 qla2x00_sp_free(void *data, void *ptr)
67 {
68 srb_t *sp = (srb_t *)ptr;
69 struct srb_iocb *iocb = &sp->u.iocb_cmd;
70 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
71
72 del_timer(&iocb->timer);
73 mempool_free(sp, vha->hw->srb_mempool);
74
75 QLA_VHA_MARK_NOT_BUSY(vha);
76 }
77
78 /* Asynchronous Login/Logout Routines -------------------------------------- */
79
80 unsigned long
81 qla2x00_get_async_timeout(struct scsi_qla_host *vha)
82 {
83 unsigned long tmo;
84 struct qla_hw_data *ha = vha->hw;
85
86 /* Firmware should use switch negotiated r_a_tov for timeout. */
87 tmo = ha->r_a_tov / 10 * 2;
88 if (!IS_FWI2_CAPABLE(ha)) {
89 /*
90 * Except for earlier ISPs where the timeout is seeded from the
91 * initialization control block.
92 */
93 tmo = ha->login_timeout;
94 }
95 return tmo;
96 }
97
98 static void
99 qla2x00_async_iocb_timeout(void *data)
100 {
101 srb_t *sp = (srb_t *)data;
102 fc_port_t *fcport = sp->fcport;
103
104 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
105 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
106 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
107 fcport->d_id.b.al_pa);
108
109 fcport->flags &= ~FCF_ASYNC_SENT;
110 if (sp->type == SRB_LOGIN_CMD) {
111 struct srb_iocb *lio = &sp->u.iocb_cmd;
112 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
113 /* Retry as needed. */
114 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
115 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
116 QLA_LOGIO_LOGIN_RETRIED : 0;
117 qla2x00_post_async_login_done_work(fcport->vha, fcport,
118 lio->u.logio.data);
119 }
120 }
121
122 static void
123 qla2x00_async_login_sp_done(void *data, void *ptr, int res)
124 {
125 srb_t *sp = (srb_t *)ptr;
126 struct srb_iocb *lio = &sp->u.iocb_cmd;
127 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
128
129 if (!test_bit(UNLOADING, &vha->dpc_flags))
130 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
131 lio->u.logio.data);
132 sp->free(sp->fcport->vha, sp);
133 }
134
135 int
136 qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
137 uint16_t *data)
138 {
139 srb_t *sp;
140 struct srb_iocb *lio;
141 int rval;
142
143 rval = QLA_FUNCTION_FAILED;
144 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
145 if (!sp)
146 goto done;
147
148 sp->type = SRB_LOGIN_CMD;
149 sp->name = "login";
150 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
151
152 lio = &sp->u.iocb_cmd;
153 lio->timeout = qla2x00_async_iocb_timeout;
154 sp->done = qla2x00_async_login_sp_done;
155 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
156 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
157 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
158 rval = qla2x00_start_sp(sp);
159 if (rval != QLA_SUCCESS)
160 goto done_free_sp;
161
162 ql_dbg(ql_dbg_disc, vha, 0x2072,
163 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
164 "retries=%d.\n", sp->handle, fcport->loop_id,
165 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
166 fcport->login_retry);
167 return rval;
168
169 done_free_sp:
170 sp->free(fcport->vha, sp);
171 done:
172 return rval;
173 }
174
175 static void
176 qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
177 {
178 srb_t *sp = (srb_t *)ptr;
179 struct srb_iocb *lio = &sp->u.iocb_cmd;
180 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
181
182 if (!test_bit(UNLOADING, &vha->dpc_flags))
183 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
184 lio->u.logio.data);
185 sp->free(sp->fcport->vha, sp);
186 }
187
188 int
189 qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
190 {
191 srb_t *sp;
192 struct srb_iocb *lio;
193 int rval;
194
195 rval = QLA_FUNCTION_FAILED;
196 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
197 if (!sp)
198 goto done;
199
200 sp->type = SRB_LOGOUT_CMD;
201 sp->name = "logout";
202 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
203
204 lio = &sp->u.iocb_cmd;
205 lio->timeout = qla2x00_async_iocb_timeout;
206 sp->done = qla2x00_async_logout_sp_done;
207 rval = qla2x00_start_sp(sp);
208 if (rval != QLA_SUCCESS)
209 goto done_free_sp;
210
211 ql_dbg(ql_dbg_disc, vha, 0x2070,
212 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
213 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
214 fcport->d_id.b.area, fcport->d_id.b.al_pa);
215 return rval;
216
217 done_free_sp:
218 sp->free(fcport->vha, sp);
219 done:
220 return rval;
221 }
222
223 static void
224 qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
225 {
226 srb_t *sp = (srb_t *)ptr;
227 struct srb_iocb *lio = &sp->u.iocb_cmd;
228 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
229
230 if (!test_bit(UNLOADING, &vha->dpc_flags))
231 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
232 lio->u.logio.data);
233 sp->free(sp->fcport->vha, sp);
234 }
235
236 int
237 qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
238 uint16_t *data)
239 {
240 srb_t *sp;
241 struct srb_iocb *lio;
242 int rval;
243
244 rval = QLA_FUNCTION_FAILED;
245 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
246 if (!sp)
247 goto done;
248
249 sp->type = SRB_ADISC_CMD;
250 sp->name = "adisc";
251 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
252
253 lio = &sp->u.iocb_cmd;
254 lio->timeout = qla2x00_async_iocb_timeout;
255 sp->done = qla2x00_async_adisc_sp_done;
256 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
257 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
258 rval = qla2x00_start_sp(sp);
259 if (rval != QLA_SUCCESS)
260 goto done_free_sp;
261
262 ql_dbg(ql_dbg_disc, vha, 0x206f,
263 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
264 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
265 fcport->d_id.b.area, fcport->d_id.b.al_pa);
266 return rval;
267
268 done_free_sp:
269 sp->free(fcport->vha, sp);
270 done:
271 return rval;
272 }
273
274 static void
275 qla2x00_async_tm_cmd_done(void *data, void *ptr, int res)
276 {
277 srb_t *sp = (srb_t *)ptr;
278 struct srb_iocb *iocb = &sp->u.iocb_cmd;
279 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
280 uint32_t flags;
281 uint16_t lun;
282 int rval;
283
284 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
285 flags = iocb->u.tmf.flags;
286 lun = (uint16_t)iocb->u.tmf.lun;
287
288 /* Issue Marker IOCB */
289 rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
290 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
291 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
292
293 if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
294 ql_dbg(ql_dbg_taskm, vha, 0x8030,
295 "TM IOCB failed (%x).\n", rval);
296 }
297 }
298 sp->free(sp->fcport->vha, sp);
299 }
300
301 int
302 qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun,
303 uint32_t tag)
304 {
305 struct scsi_qla_host *vha = fcport->vha;
306 srb_t *sp;
307 struct srb_iocb *tcf;
308 int rval;
309
310 rval = QLA_FUNCTION_FAILED;
311 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
312 if (!sp)
313 goto done;
314
315 sp->type = SRB_TM_CMD;
316 sp->name = "tmf";
317 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
318
319 tcf = &sp->u.iocb_cmd;
320 tcf->u.tmf.flags = tm_flags;
321 tcf->u.tmf.lun = lun;
322 tcf->u.tmf.data = tag;
323 tcf->timeout = qla2x00_async_iocb_timeout;
324 sp->done = qla2x00_async_tm_cmd_done;
325
326 rval = qla2x00_start_sp(sp);
327 if (rval != QLA_SUCCESS)
328 goto done_free_sp;
329
330 ql_dbg(ql_dbg_taskm, vha, 0x802f,
331 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
332 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
333 fcport->d_id.b.area, fcport->d_id.b.al_pa);
334 return rval;
335
336 done_free_sp:
337 sp->free(fcport->vha, sp);
338 done:
339 return rval;
340 }
341
342 void
343 qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
344 uint16_t *data)
345 {
346 int rval;
347
348 switch (data[0]) {
349 case MBS_COMMAND_COMPLETE:
350 /*
351 * Driver must validate login state - If PRLI not complete,
352 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
353 * requests.
354 */
355 rval = qla2x00_get_port_database(vha, fcport, 0);
356 if (rval == QLA_NOT_LOGGED_IN) {
357 fcport->flags &= ~FCF_ASYNC_SENT;
358 fcport->flags |= FCF_LOGIN_NEEDED;
359 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
360 break;
361 }
362
363 if (rval != QLA_SUCCESS) {
364 qla2x00_post_async_logout_work(vha, fcport, NULL);
365 qla2x00_post_async_login_work(vha, fcport, NULL);
366 break;
367 }
368 if (fcport->flags & FCF_FCP2_DEVICE) {
369 qla2x00_post_async_adisc_work(vha, fcport, data);
370 break;
371 }
372 qla2x00_update_fcport(vha, fcport);
373 break;
374 case MBS_COMMAND_ERROR:
375 fcport->flags &= ~FCF_ASYNC_SENT;
376 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
377 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
378 else
379 qla2x00_mark_device_lost(vha, fcport, 1, 0);
380 break;
381 case MBS_PORT_ID_USED:
382 fcport->loop_id = data[1];
383 qla2x00_post_async_logout_work(vha, fcport, NULL);
384 qla2x00_post_async_login_work(vha, fcport, NULL);
385 break;
386 case MBS_LOOP_ID_USED:
387 fcport->loop_id++;
388 rval = qla2x00_find_new_loop_id(vha, fcport);
389 if (rval != QLA_SUCCESS) {
390 fcport->flags &= ~FCF_ASYNC_SENT;
391 qla2x00_mark_device_lost(vha, fcport, 1, 0);
392 break;
393 }
394 qla2x00_post_async_login_work(vha, fcport, NULL);
395 break;
396 }
397 return;
398 }
399
400 void
401 qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
402 uint16_t *data)
403 {
404 qla2x00_mark_device_lost(vha, fcport, 1, 0);
405 return;
406 }
407
408 void
409 qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
410 uint16_t *data)
411 {
412 if (data[0] == MBS_COMMAND_COMPLETE) {
413 qla2x00_update_fcport(vha, fcport);
414
415 return;
416 }
417
418 /* Retry login. */
419 fcport->flags &= ~FCF_ASYNC_SENT;
420 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
421 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
422 else
423 qla2x00_mark_device_lost(vha, fcport, 1, 0);
424
425 return;
426 }
427
428 /****************************************************************************/
429 /* QLogic ISP2x00 Hardware Support Functions. */
430 /****************************************************************************/
431
432 static int
433 qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
434 {
435 int rval = QLA_SUCCESS;
436 struct qla_hw_data *ha = vha->hw;
437 uint32_t idc_major_ver, idc_minor_ver;
438 uint16_t config[4];
439
440 qla83xx_idc_lock(vha, 0);
441
442 /* SV: TODO: Assign initialization timeout from
443 * flash-info / other param
444 */
445 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
446 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
447
448 /* Set our fcoe function presence */
449 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
450 ql_dbg(ql_dbg_p3p, vha, 0xb077,
451 "Error while setting DRV-Presence.\n");
452 rval = QLA_FUNCTION_FAILED;
453 goto exit;
454 }
455
456 /* Decide the reset ownership */
457 qla83xx_reset_ownership(vha);
458
459 /*
460 * On first protocol driver load:
461 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
462 * register.
463 * Others: Check compatibility with current IDC Major version.
464 */
465 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
466 if (ha->flags.nic_core_reset_owner) {
467 /* Set IDC Major version */
468 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
469 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
470
471 /* Clearing IDC-Lock-Recovery register */
472 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
473 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
474 /*
475 * Clear further IDC participation if we are not compatible with
476 * the current IDC Major Version.
477 */
478 ql_log(ql_log_warn, vha, 0xb07d,
479 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
480 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
481 __qla83xx_clear_drv_presence(vha);
482 rval = QLA_FUNCTION_FAILED;
483 goto exit;
484 }
485 /* Each function sets its supported Minor version. */
486 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
487 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
488 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
489
490 if (ha->flags.nic_core_reset_owner) {
491 memset(config, 0, sizeof(config));
492 if (!qla81xx_get_port_config(vha, config))
493 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
494 QLA8XXX_DEV_READY);
495 }
496
497 rval = qla83xx_idc_state_handler(vha);
498
499 exit:
500 qla83xx_idc_unlock(vha, 0);
501
502 return rval;
503 }
504
505 /*
506 * qla2x00_initialize_adapter
507 * Initialize board.
508 *
509 * Input:
510 * ha = adapter block pointer.
511 *
512 * Returns:
513 * 0 = success
514 */
515 int
516 qla2x00_initialize_adapter(scsi_qla_host_t *vha)
517 {
518 int rval;
519 struct qla_hw_data *ha = vha->hw;
520 struct req_que *req = ha->req_q_map[0];
521
522 /* Clear adapter flags. */
523 vha->flags.online = 0;
524 ha->flags.chip_reset_done = 0;
525 vha->flags.reset_active = 0;
526 ha->flags.pci_channel_io_perm_failure = 0;
527 ha->flags.eeh_busy = 0;
528 ha->flags.thermal_supported = 1;
529 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
530 atomic_set(&vha->loop_state, LOOP_DOWN);
531 vha->device_flags = DFLG_NO_CABLE;
532 vha->dpc_flags = 0;
533 vha->flags.management_server_logged_in = 0;
534 vha->marker_needed = 0;
535 ha->isp_abort_cnt = 0;
536 ha->beacon_blink_led = 0;
537
538 set_bit(0, ha->req_qid_map);
539 set_bit(0, ha->rsp_qid_map);
540
541 ql_dbg(ql_dbg_init, vha, 0x0040,
542 "Configuring PCI space...\n");
543 rval = ha->isp_ops->pci_config(vha);
544 if (rval) {
545 ql_log(ql_log_warn, vha, 0x0044,
546 "Unable to configure PCI space.\n");
547 return (rval);
548 }
549
550 ha->isp_ops->reset_chip(vha);
551
552 rval = qla2xxx_get_flash_info(vha);
553 if (rval) {
554 ql_log(ql_log_fatal, vha, 0x004f,
555 "Unable to validate FLASH data.\n");
556 return (rval);
557 }
558
559 ha->isp_ops->get_flash_version(vha, req->ring);
560 ql_dbg(ql_dbg_init, vha, 0x0061,
561 "Configure NVRAM parameters...\n");
562
563 ha->isp_ops->nvram_config(vha);
564
565 if (ha->flags.disable_serdes) {
566 /* Mask HBA via NVRAM settings? */
567 ql_log(ql_log_info, vha, 0x0077,
568 "Masking HBA WWPN "
569 "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
570 vha->port_name[0], vha->port_name[1],
571 vha->port_name[2], vha->port_name[3],
572 vha->port_name[4], vha->port_name[5],
573 vha->port_name[6], vha->port_name[7]);
574 return QLA_FUNCTION_FAILED;
575 }
576
577 ql_dbg(ql_dbg_init, vha, 0x0078,
578 "Verifying loaded RISC code...\n");
579
580 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
581 rval = ha->isp_ops->chip_diag(vha);
582 if (rval)
583 return (rval);
584 rval = qla2x00_setup_chip(vha);
585 if (rval)
586 return (rval);
587 }
588
589 if (IS_QLA84XX(ha)) {
590 ha->cs84xx = qla84xx_get_chip(vha);
591 if (!ha->cs84xx) {
592 ql_log(ql_log_warn, vha, 0x00d0,
593 "Unable to configure ISP84XX.\n");
594 return QLA_FUNCTION_FAILED;
595 }
596 }
597
598 if (qla_ini_mode_enabled(vha))
599 rval = qla2x00_init_rings(vha);
600
601 ha->flags.chip_reset_done = 1;
602
603 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
604 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
605 rval = qla84xx_init_chip(vha);
606 if (rval != QLA_SUCCESS) {
607 ql_log(ql_log_warn, vha, 0x00d4,
608 "Unable to initialize ISP84XX.\n");
609 qla84xx_put_chip(vha);
610 }
611 }
612
613 /* Load the NIC Core f/w if we are the first protocol driver. */
614 if (IS_QLA8031(ha)) {
615 rval = qla83xx_nic_core_fw_load(vha);
616 if (rval)
617 ql_log(ql_log_warn, vha, 0x0124,
618 "Error in initializing NIC Core f/w.\n");
619 }
620
621 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
622 qla24xx_read_fcp_prio_cfg(vha);
623
624 return (rval);
625 }
626
627 /**
628 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
629 * @ha: HA context
630 *
631 * Returns 0 on success.
632 */
633 int
634 qla2100_pci_config(scsi_qla_host_t *vha)
635 {
636 uint16_t w;
637 unsigned long flags;
638 struct qla_hw_data *ha = vha->hw;
639 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
640
641 pci_set_master(ha->pdev);
642 pci_try_set_mwi(ha->pdev);
643
644 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
645 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
646 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
647
648 pci_disable_rom(ha->pdev);
649
650 /* Get PCI bus information. */
651 spin_lock_irqsave(&ha->hardware_lock, flags);
652 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
653 spin_unlock_irqrestore(&ha->hardware_lock, flags);
654
655 return QLA_SUCCESS;
656 }
657
658 /**
659 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
660 * @ha: HA context
661 *
662 * Returns 0 on success.
663 */
664 int
665 qla2300_pci_config(scsi_qla_host_t *vha)
666 {
667 uint16_t w;
668 unsigned long flags = 0;
669 uint32_t cnt;
670 struct qla_hw_data *ha = vha->hw;
671 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
672
673 pci_set_master(ha->pdev);
674 pci_try_set_mwi(ha->pdev);
675
676 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
677 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
678
679 if (IS_QLA2322(ha) || IS_QLA6322(ha))
680 w &= ~PCI_COMMAND_INTX_DISABLE;
681 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
682
683 /*
684 * If this is a 2300 card and not 2312, reset the
685 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
686 * the 2310 also reports itself as a 2300 so we need to get the
687 * fb revision level -- a 6 indicates it really is a 2300 and
688 * not a 2310.
689 */
690 if (IS_QLA2300(ha)) {
691 spin_lock_irqsave(&ha->hardware_lock, flags);
692
693 /* Pause RISC. */
694 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
695 for (cnt = 0; cnt < 30000; cnt++) {
696 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
697 break;
698
699 udelay(10);
700 }
701
702 /* Select FPM registers. */
703 WRT_REG_WORD(&reg->ctrl_status, 0x20);
704 RD_REG_WORD(&reg->ctrl_status);
705
706 /* Get the fb rev level */
707 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
708
709 if (ha->fb_rev == FPM_2300)
710 pci_clear_mwi(ha->pdev);
711
712 /* Deselect FPM registers. */
713 WRT_REG_WORD(&reg->ctrl_status, 0x0);
714 RD_REG_WORD(&reg->ctrl_status);
715
716 /* Release RISC module. */
717 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
718 for (cnt = 0; cnt < 30000; cnt++) {
719 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
720 break;
721
722 udelay(10);
723 }
724
725 spin_unlock_irqrestore(&ha->hardware_lock, flags);
726 }
727
728 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
729
730 pci_disable_rom(ha->pdev);
731
732 /* Get PCI bus information. */
733 spin_lock_irqsave(&ha->hardware_lock, flags);
734 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
735 spin_unlock_irqrestore(&ha->hardware_lock, flags);
736
737 return QLA_SUCCESS;
738 }
739
740 /**
741 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
742 * @ha: HA context
743 *
744 * Returns 0 on success.
745 */
746 int
747 qla24xx_pci_config(scsi_qla_host_t *vha)
748 {
749 uint16_t w;
750 unsigned long flags = 0;
751 struct qla_hw_data *ha = vha->hw;
752 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
753
754 pci_set_master(ha->pdev);
755 pci_try_set_mwi(ha->pdev);
756
757 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
758 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
759 w &= ~PCI_COMMAND_INTX_DISABLE;
760 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
761
762 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
763
764 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
765 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
766 pcix_set_mmrbc(ha->pdev, 2048);
767
768 /* PCIe -- adjust Maximum Read Request Size (2048). */
769 if (pci_is_pcie(ha->pdev))
770 pcie_set_readrq(ha->pdev, 4096);
771
772 pci_disable_rom(ha->pdev);
773
774 ha->chip_revision = ha->pdev->revision;
775
776 /* Get PCI bus information. */
777 spin_lock_irqsave(&ha->hardware_lock, flags);
778 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
779 spin_unlock_irqrestore(&ha->hardware_lock, flags);
780
781 return QLA_SUCCESS;
782 }
783
784 /**
785 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
786 * @ha: HA context
787 *
788 * Returns 0 on success.
789 */
790 int
791 qla25xx_pci_config(scsi_qla_host_t *vha)
792 {
793 uint16_t w;
794 struct qla_hw_data *ha = vha->hw;
795
796 pci_set_master(ha->pdev);
797 pci_try_set_mwi(ha->pdev);
798
799 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
800 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
801 w &= ~PCI_COMMAND_INTX_DISABLE;
802 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
803
804 /* PCIe -- adjust Maximum Read Request Size (2048). */
805 if (pci_is_pcie(ha->pdev))
806 pcie_set_readrq(ha->pdev, 4096);
807
808 pci_disable_rom(ha->pdev);
809
810 ha->chip_revision = ha->pdev->revision;
811
812 return QLA_SUCCESS;
813 }
814
815 /**
816 * qla2x00_isp_firmware() - Choose firmware image.
817 * @ha: HA context
818 *
819 * Returns 0 on success.
820 */
821 static int
822 qla2x00_isp_firmware(scsi_qla_host_t *vha)
823 {
824 int rval;
825 uint16_t loop_id, topo, sw_cap;
826 uint8_t domain, area, al_pa;
827 struct qla_hw_data *ha = vha->hw;
828
829 /* Assume loading risc code */
830 rval = QLA_FUNCTION_FAILED;
831
832 if (ha->flags.disable_risc_code_load) {
833 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
834
835 /* Verify checksum of loaded RISC code. */
836 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
837 if (rval == QLA_SUCCESS) {
838 /* And, verify we are not in ROM code. */
839 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
840 &area, &domain, &topo, &sw_cap);
841 }
842 }
843
844 if (rval)
845 ql_dbg(ql_dbg_init, vha, 0x007a,
846 "**** Load RISC code ****.\n");
847
848 return (rval);
849 }
850
851 /**
852 * qla2x00_reset_chip() - Reset ISP chip.
853 * @ha: HA context
854 *
855 * Returns 0 on success.
856 */
857 void
858 qla2x00_reset_chip(scsi_qla_host_t *vha)
859 {
860 unsigned long flags = 0;
861 struct qla_hw_data *ha = vha->hw;
862 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
863 uint32_t cnt;
864 uint16_t cmd;
865
866 if (unlikely(pci_channel_offline(ha->pdev)))
867 return;
868
869 ha->isp_ops->disable_intrs(ha);
870
871 spin_lock_irqsave(&ha->hardware_lock, flags);
872
873 /* Turn off master enable */
874 cmd = 0;
875 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
876 cmd &= ~PCI_COMMAND_MASTER;
877 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
878
879 if (!IS_QLA2100(ha)) {
880 /* Pause RISC. */
881 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
882 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
883 for (cnt = 0; cnt < 30000; cnt++) {
884 if ((RD_REG_WORD(&reg->hccr) &
885 HCCR_RISC_PAUSE) != 0)
886 break;
887 udelay(100);
888 }
889 } else {
890 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
891 udelay(10);
892 }
893
894 /* Select FPM registers. */
895 WRT_REG_WORD(&reg->ctrl_status, 0x20);
896 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
897
898 /* FPM Soft Reset. */
899 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
900 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
901
902 /* Toggle Fpm Reset. */
903 if (!IS_QLA2200(ha)) {
904 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
905 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
906 }
907
908 /* Select frame buffer registers. */
909 WRT_REG_WORD(&reg->ctrl_status, 0x10);
910 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
911
912 /* Reset frame buffer FIFOs. */
913 if (IS_QLA2200(ha)) {
914 WRT_FB_CMD_REG(ha, reg, 0xa000);
915 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
916 } else {
917 WRT_FB_CMD_REG(ha, reg, 0x00fc);
918
919 /* Read back fb_cmd until zero or 3 seconds max */
920 for (cnt = 0; cnt < 3000; cnt++) {
921 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
922 break;
923 udelay(100);
924 }
925 }
926
927 /* Select RISC module registers. */
928 WRT_REG_WORD(&reg->ctrl_status, 0);
929 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
930
931 /* Reset RISC processor. */
932 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
933 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
934
935 /* Release RISC processor. */
936 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
937 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
938 }
939
940 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
941 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
942
943 /* Reset ISP chip. */
944 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
945
946 /* Wait for RISC to recover from reset. */
947 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
948 /*
949 * It is necessary to for a delay here since the card doesn't
950 * respond to PCI reads during a reset. On some architectures
951 * this will result in an MCA.
952 */
953 udelay(20);
954 for (cnt = 30000; cnt; cnt--) {
955 if ((RD_REG_WORD(&reg->ctrl_status) &
956 CSR_ISP_SOFT_RESET) == 0)
957 break;
958 udelay(100);
959 }
960 } else
961 udelay(10);
962
963 /* Reset RISC processor. */
964 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
965
966 WRT_REG_WORD(&reg->semaphore, 0);
967
968 /* Release RISC processor. */
969 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
970 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
971
972 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
973 for (cnt = 0; cnt < 30000; cnt++) {
974 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
975 break;
976
977 udelay(100);
978 }
979 } else
980 udelay(100);
981
982 /* Turn on master enable */
983 cmd |= PCI_COMMAND_MASTER;
984 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
985
986 /* Disable RISC pause on FPM parity error. */
987 if (!IS_QLA2100(ha)) {
988 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
989 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
990 }
991
992 spin_unlock_irqrestore(&ha->hardware_lock, flags);
993 }
994
995 /**
996 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
997 *
998 * Returns 0 on success.
999 */
1000 static int
1001 qla81xx_reset_mpi(scsi_qla_host_t *vha)
1002 {
1003 uint16_t mb[4] = {0x1010, 0, 1, 0};
1004
1005 if (!IS_QLA81XX(vha->hw))
1006 return QLA_SUCCESS;
1007
1008 return qla81xx_write_mpi_register(vha, mb);
1009 }
1010
1011 /**
1012 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
1013 * @ha: HA context
1014 *
1015 * Returns 0 on success.
1016 */
1017 static inline void
1018 qla24xx_reset_risc(scsi_qla_host_t *vha)
1019 {
1020 unsigned long flags = 0;
1021 struct qla_hw_data *ha = vha->hw;
1022 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1023 uint32_t cnt, d2;
1024 uint16_t wd;
1025 static int abts_cnt; /* ISP abort retry counts */
1026
1027 spin_lock_irqsave(&ha->hardware_lock, flags);
1028
1029 /* Reset RISC. */
1030 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1031 for (cnt = 0; cnt < 30000; cnt++) {
1032 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1033 break;
1034
1035 udelay(10);
1036 }
1037
1038 WRT_REG_DWORD(&reg->ctrl_status,
1039 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1040 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1041
1042 udelay(100);
1043 /* Wait for firmware to complete NVRAM accesses. */
1044 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1045 for (cnt = 10000 ; cnt && d2; cnt--) {
1046 udelay(5);
1047 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1048 barrier();
1049 }
1050
1051 /* Wait for soft-reset to complete. */
1052 d2 = RD_REG_DWORD(&reg->ctrl_status);
1053 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1054 udelay(5);
1055 d2 = RD_REG_DWORD(&reg->ctrl_status);
1056 barrier();
1057 }
1058
1059 /* If required, do an MPI FW reset now */
1060 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1061 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1062 if (++abts_cnt < 5) {
1063 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1064 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1065 } else {
1066 /*
1067 * We exhausted the ISP abort retries. We have to
1068 * set the board offline.
1069 */
1070 abts_cnt = 0;
1071 vha->flags.online = 0;
1072 }
1073 }
1074 }
1075
1076 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1077 RD_REG_DWORD(&reg->hccr);
1078
1079 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1080 RD_REG_DWORD(&reg->hccr);
1081
1082 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1083 RD_REG_DWORD(&reg->hccr);
1084
1085 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1086 for (cnt = 6000000 ; cnt && d2; cnt--) {
1087 udelay(5);
1088 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1089 barrier();
1090 }
1091
1092 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1093
1094 if (IS_NOPOLLING_TYPE(ha))
1095 ha->isp_ops->enable_intrs(ha);
1096 }
1097
1098 static void
1099 qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1100 {
1101 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1102
1103 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1104 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1105
1106 }
1107
1108 static void
1109 qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1110 {
1111 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1112
1113 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1114 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1115 }
1116
1117 static void
1118 qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1119 {
1120 struct qla_hw_data *ha = vha->hw;
1121 uint32_t wd32 = 0;
1122 uint delta_msec = 100;
1123 uint elapsed_msec = 0;
1124 uint timeout_msec;
1125 ulong n;
1126
1127 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha))
1128 return;
1129
1130 attempt:
1131 timeout_msec = TIMEOUT_SEMAPHORE;
1132 n = timeout_msec / delta_msec;
1133 while (n--) {
1134 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1135 qla25xx_read_risc_sema_reg(vha, &wd32);
1136 if (wd32 & RISC_SEMAPHORE)
1137 break;
1138 msleep(delta_msec);
1139 elapsed_msec += delta_msec;
1140 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1141 goto force;
1142 }
1143
1144 if (!(wd32 & RISC_SEMAPHORE))
1145 goto force;
1146
1147 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1148 goto acquired;
1149
1150 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1151 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1152 n = timeout_msec / delta_msec;
1153 while (n--) {
1154 qla25xx_read_risc_sema_reg(vha, &wd32);
1155 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1156 break;
1157 msleep(delta_msec);
1158 elapsed_msec += delta_msec;
1159 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1160 goto force;
1161 }
1162
1163 if (wd32 & RISC_SEMAPHORE_FORCE)
1164 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1165
1166 goto attempt;
1167
1168 force:
1169 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1170
1171 acquired:
1172 return;
1173 }
1174
1175 /**
1176 * qla24xx_reset_chip() - Reset ISP24xx chip.
1177 * @ha: HA context
1178 *
1179 * Returns 0 on success.
1180 */
1181 void
1182 qla24xx_reset_chip(scsi_qla_host_t *vha)
1183 {
1184 struct qla_hw_data *ha = vha->hw;
1185
1186 if (pci_channel_offline(ha->pdev) &&
1187 ha->flags.pci_channel_io_perm_failure) {
1188 return;
1189 }
1190
1191 ha->isp_ops->disable_intrs(ha);
1192
1193 qla25xx_manipulate_risc_semaphore(vha);
1194
1195 /* Perform RISC reset. */
1196 qla24xx_reset_risc(vha);
1197 }
1198
1199 /**
1200 * qla2x00_chip_diag() - Test chip for proper operation.
1201 * @ha: HA context
1202 *
1203 * Returns 0 on success.
1204 */
1205 int
1206 qla2x00_chip_diag(scsi_qla_host_t *vha)
1207 {
1208 int rval;
1209 struct qla_hw_data *ha = vha->hw;
1210 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1211 unsigned long flags = 0;
1212 uint16_t data;
1213 uint32_t cnt;
1214 uint16_t mb[5];
1215 struct req_que *req = ha->req_q_map[0];
1216
1217 /* Assume a failed state */
1218 rval = QLA_FUNCTION_FAILED;
1219
1220 ql_dbg(ql_dbg_init, vha, 0x007b,
1221 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1222
1223 spin_lock_irqsave(&ha->hardware_lock, flags);
1224
1225 /* Reset ISP chip. */
1226 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1227
1228 /*
1229 * We need to have a delay here since the card will not respond while
1230 * in reset causing an MCA on some architectures.
1231 */
1232 udelay(20);
1233 data = qla2x00_debounce_register(&reg->ctrl_status);
1234 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1235 udelay(5);
1236 data = RD_REG_WORD(&reg->ctrl_status);
1237 barrier();
1238 }
1239
1240 if (!cnt)
1241 goto chip_diag_failed;
1242
1243 ql_dbg(ql_dbg_init, vha, 0x007c,
1244 "Reset register cleared by chip reset.\n");
1245
1246 /* Reset RISC processor. */
1247 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1248 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1249
1250 /* Workaround for QLA2312 PCI parity error */
1251 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1252 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1253 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1254 udelay(5);
1255 data = RD_MAILBOX_REG(ha, reg, 0);
1256 barrier();
1257 }
1258 } else
1259 udelay(10);
1260
1261 if (!cnt)
1262 goto chip_diag_failed;
1263
1264 /* Check product ID of chip */
1265 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1266
1267 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1268 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1269 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1270 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1271 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1272 mb[3] != PROD_ID_3) {
1273 ql_log(ql_log_warn, vha, 0x0062,
1274 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1275 mb[1], mb[2], mb[3]);
1276
1277 goto chip_diag_failed;
1278 }
1279 ha->product_id[0] = mb[1];
1280 ha->product_id[1] = mb[2];
1281 ha->product_id[2] = mb[3];
1282 ha->product_id[3] = mb[4];
1283
1284 /* Adjust fw RISC transfer size */
1285 if (req->length > 1024)
1286 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1287 else
1288 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
1289 req->length;
1290
1291 if (IS_QLA2200(ha) &&
1292 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1293 /* Limit firmware transfer size with a 2200A */
1294 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1295
1296 ha->device_type |= DT_ISP2200A;
1297 ha->fw_transfer_size = 128;
1298 }
1299
1300 /* Wrap Incoming Mailboxes Test. */
1301 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1302
1303 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
1304 rval = qla2x00_mbx_reg_test(vha);
1305 if (rval)
1306 ql_log(ql_log_warn, vha, 0x0080,
1307 "Failed mailbox send register test.\n");
1308 else
1309 /* Flag a successful rval */
1310 rval = QLA_SUCCESS;
1311 spin_lock_irqsave(&ha->hardware_lock, flags);
1312
1313 chip_diag_failed:
1314 if (rval)
1315 ql_log(ql_log_info, vha, 0x0081,
1316 "Chip diagnostics **** FAILED ****.\n");
1317
1318 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1319
1320 return (rval);
1321 }
1322
1323 /**
1324 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1325 * @ha: HA context
1326 *
1327 * Returns 0 on success.
1328 */
1329 int
1330 qla24xx_chip_diag(scsi_qla_host_t *vha)
1331 {
1332 int rval;
1333 struct qla_hw_data *ha = vha->hw;
1334 struct req_que *req = ha->req_q_map[0];
1335
1336 if (IS_QLA82XX(ha))
1337 return QLA_SUCCESS;
1338
1339 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
1340
1341 rval = qla2x00_mbx_reg_test(vha);
1342 if (rval) {
1343 ql_log(ql_log_warn, vha, 0x0082,
1344 "Failed mailbox send register test.\n");
1345 } else {
1346 /* Flag a successful rval */
1347 rval = QLA_SUCCESS;
1348 }
1349
1350 return rval;
1351 }
1352
1353 void
1354 qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
1355 {
1356 int rval;
1357 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
1358 eft_size, fce_size, mq_size;
1359 dma_addr_t tc_dma;
1360 void *tc;
1361 struct qla_hw_data *ha = vha->hw;
1362 struct req_que *req = ha->req_q_map[0];
1363 struct rsp_que *rsp = ha->rsp_q_map[0];
1364
1365 if (ha->fw_dump) {
1366 ql_dbg(ql_dbg_init, vha, 0x00bd,
1367 "Firmware dump already allocated.\n");
1368 return;
1369 }
1370
1371 ha->fw_dumped = 0;
1372 fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
1373 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
1374 fixed_size = sizeof(struct qla2100_fw_dump);
1375 } else if (IS_QLA23XX(ha)) {
1376 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1377 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1378 sizeof(uint16_t);
1379 } else if (IS_FWI2_CAPABLE(ha)) {
1380 if (IS_QLA83XX(ha))
1381 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1382 else if (IS_QLA81XX(ha))
1383 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1384 else if (IS_QLA25XX(ha))
1385 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1386 else
1387 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
1388 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1389 sizeof(uint32_t);
1390 if (ha->mqenable) {
1391 if (!IS_QLA83XX(ha))
1392 mq_size = sizeof(struct qla2xxx_mq_chain);
1393 /*
1394 * Allocate maximum buffer size for all queues.
1395 * Resizing must be done at end-of-dump processing.
1396 */
1397 mq_size += ha->max_req_queues *
1398 (req->length * sizeof(request_t));
1399 mq_size += ha->max_rsp_queues *
1400 (rsp->length * sizeof(response_t));
1401 }
1402 if (ha->tgt.atio_q_length)
1403 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
1404 /* Allocate memory for Fibre Channel Event Buffer. */
1405 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
1406 goto try_eft;
1407
1408 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1409 GFP_KERNEL);
1410 if (!tc) {
1411 ql_log(ql_log_warn, vha, 0x00be,
1412 "Unable to allocate (%d KB) for FCE.\n",
1413 FCE_SIZE / 1024);
1414 goto try_eft;
1415 }
1416
1417 memset(tc, 0, FCE_SIZE);
1418 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
1419 ha->fce_mb, &ha->fce_bufs);
1420 if (rval) {
1421 ql_log(ql_log_warn, vha, 0x00bf,
1422 "Unable to initialize FCE (%d).\n", rval);
1423 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1424 tc_dma);
1425 ha->flags.fce_enabled = 0;
1426 goto try_eft;
1427 }
1428 ql_dbg(ql_dbg_init, vha, 0x00c0,
1429 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
1430
1431 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
1432 ha->flags.fce_enabled = 1;
1433 ha->fce_dma = tc_dma;
1434 ha->fce = tc;
1435 try_eft:
1436 /* Allocate memory for Extended Trace Buffer. */
1437 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1438 GFP_KERNEL);
1439 if (!tc) {
1440 ql_log(ql_log_warn, vha, 0x00c1,
1441 "Unable to allocate (%d KB) for EFT.\n",
1442 EFT_SIZE / 1024);
1443 goto cont_alloc;
1444 }
1445
1446 memset(tc, 0, EFT_SIZE);
1447 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
1448 if (rval) {
1449 ql_log(ql_log_warn, vha, 0x00c2,
1450 "Unable to initialize EFT (%d).\n", rval);
1451 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1452 tc_dma);
1453 goto cont_alloc;
1454 }
1455 ql_dbg(ql_dbg_init, vha, 0x00c3,
1456 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
1457
1458 eft_size = EFT_SIZE;
1459 ha->eft_dma = tc_dma;
1460 ha->eft = tc;
1461 }
1462 cont_alloc:
1463 req_q_size = req->length * sizeof(request_t);
1464 rsp_q_size = rsp->length * sizeof(response_t);
1465
1466 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
1467 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
1468 ha->chain_offset = dump_size;
1469 dump_size += mq_size + fce_size;
1470
1471 ha->fw_dump = vmalloc(dump_size);
1472 if (!ha->fw_dump) {
1473 ql_log(ql_log_warn, vha, 0x00c4,
1474 "Unable to allocate (%d KB) for firmware dump.\n",
1475 dump_size / 1024);
1476
1477 if (ha->fce) {
1478 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1479 ha->fce_dma);
1480 ha->fce = NULL;
1481 ha->fce_dma = 0;
1482 }
1483
1484 if (ha->eft) {
1485 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1486 ha->eft_dma);
1487 ha->eft = NULL;
1488 ha->eft_dma = 0;
1489 }
1490 return;
1491 }
1492 ql_dbg(ql_dbg_init, vha, 0x00c5,
1493 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
1494
1495 ha->fw_dump_len = dump_size;
1496 ha->fw_dump->signature[0] = 'Q';
1497 ha->fw_dump->signature[1] = 'L';
1498 ha->fw_dump->signature[2] = 'G';
1499 ha->fw_dump->signature[3] = 'C';
1500 ha->fw_dump->version = __constant_htonl(1);
1501
1502 ha->fw_dump->fixed_size = htonl(fixed_size);
1503 ha->fw_dump->mem_size = htonl(mem_size);
1504 ha->fw_dump->req_q_size = htonl(req_q_size);
1505 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1506
1507 ha->fw_dump->eft_size = htonl(eft_size);
1508 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1509 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1510
1511 ha->fw_dump->header_size =
1512 htonl(offsetof(struct qla2xxx_fw_dump, isp));
1513 }
1514
1515 static int
1516 qla81xx_mpi_sync(scsi_qla_host_t *vha)
1517 {
1518 #define MPS_MASK 0xe0
1519 int rval;
1520 uint16_t dc;
1521 uint32_t dw;
1522
1523 if (!IS_QLA81XX(vha->hw))
1524 return QLA_SUCCESS;
1525
1526 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1527 if (rval != QLA_SUCCESS) {
1528 ql_log(ql_log_warn, vha, 0x0105,
1529 "Unable to acquire semaphore.\n");
1530 goto done;
1531 }
1532
1533 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1534 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1535 if (rval != QLA_SUCCESS) {
1536 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
1537 goto done_release;
1538 }
1539
1540 dc &= MPS_MASK;
1541 if (dc == (dw & MPS_MASK))
1542 goto done_release;
1543
1544 dw &= ~MPS_MASK;
1545 dw |= dc;
1546 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1547 if (rval != QLA_SUCCESS) {
1548 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
1549 }
1550
1551 done_release:
1552 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1553 if (rval != QLA_SUCCESS) {
1554 ql_log(ql_log_warn, vha, 0x006d,
1555 "Unable to release semaphore.\n");
1556 }
1557
1558 done:
1559 return rval;
1560 }
1561
1562 int
1563 qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1564 {
1565 /* Don't try to reallocate the array */
1566 if (req->outstanding_cmds)
1567 return QLA_SUCCESS;
1568
1569 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase &&
1570 (ql2xmultique_tag || ql2xmaxqueues > 1)))
1571 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1572 else {
1573 if (ha->fw_xcb_count <= ha->fw_iocb_count)
1574 req->num_outstanding_cmds = ha->fw_xcb_count;
1575 else
1576 req->num_outstanding_cmds = ha->fw_iocb_count;
1577 }
1578
1579 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1580 req->num_outstanding_cmds, GFP_KERNEL);
1581
1582 if (!req->outstanding_cmds) {
1583 /*
1584 * Try to allocate a minimal size just so we can get through
1585 * initialization.
1586 */
1587 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1588 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1589 req->num_outstanding_cmds, GFP_KERNEL);
1590
1591 if (!req->outstanding_cmds) {
1592 ql_log(ql_log_fatal, NULL, 0x0126,
1593 "Failed to allocate memory for "
1594 "outstanding_cmds for req_que %p.\n", req);
1595 req->num_outstanding_cmds = 0;
1596 return QLA_FUNCTION_FAILED;
1597 }
1598 }
1599
1600 return QLA_SUCCESS;
1601 }
1602
1603 /**
1604 * qla2x00_setup_chip() - Load and start RISC firmware.
1605 * @ha: HA context
1606 *
1607 * Returns 0 on success.
1608 */
1609 static int
1610 qla2x00_setup_chip(scsi_qla_host_t *vha)
1611 {
1612 int rval;
1613 uint32_t srisc_address = 0;
1614 struct qla_hw_data *ha = vha->hw;
1615 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1616 unsigned long flags;
1617 uint16_t fw_major_version;
1618
1619 if (IS_QLA82XX(ha)) {
1620 rval = ha->isp_ops->load_risc(vha, &srisc_address);
1621 if (rval == QLA_SUCCESS) {
1622 qla2x00_stop_firmware(vha);
1623 goto enable_82xx_npiv;
1624 } else
1625 goto failed;
1626 }
1627
1628 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1629 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1630 spin_lock_irqsave(&ha->hardware_lock, flags);
1631 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1632 RD_REG_WORD(&reg->hccr);
1633 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1634 }
1635
1636 qla81xx_mpi_sync(vha);
1637
1638 /* Load firmware sequences */
1639 rval = ha->isp_ops->load_risc(vha, &srisc_address);
1640 if (rval == QLA_SUCCESS) {
1641 ql_dbg(ql_dbg_init, vha, 0x00c9,
1642 "Verifying Checksum of loaded RISC code.\n");
1643
1644 rval = qla2x00_verify_checksum(vha, srisc_address);
1645 if (rval == QLA_SUCCESS) {
1646 /* Start firmware execution. */
1647 ql_dbg(ql_dbg_init, vha, 0x00ca,
1648 "Starting firmware.\n");
1649
1650 rval = qla2x00_execute_fw(vha, srisc_address);
1651 /* Retrieve firmware information. */
1652 if (rval == QLA_SUCCESS) {
1653 enable_82xx_npiv:
1654 fw_major_version = ha->fw_major_version;
1655 if (IS_QLA82XX(ha))
1656 qla82xx_check_md_needed(vha);
1657 else
1658 rval = qla2x00_get_fw_version(vha);
1659 if (rval != QLA_SUCCESS)
1660 goto failed;
1661 ha->flags.npiv_supported = 0;
1662 if (IS_QLA2XXX_MIDTYPE(ha) &&
1663 (ha->fw_attributes & BIT_2)) {
1664 ha->flags.npiv_supported = 1;
1665 if ((!ha->max_npiv_vports) ||
1666 ((ha->max_npiv_vports + 1) %
1667 MIN_MULTI_ID_FABRIC))
1668 ha->max_npiv_vports =
1669 MIN_MULTI_ID_FABRIC - 1;
1670 }
1671 qla2x00_get_resource_cnts(vha, NULL,
1672 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count,
1673 &ha->max_npiv_vports, NULL);
1674
1675 /*
1676 * Allocate the array of outstanding commands
1677 * now that we know the firmware resources.
1678 */
1679 rval = qla2x00_alloc_outstanding_cmds(ha,
1680 vha->req);
1681 if (rval != QLA_SUCCESS)
1682 goto failed;
1683
1684 if (!fw_major_version && ql2xallocfwdump
1685 && !IS_QLA82XX(ha))
1686 qla2x00_alloc_fw_dump(vha);
1687 }
1688 } else {
1689 ql_log(ql_log_fatal, vha, 0x00cd,
1690 "ISP Firmware failed checksum.\n");
1691 goto failed;
1692 }
1693 } else
1694 goto failed;
1695
1696 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1697 /* Enable proper parity. */
1698 spin_lock_irqsave(&ha->hardware_lock, flags);
1699 if (IS_QLA2300(ha))
1700 /* SRAM parity */
1701 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1702 else
1703 /* SRAM, Instruction RAM and GP RAM parity */
1704 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1705 RD_REG_WORD(&reg->hccr);
1706 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1707 }
1708
1709 if (IS_QLA83XX(ha))
1710 goto skip_fac_check;
1711
1712 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1713 uint32_t size;
1714
1715 rval = qla81xx_fac_get_sector_size(vha, &size);
1716 if (rval == QLA_SUCCESS) {
1717 ha->flags.fac_supported = 1;
1718 ha->fdt_block_size = size << 2;
1719 } else {
1720 ql_log(ql_log_warn, vha, 0x00ce,
1721 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1722 ha->fw_major_version, ha->fw_minor_version,
1723 ha->fw_subminor_version);
1724 skip_fac_check:
1725 if (IS_QLA83XX(ha)) {
1726 ha->flags.fac_supported = 0;
1727 rval = QLA_SUCCESS;
1728 }
1729 }
1730 }
1731 failed:
1732 if (rval) {
1733 ql_log(ql_log_fatal, vha, 0x00cf,
1734 "Setup chip ****FAILED****.\n");
1735 }
1736
1737 return (rval);
1738 }
1739
1740 /**
1741 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1742 * @ha: HA context
1743 *
1744 * Beginning of request ring has initialization control block already built
1745 * by nvram config routine.
1746 *
1747 * Returns 0 on success.
1748 */
1749 void
1750 qla2x00_init_response_q_entries(struct rsp_que *rsp)
1751 {
1752 uint16_t cnt;
1753 response_t *pkt;
1754
1755 rsp->ring_ptr = rsp->ring;
1756 rsp->ring_index = 0;
1757 rsp->status_srb = NULL;
1758 pkt = rsp->ring_ptr;
1759 for (cnt = 0; cnt < rsp->length; cnt++) {
1760 pkt->signature = RESPONSE_PROCESSED;
1761 pkt++;
1762 }
1763 }
1764
1765 /**
1766 * qla2x00_update_fw_options() - Read and process firmware options.
1767 * @ha: HA context
1768 *
1769 * Returns 0 on success.
1770 */
1771 void
1772 qla2x00_update_fw_options(scsi_qla_host_t *vha)
1773 {
1774 uint16_t swing, emphasis, tx_sens, rx_sens;
1775 struct qla_hw_data *ha = vha->hw;
1776
1777 memset(ha->fw_options, 0, sizeof(ha->fw_options));
1778 qla2x00_get_fw_options(vha, ha->fw_options);
1779
1780 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1781 return;
1782
1783 /* Serial Link options. */
1784 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1785 "Serial link options.\n");
1786 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1787 (uint8_t *)&ha->fw_seriallink_options,
1788 sizeof(ha->fw_seriallink_options));
1789
1790 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1791 if (ha->fw_seriallink_options[3] & BIT_2) {
1792 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1793
1794 /* 1G settings */
1795 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1796 emphasis = (ha->fw_seriallink_options[2] &
1797 (BIT_4 | BIT_3)) >> 3;
1798 tx_sens = ha->fw_seriallink_options[0] &
1799 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1800 rx_sens = (ha->fw_seriallink_options[0] &
1801 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1802 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1803 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1804 if (rx_sens == 0x0)
1805 rx_sens = 0x3;
1806 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1807 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1808 ha->fw_options[10] |= BIT_5 |
1809 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1810 (tx_sens & (BIT_1 | BIT_0));
1811
1812 /* 2G settings */
1813 swing = (ha->fw_seriallink_options[2] &
1814 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1815 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1816 tx_sens = ha->fw_seriallink_options[1] &
1817 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1818 rx_sens = (ha->fw_seriallink_options[1] &
1819 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1820 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1821 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1822 if (rx_sens == 0x0)
1823 rx_sens = 0x3;
1824 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1825 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1826 ha->fw_options[11] |= BIT_5 |
1827 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1828 (tx_sens & (BIT_1 | BIT_0));
1829 }
1830
1831 /* FCP2 options. */
1832 /* Return command IOCBs without waiting for an ABTS to complete. */
1833 ha->fw_options[3] |= BIT_13;
1834
1835 /* LED scheme. */
1836 if (ha->flags.enable_led_scheme)
1837 ha->fw_options[2] |= BIT_12;
1838
1839 /* Detect ISP6312. */
1840 if (IS_QLA6312(ha))
1841 ha->fw_options[2] |= BIT_13;
1842
1843 /* Update firmware options. */
1844 qla2x00_set_fw_options(vha, ha->fw_options);
1845 }
1846
1847 void
1848 qla24xx_update_fw_options(scsi_qla_host_t *vha)
1849 {
1850 int rval;
1851 struct qla_hw_data *ha = vha->hw;
1852
1853 if (IS_QLA82XX(ha))
1854 return;
1855
1856 /* Update Serial Link options. */
1857 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
1858 return;
1859
1860 rval = qla2x00_set_serdes_params(vha,
1861 le16_to_cpu(ha->fw_seriallink_options24[1]),
1862 le16_to_cpu(ha->fw_seriallink_options24[2]),
1863 le16_to_cpu(ha->fw_seriallink_options24[3]));
1864 if (rval != QLA_SUCCESS) {
1865 ql_log(ql_log_warn, vha, 0x0104,
1866 "Unable to update Serial Link options (%x).\n", rval);
1867 }
1868 }
1869
1870 void
1871 qla2x00_config_rings(struct scsi_qla_host *vha)
1872 {
1873 struct qla_hw_data *ha = vha->hw;
1874 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1875 struct req_que *req = ha->req_q_map[0];
1876 struct rsp_que *rsp = ha->rsp_q_map[0];
1877
1878 /* Setup ring parameters in initialization control block. */
1879 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
1880 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
1881 ha->init_cb->request_q_length = cpu_to_le16(req->length);
1882 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
1883 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1884 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1885 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1886 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1887
1888 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
1889 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
1890 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
1891 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
1892 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
1893 }
1894
1895 void
1896 qla24xx_config_rings(struct scsi_qla_host *vha)
1897 {
1898 struct qla_hw_data *ha = vha->hw;
1899 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
1900 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
1901 struct qla_msix_entry *msix;
1902 struct init_cb_24xx *icb;
1903 uint16_t rid = 0;
1904 struct req_que *req = ha->req_q_map[0];
1905 struct rsp_que *rsp = ha->rsp_q_map[0];
1906
1907 /* Setup ring parameters in initialization control block. */
1908 icb = (struct init_cb_24xx *)ha->init_cb;
1909 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1910 icb->response_q_inpointer = __constant_cpu_to_le16(0);
1911 icb->request_q_length = cpu_to_le16(req->length);
1912 icb->response_q_length = cpu_to_le16(rsp->length);
1913 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1914 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1915 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1916 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1917
1918 /* Setup ATIO queue dma pointers for target mode */
1919 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
1920 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
1921 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
1922 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
1923
1924 if (ha->mqenable || IS_QLA83XX(ha)) {
1925 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
1926 icb->rid = __constant_cpu_to_le16(rid);
1927 if (ha->flags.msix_enabled) {
1928 msix = &ha->msix_entries[1];
1929 ql_dbg(ql_dbg_init, vha, 0x00fd,
1930 "Registering vector 0x%x for base que.\n",
1931 msix->entry);
1932 icb->msix = cpu_to_le16(msix->entry);
1933 }
1934 /* Use alternate PCI bus number */
1935 if (MSB(rid))
1936 icb->firmware_options_2 |=
1937 __constant_cpu_to_le32(BIT_19);
1938 /* Use alternate PCI devfn */
1939 if (LSB(rid))
1940 icb->firmware_options_2 |=
1941 __constant_cpu_to_le32(BIT_18);
1942
1943 /* Use Disable MSIX Handshake mode for capable adapters */
1944 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
1945 (ha->flags.msix_enabled)) {
1946 icb->firmware_options_2 &=
1947 __constant_cpu_to_le32(~BIT_22);
1948 ha->flags.disable_msix_handshake = 1;
1949 ql_dbg(ql_dbg_init, vha, 0x00fe,
1950 "MSIX Handshake Disable Mode turned on.\n");
1951 } else {
1952 icb->firmware_options_2 |=
1953 __constant_cpu_to_le32(BIT_22);
1954 }
1955 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
1956
1957 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
1958 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
1959 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
1960 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
1961 } else {
1962 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
1963 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
1964 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
1965 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
1966 }
1967 qlt_24xx_config_rings(vha);
1968
1969 /* PCI posting */
1970 RD_REG_DWORD(&ioreg->hccr);
1971 }
1972
1973 /**
1974 * qla2x00_init_rings() - Initializes firmware.
1975 * @ha: HA context
1976 *
1977 * Beginning of request ring has initialization control block already built
1978 * by nvram config routine.
1979 *
1980 * Returns 0 on success.
1981 */
1982 static int
1983 qla2x00_init_rings(scsi_qla_host_t *vha)
1984 {
1985 int rval;
1986 unsigned long flags = 0;
1987 int cnt, que;
1988 struct qla_hw_data *ha = vha->hw;
1989 struct req_que *req;
1990 struct rsp_que *rsp;
1991 struct mid_init_cb_24xx *mid_init_cb =
1992 (struct mid_init_cb_24xx *) ha->init_cb;
1993
1994 spin_lock_irqsave(&ha->hardware_lock, flags);
1995
1996 /* Clear outstanding commands array. */
1997 for (que = 0; que < ha->max_req_queues; que++) {
1998 req = ha->req_q_map[que];
1999 if (!req)
2000 continue;
2001 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
2002 req->outstanding_cmds[cnt] = NULL;
2003
2004 req->current_outstanding_cmd = 1;
2005
2006 /* Initialize firmware. */
2007 req->ring_ptr = req->ring;
2008 req->ring_index = 0;
2009 req->cnt = req->length;
2010 }
2011
2012 for (que = 0; que < ha->max_rsp_queues; que++) {
2013 rsp = ha->rsp_q_map[que];
2014 if (!rsp)
2015 continue;
2016 /* Initialize response queue entries */
2017 qla2x00_init_response_q_entries(rsp);
2018 }
2019
2020 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2021 ha->tgt.atio_ring_index = 0;
2022 /* Initialize ATIO queue entries */
2023 qlt_init_atio_q_entries(vha);
2024
2025 ha->isp_ops->config_rings(vha);
2026
2027 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2028
2029 /* Update any ISP specific firmware options before initialization. */
2030 ha->isp_ops->update_fw_options(vha);
2031
2032 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2033
2034 if (ha->flags.npiv_supported) {
2035 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
2036 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
2037 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
2038 }
2039
2040 if (IS_FWI2_CAPABLE(ha)) {
2041 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
2042 mid_init_cb->init_cb.execution_throttle =
2043 cpu_to_le16(ha->fw_xcb_count);
2044 }
2045
2046 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
2047 if (rval) {
2048 ql_log(ql_log_fatal, vha, 0x00d2,
2049 "Init Firmware **** FAILED ****.\n");
2050 } else {
2051 ql_dbg(ql_dbg_init, vha, 0x00d3,
2052 "Init Firmware -- success.\n");
2053 }
2054
2055 return (rval);
2056 }
2057
2058 /**
2059 * qla2x00_fw_ready() - Waits for firmware ready.
2060 * @ha: HA context
2061 *
2062 * Returns 0 on success.
2063 */
2064 static int
2065 qla2x00_fw_ready(scsi_qla_host_t *vha)
2066 {
2067 int rval;
2068 unsigned long wtime, mtime, cs84xx_time;
2069 uint16_t min_wait; /* Minimum wait time if loop is down */
2070 uint16_t wait_time; /* Wait time if loop is coming ready */
2071 uint16_t state[5];
2072 struct qla_hw_data *ha = vha->hw;
2073
2074 rval = QLA_SUCCESS;
2075
2076 /* 20 seconds for loop down. */
2077 min_wait = 20;
2078
2079 /*
2080 * Firmware should take at most one RATOV to login, plus 5 seconds for
2081 * our own processing.
2082 */
2083 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2084 wait_time = min_wait;
2085 }
2086
2087 /* Min wait time if loop down */
2088 mtime = jiffies + (min_wait * HZ);
2089
2090 /* wait time before firmware ready */
2091 wtime = jiffies + (wait_time * HZ);
2092
2093 /* Wait for ISP to finish LIP */
2094 if (!vha->flags.init_done)
2095 ql_log(ql_log_info, vha, 0x801e,
2096 "Waiting for LIP to complete.\n");
2097
2098 do {
2099 memset(state, -1, sizeof(state));
2100 rval = qla2x00_get_firmware_state(vha, state);
2101 if (rval == QLA_SUCCESS) {
2102 if (state[0] < FSTATE_LOSS_OF_SYNC) {
2103 vha->device_flags &= ~DFLG_NO_CABLE;
2104 }
2105 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
2106 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2107 "fw_state=%x 84xx=%x.\n", state[0],
2108 state[2]);
2109 if ((state[2] & FSTATE_LOGGED_IN) &&
2110 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
2111 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2112 "Sending verify iocb.\n");
2113
2114 cs84xx_time = jiffies;
2115 rval = qla84xx_init_chip(vha);
2116 if (rval != QLA_SUCCESS) {
2117 ql_log(ql_log_warn,
2118 vha, 0x8007,
2119 "Init chip failed.\n");
2120 break;
2121 }
2122
2123 /* Add time taken to initialize. */
2124 cs84xx_time = jiffies - cs84xx_time;
2125 wtime += cs84xx_time;
2126 mtime += cs84xx_time;
2127 ql_dbg(ql_dbg_taskm, vha, 0x8008,
2128 "Increasing wait time by %ld. "
2129 "New time %ld.\n", cs84xx_time,
2130 wtime);
2131 }
2132 } else if (state[0] == FSTATE_READY) {
2133 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2134 "F/W Ready - OK.\n");
2135
2136 qla2x00_get_retry_cnt(vha, &ha->retry_count,
2137 &ha->login_timeout, &ha->r_a_tov);
2138
2139 rval = QLA_SUCCESS;
2140 break;
2141 }
2142
2143 rval = QLA_FUNCTION_FAILED;
2144
2145 if (atomic_read(&vha->loop_down_timer) &&
2146 state[0] != FSTATE_READY) {
2147 /* Loop down. Timeout on min_wait for states
2148 * other than Wait for Login.
2149 */
2150 if (time_after_eq(jiffies, mtime)) {
2151 ql_log(ql_log_info, vha, 0x8038,
2152 "Cable is unplugged...\n");
2153
2154 vha->device_flags |= DFLG_NO_CABLE;
2155 break;
2156 }
2157 }
2158 } else {
2159 /* Mailbox cmd failed. Timeout on min_wait. */
2160 if (time_after_eq(jiffies, mtime) ||
2161 ha->flags.isp82xx_fw_hung)
2162 break;
2163 }
2164
2165 if (time_after_eq(jiffies, wtime))
2166 break;
2167
2168 /* Delay for a while */
2169 msleep(500);
2170 } while (1);
2171
2172 ql_dbg(ql_dbg_taskm, vha, 0x803a,
2173 "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
2174 state[1], state[2], state[3], state[4], jiffies);
2175
2176 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
2177 ql_log(ql_log_warn, vha, 0x803b,
2178 "Firmware ready **** FAILED ****.\n");
2179 }
2180
2181 return (rval);
2182 }
2183
2184 /*
2185 * qla2x00_configure_hba
2186 * Setup adapter context.
2187 *
2188 * Input:
2189 * ha = adapter state pointer.
2190 *
2191 * Returns:
2192 * 0 = success
2193 *
2194 * Context:
2195 * Kernel context.
2196 */
2197 static int
2198 qla2x00_configure_hba(scsi_qla_host_t *vha)
2199 {
2200 int rval;
2201 uint16_t loop_id;
2202 uint16_t topo;
2203 uint16_t sw_cap;
2204 uint8_t al_pa;
2205 uint8_t area;
2206 uint8_t domain;
2207 char connect_type[22];
2208 struct qla_hw_data *ha = vha->hw;
2209 unsigned long flags;
2210 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
2211
2212 /* Get host addresses. */
2213 rval = qla2x00_get_adapter_id(vha,
2214 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
2215 if (rval != QLA_SUCCESS) {
2216 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
2217 IS_CNA_CAPABLE(ha) ||
2218 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
2219 ql_dbg(ql_dbg_disc, vha, 0x2008,
2220 "Loop is in a transition state.\n");
2221 } else {
2222 ql_log(ql_log_warn, vha, 0x2009,
2223 "Unable to get host loop ID.\n");
2224 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2225 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2226 ql_log(ql_log_warn, vha, 0x1151,
2227 "Doing link init.\n");
2228 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2229 return rval;
2230 }
2231 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2232 }
2233 return (rval);
2234 }
2235
2236 if (topo == 4) {
2237 ql_log(ql_log_info, vha, 0x200a,
2238 "Cannot get topology - retrying.\n");
2239 return (QLA_FUNCTION_FAILED);
2240 }
2241
2242 vha->loop_id = loop_id;
2243
2244 /* initialize */
2245 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2246 ha->operating_mode = LOOP;
2247 ha->switch_cap = 0;
2248
2249 switch (topo) {
2250 case 0:
2251 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
2252 ha->current_topology = ISP_CFG_NL;
2253 strcpy(connect_type, "(Loop)");
2254 break;
2255
2256 case 1:
2257 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2258 ha->switch_cap = sw_cap;
2259 ha->current_topology = ISP_CFG_FL;
2260 strcpy(connect_type, "(FL_Port)");
2261 break;
2262
2263 case 2:
2264 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
2265 ha->operating_mode = P2P;
2266 ha->current_topology = ISP_CFG_N;
2267 strcpy(connect_type, "(N_Port-to-N_Port)");
2268 break;
2269
2270 case 3:
2271 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2272 ha->switch_cap = sw_cap;
2273 ha->operating_mode = P2P;
2274 ha->current_topology = ISP_CFG_F;
2275 strcpy(connect_type, "(F_Port)");
2276 break;
2277
2278 default:
2279 ql_dbg(ql_dbg_disc, vha, 0x200f,
2280 "HBA in unknown topology %x, using NL.\n", topo);
2281 ha->current_topology = ISP_CFG_NL;
2282 strcpy(connect_type, "(Loop)");
2283 break;
2284 }
2285
2286 /* Save Host port and loop ID. */
2287 /* byte order - Big Endian */
2288 vha->d_id.b.domain = domain;
2289 vha->d_id.b.area = area;
2290 vha->d_id.b.al_pa = al_pa;
2291
2292 spin_lock_irqsave(&ha->vport_slock, flags);
2293 qlt_update_vp_map(vha, SET_AL_PA);
2294 spin_unlock_irqrestore(&ha->vport_slock, flags);
2295
2296 if (!vha->flags.init_done)
2297 ql_log(ql_log_info, vha, 0x2010,
2298 "Topology - %s, Host Loop address 0x%x.\n",
2299 connect_type, vha->loop_id);
2300
2301 if (rval) {
2302 ql_log(ql_log_warn, vha, 0x2011,
2303 "%s FAILED\n", __func__);
2304 } else {
2305 ql_dbg(ql_dbg_disc, vha, 0x2012,
2306 "%s success\n", __func__);
2307 }
2308
2309 return(rval);
2310 }
2311
2312 inline void
2313 qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2314 char *def)
2315 {
2316 char *st, *en;
2317 uint16_t index;
2318 struct qla_hw_data *ha = vha->hw;
2319 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
2320 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
2321
2322 if (memcmp(model, BINZERO, len) != 0) {
2323 strncpy(ha->model_number, model, len);
2324 st = en = ha->model_number;
2325 en += len - 1;
2326 while (en > st) {
2327 if (*en != 0x20 && *en != 0x00)
2328 break;
2329 *en-- = '\0';
2330 }
2331
2332 index = (ha->pdev->subsystem_device & 0xff);
2333 if (use_tbl &&
2334 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
2335 index < QLA_MODEL_NAMES)
2336 strncpy(ha->model_desc,
2337 qla2x00_model_name[index * 2 + 1],
2338 sizeof(ha->model_desc) - 1);
2339 } else {
2340 index = (ha->pdev->subsystem_device & 0xff);
2341 if (use_tbl &&
2342 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
2343 index < QLA_MODEL_NAMES) {
2344 strcpy(ha->model_number,
2345 qla2x00_model_name[index * 2]);
2346 strncpy(ha->model_desc,
2347 qla2x00_model_name[index * 2 + 1],
2348 sizeof(ha->model_desc) - 1);
2349 } else {
2350 strcpy(ha->model_number, def);
2351 }
2352 }
2353 if (IS_FWI2_CAPABLE(ha))
2354 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
2355 sizeof(ha->model_desc));
2356 }
2357
2358 /* On sparc systems, obtain port and node WWN from firmware
2359 * properties.
2360 */
2361 static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
2362 {
2363 #ifdef CONFIG_SPARC
2364 struct qla_hw_data *ha = vha->hw;
2365 struct pci_dev *pdev = ha->pdev;
2366 struct device_node *dp = pci_device_to_OF_node(pdev);
2367 const u8 *val;
2368 int len;
2369
2370 val = of_get_property(dp, "port-wwn", &len);
2371 if (val && len >= WWN_SIZE)
2372 memcpy(nv->port_name, val, WWN_SIZE);
2373
2374 val = of_get_property(dp, "node-wwn", &len);
2375 if (val && len >= WWN_SIZE)
2376 memcpy(nv->node_name, val, WWN_SIZE);
2377 #endif
2378 }
2379
2380 /*
2381 * NVRAM configuration for ISP 2xxx
2382 *
2383 * Input:
2384 * ha = adapter block pointer.
2385 *
2386 * Output:
2387 * initialization control block in response_ring
2388 * host adapters parameters in host adapter block
2389 *
2390 * Returns:
2391 * 0 = success.
2392 */
2393 int
2394 qla2x00_nvram_config(scsi_qla_host_t *vha)
2395 {
2396 int rval;
2397 uint8_t chksum = 0;
2398 uint16_t cnt;
2399 uint8_t *dptr1, *dptr2;
2400 struct qla_hw_data *ha = vha->hw;
2401 init_cb_t *icb = ha->init_cb;
2402 nvram_t *nv = ha->nvram;
2403 uint8_t *ptr = ha->nvram;
2404 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2405
2406 rval = QLA_SUCCESS;
2407
2408 /* Determine NVRAM starting address. */
2409 ha->nvram_size = sizeof(nvram_t);
2410 ha->nvram_base = 0;
2411 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2412 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2413 ha->nvram_base = 0x80;
2414
2415 /* Get NVRAM data and calculate checksum. */
2416 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
2417 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2418 chksum += *ptr++;
2419
2420 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2421 "Contents of NVRAM.\n");
2422 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2423 (uint8_t *)nv, ha->nvram_size);
2424
2425 /* Bad NVRAM data, set defaults parameters. */
2426 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2427 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2428 /* Reset NVRAM data. */
2429 ql_log(ql_log_warn, vha, 0x0064,
2430 "Inconsistent NVRAM "
2431 "detected: checksum=0x%x id=%c version=0x%x.\n",
2432 chksum, nv->id[0], nv->nvram_version);
2433 ql_log(ql_log_warn, vha, 0x0065,
2434 "Falling back to "
2435 "functioning (yet invalid -- WWPN) defaults.\n");
2436
2437 /*
2438 * Set default initialization control block.
2439 */
2440 memset(nv, 0, ha->nvram_size);
2441 nv->parameter_block_version = ICB_VERSION;
2442
2443 if (IS_QLA23XX(ha)) {
2444 nv->firmware_options[0] = BIT_2 | BIT_1;
2445 nv->firmware_options[1] = BIT_7 | BIT_5;
2446 nv->add_firmware_options[0] = BIT_5;
2447 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2448 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2449 nv->special_options[1] = BIT_7;
2450 } else if (IS_QLA2200(ha)) {
2451 nv->firmware_options[0] = BIT_2 | BIT_1;
2452 nv->firmware_options[1] = BIT_7 | BIT_5;
2453 nv->add_firmware_options[0] = BIT_5;
2454 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2455 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2456 } else if (IS_QLA2100(ha)) {
2457 nv->firmware_options[0] = BIT_3 | BIT_1;
2458 nv->firmware_options[1] = BIT_5;
2459 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2460 }
2461
2462 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2463 nv->execution_throttle = __constant_cpu_to_le16(16);
2464 nv->retry_count = 8;
2465 nv->retry_delay = 1;
2466
2467 nv->port_name[0] = 33;
2468 nv->port_name[3] = 224;
2469 nv->port_name[4] = 139;
2470
2471 qla2xxx_nvram_wwn_from_ofw(vha, nv);
2472
2473 nv->login_timeout = 4;
2474
2475 /*
2476 * Set default host adapter parameters
2477 */
2478 nv->host_p[1] = BIT_2;
2479 nv->reset_delay = 5;
2480 nv->port_down_retry_count = 8;
2481 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2482 nv->link_down_timeout = 60;
2483
2484 rval = 1;
2485 }
2486
2487 #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2488 /*
2489 * The SN2 does not provide BIOS emulation which means you can't change
2490 * potentially bogus BIOS settings. Force the use of default settings
2491 * for link rate and frame size. Hope that the rest of the settings
2492 * are valid.
2493 */
2494 if (ia64_platform_is("sn2")) {
2495 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2496 if (IS_QLA23XX(ha))
2497 nv->special_options[1] = BIT_7;
2498 }
2499 #endif
2500
2501 /* Reset Initialization control block */
2502 memset(icb, 0, ha->init_cb_size);
2503
2504 /*
2505 * Setup driver NVRAM options.
2506 */
2507 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2508 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2509 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2510 nv->firmware_options[1] &= ~BIT_4;
2511
2512 if (IS_QLA23XX(ha)) {
2513 nv->firmware_options[0] |= BIT_2;
2514 nv->firmware_options[0] &= ~BIT_3;
2515 nv->special_options[0] &= ~BIT_6;
2516 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
2517
2518 if (IS_QLA2300(ha)) {
2519 if (ha->fb_rev == FPM_2310) {
2520 strcpy(ha->model_number, "QLA2310");
2521 } else {
2522 strcpy(ha->model_number, "QLA2300");
2523 }
2524 } else {
2525 qla2x00_set_model_info(vha, nv->model_number,
2526 sizeof(nv->model_number), "QLA23xx");
2527 }
2528 } else if (IS_QLA2200(ha)) {
2529 nv->firmware_options[0] |= BIT_2;
2530 /*
2531 * 'Point-to-point preferred, else loop' is not a safe
2532 * connection mode setting.
2533 */
2534 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2535 (BIT_5 | BIT_4)) {
2536 /* Force 'loop preferred, else point-to-point'. */
2537 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2538 nv->add_firmware_options[0] |= BIT_5;
2539 }
2540 strcpy(ha->model_number, "QLA22xx");
2541 } else /*if (IS_QLA2100(ha))*/ {
2542 strcpy(ha->model_number, "QLA2100");
2543 }
2544
2545 /*
2546 * Copy over NVRAM RISC parameter block to initialization control block.
2547 */
2548 dptr1 = (uint8_t *)icb;
2549 dptr2 = (uint8_t *)&nv->parameter_block_version;
2550 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2551 while (cnt--)
2552 *dptr1++ = *dptr2++;
2553
2554 /* Copy 2nd half. */
2555 dptr1 = (uint8_t *)icb->add_firmware_options;
2556 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2557 while (cnt--)
2558 *dptr1++ = *dptr2++;
2559
2560 /* Use alternate WWN? */
2561 if (nv->host_p[1] & BIT_7) {
2562 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2563 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2564 }
2565
2566 /* Prepare nodename */
2567 if ((icb->firmware_options[1] & BIT_6) == 0) {
2568 /*
2569 * Firmware will apply the following mask if the nodename was
2570 * not provided.
2571 */
2572 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2573 icb->node_name[0] &= 0xF0;
2574 }
2575
2576 /*
2577 * Set host adapter parameters.
2578 */
2579
2580 /*
2581 * BIT_7 in the host-parameters section allows for modification to
2582 * internal driver logging.
2583 */
2584 if (nv->host_p[0] & BIT_7)
2585 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
2586 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2587 /* Always load RISC code on non ISP2[12]00 chips. */
2588 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2589 ha->flags.disable_risc_code_load = 0;
2590 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2591 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2592 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
2593 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
2594 ha->flags.disable_serdes = 0;
2595
2596 ha->operating_mode =
2597 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2598
2599 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2600 sizeof(ha->fw_seriallink_options));
2601
2602 /* save HBA serial number */
2603 ha->serial0 = icb->port_name[5];
2604 ha->serial1 = icb->port_name[6];
2605 ha->serial2 = icb->port_name[7];
2606 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2607 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
2608
2609 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2610
2611 ha->retry_count = nv->retry_count;
2612
2613 /* Set minimum login_timeout to 4 seconds. */
2614 if (nv->login_timeout != ql2xlogintimeout)
2615 nv->login_timeout = ql2xlogintimeout;
2616 if (nv->login_timeout < 4)
2617 nv->login_timeout = 4;
2618 ha->login_timeout = nv->login_timeout;
2619 icb->login_timeout = nv->login_timeout;
2620
2621 /* Set minimum RATOV to 100 tenths of a second. */
2622 ha->r_a_tov = 100;
2623
2624 ha->loop_reset_delay = nv->reset_delay;
2625
2626 /* Link Down Timeout = 0:
2627 *
2628 * When Port Down timer expires we will start returning
2629 * I/O's to OS with "DID_NO_CONNECT".
2630 *
2631 * Link Down Timeout != 0:
2632 *
2633 * The driver waits for the link to come up after link down
2634 * before returning I/Os to OS with "DID_NO_CONNECT".
2635 */
2636 if (nv->link_down_timeout == 0) {
2637 ha->loop_down_abort_time =
2638 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
2639 } else {
2640 ha->link_down_timeout = nv->link_down_timeout;
2641 ha->loop_down_abort_time =
2642 (LOOP_DOWN_TIME - ha->link_down_timeout);
2643 }
2644
2645 /*
2646 * Need enough time to try and get the port back.
2647 */
2648 ha->port_down_retry_count = nv->port_down_retry_count;
2649 if (qlport_down_retry)
2650 ha->port_down_retry_count = qlport_down_retry;
2651 /* Set login_retry_count */
2652 ha->login_retry_count = nv->retry_count;
2653 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2654 ha->port_down_retry_count > 3)
2655 ha->login_retry_count = ha->port_down_retry_count;
2656 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2657 ha->login_retry_count = ha->port_down_retry_count;
2658 if (ql2xloginretrycount)
2659 ha->login_retry_count = ql2xloginretrycount;
2660
2661 icb->lun_enables = __constant_cpu_to_le16(0);
2662 icb->command_resource_count = 0;
2663 icb->immediate_notify_resource_count = 0;
2664 icb->timeout = __constant_cpu_to_le16(0);
2665
2666 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2667 /* Enable RIO */
2668 icb->firmware_options[0] &= ~BIT_3;
2669 icb->add_firmware_options[0] &=
2670 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2671 icb->add_firmware_options[0] |= BIT_2;
2672 icb->response_accumulation_timer = 3;
2673 icb->interrupt_delay_timer = 5;
2674
2675 vha->flags.process_response_queue = 1;
2676 } else {
2677 /* Enable ZIO. */
2678 if (!vha->flags.init_done) {
2679 ha->zio_mode = icb->add_firmware_options[0] &
2680 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2681 ha->zio_timer = icb->interrupt_delay_timer ?
2682 icb->interrupt_delay_timer: 2;
2683 }
2684 icb->add_firmware_options[0] &=
2685 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2686 vha->flags.process_response_queue = 0;
2687 if (ha->zio_mode != QLA_ZIO_DISABLED) {
2688 ha->zio_mode = QLA_ZIO_MODE_6;
2689
2690 ql_log(ql_log_info, vha, 0x0068,
2691 "ZIO mode %d enabled; timer delay (%d us).\n",
2692 ha->zio_mode, ha->zio_timer * 100);
2693
2694 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2695 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
2696 vha->flags.process_response_queue = 1;
2697 }
2698 }
2699
2700 if (rval) {
2701 ql_log(ql_log_warn, vha, 0x0069,
2702 "NVRAM configuration failed.\n");
2703 }
2704 return (rval);
2705 }
2706
2707 static void
2708 qla2x00_rport_del(void *data)
2709 {
2710 fc_port_t *fcport = data;
2711 struct fc_rport *rport;
2712 scsi_qla_host_t *vha = fcport->vha;
2713 unsigned long flags;
2714
2715 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
2716 rport = fcport->drport ? fcport->drport: fcport->rport;
2717 fcport->drport = NULL;
2718 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2719 if (rport) {
2720 fc_remote_port_delete(rport);
2721 /*
2722 * Release the target mode FC NEXUS in qla_target.c code
2723 * if target mod is enabled.
2724 */
2725 qlt_fc_port_deleted(vha, fcport);
2726 }
2727 }
2728
2729 /**
2730 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2731 * @ha: HA context
2732 * @flags: allocation flags
2733 *
2734 * Returns a pointer to the allocated fcport, or NULL, if none available.
2735 */
2736 fc_port_t *
2737 qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
2738 {
2739 fc_port_t *fcport;
2740
2741 fcport = kzalloc(sizeof(fc_port_t), flags);
2742 if (!fcport)
2743 return NULL;
2744
2745 /* Setup fcport template structure. */
2746 fcport->vha = vha;
2747 fcport->port_type = FCT_UNKNOWN;
2748 fcport->loop_id = FC_NO_LOOP_ID;
2749 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
2750 fcport->supported_classes = FC_COS_UNSPECIFIED;
2751 fcport->scan_state = QLA_FCPORT_SCAN_NONE;
2752
2753 return fcport;
2754 }
2755
2756 /*
2757 * qla2x00_configure_loop
2758 * Updates Fibre Channel Device Database with what is actually on loop.
2759 *
2760 * Input:
2761 * ha = adapter block pointer.
2762 *
2763 * Returns:
2764 * 0 = success.
2765 * 1 = error.
2766 * 2 = database was full and device was not configured.
2767 */
2768 static int
2769 qla2x00_configure_loop(scsi_qla_host_t *vha)
2770 {
2771 int rval;
2772 unsigned long flags, save_flags;
2773 struct qla_hw_data *ha = vha->hw;
2774 rval = QLA_SUCCESS;
2775
2776 /* Get Initiator ID */
2777 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2778 rval = qla2x00_configure_hba(vha);
2779 if (rval != QLA_SUCCESS) {
2780 ql_dbg(ql_dbg_disc, vha, 0x2013,
2781 "Unable to configure HBA.\n");
2782 return (rval);
2783 }
2784 }
2785
2786 save_flags = flags = vha->dpc_flags;
2787 ql_dbg(ql_dbg_disc, vha, 0x2014,
2788 "Configure loop -- dpc flags = 0x%lx.\n", flags);
2789
2790 /*
2791 * If we have both an RSCN and PORT UPDATE pending then handle them
2792 * both at the same time.
2793 */
2794 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2795 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
2796
2797 qla2x00_get_data_rate(vha);
2798
2799 /* Determine what we need to do */
2800 if (ha->current_topology == ISP_CFG_FL &&
2801 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2802
2803 set_bit(RSCN_UPDATE, &flags);
2804
2805 } else if (ha->current_topology == ISP_CFG_F &&
2806 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2807
2808 set_bit(RSCN_UPDATE, &flags);
2809 clear_bit(LOCAL_LOOP_UPDATE, &flags);
2810
2811 } else if (ha->current_topology == ISP_CFG_N) {
2812 clear_bit(RSCN_UPDATE, &flags);
2813
2814 } else if (!vha->flags.online ||
2815 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2816
2817 set_bit(RSCN_UPDATE, &flags);
2818 set_bit(LOCAL_LOOP_UPDATE, &flags);
2819 }
2820
2821 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
2822 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2823 ql_dbg(ql_dbg_disc, vha, 0x2015,
2824 "Loop resync needed, failing.\n");
2825 rval = QLA_FUNCTION_FAILED;
2826 } else
2827 rval = qla2x00_configure_local_loop(vha);
2828 }
2829
2830 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
2831 if (LOOP_TRANSITION(vha)) {
2832 ql_dbg(ql_dbg_disc, vha, 0x201e,
2833 "Needs RSCN update and loop transition.\n");
2834 rval = QLA_FUNCTION_FAILED;
2835 }
2836 else
2837 rval = qla2x00_configure_fabric(vha);
2838 }
2839
2840 if (rval == QLA_SUCCESS) {
2841 if (atomic_read(&vha->loop_down_timer) ||
2842 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2843 rval = QLA_FUNCTION_FAILED;
2844 } else {
2845 atomic_set(&vha->loop_state, LOOP_READY);
2846 ql_dbg(ql_dbg_disc, vha, 0x2069,
2847 "LOOP READY.\n");
2848 }
2849 }
2850
2851 if (rval) {
2852 ql_dbg(ql_dbg_disc, vha, 0x206a,
2853 "%s *** FAILED ***.\n", __func__);
2854 } else {
2855 ql_dbg(ql_dbg_disc, vha, 0x206b,
2856 "%s: exiting normally.\n", __func__);
2857 }
2858
2859 /* Restore state if a resync event occurred during processing */
2860 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2861 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
2862 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2863 if (test_bit(RSCN_UPDATE, &save_flags)) {
2864 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2865 }
2866 }
2867
2868 return (rval);
2869 }
2870
2871
2872
2873 /*
2874 * qla2x00_configure_local_loop
2875 * Updates Fibre Channel Device Database with local loop devices.
2876 *
2877 * Input:
2878 * ha = adapter block pointer.
2879 *
2880 * Returns:
2881 * 0 = success.
2882 */
2883 static int
2884 qla2x00_configure_local_loop(scsi_qla_host_t *vha)
2885 {
2886 int rval, rval2;
2887 int found_devs;
2888 int found;
2889 fc_port_t *fcport, *new_fcport;
2890
2891 uint16_t index;
2892 uint16_t entries;
2893 char *id_iter;
2894 uint16_t loop_id;
2895 uint8_t domain, area, al_pa;
2896 struct qla_hw_data *ha = vha->hw;
2897
2898 found_devs = 0;
2899 new_fcport = NULL;
2900 entries = MAX_FIBRE_DEVICES_LOOP;
2901
2902 /* Get list of logged in devices. */
2903 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
2904 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
2905 &entries);
2906 if (rval != QLA_SUCCESS)
2907 goto cleanup_allocation;
2908
2909 ql_dbg(ql_dbg_disc, vha, 0x2017,
2910 "Entries in ID list (%d).\n", entries);
2911 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
2912 (uint8_t *)ha->gid_list,
2913 entries * sizeof(struct gid_list_info));
2914
2915 /* Allocate temporary fcport for any new fcports discovered. */
2916 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
2917 if (new_fcport == NULL) {
2918 ql_log(ql_log_warn, vha, 0x2018,
2919 "Memory allocation failed for fcport.\n");
2920 rval = QLA_MEMORY_ALLOC_FAILED;
2921 goto cleanup_allocation;
2922 }
2923 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2924
2925 /*
2926 * Mark local devices that were present with FCF_DEVICE_LOST for now.
2927 */
2928 list_for_each_entry(fcport, &vha->vp_fcports, list) {
2929 if (atomic_read(&fcport->state) == FCS_ONLINE &&
2930 fcport->port_type != FCT_BROADCAST &&
2931 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
2932
2933 ql_dbg(ql_dbg_disc, vha, 0x2019,
2934 "Marking port lost loop_id=0x%04x.\n",
2935 fcport->loop_id);
2936
2937 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
2938 }
2939 }
2940
2941 /* Add devices to port list. */
2942 id_iter = (char *)ha->gid_list;
2943 for (index = 0; index < entries; index++) {
2944 domain = ((struct gid_list_info *)id_iter)->domain;
2945 area = ((struct gid_list_info *)id_iter)->area;
2946 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
2947 if (IS_QLA2100(ha) || IS_QLA2200(ha))
2948 loop_id = (uint16_t)
2949 ((struct gid_list_info *)id_iter)->loop_id_2100;
2950 else
2951 loop_id = le16_to_cpu(
2952 ((struct gid_list_info *)id_iter)->loop_id);
2953 id_iter += ha->gid_list_info_size;
2954
2955 /* Bypass reserved domain fields. */
2956 if ((domain & 0xf0) == 0xf0)
2957 continue;
2958
2959 /* Bypass if not same domain and area of adapter. */
2960 if (area && domain &&
2961 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
2962 continue;
2963
2964 /* Bypass invalid local loop ID. */
2965 if (loop_id > LAST_LOCAL_LOOP_ID)
2966 continue;
2967
2968 memset(new_fcport, 0, sizeof(fc_port_t));
2969
2970 /* Fill in member data. */
2971 new_fcport->d_id.b.domain = domain;
2972 new_fcport->d_id.b.area = area;
2973 new_fcport->d_id.b.al_pa = al_pa;
2974 new_fcport->loop_id = loop_id;
2975 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
2976 if (rval2 != QLA_SUCCESS) {
2977 ql_dbg(ql_dbg_disc, vha, 0x201a,
2978 "Failed to retrieve fcport information "
2979 "-- get_port_database=%x, loop_id=0x%04x.\n",
2980 rval2, new_fcport->loop_id);
2981 ql_dbg(ql_dbg_disc, vha, 0x201b,
2982 "Scheduling resync.\n");
2983 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2984 continue;
2985 }
2986
2987 /* Check for matching device in port list. */
2988 found = 0;
2989 fcport = NULL;
2990 list_for_each_entry(fcport, &vha->vp_fcports, list) {
2991 if (memcmp(new_fcport->port_name, fcport->port_name,
2992 WWN_SIZE))
2993 continue;
2994
2995 fcport->flags &= ~FCF_FABRIC_DEVICE;
2996 fcport->loop_id = new_fcport->loop_id;
2997 fcport->port_type = new_fcport->port_type;
2998 fcport->d_id.b24 = new_fcport->d_id.b24;
2999 memcpy(fcport->node_name, new_fcport->node_name,
3000 WWN_SIZE);
3001
3002 found++;
3003 break;
3004 }
3005
3006 if (!found) {
3007 /* New device, add to fcports list. */
3008 list_add_tail(&new_fcport->list, &vha->vp_fcports);
3009
3010 /* Allocate a new replacement fcport. */
3011 fcport = new_fcport;
3012 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
3013 if (new_fcport == NULL) {
3014 ql_log(ql_log_warn, vha, 0x201c,
3015 "Failed to allocate memory for fcport.\n");
3016 rval = QLA_MEMORY_ALLOC_FAILED;
3017 goto cleanup_allocation;
3018 }
3019 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3020 }
3021
3022 /* Base iIDMA settings on HBA port speed. */
3023 fcport->fp_speed = ha->link_data_rate;
3024
3025 qla2x00_update_fcport(vha, fcport);
3026
3027 found_devs++;
3028 }
3029
3030 cleanup_allocation:
3031 kfree(new_fcport);
3032
3033 if (rval != QLA_SUCCESS) {
3034 ql_dbg(ql_dbg_disc, vha, 0x201d,
3035 "Configure local loop error exit: rval=%x.\n", rval);
3036 }
3037
3038 return (rval);
3039 }
3040
3041 static void
3042 qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
3043 {
3044 int rval;
3045 uint16_t mb[4];
3046 struct qla_hw_data *ha = vha->hw;
3047
3048 if (!IS_IIDMA_CAPABLE(ha))
3049 return;
3050
3051 if (atomic_read(&fcport->state) != FCS_ONLINE)
3052 return;
3053
3054 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3055 fcport->fp_speed > ha->link_data_rate)
3056 return;
3057
3058 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
3059 mb);
3060 if (rval != QLA_SUCCESS) {
3061 ql_dbg(ql_dbg_disc, vha, 0x2004,
3062 "Unable to adjust iIDMA "
3063 "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
3064 "%04x.\n", fcport->port_name[0], fcport->port_name[1],
3065 fcport->port_name[2], fcport->port_name[3],
3066 fcport->port_name[4], fcport->port_name[5],
3067 fcport->port_name[6], fcport->port_name[7], rval,
3068 fcport->fp_speed, mb[0], mb[1]);
3069 } else {
3070 ql_dbg(ql_dbg_disc, vha, 0x2005,
3071 "iIDMA adjusted to %s GB/s "
3072 "on %02x%02x%02x%02x%02x%02x%02x%02x.\n",
3073 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
3074 fcport->port_name[0], fcport->port_name[1],
3075 fcport->port_name[2], fcport->port_name[3],
3076 fcport->port_name[4], fcport->port_name[5],
3077 fcport->port_name[6], fcport->port_name[7]);
3078 }
3079 }
3080
3081 static void
3082 qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
3083 {
3084 struct fc_rport_identifiers rport_ids;
3085 struct fc_rport *rport;
3086 unsigned long flags;
3087
3088 qla2x00_rport_del(fcport);
3089
3090 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3091 rport_ids.port_name = wwn_to_u64(fcport->port_name);
3092 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3093 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
3094 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3095 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
3096 if (!rport) {
3097 ql_log(ql_log_warn, vha, 0x2006,
3098 "Unable to allocate fc remote port.\n");
3099 return;
3100 }
3101 /*
3102 * Create target mode FC NEXUS in qla_target.c if target mode is
3103 * enabled..
3104 */
3105 qlt_fc_port_added(vha, fcport);
3106
3107 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
3108 *((fc_port_t **)rport->dd_data) = fcport;
3109 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
3110
3111 rport->supported_classes = fcport->supported_classes;
3112
3113 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3114 if (fcport->port_type == FCT_INITIATOR)
3115 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3116 if (fcport->port_type == FCT_TARGET)
3117 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
3118 fc_remote_port_rolechg(rport, rport_ids.roles);
3119 }
3120
3121 /*
3122 * qla2x00_update_fcport
3123 * Updates device on list.
3124 *
3125 * Input:
3126 * ha = adapter block pointer.
3127 * fcport = port structure pointer.
3128 *
3129 * Return:
3130 * 0 - Success
3131 * BIT_0 - error
3132 *
3133 * Context:
3134 * Kernel context.
3135 */
3136 void
3137 qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
3138 {
3139 fcport->vha = vha;
3140 fcport->login_retry = 0;
3141 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
3142
3143 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
3144 qla2x00_iidma_fcport(vha, fcport);
3145 qla24xx_update_fcport_fcp_prio(vha, fcport);
3146 qla2x00_reg_remote_port(vha, fcport);
3147 }
3148
3149 /*
3150 * qla2x00_configure_fabric
3151 * Setup SNS devices with loop ID's.
3152 *
3153 * Input:
3154 * ha = adapter block pointer.
3155 *
3156 * Returns:
3157 * 0 = success.
3158 * BIT_0 = error
3159 */
3160 static int
3161 qla2x00_configure_fabric(scsi_qla_host_t *vha)
3162 {
3163 int rval;
3164 fc_port_t *fcport;
3165 uint16_t next_loopid;
3166 uint16_t mb[MAILBOX_REGISTER_COUNT];
3167 uint16_t loop_id;
3168 LIST_HEAD(new_fcports);
3169 struct qla_hw_data *ha = vha->hw;
3170 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
3171
3172 /* If FL port exists, then SNS is present */
3173 if (IS_FWI2_CAPABLE(ha))
3174 loop_id = NPH_F_PORT;
3175 else
3176 loop_id = SNS_FL_PORT;
3177 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
3178 if (rval != QLA_SUCCESS) {
3179 ql_dbg(ql_dbg_disc, vha, 0x201f,
3180 "MBX_GET_PORT_NAME failed, No FL Port.\n");
3181
3182 vha->device_flags &= ~SWITCH_FOUND;
3183 return (QLA_SUCCESS);
3184 }
3185 vha->device_flags |= SWITCH_FOUND;
3186
3187 do {
3188 /* FDMI support. */
3189 if (ql2xfdmienable &&
3190 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3191 qla2x00_fdmi_register(vha);
3192
3193 /* Ensure we are logged into the SNS. */
3194 if (IS_FWI2_CAPABLE(ha))
3195 loop_id = NPH_SNS;
3196 else
3197 loop_id = SIMPLE_NAME_SERVER;
3198 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3199 0xfc, mb, BIT_1|BIT_0);
3200 if (rval != QLA_SUCCESS) {
3201 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3202 break;
3203 }
3204 if (mb[0] != MBS_COMMAND_COMPLETE) {
3205 ql_dbg(ql_dbg_disc, vha, 0x2042,
3206 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3207 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3208 mb[2], mb[6], mb[7]);
3209 return (QLA_SUCCESS);
3210 }
3211
3212 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3213 if (qla2x00_rft_id(vha)) {
3214 /* EMPTY */
3215 ql_dbg(ql_dbg_disc, vha, 0x2045,
3216 "Register FC-4 TYPE failed.\n");
3217 }
3218 if (qla2x00_rff_id(vha)) {
3219 /* EMPTY */
3220 ql_dbg(ql_dbg_disc, vha, 0x2049,
3221 "Register FC-4 Features failed.\n");
3222 }
3223 if (qla2x00_rnn_id(vha)) {
3224 /* EMPTY */
3225 ql_dbg(ql_dbg_disc, vha, 0x204f,
3226 "Register Node Name failed.\n");
3227 } else if (qla2x00_rsnn_nn(vha)) {
3228 /* EMPTY */
3229 ql_dbg(ql_dbg_disc, vha, 0x2053,
3230 "Register Symobilic Node Name failed.\n");
3231 }
3232 }
3233
3234 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
3235 if (rval != QLA_SUCCESS)
3236 break;
3237
3238 /* Add new ports to existing port list */
3239 list_splice_tail_init(&new_fcports, &vha->vp_fcports);
3240
3241 /* Starting free loop ID. */
3242 next_loopid = ha->min_external_loopid;
3243
3244 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3245 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3246 break;
3247
3248 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3249 continue;
3250
3251 /* Logout lost/gone fabric devices (non-FCP2) */
3252 if (fcport->scan_state != QLA_FCPORT_SCAN_FOUND &&
3253 atomic_read(&fcport->state) == FCS_ONLINE) {
3254 qla2x00_mark_device_lost(vha, fcport,
3255 ql2xplogiabsentdevice, 0);
3256 if (fcport->loop_id != FC_NO_LOOP_ID &&
3257 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
3258 fcport->port_type != FCT_INITIATOR &&
3259 fcport->port_type != FCT_BROADCAST) {
3260 ha->isp_ops->fabric_logout(vha,
3261 fcport->loop_id,
3262 fcport->d_id.b.domain,
3263 fcport->d_id.b.area,
3264 fcport->d_id.b.al_pa);
3265 }
3266 continue;
3267 }
3268 fcport->scan_state = QLA_FCPORT_SCAN_NONE;
3269
3270 /* Login fabric devices that need a login */
3271 if ((fcport->flags & FCF_LOGIN_NEEDED) != 0 &&
3272 atomic_read(&vha->loop_down_timer) == 0) {
3273 if (fcport->loop_id == FC_NO_LOOP_ID) {
3274 fcport->loop_id = next_loopid;
3275 rval = qla2x00_find_new_loop_id(
3276 base_vha, fcport);
3277 if (rval != QLA_SUCCESS) {
3278 /* Ran out of IDs to use */
3279 continue;
3280 }
3281 }
3282 }
3283
3284 /* Login and update database */
3285 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3286 }
3287 } while (0);
3288
3289 if (rval) {
3290 ql_dbg(ql_dbg_disc, vha, 0x2068,
3291 "Configure fabric error exit rval=%d.\n", rval);
3292 }
3293
3294 return (rval);
3295 }
3296
3297 /*
3298 * qla2x00_find_all_fabric_devs
3299 *
3300 * Input:
3301 * ha = adapter block pointer.
3302 * dev = database device entry pointer.
3303 *
3304 * Returns:
3305 * 0 = success.
3306 *
3307 * Context:
3308 * Kernel context.
3309 */
3310 static int
3311 qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3312 struct list_head *new_fcports)
3313 {
3314 int rval;
3315 uint16_t loop_id;
3316 fc_port_t *fcport, *new_fcport, *fcptemp;
3317 int found;
3318
3319 sw_info_t *swl;
3320 int swl_idx;
3321 int first_dev, last_dev;
3322 port_id_t wrap = {}, nxt_d_id;
3323 struct qla_hw_data *ha = vha->hw;
3324 struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev);
3325 struct scsi_qla_host *tvp;
3326
3327 rval = QLA_SUCCESS;
3328
3329 /* Try GID_PT to get device list, else GAN. */
3330 if (!ha->swl)
3331 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
3332 GFP_KERNEL);
3333 swl = ha->swl;
3334 if (!swl) {
3335 /*EMPTY*/
3336 ql_dbg(ql_dbg_disc, vha, 0x2054,
3337 "GID_PT allocations failed, fallback on GA_NXT.\n");
3338 } else {
3339 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
3340 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
3341 swl = NULL;
3342 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
3343 swl = NULL;
3344 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
3345 swl = NULL;
3346 } else if (ql2xiidmaenable &&
3347 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3348 qla2x00_gpsc(vha, swl);
3349 }
3350
3351 /* If other queries succeeded probe for FC-4 type */
3352 if (swl)
3353 qla2x00_gff_id(vha, swl);
3354 }
3355 swl_idx = 0;
3356
3357 /* Allocate temporary fcport for any new fcports discovered. */
3358 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
3359 if (new_fcport == NULL) {
3360 ql_log(ql_log_warn, vha, 0x205e,
3361 "Failed to allocate memory for fcport.\n");
3362 return (QLA_MEMORY_ALLOC_FAILED);
3363 }
3364 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3365 /* Set start port ID scan at adapter ID. */
3366 first_dev = 1;
3367 last_dev = 0;
3368
3369 /* Starting free loop ID. */
3370 loop_id = ha->min_external_loopid;
3371 for (; loop_id <= ha->max_loop_id; loop_id++) {
3372 if (qla2x00_is_reserved_id(vha, loop_id))
3373 continue;
3374
3375 if (ha->current_topology == ISP_CFG_FL &&
3376 (atomic_read(&vha->loop_down_timer) ||
3377 LOOP_TRANSITION(vha))) {
3378 atomic_set(&vha->loop_down_timer, 0);
3379 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3380 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
3381 break;
3382 }
3383
3384 if (swl != NULL) {
3385 if (last_dev) {
3386 wrap.b24 = new_fcport->d_id.b24;
3387 } else {
3388 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3389 memcpy(new_fcport->node_name,
3390 swl[swl_idx].node_name, WWN_SIZE);
3391 memcpy(new_fcport->port_name,
3392 swl[swl_idx].port_name, WWN_SIZE);
3393 memcpy(new_fcport->fabric_port_name,
3394 swl[swl_idx].fabric_port_name, WWN_SIZE);
3395 new_fcport->fp_speed = swl[swl_idx].fp_speed;
3396 new_fcport->fc4_type = swl[swl_idx].fc4_type;
3397
3398 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3399 last_dev = 1;
3400 }
3401 swl_idx++;
3402 }
3403 } else {
3404 /* Send GA_NXT to the switch */
3405 rval = qla2x00_ga_nxt(vha, new_fcport);
3406 if (rval != QLA_SUCCESS) {
3407 ql_log(ql_log_warn, vha, 0x2064,
3408 "SNS scan failed -- assuming "
3409 "zero-entry result.\n");
3410 list_for_each_entry_safe(fcport, fcptemp,
3411 new_fcports, list) {
3412 list_del(&fcport->list);
3413 kfree(fcport);
3414 }
3415 rval = QLA_SUCCESS;
3416 break;
3417 }
3418 }
3419
3420 /* If wrap on switch device list, exit. */
3421 if (first_dev) {
3422 wrap.b24 = new_fcport->d_id.b24;
3423 first_dev = 0;
3424 } else if (new_fcport->d_id.b24 == wrap.b24) {
3425 ql_dbg(ql_dbg_disc, vha, 0x2065,
3426 "Device wrap (%02x%02x%02x).\n",
3427 new_fcport->d_id.b.domain,
3428 new_fcport->d_id.b.area,
3429 new_fcport->d_id.b.al_pa);
3430 break;
3431 }
3432
3433 /* Bypass if same physical adapter. */
3434 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
3435 continue;
3436
3437 /* Bypass virtual ports of the same host. */
3438 found = 0;
3439 if (ha->num_vhosts) {
3440 unsigned long flags;
3441
3442 spin_lock_irqsave(&ha->vport_slock, flags);
3443 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
3444 if (new_fcport->d_id.b24 == vp->d_id.b24) {
3445 found = 1;
3446 break;
3447 }
3448 }
3449 spin_unlock_irqrestore(&ha->vport_slock, flags);
3450
3451 if (found)
3452 continue;
3453 }
3454
3455 /* Bypass if same domain and area of adapter. */
3456 if (((new_fcport->d_id.b24 & 0xffff00) ==
3457 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
3458 ISP_CFG_FL)
3459 continue;
3460
3461 /* Bypass reserved domain fields. */
3462 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3463 continue;
3464
3465 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
3466 if (ql2xgffidenable &&
3467 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3468 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
3469 continue;
3470
3471 /* Locate matching device in database. */
3472 found = 0;
3473 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3474 if (memcmp(new_fcport->port_name, fcport->port_name,
3475 WWN_SIZE))
3476 continue;
3477
3478 fcport->scan_state = QLA_FCPORT_SCAN_FOUND;
3479
3480 found++;
3481
3482 /* Update port state. */
3483 memcpy(fcport->fabric_port_name,
3484 new_fcport->fabric_port_name, WWN_SIZE);
3485 fcport->fp_speed = new_fcport->fp_speed;
3486
3487 /*
3488 * If address the same and state FCS_ONLINE, nothing
3489 * changed.
3490 */
3491 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3492 atomic_read(&fcport->state) == FCS_ONLINE) {
3493 break;
3494 }
3495
3496 /*
3497 * If device was not a fabric device before.
3498 */
3499 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3500 fcport->d_id.b24 = new_fcport->d_id.b24;
3501 qla2x00_clear_loop_id(fcport);
3502 fcport->flags |= (FCF_FABRIC_DEVICE |
3503 FCF_LOGIN_NEEDED);
3504 break;
3505 }
3506
3507 /*
3508 * Port ID changed or device was marked to be updated;
3509 * Log it out if still logged in and mark it for
3510 * relogin later.
3511 */
3512 fcport->d_id.b24 = new_fcport->d_id.b24;
3513 fcport->flags |= FCF_LOGIN_NEEDED;
3514 if (fcport->loop_id != FC_NO_LOOP_ID &&
3515 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
3516 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
3517 fcport->port_type != FCT_INITIATOR &&
3518 fcport->port_type != FCT_BROADCAST) {
3519 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
3520 fcport->d_id.b.domain, fcport->d_id.b.area,
3521 fcport->d_id.b.al_pa);
3522 qla2x00_clear_loop_id(fcport);
3523 }
3524
3525 break;
3526 }
3527
3528 if (found)
3529 continue;
3530 /* If device was not in our fcports list, then add it. */
3531 list_add_tail(&new_fcport->list, new_fcports);
3532
3533 /* Allocate a new replacement fcport. */
3534 nxt_d_id.b24 = new_fcport->d_id.b24;
3535 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
3536 if (new_fcport == NULL) {
3537 ql_log(ql_log_warn, vha, 0x2066,
3538 "Memory allocation failed for fcport.\n");
3539 return (QLA_MEMORY_ALLOC_FAILED);
3540 }
3541 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3542 new_fcport->d_id.b24 = nxt_d_id.b24;
3543 }
3544
3545 kfree(new_fcport);
3546
3547 return (rval);
3548 }
3549
3550 /*
3551 * qla2x00_find_new_loop_id
3552 * Scan through our port list and find a new usable loop ID.
3553 *
3554 * Input:
3555 * ha: adapter state pointer.
3556 * dev: port structure pointer.
3557 *
3558 * Returns:
3559 * qla2x00 local function return status code.
3560 *
3561 * Context:
3562 * Kernel context.
3563 */
3564 int
3565 qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
3566 {
3567 int rval;
3568 struct qla_hw_data *ha = vha->hw;
3569 unsigned long flags = 0;
3570
3571 rval = QLA_SUCCESS;
3572
3573 spin_lock_irqsave(&ha->vport_slock, flags);
3574
3575 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3576 LOOPID_MAP_SIZE);
3577 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3578 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3579 dev->loop_id = FC_NO_LOOP_ID;
3580 rval = QLA_FUNCTION_FAILED;
3581 } else
3582 set_bit(dev->loop_id, ha->loop_id_map);
3583
3584 spin_unlock_irqrestore(&ha->vport_slock, flags);
3585
3586 if (rval == QLA_SUCCESS)
3587 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3588 "Assigning new loopid=%x, portid=%x.\n",
3589 dev->loop_id, dev->d_id.b24);
3590 else
3591 ql_log(ql_log_warn, dev->vha, 0x2087,
3592 "No loop_id's available, portid=%x.\n",
3593 dev->d_id.b24);
3594
3595 return (rval);
3596 }
3597
3598 /*
3599 * qla2x00_fabric_dev_login
3600 * Login fabric target device and update FC port database.
3601 *
3602 * Input:
3603 * ha: adapter state pointer.
3604 * fcport: port structure list pointer.
3605 * next_loopid: contains value of a new loop ID that can be used
3606 * by the next login attempt.
3607 *
3608 * Returns:
3609 * qla2x00 local function return status code.
3610 *
3611 * Context:
3612 * Kernel context.
3613 */
3614 static int
3615 qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
3616 uint16_t *next_loopid)
3617 {
3618 int rval;
3619 int retry;
3620 uint8_t opts;
3621 struct qla_hw_data *ha = vha->hw;
3622
3623 rval = QLA_SUCCESS;
3624 retry = 0;
3625
3626 if (IS_ALOGIO_CAPABLE(ha)) {
3627 if (fcport->flags & FCF_ASYNC_SENT)
3628 return rval;
3629 fcport->flags |= FCF_ASYNC_SENT;
3630 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3631 if (!rval)
3632 return rval;
3633 }
3634
3635 fcport->flags &= ~FCF_ASYNC_SENT;
3636 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
3637 if (rval == QLA_SUCCESS) {
3638 /* Send an ADISC to FCP2 devices.*/
3639 opts = 0;
3640 if (fcport->flags & FCF_FCP2_DEVICE)
3641 opts |= BIT_1;
3642 rval = qla2x00_get_port_database(vha, fcport, opts);
3643 if (rval != QLA_SUCCESS) {
3644 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
3645 fcport->d_id.b.domain, fcport->d_id.b.area,
3646 fcport->d_id.b.al_pa);
3647 qla2x00_mark_device_lost(vha, fcport, 1, 0);
3648 } else {
3649 qla2x00_update_fcport(vha, fcport);
3650 }
3651 } else {
3652 /* Retry Login. */
3653 qla2x00_mark_device_lost(vha, fcport, 1, 0);
3654 }
3655
3656 return (rval);
3657 }
3658
3659 /*
3660 * qla2x00_fabric_login
3661 * Issue fabric login command.
3662 *
3663 * Input:
3664 * ha = adapter block pointer.
3665 * device = pointer to FC device type structure.
3666 *
3667 * Returns:
3668 * 0 - Login successfully
3669 * 1 - Login failed
3670 * 2 - Initiator device
3671 * 3 - Fatal error
3672 */
3673 int
3674 qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
3675 uint16_t *next_loopid)
3676 {
3677 int rval;
3678 int retry;
3679 uint16_t tmp_loopid;
3680 uint16_t mb[MAILBOX_REGISTER_COUNT];
3681 struct qla_hw_data *ha = vha->hw;
3682
3683 retry = 0;
3684 tmp_loopid = 0;
3685
3686 for (;;) {
3687 ql_dbg(ql_dbg_disc, vha, 0x2000,
3688 "Trying Fabric Login w/loop id 0x%04x for port "
3689 "%02x%02x%02x.\n",
3690 fcport->loop_id, fcport->d_id.b.domain,
3691 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3692
3693 /* Login fcport on switch. */
3694 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
3695 fcport->d_id.b.domain, fcport->d_id.b.area,
3696 fcport->d_id.b.al_pa, mb, BIT_0);
3697 if (rval != QLA_SUCCESS) {
3698 return rval;
3699 }
3700 if (mb[0] == MBS_PORT_ID_USED) {
3701 /*
3702 * Device has another loop ID. The firmware team
3703 * recommends the driver perform an implicit login with
3704 * the specified ID again. The ID we just used is save
3705 * here so we return with an ID that can be tried by
3706 * the next login.
3707 */
3708 retry++;
3709 tmp_loopid = fcport->loop_id;
3710 fcport->loop_id = mb[1];
3711
3712 ql_dbg(ql_dbg_disc, vha, 0x2001,
3713 "Fabric Login: port in use - next loop "
3714 "id=0x%04x, port id= %02x%02x%02x.\n",
3715 fcport->loop_id, fcport->d_id.b.domain,
3716 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3717
3718 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3719 /*
3720 * Login succeeded.
3721 */
3722 if (retry) {
3723 /* A retry occurred before. */
3724 *next_loopid = tmp_loopid;
3725 } else {
3726 /*
3727 * No retry occurred before. Just increment the
3728 * ID value for next login.
3729 */
3730 *next_loopid = (fcport->loop_id + 1);
3731 }
3732
3733 if (mb[1] & BIT_0) {
3734 fcport->port_type = FCT_INITIATOR;
3735 } else {
3736 fcport->port_type = FCT_TARGET;
3737 if (mb[1] & BIT_1) {
3738 fcport->flags |= FCF_FCP2_DEVICE;
3739 }
3740 }
3741
3742 if (mb[10] & BIT_0)
3743 fcport->supported_classes |= FC_COS_CLASS2;
3744 if (mb[10] & BIT_1)
3745 fcport->supported_classes |= FC_COS_CLASS3;
3746
3747 if (IS_FWI2_CAPABLE(ha)) {
3748 if (mb[10] & BIT_7)
3749 fcport->flags |=
3750 FCF_CONF_COMP_SUPPORTED;
3751 }
3752
3753 rval = QLA_SUCCESS;
3754 break;
3755 } else if (mb[0] == MBS_LOOP_ID_USED) {
3756 /*
3757 * Loop ID already used, try next loop ID.
3758 */
3759 fcport->loop_id++;
3760 rval = qla2x00_find_new_loop_id(vha, fcport);
3761 if (rval != QLA_SUCCESS) {
3762 /* Ran out of loop IDs to use */
3763 break;
3764 }
3765 } else if (mb[0] == MBS_COMMAND_ERROR) {
3766 /*
3767 * Firmware possibly timed out during login. If NO
3768 * retries are left to do then the device is declared
3769 * dead.
3770 */
3771 *next_loopid = fcport->loop_id;
3772 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
3773 fcport->d_id.b.domain, fcport->d_id.b.area,
3774 fcport->d_id.b.al_pa);
3775 qla2x00_mark_device_lost(vha, fcport, 1, 0);
3776
3777 rval = 1;
3778 break;
3779 } else {
3780 /*
3781 * unrecoverable / not handled error
3782 */
3783 ql_dbg(ql_dbg_disc, vha, 0x2002,
3784 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3785 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3786 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3787 fcport->loop_id, jiffies);
3788
3789 *next_loopid = fcport->loop_id;
3790 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
3791 fcport->d_id.b.domain, fcport->d_id.b.area,
3792 fcport->d_id.b.al_pa);
3793 qla2x00_clear_loop_id(fcport);
3794 fcport->login_retry = 0;
3795
3796 rval = 3;
3797 break;
3798 }
3799 }
3800
3801 return (rval);
3802 }
3803
3804 /*
3805 * qla2x00_local_device_login
3806 * Issue local device login command.
3807 *
3808 * Input:
3809 * ha = adapter block pointer.
3810 * loop_id = loop id of device to login to.
3811 *
3812 * Returns (Where's the #define!!!!):
3813 * 0 - Login successfully
3814 * 1 - Login failed
3815 * 3 - Fatal error
3816 */
3817 int
3818 qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
3819 {
3820 int rval;
3821 uint16_t mb[MAILBOX_REGISTER_COUNT];
3822
3823 memset(mb, 0, sizeof(mb));
3824 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
3825 if (rval == QLA_SUCCESS) {
3826 /* Interrogate mailbox registers for any errors */
3827 if (mb[0] == MBS_COMMAND_ERROR)
3828 rval = 1;
3829 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
3830 /* device not in PCB table */
3831 rval = 3;
3832 }
3833
3834 return (rval);
3835 }
3836
3837 /*
3838 * qla2x00_loop_resync
3839 * Resync with fibre channel devices.
3840 *
3841 * Input:
3842 * ha = adapter block pointer.
3843 *
3844 * Returns:
3845 * 0 = success
3846 */
3847 int
3848 qla2x00_loop_resync(scsi_qla_host_t *vha)
3849 {
3850 int rval = QLA_SUCCESS;
3851 uint32_t wait_time;
3852 struct req_que *req;
3853 struct rsp_que *rsp;
3854
3855 if (vha->hw->flags.cpu_affinity_enabled)
3856 req = vha->hw->req_q_map[0];
3857 else
3858 req = vha->req;
3859 rsp = req->rsp;
3860
3861 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3862 if (vha->flags.online) {
3863 if (!(rval = qla2x00_fw_ready(vha))) {
3864 /* Wait at most MAX_TARGET RSCNs for a stable link. */
3865 wait_time = 256;
3866 do {
3867 /* Issue a marker after FW becomes ready. */
3868 qla2x00_marker(vha, req, rsp, 0, 0,
3869 MK_SYNC_ALL);
3870 vha->marker_needed = 0;
3871
3872 /* Remap devices on Loop. */
3873 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3874
3875 qla2x00_configure_loop(vha);
3876 wait_time--;
3877 } while (!atomic_read(&vha->loop_down_timer) &&
3878 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
3879 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
3880 &vha->dpc_flags)));
3881 }
3882 }
3883
3884 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
3885 return (QLA_FUNCTION_FAILED);
3886
3887 if (rval)
3888 ql_dbg(ql_dbg_disc, vha, 0x206c,
3889 "%s *** FAILED ***.\n", __func__);
3890
3891 return (rval);
3892 }
3893
3894 /*
3895 * qla2x00_perform_loop_resync
3896 * Description: This function will set the appropriate flags and call
3897 * qla2x00_loop_resync. If successful loop will be resynced
3898 * Arguments : scsi_qla_host_t pointer
3899 * returm : Success or Failure
3900 */
3901
3902 int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
3903 {
3904 int32_t rval = 0;
3905
3906 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
3907 /*Configure the flags so that resync happens properly*/
3908 atomic_set(&ha->loop_down_timer, 0);
3909 if (!(ha->device_flags & DFLG_NO_CABLE)) {
3910 atomic_set(&ha->loop_state, LOOP_UP);
3911 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
3912 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
3913 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
3914
3915 rval = qla2x00_loop_resync(ha);
3916 } else
3917 atomic_set(&ha->loop_state, LOOP_DEAD);
3918
3919 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
3920 }
3921
3922 return rval;
3923 }
3924
3925 void
3926 qla2x00_update_fcports(scsi_qla_host_t *base_vha)
3927 {
3928 fc_port_t *fcport;
3929 struct scsi_qla_host *vha;
3930 struct qla_hw_data *ha = base_vha->hw;
3931 unsigned long flags;
3932
3933 spin_lock_irqsave(&ha->vport_slock, flags);
3934 /* Go with deferred removal of rport references. */
3935 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
3936 atomic_inc(&vha->vref_count);
3937 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3938 if (fcport->drport &&
3939 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
3940 spin_unlock_irqrestore(&ha->vport_slock, flags);
3941
3942 qla2x00_rport_del(fcport);
3943
3944 spin_lock_irqsave(&ha->vport_slock, flags);
3945 }
3946 }
3947 atomic_dec(&vha->vref_count);
3948 }
3949 spin_unlock_irqrestore(&ha->vport_slock, flags);
3950 }
3951
3952 /* Assumes idc_lock always held on entry */
3953 void
3954 qla83xx_reset_ownership(scsi_qla_host_t *vha)
3955 {
3956 struct qla_hw_data *ha = vha->hw;
3957 uint32_t drv_presence, drv_presence_mask;
3958 uint32_t dev_part_info1, dev_part_info2, class_type;
3959 uint32_t class_type_mask = 0x3;
3960 uint16_t fcoe_other_function = 0xffff, i;
3961
3962 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
3963
3964 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
3965 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
3966 for (i = 0; i < 8; i++) {
3967 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
3968 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
3969 (i != ha->portnum)) {
3970 fcoe_other_function = i;
3971 break;
3972 }
3973 }
3974 if (fcoe_other_function == 0xffff) {
3975 for (i = 0; i < 8; i++) {
3976 class_type = ((dev_part_info2 >> (i * 4)) &
3977 class_type_mask);
3978 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
3979 ((i + 8) != ha->portnum)) {
3980 fcoe_other_function = i + 8;
3981 break;
3982 }
3983 }
3984 }
3985 /*
3986 * Prepare drv-presence mask based on fcoe functions present.
3987 * However consider only valid physical fcoe function numbers (0-15).
3988 */
3989 drv_presence_mask = ~((1 << (ha->portnum)) |
3990 ((fcoe_other_function == 0xffff) ?
3991 0 : (1 << (fcoe_other_function))));
3992
3993 /* We are the reset owner iff:
3994 * - No other protocol drivers present.
3995 * - This is the lowest among fcoe functions. */
3996 if (!(drv_presence & drv_presence_mask) &&
3997 (ha->portnum < fcoe_other_function)) {
3998 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
3999 "This host is Reset owner.\n");
4000 ha->flags.nic_core_reset_owner = 1;
4001 }
4002 }
4003
4004 static int
4005 __qla83xx_set_drv_ack(scsi_qla_host_t *vha)
4006 {
4007 int rval = QLA_SUCCESS;
4008 struct qla_hw_data *ha = vha->hw;
4009 uint32_t drv_ack;
4010
4011 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4012 if (rval == QLA_SUCCESS) {
4013 drv_ack |= (1 << ha->portnum);
4014 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4015 }
4016
4017 return rval;
4018 }
4019
4020 static int
4021 __qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4022 {
4023 int rval = QLA_SUCCESS;
4024 struct qla_hw_data *ha = vha->hw;
4025 uint32_t drv_ack;
4026
4027 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4028 if (rval == QLA_SUCCESS) {
4029 drv_ack &= ~(1 << ha->portnum);
4030 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4031 }
4032
4033 return rval;
4034 }
4035
4036 static const char *
4037 qla83xx_dev_state_to_string(uint32_t dev_state)
4038 {
4039 switch (dev_state) {
4040 case QLA8XXX_DEV_COLD:
4041 return "COLD/RE-INIT";
4042 case QLA8XXX_DEV_INITIALIZING:
4043 return "INITIALIZING";
4044 case QLA8XXX_DEV_READY:
4045 return "READY";
4046 case QLA8XXX_DEV_NEED_RESET:
4047 return "NEED RESET";
4048 case QLA8XXX_DEV_NEED_QUIESCENT:
4049 return "NEED QUIESCENT";
4050 case QLA8XXX_DEV_FAILED:
4051 return "FAILED";
4052 case QLA8XXX_DEV_QUIESCENT:
4053 return "QUIESCENT";
4054 default:
4055 return "Unknown";
4056 }
4057 }
4058
4059 /* Assumes idc-lock always held on entry */
4060 void
4061 qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4062 {
4063 struct qla_hw_data *ha = vha->hw;
4064 uint32_t idc_audit_reg = 0, duration_secs = 0;
4065
4066 switch (audit_type) {
4067 case IDC_AUDIT_TIMESTAMP:
4068 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4069 idc_audit_reg = (ha->portnum) |
4070 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4071 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4072 break;
4073
4074 case IDC_AUDIT_COMPLETION:
4075 duration_secs = ((jiffies_to_msecs(jiffies) -
4076 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4077 idc_audit_reg = (ha->portnum) |
4078 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4079 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4080 break;
4081
4082 default:
4083 ql_log(ql_log_warn, vha, 0xb078,
4084 "Invalid audit type specified.\n");
4085 break;
4086 }
4087 }
4088
4089 /* Assumes idc_lock always held on entry */
4090 static int
4091 qla83xx_initiating_reset(scsi_qla_host_t *vha)
4092 {
4093 struct qla_hw_data *ha = vha->hw;
4094 uint32_t idc_control, dev_state;
4095
4096 __qla83xx_get_idc_control(vha, &idc_control);
4097 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4098 ql_log(ql_log_info, vha, 0xb080,
4099 "NIC Core reset has been disabled. idc-control=0x%x\n",
4100 idc_control);
4101 return QLA_FUNCTION_FAILED;
4102 }
4103
4104 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4105 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4106 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4107 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4108 QLA8XXX_DEV_NEED_RESET);
4109 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4110 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4111 } else {
4112 const char *state = qla83xx_dev_state_to_string(dev_state);
4113 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4114
4115 /* SV: XXX: Is timeout required here? */
4116 /* Wait for IDC state change READY -> NEED_RESET */
4117 while (dev_state == QLA8XXX_DEV_READY) {
4118 qla83xx_idc_unlock(vha, 0);
4119 msleep(200);
4120 qla83xx_idc_lock(vha, 0);
4121 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4122 }
4123 }
4124
4125 /* Send IDC ack by writing to drv-ack register */
4126 __qla83xx_set_drv_ack(vha);
4127
4128 return QLA_SUCCESS;
4129 }
4130
4131 int
4132 __qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4133 {
4134 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4135 }
4136
4137 int
4138 __qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4139 {
4140 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4141 }
4142
4143 static int
4144 qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4145 {
4146 uint32_t drv_presence = 0;
4147 struct qla_hw_data *ha = vha->hw;
4148
4149 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4150 if (drv_presence & (1 << ha->portnum))
4151 return QLA_SUCCESS;
4152 else
4153 return QLA_TEST_FAILED;
4154 }
4155
4156 int
4157 qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4158 {
4159 int rval = QLA_SUCCESS;
4160 struct qla_hw_data *ha = vha->hw;
4161
4162 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4163 "Entered %s().\n", __func__);
4164
4165 if (vha->device_flags & DFLG_DEV_FAILED) {
4166 ql_log(ql_log_warn, vha, 0xb059,
4167 "Device in unrecoverable FAILED state.\n");
4168 return QLA_FUNCTION_FAILED;
4169 }
4170
4171 qla83xx_idc_lock(vha, 0);
4172
4173 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4174 ql_log(ql_log_warn, vha, 0xb05a,
4175 "Function=0x%x has been removed from IDC participation.\n",
4176 ha->portnum);
4177 rval = QLA_FUNCTION_FAILED;
4178 goto exit;
4179 }
4180
4181 qla83xx_reset_ownership(vha);
4182
4183 rval = qla83xx_initiating_reset(vha);
4184
4185 /*
4186 * Perform reset if we are the reset-owner,
4187 * else wait till IDC state changes to READY/FAILED.
4188 */
4189 if (rval == QLA_SUCCESS) {
4190 rval = qla83xx_idc_state_handler(vha);
4191
4192 if (rval == QLA_SUCCESS)
4193 ha->flags.nic_core_hung = 0;
4194 __qla83xx_clear_drv_ack(vha);
4195 }
4196
4197 exit:
4198 qla83xx_idc_unlock(vha, 0);
4199
4200 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4201
4202 return rval;
4203 }
4204
4205 int
4206 qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4207 {
4208 struct qla_hw_data *ha = vha->hw;
4209 int rval = QLA_FUNCTION_FAILED;
4210
4211 if (!IS_MCTP_CAPABLE(ha)) {
4212 /* This message can be removed from the final version */
4213 ql_log(ql_log_info, vha, 0x506d,
4214 "This board is not MCTP capable\n");
4215 return rval;
4216 }
4217
4218 if (!ha->mctp_dump) {
4219 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4220 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4221
4222 if (!ha->mctp_dump) {
4223 ql_log(ql_log_warn, vha, 0x506e,
4224 "Failed to allocate memory for mctp dump\n");
4225 return rval;
4226 }
4227 }
4228
4229 #define MCTP_DUMP_STR_ADDR 0x00000000
4230 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4231 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4232 if (rval != QLA_SUCCESS) {
4233 ql_log(ql_log_warn, vha, 0x506f,
4234 "Failed to capture mctp dump\n");
4235 } else {
4236 ql_log(ql_log_info, vha, 0x5070,
4237 "Mctp dump capture for host (%ld/%p).\n",
4238 vha->host_no, ha->mctp_dump);
4239 ha->mctp_dumped = 1;
4240 }
4241
4242 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
4243 ha->flags.nic_core_reset_hdlr_active = 1;
4244 rval = qla83xx_restart_nic_firmware(vha);
4245 if (rval)
4246 /* NIC Core reset failed. */
4247 ql_log(ql_log_warn, vha, 0x5071,
4248 "Failed to restart nic firmware\n");
4249 else
4250 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4251 "Restarted NIC firmware successfully.\n");
4252 ha->flags.nic_core_reset_hdlr_active = 0;
4253 }
4254
4255 return rval;
4256
4257 }
4258
4259 /*
4260 * qla2x00_quiesce_io
4261 * Description: This function will block the new I/Os
4262 * Its not aborting any I/Os as context
4263 * is not destroyed during quiescence
4264 * Arguments: scsi_qla_host_t
4265 * return : void
4266 */
4267 void
4268 qla2x00_quiesce_io(scsi_qla_host_t *vha)
4269 {
4270 struct qla_hw_data *ha = vha->hw;
4271 struct scsi_qla_host *vp;
4272
4273 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4274 "Quiescing I/O - ha=%p.\n", ha);
4275
4276 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4277 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4278 atomic_set(&vha->loop_state, LOOP_DOWN);
4279 qla2x00_mark_all_devices_lost(vha, 0);
4280 list_for_each_entry(vp, &ha->vp_list, list)
4281 qla2x00_mark_all_devices_lost(vp, 0);
4282 } else {
4283 if (!atomic_read(&vha->loop_down_timer))
4284 atomic_set(&vha->loop_down_timer,
4285 LOOP_DOWN_TIME);
4286 }
4287 /* Wait for pending cmds to complete */
4288 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4289 }
4290
4291 void
4292 qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4293 {
4294 struct qla_hw_data *ha = vha->hw;
4295 struct scsi_qla_host *vp;
4296 unsigned long flags;
4297 fc_port_t *fcport;
4298
4299 /* For ISP82XX, driver waits for completion of the commands.
4300 * online flag should be set.
4301 */
4302 if (!IS_QLA82XX(ha))
4303 vha->flags.online = 0;
4304 ha->flags.chip_reset_done = 0;
4305 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
4306 vha->qla_stats.total_isp_aborts++;
4307
4308 ql_log(ql_log_info, vha, 0x00af,
4309 "Performing ISP error recovery - ha=%p.\n", ha);
4310
4311 /* For ISP82XX, reset_chip is just disabling interrupts.
4312 * Driver waits for the completion of the commands.
4313 * the interrupts need to be enabled.
4314 */
4315 if (!IS_QLA82XX(ha))
4316 ha->isp_ops->reset_chip(vha);
4317
4318 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4319 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4320 atomic_set(&vha->loop_state, LOOP_DOWN);
4321 qla2x00_mark_all_devices_lost(vha, 0);
4322
4323 spin_lock_irqsave(&ha->vport_slock, flags);
4324 list_for_each_entry(vp, &ha->vp_list, list) {
4325 atomic_inc(&vp->vref_count);
4326 spin_unlock_irqrestore(&ha->vport_slock, flags);
4327
4328 qla2x00_mark_all_devices_lost(vp, 0);
4329
4330 spin_lock_irqsave(&ha->vport_slock, flags);
4331 atomic_dec(&vp->vref_count);
4332 }
4333 spin_unlock_irqrestore(&ha->vport_slock, flags);
4334 } else {
4335 if (!atomic_read(&vha->loop_down_timer))
4336 atomic_set(&vha->loop_down_timer,
4337 LOOP_DOWN_TIME);
4338 }
4339
4340 /* Clear all async request states across all VPs. */
4341 list_for_each_entry(fcport, &vha->vp_fcports, list)
4342 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4343 spin_lock_irqsave(&ha->vport_slock, flags);
4344 list_for_each_entry(vp, &ha->vp_list, list) {
4345 atomic_inc(&vp->vref_count);
4346 spin_unlock_irqrestore(&ha->vport_slock, flags);
4347
4348 list_for_each_entry(fcport, &vp->vp_fcports, list)
4349 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4350
4351 spin_lock_irqsave(&ha->vport_slock, flags);
4352 atomic_dec(&vp->vref_count);
4353 }
4354 spin_unlock_irqrestore(&ha->vport_slock, flags);
4355
4356 if (!ha->flags.eeh_busy) {
4357 /* Make sure for ISP 82XX IO DMA is complete */
4358 if (IS_QLA82XX(ha)) {
4359 qla82xx_chip_reset_cleanup(vha);
4360 ql_log(ql_log_info, vha, 0x00b4,
4361 "Done chip reset cleanup.\n");
4362
4363 /* Done waiting for pending commands.
4364 * Reset the online flag.
4365 */
4366 vha->flags.online = 0;
4367 }
4368
4369 /* Requeue all commands in outstanding command list. */
4370 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4371 }
4372 }
4373
4374 /*
4375 * qla2x00_abort_isp
4376 * Resets ISP and aborts all outstanding commands.
4377 *
4378 * Input:
4379 * ha = adapter block pointer.
4380 *
4381 * Returns:
4382 * 0 = success
4383 */
4384 int
4385 qla2x00_abort_isp(scsi_qla_host_t *vha)
4386 {
4387 int rval;
4388 uint8_t status = 0;
4389 struct qla_hw_data *ha = vha->hw;
4390 struct scsi_qla_host *vp;
4391 struct req_que *req = ha->req_q_map[0];
4392 unsigned long flags;
4393
4394 if (vha->flags.online) {
4395 qla2x00_abort_isp_cleanup(vha);
4396
4397 if (IS_QLA8031(ha)) {
4398 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4399 "Clearing fcoe driver presence.\n");
4400 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4401 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4402 "Error while clearing DRV-Presence.\n");
4403 }
4404
4405 if (unlikely(pci_channel_offline(ha->pdev) &&
4406 ha->flags.pci_channel_io_perm_failure)) {
4407 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4408 status = 0;
4409 return status;
4410 }
4411
4412 ha->isp_ops->get_flash_version(vha, req->ring);
4413
4414 ha->isp_ops->nvram_config(vha);
4415
4416 if (!qla2x00_restart_isp(vha)) {
4417 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
4418
4419 if (!atomic_read(&vha->loop_down_timer)) {
4420 /*
4421 * Issue marker command only when we are going
4422 * to start the I/O .
4423 */
4424 vha->marker_needed = 1;
4425 }
4426
4427 vha->flags.online = 1;
4428
4429 ha->isp_ops->enable_intrs(ha);
4430
4431 ha->isp_abort_cnt = 0;
4432 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4433
4434 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4435 qla2x00_get_fw_version(vha);
4436 if (ha->fce) {
4437 ha->flags.fce_enabled = 1;
4438 memset(ha->fce, 0,
4439 fce_calc_size(ha->fce_bufs));
4440 rval = qla2x00_enable_fce_trace(vha,
4441 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4442 &ha->fce_bufs);
4443 if (rval) {
4444 ql_log(ql_log_warn, vha, 0x8033,
4445 "Unable to reinitialize FCE "
4446 "(%d).\n", rval);
4447 ha->flags.fce_enabled = 0;
4448 }
4449 }
4450
4451 if (ha->eft) {
4452 memset(ha->eft, 0, EFT_SIZE);
4453 rval = qla2x00_enable_eft_trace(vha,
4454 ha->eft_dma, EFT_NUM_BUFFERS);
4455 if (rval) {
4456 ql_log(ql_log_warn, vha, 0x8034,
4457 "Unable to reinitialize EFT "
4458 "(%d).\n", rval);
4459 }
4460 }
4461 } else { /* failed the ISP abort */
4462 vha->flags.online = 1;
4463 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
4464 if (ha->isp_abort_cnt == 0) {
4465 ql_log(ql_log_fatal, vha, 0x8035,
4466 "ISP error recover failed - "
4467 "board disabled.\n");
4468 /*
4469 * The next call disables the board
4470 * completely.
4471 */
4472 ha->isp_ops->reset_adapter(vha);
4473 vha->flags.online = 0;
4474 clear_bit(ISP_ABORT_RETRY,
4475 &vha->dpc_flags);
4476 status = 0;
4477 } else { /* schedule another ISP abort */
4478 ha->isp_abort_cnt--;
4479 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4480 "ISP abort - retry remaining %d.\n",
4481 ha->isp_abort_cnt);
4482 status = 1;
4483 }
4484 } else {
4485 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
4486 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4487 "ISP error recovery - retrying (%d) "
4488 "more times.\n", ha->isp_abort_cnt);
4489 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4490 status = 1;
4491 }
4492 }
4493
4494 }
4495
4496 if (!status) {
4497 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
4498
4499 spin_lock_irqsave(&ha->vport_slock, flags);
4500 list_for_each_entry(vp, &ha->vp_list, list) {
4501 if (vp->vp_idx) {
4502 atomic_inc(&vp->vref_count);
4503 spin_unlock_irqrestore(&ha->vport_slock, flags);
4504
4505 qla2x00_vp_abort_isp(vp);
4506
4507 spin_lock_irqsave(&ha->vport_slock, flags);
4508 atomic_dec(&vp->vref_count);
4509 }
4510 }
4511 spin_unlock_irqrestore(&ha->vport_slock, flags);
4512
4513 if (IS_QLA8031(ha)) {
4514 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4515 "Setting back fcoe driver presence.\n");
4516 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4517 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4518 "Error while setting DRV-Presence.\n");
4519 }
4520 } else {
4521 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4522 __func__);
4523 }
4524
4525 return(status);
4526 }
4527
4528 /*
4529 * qla2x00_restart_isp
4530 * restarts the ISP after a reset
4531 *
4532 * Input:
4533 * ha = adapter block pointer.
4534 *
4535 * Returns:
4536 * 0 = success
4537 */
4538 static int
4539 qla2x00_restart_isp(scsi_qla_host_t *vha)
4540 {
4541 int status = 0;
4542 uint32_t wait_time;
4543 struct qla_hw_data *ha = vha->hw;
4544 struct req_que *req = ha->req_q_map[0];
4545 struct rsp_que *rsp = ha->rsp_q_map[0];
4546 unsigned long flags;
4547
4548 /* If firmware needs to be loaded */
4549 if (qla2x00_isp_firmware(vha)) {
4550 vha->flags.online = 0;
4551 status = ha->isp_ops->chip_diag(vha);
4552 if (!status)
4553 status = qla2x00_setup_chip(vha);
4554 }
4555
4556 if (!status && !(status = qla2x00_init_rings(vha))) {
4557 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
4558 ha->flags.chip_reset_done = 1;
4559 /* Initialize the queues in use */
4560 qla25xx_init_queues(ha);
4561
4562 status = qla2x00_fw_ready(vha);
4563 if (!status) {
4564 ql_dbg(ql_dbg_taskm, vha, 0x8031,
4565 "Start configure loop status = %d.\n", status);
4566
4567 /* Issue a marker after FW becomes ready. */
4568 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
4569
4570 vha->flags.online = 1;
4571
4572 /*
4573 * Process any ATIO queue entries that came in
4574 * while we weren't online.
4575 */
4576 spin_lock_irqsave(&ha->hardware_lock, flags);
4577 if (qla_tgt_mode_enabled(vha))
4578 qlt_24xx_process_atio_queue(vha);
4579 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4580
4581 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4582 wait_time = 256;
4583 do {
4584 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4585 qla2x00_configure_loop(vha);
4586 wait_time--;
4587 } while (!atomic_read(&vha->loop_down_timer) &&
4588 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4589 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4590 &vha->dpc_flags)));
4591 }
4592
4593 /* if no cable then assume it's good */
4594 if ((vha->device_flags & DFLG_NO_CABLE))
4595 status = 0;
4596
4597 ql_dbg(ql_dbg_taskm, vha, 0x8032,
4598 "Configure loop done, status = 0x%x.\n", status);
4599 }
4600 return (status);
4601 }
4602
4603 static int
4604 qla25xx_init_queues(struct qla_hw_data *ha)
4605 {
4606 struct rsp_que *rsp = NULL;
4607 struct req_que *req = NULL;
4608 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4609 int ret = -1;
4610 int i;
4611
4612 for (i = 1; i < ha->max_rsp_queues; i++) {
4613 rsp = ha->rsp_q_map[i];
4614 if (rsp) {
4615 rsp->options &= ~BIT_0;
4616 ret = qla25xx_init_rsp_que(base_vha, rsp);
4617 if (ret != QLA_SUCCESS)
4618 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4619 "%s Rsp que: %d init failed.\n",
4620 __func__, rsp->id);
4621 else
4622 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4623 "%s Rsp que: %d inited.\n",
4624 __func__, rsp->id);
4625 }
4626 }
4627 for (i = 1; i < ha->max_req_queues; i++) {
4628 req = ha->req_q_map[i];
4629 if (req) {
4630 /* Clear outstanding commands array. */
4631 req->options &= ~BIT_0;
4632 ret = qla25xx_init_req_que(base_vha, req);
4633 if (ret != QLA_SUCCESS)
4634 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4635 "%s Req que: %d init failed.\n",
4636 __func__, req->id);
4637 else
4638 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4639 "%s Req que: %d inited.\n",
4640 __func__, req->id);
4641 }
4642 }
4643 return ret;
4644 }
4645
4646 /*
4647 * qla2x00_reset_adapter
4648 * Reset adapter.
4649 *
4650 * Input:
4651 * ha = adapter block pointer.
4652 */
4653 void
4654 qla2x00_reset_adapter(scsi_qla_host_t *vha)
4655 {
4656 unsigned long flags = 0;
4657 struct qla_hw_data *ha = vha->hw;
4658 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4659
4660 vha->flags.online = 0;
4661 ha->isp_ops->disable_intrs(ha);
4662
4663 spin_lock_irqsave(&ha->hardware_lock, flags);
4664 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4665 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4666 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4667 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4668 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4669 }
4670
4671 void
4672 qla24xx_reset_adapter(scsi_qla_host_t *vha)
4673 {
4674 unsigned long flags = 0;
4675 struct qla_hw_data *ha = vha->hw;
4676 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4677
4678 if (IS_QLA82XX(ha))
4679 return;
4680
4681 vha->flags.online = 0;
4682 ha->isp_ops->disable_intrs(ha);
4683
4684 spin_lock_irqsave(&ha->hardware_lock, flags);
4685 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4686 RD_REG_DWORD(&reg->hccr);
4687 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4688 RD_REG_DWORD(&reg->hccr);
4689 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4690
4691 if (IS_NOPOLLING_TYPE(ha))
4692 ha->isp_ops->enable_intrs(ha);
4693 }
4694
4695 /* On sparc systems, obtain port and node WWN from firmware
4696 * properties.
4697 */
4698 static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4699 struct nvram_24xx *nv)
4700 {
4701 #ifdef CONFIG_SPARC
4702 struct qla_hw_data *ha = vha->hw;
4703 struct pci_dev *pdev = ha->pdev;
4704 struct device_node *dp = pci_device_to_OF_node(pdev);
4705 const u8 *val;
4706 int len;
4707
4708 val = of_get_property(dp, "port-wwn", &len);
4709 if (val && len >= WWN_SIZE)
4710 memcpy(nv->port_name, val, WWN_SIZE);
4711
4712 val = of_get_property(dp, "node-wwn", &len);
4713 if (val && len >= WWN_SIZE)
4714 memcpy(nv->node_name, val, WWN_SIZE);
4715 #endif
4716 }
4717
4718 int
4719 qla24xx_nvram_config(scsi_qla_host_t *vha)
4720 {
4721 int rval;
4722 struct init_cb_24xx *icb;
4723 struct nvram_24xx *nv;
4724 uint32_t *dptr;
4725 uint8_t *dptr1, *dptr2;
4726 uint32_t chksum;
4727 uint16_t cnt;
4728 struct qla_hw_data *ha = vha->hw;
4729
4730 rval = QLA_SUCCESS;
4731 icb = (struct init_cb_24xx *)ha->init_cb;
4732 nv = ha->nvram;
4733
4734 /* Determine NVRAM starting address. */
4735 if (ha->flags.port0) {
4736 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4737 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4738 } else {
4739 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
4740 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4741 }
4742 ha->nvram_size = sizeof(struct nvram_24xx);
4743 ha->vpd_size = FA_NVRAM_VPD_SIZE;
4744 if (IS_QLA82XX(ha))
4745 ha->vpd_size = FA_VPD_SIZE_82XX;
4746
4747 /* Get VPD data into cache */
4748 ha->vpd = ha->nvram + VPD_OFFSET;
4749 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
4750 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4751
4752 /* Get NVRAM data into cache and calculate checksum. */
4753 dptr = (uint32_t *)nv;
4754 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
4755 ha->nvram_size);
4756 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4757 chksum += le32_to_cpu(*dptr++);
4758
4759 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4760 "Contents of NVRAM\n");
4761 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4762 (uint8_t *)nv, ha->nvram_size);
4763
4764 /* Bad NVRAM data, set defaults parameters. */
4765 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4766 || nv->id[3] != ' ' ||
4767 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4768 /* Reset NVRAM data. */
4769 ql_log(ql_log_warn, vha, 0x006b,
4770 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
4771 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4772 ql_log(ql_log_warn, vha, 0x006c,
4773 "Falling back to functioning (yet invalid -- WWPN) "
4774 "defaults.\n");
4775
4776 /*
4777 * Set default initialization control block.
4778 */
4779 memset(nv, 0, ha->nvram_size);
4780 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4781 nv->version = __constant_cpu_to_le16(ICB_VERSION);
4782 nv->frame_payload_size = __constant_cpu_to_le16(2048);
4783 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4784 nv->exchange_count = __constant_cpu_to_le16(0);
4785 nv->hard_address = __constant_cpu_to_le16(124);
4786 nv->port_name[0] = 0x21;
4787 nv->port_name[1] = 0x00 + ha->port_no;
4788 nv->port_name[2] = 0x00;
4789 nv->port_name[3] = 0xe0;
4790 nv->port_name[4] = 0x8b;
4791 nv->port_name[5] = 0x1c;
4792 nv->port_name[6] = 0x55;
4793 nv->port_name[7] = 0x86;
4794 nv->node_name[0] = 0x20;
4795 nv->node_name[1] = 0x00;
4796 nv->node_name[2] = 0x00;
4797 nv->node_name[3] = 0xe0;
4798 nv->node_name[4] = 0x8b;
4799 nv->node_name[5] = 0x1c;
4800 nv->node_name[6] = 0x55;
4801 nv->node_name[7] = 0x86;
4802 qla24xx_nvram_wwn_from_ofw(vha, nv);
4803 nv->login_retry_count = __constant_cpu_to_le16(8);
4804 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4805 nv->login_timeout = __constant_cpu_to_le16(0);
4806 nv->firmware_options_1 =
4807 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4808 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4809 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4810 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4811 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4812 nv->efi_parameters = __constant_cpu_to_le32(0);
4813 nv->reset_delay = 5;
4814 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4815 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4816 nv->link_down_timeout = __constant_cpu_to_le16(30);
4817
4818 rval = 1;
4819 }
4820
4821 if (!qla_ini_mode_enabled(vha)) {
4822 /* Don't enable full login after initial LIP */
4823 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
4824 /* Don't enable LIP full login for initiator */
4825 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
4826 }
4827
4828 qlt_24xx_config_nvram_stage1(vha, nv);
4829
4830 /* Reset Initialization control block */
4831 memset(icb, 0, ha->init_cb_size);
4832
4833 /* Copy 1st segment. */
4834 dptr1 = (uint8_t *)icb;
4835 dptr2 = (uint8_t *)&nv->version;
4836 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
4837 while (cnt--)
4838 *dptr1++ = *dptr2++;
4839
4840 icb->login_retry_count = nv->login_retry_count;
4841 icb->link_down_on_nos = nv->link_down_on_nos;
4842
4843 /* Copy 2nd segment. */
4844 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
4845 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
4846 cnt = (uint8_t *)&icb->reserved_3 -
4847 (uint8_t *)&icb->interrupt_delay_timer;
4848 while (cnt--)
4849 *dptr1++ = *dptr2++;
4850
4851 /*
4852 * Setup driver NVRAM options.
4853 */
4854 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
4855 "QLA2462");
4856
4857 qlt_24xx_config_nvram_stage2(vha, icb);
4858
4859 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
4860 /* Use alternate WWN? */
4861 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4862 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4863 }
4864
4865 /* Prepare nodename */
4866 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
4867 /*
4868 * Firmware will apply the following mask if the nodename was
4869 * not provided.
4870 */
4871 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4872 icb->node_name[0] &= 0xF0;
4873 }
4874
4875 /* Set host adapter parameters. */
4876 ha->flags.disable_risc_code_load = 0;
4877 ha->flags.enable_lip_reset = 0;
4878 ha->flags.enable_lip_full_login =
4879 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
4880 ha->flags.enable_target_reset =
4881 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
4882 ha->flags.enable_led_scheme = 0;
4883 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
4884
4885 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
4886 (BIT_6 | BIT_5 | BIT_4)) >> 4;
4887
4888 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
4889 sizeof(ha->fw_seriallink_options24));
4890
4891 /* save HBA serial number */
4892 ha->serial0 = icb->port_name[5];
4893 ha->serial1 = icb->port_name[6];
4894 ha->serial2 = icb->port_name[7];
4895 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4896 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
4897
4898 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4899
4900 ha->retry_count = le16_to_cpu(nv->login_retry_count);
4901
4902 /* Set minimum login_timeout to 4 seconds. */
4903 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
4904 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
4905 if (le16_to_cpu(nv->login_timeout) < 4)
4906 nv->login_timeout = __constant_cpu_to_le16(4);
4907 ha->login_timeout = le16_to_cpu(nv->login_timeout);
4908 icb->login_timeout = nv->login_timeout;
4909
4910 /* Set minimum RATOV to 100 tenths of a second. */
4911 ha->r_a_tov = 100;
4912
4913 ha->loop_reset_delay = nv->reset_delay;
4914
4915 /* Link Down Timeout = 0:
4916 *
4917 * When Port Down timer expires we will start returning
4918 * I/O's to OS with "DID_NO_CONNECT".
4919 *
4920 * Link Down Timeout != 0:
4921 *
4922 * The driver waits for the link to come up after link down
4923 * before returning I/Os to OS with "DID_NO_CONNECT".
4924 */
4925 if (le16_to_cpu(nv->link_down_timeout) == 0) {
4926 ha->loop_down_abort_time =
4927 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
4928 } else {
4929 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
4930 ha->loop_down_abort_time =
4931 (LOOP_DOWN_TIME - ha->link_down_timeout);
4932 }
4933
4934 /* Need enough time to try and get the port back. */
4935 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
4936 if (qlport_down_retry)
4937 ha->port_down_retry_count = qlport_down_retry;
4938
4939 /* Set login_retry_count */
4940 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
4941 if (ha->port_down_retry_count ==
4942 le16_to_cpu(nv->port_down_retry_count) &&
4943 ha->port_down_retry_count > 3)
4944 ha->login_retry_count = ha->port_down_retry_count;
4945 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4946 ha->login_retry_count = ha->port_down_retry_count;
4947 if (ql2xloginretrycount)
4948 ha->login_retry_count = ql2xloginretrycount;
4949
4950 /* Enable ZIO. */
4951 if (!vha->flags.init_done) {
4952 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
4953 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4954 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
4955 le16_to_cpu(icb->interrupt_delay_timer): 2;
4956 }
4957 icb->firmware_options_2 &= __constant_cpu_to_le32(
4958 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
4959 vha->flags.process_response_queue = 0;
4960 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4961 ha->zio_mode = QLA_ZIO_MODE_6;
4962
4963 ql_log(ql_log_info, vha, 0x006f,
4964 "ZIO mode %d enabled; timer delay (%d us).\n",
4965 ha->zio_mode, ha->zio_timer * 100);
4966
4967 icb->firmware_options_2 |= cpu_to_le32(
4968 (uint32_t)ha->zio_mode);
4969 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
4970 vha->flags.process_response_queue = 1;
4971 }
4972
4973 if (rval) {
4974 ql_log(ql_log_warn, vha, 0x0070,
4975 "NVRAM configuration failed.\n");
4976 }
4977 return (rval);
4978 }
4979
4980 static int
4981 qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
4982 uint32_t faddr)
4983 {
4984 int rval = QLA_SUCCESS;
4985 int segments, fragment;
4986 uint32_t *dcode, dlen;
4987 uint32_t risc_addr;
4988 uint32_t risc_size;
4989 uint32_t i;
4990 struct qla_hw_data *ha = vha->hw;
4991 struct req_que *req = ha->req_q_map[0];
4992
4993 ql_dbg(ql_dbg_init, vha, 0x008b,
4994 "FW: Loading firmware from flash (%x).\n", faddr);
4995
4996 rval = QLA_SUCCESS;
4997
4998 segments = FA_RISC_CODE_SEGMENTS;
4999 dcode = (uint32_t *)req->ring;
5000 *srisc_addr = 0;
5001
5002 /* Validate firmware image by checking version. */
5003 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
5004 for (i = 0; i < 4; i++)
5005 dcode[i] = be32_to_cpu(dcode[i]);
5006 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5007 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5008 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5009 dcode[3] == 0)) {
5010 ql_log(ql_log_fatal, vha, 0x008c,
5011 "Unable to verify the integrity of flash firmware "
5012 "image.\n");
5013 ql_log(ql_log_fatal, vha, 0x008d,
5014 "Firmware data: %08x %08x %08x %08x.\n",
5015 dcode[0], dcode[1], dcode[2], dcode[3]);
5016
5017 return QLA_FUNCTION_FAILED;
5018 }
5019
5020 while (segments && rval == QLA_SUCCESS) {
5021 /* Read segment's load information. */
5022 qla24xx_read_flash_data(vha, dcode, faddr, 4);
5023
5024 risc_addr = be32_to_cpu(dcode[2]);
5025 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5026 risc_size = be32_to_cpu(dcode[3]);
5027
5028 fragment = 0;
5029 while (risc_size > 0 && rval == QLA_SUCCESS) {
5030 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5031 if (dlen > risc_size)
5032 dlen = risc_size;
5033
5034 ql_dbg(ql_dbg_init, vha, 0x008e,
5035 "Loading risc segment@ risc addr %x "
5036 "number of dwords 0x%x offset 0x%x.\n",
5037 risc_addr, dlen, faddr);
5038
5039 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
5040 for (i = 0; i < dlen; i++)
5041 dcode[i] = swab32(dcode[i]);
5042
5043 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5044 dlen);
5045 if (rval) {
5046 ql_log(ql_log_fatal, vha, 0x008f,
5047 "Failed to load segment %d of firmware.\n",
5048 fragment);
5049 break;
5050 }
5051
5052 faddr += dlen;
5053 risc_addr += dlen;
5054 risc_size -= dlen;
5055 fragment++;
5056 }
5057
5058 /* Next segment. */
5059 segments--;
5060 }
5061
5062 return rval;
5063 }
5064
5065 #define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
5066
5067 int
5068 qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5069 {
5070 int rval;
5071 int i, fragment;
5072 uint16_t *wcode, *fwcode;
5073 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5074 struct fw_blob *blob;
5075 struct qla_hw_data *ha = vha->hw;
5076 struct req_que *req = ha->req_q_map[0];
5077
5078 /* Load firmware blob. */
5079 blob = qla2x00_request_firmware(vha);
5080 if (!blob) {
5081 ql_log(ql_log_info, vha, 0x0083,
5082 "Fimware image unavailable.\n");
5083 ql_log(ql_log_info, vha, 0x0084,
5084 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5085 return QLA_FUNCTION_FAILED;
5086 }
5087
5088 rval = QLA_SUCCESS;
5089
5090 wcode = (uint16_t *)req->ring;
5091 *srisc_addr = 0;
5092 fwcode = (uint16_t *)blob->fw->data;
5093 fwclen = 0;
5094
5095 /* Validate firmware image by checking version. */
5096 if (blob->fw->size < 8 * sizeof(uint16_t)) {
5097 ql_log(ql_log_fatal, vha, 0x0085,
5098 "Unable to verify integrity of firmware image (%Zd).\n",
5099 blob->fw->size);
5100 goto fail_fw_integrity;
5101 }
5102 for (i = 0; i < 4; i++)
5103 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5104 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5105 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5106 wcode[2] == 0 && wcode[3] == 0)) {
5107 ql_log(ql_log_fatal, vha, 0x0086,
5108 "Unable to verify integrity of firmware image.\n");
5109 ql_log(ql_log_fatal, vha, 0x0087,
5110 "Firmware data: %04x %04x %04x %04x.\n",
5111 wcode[0], wcode[1], wcode[2], wcode[3]);
5112 goto fail_fw_integrity;
5113 }
5114
5115 seg = blob->segs;
5116 while (*seg && rval == QLA_SUCCESS) {
5117 risc_addr = *seg;
5118 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5119 risc_size = be16_to_cpu(fwcode[3]);
5120
5121 /* Validate firmware image size. */
5122 fwclen += risc_size * sizeof(uint16_t);
5123 if (blob->fw->size < fwclen) {
5124 ql_log(ql_log_fatal, vha, 0x0088,
5125 "Unable to verify integrity of firmware image "
5126 "(%Zd).\n", blob->fw->size);
5127 goto fail_fw_integrity;
5128 }
5129
5130 fragment = 0;
5131 while (risc_size > 0 && rval == QLA_SUCCESS) {
5132 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5133 if (wlen > risc_size)
5134 wlen = risc_size;
5135 ql_dbg(ql_dbg_init, vha, 0x0089,
5136 "Loading risc segment@ risc addr %x number of "
5137 "words 0x%x.\n", risc_addr, wlen);
5138
5139 for (i = 0; i < wlen; i++)
5140 wcode[i] = swab16(fwcode[i]);
5141
5142 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5143 wlen);
5144 if (rval) {
5145 ql_log(ql_log_fatal, vha, 0x008a,
5146 "Failed to load segment %d of firmware.\n",
5147 fragment);
5148 break;
5149 }
5150
5151 fwcode += wlen;
5152 risc_addr += wlen;
5153 risc_size -= wlen;
5154 fragment++;
5155 }
5156
5157 /* Next segment. */
5158 seg++;
5159 }
5160 return rval;
5161
5162 fail_fw_integrity:
5163 return QLA_FUNCTION_FAILED;
5164 }
5165
5166 static int
5167 qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5168 {
5169 int rval;
5170 int segments, fragment;
5171 uint32_t *dcode, dlen;
5172 uint32_t risc_addr;
5173 uint32_t risc_size;
5174 uint32_t i;
5175 struct fw_blob *blob;
5176 uint32_t *fwcode, fwclen;
5177 struct qla_hw_data *ha = vha->hw;
5178 struct req_que *req = ha->req_q_map[0];
5179
5180 /* Load firmware blob. */
5181 blob = qla2x00_request_firmware(vha);
5182 if (!blob) {
5183 ql_log(ql_log_warn, vha, 0x0090,
5184 "Fimware image unavailable.\n");
5185 ql_log(ql_log_warn, vha, 0x0091,
5186 "Firmware images can be retrieved from: "
5187 QLA_FW_URL ".\n");
5188
5189 return QLA_FUNCTION_FAILED;
5190 }
5191
5192 ql_dbg(ql_dbg_init, vha, 0x0092,
5193 "FW: Loading via request-firmware.\n");
5194
5195 rval = QLA_SUCCESS;
5196
5197 segments = FA_RISC_CODE_SEGMENTS;
5198 dcode = (uint32_t *)req->ring;
5199 *srisc_addr = 0;
5200 fwcode = (uint32_t *)blob->fw->data;
5201 fwclen = 0;
5202
5203 /* Validate firmware image by checking version. */
5204 if (blob->fw->size < 8 * sizeof(uint32_t)) {
5205 ql_log(ql_log_fatal, vha, 0x0093,
5206 "Unable to verify integrity of firmware image (%Zd).\n",
5207 blob->fw->size);
5208 goto fail_fw_integrity;
5209 }
5210 for (i = 0; i < 4; i++)
5211 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5212 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5213 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5214 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5215 dcode[3] == 0)) {
5216 ql_log(ql_log_fatal, vha, 0x0094,
5217 "Unable to verify integrity of firmware image (%Zd).\n",
5218 blob->fw->size);
5219 ql_log(ql_log_fatal, vha, 0x0095,
5220 "Firmware data: %08x %08x %08x %08x.\n",
5221 dcode[0], dcode[1], dcode[2], dcode[3]);
5222 goto fail_fw_integrity;
5223 }
5224
5225 while (segments && rval == QLA_SUCCESS) {
5226 risc_addr = be32_to_cpu(fwcode[2]);
5227 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5228 risc_size = be32_to_cpu(fwcode[3]);
5229
5230 /* Validate firmware image size. */
5231 fwclen += risc_size * sizeof(uint32_t);
5232 if (blob->fw->size < fwclen) {
5233 ql_log(ql_log_fatal, vha, 0x0096,
5234 "Unable to verify integrity of firmware image "
5235 "(%Zd).\n", blob->fw->size);
5236
5237 goto fail_fw_integrity;
5238 }
5239
5240 fragment = 0;
5241 while (risc_size > 0 && rval == QLA_SUCCESS) {
5242 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5243 if (dlen > risc_size)
5244 dlen = risc_size;
5245
5246 ql_dbg(ql_dbg_init, vha, 0x0097,
5247 "Loading risc segment@ risc addr %x "
5248 "number of dwords 0x%x.\n", risc_addr, dlen);
5249
5250 for (i = 0; i < dlen; i++)
5251 dcode[i] = swab32(fwcode[i]);
5252
5253 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5254 dlen);
5255 if (rval) {
5256 ql_log(ql_log_fatal, vha, 0x0098,
5257 "Failed to load segment %d of firmware.\n",
5258 fragment);
5259 break;
5260 }
5261
5262 fwcode += dlen;
5263 risc_addr += dlen;
5264 risc_size -= dlen;
5265 fragment++;
5266 }
5267
5268 /* Next segment. */
5269 segments--;
5270 }
5271 return rval;
5272
5273 fail_fw_integrity:
5274 return QLA_FUNCTION_FAILED;
5275 }
5276
5277 int
5278 qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5279 {
5280 int rval;
5281
5282 if (ql2xfwloadbin == 1)
5283 return qla81xx_load_risc(vha, srisc_addr);
5284
5285 /*
5286 * FW Load priority:
5287 * 1) Firmware via request-firmware interface (.bin file).
5288 * 2) Firmware residing in flash.
5289 */
5290 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5291 if (rval == QLA_SUCCESS)
5292 return rval;
5293
5294 return qla24xx_load_risc_flash(vha, srisc_addr,
5295 vha->hw->flt_region_fw);
5296 }
5297
5298 int
5299 qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5300 {
5301 int rval;
5302 struct qla_hw_data *ha = vha->hw;
5303
5304 if (ql2xfwloadbin == 2)
5305 goto try_blob_fw;
5306
5307 /*
5308 * FW Load priority:
5309 * 1) Firmware residing in flash.
5310 * 2) Firmware via request-firmware interface (.bin file).
5311 * 3) Golden-Firmware residing in flash -- limited operation.
5312 */
5313 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
5314 if (rval == QLA_SUCCESS)
5315 return rval;
5316
5317 try_blob_fw:
5318 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5319 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5320 return rval;
5321
5322 ql_log(ql_log_info, vha, 0x0099,
5323 "Attempting to fallback to golden firmware.\n");
5324 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5325 if (rval != QLA_SUCCESS)
5326 return rval;
5327
5328 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
5329 ha->flags.running_gold_fw = 1;
5330 return rval;
5331 }
5332
5333 void
5334 qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
5335 {
5336 int ret, retries;
5337 struct qla_hw_data *ha = vha->hw;
5338
5339 if (ha->flags.pci_channel_io_perm_failure)
5340 return;
5341 if (!IS_FWI2_CAPABLE(ha))
5342 return;
5343 if (!ha->fw_major_version)
5344 return;
5345
5346 ret = qla2x00_stop_firmware(vha);
5347 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
5348 ret != QLA_INVALID_COMMAND && retries ; retries--) {
5349 ha->isp_ops->reset_chip(vha);
5350 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
5351 continue;
5352 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
5353 continue;
5354 ql_log(ql_log_info, vha, 0x8015,
5355 "Attempting retry of stop-firmware command.\n");
5356 ret = qla2x00_stop_firmware(vha);
5357 }
5358 }
5359
5360 int
5361 qla24xx_configure_vhba(scsi_qla_host_t *vha)
5362 {
5363 int rval = QLA_SUCCESS;
5364 int rval2;
5365 uint16_t mb[MAILBOX_REGISTER_COUNT];
5366 struct qla_hw_data *ha = vha->hw;
5367 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
5368 struct req_que *req;
5369 struct rsp_que *rsp;
5370
5371 if (!vha->vp_idx)
5372 return -EINVAL;
5373
5374 rval = qla2x00_fw_ready(base_vha);
5375 if (ha->flags.cpu_affinity_enabled)
5376 req = ha->req_q_map[0];
5377 else
5378 req = vha->req;
5379 rsp = req->rsp;
5380
5381 if (rval == QLA_SUCCESS) {
5382 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5383 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
5384 }
5385
5386 vha->flags.management_server_logged_in = 0;
5387
5388 /* Login to SNS first */
5389 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5390 BIT_1);
5391 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5392 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5393 ql_dbg(ql_dbg_init, vha, 0x0120,
5394 "Failed SNS login: loop_id=%x, rval2=%d\n",
5395 NPH_SNS, rval2);
5396 else
5397 ql_dbg(ql_dbg_init, vha, 0x0103,
5398 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5399 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5400 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
5401 return (QLA_FUNCTION_FAILED);
5402 }
5403
5404 atomic_set(&vha->loop_down_timer, 0);
5405 atomic_set(&vha->loop_state, LOOP_UP);
5406 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5407 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5408 rval = qla2x00_loop_resync(base_vha);
5409
5410 return rval;
5411 }
5412
5413 /* 84XX Support **************************************************************/
5414
5415 static LIST_HEAD(qla_cs84xx_list);
5416 static DEFINE_MUTEX(qla_cs84xx_mutex);
5417
5418 static struct qla_chip_state_84xx *
5419 qla84xx_get_chip(struct scsi_qla_host *vha)
5420 {
5421 struct qla_chip_state_84xx *cs84xx;
5422 struct qla_hw_data *ha = vha->hw;
5423
5424 mutex_lock(&qla_cs84xx_mutex);
5425
5426 /* Find any shared 84xx chip. */
5427 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5428 if (cs84xx->bus == ha->pdev->bus) {
5429 kref_get(&cs84xx->kref);
5430 goto done;
5431 }
5432 }
5433
5434 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5435 if (!cs84xx)
5436 goto done;
5437
5438 kref_init(&cs84xx->kref);
5439 spin_lock_init(&cs84xx->access_lock);
5440 mutex_init(&cs84xx->fw_update_mutex);
5441 cs84xx->bus = ha->pdev->bus;
5442
5443 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5444 done:
5445 mutex_unlock(&qla_cs84xx_mutex);
5446 return cs84xx;
5447 }
5448
5449 static void
5450 __qla84xx_chip_release(struct kref *kref)
5451 {
5452 struct qla_chip_state_84xx *cs84xx =
5453 container_of(kref, struct qla_chip_state_84xx, kref);
5454
5455 mutex_lock(&qla_cs84xx_mutex);
5456 list_del(&cs84xx->list);
5457 mutex_unlock(&qla_cs84xx_mutex);
5458 kfree(cs84xx);
5459 }
5460
5461 void
5462 qla84xx_put_chip(struct scsi_qla_host *vha)
5463 {
5464 struct qla_hw_data *ha = vha->hw;
5465 if (ha->cs84xx)
5466 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5467 }
5468
5469 static int
5470 qla84xx_init_chip(scsi_qla_host_t *vha)
5471 {
5472 int rval;
5473 uint16_t status[2];
5474 struct qla_hw_data *ha = vha->hw;
5475
5476 mutex_lock(&ha->cs84xx->fw_update_mutex);
5477
5478 rval = qla84xx_verify_chip(vha, status);
5479
5480 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5481
5482 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5483 QLA_SUCCESS;
5484 }
5485
5486 /* 81XX Support **************************************************************/
5487
5488 int
5489 qla81xx_nvram_config(scsi_qla_host_t *vha)
5490 {
5491 int rval;
5492 struct init_cb_81xx *icb;
5493 struct nvram_81xx *nv;
5494 uint32_t *dptr;
5495 uint8_t *dptr1, *dptr2;
5496 uint32_t chksum;
5497 uint16_t cnt;
5498 struct qla_hw_data *ha = vha->hw;
5499
5500 rval = QLA_SUCCESS;
5501 icb = (struct init_cb_81xx *)ha->init_cb;
5502 nv = ha->nvram;
5503
5504 /* Determine NVRAM starting address. */
5505 ha->nvram_size = sizeof(struct nvram_81xx);
5506 ha->vpd_size = FA_NVRAM_VPD_SIZE;
5507
5508 /* Get VPD data into cache */
5509 ha->vpd = ha->nvram + VPD_OFFSET;
5510 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5511 ha->vpd_size);
5512
5513 /* Get NVRAM data into cache and calculate checksum. */
5514 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
5515 ha->nvram_size);
5516 dptr = (uint32_t *)nv;
5517 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5518 chksum += le32_to_cpu(*dptr++);
5519
5520 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5521 "Contents of NVRAM:\n");
5522 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5523 (uint8_t *)nv, ha->nvram_size);
5524
5525 /* Bad NVRAM data, set defaults parameters. */
5526 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5527 || nv->id[3] != ' ' ||
5528 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5529 /* Reset NVRAM data. */
5530 ql_log(ql_log_info, vha, 0x0073,
5531 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
5532 "version=0x%x.\n", chksum, nv->id[0],
5533 le16_to_cpu(nv->nvram_version));
5534 ql_log(ql_log_info, vha, 0x0074,
5535 "Falling back to functioning (yet invalid -- WWPN) "
5536 "defaults.\n");
5537
5538 /*
5539 * Set default initialization control block.
5540 */
5541 memset(nv, 0, ha->nvram_size);
5542 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5543 nv->version = __constant_cpu_to_le16(ICB_VERSION);
5544 nv->frame_payload_size = __constant_cpu_to_le16(2048);
5545 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5546 nv->exchange_count = __constant_cpu_to_le16(0);
5547 nv->port_name[0] = 0x21;
5548 nv->port_name[1] = 0x00 + ha->port_no;
5549 nv->port_name[2] = 0x00;
5550 nv->port_name[3] = 0xe0;
5551 nv->port_name[4] = 0x8b;
5552 nv->port_name[5] = 0x1c;
5553 nv->port_name[6] = 0x55;
5554 nv->port_name[7] = 0x86;
5555 nv->node_name[0] = 0x20;
5556 nv->node_name[1] = 0x00;
5557 nv->node_name[2] = 0x00;
5558 nv->node_name[3] = 0xe0;
5559 nv->node_name[4] = 0x8b;
5560 nv->node_name[5] = 0x1c;
5561 nv->node_name[6] = 0x55;
5562 nv->node_name[7] = 0x86;
5563 nv->login_retry_count = __constant_cpu_to_le16(8);
5564 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5565 nv->login_timeout = __constant_cpu_to_le16(0);
5566 nv->firmware_options_1 =
5567 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5568 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5569 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5570 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5571 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5572 nv->efi_parameters = __constant_cpu_to_le32(0);
5573 nv->reset_delay = 5;
5574 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5575 nv->port_down_retry_count = __constant_cpu_to_le16(30);
5576 nv->link_down_timeout = __constant_cpu_to_le16(180);
5577 nv->enode_mac[0] = 0x00;
5578 nv->enode_mac[1] = 0xC0;
5579 nv->enode_mac[2] = 0xDD;
5580 nv->enode_mac[3] = 0x04;
5581 nv->enode_mac[4] = 0x05;
5582 nv->enode_mac[5] = 0x06 + ha->port_no;
5583
5584 rval = 1;
5585 }
5586
5587 if (IS_T10_PI_CAPABLE(ha))
5588 nv->frame_payload_size &= ~7;
5589
5590 qlt_81xx_config_nvram_stage1(vha, nv);
5591
5592 /* Reset Initialization control block */
5593 memset(icb, 0, ha->init_cb_size);
5594
5595 /* Copy 1st segment. */
5596 dptr1 = (uint8_t *)icb;
5597 dptr2 = (uint8_t *)&nv->version;
5598 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5599 while (cnt--)
5600 *dptr1++ = *dptr2++;
5601
5602 icb->login_retry_count = nv->login_retry_count;
5603
5604 /* Copy 2nd segment. */
5605 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5606 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5607 cnt = (uint8_t *)&icb->reserved_5 -
5608 (uint8_t *)&icb->interrupt_delay_timer;
5609 while (cnt--)
5610 *dptr1++ = *dptr2++;
5611
5612 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5613 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
5614 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
5615 icb->enode_mac[0] = 0x00;
5616 icb->enode_mac[1] = 0xC0;
5617 icb->enode_mac[2] = 0xDD;
5618 icb->enode_mac[3] = 0x04;
5619 icb->enode_mac[4] = 0x05;
5620 icb->enode_mac[5] = 0x06 + ha->port_no;
5621 }
5622
5623 /* Use extended-initialization control block. */
5624 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5625
5626 /*
5627 * Setup driver NVRAM options.
5628 */
5629 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
5630 "QLE8XXX");
5631
5632 qlt_81xx_config_nvram_stage2(vha, icb);
5633
5634 /* Use alternate WWN? */
5635 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
5636 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5637 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5638 }
5639
5640 /* Prepare nodename */
5641 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
5642 /*
5643 * Firmware will apply the following mask if the nodename was
5644 * not provided.
5645 */
5646 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5647 icb->node_name[0] &= 0xF0;
5648 }
5649
5650 /* Set host adapter parameters. */
5651 ha->flags.disable_risc_code_load = 0;
5652 ha->flags.enable_lip_reset = 0;
5653 ha->flags.enable_lip_full_login =
5654 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5655 ha->flags.enable_target_reset =
5656 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
5657 ha->flags.enable_led_scheme = 0;
5658 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
5659
5660 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5661 (BIT_6 | BIT_5 | BIT_4)) >> 4;
5662
5663 /* save HBA serial number */
5664 ha->serial0 = icb->port_name[5];
5665 ha->serial1 = icb->port_name[6];
5666 ha->serial2 = icb->port_name[7];
5667 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5668 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
5669
5670 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5671
5672 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5673
5674 /* Set minimum login_timeout to 4 seconds. */
5675 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5676 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5677 if (le16_to_cpu(nv->login_timeout) < 4)
5678 nv->login_timeout = __constant_cpu_to_le16(4);
5679 ha->login_timeout = le16_to_cpu(nv->login_timeout);
5680 icb->login_timeout = nv->login_timeout;
5681
5682 /* Set minimum RATOV to 100 tenths of a second. */
5683 ha->r_a_tov = 100;
5684
5685 ha->loop_reset_delay = nv->reset_delay;
5686
5687 /* Link Down Timeout = 0:
5688 *
5689 * When Port Down timer expires we will start returning
5690 * I/O's to OS with "DID_NO_CONNECT".
5691 *
5692 * Link Down Timeout != 0:
5693 *
5694 * The driver waits for the link to come up after link down
5695 * before returning I/Os to OS with "DID_NO_CONNECT".
5696 */
5697 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5698 ha->loop_down_abort_time =
5699 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5700 } else {
5701 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5702 ha->loop_down_abort_time =
5703 (LOOP_DOWN_TIME - ha->link_down_timeout);
5704 }
5705
5706 /* Need enough time to try and get the port back. */
5707 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5708 if (qlport_down_retry)
5709 ha->port_down_retry_count = qlport_down_retry;
5710
5711 /* Set login_retry_count */
5712 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5713 if (ha->port_down_retry_count ==
5714 le16_to_cpu(nv->port_down_retry_count) &&
5715 ha->port_down_retry_count > 3)
5716 ha->login_retry_count = ha->port_down_retry_count;
5717 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5718 ha->login_retry_count = ha->port_down_retry_count;
5719 if (ql2xloginretrycount)
5720 ha->login_retry_count = ql2xloginretrycount;
5721
5722 /* if not running MSI-X we need handshaking on interrupts */
5723 if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha))
5724 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
5725
5726 /* Enable ZIO. */
5727 if (!vha->flags.init_done) {
5728 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5729 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5730 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5731 le16_to_cpu(icb->interrupt_delay_timer): 2;
5732 }
5733 icb->firmware_options_2 &= __constant_cpu_to_le32(
5734 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
5735 vha->flags.process_response_queue = 0;
5736 if (ha->zio_mode != QLA_ZIO_DISABLED) {
5737 ha->zio_mode = QLA_ZIO_MODE_6;
5738
5739 ql_log(ql_log_info, vha, 0x0075,
5740 "ZIO mode %d enabled; timer delay (%d us).\n",
5741 ha->zio_mode,
5742 ha->zio_timer * 100);
5743
5744 icb->firmware_options_2 |= cpu_to_le32(
5745 (uint32_t)ha->zio_mode);
5746 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
5747 vha->flags.process_response_queue = 1;
5748 }
5749
5750 if (rval) {
5751 ql_log(ql_log_warn, vha, 0x0076,
5752 "NVRAM configuration failed.\n");
5753 }
5754 return (rval);
5755 }
5756
5757 int
5758 qla82xx_restart_isp(scsi_qla_host_t *vha)
5759 {
5760 int status, rval;
5761 uint32_t wait_time;
5762 struct qla_hw_data *ha = vha->hw;
5763 struct req_que *req = ha->req_q_map[0];
5764 struct rsp_que *rsp = ha->rsp_q_map[0];
5765 struct scsi_qla_host *vp;
5766 unsigned long flags;
5767
5768 status = qla2x00_init_rings(vha);
5769 if (!status) {
5770 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5771 ha->flags.chip_reset_done = 1;
5772
5773 status = qla2x00_fw_ready(vha);
5774 if (!status) {
5775 ql_log(ql_log_info, vha, 0x803c,
5776 "Start configure loop, status =%d.\n", status);
5777
5778 /* Issue a marker after FW becomes ready. */
5779 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
5780
5781 vha->flags.online = 1;
5782 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5783 wait_time = 256;
5784 do {
5785 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5786 qla2x00_configure_loop(vha);
5787 wait_time--;
5788 } while (!atomic_read(&vha->loop_down_timer) &&
5789 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
5790 wait_time &&
5791 (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
5792 }
5793
5794 /* if no cable then assume it's good */
5795 if ((vha->device_flags & DFLG_NO_CABLE))
5796 status = 0;
5797
5798 ql_log(ql_log_info, vha, 0x8000,
5799 "Configure loop done, status = 0x%x.\n", status);
5800 }
5801
5802 if (!status) {
5803 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5804
5805 if (!atomic_read(&vha->loop_down_timer)) {
5806 /*
5807 * Issue marker command only when we are going
5808 * to start the I/O .
5809 */
5810 vha->marker_needed = 1;
5811 }
5812
5813 vha->flags.online = 1;
5814
5815 ha->isp_ops->enable_intrs(ha);
5816
5817 ha->isp_abort_cnt = 0;
5818 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5819
5820 /* Update the firmware version */
5821 status = qla82xx_check_md_needed(vha);
5822
5823 if (ha->fce) {
5824 ha->flags.fce_enabled = 1;
5825 memset(ha->fce, 0,
5826 fce_calc_size(ha->fce_bufs));
5827 rval = qla2x00_enable_fce_trace(vha,
5828 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
5829 &ha->fce_bufs);
5830 if (rval) {
5831 ql_log(ql_log_warn, vha, 0x8001,
5832 "Unable to reinitialize FCE (%d).\n",
5833 rval);
5834 ha->flags.fce_enabled = 0;
5835 }
5836 }
5837
5838 if (ha->eft) {
5839 memset(ha->eft, 0, EFT_SIZE);
5840 rval = qla2x00_enable_eft_trace(vha,
5841 ha->eft_dma, EFT_NUM_BUFFERS);
5842 if (rval) {
5843 ql_log(ql_log_warn, vha, 0x8010,
5844 "Unable to reinitialize EFT (%d).\n",
5845 rval);
5846 }
5847 }
5848 }
5849
5850 if (!status) {
5851 ql_dbg(ql_dbg_taskm, vha, 0x8011,
5852 "qla82xx_restart_isp succeeded.\n");
5853
5854 spin_lock_irqsave(&ha->vport_slock, flags);
5855 list_for_each_entry(vp, &ha->vp_list, list) {
5856 if (vp->vp_idx) {
5857 atomic_inc(&vp->vref_count);
5858 spin_unlock_irqrestore(&ha->vport_slock, flags);
5859
5860 qla2x00_vp_abort_isp(vp);
5861
5862 spin_lock_irqsave(&ha->vport_slock, flags);
5863 atomic_dec(&vp->vref_count);
5864 }
5865 }
5866 spin_unlock_irqrestore(&ha->vport_slock, flags);
5867
5868 } else {
5869 ql_log(ql_log_warn, vha, 0x8016,
5870 "qla82xx_restart_isp **** FAILED ****.\n");
5871 }
5872
5873 return status;
5874 }
5875
5876 void
5877 qla81xx_update_fw_options(scsi_qla_host_t *vha)
5878 {
5879 struct qla_hw_data *ha = vha->hw;
5880
5881 if (!ql2xetsenable)
5882 return;
5883
5884 /* Enable ETS Burst. */
5885 memset(ha->fw_options, 0, sizeof(ha->fw_options));
5886 ha->fw_options[2] |= BIT_9;
5887 qla2x00_set_fw_options(vha, ha->fw_options);
5888 }
5889
5890 /*
5891 * qla24xx_get_fcp_prio
5892 * Gets the fcp cmd priority value for the logged in port.
5893 * Looks for a match of the port descriptors within
5894 * each of the fcp prio config entries. If a match is found,
5895 * the tag (priority) value is returned.
5896 *
5897 * Input:
5898 * vha = scsi host structure pointer.
5899 * fcport = port structure pointer.
5900 *
5901 * Return:
5902 * non-zero (if found)
5903 * -1 (if not found)
5904 *
5905 * Context:
5906 * Kernel context
5907 */
5908 static int
5909 qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
5910 {
5911 int i, entries;
5912 uint8_t pid_match, wwn_match;
5913 int priority;
5914 uint32_t pid1, pid2;
5915 uint64_t wwn1, wwn2;
5916 struct qla_fcp_prio_entry *pri_entry;
5917 struct qla_hw_data *ha = vha->hw;
5918
5919 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
5920 return -1;
5921
5922 priority = -1;
5923 entries = ha->fcp_prio_cfg->num_entries;
5924 pri_entry = &ha->fcp_prio_cfg->entry[0];
5925
5926 for (i = 0; i < entries; i++) {
5927 pid_match = wwn_match = 0;
5928
5929 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
5930 pri_entry++;
5931 continue;
5932 }
5933
5934 /* check source pid for a match */
5935 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
5936 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
5937 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
5938 if (pid1 == INVALID_PORT_ID)
5939 pid_match++;
5940 else if (pid1 == pid2)
5941 pid_match++;
5942 }
5943
5944 /* check destination pid for a match */
5945 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
5946 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
5947 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
5948 if (pid1 == INVALID_PORT_ID)
5949 pid_match++;
5950 else if (pid1 == pid2)
5951 pid_match++;
5952 }
5953
5954 /* check source WWN for a match */
5955 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
5956 wwn1 = wwn_to_u64(vha->port_name);
5957 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
5958 if (wwn2 == (uint64_t)-1)
5959 wwn_match++;
5960 else if (wwn1 == wwn2)
5961 wwn_match++;
5962 }
5963
5964 /* check destination WWN for a match */
5965 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
5966 wwn1 = wwn_to_u64(fcport->port_name);
5967 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
5968 if (wwn2 == (uint64_t)-1)
5969 wwn_match++;
5970 else if (wwn1 == wwn2)
5971 wwn_match++;
5972 }
5973
5974 if (pid_match == 2 || wwn_match == 2) {
5975 /* Found a matching entry */
5976 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
5977 priority = pri_entry->tag;
5978 break;
5979 }
5980
5981 pri_entry++;
5982 }
5983
5984 return priority;
5985 }
5986
5987 /*
5988 * qla24xx_update_fcport_fcp_prio
5989 * Activates fcp priority for the logged in fc port
5990 *
5991 * Input:
5992 * vha = scsi host structure pointer.
5993 * fcp = port structure pointer.
5994 *
5995 * Return:
5996 * QLA_SUCCESS or QLA_FUNCTION_FAILED
5997 *
5998 * Context:
5999 * Kernel context.
6000 */
6001 int
6002 qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
6003 {
6004 int ret;
6005 int priority;
6006 uint16_t mb[5];
6007
6008 if (fcport->port_type != FCT_TARGET ||
6009 fcport->loop_id == FC_NO_LOOP_ID)
6010 return QLA_FUNCTION_FAILED;
6011
6012 priority = qla24xx_get_fcp_prio(vha, fcport);
6013 if (priority < 0)
6014 return QLA_FUNCTION_FAILED;
6015
6016 if (IS_QLA82XX(vha->hw)) {
6017 fcport->fcp_prio = priority & 0xf;
6018 return QLA_SUCCESS;
6019 }
6020
6021 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
6022 if (ret == QLA_SUCCESS) {
6023 if (fcport->fcp_prio != priority)
6024 ql_dbg(ql_dbg_user, vha, 0x709e,
6025 "Updated FCP_CMND priority - value=%d loop_id=%d "
6026 "port_id=%02x%02x%02x.\n", priority,
6027 fcport->loop_id, fcport->d_id.b.domain,
6028 fcport->d_id.b.area, fcport->d_id.b.al_pa);
6029 fcport->fcp_prio = priority & 0xf;
6030 } else
6031 ql_dbg(ql_dbg_user, vha, 0x704f,
6032 "Unable to update FCP_CMND priority - ret=0x%x for "
6033 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6034 fcport->d_id.b.domain, fcport->d_id.b.area,
6035 fcport->d_id.b.al_pa);
6036 return ret;
6037 }
6038
6039 /*
6040 * qla24xx_update_all_fcp_prio
6041 * Activates fcp priority for all the logged in ports
6042 *
6043 * Input:
6044 * ha = adapter block pointer.
6045 *
6046 * Return:
6047 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6048 *
6049 * Context:
6050 * Kernel context.
6051 */
6052 int
6053 qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6054 {
6055 int ret;
6056 fc_port_t *fcport;
6057
6058 ret = QLA_FUNCTION_FAILED;
6059 /* We need to set priority for all logged in ports */
6060 list_for_each_entry(fcport, &vha->vp_fcports, list)
6061 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6062
6063 return ret;
6064 }
Linux kernel - Deliverables
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