2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2012 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
8 #include <linux/delay.h>
10 #include <linux/ratelimit.h>
11 #include <linux/vmalloc.h>
12 #include <scsi/scsi_tcq.h>
14 #define MASK(n) ((1ULL<<(n))-1)
15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19 #define MS_WIN(addr) (addr & 0x0ffc0000)
20 #define QLA82XX_PCI_MN_2M (0)
21 #define QLA82XX_PCI_MS_2M (0x80000)
22 #define QLA82XX_PCI_OCM0_2M (0xc0000)
23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
25 #define BLOCK_PROTECT_BITS 0x0F
27 /* CRB window related */
28 #define CRB_BLK(off) ((off >> 20) & 0x3f)
29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30 #define CRB_WINDOW_2M (0x130060)
31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
32 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
35 #define CRB_INDIRECT_2M (0x1e0000UL)
37 #define MAX_CRB_XFORM 60
38 static unsigned long crb_addr_xform
[MAX_CRB_XFORM
];
39 int qla82xx_crb_table_initialized
;
41 #define qla82xx_crb_addr_transform(name) \
42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
45 static void qla82xx_crb_addr_transform_setup(void)
47 qla82xx_crb_addr_transform(XDMA
);
48 qla82xx_crb_addr_transform(TIMR
);
49 qla82xx_crb_addr_transform(SRE
);
50 qla82xx_crb_addr_transform(SQN3
);
51 qla82xx_crb_addr_transform(SQN2
);
52 qla82xx_crb_addr_transform(SQN1
);
53 qla82xx_crb_addr_transform(SQN0
);
54 qla82xx_crb_addr_transform(SQS3
);
55 qla82xx_crb_addr_transform(SQS2
);
56 qla82xx_crb_addr_transform(SQS1
);
57 qla82xx_crb_addr_transform(SQS0
);
58 qla82xx_crb_addr_transform(RPMX7
);
59 qla82xx_crb_addr_transform(RPMX6
);
60 qla82xx_crb_addr_transform(RPMX5
);
61 qla82xx_crb_addr_transform(RPMX4
);
62 qla82xx_crb_addr_transform(RPMX3
);
63 qla82xx_crb_addr_transform(RPMX2
);
64 qla82xx_crb_addr_transform(RPMX1
);
65 qla82xx_crb_addr_transform(RPMX0
);
66 qla82xx_crb_addr_transform(ROMUSB
);
67 qla82xx_crb_addr_transform(SN
);
68 qla82xx_crb_addr_transform(QMN
);
69 qla82xx_crb_addr_transform(QMS
);
70 qla82xx_crb_addr_transform(PGNI
);
71 qla82xx_crb_addr_transform(PGND
);
72 qla82xx_crb_addr_transform(PGN3
);
73 qla82xx_crb_addr_transform(PGN2
);
74 qla82xx_crb_addr_transform(PGN1
);
75 qla82xx_crb_addr_transform(PGN0
);
76 qla82xx_crb_addr_transform(PGSI
);
77 qla82xx_crb_addr_transform(PGSD
);
78 qla82xx_crb_addr_transform(PGS3
);
79 qla82xx_crb_addr_transform(PGS2
);
80 qla82xx_crb_addr_transform(PGS1
);
81 qla82xx_crb_addr_transform(PGS0
);
82 qla82xx_crb_addr_transform(PS
);
83 qla82xx_crb_addr_transform(PH
);
84 qla82xx_crb_addr_transform(NIU
);
85 qla82xx_crb_addr_transform(I2Q
);
86 qla82xx_crb_addr_transform(EG
);
87 qla82xx_crb_addr_transform(MN
);
88 qla82xx_crb_addr_transform(MS
);
89 qla82xx_crb_addr_transform(CAS2
);
90 qla82xx_crb_addr_transform(CAS1
);
91 qla82xx_crb_addr_transform(CAS0
);
92 qla82xx_crb_addr_transform(CAM
);
93 qla82xx_crb_addr_transform(C2C1
);
94 qla82xx_crb_addr_transform(C2C0
);
95 qla82xx_crb_addr_transform(SMB
);
96 qla82xx_crb_addr_transform(OCM0
);
98 * Used only in P3 just define it for P2 also.
100 qla82xx_crb_addr_transform(I2C0
);
102 qla82xx_crb_table_initialized
= 1;
105 struct crb_128M_2M_block_map crb_128M_2M_map
[64] = {
107 {{{1, 0x0100000, 0x0102000, 0x120000},
108 {1, 0x0110000, 0x0120000, 0x130000},
109 {1, 0x0120000, 0x0122000, 0x124000},
110 {1, 0x0130000, 0x0132000, 0x126000},
111 {1, 0x0140000, 0x0142000, 0x128000},
112 {1, 0x0150000, 0x0152000, 0x12a000},
113 {1, 0x0160000, 0x0170000, 0x110000},
114 {1, 0x0170000, 0x0172000, 0x12e000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {1, 0x01e0000, 0x01e0800, 0x122000},
122 {0, 0x0000000, 0x0000000, 0x000000} } } ,
123 {{{1, 0x0200000, 0x0210000, 0x180000} } },
125 {{{1, 0x0400000, 0x0401000, 0x169000} } },
126 {{{1, 0x0500000, 0x0510000, 0x140000} } },
127 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
128 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
129 {{{1, 0x0800000, 0x0802000, 0x170000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {1, 0x08f0000, 0x08f2000, 0x172000} } },
145 {{{1, 0x0900000, 0x0902000, 0x174000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {1, 0x09f0000, 0x09f2000, 0x176000} } },
161 {{{0, 0x0a00000, 0x0a02000, 0x178000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
177 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
193 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
194 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
195 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
196 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
197 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
198 {{{1, 0x1100000, 0x1101000, 0x160000} } },
199 {{{1, 0x1200000, 0x1201000, 0x161000} } },
200 {{{1, 0x1300000, 0x1301000, 0x162000} } },
201 {{{1, 0x1400000, 0x1401000, 0x163000} } },
202 {{{1, 0x1500000, 0x1501000, 0x165000} } },
203 {{{1, 0x1600000, 0x1601000, 0x166000} } },
210 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
211 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
212 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
214 {{{1, 0x2100000, 0x2102000, 0x120000},
215 {1, 0x2110000, 0x2120000, 0x130000},
216 {1, 0x2120000, 0x2122000, 0x124000},
217 {1, 0x2130000, 0x2132000, 0x126000},
218 {1, 0x2140000, 0x2142000, 0x128000},
219 {1, 0x2150000, 0x2152000, 0x12a000},
220 {1, 0x2160000, 0x2170000, 0x110000},
221 {1, 0x2170000, 0x2172000, 0x12e000},
222 {0, 0x0000000, 0x0000000, 0x000000},
223 {0, 0x0000000, 0x0000000, 0x000000},
224 {0, 0x0000000, 0x0000000, 0x000000},
225 {0, 0x0000000, 0x0000000, 0x000000},
226 {0, 0x0000000, 0x0000000, 0x000000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000} } },
230 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
236 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
237 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
238 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
239 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
240 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
241 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
242 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
243 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
244 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
245 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
246 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
247 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
249 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
250 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
251 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
252 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
253 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
254 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
257 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
258 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
259 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
263 * top 12 bits of crb internal address (hub, agent)
265 unsigned qla82xx_crb_hub_agt
[64] = {
267 QLA82XX_HW_CRB_HUB_AGT_ADR_PS
,
268 QLA82XX_HW_CRB_HUB_AGT_ADR_MN
,
269 QLA82XX_HW_CRB_HUB_AGT_ADR_MS
,
271 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE
,
272 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU
,
273 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN
,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0
,
275 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1
,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2
,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3
,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q
,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR
,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB
,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4
,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA
,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0
,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1
,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2
,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3
,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND
,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI
,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0
,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1
,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2
,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3
,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI
,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_SN
,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_EG
,
299 QLA82XX_HW_CRB_HUB_AGT_ADR_PS
,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM
,
306 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR
,
308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1
,
309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2
,
310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3
,
311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4
,
312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5
,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6
,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7
,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA
,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q
,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB
,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0
,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8
,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9
,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0
,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB
,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0
,
326 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1
,
328 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC
,
333 char *q_dev_state
[] = {
344 char *qdev_state(uint32_t dev_state
)
346 return q_dev_state
[dev_state
];
350 * In: 'off' is offset from CRB space in 128M pci map
351 * Out: 'off' is 2M pci map addr
352 * side effect: lock crb window
355 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data
*ha
, ulong
*off
)
358 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
360 ha
->crb_win
= CRB_HI(*off
);
362 (void *)(CRB_WINDOW_2M
+ ha
->nx_pcibase
));
364 /* Read back value to make sure write has gone through before trying
367 win_read
= RD_REG_DWORD((void *)(CRB_WINDOW_2M
+ ha
->nx_pcibase
));
368 if (win_read
!= ha
->crb_win
) {
369 ql_dbg(ql_dbg_p3p
, vha
, 0xb000,
370 "%s: Written crbwin (0x%x) "
371 "!= Read crbwin (0x%x), off=0x%lx.\n",
372 __func__
, ha
->crb_win
, win_read
, *off
);
374 *off
= (*off
& MASK(16)) + CRB_INDIRECT_2M
+ ha
->nx_pcibase
;
377 static inline unsigned long
378 qla82xx_pci_set_crbwindow(struct qla_hw_data
*ha
, u64 off
)
380 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
381 /* See if we are currently pointing to the region we want to use next */
382 if ((off
>= QLA82XX_CRB_PCIX_HOST
) && (off
< QLA82XX_CRB_DDR_NET
)) {
383 /* No need to change window. PCIX and PCIEregs are in both
384 * regs are in both windows.
389 if ((off
>= QLA82XX_CRB_PCIX_HOST
) && (off
< QLA82XX_CRB_PCIX_HOST2
)) {
390 /* We are in first CRB window */
391 if (ha
->curr_window
!= 0)
396 if ((off
> QLA82XX_CRB_PCIX_HOST2
) && (off
< QLA82XX_CRB_MAX
)) {
397 /* We are in second CRB window */
398 off
= off
- QLA82XX_CRB_PCIX_HOST2
+ QLA82XX_CRB_PCIX_HOST
;
400 if (ha
->curr_window
!= 1)
403 /* We are in the QM or direct access
404 * register region - do nothing
406 if ((off
>= QLA82XX_PCI_DIRECT_CRB
) &&
407 (off
< QLA82XX_PCI_CAMQM_MAX
))
410 /* strange address given */
411 ql_dbg(ql_dbg_p3p
, vha
, 0xb001,
412 "%s: Warning: unm_nic_pci_set_crbwindow "
413 "called with an unknown address(%llx).\n",
414 QLA2XXX_DRIVER_NAME
, off
);
419 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data
*ha
, ulong
*off
)
421 struct crb_128M_2M_sub_block_map
*m
;
423 if (*off
>= QLA82XX_CRB_MAX
)
426 if (*off
>= QLA82XX_PCI_CAMQM
&& (*off
< QLA82XX_PCI_CAMQM_2M_END
)) {
427 *off
= (*off
- QLA82XX_PCI_CAMQM
) +
428 QLA82XX_PCI_CAMQM_2M_BASE
+ ha
->nx_pcibase
;
432 if (*off
< QLA82XX_PCI_CRBSPACE
)
435 *off
-= QLA82XX_PCI_CRBSPACE
;
438 m
= &crb_128M_2M_map
[CRB_BLK(*off
)].sub_block
[CRB_SUBBLK(*off
)];
440 if (m
->valid
&& (m
->start_128M
<= *off
) && (m
->end_128M
> *off
)) {
441 *off
= *off
+ m
->start_2M
- m
->start_128M
+ ha
->nx_pcibase
;
444 /* Not in direct map, use crb window */
448 #define CRB_WIN_LOCK_TIMEOUT 100000000
449 static int qla82xx_crb_win_lock(struct qla_hw_data
*ha
)
451 int done
= 0, timeout
= 0;
454 /* acquire semaphore3 from PCI HW block */
455 done
= qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK
));
458 if (timeout
>= CRB_WIN_LOCK_TIMEOUT
)
462 qla82xx_wr_32(ha
, QLA82XX_CRB_WIN_LOCK_ID
, ha
->portnum
);
467 qla82xx_wr_32(struct qla_hw_data
*ha
, ulong off
, u32 data
)
469 unsigned long flags
= 0;
472 rv
= qla82xx_pci_get_crb_addr_2M(ha
, &off
);
477 write_lock_irqsave(&ha
->hw_lock
, flags
);
478 qla82xx_crb_win_lock(ha
);
479 qla82xx_pci_set_crbwindow_2M(ha
, &off
);
482 writel(data
, (void __iomem
*)off
);
485 qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK
));
486 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
492 qla82xx_rd_32(struct qla_hw_data
*ha
, ulong off
)
494 unsigned long flags
= 0;
498 rv
= qla82xx_pci_get_crb_addr_2M(ha
, &off
);
503 write_lock_irqsave(&ha
->hw_lock
, flags
);
504 qla82xx_crb_win_lock(ha
);
505 qla82xx_pci_set_crbwindow_2M(ha
, &off
);
507 data
= RD_REG_DWORD((void __iomem
*)off
);
510 qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK
));
511 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
516 #define IDC_LOCK_TIMEOUT 100000000
517 int qla82xx_idc_lock(struct qla_hw_data
*ha
)
520 int done
= 0, timeout
= 0;
523 /* acquire semaphore5 from PCI HW block */
524 done
= qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK
));
527 if (timeout
>= IDC_LOCK_TIMEOUT
)
536 for (i
= 0; i
< 20; i
++)
544 void qla82xx_idc_unlock(struct qla_hw_data
*ha
)
546 qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK
));
549 /* PCI Windowing for DDR regions. */
550 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
551 (((addr) <= (high)) && ((addr) >= (low)))
553 * check memory access boundary.
554 * used by test agent. support ddr access only for now
557 qla82xx_pci_mem_bound_check(struct qla_hw_data
*ha
,
558 unsigned long long addr
, int size
)
560 if (!QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_DDR_NET
,
561 QLA82XX_ADDR_DDR_NET_MAX
) ||
562 !QLA82XX_ADDR_IN_RANGE(addr
+ size
- 1, QLA82XX_ADDR_DDR_NET
,
563 QLA82XX_ADDR_DDR_NET_MAX
) ||
564 ((size
!= 1) && (size
!= 2) && (size
!= 4) && (size
!= 8)))
570 int qla82xx_pci_set_window_warning_count
;
573 qla82xx_pci_set_window(struct qla_hw_data
*ha
, unsigned long long addr
)
577 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
579 if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_DDR_NET
,
580 QLA82XX_ADDR_DDR_NET_MAX
)) {
581 /* DDR network side */
582 window
= MN_WIN(addr
);
583 ha
->ddr_mn_window
= window
;
585 ha
->mn_win_crb
| QLA82XX_PCI_CRBSPACE
, window
);
586 win_read
= qla82xx_rd_32(ha
,
587 ha
->mn_win_crb
| QLA82XX_PCI_CRBSPACE
);
588 if ((win_read
<< 17) != window
) {
589 ql_dbg(ql_dbg_p3p
, vha
, 0xb003,
590 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
591 __func__
, window
, win_read
);
593 addr
= GET_MEM_OFFS_2M(addr
) + QLA82XX_PCI_DDR_NET
;
594 } else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_OCM0
,
595 QLA82XX_ADDR_OCM0_MAX
)) {
597 if ((addr
& 0x00ff800) == 0xff800) {
598 ql_log(ql_log_warn
, vha
, 0xb004,
599 "%s: QM access not handled.\n", __func__
);
602 window
= OCM_WIN(addr
);
603 ha
->ddr_mn_window
= window
;
605 ha
->mn_win_crb
| QLA82XX_PCI_CRBSPACE
, window
);
606 win_read
= qla82xx_rd_32(ha
,
607 ha
->mn_win_crb
| QLA82XX_PCI_CRBSPACE
);
608 temp1
= ((window
& 0x1FF) << 7) |
609 ((window
& 0x0FFFE0000) >> 17);
610 if (win_read
!= temp1
) {
611 ql_log(ql_log_warn
, vha
, 0xb005,
612 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
613 __func__
, temp1
, win_read
);
615 addr
= GET_MEM_OFFS_2M(addr
) + QLA82XX_PCI_OCM0_2M
;
617 } else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_QDR_NET
,
618 QLA82XX_P3_ADDR_QDR_NET_MAX
)) {
619 /* QDR network side */
620 window
= MS_WIN(addr
);
621 ha
->qdr_sn_window
= window
;
623 ha
->ms_win_crb
| QLA82XX_PCI_CRBSPACE
, window
);
624 win_read
= qla82xx_rd_32(ha
,
625 ha
->ms_win_crb
| QLA82XX_PCI_CRBSPACE
);
626 if (win_read
!= window
) {
627 ql_log(ql_log_warn
, vha
, 0xb006,
628 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
629 __func__
, window
, win_read
);
631 addr
= GET_MEM_OFFS_2M(addr
) + QLA82XX_PCI_QDR_NET
;
634 * peg gdb frequently accesses memory that doesn't exist,
635 * this limits the chit chat so debugging isn't slowed down.
637 if ((qla82xx_pci_set_window_warning_count
++ < 8) ||
638 (qla82xx_pci_set_window_warning_count
%64 == 0)) {
639 ql_log(ql_log_warn
, vha
, 0xb007,
640 "%s: Warning:%s Unknown address range!.\n",
641 __func__
, QLA2XXX_DRIVER_NAME
);
648 /* check if address is in the same windows as the previous access */
649 static int qla82xx_pci_is_same_window(struct qla_hw_data
*ha
,
650 unsigned long long addr
)
653 unsigned long long qdr_max
;
655 qdr_max
= QLA82XX_P3_ADDR_QDR_NET_MAX
;
657 /* DDR network side */
658 if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_DDR_NET
,
659 QLA82XX_ADDR_DDR_NET_MAX
))
661 else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_OCM0
,
662 QLA82XX_ADDR_OCM0_MAX
))
664 else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_OCM1
,
665 QLA82XX_ADDR_OCM1_MAX
))
667 else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_QDR_NET
, qdr_max
)) {
668 /* QDR network side */
669 window
= ((addr
- QLA82XX_ADDR_QDR_NET
) >> 22) & 0x3f;
670 if (ha
->qdr_sn_window
== window
)
676 static int qla82xx_pci_mem_read_direct(struct qla_hw_data
*ha
,
677 u64 off
, void *data
, int size
)
683 uint8_t *mem_ptr
= NULL
;
684 unsigned long mem_base
;
685 unsigned long mem_page
;
686 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
688 write_lock_irqsave(&ha
->hw_lock
, flags
);
691 * If attempting to access unknown address or straddle hw windows,
694 start
= qla82xx_pci_set_window(ha
, off
);
695 if ((start
== -1UL) ||
696 (qla82xx_pci_is_same_window(ha
, off
+ size
- 1) == 0)) {
697 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
698 ql_log(ql_log_fatal
, vha
, 0xb008,
699 "%s out of bound pci memory "
700 "access, offset is 0x%llx.\n",
701 QLA2XXX_DRIVER_NAME
, off
);
705 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
706 mem_base
= pci_resource_start(ha
->pdev
, 0);
707 mem_page
= start
& PAGE_MASK
;
708 /* Map two pages whenever user tries to access addresses in two
711 if (mem_page
!= ((start
+ size
- 1) & PAGE_MASK
))
712 mem_ptr
= ioremap(mem_base
+ mem_page
, PAGE_SIZE
* 2);
714 mem_ptr
= ioremap(mem_base
+ mem_page
, PAGE_SIZE
);
715 if (mem_ptr
== 0UL) {
720 addr
+= start
& (PAGE_SIZE
- 1);
721 write_lock_irqsave(&ha
->hw_lock
, flags
);
725 *(u8
*)data
= readb(addr
);
728 *(u16
*)data
= readw(addr
);
731 *(u32
*)data
= readl(addr
);
734 *(u64
*)data
= readq(addr
);
740 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
748 qla82xx_pci_mem_write_direct(struct qla_hw_data
*ha
,
749 u64 off
, void *data
, int size
)
755 uint8_t *mem_ptr
= NULL
;
756 unsigned long mem_base
;
757 unsigned long mem_page
;
758 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
760 write_lock_irqsave(&ha
->hw_lock
, flags
);
763 * If attempting to access unknown address or straddle hw windows,
766 start
= qla82xx_pci_set_window(ha
, off
);
767 if ((start
== -1UL) ||
768 (qla82xx_pci_is_same_window(ha
, off
+ size
- 1) == 0)) {
769 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
770 ql_log(ql_log_fatal
, vha
, 0xb009,
771 "%s out of bount memory "
772 "access, offset is 0x%llx.\n",
773 QLA2XXX_DRIVER_NAME
, off
);
777 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
778 mem_base
= pci_resource_start(ha
->pdev
, 0);
779 mem_page
= start
& PAGE_MASK
;
780 /* Map two pages whenever user tries to access addresses in two
783 if (mem_page
!= ((start
+ size
- 1) & PAGE_MASK
))
784 mem_ptr
= ioremap(mem_base
+ mem_page
, PAGE_SIZE
*2);
786 mem_ptr
= ioremap(mem_base
+ mem_page
, PAGE_SIZE
);
791 addr
+= start
& (PAGE_SIZE
- 1);
792 write_lock_irqsave(&ha
->hw_lock
, flags
);
796 writeb(*(u8
*)data
, addr
);
799 writew(*(u16
*)data
, addr
);
802 writel(*(u32
*)data
, addr
);
805 writeq(*(u64
*)data
, addr
);
811 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
817 #define MTU_FUDGE_FACTOR 100
819 qla82xx_decode_crb_addr(unsigned long addr
)
822 unsigned long base_addr
, offset
, pci_base
;
824 if (!qla82xx_crb_table_initialized
)
825 qla82xx_crb_addr_transform_setup();
827 pci_base
= ADDR_ERROR
;
828 base_addr
= addr
& 0xfff00000;
829 offset
= addr
& 0x000fffff;
831 for (i
= 0; i
< MAX_CRB_XFORM
; i
++) {
832 if (crb_addr_xform
[i
] == base_addr
) {
837 if (pci_base
== ADDR_ERROR
)
839 return pci_base
+ offset
;
842 static long rom_max_timeout
= 100;
843 static long qla82xx_rom_lock_timeout
= 100;
846 qla82xx_rom_lock(struct qla_hw_data
*ha
)
848 int done
= 0, timeout
= 0;
851 /* acquire semaphore2 from PCI HW block */
852 done
= qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK
));
855 if (timeout
>= qla82xx_rom_lock_timeout
)
859 qla82xx_wr_32(ha
, QLA82XX_ROM_LOCK_ID
, ROM_LOCK_DRIVER
);
864 qla82xx_rom_unlock(struct qla_hw_data
*ha
)
866 qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK
));
870 qla82xx_wait_rom_busy(struct qla_hw_data
*ha
)
874 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
877 done
= qla82xx_rd_32(ha
, QLA82XX_ROMUSB_GLB_STATUS
);
880 if (timeout
>= rom_max_timeout
) {
881 ql_dbg(ql_dbg_p3p
, vha
, 0xb00a,
882 "%s: Timeout reached waiting for rom busy.\n",
883 QLA2XXX_DRIVER_NAME
);
891 qla82xx_wait_rom_done(struct qla_hw_data
*ha
)
895 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
898 done
= qla82xx_rd_32(ha
, QLA82XX_ROMUSB_GLB_STATUS
);
901 if (timeout
>= rom_max_timeout
) {
902 ql_dbg(ql_dbg_p3p
, vha
, 0xb00b,
903 "%s: Timeout reached waiting for rom done.\n",
904 QLA2XXX_DRIVER_NAME
);
912 qla82xx_md_rw_32(struct qla_hw_data
*ha
, uint32_t off
, u32 data
, uint8_t flag
)
914 uint32_t off_value
, rval
= 0;
916 WRT_REG_DWORD((void *)(CRB_WINDOW_2M
+ ha
->nx_pcibase
),
919 /* Read back value to make sure write has gone through */
920 RD_REG_DWORD((void *)(CRB_WINDOW_2M
+ ha
->nx_pcibase
));
921 off_value
= (off
& 0x0000FFFF);
924 WRT_REG_DWORD((void *)
925 (off_value
+ CRB_INDIRECT_2M
+ ha
->nx_pcibase
),
928 rval
= RD_REG_DWORD((void *)
929 (off_value
+ CRB_INDIRECT_2M
+ ha
->nx_pcibase
));
935 qla82xx_do_rom_fast_read(struct qla_hw_data
*ha
, int addr
, int *valp
)
937 /* Dword reads to flash. */
938 qla82xx_md_rw_32(ha
, MD_DIRECT_ROM_WINDOW
, (addr
& 0xFFFF0000), 1);
939 *valp
= qla82xx_md_rw_32(ha
, MD_DIRECT_ROM_READ_BASE
+
940 (addr
& 0x0000FFFF), 0, 0);
946 qla82xx_rom_fast_read(struct qla_hw_data
*ha
, int addr
, int *valp
)
949 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
951 while ((qla82xx_rom_lock(ha
) != 0) && (loops
< 50000)) {
956 if (loops
>= 50000) {
957 ql_log(ql_log_fatal
, vha
, 0x00b9,
958 "Failed to aquire SEM2 lock.\n");
961 ret
= qla82xx_do_rom_fast_read(ha
, addr
, valp
);
962 qla82xx_rom_unlock(ha
);
967 qla82xx_read_status_reg(struct qla_hw_data
*ha
, uint32_t *val
)
969 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
970 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, M25P_INSTR_RDSR
);
971 qla82xx_wait_rom_busy(ha
);
972 if (qla82xx_wait_rom_done(ha
)) {
973 ql_log(ql_log_warn
, vha
, 0xb00c,
974 "Error waiting for rom done.\n");
977 *val
= qla82xx_rd_32(ha
, QLA82XX_ROMUSB_ROM_RDATA
);
982 qla82xx_flash_wait_write_finish(struct qla_hw_data
*ha
)
988 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
990 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ABYTE_CNT
, 0);
991 while ((done
!= 0) && (ret
== 0)) {
992 ret
= qla82xx_read_status_reg(ha
, &val
);
997 if (timeout
>= 50000) {
998 ql_log(ql_log_warn
, vha
, 0xb00d,
999 "Timeout reached waiting for write finish.\n");
1007 qla82xx_flash_set_write_enable(struct qla_hw_data
*ha
)
1010 qla82xx_wait_rom_busy(ha
);
1011 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ABYTE_CNT
, 0);
1012 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, M25P_INSTR_WREN
);
1013 qla82xx_wait_rom_busy(ha
);
1014 if (qla82xx_wait_rom_done(ha
))
1016 if (qla82xx_read_status_reg(ha
, &val
) != 0)
1024 qla82xx_write_status_reg(struct qla_hw_data
*ha
, uint32_t val
)
1026 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
1027 if (qla82xx_flash_set_write_enable(ha
))
1029 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_WDATA
, val
);
1030 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, 0x1);
1031 if (qla82xx_wait_rom_done(ha
)) {
1032 ql_log(ql_log_warn
, vha
, 0xb00e,
1033 "Error waiting for rom done.\n");
1036 return qla82xx_flash_wait_write_finish(ha
);
1040 qla82xx_write_disable_flash(struct qla_hw_data
*ha
)
1042 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
1043 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, M25P_INSTR_WRDI
);
1044 if (qla82xx_wait_rom_done(ha
)) {
1045 ql_log(ql_log_warn
, vha
, 0xb00f,
1046 "Error waiting for rom done.\n");
1053 ql82xx_rom_lock_d(struct qla_hw_data
*ha
)
1056 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
1058 while ((qla82xx_rom_lock(ha
) != 0) && (loops
< 50000)) {
1063 if (loops
>= 50000) {
1064 ql_log(ql_log_warn
, vha
, 0xb010,
1065 "ROM lock failed.\n");
1072 qla82xx_write_flash_dword(struct qla_hw_data
*ha
, uint32_t flashaddr
,
1076 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
1078 ret
= ql82xx_rom_lock_d(ha
);
1080 ql_log(ql_log_warn
, vha
, 0xb011,
1081 "ROM lock failed.\n");
1085 if (qla82xx_flash_set_write_enable(ha
))
1088 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_WDATA
, data
);
1089 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ADDRESS
, flashaddr
);
1090 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ABYTE_CNT
, 3);
1091 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, M25P_INSTR_PP
);
1092 qla82xx_wait_rom_busy(ha
);
1093 if (qla82xx_wait_rom_done(ha
)) {
1094 ql_log(ql_log_warn
, vha
, 0xb012,
1095 "Error waiting for rom done.\n");
1100 ret
= qla82xx_flash_wait_write_finish(ha
);
1103 qla82xx_rom_unlock(ha
);
1107 /* This routine does CRB initialize sequence
1108 * to put the ISP into operational state
1111 qla82xx_pinit_from_rom(scsi_qla_host_t
*vha
)
1115 struct crb_addr_pair
*buf
;
1118 struct qla_hw_data
*ha
= vha
->hw
;
1120 struct crb_addr_pair
{
1125 /* Halt all the indiviual PEGs and other blocks of the ISP */
1126 qla82xx_rom_lock(ha
);
1128 /* disable all I2Q */
1129 qla82xx_wr_32(ha
, QLA82XX_CRB_I2Q
+ 0x10, 0x0);
1130 qla82xx_wr_32(ha
, QLA82XX_CRB_I2Q
+ 0x14, 0x0);
1131 qla82xx_wr_32(ha
, QLA82XX_CRB_I2Q
+ 0x18, 0x0);
1132 qla82xx_wr_32(ha
, QLA82XX_CRB_I2Q
+ 0x1c, 0x0);
1133 qla82xx_wr_32(ha
, QLA82XX_CRB_I2Q
+ 0x20, 0x0);
1134 qla82xx_wr_32(ha
, QLA82XX_CRB_I2Q
+ 0x24, 0x0);
1136 /* disable all niu interrupts */
1137 qla82xx_wr_32(ha
, QLA82XX_CRB_NIU
+ 0x40, 0xff);
1138 /* disable xge rx/tx */
1139 qla82xx_wr_32(ha
, QLA82XX_CRB_NIU
+ 0x70000, 0x00);
1140 /* disable xg1 rx/tx */
1141 qla82xx_wr_32(ha
, QLA82XX_CRB_NIU
+ 0x80000, 0x00);
1142 /* disable sideband mac */
1143 qla82xx_wr_32(ha
, QLA82XX_CRB_NIU
+ 0x90000, 0x00);
1144 /* disable ap0 mac */
1145 qla82xx_wr_32(ha
, QLA82XX_CRB_NIU
+ 0xa0000, 0x00);
1146 /* disable ap1 mac */
1147 qla82xx_wr_32(ha
, QLA82XX_CRB_NIU
+ 0xb0000, 0x00);
1150 val
= qla82xx_rd_32(ha
, QLA82XX_CRB_SRE
+ 0x1000);
1151 qla82xx_wr_32(ha
, QLA82XX_CRB_SRE
+ 0x1000, val
& (~(0x1)));
1154 qla82xx_wr_32(ha
, QLA82XX_CRB_EPG
+ 0x1300, 0x1);
1157 qla82xx_wr_32(ha
, QLA82XX_CRB_TIMER
+ 0x0, 0x0);
1158 qla82xx_wr_32(ha
, QLA82XX_CRB_TIMER
+ 0x8, 0x0);
1159 qla82xx_wr_32(ha
, QLA82XX_CRB_TIMER
+ 0x10, 0x0);
1160 qla82xx_wr_32(ha
, QLA82XX_CRB_TIMER
+ 0x18, 0x0);
1161 qla82xx_wr_32(ha
, QLA82XX_CRB_TIMER
+ 0x100, 0x0);
1162 qla82xx_wr_32(ha
, QLA82XX_CRB_TIMER
+ 0x200, 0x0);
1165 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_0
+ 0x3c, 1);
1166 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_1
+ 0x3c, 1);
1167 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_2
+ 0x3c, 1);
1168 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_3
+ 0x3c, 1);
1169 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_4
+ 0x3c, 1);
1173 if (test_bit(ABORT_ISP_ACTIVE
, &vha
->dpc_flags
))
1174 /* don't reset CAM block on reset */
1175 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, 0xfeffffff);
1177 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, 0xffffffff);
1178 qla82xx_rom_unlock(ha
);
1180 /* Read the signature value from the flash.
1181 * Offset 0: Contain signature (0xcafecafe)
1182 * Offset 4: Offset and number of addr/value pairs
1183 * that present in CRB initialize sequence
1185 if (qla82xx_rom_fast_read(ha
, 0, &n
) != 0 || n
!= 0xcafecafeUL
||
1186 qla82xx_rom_fast_read(ha
, 4, &n
) != 0) {
1187 ql_log(ql_log_fatal
, vha
, 0x006e,
1188 "Error Reading crb_init area: n: %08x.\n", n
);
1192 /* Offset in flash = lower 16 bits
1193 * Number of entries = upper 16 bits
1195 offset
= n
& 0xffffU
;
1196 n
= (n
>> 16) & 0xffffU
;
1198 /* number of addr/value pair should not exceed 1024 entries */
1200 ql_log(ql_log_fatal
, vha
, 0x0071,
1201 "Card flash not initialized:n=0x%x.\n", n
);
1205 ql_log(ql_log_info
, vha
, 0x0072,
1206 "%d CRB init values found in ROM.\n", n
);
1208 buf
= kmalloc(n
* sizeof(struct crb_addr_pair
), GFP_KERNEL
);
1210 ql_log(ql_log_fatal
, vha
, 0x010c,
1211 "Unable to allocate memory.\n");
1215 for (i
= 0; i
< n
; i
++) {
1216 if (qla82xx_rom_fast_read(ha
, 8*i
+ 4*offset
, &val
) != 0 ||
1217 qla82xx_rom_fast_read(ha
, 8*i
+ 4*offset
+ 4, &addr
) != 0) {
1226 for (i
= 0; i
< n
; i
++) {
1227 /* Translate internal CRB initialization
1228 * address to PCI bus address
1230 off
= qla82xx_decode_crb_addr((unsigned long)buf
[i
].addr
) +
1231 QLA82XX_PCI_CRBSPACE
;
1232 /* Not all CRB addr/value pair to be written,
1233 * some of them are skipped
1236 /* skipping cold reboot MAGIC */
1237 if (off
== QLA82XX_CAM_RAM(0x1fc))
1240 /* do not reset PCI */
1241 if (off
== (ROMUSB_GLB
+ 0xbc))
1244 /* skip core clock, so that firmware can increase the clock */
1245 if (off
== (ROMUSB_GLB
+ 0xc8))
1248 /* skip the function enable register */
1249 if (off
== QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION
))
1252 if (off
== QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2
))
1255 if ((off
& 0x0ff00000) == QLA82XX_CRB_SMB
)
1258 if ((off
& 0x0ff00000) == QLA82XX_CRB_DDR_NET
)
1261 if (off
== ADDR_ERROR
) {
1262 ql_log(ql_log_fatal
, vha
, 0x0116,
1263 "Unknow addr: 0x%08lx.\n", buf
[i
].addr
);
1267 qla82xx_wr_32(ha
, off
, buf
[i
].data
);
1269 /* ISP requires much bigger delay to settle down,
1270 * else crb_window returns 0xffffffff
1272 if (off
== QLA82XX_ROMUSB_GLB_SW_RESET
)
1275 /* ISP requires millisec delay between
1276 * successive CRB register updation
1283 /* Resetting the data and instruction cache */
1284 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_D
+0xec, 0x1e);
1285 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_D
+0x4c, 8);
1286 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_I
+0x4c, 8);
1288 /* Clear all protocol processing engines */
1289 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_0
+0x8, 0);
1290 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_0
+0xc, 0);
1291 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_1
+0x8, 0);
1292 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_1
+0xc, 0);
1293 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_2
+0x8, 0);
1294 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_2
+0xc, 0);
1295 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_3
+0x8, 0);
1296 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_3
+0xc, 0);
1301 qla82xx_pci_mem_write_2M(struct qla_hw_data
*ha
,
1302 u64 off
, void *data
, int size
)
1304 int i
, j
, ret
= 0, loop
, sz
[2], off0
;
1305 int scale
, shift_amount
, startword
;
1307 uint64_t off8
, mem_crb
, tmpw
, word
[2] = {0, 0};
1310 * If not MN, go check for MS or invalid.
1312 if (off
>= QLA82XX_ADDR_QDR_NET
&& off
<= QLA82XX_P3_ADDR_QDR_NET_MAX
)
1313 mem_crb
= QLA82XX_CRB_QDR_NET
;
1315 mem_crb
= QLA82XX_CRB_DDR_NET
;
1316 if (qla82xx_pci_mem_bound_check(ha
, off
, size
) == 0)
1317 return qla82xx_pci_mem_write_direct(ha
,
1322 sz
[0] = (size
< (8 - off0
)) ? size
: (8 - off0
);
1323 sz
[1] = size
- sz
[0];
1325 off8
= off
& 0xfffffff0;
1326 loop
= (((off
& 0xf) + size
- 1) >> 4) + 1;
1329 startword
= (off
& 0xf)/8;
1331 for (i
= 0; i
< loop
; i
++) {
1332 if (qla82xx_pci_mem_read_2M(ha
, off8
+
1333 (i
<< shift_amount
), &word
[i
* scale
], 8))
1339 tmpw
= *((uint8_t *)data
);
1342 tmpw
= *((uint16_t *)data
);
1345 tmpw
= *((uint32_t *)data
);
1349 tmpw
= *((uint64_t *)data
);
1354 word
[startword
] = tmpw
;
1357 ~((~(~0ULL << (sz
[0] * 8))) << (off0
* 8));
1358 word
[startword
] |= tmpw
<< (off0
* 8);
1361 word
[startword
+1] &= ~(~0ULL << (sz
[1] * 8));
1362 word
[startword
+1] |= tmpw
>> (sz
[0] * 8);
1365 for (i
= 0; i
< loop
; i
++) {
1366 temp
= off8
+ (i
<< shift_amount
);
1367 qla82xx_wr_32(ha
, mem_crb
+MIU_TEST_AGT_ADDR_LO
, temp
);
1369 qla82xx_wr_32(ha
, mem_crb
+MIU_TEST_AGT_ADDR_HI
, temp
);
1370 temp
= word
[i
* scale
] & 0xffffffff;
1371 qla82xx_wr_32(ha
, mem_crb
+MIU_TEST_AGT_WRDATA_LO
, temp
);
1372 temp
= (word
[i
* scale
] >> 32) & 0xffffffff;
1373 qla82xx_wr_32(ha
, mem_crb
+MIU_TEST_AGT_WRDATA_HI
, temp
);
1374 temp
= word
[i
*scale
+ 1] & 0xffffffff;
1375 qla82xx_wr_32(ha
, mem_crb
+
1376 MIU_TEST_AGT_WRDATA_UPPER_LO
, temp
);
1377 temp
= (word
[i
*scale
+ 1] >> 32) & 0xffffffff;
1378 qla82xx_wr_32(ha
, mem_crb
+
1379 MIU_TEST_AGT_WRDATA_UPPER_HI
, temp
);
1381 temp
= MIU_TA_CTL_ENABLE
| MIU_TA_CTL_WRITE
;
1382 qla82xx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
, temp
);
1383 temp
= MIU_TA_CTL_START
| MIU_TA_CTL_ENABLE
| MIU_TA_CTL_WRITE
;
1384 qla82xx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
, temp
);
1386 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1387 temp
= qla82xx_rd_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
);
1388 if ((temp
& MIU_TA_CTL_BUSY
) == 0)
1392 if (j
>= MAX_CTL_CHECK
) {
1393 if (printk_ratelimit())
1394 dev_err(&ha
->pdev
->dev
,
1395 "failed to write through agent.\n");
1405 qla82xx_fw_load_from_flash(struct qla_hw_data
*ha
)
1409 long flashaddr
= ha
->flt_region_bootload
<< 2;
1410 long memaddr
= BOOTLD_START
;
1413 size
= (IMAGE_START
- BOOTLD_START
) / 8;
1415 for (i
= 0; i
< size
; i
++) {
1416 if ((qla82xx_rom_fast_read(ha
, flashaddr
, (int *)&low
)) ||
1417 (qla82xx_rom_fast_read(ha
, flashaddr
+ 4, (int *)&high
))) {
1420 data
= ((u64
)high
<< 32) | low
;
1421 qla82xx_pci_mem_write_2M(ha
, memaddr
, &data
, 8);
1425 if (i
% 0x1000 == 0)
1429 read_lock(&ha
->hw_lock
);
1430 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_0
+ 0x18, 0x1020);
1431 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, 0x80001e);
1432 read_unlock(&ha
->hw_lock
);
1437 qla82xx_pci_mem_read_2M(struct qla_hw_data
*ha
,
1438 u64 off
, void *data
, int size
)
1440 int i
, j
= 0, k
, start
, end
, loop
, sz
[2], off0
[2];
1443 uint64_t off8
, val
, mem_crb
, word
[2] = {0, 0};
1446 * If not MN, go check for MS or invalid.
1449 if (off
>= QLA82XX_ADDR_QDR_NET
&& off
<= QLA82XX_P3_ADDR_QDR_NET_MAX
)
1450 mem_crb
= QLA82XX_CRB_QDR_NET
;
1452 mem_crb
= QLA82XX_CRB_DDR_NET
;
1453 if (qla82xx_pci_mem_bound_check(ha
, off
, size
) == 0)
1454 return qla82xx_pci_mem_read_direct(ha
,
1458 off8
= off
& 0xfffffff0;
1459 off0
[0] = off
& 0xf;
1460 sz
[0] = (size
< (16 - off0
[0])) ? size
: (16 - off0
[0]);
1462 loop
= ((off0
[0] + size
- 1) >> shift_amount
) + 1;
1464 sz
[1] = size
- sz
[0];
1466 for (i
= 0; i
< loop
; i
++) {
1467 temp
= off8
+ (i
<< shift_amount
);
1468 qla82xx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_ADDR_LO
, temp
);
1470 qla82xx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_ADDR_HI
, temp
);
1471 temp
= MIU_TA_CTL_ENABLE
;
1472 qla82xx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
, temp
);
1473 temp
= MIU_TA_CTL_START
| MIU_TA_CTL_ENABLE
;
1474 qla82xx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
, temp
);
1476 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1477 temp
= qla82xx_rd_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
);
1478 if ((temp
& MIU_TA_CTL_BUSY
) == 0)
1482 if (j
>= MAX_CTL_CHECK
) {
1483 if (printk_ratelimit())
1484 dev_err(&ha
->pdev
->dev
,
1485 "failed to read through agent.\n");
1489 start
= off0
[i
] >> 2;
1490 end
= (off0
[i
] + sz
[i
] - 1) >> 2;
1491 for (k
= start
; k
<= end
; k
++) {
1492 temp
= qla82xx_rd_32(ha
,
1493 mem_crb
+ MIU_TEST_AGT_RDDATA(k
));
1494 word
[i
] |= ((uint64_t)temp
<< (32 * (k
& 1)));
1498 if (j
>= MAX_CTL_CHECK
)
1501 if ((off0
[0] & 7) == 0) {
1504 val
= ((word
[0] >> (off0
[0] * 8)) & (~(~0ULL << (sz
[0] * 8)))) |
1505 ((word
[1] & (~(~0ULL << (sz
[1] * 8)))) << (sz
[0] * 8));
1510 *(uint8_t *)data
= val
;
1513 *(uint16_t *)data
= val
;
1516 *(uint32_t *)data
= val
;
1519 *(uint64_t *)data
= val
;
1526 static struct qla82xx_uri_table_desc
*
1527 qla82xx_get_table_desc(const u8
*unirom
, int section
)
1530 struct qla82xx_uri_table_desc
*directory
=
1531 (struct qla82xx_uri_table_desc
*)&unirom
[0];
1534 __le32 entries
= cpu_to_le32(directory
->num_entries
);
1536 for (i
= 0; i
< entries
; i
++) {
1537 offset
= cpu_to_le32(directory
->findex
) +
1538 (i
* cpu_to_le32(directory
->entry_size
));
1539 tab_type
= cpu_to_le32(*((u32
*)&unirom
[offset
] + 8));
1541 if (tab_type
== section
)
1542 return (struct qla82xx_uri_table_desc
*)&unirom
[offset
];
1548 static struct qla82xx_uri_data_desc
*
1549 qla82xx_get_data_desc(struct qla_hw_data
*ha
,
1550 u32 section
, u32 idx_offset
)
1552 const u8
*unirom
= ha
->hablob
->fw
->data
;
1553 int idx
= cpu_to_le32(*((int *)&unirom
[ha
->file_prd_off
] + idx_offset
));
1554 struct qla82xx_uri_table_desc
*tab_desc
= NULL
;
1557 tab_desc
= qla82xx_get_table_desc(unirom
, section
);
1561 offset
= cpu_to_le32(tab_desc
->findex
) +
1562 (cpu_to_le32(tab_desc
->entry_size
) * idx
);
1564 return (struct qla82xx_uri_data_desc
*)&unirom
[offset
];
1568 qla82xx_get_bootld_offset(struct qla_hw_data
*ha
)
1570 u32 offset
= BOOTLD_START
;
1571 struct qla82xx_uri_data_desc
*uri_desc
= NULL
;
1573 if (ha
->fw_type
== QLA82XX_UNIFIED_ROMIMAGE
) {
1574 uri_desc
= qla82xx_get_data_desc(ha
,
1575 QLA82XX_URI_DIR_SECT_BOOTLD
, QLA82XX_URI_BOOTLD_IDX_OFF
);
1577 offset
= cpu_to_le32(uri_desc
->findex
);
1580 return (u8
*)&ha
->hablob
->fw
->data
[offset
];
1584 qla82xx_get_fw_size(struct qla_hw_data
*ha
)
1586 struct qla82xx_uri_data_desc
*uri_desc
= NULL
;
1588 if (ha
->fw_type
== QLA82XX_UNIFIED_ROMIMAGE
) {
1589 uri_desc
= qla82xx_get_data_desc(ha
, QLA82XX_URI_DIR_SECT_FW
,
1590 QLA82XX_URI_FIRMWARE_IDX_OFF
);
1592 return cpu_to_le32(uri_desc
->size
);
1595 return cpu_to_le32(*(u32
*)&ha
->hablob
->fw
->data
[FW_SIZE_OFFSET
]);
1599 qla82xx_get_fw_offs(struct qla_hw_data
*ha
)
1601 u32 offset
= IMAGE_START
;
1602 struct qla82xx_uri_data_desc
*uri_desc
= NULL
;
1604 if (ha
->fw_type
== QLA82XX_UNIFIED_ROMIMAGE
) {
1605 uri_desc
= qla82xx_get_data_desc(ha
, QLA82XX_URI_DIR_SECT_FW
,
1606 QLA82XX_URI_FIRMWARE_IDX_OFF
);
1608 offset
= cpu_to_le32(uri_desc
->findex
);
1611 return (u8
*)&ha
->hablob
->fw
->data
[offset
];
1614 /* PCI related functions */
1615 int qla82xx_pci_region_offset(struct pci_dev
*pdev
, int region
)
1617 unsigned long val
= 0;
1625 pci_read_config_dword(pdev
, QLA82XX_PCI_REG_MSIX_TBL
, &control
);
1626 val
= control
+ QLA82XX_MSIX_TBL_SPACE
;
1634 qla82xx_iospace_config(struct qla_hw_data
*ha
)
1638 if (pci_request_regions(ha
->pdev
, QLA2XXX_DRIVER_NAME
)) {
1639 ql_log_pci(ql_log_fatal
, ha
->pdev
, 0x000c,
1640 "Failed to reserver selected regions.\n");
1641 goto iospace_error_exit
;
1644 /* Use MMIO operations for all accesses. */
1645 if (!(pci_resource_flags(ha
->pdev
, 0) & IORESOURCE_MEM
)) {
1646 ql_log_pci(ql_log_fatal
, ha
->pdev
, 0x000d,
1647 "Region #0 not an MMIO resource, aborting.\n");
1648 goto iospace_error_exit
;
1651 len
= pci_resource_len(ha
->pdev
, 0);
1653 (unsigned long)ioremap(pci_resource_start(ha
->pdev
, 0), len
);
1654 if (!ha
->nx_pcibase
) {
1655 ql_log_pci(ql_log_fatal
, ha
->pdev
, 0x000e,
1656 "Cannot remap pcibase MMIO, aborting.\n");
1657 pci_release_regions(ha
->pdev
);
1658 goto iospace_error_exit
;
1661 /* Mapping of IO base pointer */
1662 ha
->iobase
= (device_reg_t __iomem
*)((uint8_t *)ha
->nx_pcibase
+
1663 0xbc000 + (ha
->pdev
->devfn
<< 11));
1667 (unsigned long)ioremap((pci_resource_start(ha
->pdev
, 4) +
1668 (ha
->pdev
->devfn
<< 12)), 4);
1669 if (!ha
->nxdb_wr_ptr
) {
1670 ql_log_pci(ql_log_fatal
, ha
->pdev
, 0x000f,
1671 "Cannot remap MMIO, aborting.\n");
1672 pci_release_regions(ha
->pdev
);
1673 goto iospace_error_exit
;
1676 /* Mapping of IO base pointer,
1677 * door bell read and write pointer
1679 ha
->nxdb_rd_ptr
= (uint8_t *) ha
->nx_pcibase
+ (512 * 1024) +
1680 (ha
->pdev
->devfn
* 8);
1682 ha
->nxdb_wr_ptr
= (ha
->pdev
->devfn
== 6 ?
1683 QLA82XX_CAMRAM_DB1
:
1684 QLA82XX_CAMRAM_DB2
);
1687 ha
->max_req_queues
= ha
->max_rsp_queues
= 1;
1688 ha
->msix_count
= ha
->max_rsp_queues
+ 1;
1689 ql_dbg_pci(ql_dbg_multiq
, ha
->pdev
, 0xc006,
1690 "nx_pci_base=%p iobase=%p "
1691 "max_req_queues=%d msix_count=%d.\n",
1692 (void *)ha
->nx_pcibase
, ha
->iobase
,
1693 ha
->max_req_queues
, ha
->msix_count
);
1694 ql_dbg_pci(ql_dbg_init
, ha
->pdev
, 0x0010,
1695 "nx_pci_base=%p iobase=%p "
1696 "max_req_queues=%d msix_count=%d.\n",
1697 (void *)ha
->nx_pcibase
, ha
->iobase
,
1698 ha
->max_req_queues
, ha
->msix_count
);
1705 /* GS related functions */
1707 /* Initialization related functions */
1710 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1713 * Returns 0 on success.
1716 qla82xx_pci_config(scsi_qla_host_t
*vha
)
1718 struct qla_hw_data
*ha
= vha
->hw
;
1721 pci_set_master(ha
->pdev
);
1722 ret
= pci_set_mwi(ha
->pdev
);
1723 ha
->chip_revision
= ha
->pdev
->revision
;
1724 ql_dbg(ql_dbg_init
, vha
, 0x0043,
1725 "Chip revision:%d.\n",
1731 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1734 * Returns 0 on success.
1737 qla82xx_reset_chip(scsi_qla_host_t
*vha
)
1739 struct qla_hw_data
*ha
= vha
->hw
;
1740 ha
->isp_ops
->disable_intrs(ha
);
1743 void qla82xx_config_rings(struct scsi_qla_host
*vha
)
1745 struct qla_hw_data
*ha
= vha
->hw
;
1746 struct device_reg_82xx __iomem
*reg
= &ha
->iobase
->isp82
;
1747 struct init_cb_81xx
*icb
;
1748 struct req_que
*req
= ha
->req_q_map
[0];
1749 struct rsp_que
*rsp
= ha
->rsp_q_map
[0];
1751 /* Setup ring parameters in initialization control block. */
1752 icb
= (struct init_cb_81xx
*)ha
->init_cb
;
1753 icb
->request_q_outpointer
= __constant_cpu_to_le16(0);
1754 icb
->response_q_inpointer
= __constant_cpu_to_le16(0);
1755 icb
->request_q_length
= cpu_to_le16(req
->length
);
1756 icb
->response_q_length
= cpu_to_le16(rsp
->length
);
1757 icb
->request_q_address
[0] = cpu_to_le32(LSD(req
->dma
));
1758 icb
->request_q_address
[1] = cpu_to_le32(MSD(req
->dma
));
1759 icb
->response_q_address
[0] = cpu_to_le32(LSD(rsp
->dma
));
1760 icb
->response_q_address
[1] = cpu_to_le32(MSD(rsp
->dma
));
1762 WRT_REG_DWORD((unsigned long __iomem
*)®
->req_q_out
[0], 0);
1763 WRT_REG_DWORD((unsigned long __iomem
*)®
->rsp_q_in
[0], 0);
1764 WRT_REG_DWORD((unsigned long __iomem
*)®
->rsp_q_out
[0], 0);
1767 void qla82xx_reset_adapter(struct scsi_qla_host
*vha
)
1769 struct qla_hw_data
*ha
= vha
->hw
;
1770 vha
->flags
.online
= 0;
1771 qla2x00_try_to_stop_firmware(vha
);
1772 ha
->isp_ops
->disable_intrs(ha
);
1776 qla82xx_fw_load_from_blob(struct qla_hw_data
*ha
)
1779 u32 i
, flashaddr
, size
;
1782 size
= (IMAGE_START
- BOOTLD_START
) / 8;
1784 ptr64
= (u64
*)qla82xx_get_bootld_offset(ha
);
1785 flashaddr
= BOOTLD_START
;
1787 for (i
= 0; i
< size
; i
++) {
1788 data
= cpu_to_le64(ptr64
[i
]);
1789 if (qla82xx_pci_mem_write_2M(ha
, flashaddr
, &data
, 8))
1794 flashaddr
= FLASH_ADDR_START
;
1795 size
= (__force u32
)qla82xx_get_fw_size(ha
) / 8;
1796 ptr64
= (u64
*)qla82xx_get_fw_offs(ha
);
1798 for (i
= 0; i
< size
; i
++) {
1799 data
= cpu_to_le64(ptr64
[i
]);
1801 if (qla82xx_pci_mem_write_2M(ha
, flashaddr
, &data
, 8))
1807 /* Write a magic value to CAMRAM register
1808 * at a specified offset to indicate
1809 * that all data is written and
1810 * ready for firmware to initialize.
1812 qla82xx_wr_32(ha
, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC
);
1814 read_lock(&ha
->hw_lock
);
1815 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_0
+ 0x18, 0x1020);
1816 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, 0x80001e);
1817 read_unlock(&ha
->hw_lock
);
1822 qla82xx_set_product_offset(struct qla_hw_data
*ha
)
1824 struct qla82xx_uri_table_desc
*ptab_desc
= NULL
;
1825 const uint8_t *unirom
= ha
->hablob
->fw
->data
;
1828 __le32 flags
, file_chiprev
, offset
;
1829 uint8_t chiprev
= ha
->chip_revision
;
1830 /* Hardcoding mn_present flag for P3P */
1834 ptab_desc
= qla82xx_get_table_desc(unirom
,
1835 QLA82XX_URI_DIR_SECT_PRODUCT_TBL
);
1839 entries
= cpu_to_le32(ptab_desc
->num_entries
);
1841 for (i
= 0; i
< entries
; i
++) {
1842 offset
= cpu_to_le32(ptab_desc
->findex
) +
1843 (i
* cpu_to_le32(ptab_desc
->entry_size
));
1844 flags
= cpu_to_le32(*((int *)&unirom
[offset
] +
1845 QLA82XX_URI_FLAGS_OFF
));
1846 file_chiprev
= cpu_to_le32(*((int *)&unirom
[offset
] +
1847 QLA82XX_URI_CHIP_REV_OFF
));
1849 flagbit
= mn_present
? 1 : 2;
1851 if ((chiprev
== file_chiprev
) && ((1ULL << flagbit
) & flags
)) {
1852 ha
->file_prd_off
= offset
;
1860 qla82xx_validate_firmware_blob(scsi_qla_host_t
*vha
, uint8_t fw_type
)
1864 struct qla_hw_data
*ha
= vha
->hw
;
1865 const struct firmware
*fw
= ha
->hablob
->fw
;
1867 ha
->fw_type
= fw_type
;
1869 if (fw_type
== QLA82XX_UNIFIED_ROMIMAGE
) {
1870 if (qla82xx_set_product_offset(ha
))
1873 min_size
= QLA82XX_URI_FW_MIN_SIZE
;
1875 val
= cpu_to_le32(*(u32
*)&fw
->data
[QLA82XX_FW_MAGIC_OFFSET
]);
1876 if ((__force u32
)val
!= QLA82XX_BDINFO_MAGIC
)
1879 min_size
= QLA82XX_FW_MIN_SIZE
;
1882 if (fw
->size
< min_size
)
1888 qla82xx_check_cmdpeg_state(struct qla_hw_data
*ha
)
1892 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
1895 read_lock(&ha
->hw_lock
);
1896 val
= qla82xx_rd_32(ha
, CRB_CMDPEG_STATE
);
1897 read_unlock(&ha
->hw_lock
);
1900 case PHAN_INITIALIZE_COMPLETE
:
1901 case PHAN_INITIALIZE_ACK
:
1903 case PHAN_INITIALIZE_FAILED
:
1908 ql_log(ql_log_info
, vha
, 0x00a8,
1909 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n",
1914 } while (--retries
);
1916 ql_log(ql_log_fatal
, vha
, 0x00a9,
1917 "Cmd Peg initialization failed: 0x%x.\n", val
);
1919 val
= qla82xx_rd_32(ha
, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE
);
1920 read_lock(&ha
->hw_lock
);
1921 qla82xx_wr_32(ha
, CRB_CMDPEG_STATE
, PHAN_INITIALIZE_FAILED
);
1922 read_unlock(&ha
->hw_lock
);
1923 return QLA_FUNCTION_FAILED
;
1927 qla82xx_check_rcvpeg_state(struct qla_hw_data
*ha
)
1931 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
1934 read_lock(&ha
->hw_lock
);
1935 val
= qla82xx_rd_32(ha
, CRB_RCVPEG_STATE
);
1936 read_unlock(&ha
->hw_lock
);
1939 case PHAN_INITIALIZE_COMPLETE
:
1940 case PHAN_INITIALIZE_ACK
:
1942 case PHAN_INITIALIZE_FAILED
:
1947 ql_log(ql_log_info
, vha
, 0x00ab,
1948 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n",
1953 } while (--retries
);
1955 ql_log(ql_log_fatal
, vha
, 0x00ac,
1956 "Rcv Peg initializatin failed: 0x%x.\n", val
);
1957 read_lock(&ha
->hw_lock
);
1958 qla82xx_wr_32(ha
, CRB_RCVPEG_STATE
, PHAN_INITIALIZE_FAILED
);
1959 read_unlock(&ha
->hw_lock
);
1960 return QLA_FUNCTION_FAILED
;
1963 /* ISR related functions */
1964 uint32_t qla82xx_isr_int_target_mask_enable
[8] = {
1965 ISR_INT_TARGET_MASK
, ISR_INT_TARGET_MASK_F1
,
1966 ISR_INT_TARGET_MASK_F2
, ISR_INT_TARGET_MASK_F3
,
1967 ISR_INT_TARGET_MASK_F4
, ISR_INT_TARGET_MASK_F5
,
1968 ISR_INT_TARGET_MASK_F7
, ISR_INT_TARGET_MASK_F7
1971 uint32_t qla82xx_isr_int_target_status
[8] = {
1972 ISR_INT_TARGET_STATUS
, ISR_INT_TARGET_STATUS_F1
,
1973 ISR_INT_TARGET_STATUS_F2
, ISR_INT_TARGET_STATUS_F3
,
1974 ISR_INT_TARGET_STATUS_F4
, ISR_INT_TARGET_STATUS_F5
,
1975 ISR_INT_TARGET_STATUS_F7
, ISR_INT_TARGET_STATUS_F7
1978 static struct qla82xx_legacy_intr_set legacy_intr
[] = \
1979 QLA82XX_LEGACY_INTR_CONFIG
;
1982 * qla82xx_mbx_completion() - Process mailbox command completions.
1983 * @ha: SCSI driver HA context
1984 * @mb0: Mailbox0 register
1987 qla82xx_mbx_completion(scsi_qla_host_t
*vha
, uint16_t mb0
)
1990 uint16_t __iomem
*wptr
;
1991 struct qla_hw_data
*ha
= vha
->hw
;
1992 struct device_reg_82xx __iomem
*reg
= &ha
->iobase
->isp82
;
1993 wptr
= (uint16_t __iomem
*)®
->mailbox_out
[1];
1995 /* Load return mailbox registers. */
1996 ha
->flags
.mbox_int
= 1;
1997 ha
->mailbox_out
[0] = mb0
;
1999 for (cnt
= 1; cnt
< ha
->mbx_count
; cnt
++) {
2000 ha
->mailbox_out
[cnt
] = RD_REG_WORD(wptr
);
2005 ql_dbg(ql_dbg_async
, vha
, 0x5053,
2006 "MBX pointer ERROR.\n");
2010 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
2012 * @dev_id: SCSI driver HA context
2015 * Called by system whenever the host adapter generates an interrupt.
2017 * Returns handled flag.
2020 qla82xx_intr_handler(int irq
, void *dev_id
)
2022 scsi_qla_host_t
*vha
;
2023 struct qla_hw_data
*ha
;
2024 struct rsp_que
*rsp
;
2025 struct device_reg_82xx __iomem
*reg
;
2026 int status
= 0, status1
= 0;
2027 unsigned long flags
;
2032 rsp
= (struct rsp_que
*) dev_id
;
2034 ql_log(ql_log_info
, NULL
, 0xb053,
2035 "%s: NULL response queue pointer.\n", __func__
);
2040 if (!ha
->flags
.msi_enabled
) {
2041 status
= qla82xx_rd_32(ha
, ISR_INT_VECTOR
);
2042 if (!(status
& ha
->nx_legacy_intr
.int_vec_bit
))
2045 status1
= qla82xx_rd_32(ha
, ISR_INT_STATE_REG
);
2046 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1
))
2050 /* clear the interrupt */
2051 qla82xx_wr_32(ha
, ha
->nx_legacy_intr
.tgt_status_reg
, 0xffffffff);
2053 /* read twice to ensure write is flushed */
2054 qla82xx_rd_32(ha
, ISR_INT_VECTOR
);
2055 qla82xx_rd_32(ha
, ISR_INT_VECTOR
);
2057 reg
= &ha
->iobase
->isp82
;
2059 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
2060 vha
= pci_get_drvdata(ha
->pdev
);
2061 for (iter
= 1; iter
--; ) {
2063 if (RD_REG_DWORD(®
->host_int
)) {
2064 stat
= RD_REG_DWORD(®
->host_status
);
2066 switch (stat
& 0xff) {
2071 qla82xx_mbx_completion(vha
, MSW(stat
));
2072 status
|= MBX_INTERRUPT
;
2076 mb
[1] = RD_REG_WORD(®
->mailbox_out
[1]);
2077 mb
[2] = RD_REG_WORD(®
->mailbox_out
[2]);
2078 mb
[3] = RD_REG_WORD(®
->mailbox_out
[3]);
2079 qla2x00_async_event(vha
, rsp
, mb
);
2082 qla24xx_process_response_queue(vha
, rsp
);
2085 ql_dbg(ql_dbg_async
, vha
, 0x5054,
2086 "Unrecognized interrupt type (%d).\n",
2091 WRT_REG_DWORD(®
->host_int
, 0);
2093 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
2094 if (!ha
->flags
.msi_enabled
)
2095 qla82xx_wr_32(ha
, ha
->nx_legacy_intr
.tgt_mask_reg
, 0xfbff);
2097 #ifdef QL_DEBUG_LEVEL_17
2098 if (!irq
&& ha
->flags
.eeh_busy
)
2099 ql_log(ql_log_warn
, vha
, 0x503d,
2100 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n",
2101 status
, ha
->mbx_cmd_flags
, ha
->flags
.mbox_int
, stat
);
2104 if (test_bit(MBX_INTR_WAIT
, &ha
->mbx_cmd_flags
) &&
2105 (status
& MBX_INTERRUPT
) && ha
->flags
.mbox_int
) {
2106 set_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
);
2107 complete(&ha
->mbx_intr_comp
);
2113 qla82xx_msix_default(int irq
, void *dev_id
)
2115 scsi_qla_host_t
*vha
;
2116 struct qla_hw_data
*ha
;
2117 struct rsp_que
*rsp
;
2118 struct device_reg_82xx __iomem
*reg
;
2120 unsigned long flags
;
2124 rsp
= (struct rsp_que
*) dev_id
;
2127 "%s(): NULL response queue pointer.\n", __func__
);
2132 reg
= &ha
->iobase
->isp82
;
2134 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
2135 vha
= pci_get_drvdata(ha
->pdev
);
2137 if (RD_REG_DWORD(®
->host_int
)) {
2138 stat
= RD_REG_DWORD(®
->host_status
);
2140 switch (stat
& 0xff) {
2145 qla82xx_mbx_completion(vha
, MSW(stat
));
2146 status
|= MBX_INTERRUPT
;
2150 mb
[1] = RD_REG_WORD(®
->mailbox_out
[1]);
2151 mb
[2] = RD_REG_WORD(®
->mailbox_out
[2]);
2152 mb
[3] = RD_REG_WORD(®
->mailbox_out
[3]);
2153 qla2x00_async_event(vha
, rsp
, mb
);
2156 qla24xx_process_response_queue(vha
, rsp
);
2159 ql_dbg(ql_dbg_async
, vha
, 0x5041,
2160 "Unrecognized interrupt type (%d).\n",
2165 WRT_REG_DWORD(®
->host_int
, 0);
2168 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
2170 #ifdef QL_DEBUG_LEVEL_17
2171 if (!irq
&& ha
->flags
.eeh_busy
)
2172 ql_log(ql_log_warn
, vha
, 0x5044,
2173 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n",
2174 status
, ha
->mbx_cmd_flags
, ha
->flags
.mbox_int
, stat
);
2177 if (test_bit(MBX_INTR_WAIT
, &ha
->mbx_cmd_flags
) &&
2178 (status
& MBX_INTERRUPT
) && ha
->flags
.mbox_int
) {
2179 set_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
);
2180 complete(&ha
->mbx_intr_comp
);
2186 qla82xx_msix_rsp_q(int irq
, void *dev_id
)
2188 scsi_qla_host_t
*vha
;
2189 struct qla_hw_data
*ha
;
2190 struct rsp_que
*rsp
;
2191 struct device_reg_82xx __iomem
*reg
;
2192 unsigned long flags
;
2194 rsp
= (struct rsp_que
*) dev_id
;
2197 "%s(): NULL response queue pointer.\n", __func__
);
2202 reg
= &ha
->iobase
->isp82
;
2203 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
2204 vha
= pci_get_drvdata(ha
->pdev
);
2205 qla24xx_process_response_queue(vha
, rsp
);
2206 WRT_REG_DWORD(®
->host_int
, 0);
2207 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
2212 qla82xx_poll(int irq
, void *dev_id
)
2214 scsi_qla_host_t
*vha
;
2215 struct qla_hw_data
*ha
;
2216 struct rsp_que
*rsp
;
2217 struct device_reg_82xx __iomem
*reg
;
2221 unsigned long flags
;
2223 rsp
= (struct rsp_que
*) dev_id
;
2226 "%s(): NULL response queue pointer.\n", __func__
);
2231 reg
= &ha
->iobase
->isp82
;
2232 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
2233 vha
= pci_get_drvdata(ha
->pdev
);
2235 if (RD_REG_DWORD(®
->host_int
)) {
2236 stat
= RD_REG_DWORD(®
->host_status
);
2237 switch (stat
& 0xff) {
2242 qla82xx_mbx_completion(vha
, MSW(stat
));
2243 status
|= MBX_INTERRUPT
;
2247 mb
[1] = RD_REG_WORD(®
->mailbox_out
[1]);
2248 mb
[2] = RD_REG_WORD(®
->mailbox_out
[2]);
2249 mb
[3] = RD_REG_WORD(®
->mailbox_out
[3]);
2250 qla2x00_async_event(vha
, rsp
, mb
);
2253 qla24xx_process_response_queue(vha
, rsp
);
2256 ql_dbg(ql_dbg_p3p
, vha
, 0xb013,
2257 "Unrecognized interrupt type (%d).\n",
2262 WRT_REG_DWORD(®
->host_int
, 0);
2263 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
2267 qla82xx_enable_intrs(struct qla_hw_data
*ha
)
2269 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
2270 qla82xx_mbx_intr_enable(vha
);
2271 spin_lock_irq(&ha
->hardware_lock
);
2272 qla82xx_wr_32(ha
, ha
->nx_legacy_intr
.tgt_mask_reg
, 0xfbff);
2273 spin_unlock_irq(&ha
->hardware_lock
);
2274 ha
->interrupts_on
= 1;
2278 qla82xx_disable_intrs(struct qla_hw_data
*ha
)
2280 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
2281 qla82xx_mbx_intr_disable(vha
);
2282 spin_lock_irq(&ha
->hardware_lock
);
2283 qla82xx_wr_32(ha
, ha
->nx_legacy_intr
.tgt_mask_reg
, 0x0400);
2284 spin_unlock_irq(&ha
->hardware_lock
);
2285 ha
->interrupts_on
= 0;
2288 void qla82xx_init_flags(struct qla_hw_data
*ha
)
2290 struct qla82xx_legacy_intr_set
*nx_legacy_intr
;
2292 /* ISP 8021 initializations */
2293 rwlock_init(&ha
->hw_lock
);
2294 ha
->qdr_sn_window
= -1;
2295 ha
->ddr_mn_window
= -1;
2296 ha
->curr_window
= 255;
2297 ha
->portnum
= PCI_FUNC(ha
->pdev
->devfn
);
2298 nx_legacy_intr
= &legacy_intr
[ha
->portnum
];
2299 ha
->nx_legacy_intr
.int_vec_bit
= nx_legacy_intr
->int_vec_bit
;
2300 ha
->nx_legacy_intr
.tgt_status_reg
= nx_legacy_intr
->tgt_status_reg
;
2301 ha
->nx_legacy_intr
.tgt_mask_reg
= nx_legacy_intr
->tgt_mask_reg
;
2302 ha
->nx_legacy_intr
.pci_int_reg
= nx_legacy_intr
->pci_int_reg
;
2306 qla82xx_set_drv_active(scsi_qla_host_t
*vha
)
2308 uint32_t drv_active
;
2309 struct qla_hw_data
*ha
= vha
->hw
;
2311 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
2313 /* If reset value is all FF's, initialize DRV_ACTIVE */
2314 if (drv_active
== 0xffffffff) {
2315 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_ACTIVE
,
2316 QLA82XX_DRV_NOT_ACTIVE
);
2317 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
2319 drv_active
|= (QLA82XX_DRV_ACTIVE
<< (ha
->portnum
* 4));
2320 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_ACTIVE
, drv_active
);
2324 qla82xx_clear_drv_active(struct qla_hw_data
*ha
)
2326 uint32_t drv_active
;
2328 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
2329 drv_active
&= ~(QLA82XX_DRV_ACTIVE
<< (ha
->portnum
* 4));
2330 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_ACTIVE
, drv_active
);
2334 qla82xx_need_reset(struct qla_hw_data
*ha
)
2339 if (ha
->flags
.nic_core_reset_owner
)
2342 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2343 rval
= drv_state
& (QLA82XX_DRVST_RST_RDY
<< (ha
->portnum
* 4));
2349 qla82xx_set_rst_ready(struct qla_hw_data
*ha
)
2352 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
2354 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2356 /* If reset value is all FF's, initialize DRV_STATE */
2357 if (drv_state
== 0xffffffff) {
2358 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_STATE
, QLA82XX_DRVST_NOT_RDY
);
2359 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2361 drv_state
|= (QLA82XX_DRVST_RST_RDY
<< (ha
->portnum
* 4));
2362 ql_dbg(ql_dbg_init
, vha
, 0x00bb,
2363 "drv_state = 0x%08x.\n", drv_state
);
2364 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_STATE
, drv_state
);
2368 qla82xx_clear_rst_ready(struct qla_hw_data
*ha
)
2372 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2373 drv_state
&= ~(QLA82XX_DRVST_RST_RDY
<< (ha
->portnum
* 4));
2374 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_STATE
, drv_state
);
2378 qla82xx_set_qsnt_ready(struct qla_hw_data
*ha
)
2380 uint32_t qsnt_state
;
2382 qsnt_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2383 qsnt_state
|= (QLA82XX_DRVST_QSNT_RDY
<< (ha
->portnum
* 4));
2384 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_STATE
, qsnt_state
);
2388 qla82xx_clear_qsnt_ready(scsi_qla_host_t
*vha
)
2390 struct qla_hw_data
*ha
= vha
->hw
;
2391 uint32_t qsnt_state
;
2393 qsnt_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2394 qsnt_state
&= ~(QLA82XX_DRVST_QSNT_RDY
<< (ha
->portnum
* 4));
2395 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_STATE
, qsnt_state
);
2399 qla82xx_load_fw(scsi_qla_host_t
*vha
)
2402 struct fw_blob
*blob
;
2403 struct qla_hw_data
*ha
= vha
->hw
;
2405 if (qla82xx_pinit_from_rom(vha
) != QLA_SUCCESS
) {
2406 ql_log(ql_log_fatal
, vha
, 0x009f,
2407 "Error during CRB initialization.\n");
2408 return QLA_FUNCTION_FAILED
;
2412 /* Bring QM and CAMRAM out of reset */
2413 rst
= qla82xx_rd_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
);
2414 rst
&= ~((1 << 28) | (1 << 24));
2415 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, rst
);
2419 * 1) Operational firmware residing in flash.
2420 * 2) Firmware via request-firmware interface (.bin file).
2422 if (ql2xfwloadbin
== 2)
2425 ql_log(ql_log_info
, vha
, 0x00a0,
2426 "Attempting to load firmware from flash.\n");
2428 if (qla82xx_fw_load_from_flash(ha
) == QLA_SUCCESS
) {
2429 ql_log(ql_log_info
, vha
, 0x00a1,
2430 "Firmware loaded successfully from flash.\n");
2433 ql_log(ql_log_warn
, vha
, 0x0108,
2434 "Firmware load from flash failed.\n");
2438 ql_log(ql_log_info
, vha
, 0x00a2,
2439 "Attempting to load firmware from blob.\n");
2441 /* Load firmware blob. */
2442 blob
= ha
->hablob
= qla2x00_request_firmware(vha
);
2444 ql_log(ql_log_fatal
, vha
, 0x00a3,
2445 "Firmware image not present.\n");
2446 goto fw_load_failed
;
2449 /* Validating firmware blob */
2450 if (qla82xx_validate_firmware_blob(vha
,
2451 QLA82XX_FLASH_ROMIMAGE
)) {
2452 /* Fallback to URI format */
2453 if (qla82xx_validate_firmware_blob(vha
,
2454 QLA82XX_UNIFIED_ROMIMAGE
)) {
2455 ql_log(ql_log_fatal
, vha
, 0x00a4,
2456 "No valid firmware image found.\n");
2457 return QLA_FUNCTION_FAILED
;
2461 if (qla82xx_fw_load_from_blob(ha
) == QLA_SUCCESS
) {
2462 ql_log(ql_log_info
, vha
, 0x00a5,
2463 "Firmware loaded successfully from binary blob.\n");
2466 ql_log(ql_log_fatal
, vha
, 0x00a6,
2467 "Firmware load failed for binary blob.\n");
2470 goto fw_load_failed
;
2475 return QLA_FUNCTION_FAILED
;
2479 qla82xx_start_firmware(scsi_qla_host_t
*vha
)
2483 struct qla_hw_data
*ha
= vha
->hw
;
2485 /* scrub dma mask expansion register */
2486 qla82xx_wr_32(ha
, CRB_DMA_SHIFT
, QLA82XX_DMA_SHIFT_VALUE
);
2488 /* Put both the PEG CMD and RCV PEG to default state
2489 * of 0 before resetting the hardware
2491 qla82xx_wr_32(ha
, CRB_CMDPEG_STATE
, 0);
2492 qla82xx_wr_32(ha
, CRB_RCVPEG_STATE
, 0);
2494 /* Overwrite stale initialization register values */
2495 qla82xx_wr_32(ha
, QLA82XX_PEG_HALT_STATUS1
, 0);
2496 qla82xx_wr_32(ha
, QLA82XX_PEG_HALT_STATUS2
, 0);
2498 if (qla82xx_load_fw(vha
) != QLA_SUCCESS
) {
2499 ql_log(ql_log_fatal
, vha
, 0x00a7,
2500 "Error trying to start fw.\n");
2501 return QLA_FUNCTION_FAILED
;
2504 /* Handshake with the card before we register the devices. */
2505 if (qla82xx_check_cmdpeg_state(ha
) != QLA_SUCCESS
) {
2506 ql_log(ql_log_fatal
, vha
, 0x00aa,
2507 "Error during card handshake.\n");
2508 return QLA_FUNCTION_FAILED
;
2511 /* Negotiated Link width */
2512 pcie_cap
= pci_pcie_cap(ha
->pdev
);
2513 pci_read_config_word(ha
->pdev
, pcie_cap
+ PCI_EXP_LNKSTA
, &lnk
);
2514 ha
->link_width
= (lnk
>> 4) & 0x3f;
2516 /* Synchronize with Receive peg */
2517 return qla82xx_check_rcvpeg_state(ha
);
2521 qla82xx_read_flash_data(scsi_qla_host_t
*vha
, uint32_t *dwptr
, uint32_t faddr
,
2526 struct qla_hw_data
*ha
= vha
->hw
;
2528 /* Dword reads to flash. */
2529 for (i
= 0; i
< length
/4; i
++, faddr
+= 4) {
2530 if (qla82xx_rom_fast_read(ha
, faddr
, &val
)) {
2531 ql_log(ql_log_warn
, vha
, 0x0106,
2532 "Do ROM fast read failed.\n");
2535 dwptr
[i
] = __constant_cpu_to_le32(val
);
2542 qla82xx_unprotect_flash(struct qla_hw_data
*ha
)
2546 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
2548 ret
= ql82xx_rom_lock_d(ha
);
2550 ql_log(ql_log_warn
, vha
, 0xb014,
2551 "ROM Lock failed.\n");
2555 ret
= qla82xx_read_status_reg(ha
, &val
);
2557 goto done_unprotect
;
2559 val
&= ~(BLOCK_PROTECT_BITS
<< 2);
2560 ret
= qla82xx_write_status_reg(ha
, val
);
2562 val
|= (BLOCK_PROTECT_BITS
<< 2);
2563 qla82xx_write_status_reg(ha
, val
);
2566 if (qla82xx_write_disable_flash(ha
) != 0)
2567 ql_log(ql_log_warn
, vha
, 0xb015,
2568 "Write disable failed.\n");
2571 qla82xx_rom_unlock(ha
);
2576 qla82xx_protect_flash(struct qla_hw_data
*ha
)
2580 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
2582 ret
= ql82xx_rom_lock_d(ha
);
2584 ql_log(ql_log_warn
, vha
, 0xb016,
2585 "ROM Lock failed.\n");
2589 ret
= qla82xx_read_status_reg(ha
, &val
);
2593 val
|= (BLOCK_PROTECT_BITS
<< 2);
2594 /* LOCK all sectors */
2595 ret
= qla82xx_write_status_reg(ha
, val
);
2597 ql_log(ql_log_warn
, vha
, 0xb017,
2598 "Write status register failed.\n");
2600 if (qla82xx_write_disable_flash(ha
) != 0)
2601 ql_log(ql_log_warn
, vha
, 0xb018,
2602 "Write disable failed.\n");
2604 qla82xx_rom_unlock(ha
);
2609 qla82xx_erase_sector(struct qla_hw_data
*ha
, int addr
)
2612 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
2614 ret
= ql82xx_rom_lock_d(ha
);
2616 ql_log(ql_log_warn
, vha
, 0xb019,
2617 "ROM Lock failed.\n");
2621 qla82xx_flash_set_write_enable(ha
);
2622 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ADDRESS
, addr
);
2623 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ABYTE_CNT
, 3);
2624 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, M25P_INSTR_SE
);
2626 if (qla82xx_wait_rom_done(ha
)) {
2627 ql_log(ql_log_warn
, vha
, 0xb01a,
2628 "Error waiting for rom done.\n");
2632 ret
= qla82xx_flash_wait_write_finish(ha
);
2634 qla82xx_rom_unlock(ha
);
2639 * Address and length are byte address
2642 qla82xx_read_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
2643 uint32_t offset
, uint32_t length
)
2645 scsi_block_requests(vha
->host
);
2646 qla82xx_read_flash_data(vha
, (uint32_t *)buf
, offset
, length
);
2647 scsi_unblock_requests(vha
->host
);
2652 qla82xx_write_flash_data(struct scsi_qla_host
*vha
, uint32_t *dwptr
,
2653 uint32_t faddr
, uint32_t dwords
)
2657 uint32_t sec_mask
, rest_addr
;
2658 dma_addr_t optrom_dma
;
2659 void *optrom
= NULL
;
2661 struct qla_hw_data
*ha
= vha
->hw
;
2665 /* Prepare burst-capable write on supported ISPs. */
2666 if (page_mode
&& !(faddr
& 0xfff) &&
2667 dwords
> OPTROM_BURST_DWORDS
) {
2668 optrom
= dma_alloc_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
,
2669 &optrom_dma
, GFP_KERNEL
);
2671 ql_log(ql_log_warn
, vha
, 0xb01b,
2672 "Unable to allocate memory "
2673 "for optrom burst write (%x KB).\n",
2674 OPTROM_BURST_SIZE
/ 1024);
2678 rest_addr
= ha
->fdt_block_size
- 1;
2679 sec_mask
= ~rest_addr
;
2681 ret
= qla82xx_unprotect_flash(ha
);
2683 ql_log(ql_log_warn
, vha
, 0xb01c,
2684 "Unable to unprotect flash for update.\n");
2688 for (liter
= 0; liter
< dwords
; liter
++, faddr
+= 4, dwptr
++) {
2689 /* Are we at the beginning of a sector? */
2690 if ((faddr
& rest_addr
) == 0) {
2692 ret
= qla82xx_erase_sector(ha
, faddr
);
2694 ql_log(ql_log_warn
, vha
, 0xb01d,
2695 "Unable to erase sector: address=%x.\n",
2701 /* Go with burst-write. */
2702 if (optrom
&& (liter
+ OPTROM_BURST_DWORDS
) <= dwords
) {
2703 /* Copy data to DMA'ble buffer. */
2704 memcpy(optrom
, dwptr
, OPTROM_BURST_SIZE
);
2706 ret
= qla2x00_load_ram(vha
, optrom_dma
,
2707 (ha
->flash_data_off
| faddr
),
2708 OPTROM_BURST_DWORDS
);
2709 if (ret
!= QLA_SUCCESS
) {
2710 ql_log(ql_log_warn
, vha
, 0xb01e,
2711 "Unable to burst-write optrom segment "
2712 "(%x/%x/%llx).\n", ret
,
2713 (ha
->flash_data_off
| faddr
),
2714 (unsigned long long)optrom_dma
);
2715 ql_log(ql_log_warn
, vha
, 0xb01f,
2716 "Reverting to slow-write.\n");
2718 dma_free_coherent(&ha
->pdev
->dev
,
2719 OPTROM_BURST_SIZE
, optrom
, optrom_dma
);
2722 liter
+= OPTROM_BURST_DWORDS
- 1;
2723 faddr
+= OPTROM_BURST_DWORDS
- 1;
2724 dwptr
+= OPTROM_BURST_DWORDS
- 1;
2729 ret
= qla82xx_write_flash_dword(ha
, faddr
,
2730 cpu_to_le32(*dwptr
));
2732 ql_dbg(ql_dbg_p3p
, vha
, 0xb020,
2733 "Unable to program flash address=%x data=%x.\n",
2739 ret
= qla82xx_protect_flash(ha
);
2741 ql_log(ql_log_warn
, vha
, 0xb021,
2742 "Unable to protect flash after update.\n");
2745 dma_free_coherent(&ha
->pdev
->dev
,
2746 OPTROM_BURST_SIZE
, optrom
, optrom_dma
);
2751 qla82xx_write_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
2752 uint32_t offset
, uint32_t length
)
2757 scsi_block_requests(vha
->host
);
2758 rval
= qla82xx_write_flash_data(vha
, (uint32_t *)buf
, offset
,
2760 scsi_unblock_requests(vha
->host
);
2762 /* Convert return ISP82xx to generic */
2764 rval
= QLA_FUNCTION_FAILED
;
2771 qla82xx_start_iocbs(scsi_qla_host_t
*vha
)
2773 struct qla_hw_data
*ha
= vha
->hw
;
2774 struct req_que
*req
= ha
->req_q_map
[0];
2775 struct device_reg_82xx __iomem
*reg
;
2778 /* Adjust ring index. */
2780 if (req
->ring_index
== req
->length
) {
2781 req
->ring_index
= 0;
2782 req
->ring_ptr
= req
->ring
;
2786 reg
= &ha
->iobase
->isp82
;
2787 dbval
= 0x04 | (ha
->portnum
<< 5);
2789 dbval
= dbval
| (req
->id
<< 8) | (req
->ring_index
<< 16);
2791 qla82xx_wr_32(ha
, ha
->nxdb_wr_ptr
, dbval
);
2793 WRT_REG_DWORD((unsigned long __iomem
*)ha
->nxdb_wr_ptr
, dbval
);
2795 while (RD_REG_DWORD(ha
->nxdb_rd_ptr
) != dbval
) {
2796 WRT_REG_DWORD((unsigned long __iomem
*)ha
->nxdb_wr_ptr
,
2803 void qla82xx_rom_lock_recovery(struct qla_hw_data
*ha
)
2805 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
2807 if (qla82xx_rom_lock(ha
))
2808 /* Someone else is holding the lock. */
2809 ql_log(ql_log_info
, vha
, 0xb022,
2810 "Resetting rom_lock.\n");
2813 * Either we got the lock, or someone
2814 * else died while holding it.
2815 * In either case, unlock.
2817 qla82xx_rom_unlock(ha
);
2821 * qla82xx_device_bootstrap
2822 * Initialize device, set DEV_READY, start fw
2825 * IDC lock must be held upon entry
2832 qla82xx_device_bootstrap(scsi_qla_host_t
*vha
)
2834 int rval
= QLA_SUCCESS
;
2836 uint32_t old_count
, count
;
2837 struct qla_hw_data
*ha
= vha
->hw
;
2838 int need_reset
= 0, peg_stuck
= 1;
2840 need_reset
= qla82xx_need_reset(ha
);
2842 old_count
= qla82xx_rd_32(ha
, QLA82XX_PEG_ALIVE_COUNTER
);
2844 for (i
= 0; i
< 10; i
++) {
2845 timeout
= msleep_interruptible(200);
2847 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
,
2848 QLA8XXX_DEV_FAILED
);
2849 return QLA_FUNCTION_FAILED
;
2852 count
= qla82xx_rd_32(ha
, QLA82XX_PEG_ALIVE_COUNTER
);
2853 if (count
!= old_count
)
2858 /* We are trying to perform a recovery here. */
2860 qla82xx_rom_lock_recovery(ha
);
2861 goto dev_initialize
;
2863 /* Start of day for this ha context. */
2865 /* Either we are the first or recovery in progress. */
2866 qla82xx_rom_lock_recovery(ha
);
2867 goto dev_initialize
;
2869 /* Firmware already running. */
2876 /* set to DEV_INITIALIZING */
2877 ql_log(ql_log_info
, vha
, 0x009e,
2878 "HW State: INITIALIZING.\n");
2879 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
, QLA8XXX_DEV_INITIALIZING
);
2881 /* Driver that sets device state to initializating sets IDC version */
2882 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_IDC_VERSION
, QLA82XX_IDC_VERSION
);
2884 qla82xx_idc_unlock(ha
);
2885 rval
= qla82xx_start_firmware(vha
);
2886 qla82xx_idc_lock(ha
);
2888 if (rval
!= QLA_SUCCESS
) {
2889 ql_log(ql_log_fatal
, vha
, 0x00ad,
2890 "HW State: FAILED.\n");
2891 qla82xx_clear_drv_active(ha
);
2892 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
, QLA8XXX_DEV_FAILED
);
2897 ql_log(ql_log_info
, vha
, 0x00ae,
2898 "HW State: READY.\n");
2899 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
, QLA8XXX_DEV_READY
);
2905 * qla82xx_need_qsnt_handler
2906 * Code to start quiescence sequence
2909 * IDC lock must be held upon entry
2915 qla82xx_need_qsnt_handler(scsi_qla_host_t
*vha
)
2917 struct qla_hw_data
*ha
= vha
->hw
;
2918 uint32_t dev_state
, drv_state
, drv_active
;
2919 unsigned long reset_timeout
;
2921 if (vha
->flags
.online
) {
2922 /*Block any further I/O and wait for pending cmnds to complete*/
2923 qla2x00_quiesce_io(vha
);
2926 /* Set the quiescence ready bit */
2927 qla82xx_set_qsnt_ready(ha
);
2929 /*wait for 30 secs for other functions to ack */
2930 reset_timeout
= jiffies
+ (30 * HZ
);
2932 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2933 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
2934 /* Its 2 that is written when qsnt is acked, moving one bit */
2935 drv_active
= drv_active
<< 0x01;
2937 while (drv_state
!= drv_active
) {
2939 if (time_after_eq(jiffies
, reset_timeout
)) {
2940 /* quiescence timeout, other functions didn't ack
2941 * changing the state to DEV_READY
2943 ql_log(ql_log_info
, vha
, 0xb023,
2944 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d "
2945 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME
,
2946 drv_active
, drv_state
);
2947 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
,
2949 ql_log(ql_log_info
, vha
, 0xb025,
2950 "HW State: DEV_READY.\n");
2951 qla82xx_idc_unlock(ha
);
2952 qla2x00_perform_loop_resync(vha
);
2953 qla82xx_idc_lock(ha
);
2955 qla82xx_clear_qsnt_ready(vha
);
2959 qla82xx_idc_unlock(ha
);
2961 qla82xx_idc_lock(ha
);
2963 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2964 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
2965 drv_active
= drv_active
<< 0x01;
2967 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
2968 /* everyone acked so set the state to DEV_QUIESCENCE */
2969 if (dev_state
== QLA8XXX_DEV_NEED_QUIESCENT
) {
2970 ql_log(ql_log_info
, vha
, 0xb026,
2971 "HW State: DEV_QUIESCENT.\n");
2972 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
, QLA8XXX_DEV_QUIESCENT
);
2977 * qla82xx_wait_for_state_change
2978 * Wait for device state to change from given current state
2981 * IDC lock must not be held upon entry
2984 * Changed device state.
2987 qla82xx_wait_for_state_change(scsi_qla_host_t
*vha
, uint32_t curr_state
)
2989 struct qla_hw_data
*ha
= vha
->hw
;
2994 qla82xx_idc_lock(ha
);
2995 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
2996 qla82xx_idc_unlock(ha
);
2997 } while (dev_state
== curr_state
);
3003 qla8xxx_dev_failed_handler(scsi_qla_host_t
*vha
)
3005 struct qla_hw_data
*ha
= vha
->hw
;
3007 /* Disable the board */
3008 ql_log(ql_log_fatal
, vha
, 0x00b8,
3009 "Disabling the board.\n");
3011 qla82xx_clear_drv_active(ha
);
3012 qla82xx_idc_unlock(ha
);
3014 /* Set DEV_FAILED flag to disable timer */
3015 vha
->device_flags
|= DFLG_DEV_FAILED
;
3016 qla2x00_abort_all_cmds(vha
, DID_NO_CONNECT
<< 16);
3017 qla2x00_mark_all_devices_lost(vha
, 0);
3018 vha
->flags
.online
= 0;
3019 vha
->flags
.init_done
= 0;
3023 * qla82xx_need_reset_handler
3024 * Code to start reset sequence
3027 * IDC lock must be held upon entry
3034 qla82xx_need_reset_handler(scsi_qla_host_t
*vha
)
3036 uint32_t dev_state
, drv_state
, drv_active
;
3037 uint32_t active_mask
= 0;
3038 unsigned long reset_timeout
;
3039 struct qla_hw_data
*ha
= vha
->hw
;
3040 struct req_que
*req
= ha
->req_q_map
[0];
3042 if (vha
->flags
.online
) {
3043 qla82xx_idc_unlock(ha
);
3044 qla2x00_abort_isp_cleanup(vha
);
3045 ha
->isp_ops
->get_flash_version(vha
, req
->ring
);
3046 ha
->isp_ops
->nvram_config(vha
);
3047 qla82xx_idc_lock(ha
);
3050 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
3051 if (!ha
->flags
.nic_core_reset_owner
) {
3052 ql_dbg(ql_dbg_p3p
, vha
, 0xb028,
3053 "reset_acknowledged by 0x%x\n", ha
->portnum
);
3054 qla82xx_set_rst_ready(ha
);
3056 active_mask
= ~(QLA82XX_DRV_ACTIVE
<< (ha
->portnum
* 4));
3057 drv_active
&= active_mask
;
3058 ql_dbg(ql_dbg_p3p
, vha
, 0xb029,
3059 "active_mask: 0x%08x\n", active_mask
);
3062 /* wait for 10 seconds for reset ack from all functions */
3063 reset_timeout
= jiffies
+ (ha
->fcoe_reset_timeout
* HZ
);
3065 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
3066 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
3067 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
3069 ql_dbg(ql_dbg_p3p
, vha
, 0xb02a,
3070 "drv_state: 0x%08x, drv_active: 0x%08x, "
3071 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3072 drv_state
, drv_active
, dev_state
, active_mask
);
3074 while (drv_state
!= drv_active
&&
3075 dev_state
!= QLA8XXX_DEV_INITIALIZING
) {
3076 if (time_after_eq(jiffies
, reset_timeout
)) {
3077 ql_log(ql_log_warn
, vha
, 0x00b5,
3078 "Reset timeout.\n");
3081 qla82xx_idc_unlock(ha
);
3083 qla82xx_idc_lock(ha
);
3084 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
3085 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
3086 if (ha
->flags
.nic_core_reset_owner
)
3087 drv_active
&= active_mask
;
3088 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
3091 ql_dbg(ql_dbg_p3p
, vha
, 0xb02b,
3092 "drv_state: 0x%08x, drv_active: 0x%08x, "
3093 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3094 drv_state
, drv_active
, dev_state
, active_mask
);
3096 ql_log(ql_log_info
, vha
, 0x00b6,
3097 "Device state is 0x%x = %s.\n",
3099 dev_state
< MAX_STATES
? qdev_state(dev_state
) : "Unknown");
3101 /* Force to DEV_COLD unless someone else is starting a reset */
3102 if (dev_state
!= QLA8XXX_DEV_INITIALIZING
&&
3103 dev_state
!= QLA8XXX_DEV_COLD
) {
3104 ql_log(ql_log_info
, vha
, 0x00b7,
3105 "HW State: COLD/RE-INIT.\n");
3106 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
, QLA8XXX_DEV_COLD
);
3107 qla82xx_set_rst_ready(ha
);
3109 if (qla82xx_md_collect(vha
))
3110 ql_log(ql_log_warn
, vha
, 0xb02c,
3111 "Minidump not collected.\n");
3113 ql_log(ql_log_warn
, vha
, 0xb04f,
3114 "Minidump disabled.\n");
3119 qla82xx_check_md_needed(scsi_qla_host_t
*vha
)
3121 struct qla_hw_data
*ha
= vha
->hw
;
3122 uint16_t fw_major_version
, fw_minor_version
, fw_subminor_version
;
3123 int rval
= QLA_SUCCESS
;
3125 fw_major_version
= ha
->fw_major_version
;
3126 fw_minor_version
= ha
->fw_minor_version
;
3127 fw_subminor_version
= ha
->fw_subminor_version
;
3129 rval
= qla2x00_get_fw_version(vha
);
3130 if (rval
!= QLA_SUCCESS
)
3134 if (!ha
->fw_dumped
) {
3135 if (fw_major_version
!= ha
->fw_major_version
||
3136 fw_minor_version
!= ha
->fw_minor_version
||
3137 fw_subminor_version
!= ha
->fw_subminor_version
) {
3138 ql_log(ql_log_info
, vha
, 0xb02d,
3139 "Firmware version differs "
3140 "Previous version: %d:%d:%d - "
3141 "New version: %d:%d:%d\n",
3142 fw_major_version
, fw_minor_version
,
3143 fw_subminor_version
,
3144 ha
->fw_major_version
,
3145 ha
->fw_minor_version
,
3146 ha
->fw_subminor_version
);
3147 /* Release MiniDump resources */
3148 qla82xx_md_free(vha
);
3149 /* ALlocate MiniDump resources */
3150 qla82xx_md_prep(vha
);
3153 ql_log(ql_log_info
, vha
, 0xb02e,
3154 "Firmware dump available to retrieve\n");
3161 qla82xx_check_fw_alive(scsi_qla_host_t
*vha
)
3163 uint32_t fw_heartbeat_counter
;
3166 fw_heartbeat_counter
= qla82xx_rd_32(vha
->hw
,
3167 QLA82XX_PEG_ALIVE_COUNTER
);
3168 /* all 0xff, assume AER/EEH in progress, ignore */
3169 if (fw_heartbeat_counter
== 0xffffffff) {
3170 ql_dbg(ql_dbg_timer
, vha
, 0x6003,
3171 "FW heartbeat counter is 0xffffffff, "
3172 "returning status=%d.\n", status
);
3175 if (vha
->fw_heartbeat_counter
== fw_heartbeat_counter
) {
3176 vha
->seconds_since_last_heartbeat
++;
3177 /* FW not alive after 2 seconds */
3178 if (vha
->seconds_since_last_heartbeat
== 2) {
3179 vha
->seconds_since_last_heartbeat
= 0;
3183 vha
->seconds_since_last_heartbeat
= 0;
3184 vha
->fw_heartbeat_counter
= fw_heartbeat_counter
;
3186 ql_dbg(ql_dbg_timer
, vha
, 0x6004,
3187 "Returning status=%d.\n", status
);
3192 * qla82xx_device_state_handler
3193 * Main state handler
3196 * IDC lock must be held upon entry
3203 qla82xx_device_state_handler(scsi_qla_host_t
*vha
)
3206 uint32_t old_dev_state
;
3207 int rval
= QLA_SUCCESS
;
3208 unsigned long dev_init_timeout
;
3209 struct qla_hw_data
*ha
= vha
->hw
;
3212 qla82xx_idc_lock(ha
);
3213 if (!vha
->flags
.init_done
)
3214 qla82xx_set_drv_active(vha
);
3216 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
3217 old_dev_state
= dev_state
;
3218 ql_log(ql_log_info
, vha
, 0x009b,
3219 "Device state is 0x%x = %s.\n",
3221 dev_state
< MAX_STATES
? qdev_state(dev_state
) : "Unknown");
3223 /* wait for 30 seconds for device to go ready */
3224 dev_init_timeout
= jiffies
+ (ha
->fcoe_dev_init_timeout
* HZ
);
3228 if (time_after_eq(jiffies
, dev_init_timeout
)) {
3229 ql_log(ql_log_fatal
, vha
, 0x009c,
3230 "Device init failed.\n");
3231 rval
= QLA_FUNCTION_FAILED
;
3234 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
3235 if (old_dev_state
!= dev_state
) {
3237 old_dev_state
= dev_state
;
3239 if (loopcount
< 5) {
3240 ql_log(ql_log_info
, vha
, 0x009d,
3241 "Device state is 0x%x = %s.\n",
3243 dev_state
< MAX_STATES
? qdev_state(dev_state
) :
3247 switch (dev_state
) {
3248 case QLA8XXX_DEV_READY
:
3249 ha
->flags
.nic_core_reset_owner
= 0;
3251 case QLA8XXX_DEV_COLD
:
3252 rval
= qla82xx_device_bootstrap(vha
);
3254 case QLA8XXX_DEV_INITIALIZING
:
3255 qla82xx_idc_unlock(ha
);
3257 qla82xx_idc_lock(ha
);
3259 case QLA8XXX_DEV_NEED_RESET
:
3260 if (!ql2xdontresethba
)
3261 qla82xx_need_reset_handler(vha
);
3263 qla82xx_idc_unlock(ha
);
3265 qla82xx_idc_lock(ha
);
3267 dev_init_timeout
= jiffies
+
3268 (ha
->fcoe_dev_init_timeout
* HZ
);
3270 case QLA8XXX_DEV_NEED_QUIESCENT
:
3271 qla82xx_need_qsnt_handler(vha
);
3272 /* Reset timeout value after quiescence handler */
3273 dev_init_timeout
= jiffies
+ (ha
->fcoe_dev_init_timeout\
3276 case QLA8XXX_DEV_QUIESCENT
:
3277 /* Owner will exit and other will wait for the state
3280 if (ha
->flags
.quiesce_owner
)
3283 qla82xx_idc_unlock(ha
);
3285 qla82xx_idc_lock(ha
);
3287 /* Reset timeout value after quiescence handler */
3288 dev_init_timeout
= jiffies
+ (ha
->fcoe_dev_init_timeout\
3291 case QLA8XXX_DEV_FAILED
:
3292 qla8xxx_dev_failed_handler(vha
);
3293 rval
= QLA_FUNCTION_FAILED
;
3296 qla82xx_idc_unlock(ha
);
3298 qla82xx_idc_lock(ha
);
3303 qla82xx_idc_unlock(ha
);
3308 static int qla82xx_check_temp(scsi_qla_host_t
*vha
)
3310 uint32_t temp
, temp_state
, temp_val
;
3311 struct qla_hw_data
*ha
= vha
->hw
;
3313 temp
= qla82xx_rd_32(ha
, CRB_TEMP_STATE
);
3314 temp_state
= qla82xx_get_temp_state(temp
);
3315 temp_val
= qla82xx_get_temp_val(temp
);
3317 if (temp_state
== QLA82XX_TEMP_PANIC
) {
3318 ql_log(ql_log_warn
, vha
, 0x600e,
3319 "Device temperature %d degrees C exceeds "
3320 " maximum allowed. Hardware has been shut down.\n",
3323 } else if (temp_state
== QLA82XX_TEMP_WARN
) {
3324 ql_log(ql_log_warn
, vha
, 0x600f,
3325 "Device temperature %d degrees C exceeds "
3326 "operating range. Immediate action needed.\n",
3332 void qla82xx_clear_pending_mbx(scsi_qla_host_t
*vha
)
3334 struct qla_hw_data
*ha
= vha
->hw
;
3336 if (ha
->flags
.mbox_busy
) {
3337 ha
->flags
.mbox_int
= 1;
3338 ha
->flags
.mbox_busy
= 0;
3339 ql_log(ql_log_warn
, vha
, 0x6010,
3340 "Doing premature completion of mbx command.\n");
3341 if (test_bit(MBX_INTR_WAIT
, &ha
->mbx_cmd_flags
))
3342 complete(&ha
->mbx_intr_comp
);
3346 void qla82xx_watchdog(scsi_qla_host_t
*vha
)
3348 uint32_t dev_state
, halt_status
;
3349 struct qla_hw_data
*ha
= vha
->hw
;
3351 /* don't poll if reset is going on */
3352 if (!ha
->flags
.nic_core_reset_hdlr_active
) {
3353 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
3354 if (qla82xx_check_temp(vha
)) {
3355 set_bit(ISP_UNRECOVERABLE
, &vha
->dpc_flags
);
3356 ha
->flags
.isp82xx_fw_hung
= 1;
3357 qla82xx_clear_pending_mbx(vha
);
3358 } else if (dev_state
== QLA8XXX_DEV_NEED_RESET
&&
3359 !test_bit(ISP_ABORT_NEEDED
, &vha
->dpc_flags
)) {
3360 ql_log(ql_log_warn
, vha
, 0x6001,
3361 "Adapter reset needed.\n");
3362 set_bit(ISP_ABORT_NEEDED
, &vha
->dpc_flags
);
3363 } else if (dev_state
== QLA8XXX_DEV_NEED_QUIESCENT
&&
3364 !test_bit(ISP_QUIESCE_NEEDED
, &vha
->dpc_flags
)) {
3365 ql_log(ql_log_warn
, vha
, 0x6002,
3366 "Quiescent needed.\n");
3367 set_bit(ISP_QUIESCE_NEEDED
, &vha
->dpc_flags
);
3368 } else if (dev_state
== QLA8XXX_DEV_FAILED
&&
3369 !test_bit(ISP_UNRECOVERABLE
, &vha
->dpc_flags
) &&
3370 vha
->flags
.online
== 1) {
3371 ql_log(ql_log_warn
, vha
, 0xb055,
3372 "Adapter state is failed. Offlining.\n");
3373 set_bit(ISP_UNRECOVERABLE
, &vha
->dpc_flags
);
3374 ha
->flags
.isp82xx_fw_hung
= 1;
3375 qla82xx_clear_pending_mbx(vha
);
3377 if (qla82xx_check_fw_alive(vha
)) {
3378 ql_dbg(ql_dbg_timer
, vha
, 0x6011,
3379 "disabling pause transmit on port 0 & 1.\n");
3380 qla82xx_wr_32(ha
, QLA82XX_CRB_NIU
+ 0x98,
3381 CRB_NIU_XG_PAUSE_CTL_P0
|CRB_NIU_XG_PAUSE_CTL_P1
);
3382 halt_status
= qla82xx_rd_32(ha
,
3383 QLA82XX_PEG_HALT_STATUS1
);
3384 ql_log(ql_log_info
, vha
, 0x6005,
3385 "dumping hw/fw registers:.\n "
3386 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n "
3387 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n "
3388 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n "
3389 " PEG_NET_4_PC: 0x%x.\n", halt_status
,
3390 qla82xx_rd_32(ha
, QLA82XX_PEG_HALT_STATUS2
),
3392 QLA82XX_CRB_PEG_NET_0
+ 0x3c),
3394 QLA82XX_CRB_PEG_NET_1
+ 0x3c),
3396 QLA82XX_CRB_PEG_NET_2
+ 0x3c),
3398 QLA82XX_CRB_PEG_NET_3
+ 0x3c),
3400 QLA82XX_CRB_PEG_NET_4
+ 0x3c));
3401 if (((halt_status
& 0x1fffff00) >> 8) == 0x67)
3402 ql_log(ql_log_warn
, vha
, 0xb052,
3403 "Firmware aborted with "
3404 "error code 0x00006700. Device is "
3406 if (halt_status
& HALT_STATUS_UNRECOVERABLE
) {
3407 set_bit(ISP_UNRECOVERABLE
,
3410 ql_log(ql_log_info
, vha
, 0x6006,
3411 "Detect abort needed.\n");
3412 set_bit(ISP_ABORT_NEEDED
,
3415 ha
->flags
.isp82xx_fw_hung
= 1;
3416 ql_log(ql_log_warn
, vha
, 0x6007, "Firmware hung.\n");
3417 qla82xx_clear_pending_mbx(vha
);
3423 int qla82xx_load_risc(scsi_qla_host_t
*vha
, uint32_t *srisc_addr
)
3426 rval
= qla82xx_device_state_handler(vha
);
3431 qla82xx_set_reset_owner(scsi_qla_host_t
*vha
)
3433 struct qla_hw_data
*ha
= vha
->hw
;
3436 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
3437 if (dev_state
== QLA8XXX_DEV_READY
) {
3438 ql_log(ql_log_info
, vha
, 0xb02f,
3439 "HW State: NEED RESET\n");
3440 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
,
3441 QLA8XXX_DEV_NEED_RESET
);
3442 ha
->flags
.nic_core_reset_owner
= 1;
3443 ql_dbg(ql_dbg_p3p
, vha
, 0xb030,
3444 "reset_owner is 0x%x\n", ha
->portnum
);
3446 ql_log(ql_log_info
, vha
, 0xb031,
3447 "Device state is 0x%x = %s.\n",
3449 dev_state
< MAX_STATES
? qdev_state(dev_state
) : "Unknown");
3454 * Resets ISP and aborts all outstanding commands.
3457 * ha = adapter block pointer.
3463 qla82xx_abort_isp(scsi_qla_host_t
*vha
)
3466 struct qla_hw_data
*ha
= vha
->hw
;
3468 if (vha
->device_flags
& DFLG_DEV_FAILED
) {
3469 ql_log(ql_log_warn
, vha
, 0x8024,
3470 "Device in failed state, exiting.\n");
3473 ha
->flags
.nic_core_reset_hdlr_active
= 1;
3475 qla82xx_idc_lock(ha
);
3476 qla82xx_set_reset_owner(vha
);
3477 qla82xx_idc_unlock(ha
);
3479 rval
= qla82xx_device_state_handler(vha
);
3481 qla82xx_idc_lock(ha
);
3482 qla82xx_clear_rst_ready(ha
);
3483 qla82xx_idc_unlock(ha
);
3485 if (rval
== QLA_SUCCESS
) {
3486 ha
->flags
.isp82xx_fw_hung
= 0;
3487 ha
->flags
.nic_core_reset_hdlr_active
= 0;
3488 qla82xx_restart_isp(vha
);
3492 vha
->flags
.online
= 1;
3493 if (test_bit(ISP_ABORT_RETRY
, &vha
->dpc_flags
)) {
3494 if (ha
->isp_abort_cnt
== 0) {
3495 ql_log(ql_log_warn
, vha
, 0x8027,
3496 "ISP error recover failed - board "
3499 * The next call disables the board
3502 ha
->isp_ops
->reset_adapter(vha
);
3503 vha
->flags
.online
= 0;
3504 clear_bit(ISP_ABORT_RETRY
,
3507 } else { /* schedule another ISP abort */
3508 ha
->isp_abort_cnt
--;
3509 ql_log(ql_log_warn
, vha
, 0x8036,
3510 "ISP abort - retry remaining %d.\n",
3512 rval
= QLA_FUNCTION_FAILED
;
3515 ha
->isp_abort_cnt
= MAX_RETRIES_OF_ISP_ABORT
;
3516 ql_dbg(ql_dbg_taskm
, vha
, 0x8029,
3517 "ISP error recovery - retrying (%d) more times.\n",
3519 set_bit(ISP_ABORT_RETRY
, &vha
->dpc_flags
);
3520 rval
= QLA_FUNCTION_FAILED
;
3527 * qla82xx_fcoe_ctx_reset
3528 * Perform a quick reset and aborts all outstanding commands.
3529 * This will only perform an FCoE context reset and avoids a full blown
3533 * ha = adapter block pointer.
3534 * is_reset_path = flag for identifying the reset path.
3539 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t
*vha
)
3541 int rval
= QLA_FUNCTION_FAILED
;
3543 if (vha
->flags
.online
) {
3544 /* Abort all outstanding commands, so as to be requeued later */
3545 qla2x00_abort_isp_cleanup(vha
);
3548 /* Stop currently executing firmware.
3549 * This will destroy existing FCoE context at the F/W end.
3551 qla2x00_try_to_stop_firmware(vha
);
3553 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3554 rval
= qla82xx_restart_isp(vha
);
3560 * qla2x00_wait_for_fcoe_ctx_reset
3561 * Wait till the FCoE context is reset.
3564 * Does context switching here.
3565 * Release SPIN_LOCK (if any) before calling this routine.
3568 * Success (fcoe_ctx reset is done) : 0
3569 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1
3571 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t
*vha
)
3573 int status
= QLA_FUNCTION_FAILED
;
3574 unsigned long wait_reset
;
3576 wait_reset
= jiffies
+ (MAX_LOOP_TIMEOUT
* HZ
);
3577 while ((test_bit(FCOE_CTX_RESET_NEEDED
, &vha
->dpc_flags
) ||
3578 test_bit(ABORT_ISP_ACTIVE
, &vha
->dpc_flags
))
3579 && time_before(jiffies
, wait_reset
)) {
3581 set_current_state(TASK_UNINTERRUPTIBLE
);
3582 schedule_timeout(HZ
);
3584 if (!test_bit(FCOE_CTX_RESET_NEEDED
, &vha
->dpc_flags
) &&
3585 !test_bit(ABORT_ISP_ACTIVE
, &vha
->dpc_flags
)) {
3586 status
= QLA_SUCCESS
;
3590 ql_dbg(ql_dbg_p3p
, vha
, 0xb027,
3591 "%s: status=%d.\n", __func__
, status
);
3597 qla82xx_chip_reset_cleanup(scsi_qla_host_t
*vha
)
3600 unsigned long flags
;
3601 struct qla_hw_data
*ha
= vha
->hw
;
3603 /* Check if 82XX firmware is alive or not
3604 * We may have arrived here from NEED_RESET
3607 if (!ha
->flags
.isp82xx_fw_hung
) {
3608 for (i
= 0; i
< 2; i
++) {
3610 if (qla82xx_check_fw_alive(vha
)) {
3611 ha
->flags
.isp82xx_fw_hung
= 1;
3612 qla82xx_clear_pending_mbx(vha
);
3617 ql_dbg(ql_dbg_init
, vha
, 0x00b0,
3618 "Entered %s fw_hung=%d.\n",
3619 __func__
, ha
->flags
.isp82xx_fw_hung
);
3621 /* Abort all commands gracefully if fw NOT hung */
3622 if (!ha
->flags
.isp82xx_fw_hung
) {
3625 struct req_que
*req
;
3627 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
3628 for (que
= 0; que
< ha
->max_req_queues
; que
++) {
3629 req
= ha
->req_q_map
[que
];
3632 for (cnt
= 1; cnt
< MAX_OUTSTANDING_COMMANDS
; cnt
++) {
3633 sp
= req
->outstanding_cmds
[cnt
];
3635 if (!sp
->u
.scmd
.ctx
||
3636 (sp
->flags
& SRB_FCP_CMND_DMA_VALID
)) {
3637 spin_unlock_irqrestore(
3638 &ha
->hardware_lock
, flags
);
3639 if (ha
->isp_ops
->abort_command(sp
)) {
3640 ql_log(ql_log_info
, vha
,
3642 "mbx abort failed.\n");
3644 ql_log(ql_log_info
, vha
,
3646 "mbx abort success.\n");
3648 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
3653 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
3655 /* Wait for pending cmds (physical and virtual) to complete */
3656 if (!qla2x00_eh_wait_for_pending_commands(vha
, 0, 0,
3657 WAIT_HOST
) == QLA_SUCCESS
) {
3658 ql_dbg(ql_dbg_init
, vha
, 0x00b3,
3660 "pending commands.\n");
3665 /* Minidump related functions */
3667 qla82xx_minidump_process_control(scsi_qla_host_t
*vha
,
3668 qla82xx_md_entry_hdr_t
*entry_hdr
, uint32_t **d_ptr
)
3670 struct qla_hw_data
*ha
= vha
->hw
;
3671 struct qla82xx_md_entry_crb
*crb_entry
;
3672 uint32_t read_value
, opcode
, poll_time
;
3673 uint32_t addr
, index
, crb_addr
;
3674 unsigned long wtime
;
3675 struct qla82xx_md_template_hdr
*tmplt_hdr
;
3676 uint32_t rval
= QLA_SUCCESS
;
3679 tmplt_hdr
= (struct qla82xx_md_template_hdr
*)ha
->md_tmplt_hdr
;
3680 crb_entry
= (struct qla82xx_md_entry_crb
*)entry_hdr
;
3681 crb_addr
= crb_entry
->addr
;
3683 for (i
= 0; i
< crb_entry
->op_count
; i
++) {
3684 opcode
= crb_entry
->crb_ctrl
.opcode
;
3685 if (opcode
& QLA82XX_DBG_OPCODE_WR
) {
3686 qla82xx_md_rw_32(ha
, crb_addr
,
3687 crb_entry
->value_1
, 1);
3688 opcode
&= ~QLA82XX_DBG_OPCODE_WR
;
3691 if (opcode
& QLA82XX_DBG_OPCODE_RW
) {
3692 read_value
= qla82xx_md_rw_32(ha
, crb_addr
, 0, 0);
3693 qla82xx_md_rw_32(ha
, crb_addr
, read_value
, 1);
3694 opcode
&= ~QLA82XX_DBG_OPCODE_RW
;
3697 if (opcode
& QLA82XX_DBG_OPCODE_AND
) {
3698 read_value
= qla82xx_md_rw_32(ha
, crb_addr
, 0, 0);
3699 read_value
&= crb_entry
->value_2
;
3700 opcode
&= ~QLA82XX_DBG_OPCODE_AND
;
3701 if (opcode
& QLA82XX_DBG_OPCODE_OR
) {
3702 read_value
|= crb_entry
->value_3
;
3703 opcode
&= ~QLA82XX_DBG_OPCODE_OR
;
3705 qla82xx_md_rw_32(ha
, crb_addr
, read_value
, 1);
3708 if (opcode
& QLA82XX_DBG_OPCODE_OR
) {
3709 read_value
= qla82xx_md_rw_32(ha
, crb_addr
, 0, 0);
3710 read_value
|= crb_entry
->value_3
;
3711 qla82xx_md_rw_32(ha
, crb_addr
, read_value
, 1);
3712 opcode
&= ~QLA82XX_DBG_OPCODE_OR
;
3715 if (opcode
& QLA82XX_DBG_OPCODE_POLL
) {
3716 poll_time
= crb_entry
->crb_strd
.poll_timeout
;
3717 wtime
= jiffies
+ poll_time
;
3718 read_value
= qla82xx_md_rw_32(ha
, crb_addr
, 0, 0);
3721 if ((read_value
& crb_entry
->value_2
)
3722 == crb_entry
->value_1
)
3724 else if (time_after_eq(jiffies
, wtime
)) {
3725 /* capturing dump failed */
3726 rval
= QLA_FUNCTION_FAILED
;
3729 read_value
= qla82xx_md_rw_32(ha
,
3732 opcode
&= ~QLA82XX_DBG_OPCODE_POLL
;
3735 if (opcode
& QLA82XX_DBG_OPCODE_RDSTATE
) {
3736 if (crb_entry
->crb_strd
.state_index_a
) {
3737 index
= crb_entry
->crb_strd
.state_index_a
;
3738 addr
= tmplt_hdr
->saved_state_array
[index
];
3742 read_value
= qla82xx_md_rw_32(ha
, addr
, 0, 0);
3743 index
= crb_entry
->crb_ctrl
.state_index_v
;
3744 tmplt_hdr
->saved_state_array
[index
] = read_value
;
3745 opcode
&= ~QLA82XX_DBG_OPCODE_RDSTATE
;
3748 if (opcode
& QLA82XX_DBG_OPCODE_WRSTATE
) {
3749 if (crb_entry
->crb_strd
.state_index_a
) {
3750 index
= crb_entry
->crb_strd
.state_index_a
;
3751 addr
= tmplt_hdr
->saved_state_array
[index
];
3755 if (crb_entry
->crb_ctrl
.state_index_v
) {
3756 index
= crb_entry
->crb_ctrl
.state_index_v
;
3758 tmplt_hdr
->saved_state_array
[index
];
3760 read_value
= crb_entry
->value_1
;
3762 qla82xx_md_rw_32(ha
, addr
, read_value
, 1);
3763 opcode
&= ~QLA82XX_DBG_OPCODE_WRSTATE
;
3766 if (opcode
& QLA82XX_DBG_OPCODE_MDSTATE
) {
3767 index
= crb_entry
->crb_ctrl
.state_index_v
;
3768 read_value
= tmplt_hdr
->saved_state_array
[index
];
3769 read_value
<<= crb_entry
->crb_ctrl
.shl
;
3770 read_value
>>= crb_entry
->crb_ctrl
.shr
;
3771 if (crb_entry
->value_2
)
3772 read_value
&= crb_entry
->value_2
;
3773 read_value
|= crb_entry
->value_3
;
3774 read_value
+= crb_entry
->value_1
;
3775 tmplt_hdr
->saved_state_array
[index
] = read_value
;
3776 opcode
&= ~QLA82XX_DBG_OPCODE_MDSTATE
;
3778 crb_addr
+= crb_entry
->crb_strd
.addr_stride
;
3784 qla82xx_minidump_process_rdocm(scsi_qla_host_t
*vha
,
3785 qla82xx_md_entry_hdr_t
*entry_hdr
, uint32_t **d_ptr
)
3787 struct qla_hw_data
*ha
= vha
->hw
;
3788 uint32_t r_addr
, r_stride
, loop_cnt
, i
, r_value
;
3789 struct qla82xx_md_entry_rdocm
*ocm_hdr
;
3790 uint32_t *data_ptr
= *d_ptr
;
3792 ocm_hdr
= (struct qla82xx_md_entry_rdocm
*)entry_hdr
;
3793 r_addr
= ocm_hdr
->read_addr
;
3794 r_stride
= ocm_hdr
->read_addr_stride
;
3795 loop_cnt
= ocm_hdr
->op_count
;
3797 for (i
= 0; i
< loop_cnt
; i
++) {
3798 r_value
= RD_REG_DWORD((void *)(r_addr
+ ha
->nx_pcibase
));
3799 *data_ptr
++ = cpu_to_le32(r_value
);
3806 qla82xx_minidump_process_rdmux(scsi_qla_host_t
*vha
,
3807 qla82xx_md_entry_hdr_t
*entry_hdr
, uint32_t **d_ptr
)
3809 struct qla_hw_data
*ha
= vha
->hw
;
3810 uint32_t r_addr
, s_stride
, s_addr
, s_value
, loop_cnt
, i
, r_value
;
3811 struct qla82xx_md_entry_mux
*mux_hdr
;
3812 uint32_t *data_ptr
= *d_ptr
;
3814 mux_hdr
= (struct qla82xx_md_entry_mux
*)entry_hdr
;
3815 r_addr
= mux_hdr
->read_addr
;
3816 s_addr
= mux_hdr
->select_addr
;
3817 s_stride
= mux_hdr
->select_value_stride
;
3818 s_value
= mux_hdr
->select_value
;
3819 loop_cnt
= mux_hdr
->op_count
;
3821 for (i
= 0; i
< loop_cnt
; i
++) {
3822 qla82xx_md_rw_32(ha
, s_addr
, s_value
, 1);
3823 r_value
= qla82xx_md_rw_32(ha
, r_addr
, 0, 0);
3824 *data_ptr
++ = cpu_to_le32(s_value
);
3825 *data_ptr
++ = cpu_to_le32(r_value
);
3826 s_value
+= s_stride
;
3832 qla82xx_minidump_process_rdcrb(scsi_qla_host_t
*vha
,
3833 qla82xx_md_entry_hdr_t
*entry_hdr
, uint32_t **d_ptr
)
3835 struct qla_hw_data
*ha
= vha
->hw
;
3836 uint32_t r_addr
, r_stride
, loop_cnt
, i
, r_value
;
3837 struct qla82xx_md_entry_crb
*crb_hdr
;
3838 uint32_t *data_ptr
= *d_ptr
;
3840 crb_hdr
= (struct qla82xx_md_entry_crb
*)entry_hdr
;
3841 r_addr
= crb_hdr
->addr
;
3842 r_stride
= crb_hdr
->crb_strd
.addr_stride
;
3843 loop_cnt
= crb_hdr
->op_count
;
3845 for (i
= 0; i
< loop_cnt
; i
++) {
3846 r_value
= qla82xx_md_rw_32(ha
, r_addr
, 0, 0);
3847 *data_ptr
++ = cpu_to_le32(r_addr
);
3848 *data_ptr
++ = cpu_to_le32(r_value
);
3855 qla82xx_minidump_process_l2tag(scsi_qla_host_t
*vha
,
3856 qla82xx_md_entry_hdr_t
*entry_hdr
, uint32_t **d_ptr
)
3858 struct qla_hw_data
*ha
= vha
->hw
;
3859 uint32_t addr
, r_addr
, c_addr
, t_r_addr
;
3860 uint32_t i
, k
, loop_count
, t_value
, r_cnt
, r_value
;
3861 unsigned long p_wait
, w_time
, p_mask
;
3862 uint32_t c_value_w
, c_value_r
;
3863 struct qla82xx_md_entry_cache
*cache_hdr
;
3864 int rval
= QLA_FUNCTION_FAILED
;
3865 uint32_t *data_ptr
= *d_ptr
;
3867 cache_hdr
= (struct qla82xx_md_entry_cache
*)entry_hdr
;
3868 loop_count
= cache_hdr
->op_count
;
3869 r_addr
= cache_hdr
->read_addr
;
3870 c_addr
= cache_hdr
->control_addr
;
3871 c_value_w
= cache_hdr
->cache_ctrl
.write_value
;
3873 t_r_addr
= cache_hdr
->tag_reg_addr
;
3874 t_value
= cache_hdr
->addr_ctrl
.init_tag_value
;
3875 r_cnt
= cache_hdr
->read_ctrl
.read_addr_cnt
;
3876 p_wait
= cache_hdr
->cache_ctrl
.poll_wait
;
3877 p_mask
= cache_hdr
->cache_ctrl
.poll_mask
;
3879 for (i
= 0; i
< loop_count
; i
++) {
3880 qla82xx_md_rw_32(ha
, t_r_addr
, t_value
, 1);
3882 qla82xx_md_rw_32(ha
, c_addr
, c_value_w
, 1);
3885 w_time
= jiffies
+ p_wait
;
3887 c_value_r
= qla82xx_md_rw_32(ha
, c_addr
, 0, 0);
3888 if ((c_value_r
& p_mask
) == 0)
3890 else if (time_after_eq(jiffies
, w_time
)) {
3891 /* capturing dump failed */
3892 ql_dbg(ql_dbg_p3p
, vha
, 0xb032,
3893 "c_value_r: 0x%x, poll_mask: 0x%lx, "
3895 c_value_r
, p_mask
, w_time
);
3902 for (k
= 0; k
< r_cnt
; k
++) {
3903 r_value
= qla82xx_md_rw_32(ha
, addr
, 0, 0);
3904 *data_ptr
++ = cpu_to_le32(r_value
);
3905 addr
+= cache_hdr
->read_ctrl
.read_addr_stride
;
3907 t_value
+= cache_hdr
->addr_ctrl
.tag_value_stride
;
3914 qla82xx_minidump_process_l1cache(scsi_qla_host_t
*vha
,
3915 qla82xx_md_entry_hdr_t
*entry_hdr
, uint32_t **d_ptr
)
3917 struct qla_hw_data
*ha
= vha
->hw
;
3918 uint32_t addr
, r_addr
, c_addr
, t_r_addr
;
3919 uint32_t i
, k
, loop_count
, t_value
, r_cnt
, r_value
;
3921 struct qla82xx_md_entry_cache
*cache_hdr
;
3922 uint32_t *data_ptr
= *d_ptr
;
3924 cache_hdr
= (struct qla82xx_md_entry_cache
*)entry_hdr
;
3925 loop_count
= cache_hdr
->op_count
;
3926 r_addr
= cache_hdr
->read_addr
;
3927 c_addr
= cache_hdr
->control_addr
;
3928 c_value_w
= cache_hdr
->cache_ctrl
.write_value
;
3930 t_r_addr
= cache_hdr
->tag_reg_addr
;
3931 t_value
= cache_hdr
->addr_ctrl
.init_tag_value
;
3932 r_cnt
= cache_hdr
->read_ctrl
.read_addr_cnt
;
3934 for (i
= 0; i
< loop_count
; i
++) {
3935 qla82xx_md_rw_32(ha
, t_r_addr
, t_value
, 1);
3936 qla82xx_md_rw_32(ha
, c_addr
, c_value_w
, 1);
3938 for (k
= 0; k
< r_cnt
; k
++) {
3939 r_value
= qla82xx_md_rw_32(ha
, addr
, 0, 0);
3940 *data_ptr
++ = cpu_to_le32(r_value
);
3941 addr
+= cache_hdr
->read_ctrl
.read_addr_stride
;
3943 t_value
+= cache_hdr
->addr_ctrl
.tag_value_stride
;
3949 qla82xx_minidump_process_queue(scsi_qla_host_t
*vha
,
3950 qla82xx_md_entry_hdr_t
*entry_hdr
, uint32_t **d_ptr
)
3952 struct qla_hw_data
*ha
= vha
->hw
;
3953 uint32_t s_addr
, r_addr
;
3954 uint32_t r_stride
, r_value
, r_cnt
, qid
= 0;
3955 uint32_t i
, k
, loop_cnt
;
3956 struct qla82xx_md_entry_queue
*q_hdr
;
3957 uint32_t *data_ptr
= *d_ptr
;
3959 q_hdr
= (struct qla82xx_md_entry_queue
*)entry_hdr
;
3960 s_addr
= q_hdr
->select_addr
;
3961 r_cnt
= q_hdr
->rd_strd
.read_addr_cnt
;
3962 r_stride
= q_hdr
->rd_strd
.read_addr_stride
;
3963 loop_cnt
= q_hdr
->op_count
;
3965 for (i
= 0; i
< loop_cnt
; i
++) {
3966 qla82xx_md_rw_32(ha
, s_addr
, qid
, 1);
3967 r_addr
= q_hdr
->read_addr
;
3968 for (k
= 0; k
< r_cnt
; k
++) {
3969 r_value
= qla82xx_md_rw_32(ha
, r_addr
, 0, 0);
3970 *data_ptr
++ = cpu_to_le32(r_value
);
3973 qid
+= q_hdr
->q_strd
.queue_id_stride
;
3979 qla82xx_minidump_process_rdrom(scsi_qla_host_t
*vha
,
3980 qla82xx_md_entry_hdr_t
*entry_hdr
, uint32_t **d_ptr
)
3982 struct qla_hw_data
*ha
= vha
->hw
;
3983 uint32_t r_addr
, r_value
;
3984 uint32_t i
, loop_cnt
;
3985 struct qla82xx_md_entry_rdrom
*rom_hdr
;
3986 uint32_t *data_ptr
= *d_ptr
;
3988 rom_hdr
= (struct qla82xx_md_entry_rdrom
*)entry_hdr
;
3989 r_addr
= rom_hdr
->read_addr
;
3990 loop_cnt
= rom_hdr
->read_data_size
/sizeof(uint32_t);
3992 for (i
= 0; i
< loop_cnt
; i
++) {
3993 qla82xx_md_rw_32(ha
, MD_DIRECT_ROM_WINDOW
,
3994 (r_addr
& 0xFFFF0000), 1);
3995 r_value
= qla82xx_md_rw_32(ha
,
3996 MD_DIRECT_ROM_READ_BASE
+
3997 (r_addr
& 0x0000FFFF), 0, 0);
3998 *data_ptr
++ = cpu_to_le32(r_value
);
3999 r_addr
+= sizeof(uint32_t);
4005 qla82xx_minidump_process_rdmem(scsi_qla_host_t
*vha
,
4006 qla82xx_md_entry_hdr_t
*entry_hdr
, uint32_t **d_ptr
)
4008 struct qla_hw_data
*ha
= vha
->hw
;
4009 uint32_t r_addr
, r_value
, r_data
;
4010 uint32_t i
, j
, loop_cnt
;
4011 struct qla82xx_md_entry_rdmem
*m_hdr
;
4012 unsigned long flags
;
4013 int rval
= QLA_FUNCTION_FAILED
;
4014 uint32_t *data_ptr
= *d_ptr
;
4016 m_hdr
= (struct qla82xx_md_entry_rdmem
*)entry_hdr
;
4017 r_addr
= m_hdr
->read_addr
;
4018 loop_cnt
= m_hdr
->read_data_size
/16;
4021 ql_log(ql_log_warn
, vha
, 0xb033,
4022 "Read addr 0x%x not 16 bytes aligned\n", r_addr
);
4026 if (m_hdr
->read_data_size
% 16) {
4027 ql_log(ql_log_warn
, vha
, 0xb034,
4028 "Read data[0x%x] not multiple of 16 bytes\n",
4029 m_hdr
->read_data_size
);
4033 ql_dbg(ql_dbg_p3p
, vha
, 0xb035,
4034 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
4035 __func__
, r_addr
, m_hdr
->read_data_size
, loop_cnt
);
4037 write_lock_irqsave(&ha
->hw_lock
, flags
);
4038 for (i
= 0; i
< loop_cnt
; i
++) {
4039 qla82xx_md_rw_32(ha
, MD_MIU_TEST_AGT_ADDR_LO
, r_addr
, 1);
4041 qla82xx_md_rw_32(ha
, MD_MIU_TEST_AGT_ADDR_HI
, r_value
, 1);
4042 r_value
= MIU_TA_CTL_ENABLE
;
4043 qla82xx_md_rw_32(ha
, MD_MIU_TEST_AGT_CTRL
, r_value
, 1);
4044 r_value
= MIU_TA_CTL_START
| MIU_TA_CTL_ENABLE
;
4045 qla82xx_md_rw_32(ha
, MD_MIU_TEST_AGT_CTRL
, r_value
, 1);
4047 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
4048 r_value
= qla82xx_md_rw_32(ha
,
4049 MD_MIU_TEST_AGT_CTRL
, 0, 0);
4050 if ((r_value
& MIU_TA_CTL_BUSY
) == 0)
4054 if (j
>= MAX_CTL_CHECK
) {
4055 printk_ratelimited(KERN_ERR
4056 "failed to read through agent\n");
4057 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
4061 for (j
= 0; j
< 4; j
++) {
4062 r_data
= qla82xx_md_rw_32(ha
,
4063 MD_MIU_TEST_AGT_RDDATA
[j
], 0, 0);
4064 *data_ptr
++ = cpu_to_le32(r_data
);
4068 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
4074 qla82xx_validate_template_chksum(scsi_qla_host_t
*vha
)
4076 struct qla_hw_data
*ha
= vha
->hw
;
4077 uint64_t chksum
= 0;
4078 uint32_t *d_ptr
= (uint32_t *)ha
->md_tmplt_hdr
;
4079 int count
= ha
->md_template_size
/sizeof(uint32_t);
4083 while (chksum
>> 32)
4084 chksum
= (chksum
& 0xFFFFFFFF) + (chksum
>> 32);
4089 qla82xx_mark_entry_skipped(scsi_qla_host_t
*vha
,
4090 qla82xx_md_entry_hdr_t
*entry_hdr
, int index
)
4092 entry_hdr
->d_ctrl
.driver_flags
|= QLA82XX_DBG_SKIPPED_FLAG
;
4093 ql_dbg(ql_dbg_p3p
, vha
, 0xb036,
4094 "Skipping entry[%d]: "
4095 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4096 index
, entry_hdr
->entry_type
,
4097 entry_hdr
->d_ctrl
.entry_capture_mask
);
4101 qla82xx_md_collect(scsi_qla_host_t
*vha
)
4103 struct qla_hw_data
*ha
= vha
->hw
;
4104 int no_entry_hdr
= 0;
4105 qla82xx_md_entry_hdr_t
*entry_hdr
;
4106 struct qla82xx_md_template_hdr
*tmplt_hdr
;
4108 uint32_t total_data_size
= 0, f_capture_mask
, data_collected
= 0;
4109 int i
= 0, rval
= QLA_FUNCTION_FAILED
;
4111 tmplt_hdr
= (struct qla82xx_md_template_hdr
*)ha
->md_tmplt_hdr
;
4112 data_ptr
= (uint32_t *)ha
->md_dump
;
4114 if (ha
->fw_dumped
) {
4115 ql_log(ql_log_warn
, vha
, 0xb037,
4116 "Firmware has been previously dumped (%p) "
4117 "-- ignoring request.\n", ha
->fw_dump
);
4123 if (!ha
->md_tmplt_hdr
|| !ha
->md_dump
) {
4124 ql_log(ql_log_warn
, vha
, 0xb038,
4125 "Memory not allocated for minidump capture\n");
4129 if (ha
->flags
.isp82xx_no_md_cap
) {
4130 ql_log(ql_log_warn
, vha
, 0xb054,
4131 "Forced reset from application, "
4132 "ignore minidump capture\n");
4133 ha
->flags
.isp82xx_no_md_cap
= 0;
4137 if (qla82xx_validate_template_chksum(vha
)) {
4138 ql_log(ql_log_info
, vha
, 0xb039,
4139 "Template checksum validation error\n");
4143 no_entry_hdr
= tmplt_hdr
->num_of_entries
;
4144 ql_dbg(ql_dbg_p3p
, vha
, 0xb03a,
4145 "No of entry headers in Template: 0x%x\n", no_entry_hdr
);
4147 ql_dbg(ql_dbg_p3p
, vha
, 0xb03b,
4148 "Capture Mask obtained: 0x%x\n", tmplt_hdr
->capture_debug_level
);
4150 f_capture_mask
= tmplt_hdr
->capture_debug_level
& 0xFF;
4152 /* Validate whether required debug level is set */
4153 if ((f_capture_mask
& 0x3) != 0x3) {
4154 ql_log(ql_log_warn
, vha
, 0xb03c,
4155 "Minimum required capture mask[0x%x] level not set\n",
4159 tmplt_hdr
->driver_capture_mask
= ql2xmdcapmask
;
4161 tmplt_hdr
->driver_info
[0] = vha
->host_no
;
4162 tmplt_hdr
->driver_info
[1] = (QLA_DRIVER_MAJOR_VER
<< 24) |
4163 (QLA_DRIVER_MINOR_VER
<< 16) | (QLA_DRIVER_PATCH_VER
<< 8) |
4164 QLA_DRIVER_BETA_VER
;
4166 total_data_size
= ha
->md_dump_size
;
4168 ql_dbg(ql_dbg_p3p
, vha
, 0xb03d,
4169 "Total minidump data_size 0x%x to be captured\n", total_data_size
);
4171 /* Check whether template obtained is valid */
4172 if (tmplt_hdr
->entry_type
!= QLA82XX_TLHDR
) {
4173 ql_log(ql_log_warn
, vha
, 0xb04e,
4174 "Bad template header entry type: 0x%x obtained\n",
4175 tmplt_hdr
->entry_type
);
4179 entry_hdr
= (qla82xx_md_entry_hdr_t
*) \
4180 (((uint8_t *)ha
->md_tmplt_hdr
) + tmplt_hdr
->first_entry_offset
);
4182 /* Walk through the entry headers */
4183 for (i
= 0; i
< no_entry_hdr
; i
++) {
4185 if (data_collected
> total_data_size
) {
4186 ql_log(ql_log_warn
, vha
, 0xb03e,
4187 "More MiniDump data collected: [0x%x]\n",
4192 if (!(entry_hdr
->d_ctrl
.entry_capture_mask
&
4194 entry_hdr
->d_ctrl
.driver_flags
|=
4195 QLA82XX_DBG_SKIPPED_FLAG
;
4196 ql_dbg(ql_dbg_p3p
, vha
, 0xb03f,
4197 "Skipping entry[%d]: "
4198 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4199 i
, entry_hdr
->entry_type
,
4200 entry_hdr
->d_ctrl
.entry_capture_mask
);
4201 goto skip_nxt_entry
;
4204 ql_dbg(ql_dbg_p3p
, vha
, 0xb040,
4205 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n"
4206 "entry_type: 0x%x, captrue_mask: 0x%x\n",
4207 __func__
, i
, data_ptr
, entry_hdr
,
4208 entry_hdr
->entry_type
,
4209 entry_hdr
->d_ctrl
.entry_capture_mask
);
4211 ql_dbg(ql_dbg_p3p
, vha
, 0xb041,
4212 "Data collected: [0x%x], Dump size left:[0x%x]\n",
4213 data_collected
, (ha
->md_dump_size
- data_collected
));
4215 /* Decode the entry type and take
4216 * required action to capture debug data */
4217 switch (entry_hdr
->entry_type
) {
4219 qla82xx_mark_entry_skipped(vha
, entry_hdr
, i
);
4222 rval
= qla82xx_minidump_process_control(vha
,
4223 entry_hdr
, &data_ptr
);
4224 if (rval
!= QLA_SUCCESS
) {
4225 qla82xx_mark_entry_skipped(vha
, entry_hdr
, i
);
4230 qla82xx_minidump_process_rdcrb(vha
,
4231 entry_hdr
, &data_ptr
);
4234 rval
= qla82xx_minidump_process_rdmem(vha
,
4235 entry_hdr
, &data_ptr
);
4236 if (rval
!= QLA_SUCCESS
) {
4237 qla82xx_mark_entry_skipped(vha
, entry_hdr
, i
);
4243 qla82xx_minidump_process_rdrom(vha
,
4244 entry_hdr
, &data_ptr
);
4250 rval
= qla82xx_minidump_process_l2tag(vha
,
4251 entry_hdr
, &data_ptr
);
4252 if (rval
!= QLA_SUCCESS
) {
4253 qla82xx_mark_entry_skipped(vha
, entry_hdr
, i
);
4259 qla82xx_minidump_process_l1cache(vha
,
4260 entry_hdr
, &data_ptr
);
4263 qla82xx_minidump_process_rdocm(vha
,
4264 entry_hdr
, &data_ptr
);
4267 qla82xx_minidump_process_rdmux(vha
,
4268 entry_hdr
, &data_ptr
);
4271 qla82xx_minidump_process_queue(vha
,
4272 entry_hdr
, &data_ptr
);
4276 qla82xx_mark_entry_skipped(vha
, entry_hdr
, i
);
4280 ql_dbg(ql_dbg_p3p
, vha
, 0xb042,
4281 "[%s]: data ptr[%d]: %p\n", __func__
, i
, data_ptr
);
4283 data_collected
= (uint8_t *)data_ptr
-
4284 (uint8_t *)ha
->md_dump
;
4286 entry_hdr
= (qla82xx_md_entry_hdr_t
*) \
4287 (((uint8_t *)entry_hdr
) + entry_hdr
->entry_size
);
4290 if (data_collected
!= total_data_size
) {
4291 ql_dbg(ql_dbg_p3p
, vha
, 0xb043,
4292 "MiniDump data mismatch: Data collected: [0x%x],"
4293 "total_data_size:[0x%x]\n",
4294 data_collected
, total_data_size
);
4298 ql_log(ql_log_info
, vha
, 0xb044,
4299 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
4300 vha
->host_no
, ha
->md_tmplt_hdr
, vha
->host_no
, ha
->md_dump
);
4302 qla2x00_post_uevent_work(vha
, QLA_UEVENT_CODE_FW_DUMP
);
4309 qla82xx_md_alloc(scsi_qla_host_t
*vha
)
4311 struct qla_hw_data
*ha
= vha
->hw
;
4313 struct qla82xx_md_template_hdr
*tmplt_hdr
;
4315 tmplt_hdr
= (struct qla82xx_md_template_hdr
*)ha
->md_tmplt_hdr
;
4317 if (ql2xmdcapmask
< 0x3 || ql2xmdcapmask
> 0x7F) {
4318 ql2xmdcapmask
= tmplt_hdr
->capture_debug_level
& 0xFF;
4319 ql_log(ql_log_info
, vha
, 0xb045,
4320 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n",
4324 for (i
= 0x2, k
= 1; (i
& QLA82XX_DEFAULT_CAP_MASK
); i
<<= 1, k
++) {
4325 if (i
& ql2xmdcapmask
)
4326 ha
->md_dump_size
+= tmplt_hdr
->capture_size_array
[k
];
4330 ql_log(ql_log_warn
, vha
, 0xb046,
4331 "Firmware dump previously allocated.\n");
4335 ha
->md_dump
= vmalloc(ha
->md_dump_size
);
4336 if (ha
->md_dump
== NULL
) {
4337 ql_log(ql_log_warn
, vha
, 0xb047,
4338 "Unable to allocate memory for Minidump size "
4339 "(0x%x).\n", ha
->md_dump_size
);
4346 qla82xx_md_free(scsi_qla_host_t
*vha
)
4348 struct qla_hw_data
*ha
= vha
->hw
;
4350 /* Release the template header allocated */
4351 if (ha
->md_tmplt_hdr
) {
4352 ql_log(ql_log_info
, vha
, 0xb048,
4353 "Free MiniDump template: %p, size (%d KB)\n",
4354 ha
->md_tmplt_hdr
, ha
->md_template_size
/ 1024);
4355 dma_free_coherent(&ha
->pdev
->dev
, ha
->md_template_size
,
4356 ha
->md_tmplt_hdr
, ha
->md_tmplt_hdr_dma
);
4357 ha
->md_tmplt_hdr
= 0;
4360 /* Release the template data buffer allocated */
4362 ql_log(ql_log_info
, vha
, 0xb049,
4363 "Free MiniDump memory: %p, size (%d KB)\n",
4364 ha
->md_dump
, ha
->md_dump_size
/ 1024);
4366 ha
->md_dump_size
= 0;
4372 qla82xx_md_prep(scsi_qla_host_t
*vha
)
4374 struct qla_hw_data
*ha
= vha
->hw
;
4377 /* Get Minidump template size */
4378 rval
= qla82xx_md_get_template_size(vha
);
4379 if (rval
== QLA_SUCCESS
) {
4380 ql_log(ql_log_info
, vha
, 0xb04a,
4381 "MiniDump Template size obtained (%d KB)\n",
4382 ha
->md_template_size
/ 1024);
4384 /* Get Minidump template */
4385 rval
= qla82xx_md_get_template(vha
);
4386 if (rval
== QLA_SUCCESS
) {
4387 ql_dbg(ql_dbg_p3p
, vha
, 0xb04b,
4388 "MiniDump Template obtained\n");
4390 /* Allocate memory for minidump */
4391 rval
= qla82xx_md_alloc(vha
);
4392 if (rval
== QLA_SUCCESS
)
4393 ql_log(ql_log_info
, vha
, 0xb04c,
4394 "MiniDump memory allocated (%d KB)\n",
4395 ha
->md_dump_size
/ 1024);
4397 ql_log(ql_log_info
, vha
, 0xb04d,
4398 "Free MiniDump template: %p, size: (%d KB)\n",
4400 ha
->md_template_size
/ 1024);
4401 dma_free_coherent(&ha
->pdev
->dev
,
4402 ha
->md_template_size
,
4403 ha
->md_tmplt_hdr
, ha
->md_tmplt_hdr_dma
);
4404 ha
->md_tmplt_hdr
= 0;
4412 qla82xx_beacon_on(struct scsi_qla_host
*vha
)
4416 struct qla_hw_data
*ha
= vha
->hw
;
4417 qla82xx_idc_lock(ha
);
4418 rval
= qla82xx_mbx_beacon_ctl(vha
, 1);
4421 ql_log(ql_log_warn
, vha
, 0xb050,
4422 "mbx set led config failed in %s\n", __func__
);
4425 ha
->beacon_blink_led
= 1;
4427 qla82xx_idc_unlock(ha
);
4432 qla82xx_beacon_off(struct scsi_qla_host
*vha
)
4436 struct qla_hw_data
*ha
= vha
->hw
;
4437 qla82xx_idc_lock(ha
);
4438 rval
= qla82xx_mbx_beacon_ctl(vha
, 0);
4441 ql_log(ql_log_warn
, vha
, 0xb051,
4442 "mbx set led config failed in %s\n", __func__
);
4445 ha
->beacon_blink_led
= 0;
4447 qla82xx_idc_unlock(ha
);