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qla2xxx: Add module parameter alternate/short names.
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_os.c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <scsi/scsi_tcq.h>
17 #include <scsi/scsicam.h>
18 #include <scsi/scsi_transport.h>
19 #include <scsi/scsi_transport_fc.h>
20
21 #include "qla_target.h"
22
23 /*
24 * Driver version
25 */
26 char qla2x00_version_str[40];
27
28 static int apidev_major;
29
30 /*
31 * SRB allocation cache
32 */
33 static struct kmem_cache *srb_cachep;
34
35 /*
36 * CT6 CTX allocation cache
37 */
38 static struct kmem_cache *ctx_cachep;
39 /*
40 * error level for logging
41 */
42 int ql_errlev = ql_log_all;
43
44 static int ql2xenableclass2;
45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46 MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
50
51 int ql2xlogintimeout = 20;
52 module_param(ql2xlogintimeout, int, S_IRUGO);
53 MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
56 int qlport_down_retry;
57 module_param(qlport_down_retry, int, S_IRUGO);
58 MODULE_PARM_DESC(qlport_down_retry,
59 "Maximum number of command retries to a port that returns "
60 "a PORT-DOWN status.");
61
62 int ql2xplogiabsentdevice;
63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64 MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
66 "a Fabric scan. This is needed for several broken switches. "
67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
69 int ql2xloginretrycount = 0;
70 module_param(ql2xloginretrycount, int, S_IRUGO);
71 MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
74 int ql2xallocfwdump = 1;
75 module_param(ql2xallocfwdump, int, S_IRUGO);
76 MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
81 int ql2xextended_error_logging;
82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
83 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
84 MODULE_PARM_DESC(ql2xextended_error_logging,
85 "Option to enable extended error logging,\n"
86 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
87 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
88 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
89 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
90 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
91 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
92 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
93 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
94 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
95 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
96 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
97 "\t\t0x1e400000 - Preferred value for capturing essential "
98 "debug information (equivalent to old "
99 "ql2xextended_error_logging=1).\n"
100 "\t\tDo LOGICAL OR of the value to enable more than one level");
101
102 int ql2xshiftctondsd = 6;
103 module_param(ql2xshiftctondsd, int, S_IRUGO);
104 MODULE_PARM_DESC(ql2xshiftctondsd,
105 "Set to control shifting of command type processing "
106 "based on total number of SG elements.");
107
108 int ql2xfdmienable=1;
109 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
110 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
111 MODULE_PARM_DESC(ql2xfdmienable,
112 "Enables FDMI registrations. "
113 "0 - no FDMI. Default is 1 - perform FDMI.");
114
115 #define MAX_Q_DEPTH 32
116 static int ql2xmaxqdepth = MAX_Q_DEPTH;
117 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
118 MODULE_PARM_DESC(ql2xmaxqdepth,
119 "Maximum queue depth to set for each LUN. "
120 "Default is 32.");
121
122 int ql2xenabledif = 2;
123 module_param(ql2xenabledif, int, S_IRUGO);
124 MODULE_PARM_DESC(ql2xenabledif,
125 " Enable T10-CRC-DIF:\n"
126 " Default is 2.\n"
127 " 0 -- No DIF Support\n"
128 " 1 -- Enable DIF for all types\n"
129 " 2 -- Enable DIF for all types, except Type 0.\n");
130
131 int ql2xenablehba_err_chk = 2;
132 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
133 MODULE_PARM_DESC(ql2xenablehba_err_chk,
134 " Enable T10-CRC-DIF Error isolation by HBA:\n"
135 " Default is 2.\n"
136 " 0 -- Error isolation disabled\n"
137 " 1 -- Error isolation enabled only for DIX Type 0\n"
138 " 2 -- Error isolation enabled for all Types\n");
139
140 int ql2xiidmaenable=1;
141 module_param(ql2xiidmaenable, int, S_IRUGO);
142 MODULE_PARM_DESC(ql2xiidmaenable,
143 "Enables iIDMA settings "
144 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
145
146 int ql2xmaxqueues = 1;
147 module_param(ql2xmaxqueues, int, S_IRUGO);
148 MODULE_PARM_DESC(ql2xmaxqueues,
149 "Enables MQ settings "
150 "Default is 1 for single queue. Set it to number "
151 "of queues in MQ mode.");
152
153 int ql2xmultique_tag;
154 module_param(ql2xmultique_tag, int, S_IRUGO);
155 MODULE_PARM_DESC(ql2xmultique_tag,
156 "Enables CPU affinity settings for the driver "
157 "Default is 0 for no affinity of request and response IO. "
158 "Set it to 1 to turn on the cpu affinity.");
159
160 int ql2xfwloadbin;
161 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
162 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
163 MODULE_PARM_DESC(ql2xfwloadbin,
164 "Option to specify location from which to load ISP firmware:.\n"
165 " 2 -- load firmware via the request_firmware() (hotplug).\n"
166 " interface.\n"
167 " 1 -- load firmware from flash.\n"
168 " 0 -- use default semantics.\n");
169
170 int ql2xetsenable;
171 module_param(ql2xetsenable, int, S_IRUGO);
172 MODULE_PARM_DESC(ql2xetsenable,
173 "Enables firmware ETS burst."
174 "Default is 0 - skip ETS enablement.");
175
176 int ql2xdbwr = 1;
177 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
178 MODULE_PARM_DESC(ql2xdbwr,
179 "Option to specify scheme for request queue posting.\n"
180 " 0 -- Regular doorbell.\n"
181 " 1 -- CAMRAM doorbell (faster).\n");
182
183 int ql2xtargetreset = 1;
184 module_param(ql2xtargetreset, int, S_IRUGO);
185 MODULE_PARM_DESC(ql2xtargetreset,
186 "Enable target reset."
187 "Default is 1 - use hw defaults.");
188
189 int ql2xgffidenable;
190 module_param(ql2xgffidenable, int, S_IRUGO);
191 MODULE_PARM_DESC(ql2xgffidenable,
192 "Enables GFF_ID checks of port type. "
193 "Default is 0 - Do not use GFF_ID information.");
194
195 int ql2xasynctmfenable;
196 module_param(ql2xasynctmfenable, int, S_IRUGO);
197 MODULE_PARM_DESC(ql2xasynctmfenable,
198 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
199 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
200
201 int ql2xdontresethba;
202 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
203 MODULE_PARM_DESC(ql2xdontresethba,
204 "Option to specify reset behaviour.\n"
205 " 0 (Default) -- Reset on failure.\n"
206 " 1 -- Do not reset on failure.\n");
207
208 uint64_t ql2xmaxlun = MAX_LUNS;
209 module_param(ql2xmaxlun, ullong, S_IRUGO);
210 MODULE_PARM_DESC(ql2xmaxlun,
211 "Defines the maximum LU number to register with the SCSI "
212 "midlayer. Default is 65535.");
213
214 int ql2xmdcapmask = 0x1F;
215 module_param(ql2xmdcapmask, int, S_IRUGO);
216 MODULE_PARM_DESC(ql2xmdcapmask,
217 "Set the Minidump driver capture mask level. "
218 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
219
220 int ql2xmdenable = 1;
221 module_param(ql2xmdenable, int, S_IRUGO);
222 MODULE_PARM_DESC(ql2xmdenable,
223 "Enable/disable MiniDump. "
224 "0 - MiniDump disabled. "
225 "1 (Default) - MiniDump enabled.");
226
227 int ql2xexlogins = 0;
228 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
229 MODULE_PARM_DESC(ql2xexlogins,
230 "Number of extended Logins. "
231 "0 (Default)- Disabled.");
232
233 int ql2xexchoffld = 0;
234 module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR);
235 MODULE_PARM_DESC(ql2xexchoffld,
236 "Number of exchanges to offload. "
237 "0 (Default)- Disabled.");
238
239 int ql2xfwholdabts = 0;
240 module_param(ql2xfwholdabts, int, S_IRUGO);
241 MODULE_PARM_DESC(ql2xfwholdabts,
242 "Allow FW to hold status IOCB until ABTS rsp received. "
243 "0 (Default) Do not set fw option. "
244 "1 - Set fw option to hold ABTS.");
245
246 /*
247 * SCSI host template entry points
248 */
249 static int qla2xxx_slave_configure(struct scsi_device * device);
250 static int qla2xxx_slave_alloc(struct scsi_device *);
251 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
252 static void qla2xxx_scan_start(struct Scsi_Host *);
253 static void qla2xxx_slave_destroy(struct scsi_device *);
254 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
255 static int qla2xxx_eh_abort(struct scsi_cmnd *);
256 static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
257 static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
258 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
259 static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
260
261 static void qla2x00_clear_drv_active(struct qla_hw_data *);
262 static void qla2x00_free_device(scsi_qla_host_t *);
263 static void qla83xx_disable_laser(scsi_qla_host_t *vha);
264
265 struct scsi_host_template qla2xxx_driver_template = {
266 .module = THIS_MODULE,
267 .name = QLA2XXX_DRIVER_NAME,
268 .queuecommand = qla2xxx_queuecommand,
269
270 .eh_abort_handler = qla2xxx_eh_abort,
271 .eh_device_reset_handler = qla2xxx_eh_device_reset,
272 .eh_target_reset_handler = qla2xxx_eh_target_reset,
273 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
274 .eh_host_reset_handler = qla2xxx_eh_host_reset,
275
276 .slave_configure = qla2xxx_slave_configure,
277
278 .slave_alloc = qla2xxx_slave_alloc,
279 .slave_destroy = qla2xxx_slave_destroy,
280 .scan_finished = qla2xxx_scan_finished,
281 .scan_start = qla2xxx_scan_start,
282 .change_queue_depth = scsi_change_queue_depth,
283 .this_id = -1,
284 .cmd_per_lun = 3,
285 .use_clustering = ENABLE_CLUSTERING,
286 .sg_tablesize = SG_ALL,
287
288 .max_sectors = 0xFFFF,
289 .shost_attrs = qla2x00_host_attrs,
290
291 .supported_mode = MODE_INITIATOR,
292 .track_queue_depth = 1,
293 };
294
295 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
296 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
297
298 /* TODO Convert to inlines
299 *
300 * Timer routines
301 */
302
303 __inline__ void
304 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
305 {
306 init_timer(&vha->timer);
307 vha->timer.expires = jiffies + interval * HZ;
308 vha->timer.data = (unsigned long)vha;
309 vha->timer.function = (void (*)(unsigned long))func;
310 add_timer(&vha->timer);
311 vha->timer_active = 1;
312 }
313
314 static inline void
315 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
316 {
317 /* Currently used for 82XX only. */
318 if (vha->device_flags & DFLG_DEV_FAILED) {
319 ql_dbg(ql_dbg_timer, vha, 0x600d,
320 "Device in a failed state, returning.\n");
321 return;
322 }
323
324 mod_timer(&vha->timer, jiffies + interval * HZ);
325 }
326
327 static __inline__ void
328 qla2x00_stop_timer(scsi_qla_host_t *vha)
329 {
330 del_timer_sync(&vha->timer);
331 vha->timer_active = 0;
332 }
333
334 static int qla2x00_do_dpc(void *data);
335
336 static void qla2x00_rst_aen(scsi_qla_host_t *);
337
338 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
339 struct req_que **, struct rsp_que **);
340 static void qla2x00_free_fw_dump(struct qla_hw_data *);
341 static void qla2x00_mem_free(struct qla_hw_data *);
342
343 /* -------------------------------------------------------------------------- */
344 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
345 struct rsp_que *rsp)
346 {
347 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
348 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
349 GFP_KERNEL);
350 if (!ha->req_q_map) {
351 ql_log(ql_log_fatal, vha, 0x003b,
352 "Unable to allocate memory for request queue ptrs.\n");
353 goto fail_req_map;
354 }
355
356 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
357 GFP_KERNEL);
358 if (!ha->rsp_q_map) {
359 ql_log(ql_log_fatal, vha, 0x003c,
360 "Unable to allocate memory for response queue ptrs.\n");
361 goto fail_rsp_map;
362 }
363 /*
364 * Make sure we record at least the request and response queue zero in
365 * case we need to free them if part of the probe fails.
366 */
367 ha->rsp_q_map[0] = rsp;
368 ha->req_q_map[0] = req;
369 set_bit(0, ha->rsp_qid_map);
370 set_bit(0, ha->req_qid_map);
371 return 1;
372
373 fail_rsp_map:
374 kfree(ha->req_q_map);
375 ha->req_q_map = NULL;
376 fail_req_map:
377 return -ENOMEM;
378 }
379
380 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
381 {
382 if (IS_QLAFX00(ha)) {
383 if (req && req->ring_fx00)
384 dma_free_coherent(&ha->pdev->dev,
385 (req->length_fx00 + 1) * sizeof(request_t),
386 req->ring_fx00, req->dma_fx00);
387 } else if (req && req->ring)
388 dma_free_coherent(&ha->pdev->dev,
389 (req->length + 1) * sizeof(request_t),
390 req->ring, req->dma);
391
392 if (req)
393 kfree(req->outstanding_cmds);
394
395 kfree(req);
396 req = NULL;
397 }
398
399 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
400 {
401 if (IS_QLAFX00(ha)) {
402 if (rsp && rsp->ring)
403 dma_free_coherent(&ha->pdev->dev,
404 (rsp->length_fx00 + 1) * sizeof(request_t),
405 rsp->ring_fx00, rsp->dma_fx00);
406 } else if (rsp && rsp->ring) {
407 dma_free_coherent(&ha->pdev->dev,
408 (rsp->length + 1) * sizeof(response_t),
409 rsp->ring, rsp->dma);
410 }
411 kfree(rsp);
412 rsp = NULL;
413 }
414
415 static void qla2x00_free_queues(struct qla_hw_data *ha)
416 {
417 struct req_que *req;
418 struct rsp_que *rsp;
419 int cnt;
420
421 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
422 if (!test_bit(cnt, ha->req_qid_map))
423 continue;
424
425 req = ha->req_q_map[cnt];
426 qla2x00_free_req_que(ha, req);
427 }
428 kfree(ha->req_q_map);
429 ha->req_q_map = NULL;
430
431 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
432 if (!test_bit(cnt, ha->rsp_qid_map))
433 continue;
434
435 rsp = ha->rsp_q_map[cnt];
436 qla2x00_free_rsp_que(ha, rsp);
437 }
438 kfree(ha->rsp_q_map);
439 ha->rsp_q_map = NULL;
440 }
441
442 static int qla25xx_setup_mode(struct scsi_qla_host *vha)
443 {
444 uint16_t options = 0;
445 int ques, req, ret;
446 struct qla_hw_data *ha = vha->hw;
447
448 if (!(ha->fw_attributes & BIT_6)) {
449 ql_log(ql_log_warn, vha, 0x00d8,
450 "Firmware is not multi-queue capable.\n");
451 goto fail;
452 }
453 if (ql2xmultique_tag) {
454 /* create a request queue for IO */
455 options |= BIT_7;
456 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
457 QLA_DEFAULT_QUE_QOS);
458 if (!req) {
459 ql_log(ql_log_warn, vha, 0x00e0,
460 "Failed to create request queue.\n");
461 goto fail;
462 }
463 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
464 vha->req = ha->req_q_map[req];
465 options |= BIT_1;
466 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
467 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
468 if (!ret) {
469 ql_log(ql_log_warn, vha, 0x00e8,
470 "Failed to create response queue.\n");
471 goto fail2;
472 }
473 }
474 ha->flags.cpu_affinity_enabled = 1;
475 ql_dbg(ql_dbg_multiq, vha, 0xc007,
476 "CPU affinity mode enabled, "
477 "no. of response queues:%d no. of request queues:%d.\n",
478 ha->max_rsp_queues, ha->max_req_queues);
479 ql_dbg(ql_dbg_init, vha, 0x00e9,
480 "CPU affinity mode enabled, "
481 "no. of response queues:%d no. of request queues:%d.\n",
482 ha->max_rsp_queues, ha->max_req_queues);
483 }
484 return 0;
485 fail2:
486 qla25xx_delete_queues(vha);
487 destroy_workqueue(ha->wq);
488 ha->wq = NULL;
489 vha->req = ha->req_q_map[0];
490 fail:
491 ha->mqenable = 0;
492 kfree(ha->req_q_map);
493 kfree(ha->rsp_q_map);
494 ha->max_req_queues = ha->max_rsp_queues = 1;
495 return 1;
496 }
497
498 static char *
499 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
500 {
501 struct qla_hw_data *ha = vha->hw;
502 static char *pci_bus_modes[] = {
503 "33", "66", "100", "133",
504 };
505 uint16_t pci_bus;
506
507 strcpy(str, "PCI");
508 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
509 if (pci_bus) {
510 strcat(str, "-X (");
511 strcat(str, pci_bus_modes[pci_bus]);
512 } else {
513 pci_bus = (ha->pci_attr & BIT_8) >> 8;
514 strcat(str, " (");
515 strcat(str, pci_bus_modes[pci_bus]);
516 }
517 strcat(str, " MHz)");
518
519 return (str);
520 }
521
522 static char *
523 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
524 {
525 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
526 struct qla_hw_data *ha = vha->hw;
527 uint32_t pci_bus;
528
529 if (pci_is_pcie(ha->pdev)) {
530 char lwstr[6];
531 uint32_t lstat, lspeed, lwidth;
532
533 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
534 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
535 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
536
537 strcpy(str, "PCIe (");
538 switch (lspeed) {
539 case 1:
540 strcat(str, "2.5GT/s ");
541 break;
542 case 2:
543 strcat(str, "5.0GT/s ");
544 break;
545 case 3:
546 strcat(str, "8.0GT/s ");
547 break;
548 default:
549 strcat(str, "<unknown> ");
550 break;
551 }
552 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
553 strcat(str, lwstr);
554
555 return str;
556 }
557
558 strcpy(str, "PCI");
559 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
560 if (pci_bus == 0 || pci_bus == 8) {
561 strcat(str, " (");
562 strcat(str, pci_bus_modes[pci_bus >> 3]);
563 } else {
564 strcat(str, "-X ");
565 if (pci_bus & BIT_2)
566 strcat(str, "Mode 2");
567 else
568 strcat(str, "Mode 1");
569 strcat(str, " (");
570 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
571 }
572 strcat(str, " MHz)");
573
574 return str;
575 }
576
577 static char *
578 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
579 {
580 char un_str[10];
581 struct qla_hw_data *ha = vha->hw;
582
583 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
584 ha->fw_minor_version, ha->fw_subminor_version);
585
586 if (ha->fw_attributes & BIT_9) {
587 strcat(str, "FLX");
588 return (str);
589 }
590
591 switch (ha->fw_attributes & 0xFF) {
592 case 0x7:
593 strcat(str, "EF");
594 break;
595 case 0x17:
596 strcat(str, "TP");
597 break;
598 case 0x37:
599 strcat(str, "IP");
600 break;
601 case 0x77:
602 strcat(str, "VI");
603 break;
604 default:
605 sprintf(un_str, "(%x)", ha->fw_attributes);
606 strcat(str, un_str);
607 break;
608 }
609 if (ha->fw_attributes & 0x100)
610 strcat(str, "X");
611
612 return (str);
613 }
614
615 static char *
616 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
617 {
618 struct qla_hw_data *ha = vha->hw;
619
620 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
621 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
622 return str;
623 }
624
625 void
626 qla2x00_sp_free_dma(void *vha, void *ptr)
627 {
628 srb_t *sp = (srb_t *)ptr;
629 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
630 struct qla_hw_data *ha = sp->fcport->vha->hw;
631 void *ctx = GET_CMD_CTX_SP(sp);
632
633 if (sp->flags & SRB_DMA_VALID) {
634 scsi_dma_unmap(cmd);
635 sp->flags &= ~SRB_DMA_VALID;
636 }
637
638 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
639 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
640 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
641 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
642 }
643
644 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
645 /* List assured to be having elements */
646 qla2x00_clean_dsd_pool(ha, sp, NULL);
647 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
648 }
649
650 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
651 dma_pool_free(ha->dl_dma_pool, ctx,
652 ((struct crc_context *)ctx)->crc_ctx_dma);
653 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
654 }
655
656 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
657 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
658
659 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
660 ctx1->fcp_cmnd_dma);
661 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
662 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
663 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
664 mempool_free(ctx1, ha->ctx_mempool);
665 ctx1 = NULL;
666 }
667
668 CMD_SP(cmd) = NULL;
669 qla2x00_rel_sp(sp->fcport->vha, sp);
670 }
671
672 static void
673 qla2x00_sp_compl(void *data, void *ptr, int res)
674 {
675 struct qla_hw_data *ha = (struct qla_hw_data *)data;
676 srb_t *sp = (srb_t *)ptr;
677 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
678
679 cmd->result = res;
680
681 if (atomic_read(&sp->ref_count) == 0) {
682 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
683 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
684 sp, GET_CMD_SP(sp));
685 if (ql2xextended_error_logging & ql_dbg_io)
686 WARN_ON(atomic_read(&sp->ref_count) == 0);
687 return;
688 }
689 if (!atomic_dec_and_test(&sp->ref_count))
690 return;
691
692 qla2x00_sp_free_dma(ha, sp);
693 cmd->scsi_done(cmd);
694 }
695
696 /* If we are SP1 here, we need to still take and release the host_lock as SP1
697 * does not have the changes necessary to avoid taking host->host_lock.
698 */
699 static int
700 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
701 {
702 scsi_qla_host_t *vha = shost_priv(host);
703 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
704 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
705 struct qla_hw_data *ha = vha->hw;
706 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
707 srb_t *sp;
708 int rval;
709
710 if (ha->flags.eeh_busy) {
711 if (ha->flags.pci_channel_io_perm_failure) {
712 ql_dbg(ql_dbg_aer, vha, 0x9010,
713 "PCI Channel IO permanent failure, exiting "
714 "cmd=%p.\n", cmd);
715 cmd->result = DID_NO_CONNECT << 16;
716 } else {
717 ql_dbg(ql_dbg_aer, vha, 0x9011,
718 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
719 cmd->result = DID_REQUEUE << 16;
720 }
721 goto qc24_fail_command;
722 }
723
724 rval = fc_remote_port_chkready(rport);
725 if (rval) {
726 cmd->result = rval;
727 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
728 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
729 cmd, rval);
730 goto qc24_fail_command;
731 }
732
733 if (!vha->flags.difdix_supported &&
734 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
735 ql_dbg(ql_dbg_io, vha, 0x3004,
736 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
737 cmd);
738 cmd->result = DID_NO_CONNECT << 16;
739 goto qc24_fail_command;
740 }
741
742 if (!fcport) {
743 cmd->result = DID_NO_CONNECT << 16;
744 goto qc24_fail_command;
745 }
746
747 if (atomic_read(&fcport->state) != FCS_ONLINE) {
748 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
749 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
750 ql_dbg(ql_dbg_io, vha, 0x3005,
751 "Returning DNC, fcport_state=%d loop_state=%d.\n",
752 atomic_read(&fcport->state),
753 atomic_read(&base_vha->loop_state));
754 cmd->result = DID_NO_CONNECT << 16;
755 goto qc24_fail_command;
756 }
757 goto qc24_target_busy;
758 }
759
760 /*
761 * Return target busy if we've received a non-zero retry_delay_timer
762 * in a FCP_RSP.
763 */
764 if (fcport->retry_delay_timestamp == 0) {
765 /* retry delay not set */
766 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
767 fcport->retry_delay_timestamp = 0;
768 else
769 goto qc24_target_busy;
770
771 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
772 if (!sp)
773 goto qc24_host_busy;
774
775 sp->u.scmd.cmd = cmd;
776 sp->type = SRB_SCSI_CMD;
777 atomic_set(&sp->ref_count, 1);
778 CMD_SP(cmd) = (void *)sp;
779 sp->free = qla2x00_sp_free_dma;
780 sp->done = qla2x00_sp_compl;
781
782 rval = ha->isp_ops->start_scsi(sp);
783 if (rval != QLA_SUCCESS) {
784 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
785 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
786 goto qc24_host_busy_free_sp;
787 }
788
789 return 0;
790
791 qc24_host_busy_free_sp:
792 qla2x00_sp_free_dma(ha, sp);
793
794 qc24_host_busy:
795 return SCSI_MLQUEUE_HOST_BUSY;
796
797 qc24_target_busy:
798 return SCSI_MLQUEUE_TARGET_BUSY;
799
800 qc24_fail_command:
801 cmd->scsi_done(cmd);
802
803 return 0;
804 }
805
806 /*
807 * qla2x00_eh_wait_on_command
808 * Waits for the command to be returned by the Firmware for some
809 * max time.
810 *
811 * Input:
812 * cmd = Scsi Command to wait on.
813 *
814 * Return:
815 * Not Found : 0
816 * Found : 1
817 */
818 static int
819 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
820 {
821 #define ABORT_POLLING_PERIOD 1000
822 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
823 unsigned long wait_iter = ABORT_WAIT_ITER;
824 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
825 struct qla_hw_data *ha = vha->hw;
826 int ret = QLA_SUCCESS;
827
828 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
829 ql_dbg(ql_dbg_taskm, vha, 0x8005,
830 "Return:eh_wait.\n");
831 return ret;
832 }
833
834 while (CMD_SP(cmd) && wait_iter--) {
835 msleep(ABORT_POLLING_PERIOD);
836 }
837 if (CMD_SP(cmd))
838 ret = QLA_FUNCTION_FAILED;
839
840 return ret;
841 }
842
843 /*
844 * qla2x00_wait_for_hba_online
845 * Wait till the HBA is online after going through
846 * <= MAX_RETRIES_OF_ISP_ABORT or
847 * finally HBA is disabled ie marked offline
848 *
849 * Input:
850 * ha - pointer to host adapter structure
851 *
852 * Note:
853 * Does context switching-Release SPIN_LOCK
854 * (if any) before calling this routine.
855 *
856 * Return:
857 * Success (Adapter is online) : 0
858 * Failed (Adapter is offline/disabled) : 1
859 */
860 int
861 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
862 {
863 int return_status;
864 unsigned long wait_online;
865 struct qla_hw_data *ha = vha->hw;
866 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
867
868 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
869 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
870 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
871 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
872 ha->dpc_active) && time_before(jiffies, wait_online)) {
873
874 msleep(1000);
875 }
876 if (base_vha->flags.online)
877 return_status = QLA_SUCCESS;
878 else
879 return_status = QLA_FUNCTION_FAILED;
880
881 return (return_status);
882 }
883
884 /*
885 * qla2x00_wait_for_hba_ready
886 * Wait till the HBA is ready before doing driver unload
887 *
888 * Input:
889 * ha - pointer to host adapter structure
890 *
891 * Note:
892 * Does context switching-Release SPIN_LOCK
893 * (if any) before calling this routine.
894 *
895 */
896 static void
897 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
898 {
899 struct qla_hw_data *ha = vha->hw;
900
901 while (((qla2x00_reset_active(vha)) || ha->dpc_active ||
902 ha->flags.mbox_busy) ||
903 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
904 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags))
905 msleep(1000);
906 }
907
908 int
909 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
910 {
911 int return_status;
912 unsigned long wait_reset;
913 struct qla_hw_data *ha = vha->hw;
914 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
915
916 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
917 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
918 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
919 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
920 ha->dpc_active) && time_before(jiffies, wait_reset)) {
921
922 msleep(1000);
923
924 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
925 ha->flags.chip_reset_done)
926 break;
927 }
928 if (ha->flags.chip_reset_done)
929 return_status = QLA_SUCCESS;
930 else
931 return_status = QLA_FUNCTION_FAILED;
932
933 return return_status;
934 }
935
936 static void
937 sp_get(struct srb *sp)
938 {
939 atomic_inc(&sp->ref_count);
940 }
941
942 /**************************************************************************
943 * qla2xxx_eh_abort
944 *
945 * Description:
946 * The abort function will abort the specified command.
947 *
948 * Input:
949 * cmd = Linux SCSI command packet to be aborted.
950 *
951 * Returns:
952 * Either SUCCESS or FAILED.
953 *
954 * Note:
955 * Only return FAILED if command not returned by firmware.
956 **************************************************************************/
957 static int
958 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
959 {
960 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
961 srb_t *sp;
962 int ret;
963 unsigned int id;
964 uint64_t lun;
965 unsigned long flags;
966 int rval, wait = 0;
967 struct qla_hw_data *ha = vha->hw;
968
969 if (!CMD_SP(cmd))
970 return SUCCESS;
971
972 ret = fc_block_scsi_eh(cmd);
973 if (ret != 0)
974 return ret;
975 ret = SUCCESS;
976
977 id = cmd->device->id;
978 lun = cmd->device->lun;
979
980 spin_lock_irqsave(&ha->hardware_lock, flags);
981 sp = (srb_t *) CMD_SP(cmd);
982 if (!sp) {
983 spin_unlock_irqrestore(&ha->hardware_lock, flags);
984 return SUCCESS;
985 }
986
987 ql_dbg(ql_dbg_taskm, vha, 0x8002,
988 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
989 vha->host_no, id, lun, sp, cmd, sp->handle);
990
991 /* Get a reference to the sp and drop the lock.*/
992 sp_get(sp);
993
994 spin_unlock_irqrestore(&ha->hardware_lock, flags);
995 rval = ha->isp_ops->abort_command(sp);
996 if (rval) {
997 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
998 ret = SUCCESS;
999 else
1000 ret = FAILED;
1001
1002 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1003 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
1004 } else {
1005 ql_dbg(ql_dbg_taskm, vha, 0x8004,
1006 "Abort command mbx success cmd=%p.\n", cmd);
1007 wait = 1;
1008 }
1009
1010 spin_lock_irqsave(&ha->hardware_lock, flags);
1011 sp->done(ha, sp, 0);
1012 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1013
1014 /* Did the command return during mailbox execution? */
1015 if (ret == FAILED && !CMD_SP(cmd))
1016 ret = SUCCESS;
1017
1018 /* Wait for the command to be returned. */
1019 if (wait) {
1020 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
1021 ql_log(ql_log_warn, vha, 0x8006,
1022 "Abort handler timed out cmd=%p.\n", cmd);
1023 ret = FAILED;
1024 }
1025 }
1026
1027 ql_log(ql_log_info, vha, 0x801c,
1028 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
1029 vha->host_no, id, lun, wait, ret);
1030
1031 return ret;
1032 }
1033
1034 int
1035 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1036 uint64_t l, enum nexus_wait_type type)
1037 {
1038 int cnt, match, status;
1039 unsigned long flags;
1040 struct qla_hw_data *ha = vha->hw;
1041 struct req_que *req;
1042 srb_t *sp;
1043 struct scsi_cmnd *cmd;
1044
1045 status = QLA_SUCCESS;
1046
1047 spin_lock_irqsave(&ha->hardware_lock, flags);
1048 req = vha->req;
1049 for (cnt = 1; status == QLA_SUCCESS &&
1050 cnt < req->num_outstanding_cmds; cnt++) {
1051 sp = req->outstanding_cmds[cnt];
1052 if (!sp)
1053 continue;
1054 if (sp->type != SRB_SCSI_CMD)
1055 continue;
1056 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1057 continue;
1058 match = 0;
1059 cmd = GET_CMD_SP(sp);
1060 switch (type) {
1061 case WAIT_HOST:
1062 match = 1;
1063 break;
1064 case WAIT_TARGET:
1065 match = cmd->device->id == t;
1066 break;
1067 case WAIT_LUN:
1068 match = (cmd->device->id == t &&
1069 cmd->device->lun == l);
1070 break;
1071 }
1072 if (!match)
1073 continue;
1074
1075 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1076 status = qla2x00_eh_wait_on_command(cmd);
1077 spin_lock_irqsave(&ha->hardware_lock, flags);
1078 }
1079 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1080
1081 return status;
1082 }
1083
1084 static char *reset_errors[] = {
1085 "HBA not online",
1086 "HBA not ready",
1087 "Task management failed",
1088 "Waiting for command completions",
1089 };
1090
1091 static int
1092 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1093 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1094 {
1095 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1096 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1097 int err;
1098
1099 if (!fcport) {
1100 return FAILED;
1101 }
1102
1103 err = fc_block_scsi_eh(cmd);
1104 if (err != 0)
1105 return err;
1106
1107 ql_log(ql_log_info, vha, 0x8009,
1108 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
1109 cmd->device->id, cmd->device->lun, cmd);
1110
1111 err = 0;
1112 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1113 ql_log(ql_log_warn, vha, 0x800a,
1114 "Wait for hba online failed for cmd=%p.\n", cmd);
1115 goto eh_reset_failed;
1116 }
1117 err = 2;
1118 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
1119 != QLA_SUCCESS) {
1120 ql_log(ql_log_warn, vha, 0x800c,
1121 "do_reset failed for cmd=%p.\n", cmd);
1122 goto eh_reset_failed;
1123 }
1124 err = 3;
1125 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1126 cmd->device->lun, type) != QLA_SUCCESS) {
1127 ql_log(ql_log_warn, vha, 0x800d,
1128 "wait for pending cmds failed for cmd=%p.\n", cmd);
1129 goto eh_reset_failed;
1130 }
1131
1132 ql_log(ql_log_info, vha, 0x800e,
1133 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
1134 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1135
1136 return SUCCESS;
1137
1138 eh_reset_failed:
1139 ql_log(ql_log_info, vha, 0x800f,
1140 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
1141 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1142 cmd);
1143 return FAILED;
1144 }
1145
1146 static int
1147 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1148 {
1149 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1150 struct qla_hw_data *ha = vha->hw;
1151
1152 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1153 ha->isp_ops->lun_reset);
1154 }
1155
1156 static int
1157 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1158 {
1159 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1160 struct qla_hw_data *ha = vha->hw;
1161
1162 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1163 ha->isp_ops->target_reset);
1164 }
1165
1166 /**************************************************************************
1167 * qla2xxx_eh_bus_reset
1168 *
1169 * Description:
1170 * The bus reset function will reset the bus and abort any executing
1171 * commands.
1172 *
1173 * Input:
1174 * cmd = Linux SCSI command packet of the command that cause the
1175 * bus reset.
1176 *
1177 * Returns:
1178 * SUCCESS/FAILURE (defined as macro in scsi.h).
1179 *
1180 **************************************************************************/
1181 static int
1182 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1183 {
1184 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1185 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1186 int ret = FAILED;
1187 unsigned int id;
1188 uint64_t lun;
1189
1190 id = cmd->device->id;
1191 lun = cmd->device->lun;
1192
1193 if (!fcport) {
1194 return ret;
1195 }
1196
1197 ret = fc_block_scsi_eh(cmd);
1198 if (ret != 0)
1199 return ret;
1200 ret = FAILED;
1201
1202 ql_log(ql_log_info, vha, 0x8012,
1203 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1204
1205 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1206 ql_log(ql_log_fatal, vha, 0x8013,
1207 "Wait for hba online failed board disabled.\n");
1208 goto eh_bus_reset_done;
1209 }
1210
1211 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1212 ret = SUCCESS;
1213
1214 if (ret == FAILED)
1215 goto eh_bus_reset_done;
1216
1217 /* Flush outstanding commands. */
1218 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1219 QLA_SUCCESS) {
1220 ql_log(ql_log_warn, vha, 0x8014,
1221 "Wait for pending commands failed.\n");
1222 ret = FAILED;
1223 }
1224
1225 eh_bus_reset_done:
1226 ql_log(ql_log_warn, vha, 0x802b,
1227 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1228 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1229
1230 return ret;
1231 }
1232
1233 /**************************************************************************
1234 * qla2xxx_eh_host_reset
1235 *
1236 * Description:
1237 * The reset function will reset the Adapter.
1238 *
1239 * Input:
1240 * cmd = Linux SCSI command packet of the command that cause the
1241 * adapter reset.
1242 *
1243 * Returns:
1244 * Either SUCCESS or FAILED.
1245 *
1246 * Note:
1247 **************************************************************************/
1248 static int
1249 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1250 {
1251 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1252 struct qla_hw_data *ha = vha->hw;
1253 int ret = FAILED;
1254 unsigned int id;
1255 uint64_t lun;
1256 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1257
1258 id = cmd->device->id;
1259 lun = cmd->device->lun;
1260
1261 ql_log(ql_log_info, vha, 0x8018,
1262 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1263
1264 /*
1265 * No point in issuing another reset if one is active. Also do not
1266 * attempt a reset if we are updating flash.
1267 */
1268 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1269 goto eh_host_reset_lock;
1270
1271 if (vha != base_vha) {
1272 if (qla2x00_vp_abort_isp(vha))
1273 goto eh_host_reset_lock;
1274 } else {
1275 if (IS_P3P_TYPE(vha->hw)) {
1276 if (!qla82xx_fcoe_ctx_reset(vha)) {
1277 /* Ctx reset success */
1278 ret = SUCCESS;
1279 goto eh_host_reset_lock;
1280 }
1281 /* fall thru if ctx reset failed */
1282 }
1283 if (ha->wq)
1284 flush_workqueue(ha->wq);
1285
1286 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1287 if (ha->isp_ops->abort_isp(base_vha)) {
1288 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1289 /* failed. schedule dpc to try */
1290 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1291
1292 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1293 ql_log(ql_log_warn, vha, 0x802a,
1294 "wait for hba online failed.\n");
1295 goto eh_host_reset_lock;
1296 }
1297 }
1298 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1299 }
1300
1301 /* Waiting for command to be returned to OS.*/
1302 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1303 QLA_SUCCESS)
1304 ret = SUCCESS;
1305
1306 eh_host_reset_lock:
1307 ql_log(ql_log_info, vha, 0x8017,
1308 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1309 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1310
1311 return ret;
1312 }
1313
1314 /*
1315 * qla2x00_loop_reset
1316 * Issue loop reset.
1317 *
1318 * Input:
1319 * ha = adapter block pointer.
1320 *
1321 * Returns:
1322 * 0 = success
1323 */
1324 int
1325 qla2x00_loop_reset(scsi_qla_host_t *vha)
1326 {
1327 int ret;
1328 struct fc_port *fcport;
1329 struct qla_hw_data *ha = vha->hw;
1330
1331 if (IS_QLAFX00(ha)) {
1332 return qlafx00_loop_reset(vha);
1333 }
1334
1335 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1336 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1337 if (fcport->port_type != FCT_TARGET)
1338 continue;
1339
1340 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1341 if (ret != QLA_SUCCESS) {
1342 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1343 "Bus Reset failed: Reset=%d "
1344 "d_id=%x.\n", ret, fcport->d_id.b24);
1345 }
1346 }
1347 }
1348
1349
1350 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1351 atomic_set(&vha->loop_state, LOOP_DOWN);
1352 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1353 qla2x00_mark_all_devices_lost(vha, 0);
1354 ret = qla2x00_full_login_lip(vha);
1355 if (ret != QLA_SUCCESS) {
1356 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1357 "full_login_lip=%d.\n", ret);
1358 }
1359 }
1360
1361 if (ha->flags.enable_lip_reset) {
1362 ret = qla2x00_lip_reset(vha);
1363 if (ret != QLA_SUCCESS)
1364 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1365 "lip_reset failed (%d).\n", ret);
1366 }
1367
1368 /* Issue marker command only when we are going to start the I/O */
1369 vha->marker_needed = 1;
1370
1371 return QLA_SUCCESS;
1372 }
1373
1374 void
1375 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1376 {
1377 int que, cnt;
1378 unsigned long flags;
1379 srb_t *sp;
1380 struct qla_hw_data *ha = vha->hw;
1381 struct req_que *req;
1382
1383 qlt_host_reset_handler(ha);
1384
1385 spin_lock_irqsave(&ha->hardware_lock, flags);
1386 for (que = 0; que < ha->max_req_queues; que++) {
1387 req = ha->req_q_map[que];
1388 if (!req)
1389 continue;
1390 if (!req->outstanding_cmds)
1391 continue;
1392 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1393 sp = req->outstanding_cmds[cnt];
1394 if (sp) {
1395 req->outstanding_cmds[cnt] = NULL;
1396 sp->done(vha, sp, res);
1397 }
1398 }
1399 }
1400 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1401 }
1402
1403 static int
1404 qla2xxx_slave_alloc(struct scsi_device *sdev)
1405 {
1406 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1407
1408 if (!rport || fc_remote_port_chkready(rport))
1409 return -ENXIO;
1410
1411 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1412
1413 return 0;
1414 }
1415
1416 static int
1417 qla2xxx_slave_configure(struct scsi_device *sdev)
1418 {
1419 scsi_qla_host_t *vha = shost_priv(sdev->host);
1420 struct req_que *req = vha->req;
1421
1422 if (IS_T10_PI_CAPABLE(vha->hw))
1423 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1424
1425 scsi_change_queue_depth(sdev, req->max_q_depth);
1426 return 0;
1427 }
1428
1429 static void
1430 qla2xxx_slave_destroy(struct scsi_device *sdev)
1431 {
1432 sdev->hostdata = NULL;
1433 }
1434
1435 /**
1436 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1437 * @ha: HA context
1438 *
1439 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1440 * supported addressing method.
1441 */
1442 static void
1443 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1444 {
1445 /* Assume a 32bit DMA mask. */
1446 ha->flags.enable_64bit_addressing = 0;
1447
1448 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1449 /* Any upper-dword bits set? */
1450 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1451 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1452 /* Ok, a 64bit DMA mask is applicable. */
1453 ha->flags.enable_64bit_addressing = 1;
1454 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1455 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1456 return;
1457 }
1458 }
1459
1460 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1461 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1462 }
1463
1464 static void
1465 qla2x00_enable_intrs(struct qla_hw_data *ha)
1466 {
1467 unsigned long flags = 0;
1468 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1469
1470 spin_lock_irqsave(&ha->hardware_lock, flags);
1471 ha->interrupts_on = 1;
1472 /* enable risc and host interrupts */
1473 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1474 RD_REG_WORD(&reg->ictrl);
1475 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1476
1477 }
1478
1479 static void
1480 qla2x00_disable_intrs(struct qla_hw_data *ha)
1481 {
1482 unsigned long flags = 0;
1483 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1484
1485 spin_lock_irqsave(&ha->hardware_lock, flags);
1486 ha->interrupts_on = 0;
1487 /* disable risc and host interrupts */
1488 WRT_REG_WORD(&reg->ictrl, 0);
1489 RD_REG_WORD(&reg->ictrl);
1490 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1491 }
1492
1493 static void
1494 qla24xx_enable_intrs(struct qla_hw_data *ha)
1495 {
1496 unsigned long flags = 0;
1497 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1498
1499 spin_lock_irqsave(&ha->hardware_lock, flags);
1500 ha->interrupts_on = 1;
1501 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1502 RD_REG_DWORD(&reg->ictrl);
1503 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1504 }
1505
1506 static void
1507 qla24xx_disable_intrs(struct qla_hw_data *ha)
1508 {
1509 unsigned long flags = 0;
1510 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1511
1512 if (IS_NOPOLLING_TYPE(ha))
1513 return;
1514 spin_lock_irqsave(&ha->hardware_lock, flags);
1515 ha->interrupts_on = 0;
1516 WRT_REG_DWORD(&reg->ictrl, 0);
1517 RD_REG_DWORD(&reg->ictrl);
1518 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1519 }
1520
1521 static int
1522 qla2x00_iospace_config(struct qla_hw_data *ha)
1523 {
1524 resource_size_t pio;
1525 uint16_t msix;
1526 int cpus;
1527
1528 if (pci_request_selected_regions(ha->pdev, ha->bars,
1529 QLA2XXX_DRIVER_NAME)) {
1530 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1531 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1532 pci_name(ha->pdev));
1533 goto iospace_error_exit;
1534 }
1535 if (!(ha->bars & 1))
1536 goto skip_pio;
1537
1538 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1539 pio = pci_resource_start(ha->pdev, 0);
1540 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1541 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1542 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1543 "Invalid pci I/O region size (%s).\n",
1544 pci_name(ha->pdev));
1545 pio = 0;
1546 }
1547 } else {
1548 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1549 "Region #0 no a PIO resource (%s).\n",
1550 pci_name(ha->pdev));
1551 pio = 0;
1552 }
1553 ha->pio_address = pio;
1554 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1555 "PIO address=%llu.\n",
1556 (unsigned long long)ha->pio_address);
1557
1558 skip_pio:
1559 /* Use MMIO operations for all accesses. */
1560 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1561 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1562 "Region #1 not an MMIO resource (%s), aborting.\n",
1563 pci_name(ha->pdev));
1564 goto iospace_error_exit;
1565 }
1566 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1567 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1568 "Invalid PCI mem region size (%s), aborting.\n",
1569 pci_name(ha->pdev));
1570 goto iospace_error_exit;
1571 }
1572
1573 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1574 if (!ha->iobase) {
1575 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1576 "Cannot remap MMIO (%s), aborting.\n",
1577 pci_name(ha->pdev));
1578 goto iospace_error_exit;
1579 }
1580
1581 /* Determine queue resources */
1582 ha->max_req_queues = ha->max_rsp_queues = 1;
1583 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1584 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1585 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1586 goto mqiobase_exit;
1587
1588 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1589 pci_resource_len(ha->pdev, 3));
1590 if (ha->mqiobase) {
1591 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1592 "MQIO Base=%p.\n", ha->mqiobase);
1593 /* Read MSIX vector size of the board */
1594 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1595 ha->msix_count = msix;
1596 /* Max queues are bounded by available msix vectors */
1597 /* queue 0 uses two msix vectors */
1598 if (ql2xmultique_tag) {
1599 cpus = num_online_cpus();
1600 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1601 (cpus + 1) : (ha->msix_count - 1);
1602 ha->max_req_queues = 2;
1603 } else if (ql2xmaxqueues > 1) {
1604 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1605 QLA_MQ_SIZE : ql2xmaxqueues;
1606 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1607 "QoS mode set, max no of request queues:%d.\n",
1608 ha->max_req_queues);
1609 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1610 "QoS mode set, max no of request queues:%d.\n",
1611 ha->max_req_queues);
1612 }
1613 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1614 "MSI-X vector count: %d.\n", msix);
1615 } else
1616 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1617 "BAR 3 not enabled.\n");
1618
1619 mqiobase_exit:
1620 ha->msix_count = ha->max_rsp_queues + 1;
1621 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1622 "MSIX Count:%d.\n", ha->msix_count);
1623 return (0);
1624
1625 iospace_error_exit:
1626 return (-ENOMEM);
1627 }
1628
1629
1630 static int
1631 qla83xx_iospace_config(struct qla_hw_data *ha)
1632 {
1633 uint16_t msix;
1634 int cpus;
1635
1636 if (pci_request_selected_regions(ha->pdev, ha->bars,
1637 QLA2XXX_DRIVER_NAME)) {
1638 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1639 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1640 pci_name(ha->pdev));
1641
1642 goto iospace_error_exit;
1643 }
1644
1645 /* Use MMIO operations for all accesses. */
1646 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1647 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1648 "Invalid pci I/O region size (%s).\n",
1649 pci_name(ha->pdev));
1650 goto iospace_error_exit;
1651 }
1652 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1653 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1654 "Invalid PCI mem region size (%s), aborting\n",
1655 pci_name(ha->pdev));
1656 goto iospace_error_exit;
1657 }
1658
1659 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1660 if (!ha->iobase) {
1661 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1662 "Cannot remap MMIO (%s), aborting.\n",
1663 pci_name(ha->pdev));
1664 goto iospace_error_exit;
1665 }
1666
1667 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1668 /* 83XX 26XX always use MQ type access for queues
1669 * - mbar 2, a.k.a region 4 */
1670 ha->max_req_queues = ha->max_rsp_queues = 1;
1671 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1672 pci_resource_len(ha->pdev, 4));
1673
1674 if (!ha->mqiobase) {
1675 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1676 "BAR2/region4 not enabled\n");
1677 goto mqiobase_exit;
1678 }
1679
1680 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1681 pci_resource_len(ha->pdev, 2));
1682 if (ha->msixbase) {
1683 /* Read MSIX vector size of the board */
1684 pci_read_config_word(ha->pdev,
1685 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1686 ha->msix_count = msix;
1687 /* Max queues are bounded by available msix vectors */
1688 /* queue 0 uses two msix vectors */
1689 if (ql2xmultique_tag) {
1690 cpus = num_online_cpus();
1691 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1692 (cpus + 1) : (ha->msix_count - 1);
1693 ha->max_req_queues = 2;
1694 } else if (ql2xmaxqueues > 1) {
1695 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1696 QLA_MQ_SIZE : ql2xmaxqueues;
1697 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1698 "QoS mode set, max no of request queues:%d.\n",
1699 ha->max_req_queues);
1700 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1701 "QoS mode set, max no of request queues:%d.\n",
1702 ha->max_req_queues);
1703 }
1704 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1705 "MSI-X vector count: %d.\n", msix);
1706 } else
1707 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1708 "BAR 1 not enabled.\n");
1709
1710 mqiobase_exit:
1711 ha->msix_count = ha->max_rsp_queues + 1;
1712
1713 qlt_83xx_iospace_config(ha);
1714
1715 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1716 "MSIX Count:%d.\n", ha->msix_count);
1717 return 0;
1718
1719 iospace_error_exit:
1720 return -ENOMEM;
1721 }
1722
1723 static struct isp_operations qla2100_isp_ops = {
1724 .pci_config = qla2100_pci_config,
1725 .reset_chip = qla2x00_reset_chip,
1726 .chip_diag = qla2x00_chip_diag,
1727 .config_rings = qla2x00_config_rings,
1728 .reset_adapter = qla2x00_reset_adapter,
1729 .nvram_config = qla2x00_nvram_config,
1730 .update_fw_options = qla2x00_update_fw_options,
1731 .load_risc = qla2x00_load_risc,
1732 .pci_info_str = qla2x00_pci_info_str,
1733 .fw_version_str = qla2x00_fw_version_str,
1734 .intr_handler = qla2100_intr_handler,
1735 .enable_intrs = qla2x00_enable_intrs,
1736 .disable_intrs = qla2x00_disable_intrs,
1737 .abort_command = qla2x00_abort_command,
1738 .target_reset = qla2x00_abort_target,
1739 .lun_reset = qla2x00_lun_reset,
1740 .fabric_login = qla2x00_login_fabric,
1741 .fabric_logout = qla2x00_fabric_logout,
1742 .calc_req_entries = qla2x00_calc_iocbs_32,
1743 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1744 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1745 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1746 .read_nvram = qla2x00_read_nvram_data,
1747 .write_nvram = qla2x00_write_nvram_data,
1748 .fw_dump = qla2100_fw_dump,
1749 .beacon_on = NULL,
1750 .beacon_off = NULL,
1751 .beacon_blink = NULL,
1752 .read_optrom = qla2x00_read_optrom_data,
1753 .write_optrom = qla2x00_write_optrom_data,
1754 .get_flash_version = qla2x00_get_flash_version,
1755 .start_scsi = qla2x00_start_scsi,
1756 .abort_isp = qla2x00_abort_isp,
1757 .iospace_config = qla2x00_iospace_config,
1758 .initialize_adapter = qla2x00_initialize_adapter,
1759 };
1760
1761 static struct isp_operations qla2300_isp_ops = {
1762 .pci_config = qla2300_pci_config,
1763 .reset_chip = qla2x00_reset_chip,
1764 .chip_diag = qla2x00_chip_diag,
1765 .config_rings = qla2x00_config_rings,
1766 .reset_adapter = qla2x00_reset_adapter,
1767 .nvram_config = qla2x00_nvram_config,
1768 .update_fw_options = qla2x00_update_fw_options,
1769 .load_risc = qla2x00_load_risc,
1770 .pci_info_str = qla2x00_pci_info_str,
1771 .fw_version_str = qla2x00_fw_version_str,
1772 .intr_handler = qla2300_intr_handler,
1773 .enable_intrs = qla2x00_enable_intrs,
1774 .disable_intrs = qla2x00_disable_intrs,
1775 .abort_command = qla2x00_abort_command,
1776 .target_reset = qla2x00_abort_target,
1777 .lun_reset = qla2x00_lun_reset,
1778 .fabric_login = qla2x00_login_fabric,
1779 .fabric_logout = qla2x00_fabric_logout,
1780 .calc_req_entries = qla2x00_calc_iocbs_32,
1781 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1782 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1783 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1784 .read_nvram = qla2x00_read_nvram_data,
1785 .write_nvram = qla2x00_write_nvram_data,
1786 .fw_dump = qla2300_fw_dump,
1787 .beacon_on = qla2x00_beacon_on,
1788 .beacon_off = qla2x00_beacon_off,
1789 .beacon_blink = qla2x00_beacon_blink,
1790 .read_optrom = qla2x00_read_optrom_data,
1791 .write_optrom = qla2x00_write_optrom_data,
1792 .get_flash_version = qla2x00_get_flash_version,
1793 .start_scsi = qla2x00_start_scsi,
1794 .abort_isp = qla2x00_abort_isp,
1795 .iospace_config = qla2x00_iospace_config,
1796 .initialize_adapter = qla2x00_initialize_adapter,
1797 };
1798
1799 static struct isp_operations qla24xx_isp_ops = {
1800 .pci_config = qla24xx_pci_config,
1801 .reset_chip = qla24xx_reset_chip,
1802 .chip_diag = qla24xx_chip_diag,
1803 .config_rings = qla24xx_config_rings,
1804 .reset_adapter = qla24xx_reset_adapter,
1805 .nvram_config = qla24xx_nvram_config,
1806 .update_fw_options = qla24xx_update_fw_options,
1807 .load_risc = qla24xx_load_risc,
1808 .pci_info_str = qla24xx_pci_info_str,
1809 .fw_version_str = qla24xx_fw_version_str,
1810 .intr_handler = qla24xx_intr_handler,
1811 .enable_intrs = qla24xx_enable_intrs,
1812 .disable_intrs = qla24xx_disable_intrs,
1813 .abort_command = qla24xx_abort_command,
1814 .target_reset = qla24xx_abort_target,
1815 .lun_reset = qla24xx_lun_reset,
1816 .fabric_login = qla24xx_login_fabric,
1817 .fabric_logout = qla24xx_fabric_logout,
1818 .calc_req_entries = NULL,
1819 .build_iocbs = NULL,
1820 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1821 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1822 .read_nvram = qla24xx_read_nvram_data,
1823 .write_nvram = qla24xx_write_nvram_data,
1824 .fw_dump = qla24xx_fw_dump,
1825 .beacon_on = qla24xx_beacon_on,
1826 .beacon_off = qla24xx_beacon_off,
1827 .beacon_blink = qla24xx_beacon_blink,
1828 .read_optrom = qla24xx_read_optrom_data,
1829 .write_optrom = qla24xx_write_optrom_data,
1830 .get_flash_version = qla24xx_get_flash_version,
1831 .start_scsi = qla24xx_start_scsi,
1832 .abort_isp = qla2x00_abort_isp,
1833 .iospace_config = qla2x00_iospace_config,
1834 .initialize_adapter = qla2x00_initialize_adapter,
1835 };
1836
1837 static struct isp_operations qla25xx_isp_ops = {
1838 .pci_config = qla25xx_pci_config,
1839 .reset_chip = qla24xx_reset_chip,
1840 .chip_diag = qla24xx_chip_diag,
1841 .config_rings = qla24xx_config_rings,
1842 .reset_adapter = qla24xx_reset_adapter,
1843 .nvram_config = qla24xx_nvram_config,
1844 .update_fw_options = qla24xx_update_fw_options,
1845 .load_risc = qla24xx_load_risc,
1846 .pci_info_str = qla24xx_pci_info_str,
1847 .fw_version_str = qla24xx_fw_version_str,
1848 .intr_handler = qla24xx_intr_handler,
1849 .enable_intrs = qla24xx_enable_intrs,
1850 .disable_intrs = qla24xx_disable_intrs,
1851 .abort_command = qla24xx_abort_command,
1852 .target_reset = qla24xx_abort_target,
1853 .lun_reset = qla24xx_lun_reset,
1854 .fabric_login = qla24xx_login_fabric,
1855 .fabric_logout = qla24xx_fabric_logout,
1856 .calc_req_entries = NULL,
1857 .build_iocbs = NULL,
1858 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1859 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1860 .read_nvram = qla25xx_read_nvram_data,
1861 .write_nvram = qla25xx_write_nvram_data,
1862 .fw_dump = qla25xx_fw_dump,
1863 .beacon_on = qla24xx_beacon_on,
1864 .beacon_off = qla24xx_beacon_off,
1865 .beacon_blink = qla24xx_beacon_blink,
1866 .read_optrom = qla25xx_read_optrom_data,
1867 .write_optrom = qla24xx_write_optrom_data,
1868 .get_flash_version = qla24xx_get_flash_version,
1869 .start_scsi = qla24xx_dif_start_scsi,
1870 .abort_isp = qla2x00_abort_isp,
1871 .iospace_config = qla2x00_iospace_config,
1872 .initialize_adapter = qla2x00_initialize_adapter,
1873 };
1874
1875 static struct isp_operations qla81xx_isp_ops = {
1876 .pci_config = qla25xx_pci_config,
1877 .reset_chip = qla24xx_reset_chip,
1878 .chip_diag = qla24xx_chip_diag,
1879 .config_rings = qla24xx_config_rings,
1880 .reset_adapter = qla24xx_reset_adapter,
1881 .nvram_config = qla81xx_nvram_config,
1882 .update_fw_options = qla81xx_update_fw_options,
1883 .load_risc = qla81xx_load_risc,
1884 .pci_info_str = qla24xx_pci_info_str,
1885 .fw_version_str = qla24xx_fw_version_str,
1886 .intr_handler = qla24xx_intr_handler,
1887 .enable_intrs = qla24xx_enable_intrs,
1888 .disable_intrs = qla24xx_disable_intrs,
1889 .abort_command = qla24xx_abort_command,
1890 .target_reset = qla24xx_abort_target,
1891 .lun_reset = qla24xx_lun_reset,
1892 .fabric_login = qla24xx_login_fabric,
1893 .fabric_logout = qla24xx_fabric_logout,
1894 .calc_req_entries = NULL,
1895 .build_iocbs = NULL,
1896 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1897 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1898 .read_nvram = NULL,
1899 .write_nvram = NULL,
1900 .fw_dump = qla81xx_fw_dump,
1901 .beacon_on = qla24xx_beacon_on,
1902 .beacon_off = qla24xx_beacon_off,
1903 .beacon_blink = qla83xx_beacon_blink,
1904 .read_optrom = qla25xx_read_optrom_data,
1905 .write_optrom = qla24xx_write_optrom_data,
1906 .get_flash_version = qla24xx_get_flash_version,
1907 .start_scsi = qla24xx_dif_start_scsi,
1908 .abort_isp = qla2x00_abort_isp,
1909 .iospace_config = qla2x00_iospace_config,
1910 .initialize_adapter = qla2x00_initialize_adapter,
1911 };
1912
1913 static struct isp_operations qla82xx_isp_ops = {
1914 .pci_config = qla82xx_pci_config,
1915 .reset_chip = qla82xx_reset_chip,
1916 .chip_diag = qla24xx_chip_diag,
1917 .config_rings = qla82xx_config_rings,
1918 .reset_adapter = qla24xx_reset_adapter,
1919 .nvram_config = qla81xx_nvram_config,
1920 .update_fw_options = qla24xx_update_fw_options,
1921 .load_risc = qla82xx_load_risc,
1922 .pci_info_str = qla24xx_pci_info_str,
1923 .fw_version_str = qla24xx_fw_version_str,
1924 .intr_handler = qla82xx_intr_handler,
1925 .enable_intrs = qla82xx_enable_intrs,
1926 .disable_intrs = qla82xx_disable_intrs,
1927 .abort_command = qla24xx_abort_command,
1928 .target_reset = qla24xx_abort_target,
1929 .lun_reset = qla24xx_lun_reset,
1930 .fabric_login = qla24xx_login_fabric,
1931 .fabric_logout = qla24xx_fabric_logout,
1932 .calc_req_entries = NULL,
1933 .build_iocbs = NULL,
1934 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1935 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1936 .read_nvram = qla24xx_read_nvram_data,
1937 .write_nvram = qla24xx_write_nvram_data,
1938 .fw_dump = qla82xx_fw_dump,
1939 .beacon_on = qla82xx_beacon_on,
1940 .beacon_off = qla82xx_beacon_off,
1941 .beacon_blink = NULL,
1942 .read_optrom = qla82xx_read_optrom_data,
1943 .write_optrom = qla82xx_write_optrom_data,
1944 .get_flash_version = qla82xx_get_flash_version,
1945 .start_scsi = qla82xx_start_scsi,
1946 .abort_isp = qla82xx_abort_isp,
1947 .iospace_config = qla82xx_iospace_config,
1948 .initialize_adapter = qla2x00_initialize_adapter,
1949 };
1950
1951 static struct isp_operations qla8044_isp_ops = {
1952 .pci_config = qla82xx_pci_config,
1953 .reset_chip = qla82xx_reset_chip,
1954 .chip_diag = qla24xx_chip_diag,
1955 .config_rings = qla82xx_config_rings,
1956 .reset_adapter = qla24xx_reset_adapter,
1957 .nvram_config = qla81xx_nvram_config,
1958 .update_fw_options = qla24xx_update_fw_options,
1959 .load_risc = qla82xx_load_risc,
1960 .pci_info_str = qla24xx_pci_info_str,
1961 .fw_version_str = qla24xx_fw_version_str,
1962 .intr_handler = qla8044_intr_handler,
1963 .enable_intrs = qla82xx_enable_intrs,
1964 .disable_intrs = qla82xx_disable_intrs,
1965 .abort_command = qla24xx_abort_command,
1966 .target_reset = qla24xx_abort_target,
1967 .lun_reset = qla24xx_lun_reset,
1968 .fabric_login = qla24xx_login_fabric,
1969 .fabric_logout = qla24xx_fabric_logout,
1970 .calc_req_entries = NULL,
1971 .build_iocbs = NULL,
1972 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1973 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1974 .read_nvram = NULL,
1975 .write_nvram = NULL,
1976 .fw_dump = qla8044_fw_dump,
1977 .beacon_on = qla82xx_beacon_on,
1978 .beacon_off = qla82xx_beacon_off,
1979 .beacon_blink = NULL,
1980 .read_optrom = qla8044_read_optrom_data,
1981 .write_optrom = qla8044_write_optrom_data,
1982 .get_flash_version = qla82xx_get_flash_version,
1983 .start_scsi = qla82xx_start_scsi,
1984 .abort_isp = qla8044_abort_isp,
1985 .iospace_config = qla82xx_iospace_config,
1986 .initialize_adapter = qla2x00_initialize_adapter,
1987 };
1988
1989 static struct isp_operations qla83xx_isp_ops = {
1990 .pci_config = qla25xx_pci_config,
1991 .reset_chip = qla24xx_reset_chip,
1992 .chip_diag = qla24xx_chip_diag,
1993 .config_rings = qla24xx_config_rings,
1994 .reset_adapter = qla24xx_reset_adapter,
1995 .nvram_config = qla81xx_nvram_config,
1996 .update_fw_options = qla81xx_update_fw_options,
1997 .load_risc = qla81xx_load_risc,
1998 .pci_info_str = qla24xx_pci_info_str,
1999 .fw_version_str = qla24xx_fw_version_str,
2000 .intr_handler = qla24xx_intr_handler,
2001 .enable_intrs = qla24xx_enable_intrs,
2002 .disable_intrs = qla24xx_disable_intrs,
2003 .abort_command = qla24xx_abort_command,
2004 .target_reset = qla24xx_abort_target,
2005 .lun_reset = qla24xx_lun_reset,
2006 .fabric_login = qla24xx_login_fabric,
2007 .fabric_logout = qla24xx_fabric_logout,
2008 .calc_req_entries = NULL,
2009 .build_iocbs = NULL,
2010 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2011 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2012 .read_nvram = NULL,
2013 .write_nvram = NULL,
2014 .fw_dump = qla83xx_fw_dump,
2015 .beacon_on = qla24xx_beacon_on,
2016 .beacon_off = qla24xx_beacon_off,
2017 .beacon_blink = qla83xx_beacon_blink,
2018 .read_optrom = qla25xx_read_optrom_data,
2019 .write_optrom = qla24xx_write_optrom_data,
2020 .get_flash_version = qla24xx_get_flash_version,
2021 .start_scsi = qla24xx_dif_start_scsi,
2022 .abort_isp = qla2x00_abort_isp,
2023 .iospace_config = qla83xx_iospace_config,
2024 .initialize_adapter = qla2x00_initialize_adapter,
2025 };
2026
2027 static struct isp_operations qlafx00_isp_ops = {
2028 .pci_config = qlafx00_pci_config,
2029 .reset_chip = qlafx00_soft_reset,
2030 .chip_diag = qlafx00_chip_diag,
2031 .config_rings = qlafx00_config_rings,
2032 .reset_adapter = qlafx00_soft_reset,
2033 .nvram_config = NULL,
2034 .update_fw_options = NULL,
2035 .load_risc = NULL,
2036 .pci_info_str = qlafx00_pci_info_str,
2037 .fw_version_str = qlafx00_fw_version_str,
2038 .intr_handler = qlafx00_intr_handler,
2039 .enable_intrs = qlafx00_enable_intrs,
2040 .disable_intrs = qlafx00_disable_intrs,
2041 .abort_command = qla24xx_async_abort_command,
2042 .target_reset = qlafx00_abort_target,
2043 .lun_reset = qlafx00_lun_reset,
2044 .fabric_login = NULL,
2045 .fabric_logout = NULL,
2046 .calc_req_entries = NULL,
2047 .build_iocbs = NULL,
2048 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2049 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2050 .read_nvram = qla24xx_read_nvram_data,
2051 .write_nvram = qla24xx_write_nvram_data,
2052 .fw_dump = NULL,
2053 .beacon_on = qla24xx_beacon_on,
2054 .beacon_off = qla24xx_beacon_off,
2055 .beacon_blink = NULL,
2056 .read_optrom = qla24xx_read_optrom_data,
2057 .write_optrom = qla24xx_write_optrom_data,
2058 .get_flash_version = qla24xx_get_flash_version,
2059 .start_scsi = qlafx00_start_scsi,
2060 .abort_isp = qlafx00_abort_isp,
2061 .iospace_config = qlafx00_iospace_config,
2062 .initialize_adapter = qlafx00_initialize_adapter,
2063 };
2064
2065 static struct isp_operations qla27xx_isp_ops = {
2066 .pci_config = qla25xx_pci_config,
2067 .reset_chip = qla24xx_reset_chip,
2068 .chip_diag = qla24xx_chip_diag,
2069 .config_rings = qla24xx_config_rings,
2070 .reset_adapter = qla24xx_reset_adapter,
2071 .nvram_config = qla81xx_nvram_config,
2072 .update_fw_options = qla81xx_update_fw_options,
2073 .load_risc = qla81xx_load_risc,
2074 .pci_info_str = qla24xx_pci_info_str,
2075 .fw_version_str = qla24xx_fw_version_str,
2076 .intr_handler = qla24xx_intr_handler,
2077 .enable_intrs = qla24xx_enable_intrs,
2078 .disable_intrs = qla24xx_disable_intrs,
2079 .abort_command = qla24xx_abort_command,
2080 .target_reset = qla24xx_abort_target,
2081 .lun_reset = qla24xx_lun_reset,
2082 .fabric_login = qla24xx_login_fabric,
2083 .fabric_logout = qla24xx_fabric_logout,
2084 .calc_req_entries = NULL,
2085 .build_iocbs = NULL,
2086 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2087 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2088 .read_nvram = NULL,
2089 .write_nvram = NULL,
2090 .fw_dump = qla27xx_fwdump,
2091 .beacon_on = qla24xx_beacon_on,
2092 .beacon_off = qla24xx_beacon_off,
2093 .beacon_blink = qla83xx_beacon_blink,
2094 .read_optrom = qla25xx_read_optrom_data,
2095 .write_optrom = qla24xx_write_optrom_data,
2096 .get_flash_version = qla24xx_get_flash_version,
2097 .start_scsi = qla24xx_dif_start_scsi,
2098 .abort_isp = qla2x00_abort_isp,
2099 .iospace_config = qla83xx_iospace_config,
2100 .initialize_adapter = qla2x00_initialize_adapter,
2101 };
2102
2103 static inline void
2104 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2105 {
2106 ha->device_type = DT_EXTENDED_IDS;
2107 switch (ha->pdev->device) {
2108 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2109 ha->device_type |= DT_ISP2100;
2110 ha->device_type &= ~DT_EXTENDED_IDS;
2111 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2112 break;
2113 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2114 ha->device_type |= DT_ISP2200;
2115 ha->device_type &= ~DT_EXTENDED_IDS;
2116 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2117 break;
2118 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2119 ha->device_type |= DT_ISP2300;
2120 ha->device_type |= DT_ZIO_SUPPORTED;
2121 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2122 break;
2123 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2124 ha->device_type |= DT_ISP2312;
2125 ha->device_type |= DT_ZIO_SUPPORTED;
2126 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2127 break;
2128 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2129 ha->device_type |= DT_ISP2322;
2130 ha->device_type |= DT_ZIO_SUPPORTED;
2131 if (ha->pdev->subsystem_vendor == 0x1028 &&
2132 ha->pdev->subsystem_device == 0x0170)
2133 ha->device_type |= DT_OEM_001;
2134 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2135 break;
2136 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2137 ha->device_type |= DT_ISP6312;
2138 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2139 break;
2140 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2141 ha->device_type |= DT_ISP6322;
2142 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2143 break;
2144 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2145 ha->device_type |= DT_ISP2422;
2146 ha->device_type |= DT_ZIO_SUPPORTED;
2147 ha->device_type |= DT_FWI2;
2148 ha->device_type |= DT_IIDMA;
2149 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2150 break;
2151 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2152 ha->device_type |= DT_ISP2432;
2153 ha->device_type |= DT_ZIO_SUPPORTED;
2154 ha->device_type |= DT_FWI2;
2155 ha->device_type |= DT_IIDMA;
2156 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2157 break;
2158 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2159 ha->device_type |= DT_ISP8432;
2160 ha->device_type |= DT_ZIO_SUPPORTED;
2161 ha->device_type |= DT_FWI2;
2162 ha->device_type |= DT_IIDMA;
2163 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2164 break;
2165 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2166 ha->device_type |= DT_ISP5422;
2167 ha->device_type |= DT_FWI2;
2168 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2169 break;
2170 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2171 ha->device_type |= DT_ISP5432;
2172 ha->device_type |= DT_FWI2;
2173 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2174 break;
2175 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2176 ha->device_type |= DT_ISP2532;
2177 ha->device_type |= DT_ZIO_SUPPORTED;
2178 ha->device_type |= DT_FWI2;
2179 ha->device_type |= DT_IIDMA;
2180 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2181 break;
2182 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2183 ha->device_type |= DT_ISP8001;
2184 ha->device_type |= DT_ZIO_SUPPORTED;
2185 ha->device_type |= DT_FWI2;
2186 ha->device_type |= DT_IIDMA;
2187 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2188 break;
2189 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2190 ha->device_type |= DT_ISP8021;
2191 ha->device_type |= DT_ZIO_SUPPORTED;
2192 ha->device_type |= DT_FWI2;
2193 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2194 /* Initialize 82XX ISP flags */
2195 qla82xx_init_flags(ha);
2196 break;
2197 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2198 ha->device_type |= DT_ISP8044;
2199 ha->device_type |= DT_ZIO_SUPPORTED;
2200 ha->device_type |= DT_FWI2;
2201 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2202 /* Initialize 82XX ISP flags */
2203 qla82xx_init_flags(ha);
2204 break;
2205 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2206 ha->device_type |= DT_ISP2031;
2207 ha->device_type |= DT_ZIO_SUPPORTED;
2208 ha->device_type |= DT_FWI2;
2209 ha->device_type |= DT_IIDMA;
2210 ha->device_type |= DT_T10_PI;
2211 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2212 break;
2213 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2214 ha->device_type |= DT_ISP8031;
2215 ha->device_type |= DT_ZIO_SUPPORTED;
2216 ha->device_type |= DT_FWI2;
2217 ha->device_type |= DT_IIDMA;
2218 ha->device_type |= DT_T10_PI;
2219 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2220 break;
2221 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2222 ha->device_type |= DT_ISPFX00;
2223 break;
2224 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2225 ha->device_type |= DT_ISP2071;
2226 ha->device_type |= DT_ZIO_SUPPORTED;
2227 ha->device_type |= DT_FWI2;
2228 ha->device_type |= DT_IIDMA;
2229 ha->device_type |= DT_T10_PI;
2230 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2231 break;
2232 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2233 ha->device_type |= DT_ISP2271;
2234 ha->device_type |= DT_ZIO_SUPPORTED;
2235 ha->device_type |= DT_FWI2;
2236 ha->device_type |= DT_IIDMA;
2237 ha->device_type |= DT_T10_PI;
2238 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2239 break;
2240 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2241 ha->device_type |= DT_ISP2261;
2242 ha->device_type |= DT_ZIO_SUPPORTED;
2243 ha->device_type |= DT_FWI2;
2244 ha->device_type |= DT_IIDMA;
2245 ha->device_type |= DT_T10_PI;
2246 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2247 break;
2248 }
2249
2250 if (IS_QLA82XX(ha))
2251 ha->port_no = ha->portnum & 1;
2252 else {
2253 /* Get adapter physical port no from interrupt pin register. */
2254 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2255 if (IS_QLA27XX(ha))
2256 ha->port_no--;
2257 else
2258 ha->port_no = !(ha->port_no & 1);
2259 }
2260
2261 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2262 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2263 ha->device_type, ha->port_no, ha->fw_srisc_address);
2264 }
2265
2266 static void
2267 qla2xxx_scan_start(struct Scsi_Host *shost)
2268 {
2269 scsi_qla_host_t *vha = shost_priv(shost);
2270
2271 if (vha->hw->flags.running_gold_fw)
2272 return;
2273
2274 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2275 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2276 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2277 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2278 }
2279
2280 static int
2281 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2282 {
2283 scsi_qla_host_t *vha = shost_priv(shost);
2284
2285 if (!vha->host)
2286 return 1;
2287 if (time > vha->hw->loop_reset_delay * HZ)
2288 return 1;
2289
2290 return atomic_read(&vha->loop_state) == LOOP_READY;
2291 }
2292
2293 /*
2294 * PCI driver interface
2295 */
2296 static int
2297 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2298 {
2299 int ret = -ENODEV;
2300 struct Scsi_Host *host;
2301 scsi_qla_host_t *base_vha = NULL;
2302 struct qla_hw_data *ha;
2303 char pci_info[30];
2304 char fw_str[30], wq_name[30];
2305 struct scsi_host_template *sht;
2306 int bars, mem_only = 0;
2307 uint16_t req_length = 0, rsp_length = 0;
2308 struct req_que *req = NULL;
2309 struct rsp_que *rsp = NULL;
2310 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2311 sht = &qla2xxx_driver_template;
2312 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2313 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2314 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2315 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2316 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2317 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2318 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2319 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2320 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2321 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2322 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2323 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2324 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2325 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2326 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
2327 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2328 mem_only = 1;
2329 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2330 "Mem only adapter.\n");
2331 }
2332 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2333 "Bars=%d.\n", bars);
2334
2335 if (mem_only) {
2336 if (pci_enable_device_mem(pdev))
2337 goto probe_out;
2338 } else {
2339 if (pci_enable_device(pdev))
2340 goto probe_out;
2341 }
2342
2343 /* This may fail but that's ok */
2344 pci_enable_pcie_error_reporting(pdev);
2345
2346 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2347 if (!ha) {
2348 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2349 "Unable to allocate memory for ha.\n");
2350 goto probe_out;
2351 }
2352 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2353 "Memory allocated for ha=%p.\n", ha);
2354 ha->pdev = pdev;
2355 ha->tgt.enable_class_2 = ql2xenableclass2;
2356 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2357 spin_lock_init(&ha->tgt.q_full_lock);
2358 spin_lock_init(&ha->tgt.sess_lock);
2359 spin_lock_init(&ha->tgt.atio_lock);
2360
2361
2362 /* Clear our data area */
2363 ha->bars = bars;
2364 ha->mem_only = mem_only;
2365 spin_lock_init(&ha->hardware_lock);
2366 spin_lock_init(&ha->vport_slock);
2367 mutex_init(&ha->selflogin_lock);
2368 mutex_init(&ha->optrom_mutex);
2369
2370 /* Set ISP-type information. */
2371 qla2x00_set_isp_flags(ha);
2372
2373 /* Set EEH reset type to fundamental if required by hba */
2374 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2375 IS_QLA83XX(ha) || IS_QLA27XX(ha))
2376 pdev->needs_freset = 1;
2377
2378 ha->prev_topology = 0;
2379 ha->init_cb_size = sizeof(init_cb_t);
2380 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2381 ha->optrom_size = OPTROM_SIZE_2300;
2382
2383 /* Assign ISP specific operations. */
2384 if (IS_QLA2100(ha)) {
2385 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2386 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2387 req_length = REQUEST_ENTRY_CNT_2100;
2388 rsp_length = RESPONSE_ENTRY_CNT_2100;
2389 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2390 ha->gid_list_info_size = 4;
2391 ha->flash_conf_off = ~0;
2392 ha->flash_data_off = ~0;
2393 ha->nvram_conf_off = ~0;
2394 ha->nvram_data_off = ~0;
2395 ha->isp_ops = &qla2100_isp_ops;
2396 } else if (IS_QLA2200(ha)) {
2397 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2398 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2399 req_length = REQUEST_ENTRY_CNT_2200;
2400 rsp_length = RESPONSE_ENTRY_CNT_2100;
2401 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2402 ha->gid_list_info_size = 4;
2403 ha->flash_conf_off = ~0;
2404 ha->flash_data_off = ~0;
2405 ha->nvram_conf_off = ~0;
2406 ha->nvram_data_off = ~0;
2407 ha->isp_ops = &qla2100_isp_ops;
2408 } else if (IS_QLA23XX(ha)) {
2409 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2410 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2411 req_length = REQUEST_ENTRY_CNT_2200;
2412 rsp_length = RESPONSE_ENTRY_CNT_2300;
2413 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2414 ha->gid_list_info_size = 6;
2415 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2416 ha->optrom_size = OPTROM_SIZE_2322;
2417 ha->flash_conf_off = ~0;
2418 ha->flash_data_off = ~0;
2419 ha->nvram_conf_off = ~0;
2420 ha->nvram_data_off = ~0;
2421 ha->isp_ops = &qla2300_isp_ops;
2422 } else if (IS_QLA24XX_TYPE(ha)) {
2423 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2424 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2425 req_length = REQUEST_ENTRY_CNT_24XX;
2426 rsp_length = RESPONSE_ENTRY_CNT_2300;
2427 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2428 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2429 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2430 ha->gid_list_info_size = 8;
2431 ha->optrom_size = OPTROM_SIZE_24XX;
2432 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2433 ha->isp_ops = &qla24xx_isp_ops;
2434 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2435 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2436 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2437 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2438 } else if (IS_QLA25XX(ha)) {
2439 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2440 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2441 req_length = REQUEST_ENTRY_CNT_24XX;
2442 rsp_length = RESPONSE_ENTRY_CNT_2300;
2443 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2444 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2445 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2446 ha->gid_list_info_size = 8;
2447 ha->optrom_size = OPTROM_SIZE_25XX;
2448 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2449 ha->isp_ops = &qla25xx_isp_ops;
2450 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2451 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2452 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2453 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2454 } else if (IS_QLA81XX(ha)) {
2455 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2456 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2457 req_length = REQUEST_ENTRY_CNT_24XX;
2458 rsp_length = RESPONSE_ENTRY_CNT_2300;
2459 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2460 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2461 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2462 ha->gid_list_info_size = 8;
2463 ha->optrom_size = OPTROM_SIZE_81XX;
2464 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2465 ha->isp_ops = &qla81xx_isp_ops;
2466 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2467 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2468 ha->nvram_conf_off = ~0;
2469 ha->nvram_data_off = ~0;
2470 } else if (IS_QLA82XX(ha)) {
2471 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2472 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2473 req_length = REQUEST_ENTRY_CNT_82XX;
2474 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2475 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2476 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2477 ha->gid_list_info_size = 8;
2478 ha->optrom_size = OPTROM_SIZE_82XX;
2479 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2480 ha->isp_ops = &qla82xx_isp_ops;
2481 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2482 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2483 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2484 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2485 } else if (IS_QLA8044(ha)) {
2486 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2487 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2488 req_length = REQUEST_ENTRY_CNT_82XX;
2489 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2490 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2491 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2492 ha->gid_list_info_size = 8;
2493 ha->optrom_size = OPTROM_SIZE_83XX;
2494 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2495 ha->isp_ops = &qla8044_isp_ops;
2496 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2497 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2498 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2499 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2500 } else if (IS_QLA83XX(ha)) {
2501 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2502 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2503 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2504 req_length = REQUEST_ENTRY_CNT_83XX;
2505 rsp_length = RESPONSE_ENTRY_CNT_83XX;
2506 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2507 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2508 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2509 ha->gid_list_info_size = 8;
2510 ha->optrom_size = OPTROM_SIZE_83XX;
2511 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2512 ha->isp_ops = &qla83xx_isp_ops;
2513 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2514 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2515 ha->nvram_conf_off = ~0;
2516 ha->nvram_data_off = ~0;
2517 } else if (IS_QLAFX00(ha)) {
2518 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2519 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2520 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2521 req_length = REQUEST_ENTRY_CNT_FX00;
2522 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2523 ha->isp_ops = &qlafx00_isp_ops;
2524 ha->port_down_retry_count = 30; /* default value */
2525 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2526 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
2527 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
2528 ha->mr.fw_hbt_en = 1;
2529 ha->mr.host_info_resend = false;
2530 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
2531 } else if (IS_QLA27XX(ha)) {
2532 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2533 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2534 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2535 req_length = REQUEST_ENTRY_CNT_83XX;
2536 rsp_length = RESPONSE_ENTRY_CNT_83XX;
2537 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2538 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2539 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2540 ha->gid_list_info_size = 8;
2541 ha->optrom_size = OPTROM_SIZE_83XX;
2542 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2543 ha->isp_ops = &qla27xx_isp_ops;
2544 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2545 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2546 ha->nvram_conf_off = ~0;
2547 ha->nvram_data_off = ~0;
2548 }
2549
2550 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2551 "mbx_count=%d, req_length=%d, "
2552 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2553 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2554 "max_fibre_devices=%d.\n",
2555 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2556 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2557 ha->nvram_npiv_size, ha->max_fibre_devices);
2558 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2559 "isp_ops=%p, flash_conf_off=%d, "
2560 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2561 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2562 ha->nvram_conf_off, ha->nvram_data_off);
2563
2564 /* Configure PCI I/O space */
2565 ret = ha->isp_ops->iospace_config(ha);
2566 if (ret)
2567 goto iospace_config_failed;
2568
2569 ql_log_pci(ql_log_info, pdev, 0x001d,
2570 "Found an ISP%04X irq %d iobase 0x%p.\n",
2571 pdev->device, pdev->irq, ha->iobase);
2572 mutex_init(&ha->vport_lock);
2573 init_completion(&ha->mbx_cmd_comp);
2574 complete(&ha->mbx_cmd_comp);
2575 init_completion(&ha->mbx_intr_comp);
2576 init_completion(&ha->dcbx_comp);
2577 init_completion(&ha->lb_portup_comp);
2578
2579 set_bit(0, (unsigned long *) ha->vp_idx_map);
2580
2581 qla2x00_config_dma_addressing(ha);
2582 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2583 "64 Bit addressing is %s.\n",
2584 ha->flags.enable_64bit_addressing ? "enable" :
2585 "disable");
2586 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
2587 if (ret) {
2588 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2589 "Failed to allocate memory for adapter, aborting.\n");
2590
2591 goto probe_hw_failed;
2592 }
2593
2594 req->max_q_depth = MAX_Q_DEPTH;
2595 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
2596 req->max_q_depth = ql2xmaxqdepth;
2597
2598
2599 base_vha = qla2x00_create_host(sht, ha);
2600 if (!base_vha) {
2601 ret = -ENOMEM;
2602 qla2x00_mem_free(ha);
2603 qla2x00_free_req_que(ha, req);
2604 qla2x00_free_rsp_que(ha, rsp);
2605 goto probe_hw_failed;
2606 }
2607
2608 pci_set_drvdata(pdev, base_vha);
2609 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
2610
2611 host = base_vha->host;
2612 base_vha->req = req;
2613 if (IS_QLA2XXX_MIDTYPE(ha))
2614 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
2615 else
2616 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2617 base_vha->vp_idx;
2618
2619 /* Setup fcport template structure. */
2620 ha->mr.fcport.vha = base_vha;
2621 ha->mr.fcport.port_type = FCT_UNKNOWN;
2622 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2623 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2624 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2625 ha->mr.fcport.scan_state = 1;
2626
2627 /* Set the SG table size based on ISP type */
2628 if (!IS_FWI2_CAPABLE(ha)) {
2629 if (IS_QLA2100(ha))
2630 host->sg_tablesize = 32;
2631 } else {
2632 if (!IS_QLA82XX(ha))
2633 host->sg_tablesize = QLA_SG_ALL;
2634 }
2635 host->max_id = ha->max_fibre_devices;
2636 host->cmd_per_lun = 3;
2637 host->unique_id = host->host_no;
2638 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
2639 host->max_cmd_len = 32;
2640 else
2641 host->max_cmd_len = MAX_CMDSZ;
2642 host->max_channel = MAX_BUSES - 1;
2643 /* Older HBAs support only 16-bit LUNs */
2644 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2645 ql2xmaxlun > 0xffff)
2646 host->max_lun = 0xffff;
2647 else
2648 host->max_lun = ql2xmaxlun;
2649 host->transportt = qla2xxx_transport_template;
2650 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
2651
2652 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2653 "max_id=%d this_id=%d "
2654 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2655 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
2656 host->this_id, host->cmd_per_lun, host->unique_id,
2657 host->max_cmd_len, host->max_channel, host->max_lun,
2658 host->transportt, sht->vendor_id);
2659
2660 que_init:
2661 /* Alloc arrays of request and response ring ptrs */
2662 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2663 ql_log(ql_log_fatal, base_vha, 0x003d,
2664 "Failed to allocate memory for queue pointers..."
2665 "aborting.\n");
2666 goto probe_init_failed;
2667 }
2668
2669 qlt_probe_one_stage1(base_vha, ha);
2670
2671 /* Set up the irqs */
2672 ret = qla2x00_request_irqs(ha, rsp);
2673 if (ret)
2674 goto probe_init_failed;
2675
2676 pci_save_state(pdev);
2677
2678 /* Assign back pointers */
2679 rsp->req = req;
2680 req->rsp = rsp;
2681
2682 if (IS_QLAFX00(ha)) {
2683 ha->rsp_q_map[0] = rsp;
2684 ha->req_q_map[0] = req;
2685 set_bit(0, ha->req_qid_map);
2686 set_bit(0, ha->rsp_qid_map);
2687 }
2688
2689 /* FWI2-capable only. */
2690 req->req_q_in = &ha->iobase->isp24.req_q_in;
2691 req->req_q_out = &ha->iobase->isp24.req_q_out;
2692 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2693 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
2694 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
2695 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2696 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2697 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2698 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
2699 }
2700
2701 if (IS_QLAFX00(ha)) {
2702 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2703 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2704 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2705 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2706 }
2707
2708 if (IS_P3P_TYPE(ha)) {
2709 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2710 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2711 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2712 }
2713
2714 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2715 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2716 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2717 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2718 "req->req_q_in=%p req->req_q_out=%p "
2719 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2720 req->req_q_in, req->req_q_out,
2721 rsp->rsp_q_in, rsp->rsp_q_out);
2722 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2723 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2724 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2725 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2726 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2727 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
2728
2729 if (ha->isp_ops->initialize_adapter(base_vha)) {
2730 ql_log(ql_log_fatal, base_vha, 0x00d6,
2731 "Failed to initialize adapter - Adapter flags %x.\n",
2732 base_vha->device_flags);
2733
2734 if (IS_QLA82XX(ha)) {
2735 qla82xx_idc_lock(ha);
2736 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2737 QLA8XXX_DEV_FAILED);
2738 qla82xx_idc_unlock(ha);
2739 ql_log(ql_log_fatal, base_vha, 0x00d7,
2740 "HW State: FAILED.\n");
2741 } else if (IS_QLA8044(ha)) {
2742 qla8044_idc_lock(ha);
2743 qla8044_wr_direct(base_vha,
2744 QLA8044_CRB_DEV_STATE_INDEX,
2745 QLA8XXX_DEV_FAILED);
2746 qla8044_idc_unlock(ha);
2747 ql_log(ql_log_fatal, base_vha, 0x0150,
2748 "HW State: FAILED.\n");
2749 }
2750
2751 ret = -ENODEV;
2752 goto probe_failed;
2753 }
2754
2755 if (IS_QLAFX00(ha))
2756 host->can_queue = QLAFX00_MAX_CANQUEUE;
2757 else
2758 host->can_queue = req->num_outstanding_cmds - 10;
2759
2760 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2761 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2762 host->can_queue, base_vha->req,
2763 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2764
2765 if (ha->mqenable) {
2766 if (qla25xx_setup_mode(base_vha)) {
2767 ql_log(ql_log_warn, base_vha, 0x00ec,
2768 "Failed to create queues, falling back to single queue mode.\n");
2769 goto que_init;
2770 }
2771 }
2772
2773 if (ha->flags.running_gold_fw)
2774 goto skip_dpc;
2775
2776 /*
2777 * Startup the kernel thread for this host adapter
2778 */
2779 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
2780 "%s_dpc", base_vha->host_str);
2781 if (IS_ERR(ha->dpc_thread)) {
2782 ql_log(ql_log_fatal, base_vha, 0x00ed,
2783 "Failed to start DPC thread.\n");
2784 ret = PTR_ERR(ha->dpc_thread);
2785 goto probe_failed;
2786 }
2787 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2788 "DPC thread started successfully.\n");
2789
2790 /*
2791 * If we're not coming up in initiator mode, we might sit for
2792 * a while without waking up the dpc thread, which leads to a
2793 * stuck process warning. So just kick the dpc once here and
2794 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2795 */
2796 qla2xxx_wake_dpc(base_vha);
2797
2798 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2799
2800 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2801 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2802 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2803 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2804
2805 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2806 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2807 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2808 INIT_WORK(&ha->idc_state_handler,
2809 qla83xx_idc_state_handler_work);
2810 INIT_WORK(&ha->nic_core_unrecoverable,
2811 qla83xx_nic_core_unrecoverable_work);
2812 }
2813
2814 skip_dpc:
2815 list_add_tail(&base_vha->list, &ha->vp_list);
2816 base_vha->host->irq = ha->pdev->irq;
2817
2818 /* Initialized the timer */
2819 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
2820 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2821 "Started qla2x00_timer with "
2822 "interval=%d.\n", WATCH_INTERVAL);
2823 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2824 "Detected hba at address=%p.\n",
2825 ha);
2826
2827 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
2828 if (ha->fw_attributes & BIT_4) {
2829 int prot = 0, guard;
2830 base_vha->flags.difdix_supported = 1;
2831 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2832 "Registering for DIF/DIX type 1 and 3 protection.\n");
2833 if (ql2xenabledif == 1)
2834 prot = SHOST_DIX_TYPE0_PROTECTION;
2835 scsi_host_set_prot(host,
2836 prot | SHOST_DIF_TYPE1_PROTECTION
2837 | SHOST_DIF_TYPE2_PROTECTION
2838 | SHOST_DIF_TYPE3_PROTECTION
2839 | SHOST_DIX_TYPE1_PROTECTION
2840 | SHOST_DIX_TYPE2_PROTECTION
2841 | SHOST_DIX_TYPE3_PROTECTION);
2842
2843 guard = SHOST_DIX_GUARD_CRC;
2844
2845 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2846 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2847 guard |= SHOST_DIX_GUARD_IP;
2848
2849 scsi_host_set_guard(host, guard);
2850 } else
2851 base_vha->flags.difdix_supported = 0;
2852 }
2853
2854 ha->isp_ops->enable_intrs(ha);
2855
2856 if (IS_QLAFX00(ha)) {
2857 ret = qlafx00_fx_disc(base_vha,
2858 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2859 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2860 QLA_SG_ALL : 128;
2861 }
2862
2863 ret = scsi_add_host(host, &pdev->dev);
2864 if (ret)
2865 goto probe_failed;
2866
2867 base_vha->flags.init_done = 1;
2868 base_vha->flags.online = 1;
2869 ha->prev_minidump_failed = 0;
2870
2871 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2872 "Init done and hba is online.\n");
2873
2874 if (qla_ini_mode_enabled(base_vha))
2875 scsi_scan_host(host);
2876 else
2877 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2878 "skipping scsi_scan_host() for non-initiator port\n");
2879
2880 qla2x00_alloc_sysfs_attr(base_vha);
2881
2882 if (IS_QLAFX00(ha)) {
2883 ret = qlafx00_fx_disc(base_vha,
2884 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2885
2886 /* Register system information */
2887 ret = qlafx00_fx_disc(base_vha,
2888 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2889 }
2890
2891 qla2x00_init_host_attr(base_vha);
2892
2893 qla2x00_dfs_setup(base_vha);
2894
2895 ql_log(ql_log_info, base_vha, 0x00fb,
2896 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
2897 ql_log(ql_log_info, base_vha, 0x00fc,
2898 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2899 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2900 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2901 base_vha->host_no,
2902 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
2903
2904 qlt_add_target(ha, base_vha);
2905
2906 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
2907
2908 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2909 return -ENODEV;
2910
2911 return 0;
2912
2913 probe_init_failed:
2914 qla2x00_free_req_que(ha, req);
2915 ha->req_q_map[0] = NULL;
2916 clear_bit(0, ha->req_qid_map);
2917 qla2x00_free_rsp_que(ha, rsp);
2918 ha->rsp_q_map[0] = NULL;
2919 clear_bit(0, ha->rsp_qid_map);
2920 ha->max_req_queues = ha->max_rsp_queues = 0;
2921
2922 probe_failed:
2923 if (base_vha->timer_active)
2924 qla2x00_stop_timer(base_vha);
2925 base_vha->flags.online = 0;
2926 if (ha->dpc_thread) {
2927 struct task_struct *t = ha->dpc_thread;
2928
2929 ha->dpc_thread = NULL;
2930 kthread_stop(t);
2931 }
2932
2933 qla2x00_free_device(base_vha);
2934
2935 scsi_host_put(base_vha->host);
2936
2937 probe_hw_failed:
2938 qla2x00_clear_drv_active(ha);
2939
2940 iospace_config_failed:
2941 if (IS_P3P_TYPE(ha)) {
2942 if (!ha->nx_pcibase)
2943 iounmap((device_reg_t *)ha->nx_pcibase);
2944 if (!ql2xdbwr)
2945 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
2946 } else {
2947 if (ha->iobase)
2948 iounmap(ha->iobase);
2949 if (ha->cregbase)
2950 iounmap(ha->cregbase);
2951 }
2952 pci_release_selected_regions(ha->pdev, ha->bars);
2953 kfree(ha);
2954 ha = NULL;
2955
2956 probe_out:
2957 pci_disable_pcie_error_reporting(pdev);
2958 pci_disable_device(pdev);
2959 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2960 return -ENODEV;
2961 return ret;
2962 }
2963
2964 static void
2965 qla2x00_shutdown(struct pci_dev *pdev)
2966 {
2967 scsi_qla_host_t *vha;
2968 struct qla_hw_data *ha;
2969
2970 if (!atomic_read(&pdev->enable_cnt))
2971 return;
2972
2973 vha = pci_get_drvdata(pdev);
2974 ha = vha->hw;
2975
2976 /* Notify ISPFX00 firmware */
2977 if (IS_QLAFX00(ha))
2978 qlafx00_driver_shutdown(vha, 20);
2979
2980 /* Turn-off FCE trace */
2981 if (ha->flags.fce_enabled) {
2982 qla2x00_disable_fce_trace(vha, NULL, NULL);
2983 ha->flags.fce_enabled = 0;
2984 }
2985
2986 /* Turn-off EFT trace */
2987 if (ha->eft)
2988 qla2x00_disable_eft_trace(vha);
2989
2990 /* Stop currently executing firmware. */
2991 qla2x00_try_to_stop_firmware(vha);
2992
2993 /* Turn adapter off line */
2994 vha->flags.online = 0;
2995
2996 /* turn-off interrupts on the card */
2997 if (ha->interrupts_on) {
2998 vha->flags.init_done = 0;
2999 ha->isp_ops->disable_intrs(ha);
3000 }
3001
3002 qla2x00_free_irqs(vha);
3003
3004 qla2x00_free_fw_dump(ha);
3005
3006 pci_disable_pcie_error_reporting(pdev);
3007 pci_disable_device(pdev);
3008 }
3009
3010 /* Deletes all the virtual ports for a given ha */
3011 static void
3012 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3013 {
3014 scsi_qla_host_t *vha;
3015 unsigned long flags;
3016
3017 mutex_lock(&ha->vport_lock);
3018 while (ha->cur_vport_count) {
3019 spin_lock_irqsave(&ha->vport_slock, flags);
3020
3021 BUG_ON(base_vha->list.next == &ha->vp_list);
3022 /* This assumes first entry in ha->vp_list is always base vha */
3023 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3024 scsi_host_get(vha->host);
3025
3026 spin_unlock_irqrestore(&ha->vport_slock, flags);
3027 mutex_unlock(&ha->vport_lock);
3028
3029 fc_vport_terminate(vha->fc_vport);
3030 scsi_host_put(vha->host);
3031
3032 mutex_lock(&ha->vport_lock);
3033 }
3034 mutex_unlock(&ha->vport_lock);
3035 }
3036
3037 /* Stops all deferred work threads */
3038 static void
3039 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3040 {
3041 /* Flush the work queue and remove it */
3042 if (ha->wq) {
3043 flush_workqueue(ha->wq);
3044 destroy_workqueue(ha->wq);
3045 ha->wq = NULL;
3046 }
3047
3048 /* Cancel all work and destroy DPC workqueues */
3049 if (ha->dpc_lp_wq) {
3050 cancel_work_sync(&ha->idc_aen);
3051 destroy_workqueue(ha->dpc_lp_wq);
3052 ha->dpc_lp_wq = NULL;
3053 }
3054
3055 if (ha->dpc_hp_wq) {
3056 cancel_work_sync(&ha->nic_core_reset);
3057 cancel_work_sync(&ha->idc_state_handler);
3058 cancel_work_sync(&ha->nic_core_unrecoverable);
3059 destroy_workqueue(ha->dpc_hp_wq);
3060 ha->dpc_hp_wq = NULL;
3061 }
3062
3063 /* Kill the kernel thread for this host */
3064 if (ha->dpc_thread) {
3065 struct task_struct *t = ha->dpc_thread;
3066
3067 /*
3068 * qla2xxx_wake_dpc checks for ->dpc_thread
3069 * so we need to zero it out.
3070 */
3071 ha->dpc_thread = NULL;
3072 kthread_stop(t);
3073 }
3074 }
3075
3076 static void
3077 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3078 {
3079 if (IS_QLA82XX(ha)) {
3080
3081 iounmap((device_reg_t *)ha->nx_pcibase);
3082 if (!ql2xdbwr)
3083 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3084 } else {
3085 if (ha->iobase)
3086 iounmap(ha->iobase);
3087
3088 if (ha->cregbase)
3089 iounmap(ha->cregbase);
3090
3091 if (ha->mqiobase)
3092 iounmap(ha->mqiobase);
3093
3094 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
3095 iounmap(ha->msixbase);
3096 }
3097 }
3098
3099 static void
3100 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3101 {
3102 if (IS_QLA8044(ha)) {
3103 qla8044_idc_lock(ha);
3104 qla8044_clear_drv_active(ha);
3105 qla8044_idc_unlock(ha);
3106 } else if (IS_QLA82XX(ha)) {
3107 qla82xx_idc_lock(ha);
3108 qla82xx_clear_drv_active(ha);
3109 qla82xx_idc_unlock(ha);
3110 }
3111 }
3112
3113 static void
3114 qla2x00_remove_one(struct pci_dev *pdev)
3115 {
3116 scsi_qla_host_t *base_vha;
3117 struct qla_hw_data *ha;
3118
3119 base_vha = pci_get_drvdata(pdev);
3120 ha = base_vha->hw;
3121
3122 /* Indicate device removal to prevent future board_disable and wait
3123 * until any pending board_disable has completed. */
3124 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3125 cancel_work_sync(&ha->board_disable);
3126
3127 /*
3128 * If the PCI device is disabled then there was a PCI-disconnect and
3129 * qla2x00_disable_board_on_pci_error has taken care of most of the
3130 * resources.
3131 */
3132 if (!atomic_read(&pdev->enable_cnt)) {
3133 scsi_host_put(base_vha->host);
3134 kfree(ha);
3135 pci_set_drvdata(pdev, NULL);
3136 return;
3137 }
3138
3139 qla2x00_wait_for_hba_ready(base_vha);
3140
3141 set_bit(UNLOADING, &base_vha->dpc_flags);
3142
3143 if (IS_QLAFX00(ha))
3144 qlafx00_driver_shutdown(base_vha, 20);
3145
3146 qla2x00_delete_all_vps(ha, base_vha);
3147
3148 if (IS_QLA8031(ha)) {
3149 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3150 "Clearing fcoe driver presence.\n");
3151 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3152 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3153 "Error while clearing DRV-Presence.\n");
3154 }
3155
3156 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3157
3158 qla2x00_dfs_remove(base_vha);
3159
3160 qla84xx_put_chip(base_vha);
3161
3162 /* Laser should be disabled only for ISP2031 */
3163 if (IS_QLA2031(ha))
3164 qla83xx_disable_laser(base_vha);
3165
3166 /* Disable timer */
3167 if (base_vha->timer_active)
3168 qla2x00_stop_timer(base_vha);
3169
3170 base_vha->flags.online = 0;
3171
3172 /* free DMA memory */
3173 if (ha->exlogin_buf)
3174 qla2x00_free_exlogin_buffer(ha);
3175
3176 /* free DMA memory */
3177 if (ha->exchoffld_buf)
3178 qla2x00_free_exchoffld_buffer(ha);
3179
3180 qla2x00_destroy_deferred_work(ha);
3181
3182 qlt_remove_target(ha, base_vha);
3183
3184 qla2x00_free_sysfs_attr(base_vha, true);
3185
3186 fc_remove_host(base_vha->host);
3187
3188 scsi_remove_host(base_vha->host);
3189
3190 qla2x00_free_device(base_vha);
3191
3192 qla2x00_clear_drv_active(ha);
3193
3194 scsi_host_put(base_vha->host);
3195
3196 qla2x00_unmap_iobases(ha);
3197
3198 pci_release_selected_regions(ha->pdev, ha->bars);
3199 kfree(ha);
3200 ha = NULL;
3201
3202 pci_disable_pcie_error_reporting(pdev);
3203
3204 pci_disable_device(pdev);
3205 }
3206
3207 static void
3208 qla2x00_free_device(scsi_qla_host_t *vha)
3209 {
3210 struct qla_hw_data *ha = vha->hw;
3211
3212 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3213
3214 /* Disable timer */
3215 if (vha->timer_active)
3216 qla2x00_stop_timer(vha);
3217
3218 qla25xx_delete_queues(vha);
3219
3220 if (ha->flags.fce_enabled)
3221 qla2x00_disable_fce_trace(vha, NULL, NULL);
3222
3223 if (ha->eft)
3224 qla2x00_disable_eft_trace(vha);
3225
3226 /* Stop currently executing firmware. */
3227 qla2x00_try_to_stop_firmware(vha);
3228
3229 vha->flags.online = 0;
3230
3231 /* turn-off interrupts on the card */
3232 if (ha->interrupts_on) {
3233 vha->flags.init_done = 0;
3234 ha->isp_ops->disable_intrs(ha);
3235 }
3236
3237 qla2x00_free_irqs(vha);
3238
3239 qla2x00_free_fcports(vha);
3240
3241 qla2x00_mem_free(ha);
3242
3243 qla82xx_md_free(vha);
3244
3245 qla2x00_free_queues(ha);
3246 }
3247
3248 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3249 {
3250 fc_port_t *fcport, *tfcport;
3251
3252 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3253 list_del(&fcport->list);
3254 qla2x00_clear_loop_id(fcport);
3255 kfree(fcport);
3256 fcport = NULL;
3257 }
3258 }
3259
3260 static inline void
3261 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
3262 int defer)
3263 {
3264 struct fc_rport *rport;
3265 scsi_qla_host_t *base_vha;
3266 unsigned long flags;
3267
3268 if (!fcport->rport)
3269 return;
3270
3271 rport = fcport->rport;
3272 if (defer) {
3273 base_vha = pci_get_drvdata(vha->hw->pdev);
3274 spin_lock_irqsave(vha->host->host_lock, flags);
3275 fcport->drport = rport;
3276 spin_unlock_irqrestore(vha->host->host_lock, flags);
3277 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
3278 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3279 qla2xxx_wake_dpc(base_vha);
3280 } else {
3281 int now;
3282 if (rport)
3283 fc_remote_port_delete(rport);
3284 qlt_do_generation_tick(vha, &now);
3285 qlt_fc_port_deleted(vha, fcport, now);
3286 }
3287 }
3288
3289 /*
3290 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3291 *
3292 * Input: ha = adapter block pointer. fcport = port structure pointer.
3293 *
3294 * Return: None.
3295 *
3296 * Context:
3297 */
3298 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3299 int do_login, int defer)
3300 {
3301 if (IS_QLAFX00(vha->hw)) {
3302 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3303 qla2x00_schedule_rport_del(vha, fcport, defer);
3304 return;
3305 }
3306
3307 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3308 vha->vp_idx == fcport->vha->vp_idx) {
3309 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3310 qla2x00_schedule_rport_del(vha, fcport, defer);
3311 }
3312 /*
3313 * We may need to retry the login, so don't change the state of the
3314 * port but do the retries.
3315 */
3316 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3317 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3318
3319 if (!do_login)
3320 return;
3321
3322 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3323
3324 if (fcport->login_retry == 0) {
3325 fcport->login_retry = vha->hw->login_retry_count;
3326
3327 ql_dbg(ql_dbg_disc, vha, 0x2067,
3328 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3329 fcport->port_name, fcport->loop_id, fcport->login_retry);
3330 }
3331 }
3332
3333 /*
3334 * qla2x00_mark_all_devices_lost
3335 * Updates fcport state when device goes offline.
3336 *
3337 * Input:
3338 * ha = adapter block pointer.
3339 * fcport = port structure pointer.
3340 *
3341 * Return:
3342 * None.
3343 *
3344 * Context:
3345 */
3346 void
3347 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
3348 {
3349 fc_port_t *fcport;
3350
3351 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3352 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
3353 continue;
3354
3355 /*
3356 * No point in marking the device as lost, if the device is
3357 * already DEAD.
3358 */
3359 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3360 continue;
3361 if (atomic_read(&fcport->state) == FCS_ONLINE) {
3362 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3363 if (defer)
3364 qla2x00_schedule_rport_del(vha, fcport, defer);
3365 else if (vha->vp_idx == fcport->vha->vp_idx)
3366 qla2x00_schedule_rport_del(vha, fcport, defer);
3367 }
3368 }
3369 }
3370
3371 /*
3372 * qla2x00_mem_alloc
3373 * Allocates adapter memory.
3374 *
3375 * Returns:
3376 * 0 = success.
3377 * !0 = failure.
3378 */
3379 static int
3380 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3381 struct req_que **req, struct rsp_que **rsp)
3382 {
3383 char name[16];
3384
3385 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3386 &ha->init_cb_dma, GFP_KERNEL);
3387 if (!ha->init_cb)
3388 goto fail;
3389
3390 if (qlt_mem_alloc(ha) < 0)
3391 goto fail_free_init_cb;
3392
3393 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3394 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3395 if (!ha->gid_list)
3396 goto fail_free_tgt_mem;
3397
3398 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3399 if (!ha->srb_mempool)
3400 goto fail_free_gid_list;
3401
3402 if (IS_P3P_TYPE(ha)) {
3403 /* Allocate cache for CT6 Ctx. */
3404 if (!ctx_cachep) {
3405 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3406 sizeof(struct ct6_dsd), 0,
3407 SLAB_HWCACHE_ALIGN, NULL);
3408 if (!ctx_cachep)
3409 goto fail_free_gid_list;
3410 }
3411 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3412 ctx_cachep);
3413 if (!ha->ctx_mempool)
3414 goto fail_free_srb_mempool;
3415 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3416 "ctx_cachep=%p ctx_mempool=%p.\n",
3417 ctx_cachep, ha->ctx_mempool);
3418 }
3419
3420 /* Get memory for cached NVRAM */
3421 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3422 if (!ha->nvram)
3423 goto fail_free_ctx_mempool;
3424
3425 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3426 ha->pdev->device);
3427 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3428 DMA_POOL_SIZE, 8, 0);
3429 if (!ha->s_dma_pool)
3430 goto fail_free_nvram;
3431
3432 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3433 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3434 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3435
3436 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
3437 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3438 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3439 if (!ha->dl_dma_pool) {
3440 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3441 "Failed to allocate memory for dl_dma_pool.\n");
3442 goto fail_s_dma_pool;
3443 }
3444
3445 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3446 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3447 if (!ha->fcp_cmnd_dma_pool) {
3448 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3449 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
3450 goto fail_dl_dma_pool;
3451 }
3452 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3453 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3454 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
3455 }
3456
3457 /* Allocate memory for SNS commands */
3458 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3459 /* Get consistent memory allocated for SNS commands */
3460 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
3461 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
3462 if (!ha->sns_cmd)
3463 goto fail_dma_pool;
3464 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
3465 "sns_cmd: %p.\n", ha->sns_cmd);
3466 } else {
3467 /* Get consistent memory allocated for MS IOCB */
3468 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3469 &ha->ms_iocb_dma);
3470 if (!ha->ms_iocb)
3471 goto fail_dma_pool;
3472 /* Get consistent memory allocated for CT SNS commands */
3473 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
3474 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
3475 if (!ha->ct_sns)
3476 goto fail_free_ms_iocb;
3477 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3478 "ms_iocb=%p ct_sns=%p.\n",
3479 ha->ms_iocb, ha->ct_sns);
3480 }
3481
3482 /* Allocate memory for request ring */
3483 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3484 if (!*req) {
3485 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3486 "Failed to allocate memory for req.\n");
3487 goto fail_req;
3488 }
3489 (*req)->length = req_len;
3490 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3491 ((*req)->length + 1) * sizeof(request_t),
3492 &(*req)->dma, GFP_KERNEL);
3493 if (!(*req)->ring) {
3494 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3495 "Failed to allocate memory for req_ring.\n");
3496 goto fail_req_ring;
3497 }
3498 /* Allocate memory for response ring */
3499 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3500 if (!*rsp) {
3501 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3502 "Failed to allocate memory for rsp.\n");
3503 goto fail_rsp;
3504 }
3505 (*rsp)->hw = ha;
3506 (*rsp)->length = rsp_len;
3507 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3508 ((*rsp)->length + 1) * sizeof(response_t),
3509 &(*rsp)->dma, GFP_KERNEL);
3510 if (!(*rsp)->ring) {
3511 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3512 "Failed to allocate memory for rsp_ring.\n");
3513 goto fail_rsp_ring;
3514 }
3515 (*req)->rsp = *rsp;
3516 (*rsp)->req = *req;
3517 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3518 "req=%p req->length=%d req->ring=%p rsp=%p "
3519 "rsp->length=%d rsp->ring=%p.\n",
3520 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3521 (*rsp)->ring);
3522 /* Allocate memory for NVRAM data for vports */
3523 if (ha->nvram_npiv_size) {
3524 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
3525 ha->nvram_npiv_size, GFP_KERNEL);
3526 if (!ha->npiv_info) {
3527 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3528 "Failed to allocate memory for npiv_info.\n");
3529 goto fail_npiv_info;
3530 }
3531 } else
3532 ha->npiv_info = NULL;
3533
3534 /* Get consistent memory allocated for EX-INIT-CB. */
3535 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3536 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3537 &ha->ex_init_cb_dma);
3538 if (!ha->ex_init_cb)
3539 goto fail_ex_init_cb;
3540 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3541 "ex_init_cb=%p.\n", ha->ex_init_cb);
3542 }
3543
3544 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3545
3546 /* Get consistent memory allocated for Async Port-Database. */
3547 if (!IS_FWI2_CAPABLE(ha)) {
3548 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3549 &ha->async_pd_dma);
3550 if (!ha->async_pd)
3551 goto fail_async_pd;
3552 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3553 "async_pd=%p.\n", ha->async_pd);
3554 }
3555
3556 INIT_LIST_HEAD(&ha->vp_list);
3557
3558 /* Allocate memory for our loop_id bitmap */
3559 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3560 GFP_KERNEL);
3561 if (!ha->loop_id_map)
3562 goto fail_async_pd;
3563 else {
3564 qla2x00_set_reserved_loop_ids(ha);
3565 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3566 "loop_id_map=%p.\n", ha->loop_id_map);
3567 }
3568
3569 return 0;
3570
3571 fail_async_pd:
3572 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
3573 fail_ex_init_cb:
3574 kfree(ha->npiv_info);
3575 fail_npiv_info:
3576 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3577 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3578 (*rsp)->ring = NULL;
3579 (*rsp)->dma = 0;
3580 fail_rsp_ring:
3581 kfree(*rsp);
3582 fail_rsp:
3583 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3584 sizeof(request_t), (*req)->ring, (*req)->dma);
3585 (*req)->ring = NULL;
3586 (*req)->dma = 0;
3587 fail_req_ring:
3588 kfree(*req);
3589 fail_req:
3590 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3591 ha->ct_sns, ha->ct_sns_dma);
3592 ha->ct_sns = NULL;
3593 ha->ct_sns_dma = 0;
3594 fail_free_ms_iocb:
3595 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3596 ha->ms_iocb = NULL;
3597 ha->ms_iocb_dma = 0;
3598 fail_dma_pool:
3599 if (IS_QLA82XX(ha) || ql2xenabledif) {
3600 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3601 ha->fcp_cmnd_dma_pool = NULL;
3602 }
3603 fail_dl_dma_pool:
3604 if (IS_QLA82XX(ha) || ql2xenabledif) {
3605 dma_pool_destroy(ha->dl_dma_pool);
3606 ha->dl_dma_pool = NULL;
3607 }
3608 fail_s_dma_pool:
3609 dma_pool_destroy(ha->s_dma_pool);
3610 ha->s_dma_pool = NULL;
3611 fail_free_nvram:
3612 kfree(ha->nvram);
3613 ha->nvram = NULL;
3614 fail_free_ctx_mempool:
3615 mempool_destroy(ha->ctx_mempool);
3616 ha->ctx_mempool = NULL;
3617 fail_free_srb_mempool:
3618 mempool_destroy(ha->srb_mempool);
3619 ha->srb_mempool = NULL;
3620 fail_free_gid_list:
3621 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3622 ha->gid_list,
3623 ha->gid_list_dma);
3624 ha->gid_list = NULL;
3625 ha->gid_list_dma = 0;
3626 fail_free_tgt_mem:
3627 qlt_mem_free(ha);
3628 fail_free_init_cb:
3629 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3630 ha->init_cb_dma);
3631 ha->init_cb = NULL;
3632 ha->init_cb_dma = 0;
3633 fail:
3634 ql_log(ql_log_fatal, NULL, 0x0030,
3635 "Memory allocation failure.\n");
3636 return -ENOMEM;
3637 }
3638
3639 int
3640 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
3641 {
3642 int rval;
3643 uint16_t size, max_cnt, temp;
3644 struct qla_hw_data *ha = vha->hw;
3645
3646 /* Return if we don't need to alloacate any extended logins */
3647 if (!ql2xexlogins)
3648 return QLA_SUCCESS;
3649
3650 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
3651 max_cnt = 0;
3652 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
3653 if (rval != QLA_SUCCESS) {
3654 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
3655 "Failed to get exlogin status.\n");
3656 return rval;
3657 }
3658
3659 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
3660 ha->exlogin_size = (size * temp);
3661 ql_log(ql_log_info, vha, 0xd024,
3662 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
3663 max_cnt, size, temp);
3664
3665 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n",
3666 ha->exlogin_size);
3667
3668 /* Get consistent memory for extended logins */
3669 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
3670 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
3671 if (!ha->exlogin_buf) {
3672 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
3673 "Failed to allocate memory for exlogin_buf_dma.\n");
3674 return -ENOMEM;
3675 }
3676
3677 /* Now configure the dma buffer */
3678 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
3679 if (rval) {
3680 ql_log(ql_log_fatal, vha, 0x00cf,
3681 "Setup extended login buffer ****FAILED****.\n");
3682 qla2x00_free_exlogin_buffer(ha);
3683 }
3684
3685 return rval;
3686 }
3687
3688 /*
3689 * qla2x00_free_exlogin_buffer
3690 *
3691 * Input:
3692 * ha = adapter block pointer
3693 */
3694 void
3695 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
3696 {
3697 if (ha->exlogin_buf) {
3698 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
3699 ha->exlogin_buf, ha->exlogin_buf_dma);
3700 ha->exlogin_buf = NULL;
3701 ha->exlogin_size = 0;
3702 }
3703 }
3704
3705 int
3706 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
3707 {
3708 int rval;
3709 uint16_t size, max_cnt, temp;
3710 struct qla_hw_data *ha = vha->hw;
3711
3712 /* Return if we don't need to alloacate any extended logins */
3713 if (!ql2xexchoffld)
3714 return QLA_SUCCESS;
3715
3716 ql_log(ql_log_info, vha, 0xd014,
3717 "Exchange offload count: %d.\n", ql2xexlogins);
3718
3719 max_cnt = 0;
3720 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
3721 if (rval != QLA_SUCCESS) {
3722 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
3723 "Failed to get exlogin status.\n");
3724 return rval;
3725 }
3726
3727 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld;
3728 ha->exchoffld_size = (size * temp);
3729 ql_log(ql_log_info, vha, 0xd016,
3730 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
3731 max_cnt, size, temp);
3732
3733 ql_log(ql_log_info, vha, 0xd017,
3734 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size);
3735
3736 /* Get consistent memory for extended logins */
3737 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
3738 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
3739 if (!ha->exchoffld_buf) {
3740 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
3741 "Failed to allocate memory for exchoffld_buf_dma.\n");
3742 return -ENOMEM;
3743 }
3744
3745 /* Now configure the dma buffer */
3746 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma);
3747 if (rval) {
3748 ql_log(ql_log_fatal, vha, 0xd02e,
3749 "Setup exchange offload buffer ****FAILED****.\n");
3750 qla2x00_free_exchoffld_buffer(ha);
3751 }
3752
3753 return rval;
3754 }
3755
3756 /*
3757 * qla2x00_free_exchoffld_buffer
3758 *
3759 * Input:
3760 * ha = adapter block pointer
3761 */
3762 void
3763 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
3764 {
3765 if (ha->exchoffld_buf) {
3766 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
3767 ha->exchoffld_buf, ha->exchoffld_buf_dma);
3768 ha->exchoffld_buf = NULL;
3769 ha->exchoffld_size = 0;
3770 }
3771 }
3772
3773 /*
3774 * qla2x00_free_fw_dump
3775 * Frees fw dump stuff.
3776 *
3777 * Input:
3778 * ha = adapter block pointer
3779 */
3780 static void
3781 qla2x00_free_fw_dump(struct qla_hw_data *ha)
3782 {
3783 if (ha->fce)
3784 dma_free_coherent(&ha->pdev->dev,
3785 FCE_SIZE, ha->fce, ha->fce_dma);
3786
3787 if (ha->eft)
3788 dma_free_coherent(&ha->pdev->dev,
3789 EFT_SIZE, ha->eft, ha->eft_dma);
3790
3791 if (ha->fw_dump)
3792 vfree(ha->fw_dump);
3793 if (ha->fw_dump_template)
3794 vfree(ha->fw_dump_template);
3795
3796 ha->fce = NULL;
3797 ha->fce_dma = 0;
3798 ha->eft = NULL;
3799 ha->eft_dma = 0;
3800 ha->fw_dumped = 0;
3801 ha->fw_dump_cap_flags = 0;
3802 ha->fw_dump_reading = 0;
3803 ha->fw_dump = NULL;
3804 ha->fw_dump_len = 0;
3805 ha->fw_dump_template = NULL;
3806 ha->fw_dump_template_len = 0;
3807 }
3808
3809 /*
3810 * qla2x00_mem_free
3811 * Frees all adapter allocated memory.
3812 *
3813 * Input:
3814 * ha = adapter block pointer.
3815 */
3816 static void
3817 qla2x00_mem_free(struct qla_hw_data *ha)
3818 {
3819 qla2x00_free_fw_dump(ha);
3820
3821 if (ha->mctp_dump)
3822 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3823 ha->mctp_dump_dma);
3824
3825 if (ha->srb_mempool)
3826 mempool_destroy(ha->srb_mempool);
3827
3828 if (ha->dcbx_tlv)
3829 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3830 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3831
3832 if (ha->xgmac_data)
3833 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3834 ha->xgmac_data, ha->xgmac_data_dma);
3835
3836 if (ha->sns_cmd)
3837 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3838 ha->sns_cmd, ha->sns_cmd_dma);
3839
3840 if (ha->ct_sns)
3841 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3842 ha->ct_sns, ha->ct_sns_dma);
3843
3844 if (ha->sfp_data)
3845 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3846
3847 if (ha->ms_iocb)
3848 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3849
3850 if (ha->ex_init_cb)
3851 dma_pool_free(ha->s_dma_pool,
3852 ha->ex_init_cb, ha->ex_init_cb_dma);
3853
3854 if (ha->async_pd)
3855 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3856
3857 if (ha->s_dma_pool)
3858 dma_pool_destroy(ha->s_dma_pool);
3859
3860 if (ha->gid_list)
3861 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3862 ha->gid_list, ha->gid_list_dma);
3863
3864 if (IS_QLA82XX(ha)) {
3865 if (!list_empty(&ha->gbl_dsd_list)) {
3866 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3867
3868 /* clean up allocated prev pool */
3869 list_for_each_entry_safe(dsd_ptr,
3870 tdsd_ptr, &ha->gbl_dsd_list, list) {
3871 dma_pool_free(ha->dl_dma_pool,
3872 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3873 list_del(&dsd_ptr->list);
3874 kfree(dsd_ptr);
3875 }
3876 }
3877 }
3878
3879 if (ha->dl_dma_pool)
3880 dma_pool_destroy(ha->dl_dma_pool);
3881
3882 if (ha->fcp_cmnd_dma_pool)
3883 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3884
3885 if (ha->ctx_mempool)
3886 mempool_destroy(ha->ctx_mempool);
3887
3888 qlt_mem_free(ha);
3889
3890 if (ha->init_cb)
3891 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
3892 ha->init_cb, ha->init_cb_dma);
3893 vfree(ha->optrom_buffer);
3894 kfree(ha->nvram);
3895 kfree(ha->npiv_info);
3896 kfree(ha->swl);
3897 kfree(ha->loop_id_map);
3898
3899 ha->srb_mempool = NULL;
3900 ha->ctx_mempool = NULL;
3901 ha->sns_cmd = NULL;
3902 ha->sns_cmd_dma = 0;
3903 ha->ct_sns = NULL;
3904 ha->ct_sns_dma = 0;
3905 ha->ms_iocb = NULL;
3906 ha->ms_iocb_dma = 0;
3907 ha->init_cb = NULL;
3908 ha->init_cb_dma = 0;
3909 ha->ex_init_cb = NULL;
3910 ha->ex_init_cb_dma = 0;
3911 ha->async_pd = NULL;
3912 ha->async_pd_dma = 0;
3913
3914 ha->s_dma_pool = NULL;
3915 ha->dl_dma_pool = NULL;
3916 ha->fcp_cmnd_dma_pool = NULL;
3917
3918 ha->gid_list = NULL;
3919 ha->gid_list_dma = 0;
3920
3921 ha->tgt.atio_ring = NULL;
3922 ha->tgt.atio_dma = 0;
3923 ha->tgt.tgt_vp_map = NULL;
3924 }
3925
3926 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3927 struct qla_hw_data *ha)
3928 {
3929 struct Scsi_Host *host;
3930 struct scsi_qla_host *vha = NULL;
3931
3932 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3933 if (host == NULL) {
3934 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3935 "Failed to allocate host from the scsi layer, aborting.\n");
3936 goto fail;
3937 }
3938
3939 /* Clear our data area */
3940 vha = shost_priv(host);
3941 memset(vha, 0, sizeof(scsi_qla_host_t));
3942
3943 vha->host = host;
3944 vha->host_no = host->host_no;
3945 vha->hw = ha;
3946
3947 INIT_LIST_HEAD(&vha->vp_fcports);
3948 INIT_LIST_HEAD(&vha->work_list);
3949 INIT_LIST_HEAD(&vha->list);
3950 INIT_LIST_HEAD(&vha->qla_cmd_list);
3951 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
3952 INIT_LIST_HEAD(&vha->logo_list);
3953 INIT_LIST_HEAD(&vha->plogi_ack_list);
3954
3955 spin_lock_init(&vha->work_lock);
3956 spin_lock_init(&vha->cmd_list_lock);
3957
3958 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
3959 ql_dbg(ql_dbg_init, vha, 0x0041,
3960 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3961 vha->host, vha->hw, vha,
3962 dev_name(&(ha->pdev->dev)));
3963
3964 return vha;
3965
3966 fail:
3967 return vha;
3968 }
3969
3970 static struct qla_work_evt *
3971 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
3972 {
3973 struct qla_work_evt *e;
3974 uint8_t bail;
3975
3976 QLA_VHA_MARK_BUSY(vha, bail);
3977 if (bail)
3978 return NULL;
3979
3980 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
3981 if (!e) {
3982 QLA_VHA_MARK_NOT_BUSY(vha);
3983 return NULL;
3984 }
3985
3986 INIT_LIST_HEAD(&e->list);
3987 e->type = type;
3988 e->flags = QLA_EVT_FLAG_FREE;
3989 return e;
3990 }
3991
3992 static int
3993 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
3994 {
3995 unsigned long flags;
3996
3997 spin_lock_irqsave(&vha->work_lock, flags);
3998 list_add_tail(&e->list, &vha->work_list);
3999 spin_unlock_irqrestore(&vha->work_lock, flags);
4000 qla2xxx_wake_dpc(vha);
4001
4002 return QLA_SUCCESS;
4003 }
4004
4005 int
4006 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
4007 u32 data)
4008 {
4009 struct qla_work_evt *e;
4010
4011 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
4012 if (!e)
4013 return QLA_FUNCTION_FAILED;
4014
4015 e->u.aen.code = code;
4016 e->u.aen.data = data;
4017 return qla2x00_post_work(vha, e);
4018 }
4019
4020 int
4021 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4022 {
4023 struct qla_work_evt *e;
4024
4025 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
4026 if (!e)
4027 return QLA_FUNCTION_FAILED;
4028
4029 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4030 return qla2x00_post_work(vha, e);
4031 }
4032
4033 #define qla2x00_post_async_work(name, type) \
4034 int qla2x00_post_async_##name##_work( \
4035 struct scsi_qla_host *vha, \
4036 fc_port_t *fcport, uint16_t *data) \
4037 { \
4038 struct qla_work_evt *e; \
4039 \
4040 e = qla2x00_alloc_work(vha, type); \
4041 if (!e) \
4042 return QLA_FUNCTION_FAILED; \
4043 \
4044 e->u.logio.fcport = fcport; \
4045 if (data) { \
4046 e->u.logio.data[0] = data[0]; \
4047 e->u.logio.data[1] = data[1]; \
4048 } \
4049 return qla2x00_post_work(vha, e); \
4050 }
4051
4052 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
4053 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
4054 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4055 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
4056 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4057 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
4058
4059 int
4060 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4061 {
4062 struct qla_work_evt *e;
4063
4064 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4065 if (!e)
4066 return QLA_FUNCTION_FAILED;
4067
4068 e->u.uevent.code = code;
4069 return qla2x00_post_work(vha, e);
4070 }
4071
4072 static void
4073 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4074 {
4075 char event_string[40];
4076 char *envp[] = { event_string, NULL };
4077
4078 switch (code) {
4079 case QLA_UEVENT_CODE_FW_DUMP:
4080 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4081 vha->host_no);
4082 break;
4083 default:
4084 /* do nothing */
4085 break;
4086 }
4087 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4088 }
4089
4090 int
4091 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4092 uint32_t *data, int cnt)
4093 {
4094 struct qla_work_evt *e;
4095
4096 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4097 if (!e)
4098 return QLA_FUNCTION_FAILED;
4099
4100 e->u.aenfx.evtcode = evtcode;
4101 e->u.aenfx.count = cnt;
4102 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4103 return qla2x00_post_work(vha, e);
4104 }
4105
4106 void
4107 qla2x00_do_work(struct scsi_qla_host *vha)
4108 {
4109 struct qla_work_evt *e, *tmp;
4110 unsigned long flags;
4111 LIST_HEAD(work);
4112
4113 spin_lock_irqsave(&vha->work_lock, flags);
4114 list_splice_init(&vha->work_list, &work);
4115 spin_unlock_irqrestore(&vha->work_lock, flags);
4116
4117 list_for_each_entry_safe(e, tmp, &work, list) {
4118 list_del_init(&e->list);
4119
4120 switch (e->type) {
4121 case QLA_EVT_AEN:
4122 fc_host_post_event(vha->host, fc_get_event_number(),
4123 e->u.aen.code, e->u.aen.data);
4124 break;
4125 case QLA_EVT_IDC_ACK:
4126 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4127 break;
4128 case QLA_EVT_ASYNC_LOGIN:
4129 qla2x00_async_login(vha, e->u.logio.fcport,
4130 e->u.logio.data);
4131 break;
4132 case QLA_EVT_ASYNC_LOGIN_DONE:
4133 qla2x00_async_login_done(vha, e->u.logio.fcport,
4134 e->u.logio.data);
4135 break;
4136 case QLA_EVT_ASYNC_LOGOUT:
4137 qla2x00_async_logout(vha, e->u.logio.fcport);
4138 break;
4139 case QLA_EVT_ASYNC_LOGOUT_DONE:
4140 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4141 e->u.logio.data);
4142 break;
4143 case QLA_EVT_ASYNC_ADISC:
4144 qla2x00_async_adisc(vha, e->u.logio.fcport,
4145 e->u.logio.data);
4146 break;
4147 case QLA_EVT_ASYNC_ADISC_DONE:
4148 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4149 e->u.logio.data);
4150 break;
4151 case QLA_EVT_UEVENT:
4152 qla2x00_uevent_emit(vha, e->u.uevent.code);
4153 break;
4154 case QLA_EVT_AENFX:
4155 qlafx00_process_aen(vha, e);
4156 break;
4157 }
4158 if (e->flags & QLA_EVT_FLAG_FREE)
4159 kfree(e);
4160
4161 /* For each work completed decrement vha ref count */
4162 QLA_VHA_MARK_NOT_BUSY(vha);
4163 }
4164 }
4165
4166 /* Relogins all the fcports of a vport
4167 * Context: dpc thread
4168 */
4169 void qla2x00_relogin(struct scsi_qla_host *vha)
4170 {
4171 fc_port_t *fcport;
4172 int status;
4173 uint16_t next_loopid = 0;
4174 struct qla_hw_data *ha = vha->hw;
4175 uint16_t data[2];
4176
4177 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4178 /*
4179 * If the port is not ONLINE then try to login
4180 * to it if we haven't run out of retries.
4181 */
4182 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4183 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
4184 fcport->login_retry--;
4185 if (fcport->flags & FCF_FABRIC_DEVICE) {
4186 if (fcport->flags & FCF_FCP2_DEVICE)
4187 ha->isp_ops->fabric_logout(vha,
4188 fcport->loop_id,
4189 fcport->d_id.b.domain,
4190 fcport->d_id.b.area,
4191 fcport->d_id.b.al_pa);
4192
4193 if (fcport->loop_id == FC_NO_LOOP_ID) {
4194 fcport->loop_id = next_loopid =
4195 ha->min_external_loopid;
4196 status = qla2x00_find_new_loop_id(
4197 vha, fcport);
4198 if (status != QLA_SUCCESS) {
4199 /* Ran out of IDs to use */
4200 break;
4201 }
4202 }
4203
4204 if (IS_ALOGIO_CAPABLE(ha)) {
4205 fcport->flags |= FCF_ASYNC_SENT;
4206 data[0] = 0;
4207 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4208 status = qla2x00_post_async_login_work(
4209 vha, fcport, data);
4210 if (status == QLA_SUCCESS)
4211 continue;
4212 /* Attempt a retry. */
4213 status = 1;
4214 } else {
4215 status = qla2x00_fabric_login(vha,
4216 fcport, &next_loopid);
4217 if (status == QLA_SUCCESS) {
4218 int status2;
4219 uint8_t opts;
4220
4221 opts = 0;
4222 if (fcport->flags &
4223 FCF_FCP2_DEVICE)
4224 opts |= BIT_1;
4225 status2 =
4226 qla2x00_get_port_database(
4227 vha, fcport, opts);
4228 if (status2 != QLA_SUCCESS)
4229 status = 1;
4230 }
4231 }
4232 } else
4233 status = qla2x00_local_device_login(vha,
4234 fcport);
4235
4236 if (status == QLA_SUCCESS) {
4237 fcport->old_loop_id = fcport->loop_id;
4238
4239 ql_dbg(ql_dbg_disc, vha, 0x2003,
4240 "Port login OK: logged in ID 0x%x.\n",
4241 fcport->loop_id);
4242
4243 qla2x00_update_fcport(vha, fcport);
4244
4245 } else if (status == 1) {
4246 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4247 /* retry the login again */
4248 ql_dbg(ql_dbg_disc, vha, 0x2007,
4249 "Retrying %d login again loop_id 0x%x.\n",
4250 fcport->login_retry, fcport->loop_id);
4251 } else {
4252 fcport->login_retry = 0;
4253 }
4254
4255 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
4256 qla2x00_clear_loop_id(fcport);
4257 }
4258 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4259 break;
4260 }
4261 }
4262
4263 /* Schedule work on any of the dpc-workqueues */
4264 void
4265 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4266 {
4267 struct qla_hw_data *ha = base_vha->hw;
4268
4269 switch (work_code) {
4270 case MBA_IDC_AEN: /* 0x8200 */
4271 if (ha->dpc_lp_wq)
4272 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4273 break;
4274
4275 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4276 if (!ha->flags.nic_core_reset_hdlr_active) {
4277 if (ha->dpc_hp_wq)
4278 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4279 } else
4280 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4281 "NIC Core reset is already active. Skip "
4282 "scheduling it again.\n");
4283 break;
4284 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4285 if (ha->dpc_hp_wq)
4286 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4287 break;
4288 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4289 if (ha->dpc_hp_wq)
4290 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4291 break;
4292 default:
4293 ql_log(ql_log_warn, base_vha, 0xb05f,
4294 "Unknown work-code=0x%x.\n", work_code);
4295 }
4296
4297 return;
4298 }
4299
4300 /* Work: Perform NIC Core Unrecoverable state handling */
4301 void
4302 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4303 {
4304 struct qla_hw_data *ha =
4305 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
4306 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4307 uint32_t dev_state = 0;
4308
4309 qla83xx_idc_lock(base_vha, 0);
4310 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4311 qla83xx_reset_ownership(base_vha);
4312 if (ha->flags.nic_core_reset_owner) {
4313 ha->flags.nic_core_reset_owner = 0;
4314 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4315 QLA8XXX_DEV_FAILED);
4316 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4317 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4318 }
4319 qla83xx_idc_unlock(base_vha, 0);
4320 }
4321
4322 /* Work: Execute IDC state handler */
4323 void
4324 qla83xx_idc_state_handler_work(struct work_struct *work)
4325 {
4326 struct qla_hw_data *ha =
4327 container_of(work, struct qla_hw_data, idc_state_handler);
4328 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4329 uint32_t dev_state = 0;
4330
4331 qla83xx_idc_lock(base_vha, 0);
4332 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4333 if (dev_state == QLA8XXX_DEV_FAILED ||
4334 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4335 qla83xx_idc_state_handler(base_vha);
4336 qla83xx_idc_unlock(base_vha, 0);
4337 }
4338
4339 static int
4340 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4341 {
4342 int rval = QLA_SUCCESS;
4343 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4344 uint32_t heart_beat_counter1, heart_beat_counter2;
4345
4346 do {
4347 if (time_after(jiffies, heart_beat_wait)) {
4348 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4349 "Nic Core f/w is not alive.\n");
4350 rval = QLA_FUNCTION_FAILED;
4351 break;
4352 }
4353
4354 qla83xx_idc_lock(base_vha, 0);
4355 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4356 &heart_beat_counter1);
4357 qla83xx_idc_unlock(base_vha, 0);
4358 msleep(100);
4359 qla83xx_idc_lock(base_vha, 0);
4360 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4361 &heart_beat_counter2);
4362 qla83xx_idc_unlock(base_vha, 0);
4363 } while (heart_beat_counter1 == heart_beat_counter2);
4364
4365 return rval;
4366 }
4367
4368 /* Work: Perform NIC Core Reset handling */
4369 void
4370 qla83xx_nic_core_reset_work(struct work_struct *work)
4371 {
4372 struct qla_hw_data *ha =
4373 container_of(work, struct qla_hw_data, nic_core_reset);
4374 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4375 uint32_t dev_state = 0;
4376
4377 if (IS_QLA2031(ha)) {
4378 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4379 ql_log(ql_log_warn, base_vha, 0xb081,
4380 "Failed to dump mctp\n");
4381 return;
4382 }
4383
4384 if (!ha->flags.nic_core_reset_hdlr_active) {
4385 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4386 qla83xx_idc_lock(base_vha, 0);
4387 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4388 &dev_state);
4389 qla83xx_idc_unlock(base_vha, 0);
4390 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4391 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4392 "Nic Core f/w is alive.\n");
4393 return;
4394 }
4395 }
4396
4397 ha->flags.nic_core_reset_hdlr_active = 1;
4398 if (qla83xx_nic_core_reset(base_vha)) {
4399 /* NIC Core reset failed. */
4400 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4401 "NIC Core reset failed.\n");
4402 }
4403 ha->flags.nic_core_reset_hdlr_active = 0;
4404 }
4405 }
4406
4407 /* Work: Handle 8200 IDC aens */
4408 void
4409 qla83xx_service_idc_aen(struct work_struct *work)
4410 {
4411 struct qla_hw_data *ha =
4412 container_of(work, struct qla_hw_data, idc_aen);
4413 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4414 uint32_t dev_state, idc_control;
4415
4416 qla83xx_idc_lock(base_vha, 0);
4417 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4418 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4419 qla83xx_idc_unlock(base_vha, 0);
4420 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4421 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4422 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4423 "Application requested NIC Core Reset.\n");
4424 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4425 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4426 QLA_SUCCESS) {
4427 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4428 "Other protocol driver requested NIC Core Reset.\n");
4429 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4430 }
4431 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4432 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4433 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4434 }
4435 }
4436
4437 static void
4438 qla83xx_wait_logic(void)
4439 {
4440 int i;
4441
4442 /* Yield CPU */
4443 if (!in_interrupt()) {
4444 /*
4445 * Wait about 200ms before retrying again.
4446 * This controls the number of retries for single
4447 * lock operation.
4448 */
4449 msleep(100);
4450 schedule();
4451 } else {
4452 for (i = 0; i < 20; i++)
4453 cpu_relax(); /* This a nop instr on i386 */
4454 }
4455 }
4456
4457 static int
4458 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4459 {
4460 int rval;
4461 uint32_t data;
4462 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4463 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4464 struct qla_hw_data *ha = base_vha->hw;
4465 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4466 "Trying force recovery of the IDC lock.\n");
4467
4468 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4469 if (rval)
4470 return rval;
4471
4472 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4473 return QLA_SUCCESS;
4474 } else {
4475 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4476 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4477 data);
4478 if (rval)
4479 return rval;
4480
4481 msleep(200);
4482
4483 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4484 &data);
4485 if (rval)
4486 return rval;
4487
4488 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4489 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4490 ~(idc_lck_rcvry_stage_mask));
4491 rval = qla83xx_wr_reg(base_vha,
4492 QLA83XX_IDC_LOCK_RECOVERY, data);
4493 if (rval)
4494 return rval;
4495
4496 /* Forcefully perform IDC UnLock */
4497 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4498 &data);
4499 if (rval)
4500 return rval;
4501 /* Clear lock-id by setting 0xff */
4502 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4503 0xff);
4504 if (rval)
4505 return rval;
4506 /* Clear lock-recovery by setting 0x0 */
4507 rval = qla83xx_wr_reg(base_vha,
4508 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4509 if (rval)
4510 return rval;
4511 } else
4512 return QLA_SUCCESS;
4513 }
4514
4515 return rval;
4516 }
4517
4518 static int
4519 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4520 {
4521 int rval = QLA_SUCCESS;
4522 uint32_t o_drv_lockid, n_drv_lockid;
4523 unsigned long lock_recovery_timeout;
4524
4525 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4526 retry_lockid:
4527 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4528 if (rval)
4529 goto exit;
4530
4531 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4532 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4533 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4534 return QLA_SUCCESS;
4535 else
4536 return QLA_FUNCTION_FAILED;
4537 }
4538
4539 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4540 if (rval)
4541 goto exit;
4542
4543 if (o_drv_lockid == n_drv_lockid) {
4544 qla83xx_wait_logic();
4545 goto retry_lockid;
4546 } else
4547 return QLA_SUCCESS;
4548
4549 exit:
4550 return rval;
4551 }
4552
4553 void
4554 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4555 {
4556 uint16_t options = (requester_id << 15) | BIT_6;
4557 uint32_t data;
4558 uint32_t lock_owner;
4559 struct qla_hw_data *ha = base_vha->hw;
4560
4561 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4562 retry_lock:
4563 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4564 == QLA_SUCCESS) {
4565 if (data) {
4566 /* Setting lock-id to our function-number */
4567 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4568 ha->portnum);
4569 } else {
4570 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4571 &lock_owner);
4572 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
4573 "Failed to acquire IDC lock, acquired by %d, "
4574 "retrying...\n", lock_owner);
4575
4576 /* Retry/Perform IDC-Lock recovery */
4577 if (qla83xx_idc_lock_recovery(base_vha)
4578 == QLA_SUCCESS) {
4579 qla83xx_wait_logic();
4580 goto retry_lock;
4581 } else
4582 ql_log(ql_log_warn, base_vha, 0xb075,
4583 "IDC Lock recovery FAILED.\n");
4584 }
4585
4586 }
4587
4588 return;
4589
4590 /* XXX: IDC-lock implementation using access-control mbx */
4591 retry_lock2:
4592 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4593 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4594 "Failed to acquire IDC lock. retrying...\n");
4595 /* Retry/Perform IDC-Lock recovery */
4596 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4597 qla83xx_wait_logic();
4598 goto retry_lock2;
4599 } else
4600 ql_log(ql_log_warn, base_vha, 0xb076,
4601 "IDC Lock recovery FAILED.\n");
4602 }
4603
4604 return;
4605 }
4606
4607 void
4608 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4609 {
4610 #if 0
4611 uint16_t options = (requester_id << 15) | BIT_7;
4612 #endif
4613 uint16_t retry;
4614 uint32_t data;
4615 struct qla_hw_data *ha = base_vha->hw;
4616
4617 /* IDC-unlock implementation using driver-unlock/lock-id
4618 * remote registers
4619 */
4620 retry = 0;
4621 retry_unlock:
4622 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4623 == QLA_SUCCESS) {
4624 if (data == ha->portnum) {
4625 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4626 /* Clearing lock-id by setting 0xff */
4627 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4628 } else if (retry < 10) {
4629 /* SV: XXX: IDC unlock retrying needed here? */
4630
4631 /* Retry for IDC-unlock */
4632 qla83xx_wait_logic();
4633 retry++;
4634 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4635 "Failed to release IDC lock, retyring=%d\n", retry);
4636 goto retry_unlock;
4637 }
4638 } else if (retry < 10) {
4639 /* Retry for IDC-unlock */
4640 qla83xx_wait_logic();
4641 retry++;
4642 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4643 "Failed to read drv-lockid, retyring=%d\n", retry);
4644 goto retry_unlock;
4645 }
4646
4647 return;
4648
4649 #if 0
4650 /* XXX: IDC-unlock implementation using access-control mbx */
4651 retry = 0;
4652 retry_unlock2:
4653 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4654 if (retry < 10) {
4655 /* Retry for IDC-unlock */
4656 qla83xx_wait_logic();
4657 retry++;
4658 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4659 "Failed to release IDC lock, retyring=%d\n", retry);
4660 goto retry_unlock2;
4661 }
4662 }
4663
4664 return;
4665 #endif
4666 }
4667
4668 int
4669 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4670 {
4671 int rval = QLA_SUCCESS;
4672 struct qla_hw_data *ha = vha->hw;
4673 uint32_t drv_presence;
4674
4675 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4676 if (rval == QLA_SUCCESS) {
4677 drv_presence |= (1 << ha->portnum);
4678 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4679 drv_presence);
4680 }
4681
4682 return rval;
4683 }
4684
4685 int
4686 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4687 {
4688 int rval = QLA_SUCCESS;
4689
4690 qla83xx_idc_lock(vha, 0);
4691 rval = __qla83xx_set_drv_presence(vha);
4692 qla83xx_idc_unlock(vha, 0);
4693
4694 return rval;
4695 }
4696
4697 int
4698 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4699 {
4700 int rval = QLA_SUCCESS;
4701 struct qla_hw_data *ha = vha->hw;
4702 uint32_t drv_presence;
4703
4704 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4705 if (rval == QLA_SUCCESS) {
4706 drv_presence &= ~(1 << ha->portnum);
4707 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4708 drv_presence);
4709 }
4710
4711 return rval;
4712 }
4713
4714 int
4715 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4716 {
4717 int rval = QLA_SUCCESS;
4718
4719 qla83xx_idc_lock(vha, 0);
4720 rval = __qla83xx_clear_drv_presence(vha);
4721 qla83xx_idc_unlock(vha, 0);
4722
4723 return rval;
4724 }
4725
4726 static void
4727 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4728 {
4729 struct qla_hw_data *ha = vha->hw;
4730 uint32_t drv_ack, drv_presence;
4731 unsigned long ack_timeout;
4732
4733 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4734 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4735 while (1) {
4736 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4737 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4738 if ((drv_ack & drv_presence) == drv_presence)
4739 break;
4740
4741 if (time_after_eq(jiffies, ack_timeout)) {
4742 ql_log(ql_log_warn, vha, 0xb067,
4743 "RESET ACK TIMEOUT! drv_presence=0x%x "
4744 "drv_ack=0x%x\n", drv_presence, drv_ack);
4745 /*
4746 * The function(s) which did not ack in time are forced
4747 * to withdraw any further participation in the IDC
4748 * reset.
4749 */
4750 if (drv_ack != drv_presence)
4751 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4752 drv_ack);
4753 break;
4754 }
4755
4756 qla83xx_idc_unlock(vha, 0);
4757 msleep(1000);
4758 qla83xx_idc_lock(vha, 0);
4759 }
4760
4761 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4762 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4763 }
4764
4765 static int
4766 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4767 {
4768 int rval = QLA_SUCCESS;
4769 uint32_t idc_control;
4770
4771 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4772 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4773
4774 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4775 __qla83xx_get_idc_control(vha, &idc_control);
4776 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4777 __qla83xx_set_idc_control(vha, 0);
4778
4779 qla83xx_idc_unlock(vha, 0);
4780 rval = qla83xx_restart_nic_firmware(vha);
4781 qla83xx_idc_lock(vha, 0);
4782
4783 if (rval != QLA_SUCCESS) {
4784 ql_log(ql_log_fatal, vha, 0xb06a,
4785 "Failed to restart NIC f/w.\n");
4786 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4787 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4788 } else {
4789 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4790 "Success in restarting nic f/w.\n");
4791 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4792 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4793 }
4794
4795 return rval;
4796 }
4797
4798 /* Assumes idc_lock always held on entry */
4799 int
4800 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4801 {
4802 struct qla_hw_data *ha = base_vha->hw;
4803 int rval = QLA_SUCCESS;
4804 unsigned long dev_init_timeout;
4805 uint32_t dev_state;
4806
4807 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4808 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4809
4810 while (1) {
4811
4812 if (time_after_eq(jiffies, dev_init_timeout)) {
4813 ql_log(ql_log_warn, base_vha, 0xb06e,
4814 "Initialization TIMEOUT!\n");
4815 /* Init timeout. Disable further NIC Core
4816 * communication.
4817 */
4818 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4819 QLA8XXX_DEV_FAILED);
4820 ql_log(ql_log_info, base_vha, 0xb06f,
4821 "HW State: FAILED.\n");
4822 }
4823
4824 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4825 switch (dev_state) {
4826 case QLA8XXX_DEV_READY:
4827 if (ha->flags.nic_core_reset_owner)
4828 qla83xx_idc_audit(base_vha,
4829 IDC_AUDIT_COMPLETION);
4830 ha->flags.nic_core_reset_owner = 0;
4831 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4832 "Reset_owner reset by 0x%x.\n",
4833 ha->portnum);
4834 goto exit;
4835 case QLA8XXX_DEV_COLD:
4836 if (ha->flags.nic_core_reset_owner)
4837 rval = qla83xx_device_bootstrap(base_vha);
4838 else {
4839 /* Wait for AEN to change device-state */
4840 qla83xx_idc_unlock(base_vha, 0);
4841 msleep(1000);
4842 qla83xx_idc_lock(base_vha, 0);
4843 }
4844 break;
4845 case QLA8XXX_DEV_INITIALIZING:
4846 /* Wait for AEN to change device-state */
4847 qla83xx_idc_unlock(base_vha, 0);
4848 msleep(1000);
4849 qla83xx_idc_lock(base_vha, 0);
4850 break;
4851 case QLA8XXX_DEV_NEED_RESET:
4852 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4853 qla83xx_need_reset_handler(base_vha);
4854 else {
4855 /* Wait for AEN to change device-state */
4856 qla83xx_idc_unlock(base_vha, 0);
4857 msleep(1000);
4858 qla83xx_idc_lock(base_vha, 0);
4859 }
4860 /* reset timeout value after need reset handler */
4861 dev_init_timeout = jiffies +
4862 (ha->fcoe_dev_init_timeout * HZ);
4863 break;
4864 case QLA8XXX_DEV_NEED_QUIESCENT:
4865 /* XXX: DEBUG for now */
4866 qla83xx_idc_unlock(base_vha, 0);
4867 msleep(1000);
4868 qla83xx_idc_lock(base_vha, 0);
4869 break;
4870 case QLA8XXX_DEV_QUIESCENT:
4871 /* XXX: DEBUG for now */
4872 if (ha->flags.quiesce_owner)
4873 goto exit;
4874
4875 qla83xx_idc_unlock(base_vha, 0);
4876 msleep(1000);
4877 qla83xx_idc_lock(base_vha, 0);
4878 dev_init_timeout = jiffies +
4879 (ha->fcoe_dev_init_timeout * HZ);
4880 break;
4881 case QLA8XXX_DEV_FAILED:
4882 if (ha->flags.nic_core_reset_owner)
4883 qla83xx_idc_audit(base_vha,
4884 IDC_AUDIT_COMPLETION);
4885 ha->flags.nic_core_reset_owner = 0;
4886 __qla83xx_clear_drv_presence(base_vha);
4887 qla83xx_idc_unlock(base_vha, 0);
4888 qla8xxx_dev_failed_handler(base_vha);
4889 rval = QLA_FUNCTION_FAILED;
4890 qla83xx_idc_lock(base_vha, 0);
4891 goto exit;
4892 case QLA8XXX_BAD_VALUE:
4893 qla83xx_idc_unlock(base_vha, 0);
4894 msleep(1000);
4895 qla83xx_idc_lock(base_vha, 0);
4896 break;
4897 default:
4898 ql_log(ql_log_warn, base_vha, 0xb071,
4899 "Unknown Device State: %x.\n", dev_state);
4900 qla83xx_idc_unlock(base_vha, 0);
4901 qla8xxx_dev_failed_handler(base_vha);
4902 rval = QLA_FUNCTION_FAILED;
4903 qla83xx_idc_lock(base_vha, 0);
4904 goto exit;
4905 }
4906 }
4907
4908 exit:
4909 return rval;
4910 }
4911
4912 void
4913 qla2x00_disable_board_on_pci_error(struct work_struct *work)
4914 {
4915 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4916 board_disable);
4917 struct pci_dev *pdev = ha->pdev;
4918 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4919
4920 ql_log(ql_log_warn, base_vha, 0x015b,
4921 "Disabling adapter.\n");
4922
4923 set_bit(UNLOADING, &base_vha->dpc_flags);
4924
4925 qla2x00_delete_all_vps(ha, base_vha);
4926
4927 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4928
4929 qla2x00_dfs_remove(base_vha);
4930
4931 qla84xx_put_chip(base_vha);
4932
4933 if (base_vha->timer_active)
4934 qla2x00_stop_timer(base_vha);
4935
4936 base_vha->flags.online = 0;
4937
4938 qla2x00_destroy_deferred_work(ha);
4939
4940 /*
4941 * Do not try to stop beacon blink as it will issue a mailbox
4942 * command.
4943 */
4944 qla2x00_free_sysfs_attr(base_vha, false);
4945
4946 fc_remove_host(base_vha->host);
4947
4948 scsi_remove_host(base_vha->host);
4949
4950 base_vha->flags.init_done = 0;
4951 qla25xx_delete_queues(base_vha);
4952 qla2x00_free_irqs(base_vha);
4953 qla2x00_free_fcports(base_vha);
4954 qla2x00_mem_free(ha);
4955 qla82xx_md_free(base_vha);
4956 qla2x00_free_queues(ha);
4957
4958 qla2x00_unmap_iobases(ha);
4959
4960 pci_release_selected_regions(ha->pdev, ha->bars);
4961 pci_disable_pcie_error_reporting(pdev);
4962 pci_disable_device(pdev);
4963
4964 /*
4965 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
4966 */
4967 }
4968
4969 /**************************************************************************
4970 * qla2x00_do_dpc
4971 * This kernel thread is a task that is schedule by the interrupt handler
4972 * to perform the background processing for interrupts.
4973 *
4974 * Notes:
4975 * This task always run in the context of a kernel thread. It
4976 * is kick-off by the driver's detect code and starts up
4977 * up one per adapter. It immediately goes to sleep and waits for
4978 * some fibre event. When either the interrupt handler or
4979 * the timer routine detects a event it will one of the task
4980 * bits then wake us up.
4981 **************************************************************************/
4982 static int
4983 qla2x00_do_dpc(void *data)
4984 {
4985 scsi_qla_host_t *base_vha;
4986 struct qla_hw_data *ha;
4987
4988 ha = (struct qla_hw_data *)data;
4989 base_vha = pci_get_drvdata(ha->pdev);
4990
4991 set_user_nice(current, MIN_NICE);
4992
4993 set_current_state(TASK_INTERRUPTIBLE);
4994 while (!kthread_should_stop()) {
4995 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4996 "DPC handler sleeping.\n");
4997
4998 schedule();
4999
5000 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5001 goto end_loop;
5002
5003 if (ha->flags.eeh_busy) {
5004 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5005 "eeh_busy=%d.\n", ha->flags.eeh_busy);
5006 goto end_loop;
5007 }
5008
5009 ha->dpc_active = 1;
5010
5011 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5012 "DPC handler waking up, dpc_flags=0x%lx.\n",
5013 base_vha->dpc_flags);
5014
5015 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5016 break;
5017
5018 qla2x00_do_work(base_vha);
5019
5020 if (IS_P3P_TYPE(ha)) {
5021 if (IS_QLA8044(ha)) {
5022 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5023 &base_vha->dpc_flags)) {
5024 qla8044_idc_lock(ha);
5025 qla8044_wr_direct(base_vha,
5026 QLA8044_CRB_DEV_STATE_INDEX,
5027 QLA8XXX_DEV_FAILED);
5028 qla8044_idc_unlock(ha);
5029 ql_log(ql_log_info, base_vha, 0x4004,
5030 "HW State: FAILED.\n");
5031 qla8044_device_state_handler(base_vha);
5032 continue;
5033 }
5034
5035 } else {
5036 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5037 &base_vha->dpc_flags)) {
5038 qla82xx_idc_lock(ha);
5039 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5040 QLA8XXX_DEV_FAILED);
5041 qla82xx_idc_unlock(ha);
5042 ql_log(ql_log_info, base_vha, 0x0151,
5043 "HW State: FAILED.\n");
5044 qla82xx_device_state_handler(base_vha);
5045 continue;
5046 }
5047 }
5048
5049 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5050 &base_vha->dpc_flags)) {
5051
5052 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5053 "FCoE context reset scheduled.\n");
5054 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5055 &base_vha->dpc_flags))) {
5056 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5057 /* FCoE-ctx reset failed.
5058 * Escalate to chip-reset
5059 */
5060 set_bit(ISP_ABORT_NEEDED,
5061 &base_vha->dpc_flags);
5062 }
5063 clear_bit(ABORT_ISP_ACTIVE,
5064 &base_vha->dpc_flags);
5065 }
5066
5067 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5068 "FCoE context reset end.\n");
5069 }
5070 } else if (IS_QLAFX00(ha)) {
5071 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5072 &base_vha->dpc_flags)) {
5073 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5074 "Firmware Reset Recovery\n");
5075 if (qlafx00_reset_initialize(base_vha)) {
5076 /* Failed. Abort isp later. */
5077 if (!test_bit(UNLOADING,
5078 &base_vha->dpc_flags)) {
5079 set_bit(ISP_UNRECOVERABLE,
5080 &base_vha->dpc_flags);
5081 ql_dbg(ql_dbg_dpc, base_vha,
5082 0x4021,
5083 "Reset Recovery Failed\n");
5084 }
5085 }
5086 }
5087
5088 if (test_and_clear_bit(FX00_TARGET_SCAN,
5089 &base_vha->dpc_flags)) {
5090 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5091 "ISPFx00 Target Scan scheduled\n");
5092 if (qlafx00_rescan_isp(base_vha)) {
5093 if (!test_bit(UNLOADING,
5094 &base_vha->dpc_flags))
5095 set_bit(ISP_UNRECOVERABLE,
5096 &base_vha->dpc_flags);
5097 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5098 "ISPFx00 Target Scan Failed\n");
5099 }
5100 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5101 "ISPFx00 Target Scan End\n");
5102 }
5103 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5104 &base_vha->dpc_flags)) {
5105 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5106 "ISPFx00 Host Info resend scheduled\n");
5107 qlafx00_fx_disc(base_vha,
5108 &base_vha->hw->mr.fcport,
5109 FXDISC_REG_HOST_INFO);
5110 }
5111 }
5112
5113 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5114 &base_vha->dpc_flags)) {
5115
5116 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5117 "ISP abort scheduled.\n");
5118 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5119 &base_vha->dpc_flags))) {
5120
5121 if (ha->isp_ops->abort_isp(base_vha)) {
5122 /* failed. retry later */
5123 set_bit(ISP_ABORT_NEEDED,
5124 &base_vha->dpc_flags);
5125 }
5126 clear_bit(ABORT_ISP_ACTIVE,
5127 &base_vha->dpc_flags);
5128 }
5129
5130 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5131 "ISP abort end.\n");
5132 }
5133
5134 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5135 &base_vha->dpc_flags)) {
5136 qla2x00_update_fcports(base_vha);
5137 }
5138
5139 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
5140 int ret;
5141 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
5142 if (ret != QLA_SUCCESS)
5143 ql_log(ql_log_warn, base_vha, 0x121,
5144 "Failed to enable receiving of RSCN "
5145 "requests: 0x%x.\n", ret);
5146 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
5147 }
5148
5149 if (IS_QLAFX00(ha))
5150 goto loop_resync_check;
5151
5152 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
5153 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5154 "Quiescence mode scheduled.\n");
5155 if (IS_P3P_TYPE(ha)) {
5156 if (IS_QLA82XX(ha))
5157 qla82xx_device_state_handler(base_vha);
5158 if (IS_QLA8044(ha))
5159 qla8044_device_state_handler(base_vha);
5160 clear_bit(ISP_QUIESCE_NEEDED,
5161 &base_vha->dpc_flags);
5162 if (!ha->flags.quiesce_owner) {
5163 qla2x00_perform_loop_resync(base_vha);
5164 if (IS_QLA82XX(ha)) {
5165 qla82xx_idc_lock(ha);
5166 qla82xx_clear_qsnt_ready(
5167 base_vha);
5168 qla82xx_idc_unlock(ha);
5169 } else if (IS_QLA8044(ha)) {
5170 qla8044_idc_lock(ha);
5171 qla8044_clear_qsnt_ready(
5172 base_vha);
5173 qla8044_idc_unlock(ha);
5174 }
5175 }
5176 } else {
5177 clear_bit(ISP_QUIESCE_NEEDED,
5178 &base_vha->dpc_flags);
5179 qla2x00_quiesce_io(base_vha);
5180 }
5181 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5182 "Quiescence mode end.\n");
5183 }
5184
5185 if (test_and_clear_bit(RESET_MARKER_NEEDED,
5186 &base_vha->dpc_flags) &&
5187 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
5188
5189 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5190 "Reset marker scheduled.\n");
5191 qla2x00_rst_aen(base_vha);
5192 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
5193 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5194 "Reset marker end.\n");
5195 }
5196
5197 /* Retry each device up to login retry count */
5198 if ((test_and_clear_bit(RELOGIN_NEEDED,
5199 &base_vha->dpc_flags)) &&
5200 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5201 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
5202
5203 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5204 "Relogin scheduled.\n");
5205 qla2x00_relogin(base_vha);
5206 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5207 "Relogin end.\n");
5208 }
5209 loop_resync_check:
5210 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
5211 &base_vha->dpc_flags)) {
5212
5213 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5214 "Loop resync scheduled.\n");
5215
5216 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
5217 &base_vha->dpc_flags))) {
5218
5219 qla2x00_loop_resync(base_vha);
5220
5221 clear_bit(LOOP_RESYNC_ACTIVE,
5222 &base_vha->dpc_flags);
5223 }
5224
5225 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5226 "Loop resync end.\n");
5227 }
5228
5229 if (IS_QLAFX00(ha))
5230 goto intr_on_check;
5231
5232 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5233 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5234 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5235 qla2xxx_flash_npiv_conf(base_vha);
5236 }
5237
5238 intr_on_check:
5239 if (!ha->interrupts_on)
5240 ha->isp_ops->enable_intrs(ha);
5241
5242 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
5243 &base_vha->dpc_flags)) {
5244 if (ha->beacon_blink_led == 1)
5245 ha->isp_ops->beacon_blink(base_vha);
5246 }
5247
5248 if (!IS_QLAFX00(ha))
5249 qla2x00_do_dpc_all_vps(base_vha);
5250
5251 ha->dpc_active = 0;
5252 end_loop:
5253 set_current_state(TASK_INTERRUPTIBLE);
5254 } /* End of while(1) */
5255 __set_current_state(TASK_RUNNING);
5256
5257 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5258 "DPC handler exiting.\n");
5259
5260 /*
5261 * Make sure that nobody tries to wake us up again.
5262 */
5263 ha->dpc_active = 0;
5264
5265 /* Cleanup any residual CTX SRBs. */
5266 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5267
5268 return 0;
5269 }
5270
5271 void
5272 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
5273 {
5274 struct qla_hw_data *ha = vha->hw;
5275 struct task_struct *t = ha->dpc_thread;
5276
5277 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
5278 wake_up_process(t);
5279 }
5280
5281 /*
5282 * qla2x00_rst_aen
5283 * Processes asynchronous reset.
5284 *
5285 * Input:
5286 * ha = adapter block pointer.
5287 */
5288 static void
5289 qla2x00_rst_aen(scsi_qla_host_t *vha)
5290 {
5291 if (vha->flags.online && !vha->flags.reset_active &&
5292 !atomic_read(&vha->loop_down_timer) &&
5293 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
5294 do {
5295 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5296
5297 /*
5298 * Issue marker command only when we are going to start
5299 * the I/O.
5300 */
5301 vha->marker_needed = 1;
5302 } while (!atomic_read(&vha->loop_down_timer) &&
5303 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
5304 }
5305 }
5306
5307 /**************************************************************************
5308 * qla2x00_timer
5309 *
5310 * Description:
5311 * One second timer
5312 *
5313 * Context: Interrupt
5314 ***************************************************************************/
5315 void
5316 qla2x00_timer(scsi_qla_host_t *vha)
5317 {
5318 unsigned long cpu_flags = 0;
5319 int start_dpc = 0;
5320 int index;
5321 srb_t *sp;
5322 uint16_t w;
5323 struct qla_hw_data *ha = vha->hw;
5324 struct req_que *req;
5325
5326 if (ha->flags.eeh_busy) {
5327 ql_dbg(ql_dbg_timer, vha, 0x6000,
5328 "EEH = %d, restarting timer.\n",
5329 ha->flags.eeh_busy);
5330 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5331 return;
5332 }
5333
5334 /*
5335 * Hardware read to raise pending EEH errors during mailbox waits. If
5336 * the read returns -1 then disable the board.
5337 */
5338 if (!pci_channel_offline(ha->pdev)) {
5339 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
5340 qla2x00_check_reg16_for_disconnect(vha, w);
5341 }
5342
5343 /* Make sure qla82xx_watchdog is run only for physical port */
5344 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
5345 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5346 start_dpc++;
5347 if (IS_QLA82XX(ha))
5348 qla82xx_watchdog(vha);
5349 else if (IS_QLA8044(ha))
5350 qla8044_watchdog(vha);
5351 }
5352
5353 if (!vha->vp_idx && IS_QLAFX00(ha))
5354 qlafx00_timer_routine(vha);
5355
5356 /* Loop down handler. */
5357 if (atomic_read(&vha->loop_down_timer) > 0 &&
5358 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5359 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
5360 && vha->flags.online) {
5361
5362 if (atomic_read(&vha->loop_down_timer) ==
5363 vha->loop_down_abort_time) {
5364
5365 ql_log(ql_log_info, vha, 0x6008,
5366 "Loop down - aborting the queues before time expires.\n");
5367
5368 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5369 atomic_set(&vha->loop_state, LOOP_DEAD);
5370
5371 /*
5372 * Schedule an ISP abort to return any FCP2-device
5373 * commands.
5374 */
5375 /* NPIV - scan physical port only */
5376 if (!vha->vp_idx) {
5377 spin_lock_irqsave(&ha->hardware_lock,
5378 cpu_flags);
5379 req = ha->req_q_map[0];
5380 for (index = 1;
5381 index < req->num_outstanding_cmds;
5382 index++) {
5383 fc_port_t *sfcp;
5384
5385 sp = req->outstanding_cmds[index];
5386 if (!sp)
5387 continue;
5388 if (sp->type != SRB_SCSI_CMD)
5389 continue;
5390 sfcp = sp->fcport;
5391 if (!(sfcp->flags & FCF_FCP2_DEVICE))
5392 continue;
5393
5394 if (IS_QLA82XX(ha))
5395 set_bit(FCOE_CTX_RESET_NEEDED,
5396 &vha->dpc_flags);
5397 else
5398 set_bit(ISP_ABORT_NEEDED,
5399 &vha->dpc_flags);
5400 break;
5401 }
5402 spin_unlock_irqrestore(&ha->hardware_lock,
5403 cpu_flags);
5404 }
5405 start_dpc++;
5406 }
5407
5408 /* if the loop has been down for 4 minutes, reinit adapter */
5409 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
5410 if (!(vha->device_flags & DFLG_NO_CABLE)) {
5411 ql_log(ql_log_warn, vha, 0x6009,
5412 "Loop down - aborting ISP.\n");
5413
5414 if (IS_QLA82XX(ha))
5415 set_bit(FCOE_CTX_RESET_NEEDED,
5416 &vha->dpc_flags);
5417 else
5418 set_bit(ISP_ABORT_NEEDED,
5419 &vha->dpc_flags);
5420 }
5421 }
5422 ql_dbg(ql_dbg_timer, vha, 0x600a,
5423 "Loop down - seconds remaining %d.\n",
5424 atomic_read(&vha->loop_down_timer));
5425 }
5426 /* Check if beacon LED needs to be blinked for physical host only */
5427 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
5428 /* There is no beacon_blink function for ISP82xx */
5429 if (!IS_P3P_TYPE(ha)) {
5430 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5431 start_dpc++;
5432 }
5433 }
5434
5435 /* Process any deferred work. */
5436 if (!list_empty(&vha->work_list))
5437 start_dpc++;
5438
5439 /* Schedule the DPC routine if needed */
5440 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5441 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5442 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
5443 start_dpc ||
5444 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5445 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
5446 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5447 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
5448 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
5449 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
5450 ql_dbg(ql_dbg_timer, vha, 0x600b,
5451 "isp_abort_needed=%d loop_resync_needed=%d "
5452 "fcport_update_needed=%d start_dpc=%d "
5453 "reset_marker_needed=%d",
5454 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5455 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5456 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5457 start_dpc,
5458 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5459 ql_dbg(ql_dbg_timer, vha, 0x600c,
5460 "beacon_blink_needed=%d isp_unrecoverable=%d "
5461 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
5462 "relogin_needed=%d.\n",
5463 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5464 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5465 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5466 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
5467 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
5468 qla2xxx_wake_dpc(vha);
5469 }
5470
5471 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5472 }
5473
5474 /* Firmware interface routines. */
5475
5476 #define FW_BLOBS 11
5477 #define FW_ISP21XX 0
5478 #define FW_ISP22XX 1
5479 #define FW_ISP2300 2
5480 #define FW_ISP2322 3
5481 #define FW_ISP24XX 4
5482 #define FW_ISP25XX 5
5483 #define FW_ISP81XX 6
5484 #define FW_ISP82XX 7
5485 #define FW_ISP2031 8
5486 #define FW_ISP8031 9
5487 #define FW_ISP27XX 10
5488
5489 #define FW_FILE_ISP21XX "ql2100_fw.bin"
5490 #define FW_FILE_ISP22XX "ql2200_fw.bin"
5491 #define FW_FILE_ISP2300 "ql2300_fw.bin"
5492 #define FW_FILE_ISP2322 "ql2322_fw.bin"
5493 #define FW_FILE_ISP24XX "ql2400_fw.bin"
5494 #define FW_FILE_ISP25XX "ql2500_fw.bin"
5495 #define FW_FILE_ISP81XX "ql8100_fw.bin"
5496 #define FW_FILE_ISP82XX "ql8200_fw.bin"
5497 #define FW_FILE_ISP2031 "ql2600_fw.bin"
5498 #define FW_FILE_ISP8031 "ql8300_fw.bin"
5499 #define FW_FILE_ISP27XX "ql2700_fw.bin"
5500
5501
5502 static DEFINE_MUTEX(qla_fw_lock);
5503
5504 static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
5505 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5506 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5507 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5508 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5509 { .name = FW_FILE_ISP24XX, },
5510 { .name = FW_FILE_ISP25XX, },
5511 { .name = FW_FILE_ISP81XX, },
5512 { .name = FW_FILE_ISP82XX, },
5513 { .name = FW_FILE_ISP2031, },
5514 { .name = FW_FILE_ISP8031, },
5515 { .name = FW_FILE_ISP27XX, },
5516 };
5517
5518 struct fw_blob *
5519 qla2x00_request_firmware(scsi_qla_host_t *vha)
5520 {
5521 struct qla_hw_data *ha = vha->hw;
5522 struct fw_blob *blob;
5523
5524 if (IS_QLA2100(ha)) {
5525 blob = &qla_fw_blobs[FW_ISP21XX];
5526 } else if (IS_QLA2200(ha)) {
5527 blob = &qla_fw_blobs[FW_ISP22XX];
5528 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5529 blob = &qla_fw_blobs[FW_ISP2300];
5530 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5531 blob = &qla_fw_blobs[FW_ISP2322];
5532 } else if (IS_QLA24XX_TYPE(ha)) {
5533 blob = &qla_fw_blobs[FW_ISP24XX];
5534 } else if (IS_QLA25XX(ha)) {
5535 blob = &qla_fw_blobs[FW_ISP25XX];
5536 } else if (IS_QLA81XX(ha)) {
5537 blob = &qla_fw_blobs[FW_ISP81XX];
5538 } else if (IS_QLA82XX(ha)) {
5539 blob = &qla_fw_blobs[FW_ISP82XX];
5540 } else if (IS_QLA2031(ha)) {
5541 blob = &qla_fw_blobs[FW_ISP2031];
5542 } else if (IS_QLA8031(ha)) {
5543 blob = &qla_fw_blobs[FW_ISP8031];
5544 } else if (IS_QLA27XX(ha)) {
5545 blob = &qla_fw_blobs[FW_ISP27XX];
5546 } else {
5547 return NULL;
5548 }
5549
5550 mutex_lock(&qla_fw_lock);
5551 if (blob->fw)
5552 goto out;
5553
5554 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
5555 ql_log(ql_log_warn, vha, 0x0063,
5556 "Failed to load firmware image (%s).\n", blob->name);
5557 blob->fw = NULL;
5558 blob = NULL;
5559 goto out;
5560 }
5561
5562 out:
5563 mutex_unlock(&qla_fw_lock);
5564 return blob;
5565 }
5566
5567 static void
5568 qla2x00_release_firmware(void)
5569 {
5570 int idx;
5571
5572 mutex_lock(&qla_fw_lock);
5573 for (idx = 0; idx < FW_BLOBS; idx++)
5574 release_firmware(qla_fw_blobs[idx].fw);
5575 mutex_unlock(&qla_fw_lock);
5576 }
5577
5578 static pci_ers_result_t
5579 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5580 {
5581 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5582 struct qla_hw_data *ha = vha->hw;
5583
5584 ql_dbg(ql_dbg_aer, vha, 0x9000,
5585 "PCI error detected, state %x.\n", state);
5586
5587 switch (state) {
5588 case pci_channel_io_normal:
5589 ha->flags.eeh_busy = 0;
5590 return PCI_ERS_RESULT_CAN_RECOVER;
5591 case pci_channel_io_frozen:
5592 ha->flags.eeh_busy = 1;
5593 /* For ISP82XX complete any pending mailbox cmd */
5594 if (IS_QLA82XX(ha)) {
5595 ha->flags.isp82xx_fw_hung = 1;
5596 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5597 qla82xx_clear_pending_mbx(vha);
5598 }
5599 qla2x00_free_irqs(vha);
5600 pci_disable_device(pdev);
5601 /* Return back all IOs */
5602 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
5603 return PCI_ERS_RESULT_NEED_RESET;
5604 case pci_channel_io_perm_failure:
5605 ha->flags.pci_channel_io_perm_failure = 1;
5606 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
5607 return PCI_ERS_RESULT_DISCONNECT;
5608 }
5609 return PCI_ERS_RESULT_NEED_RESET;
5610 }
5611
5612 static pci_ers_result_t
5613 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5614 {
5615 int risc_paused = 0;
5616 uint32_t stat;
5617 unsigned long flags;
5618 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5619 struct qla_hw_data *ha = base_vha->hw;
5620 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5621 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5622
5623 if (IS_QLA82XX(ha))
5624 return PCI_ERS_RESULT_RECOVERED;
5625
5626 spin_lock_irqsave(&ha->hardware_lock, flags);
5627 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5628 stat = RD_REG_DWORD(&reg->hccr);
5629 if (stat & HCCR_RISC_PAUSE)
5630 risc_paused = 1;
5631 } else if (IS_QLA23XX(ha)) {
5632 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5633 if (stat & HSR_RISC_PAUSED)
5634 risc_paused = 1;
5635 } else if (IS_FWI2_CAPABLE(ha)) {
5636 stat = RD_REG_DWORD(&reg24->host_status);
5637 if (stat & HSRX_RISC_PAUSED)
5638 risc_paused = 1;
5639 }
5640 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5641
5642 if (risc_paused) {
5643 ql_log(ql_log_info, base_vha, 0x9003,
5644 "RISC paused -- mmio_enabled, Dumping firmware.\n");
5645 ha->isp_ops->fw_dump(base_vha, 0);
5646
5647 return PCI_ERS_RESULT_NEED_RESET;
5648 } else
5649 return PCI_ERS_RESULT_RECOVERED;
5650 }
5651
5652 static uint32_t
5653 qla82xx_error_recovery(scsi_qla_host_t *base_vha)
5654 {
5655 uint32_t rval = QLA_FUNCTION_FAILED;
5656 uint32_t drv_active = 0;
5657 struct qla_hw_data *ha = base_vha->hw;
5658 int fn;
5659 struct pci_dev *other_pdev = NULL;
5660
5661 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5662 "Entered %s.\n", __func__);
5663
5664 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5665
5666 if (base_vha->flags.online) {
5667 /* Abort all outstanding commands,
5668 * so as to be requeued later */
5669 qla2x00_abort_isp_cleanup(base_vha);
5670 }
5671
5672
5673 fn = PCI_FUNC(ha->pdev->devfn);
5674 while (fn > 0) {
5675 fn--;
5676 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5677 "Finding pci device at function = 0x%x.\n", fn);
5678 other_pdev =
5679 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5680 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5681 fn));
5682
5683 if (!other_pdev)
5684 continue;
5685 if (atomic_read(&other_pdev->enable_cnt)) {
5686 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5687 "Found PCI func available and enable at 0x%x.\n",
5688 fn);
5689 pci_dev_put(other_pdev);
5690 break;
5691 }
5692 pci_dev_put(other_pdev);
5693 }
5694
5695 if (!fn) {
5696 /* Reset owner */
5697 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5698 "This devfn is reset owner = 0x%x.\n",
5699 ha->pdev->devfn);
5700 qla82xx_idc_lock(ha);
5701
5702 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5703 QLA8XXX_DEV_INITIALIZING);
5704
5705 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5706 QLA82XX_IDC_VERSION);
5707
5708 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
5709 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5710 "drv_active = 0x%x.\n", drv_active);
5711
5712 qla82xx_idc_unlock(ha);
5713 /* Reset if device is not already reset
5714 * drv_active would be 0 if a reset has already been done
5715 */
5716 if (drv_active)
5717 rval = qla82xx_start_firmware(base_vha);
5718 else
5719 rval = QLA_SUCCESS;
5720 qla82xx_idc_lock(ha);
5721
5722 if (rval != QLA_SUCCESS) {
5723 ql_log(ql_log_info, base_vha, 0x900b,
5724 "HW State: FAILED.\n");
5725 qla82xx_clear_drv_active(ha);
5726 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5727 QLA8XXX_DEV_FAILED);
5728 } else {
5729 ql_log(ql_log_info, base_vha, 0x900c,
5730 "HW State: READY.\n");
5731 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5732 QLA8XXX_DEV_READY);
5733 qla82xx_idc_unlock(ha);
5734 ha->flags.isp82xx_fw_hung = 0;
5735 rval = qla82xx_restart_isp(base_vha);
5736 qla82xx_idc_lock(ha);
5737 /* Clear driver state register */
5738 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5739 qla82xx_set_drv_active(base_vha);
5740 }
5741 qla82xx_idc_unlock(ha);
5742 } else {
5743 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5744 "This devfn is not reset owner = 0x%x.\n",
5745 ha->pdev->devfn);
5746 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
5747 QLA8XXX_DEV_READY)) {
5748 ha->flags.isp82xx_fw_hung = 0;
5749 rval = qla82xx_restart_isp(base_vha);
5750 qla82xx_idc_lock(ha);
5751 qla82xx_set_drv_active(base_vha);
5752 qla82xx_idc_unlock(ha);
5753 }
5754 }
5755 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5756
5757 return rval;
5758 }
5759
5760 static pci_ers_result_t
5761 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5762 {
5763 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
5764 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5765 struct qla_hw_data *ha = base_vha->hw;
5766 struct rsp_que *rsp;
5767 int rc, retries = 10;
5768
5769 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5770 "Slot Reset.\n");
5771
5772 /* Workaround: qla2xxx driver which access hardware earlier
5773 * needs error state to be pci_channel_io_online.
5774 * Otherwise mailbox command timesout.
5775 */
5776 pdev->error_state = pci_channel_io_normal;
5777
5778 pci_restore_state(pdev);
5779
5780 /* pci_restore_state() clears the saved_state flag of the device
5781 * save restored state which resets saved_state flag
5782 */
5783 pci_save_state(pdev);
5784
5785 if (ha->mem_only)
5786 rc = pci_enable_device_mem(pdev);
5787 else
5788 rc = pci_enable_device(pdev);
5789
5790 if (rc) {
5791 ql_log(ql_log_warn, base_vha, 0x9005,
5792 "Can't re-enable PCI device after reset.\n");
5793 goto exit_slot_reset;
5794 }
5795
5796 rsp = ha->rsp_q_map[0];
5797 if (qla2x00_request_irqs(ha, rsp))
5798 goto exit_slot_reset;
5799
5800 if (ha->isp_ops->pci_config(base_vha))
5801 goto exit_slot_reset;
5802
5803 if (IS_QLA82XX(ha)) {
5804 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5805 ret = PCI_ERS_RESULT_RECOVERED;
5806 goto exit_slot_reset;
5807 } else
5808 goto exit_slot_reset;
5809 }
5810
5811 while (ha->flags.mbox_busy && retries--)
5812 msleep(1000);
5813
5814 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5815 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
5816 ret = PCI_ERS_RESULT_RECOVERED;
5817 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5818
5819
5820 exit_slot_reset:
5821 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5822 "slot_reset return %x.\n", ret);
5823
5824 return ret;
5825 }
5826
5827 static void
5828 qla2xxx_pci_resume(struct pci_dev *pdev)
5829 {
5830 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5831 struct qla_hw_data *ha = base_vha->hw;
5832 int ret;
5833
5834 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5835 "pci_resume.\n");
5836
5837 ret = qla2x00_wait_for_hba_online(base_vha);
5838 if (ret != QLA_SUCCESS) {
5839 ql_log(ql_log_fatal, base_vha, 0x9002,
5840 "The device failed to resume I/O from slot/link_reset.\n");
5841 }
5842
5843 pci_cleanup_aer_uncorrect_error_status(pdev);
5844
5845 ha->flags.eeh_busy = 0;
5846 }
5847
5848 static void
5849 qla83xx_disable_laser(scsi_qla_host_t *vha)
5850 {
5851 uint32_t reg, data, fn;
5852 struct qla_hw_data *ha = vha->hw;
5853 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
5854
5855 /* pci func #/port # */
5856 ql_dbg(ql_dbg_init, vha, 0x004b,
5857 "Disabling Laser for hba: %p\n", vha);
5858
5859 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
5860 (BIT_15|BIT_14|BIT_13|BIT_12));
5861
5862 fn = (fn >> 12);
5863
5864 if (fn & 1)
5865 reg = PORT_1_2031;
5866 else
5867 reg = PORT_0_2031;
5868
5869 data = LASER_OFF_2031;
5870
5871 qla83xx_wr_reg(vha, reg, data);
5872 }
5873
5874 static const struct pci_error_handlers qla2xxx_err_handler = {
5875 .error_detected = qla2xxx_pci_error_detected,
5876 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5877 .slot_reset = qla2xxx_pci_slot_reset,
5878 .resume = qla2xxx_pci_resume,
5879 };
5880
5881 static struct pci_device_id qla2xxx_pci_tbl[] = {
5882 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5883 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5884 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5885 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5886 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5887 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5888 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5889 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5890 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
5891 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
5892 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5893 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
5894 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
5895 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
5896 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
5897 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5898 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
5899 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
5900 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
5901 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
5902 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
5903 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5904 { 0 },
5905 };
5906 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5907
5908 static struct pci_driver qla2xxx_pci_driver = {
5909 .name = QLA2XXX_DRIVER_NAME,
5910 .driver = {
5911 .owner = THIS_MODULE,
5912 },
5913 .id_table = qla2xxx_pci_tbl,
5914 .probe = qla2x00_probe_one,
5915 .remove = qla2x00_remove_one,
5916 .shutdown = qla2x00_shutdown,
5917 .err_handler = &qla2xxx_err_handler,
5918 };
5919
5920 static const struct file_operations apidev_fops = {
5921 .owner = THIS_MODULE,
5922 .llseek = noop_llseek,
5923 };
5924
5925 /**
5926 * qla2x00_module_init - Module initialization.
5927 **/
5928 static int __init
5929 qla2x00_module_init(void)
5930 {
5931 int ret = 0;
5932
5933 /* Allocate cache for SRBs. */
5934 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
5935 SLAB_HWCACHE_ALIGN, NULL);
5936 if (srb_cachep == NULL) {
5937 ql_log(ql_log_fatal, NULL, 0x0001,
5938 "Unable to allocate SRB cache...Failing load!.\n");
5939 return -ENOMEM;
5940 }
5941
5942 /* Initialize target kmem_cache and mem_pools */
5943 ret = qlt_init();
5944 if (ret < 0) {
5945 kmem_cache_destroy(srb_cachep);
5946 return ret;
5947 } else if (ret > 0) {
5948 /*
5949 * If initiator mode is explictly disabled by qlt_init(),
5950 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5951 * performing scsi_scan_target() during LOOP UP event.
5952 */
5953 qla2xxx_transport_functions.disable_target_scan = 1;
5954 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5955 }
5956
5957 /* Derive version string. */
5958 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
5959 if (ql2xextended_error_logging)
5960 strcat(qla2x00_version_str, "-debug");
5961
5962 qla2xxx_transport_template =
5963 fc_attach_transport(&qla2xxx_transport_functions);
5964 if (!qla2xxx_transport_template) {
5965 kmem_cache_destroy(srb_cachep);
5966 ql_log(ql_log_fatal, NULL, 0x0002,
5967 "fc_attach_transport failed...Failing load!.\n");
5968 qlt_exit();
5969 return -ENODEV;
5970 }
5971
5972 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5973 if (apidev_major < 0) {
5974 ql_log(ql_log_fatal, NULL, 0x0003,
5975 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
5976 }
5977
5978 qla2xxx_transport_vport_template =
5979 fc_attach_transport(&qla2xxx_transport_vport_functions);
5980 if (!qla2xxx_transport_vport_template) {
5981 kmem_cache_destroy(srb_cachep);
5982 qlt_exit();
5983 fc_release_transport(qla2xxx_transport_template);
5984 ql_log(ql_log_fatal, NULL, 0x0004,
5985 "fc_attach_transport vport failed...Failing load!.\n");
5986 return -ENODEV;
5987 }
5988 ql_log(ql_log_info, NULL, 0x0005,
5989 "QLogic Fibre Channel HBA Driver: %s.\n",
5990 qla2x00_version_str);
5991 ret = pci_register_driver(&qla2xxx_pci_driver);
5992 if (ret) {
5993 kmem_cache_destroy(srb_cachep);
5994 qlt_exit();
5995 fc_release_transport(qla2xxx_transport_template);
5996 fc_release_transport(qla2xxx_transport_vport_template);
5997 ql_log(ql_log_fatal, NULL, 0x0006,
5998 "pci_register_driver failed...ret=%d Failing load!.\n",
5999 ret);
6000 }
6001 return ret;
6002 }
6003
6004 /**
6005 * qla2x00_module_exit - Module cleanup.
6006 **/
6007 static void __exit
6008 qla2x00_module_exit(void)
6009 {
6010 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
6011 pci_unregister_driver(&qla2xxx_pci_driver);
6012 qla2x00_release_firmware();
6013 kmem_cache_destroy(srb_cachep);
6014 qlt_exit();
6015 if (ctx_cachep)
6016 kmem_cache_destroy(ctx_cachep);
6017 fc_release_transport(qla2xxx_transport_template);
6018 fc_release_transport(qla2xxx_transport_vport_template);
6019 }
6020
6021 module_init(qla2x00_module_init);
6022 module_exit(qla2x00_module_exit);
6023
6024 MODULE_AUTHOR("QLogic Corporation");
6025 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6026 MODULE_LICENSE("GPL");
6027 MODULE_VERSION(QLA2XXX_VERSION);
6028 MODULE_FIRMWARE(FW_FILE_ISP21XX);
6029 MODULE_FIRMWARE(FW_FILE_ISP22XX);
6030 MODULE_FIRMWARE(FW_FILE_ISP2300);
6031 MODULE_FIRMWARE(FW_FILE_ISP2322);
6032 MODULE_FIRMWARE(FW_FILE_ISP24XX);
6033 MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux kernel - Deliverables
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