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qla2xxx: Restrict max_lun to 16-bit for older HBAs
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_os.c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <scsi/scsi_tcq.h>
17 #include <scsi/scsicam.h>
18 #include <scsi/scsi_transport.h>
19 #include <scsi/scsi_transport_fc.h>
20
21 #include "qla_target.h"
22
23 /*
24 * Driver version
25 */
26 char qla2x00_version_str[40];
27
28 static int apidev_major;
29
30 /*
31 * SRB allocation cache
32 */
33 static struct kmem_cache *srb_cachep;
34
35 /*
36 * CT6 CTX allocation cache
37 */
38 static struct kmem_cache *ctx_cachep;
39 /*
40 * error level for logging
41 */
42 int ql_errlev = ql_log_all;
43
44 static int ql2xenableclass2;
45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46 MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
50
51 int ql2xlogintimeout = 20;
52 module_param(ql2xlogintimeout, int, S_IRUGO);
53 MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
56 int qlport_down_retry;
57 module_param(qlport_down_retry, int, S_IRUGO);
58 MODULE_PARM_DESC(qlport_down_retry,
59 "Maximum number of command retries to a port that returns "
60 "a PORT-DOWN status.");
61
62 int ql2xplogiabsentdevice;
63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64 MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
66 "a Fabric scan. This is needed for several broken switches. "
67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
69 int ql2xloginretrycount = 0;
70 module_param(ql2xloginretrycount, int, S_IRUGO);
71 MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
74 int ql2xallocfwdump = 1;
75 module_param(ql2xallocfwdump, int, S_IRUGO);
76 MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
81 int ql2xextended_error_logging;
82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
83 MODULE_PARM_DESC(ql2xextended_error_logging,
84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
99 "\t\tDo LOGICAL OR of the value to enable more than one level");
100
101 int ql2xshiftctondsd = 6;
102 module_param(ql2xshiftctondsd, int, S_IRUGO);
103 MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
107 int ql2xfdmienable=1;
108 module_param(ql2xfdmienable, int, S_IRUGO);
109 MODULE_PARM_DESC(ql2xfdmienable,
110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
112
113 #define MAX_Q_DEPTH 32
114 static int ql2xmaxqdepth = MAX_Q_DEPTH;
115 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116 MODULE_PARM_DESC(ql2xmaxqdepth,
117 "Maximum queue depth to set for each LUN. "
118 "Default is 32.");
119
120 int ql2xenabledif = 2;
121 module_param(ql2xenabledif, int, S_IRUGO);
122 MODULE_PARM_DESC(ql2xenabledif,
123 " Enable T10-CRC-DIF:\n"
124 " Default is 2.\n"
125 " 0 -- No DIF Support\n"
126 " 1 -- Enable DIF for all types\n"
127 " 2 -- Enable DIF for all types, except Type 0.\n");
128
129 int ql2xenablehba_err_chk = 2;
130 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
131 MODULE_PARM_DESC(ql2xenablehba_err_chk,
132 " Enable T10-CRC-DIF Error isolation by HBA:\n"
133 " Default is 2.\n"
134 " 0 -- Error isolation disabled\n"
135 " 1 -- Error isolation enabled only for DIX Type 0\n"
136 " 2 -- Error isolation enabled for all Types\n");
137
138 int ql2xiidmaenable=1;
139 module_param(ql2xiidmaenable, int, S_IRUGO);
140 MODULE_PARM_DESC(ql2xiidmaenable,
141 "Enables iIDMA settings "
142 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
143
144 int ql2xmaxqueues = 1;
145 module_param(ql2xmaxqueues, int, S_IRUGO);
146 MODULE_PARM_DESC(ql2xmaxqueues,
147 "Enables MQ settings "
148 "Default is 1 for single queue. Set it to number "
149 "of queues in MQ mode.");
150
151 int ql2xmultique_tag;
152 module_param(ql2xmultique_tag, int, S_IRUGO);
153 MODULE_PARM_DESC(ql2xmultique_tag,
154 "Enables CPU affinity settings for the driver "
155 "Default is 0 for no affinity of request and response IO. "
156 "Set it to 1 to turn on the cpu affinity.");
157
158 int ql2xfwloadbin;
159 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
160 MODULE_PARM_DESC(ql2xfwloadbin,
161 "Option to specify location from which to load ISP firmware:.\n"
162 " 2 -- load firmware via the request_firmware() (hotplug).\n"
163 " interface.\n"
164 " 1 -- load firmware from flash.\n"
165 " 0 -- use default semantics.\n");
166
167 int ql2xetsenable;
168 module_param(ql2xetsenable, int, S_IRUGO);
169 MODULE_PARM_DESC(ql2xetsenable,
170 "Enables firmware ETS burst."
171 "Default is 0 - skip ETS enablement.");
172
173 int ql2xdbwr = 1;
174 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
175 MODULE_PARM_DESC(ql2xdbwr,
176 "Option to specify scheme for request queue posting.\n"
177 " 0 -- Regular doorbell.\n"
178 " 1 -- CAMRAM doorbell (faster).\n");
179
180 int ql2xtargetreset = 1;
181 module_param(ql2xtargetreset, int, S_IRUGO);
182 MODULE_PARM_DESC(ql2xtargetreset,
183 "Enable target reset."
184 "Default is 1 - use hw defaults.");
185
186 int ql2xgffidenable;
187 module_param(ql2xgffidenable, int, S_IRUGO);
188 MODULE_PARM_DESC(ql2xgffidenable,
189 "Enables GFF_ID checks of port type. "
190 "Default is 0 - Do not use GFF_ID information.");
191
192 int ql2xasynctmfenable;
193 module_param(ql2xasynctmfenable, int, S_IRUGO);
194 MODULE_PARM_DESC(ql2xasynctmfenable,
195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
196 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
197
198 int ql2xdontresethba;
199 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
200 MODULE_PARM_DESC(ql2xdontresethba,
201 "Option to specify reset behaviour.\n"
202 " 0 (Default) -- Reset on failure.\n"
203 " 1 -- Do not reset on failure.\n");
204
205 uint ql2xmaxlun = MAX_LUNS;
206 module_param(ql2xmaxlun, uint, S_IRUGO);
207 MODULE_PARM_DESC(ql2xmaxlun,
208 "Defines the maximum LU number to register with the SCSI "
209 "midlayer. Default is 65535.");
210
211 int ql2xmdcapmask = 0x1F;
212 module_param(ql2xmdcapmask, int, S_IRUGO);
213 MODULE_PARM_DESC(ql2xmdcapmask,
214 "Set the Minidump driver capture mask level. "
215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
216
217 int ql2xmdenable = 1;
218 module_param(ql2xmdenable, int, S_IRUGO);
219 MODULE_PARM_DESC(ql2xmdenable,
220 "Enable/disable MiniDump. "
221 "0 - MiniDump disabled. "
222 "1 (Default) - MiniDump enabled.");
223
224 /*
225 * SCSI host template entry points
226 */
227 static int qla2xxx_slave_configure(struct scsi_device * device);
228 static int qla2xxx_slave_alloc(struct scsi_device *);
229 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
230 static void qla2xxx_scan_start(struct Scsi_Host *);
231 static void qla2xxx_slave_destroy(struct scsi_device *);
232 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
233 static int qla2xxx_eh_abort(struct scsi_cmnd *);
234 static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
235 static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
236 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
237 static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
238
239 static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
240 static int qla2x00_change_queue_type(struct scsi_device *, int);
241 static void qla2x00_free_device(scsi_qla_host_t *);
242
243 struct scsi_host_template qla2xxx_driver_template = {
244 .module = THIS_MODULE,
245 .name = QLA2XXX_DRIVER_NAME,
246 .queuecommand = qla2xxx_queuecommand,
247
248 .eh_abort_handler = qla2xxx_eh_abort,
249 .eh_device_reset_handler = qla2xxx_eh_device_reset,
250 .eh_target_reset_handler = qla2xxx_eh_target_reset,
251 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
252 .eh_host_reset_handler = qla2xxx_eh_host_reset,
253
254 .slave_configure = qla2xxx_slave_configure,
255
256 .slave_alloc = qla2xxx_slave_alloc,
257 .slave_destroy = qla2xxx_slave_destroy,
258 .scan_finished = qla2xxx_scan_finished,
259 .scan_start = qla2xxx_scan_start,
260 .change_queue_depth = qla2x00_change_queue_depth,
261 .change_queue_type = qla2x00_change_queue_type,
262 .this_id = -1,
263 .cmd_per_lun = 3,
264 .use_clustering = ENABLE_CLUSTERING,
265 .sg_tablesize = SG_ALL,
266
267 .max_sectors = 0xFFFF,
268 .shost_attrs = qla2x00_host_attrs,
269
270 .supported_mode = MODE_INITIATOR,
271 };
272
273 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
274 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
275
276 /* TODO Convert to inlines
277 *
278 * Timer routines
279 */
280
281 __inline__ void
282 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
283 {
284 init_timer(&vha->timer);
285 vha->timer.expires = jiffies + interval * HZ;
286 vha->timer.data = (unsigned long)vha;
287 vha->timer.function = (void (*)(unsigned long))func;
288 add_timer(&vha->timer);
289 vha->timer_active = 1;
290 }
291
292 static inline void
293 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
294 {
295 /* Currently used for 82XX only. */
296 if (vha->device_flags & DFLG_DEV_FAILED) {
297 ql_dbg(ql_dbg_timer, vha, 0x600d,
298 "Device in a failed state, returning.\n");
299 return;
300 }
301
302 mod_timer(&vha->timer, jiffies + interval * HZ);
303 }
304
305 static __inline__ void
306 qla2x00_stop_timer(scsi_qla_host_t *vha)
307 {
308 del_timer_sync(&vha->timer);
309 vha->timer_active = 0;
310 }
311
312 static int qla2x00_do_dpc(void *data);
313
314 static void qla2x00_rst_aen(scsi_qla_host_t *);
315
316 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
317 struct req_que **, struct rsp_que **);
318 static void qla2x00_free_fw_dump(struct qla_hw_data *);
319 static void qla2x00_mem_free(struct qla_hw_data *);
320
321 /* -------------------------------------------------------------------------- */
322 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
323 struct rsp_que *rsp)
324 {
325 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
326 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
327 GFP_KERNEL);
328 if (!ha->req_q_map) {
329 ql_log(ql_log_fatal, vha, 0x003b,
330 "Unable to allocate memory for request queue ptrs.\n");
331 goto fail_req_map;
332 }
333
334 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
335 GFP_KERNEL);
336 if (!ha->rsp_q_map) {
337 ql_log(ql_log_fatal, vha, 0x003c,
338 "Unable to allocate memory for response queue ptrs.\n");
339 goto fail_rsp_map;
340 }
341 /*
342 * Make sure we record at least the request and response queue zero in
343 * case we need to free them if part of the probe fails.
344 */
345 ha->rsp_q_map[0] = rsp;
346 ha->req_q_map[0] = req;
347 set_bit(0, ha->rsp_qid_map);
348 set_bit(0, ha->req_qid_map);
349 return 1;
350
351 fail_rsp_map:
352 kfree(ha->req_q_map);
353 ha->req_q_map = NULL;
354 fail_req_map:
355 return -ENOMEM;
356 }
357
358 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
359 {
360 if (IS_QLAFX00(ha)) {
361 if (req && req->ring_fx00)
362 dma_free_coherent(&ha->pdev->dev,
363 (req->length_fx00 + 1) * sizeof(request_t),
364 req->ring_fx00, req->dma_fx00);
365 } else if (req && req->ring)
366 dma_free_coherent(&ha->pdev->dev,
367 (req->length + 1) * sizeof(request_t),
368 req->ring, req->dma);
369
370 if (req)
371 kfree(req->outstanding_cmds);
372
373 kfree(req);
374 req = NULL;
375 }
376
377 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
378 {
379 if (IS_QLAFX00(ha)) {
380 if (rsp && rsp->ring)
381 dma_free_coherent(&ha->pdev->dev,
382 (rsp->length_fx00 + 1) * sizeof(request_t),
383 rsp->ring_fx00, rsp->dma_fx00);
384 } else if (rsp && rsp->ring) {
385 dma_free_coherent(&ha->pdev->dev,
386 (rsp->length + 1) * sizeof(response_t),
387 rsp->ring, rsp->dma);
388 }
389 kfree(rsp);
390 rsp = NULL;
391 }
392
393 static void qla2x00_free_queues(struct qla_hw_data *ha)
394 {
395 struct req_que *req;
396 struct rsp_que *rsp;
397 int cnt;
398
399 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
400 req = ha->req_q_map[cnt];
401 qla2x00_free_req_que(ha, req);
402 }
403 kfree(ha->req_q_map);
404 ha->req_q_map = NULL;
405
406 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
407 rsp = ha->rsp_q_map[cnt];
408 qla2x00_free_rsp_que(ha, rsp);
409 }
410 kfree(ha->rsp_q_map);
411 ha->rsp_q_map = NULL;
412 }
413
414 static int qla25xx_setup_mode(struct scsi_qla_host *vha)
415 {
416 uint16_t options = 0;
417 int ques, req, ret;
418 struct qla_hw_data *ha = vha->hw;
419
420 if (!(ha->fw_attributes & BIT_6)) {
421 ql_log(ql_log_warn, vha, 0x00d8,
422 "Firmware is not multi-queue capable.\n");
423 goto fail;
424 }
425 if (ql2xmultique_tag) {
426 /* create a request queue for IO */
427 options |= BIT_7;
428 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
429 QLA_DEFAULT_QUE_QOS);
430 if (!req) {
431 ql_log(ql_log_warn, vha, 0x00e0,
432 "Failed to create request queue.\n");
433 goto fail;
434 }
435 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
436 vha->req = ha->req_q_map[req];
437 options |= BIT_1;
438 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
439 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
440 if (!ret) {
441 ql_log(ql_log_warn, vha, 0x00e8,
442 "Failed to create response queue.\n");
443 goto fail2;
444 }
445 }
446 ha->flags.cpu_affinity_enabled = 1;
447 ql_dbg(ql_dbg_multiq, vha, 0xc007,
448 "CPU affinity mode enalbed, "
449 "no. of response queues:%d no. of request queues:%d.\n",
450 ha->max_rsp_queues, ha->max_req_queues);
451 ql_dbg(ql_dbg_init, vha, 0x00e9,
452 "CPU affinity mode enalbed, "
453 "no. of response queues:%d no. of request queues:%d.\n",
454 ha->max_rsp_queues, ha->max_req_queues);
455 }
456 return 0;
457 fail2:
458 qla25xx_delete_queues(vha);
459 destroy_workqueue(ha->wq);
460 ha->wq = NULL;
461 vha->req = ha->req_q_map[0];
462 fail:
463 ha->mqenable = 0;
464 kfree(ha->req_q_map);
465 kfree(ha->rsp_q_map);
466 ha->max_req_queues = ha->max_rsp_queues = 1;
467 return 1;
468 }
469
470 static char *
471 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
472 {
473 struct qla_hw_data *ha = vha->hw;
474 static char *pci_bus_modes[] = {
475 "33", "66", "100", "133",
476 };
477 uint16_t pci_bus;
478
479 strcpy(str, "PCI");
480 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
481 if (pci_bus) {
482 strcat(str, "-X (");
483 strcat(str, pci_bus_modes[pci_bus]);
484 } else {
485 pci_bus = (ha->pci_attr & BIT_8) >> 8;
486 strcat(str, " (");
487 strcat(str, pci_bus_modes[pci_bus]);
488 }
489 strcat(str, " MHz)");
490
491 return (str);
492 }
493
494 static char *
495 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
496 {
497 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
498 struct qla_hw_data *ha = vha->hw;
499 uint32_t pci_bus;
500
501 if (pci_is_pcie(ha->pdev)) {
502 char lwstr[6];
503 uint32_t lstat, lspeed, lwidth;
504
505 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
506 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
507 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
508
509 strcpy(str, "PCIe (");
510 switch (lspeed) {
511 case 1:
512 strcat(str, "2.5GT/s ");
513 break;
514 case 2:
515 strcat(str, "5.0GT/s ");
516 break;
517 case 3:
518 strcat(str, "8.0GT/s ");
519 break;
520 default:
521 strcat(str, "<unknown> ");
522 break;
523 }
524 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
525 strcat(str, lwstr);
526
527 return str;
528 }
529
530 strcpy(str, "PCI");
531 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
532 if (pci_bus == 0 || pci_bus == 8) {
533 strcat(str, " (");
534 strcat(str, pci_bus_modes[pci_bus >> 3]);
535 } else {
536 strcat(str, "-X ");
537 if (pci_bus & BIT_2)
538 strcat(str, "Mode 2");
539 else
540 strcat(str, "Mode 1");
541 strcat(str, " (");
542 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
543 }
544 strcat(str, " MHz)");
545
546 return str;
547 }
548
549 static char *
550 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
551 {
552 char un_str[10];
553 struct qla_hw_data *ha = vha->hw;
554
555 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
556 ha->fw_minor_version,
557 ha->fw_subminor_version);
558
559 if (ha->fw_attributes & BIT_9) {
560 strcat(str, "FLX");
561 return (str);
562 }
563
564 switch (ha->fw_attributes & 0xFF) {
565 case 0x7:
566 strcat(str, "EF");
567 break;
568 case 0x17:
569 strcat(str, "TP");
570 break;
571 case 0x37:
572 strcat(str, "IP");
573 break;
574 case 0x77:
575 strcat(str, "VI");
576 break;
577 default:
578 sprintf(un_str, "(%x)", ha->fw_attributes);
579 strcat(str, un_str);
580 break;
581 }
582 if (ha->fw_attributes & 0x100)
583 strcat(str, "X");
584
585 return (str);
586 }
587
588 static char *
589 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
590 {
591 struct qla_hw_data *ha = vha->hw;
592
593 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
594 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
595 return str;
596 }
597
598 void
599 qla2x00_sp_free_dma(void *vha, void *ptr)
600 {
601 srb_t *sp = (srb_t *)ptr;
602 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
603 struct qla_hw_data *ha = sp->fcport->vha->hw;
604 void *ctx = GET_CMD_CTX_SP(sp);
605
606 if (sp->flags & SRB_DMA_VALID) {
607 scsi_dma_unmap(cmd);
608 sp->flags &= ~SRB_DMA_VALID;
609 }
610
611 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
612 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
613 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
614 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
615 }
616
617 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
618 /* List assured to be having elements */
619 qla2x00_clean_dsd_pool(ha, sp, NULL);
620 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
621 }
622
623 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
624 dma_pool_free(ha->dl_dma_pool, ctx,
625 ((struct crc_context *)ctx)->crc_ctx_dma);
626 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
627 }
628
629 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
630 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
631
632 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
633 ctx1->fcp_cmnd_dma);
634 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
635 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
636 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
637 mempool_free(ctx1, ha->ctx_mempool);
638 ctx1 = NULL;
639 }
640
641 CMD_SP(cmd) = NULL;
642 qla2x00_rel_sp(sp->fcport->vha, sp);
643 }
644
645 static void
646 qla2x00_sp_compl(void *data, void *ptr, int res)
647 {
648 struct qla_hw_data *ha = (struct qla_hw_data *)data;
649 srb_t *sp = (srb_t *)ptr;
650 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
651
652 cmd->result = res;
653
654 if (atomic_read(&sp->ref_count) == 0) {
655 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
656 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
657 sp, GET_CMD_SP(sp));
658 if (ql2xextended_error_logging & ql_dbg_io)
659 BUG();
660 return;
661 }
662 if (!atomic_dec_and_test(&sp->ref_count))
663 return;
664
665 qla2x00_sp_free_dma(ha, sp);
666 cmd->scsi_done(cmd);
667 }
668
669 /* If we are SP1 here, we need to still take and release the host_lock as SP1
670 * does not have the changes necessary to avoid taking host->host_lock.
671 */
672 static int
673 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
674 {
675 scsi_qla_host_t *vha = shost_priv(host);
676 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
677 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
678 struct qla_hw_data *ha = vha->hw;
679 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
680 srb_t *sp;
681 int rval;
682
683 if (ha->flags.eeh_busy) {
684 if (ha->flags.pci_channel_io_perm_failure) {
685 ql_dbg(ql_dbg_aer, vha, 0x9010,
686 "PCI Channel IO permanent failure, exiting "
687 "cmd=%p.\n", cmd);
688 cmd->result = DID_NO_CONNECT << 16;
689 } else {
690 ql_dbg(ql_dbg_aer, vha, 0x9011,
691 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
692 cmd->result = DID_REQUEUE << 16;
693 }
694 goto qc24_fail_command;
695 }
696
697 rval = fc_remote_port_chkready(rport);
698 if (rval) {
699 cmd->result = rval;
700 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
701 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
702 cmd, rval);
703 goto qc24_fail_command;
704 }
705
706 if (!vha->flags.difdix_supported &&
707 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
708 ql_dbg(ql_dbg_io, vha, 0x3004,
709 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
710 cmd);
711 cmd->result = DID_NO_CONNECT << 16;
712 goto qc24_fail_command;
713 }
714
715 if (!fcport) {
716 cmd->result = DID_NO_CONNECT << 16;
717 goto qc24_fail_command;
718 }
719
720 if (atomic_read(&fcport->state) != FCS_ONLINE) {
721 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
722 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
723 ql_dbg(ql_dbg_io, vha, 0x3005,
724 "Returning DNC, fcport_state=%d loop_state=%d.\n",
725 atomic_read(&fcport->state),
726 atomic_read(&base_vha->loop_state));
727 cmd->result = DID_NO_CONNECT << 16;
728 goto qc24_fail_command;
729 }
730 goto qc24_target_busy;
731 }
732
733 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
734 if (!sp)
735 goto qc24_host_busy;
736
737 sp->u.scmd.cmd = cmd;
738 sp->type = SRB_SCSI_CMD;
739 atomic_set(&sp->ref_count, 1);
740 CMD_SP(cmd) = (void *)sp;
741 sp->free = qla2x00_sp_free_dma;
742 sp->done = qla2x00_sp_compl;
743
744 rval = ha->isp_ops->start_scsi(sp);
745 if (rval != QLA_SUCCESS) {
746 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
747 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
748 goto qc24_host_busy_free_sp;
749 }
750
751 return 0;
752
753 qc24_host_busy_free_sp:
754 qla2x00_sp_free_dma(ha, sp);
755
756 qc24_host_busy:
757 return SCSI_MLQUEUE_HOST_BUSY;
758
759 qc24_target_busy:
760 return SCSI_MLQUEUE_TARGET_BUSY;
761
762 qc24_fail_command:
763 cmd->scsi_done(cmd);
764
765 return 0;
766 }
767
768 /*
769 * qla2x00_eh_wait_on_command
770 * Waits for the command to be returned by the Firmware for some
771 * max time.
772 *
773 * Input:
774 * cmd = Scsi Command to wait on.
775 *
776 * Return:
777 * Not Found : 0
778 * Found : 1
779 */
780 static int
781 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
782 {
783 #define ABORT_POLLING_PERIOD 1000
784 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
785 unsigned long wait_iter = ABORT_WAIT_ITER;
786 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
787 struct qla_hw_data *ha = vha->hw;
788 int ret = QLA_SUCCESS;
789
790 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
791 ql_dbg(ql_dbg_taskm, vha, 0x8005,
792 "Return:eh_wait.\n");
793 return ret;
794 }
795
796 while (CMD_SP(cmd) && wait_iter--) {
797 msleep(ABORT_POLLING_PERIOD);
798 }
799 if (CMD_SP(cmd))
800 ret = QLA_FUNCTION_FAILED;
801
802 return ret;
803 }
804
805 /*
806 * qla2x00_wait_for_hba_online
807 * Wait till the HBA is online after going through
808 * <= MAX_RETRIES_OF_ISP_ABORT or
809 * finally HBA is disabled ie marked offline
810 *
811 * Input:
812 * ha - pointer to host adapter structure
813 *
814 * Note:
815 * Does context switching-Release SPIN_LOCK
816 * (if any) before calling this routine.
817 *
818 * Return:
819 * Success (Adapter is online) : 0
820 * Failed (Adapter is offline/disabled) : 1
821 */
822 int
823 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
824 {
825 int return_status;
826 unsigned long wait_online;
827 struct qla_hw_data *ha = vha->hw;
828 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
829
830 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
831 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
832 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
833 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
834 ha->dpc_active) && time_before(jiffies, wait_online)) {
835
836 msleep(1000);
837 }
838 if (base_vha->flags.online)
839 return_status = QLA_SUCCESS;
840 else
841 return_status = QLA_FUNCTION_FAILED;
842
843 return (return_status);
844 }
845
846 /*
847 * qla2x00_wait_for_hba_ready
848 * Wait till the HBA is ready before doing driver unload
849 *
850 * Input:
851 * ha - pointer to host adapter structure
852 *
853 * Note:
854 * Does context switching-Release SPIN_LOCK
855 * (if any) before calling this routine.
856 *
857 */
858 static void
859 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
860 {
861 struct qla_hw_data *ha = vha->hw;
862
863 while ((!(vha->flags.online) || ha->dpc_active ||
864 ha->flags.mbox_busy))
865 msleep(1000);
866 }
867
868 int
869 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
870 {
871 int return_status;
872 unsigned long wait_reset;
873 struct qla_hw_data *ha = vha->hw;
874 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
875
876 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
877 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
878 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
879 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
880 ha->dpc_active) && time_before(jiffies, wait_reset)) {
881
882 msleep(1000);
883
884 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
885 ha->flags.chip_reset_done)
886 break;
887 }
888 if (ha->flags.chip_reset_done)
889 return_status = QLA_SUCCESS;
890 else
891 return_status = QLA_FUNCTION_FAILED;
892
893 return return_status;
894 }
895
896 static void
897 sp_get(struct srb *sp)
898 {
899 atomic_inc(&sp->ref_count);
900 }
901
902 /**************************************************************************
903 * qla2xxx_eh_abort
904 *
905 * Description:
906 * The abort function will abort the specified command.
907 *
908 * Input:
909 * cmd = Linux SCSI command packet to be aborted.
910 *
911 * Returns:
912 * Either SUCCESS or FAILED.
913 *
914 * Note:
915 * Only return FAILED if command not returned by firmware.
916 **************************************************************************/
917 static int
918 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
919 {
920 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
921 srb_t *sp;
922 int ret;
923 unsigned int id, lun;
924 unsigned long flags;
925 int rval, wait = 0;
926 struct qla_hw_data *ha = vha->hw;
927
928 if (!CMD_SP(cmd))
929 return SUCCESS;
930
931 ret = fc_block_scsi_eh(cmd);
932 if (ret != 0)
933 return ret;
934 ret = SUCCESS;
935
936 id = cmd->device->id;
937 lun = cmd->device->lun;
938
939 spin_lock_irqsave(&ha->hardware_lock, flags);
940 sp = (srb_t *) CMD_SP(cmd);
941 if (!sp) {
942 spin_unlock_irqrestore(&ha->hardware_lock, flags);
943 return SUCCESS;
944 }
945
946 ql_dbg(ql_dbg_taskm, vha, 0x8002,
947 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n",
948 vha->host_no, id, lun, sp, cmd);
949
950 /* Get a reference to the sp and drop the lock.*/
951 sp_get(sp);
952
953 spin_unlock_irqrestore(&ha->hardware_lock, flags);
954 rval = ha->isp_ops->abort_command(sp);
955 if (rval) {
956 if (rval == QLA_FUNCTION_PARAMETER_ERROR) {
957 /*
958 * Decrement the ref_count since we can't find the
959 * command
960 */
961 atomic_dec(&sp->ref_count);
962 ret = SUCCESS;
963 } else
964 ret = FAILED;
965
966 ql_dbg(ql_dbg_taskm, vha, 0x8003,
967 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
968 } else {
969 ql_dbg(ql_dbg_taskm, vha, 0x8004,
970 "Abort command mbx success cmd=%p.\n", cmd);
971 wait = 1;
972 }
973
974 spin_lock_irqsave(&ha->hardware_lock, flags);
975 /*
976 * Clear the slot in the oustanding_cmds array if we can't find the
977 * command to reclaim the resources.
978 */
979 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
980 vha->req->outstanding_cmds[sp->handle] = NULL;
981 sp->done(ha, sp, 0);
982 spin_unlock_irqrestore(&ha->hardware_lock, flags);
983
984 /* Did the command return during mailbox execution? */
985 if (ret == FAILED && !CMD_SP(cmd))
986 ret = SUCCESS;
987
988 /* Wait for the command to be returned. */
989 if (wait) {
990 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
991 ql_log(ql_log_warn, vha, 0x8006,
992 "Abort handler timed out cmd=%p.\n", cmd);
993 ret = FAILED;
994 }
995 }
996
997 ql_log(ql_log_info, vha, 0x801c,
998 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n",
999 vha->host_no, id, lun, wait, ret);
1000
1001 return ret;
1002 }
1003
1004 int
1005 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1006 unsigned int l, enum nexus_wait_type type)
1007 {
1008 int cnt, match, status;
1009 unsigned long flags;
1010 struct qla_hw_data *ha = vha->hw;
1011 struct req_que *req;
1012 srb_t *sp;
1013 struct scsi_cmnd *cmd;
1014
1015 status = QLA_SUCCESS;
1016
1017 spin_lock_irqsave(&ha->hardware_lock, flags);
1018 req = vha->req;
1019 for (cnt = 1; status == QLA_SUCCESS &&
1020 cnt < req->num_outstanding_cmds; cnt++) {
1021 sp = req->outstanding_cmds[cnt];
1022 if (!sp)
1023 continue;
1024 if (sp->type != SRB_SCSI_CMD)
1025 continue;
1026 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1027 continue;
1028 match = 0;
1029 cmd = GET_CMD_SP(sp);
1030 switch (type) {
1031 case WAIT_HOST:
1032 match = 1;
1033 break;
1034 case WAIT_TARGET:
1035 match = cmd->device->id == t;
1036 break;
1037 case WAIT_LUN:
1038 match = (cmd->device->id == t &&
1039 cmd->device->lun == l);
1040 break;
1041 }
1042 if (!match)
1043 continue;
1044
1045 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1046 status = qla2x00_eh_wait_on_command(cmd);
1047 spin_lock_irqsave(&ha->hardware_lock, flags);
1048 }
1049 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1050
1051 return status;
1052 }
1053
1054 static char *reset_errors[] = {
1055 "HBA not online",
1056 "HBA not ready",
1057 "Task management failed",
1058 "Waiting for command completions",
1059 };
1060
1061 static int
1062 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1063 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1064 {
1065 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1066 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1067 int err;
1068
1069 if (!fcport) {
1070 return FAILED;
1071 }
1072
1073 err = fc_block_scsi_eh(cmd);
1074 if (err != 0)
1075 return err;
1076
1077 ql_log(ql_log_info, vha, 0x8009,
1078 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no,
1079 cmd->device->id, cmd->device->lun, cmd);
1080
1081 err = 0;
1082 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1083 ql_log(ql_log_warn, vha, 0x800a,
1084 "Wait for hba online failed for cmd=%p.\n", cmd);
1085 goto eh_reset_failed;
1086 }
1087 err = 2;
1088 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
1089 != QLA_SUCCESS) {
1090 ql_log(ql_log_warn, vha, 0x800c,
1091 "do_reset failed for cmd=%p.\n", cmd);
1092 goto eh_reset_failed;
1093 }
1094 err = 3;
1095 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1096 cmd->device->lun, type) != QLA_SUCCESS) {
1097 ql_log(ql_log_warn, vha, 0x800d,
1098 "wait for pending cmds failed for cmd=%p.\n", cmd);
1099 goto eh_reset_failed;
1100 }
1101
1102 ql_log(ql_log_info, vha, 0x800e,
1103 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name,
1104 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1105
1106 return SUCCESS;
1107
1108 eh_reset_failed:
1109 ql_log(ql_log_info, vha, 0x800f,
1110 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name,
1111 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1112 cmd);
1113 return FAILED;
1114 }
1115
1116 static int
1117 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1118 {
1119 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1120 struct qla_hw_data *ha = vha->hw;
1121
1122 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1123 ha->isp_ops->lun_reset);
1124 }
1125
1126 static int
1127 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1128 {
1129 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1130 struct qla_hw_data *ha = vha->hw;
1131
1132 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1133 ha->isp_ops->target_reset);
1134 }
1135
1136 /**************************************************************************
1137 * qla2xxx_eh_bus_reset
1138 *
1139 * Description:
1140 * The bus reset function will reset the bus and abort any executing
1141 * commands.
1142 *
1143 * Input:
1144 * cmd = Linux SCSI command packet of the command that cause the
1145 * bus reset.
1146 *
1147 * Returns:
1148 * SUCCESS/FAILURE (defined as macro in scsi.h).
1149 *
1150 **************************************************************************/
1151 static int
1152 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1153 {
1154 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1155 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1156 int ret = FAILED;
1157 unsigned int id, lun;
1158
1159 id = cmd->device->id;
1160 lun = cmd->device->lun;
1161
1162 if (!fcport) {
1163 return ret;
1164 }
1165
1166 ret = fc_block_scsi_eh(cmd);
1167 if (ret != 0)
1168 return ret;
1169 ret = FAILED;
1170
1171 ql_log(ql_log_info, vha, 0x8012,
1172 "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1173
1174 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1175 ql_log(ql_log_fatal, vha, 0x8013,
1176 "Wait for hba online failed board disabled.\n");
1177 goto eh_bus_reset_done;
1178 }
1179
1180 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1181 ret = SUCCESS;
1182
1183 if (ret == FAILED)
1184 goto eh_bus_reset_done;
1185
1186 /* Flush outstanding commands. */
1187 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1188 QLA_SUCCESS) {
1189 ql_log(ql_log_warn, vha, 0x8014,
1190 "Wait for pending commands failed.\n");
1191 ret = FAILED;
1192 }
1193
1194 eh_bus_reset_done:
1195 ql_log(ql_log_warn, vha, 0x802b,
1196 "BUS RESET %s nexus=%ld:%d:%d.\n",
1197 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1198
1199 return ret;
1200 }
1201
1202 /**************************************************************************
1203 * qla2xxx_eh_host_reset
1204 *
1205 * Description:
1206 * The reset function will reset the Adapter.
1207 *
1208 * Input:
1209 * cmd = Linux SCSI command packet of the command that cause the
1210 * adapter reset.
1211 *
1212 * Returns:
1213 * Either SUCCESS or FAILED.
1214 *
1215 * Note:
1216 **************************************************************************/
1217 static int
1218 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1219 {
1220 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1221 struct qla_hw_data *ha = vha->hw;
1222 int ret = FAILED;
1223 unsigned int id, lun;
1224 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1225
1226 id = cmd->device->id;
1227 lun = cmd->device->lun;
1228
1229 ql_log(ql_log_info, vha, 0x8018,
1230 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1231
1232 /*
1233 * No point in issuing another reset if one is active. Also do not
1234 * attempt a reset if we are updating flash.
1235 */
1236 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1237 goto eh_host_reset_lock;
1238
1239 if (vha != base_vha) {
1240 if (qla2x00_vp_abort_isp(vha))
1241 goto eh_host_reset_lock;
1242 } else {
1243 if (IS_P3P_TYPE(vha->hw)) {
1244 if (!qla82xx_fcoe_ctx_reset(vha)) {
1245 /* Ctx reset success */
1246 ret = SUCCESS;
1247 goto eh_host_reset_lock;
1248 }
1249 /* fall thru if ctx reset failed */
1250 }
1251 if (ha->wq)
1252 flush_workqueue(ha->wq);
1253
1254 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1255 if (ha->isp_ops->abort_isp(base_vha)) {
1256 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1257 /* failed. schedule dpc to try */
1258 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1259
1260 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1261 ql_log(ql_log_warn, vha, 0x802a,
1262 "wait for hba online failed.\n");
1263 goto eh_host_reset_lock;
1264 }
1265 }
1266 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1267 }
1268
1269 /* Waiting for command to be returned to OS.*/
1270 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1271 QLA_SUCCESS)
1272 ret = SUCCESS;
1273
1274 eh_host_reset_lock:
1275 ql_log(ql_log_info, vha, 0x8017,
1276 "ADAPTER RESET %s nexus=%ld:%d:%d.\n",
1277 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1278
1279 return ret;
1280 }
1281
1282 /*
1283 * qla2x00_loop_reset
1284 * Issue loop reset.
1285 *
1286 * Input:
1287 * ha = adapter block pointer.
1288 *
1289 * Returns:
1290 * 0 = success
1291 */
1292 int
1293 qla2x00_loop_reset(scsi_qla_host_t *vha)
1294 {
1295 int ret;
1296 struct fc_port *fcport;
1297 struct qla_hw_data *ha = vha->hw;
1298
1299 if (IS_QLAFX00(ha)) {
1300 return qlafx00_loop_reset(vha);
1301 }
1302
1303 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1304 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1305 if (fcport->port_type != FCT_TARGET)
1306 continue;
1307
1308 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1309 if (ret != QLA_SUCCESS) {
1310 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1311 "Bus Reset failed: Reset=%d "
1312 "d_id=%x.\n", ret, fcport->d_id.b24);
1313 }
1314 }
1315 }
1316
1317
1318 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1319 atomic_set(&vha->loop_state, LOOP_DOWN);
1320 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1321 qla2x00_mark_all_devices_lost(vha, 0);
1322 ret = qla2x00_full_login_lip(vha);
1323 if (ret != QLA_SUCCESS) {
1324 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1325 "full_login_lip=%d.\n", ret);
1326 }
1327 }
1328
1329 if (ha->flags.enable_lip_reset) {
1330 ret = qla2x00_lip_reset(vha);
1331 if (ret != QLA_SUCCESS)
1332 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1333 "lip_reset failed (%d).\n", ret);
1334 }
1335
1336 /* Issue marker command only when we are going to start the I/O */
1337 vha->marker_needed = 1;
1338
1339 return QLA_SUCCESS;
1340 }
1341
1342 void
1343 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1344 {
1345 int que, cnt;
1346 unsigned long flags;
1347 srb_t *sp;
1348 struct qla_hw_data *ha = vha->hw;
1349 struct req_que *req;
1350
1351 spin_lock_irqsave(&ha->hardware_lock, flags);
1352 for (que = 0; que < ha->max_req_queues; que++) {
1353 req = ha->req_q_map[que];
1354 if (!req)
1355 continue;
1356 if (!req->outstanding_cmds)
1357 continue;
1358 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1359 sp = req->outstanding_cmds[cnt];
1360 if (sp) {
1361 req->outstanding_cmds[cnt] = NULL;
1362 sp->done(vha, sp, res);
1363 }
1364 }
1365 }
1366 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1367 }
1368
1369 static int
1370 qla2xxx_slave_alloc(struct scsi_device *sdev)
1371 {
1372 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1373
1374 if (!rport || fc_remote_port_chkready(rport))
1375 return -ENXIO;
1376
1377 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1378
1379 return 0;
1380 }
1381
1382 static int
1383 qla2xxx_slave_configure(struct scsi_device *sdev)
1384 {
1385 scsi_qla_host_t *vha = shost_priv(sdev->host);
1386 struct req_que *req = vha->req;
1387
1388 if (IS_T10_PI_CAPABLE(vha->hw))
1389 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1390
1391 if (sdev->tagged_supported)
1392 scsi_activate_tcq(sdev, req->max_q_depth);
1393 else
1394 scsi_deactivate_tcq(sdev, req->max_q_depth);
1395 return 0;
1396 }
1397
1398 static void
1399 qla2xxx_slave_destroy(struct scsi_device *sdev)
1400 {
1401 sdev->hostdata = NULL;
1402 }
1403
1404 static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1405 {
1406 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1407
1408 if (!scsi_track_queue_full(sdev, qdepth))
1409 return;
1410
1411 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
1412 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n",
1413 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
1414 }
1415
1416 static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1417 {
1418 fc_port_t *fcport = sdev->hostdata;
1419 struct scsi_qla_host *vha = fcport->vha;
1420 struct req_que *req = NULL;
1421
1422 req = vha->req;
1423 if (!req)
1424 return;
1425
1426 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1427 return;
1428
1429 if (sdev->ordered_tags)
1430 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1431 else
1432 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1433
1434 ql_dbg(ql_dbg_io, vha, 0x302a,
1435 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n",
1436 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
1437 }
1438
1439 static int
1440 qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
1441 {
1442 switch (reason) {
1443 case SCSI_QDEPTH_DEFAULT:
1444 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1445 break;
1446 case SCSI_QDEPTH_QFULL:
1447 qla2x00_handle_queue_full(sdev, qdepth);
1448 break;
1449 case SCSI_QDEPTH_RAMP_UP:
1450 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1451 break;
1452 default:
1453 return -EOPNOTSUPP;
1454 }
1455
1456 return sdev->queue_depth;
1457 }
1458
1459 static int
1460 qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1461 {
1462 if (sdev->tagged_supported) {
1463 scsi_set_tag_type(sdev, tag_type);
1464 if (tag_type)
1465 scsi_activate_tcq(sdev, sdev->queue_depth);
1466 else
1467 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1468 } else
1469 tag_type = 0;
1470
1471 return tag_type;
1472 }
1473
1474 /**
1475 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1476 * @ha: HA context
1477 *
1478 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1479 * supported addressing method.
1480 */
1481 static void
1482 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1483 {
1484 /* Assume a 32bit DMA mask. */
1485 ha->flags.enable_64bit_addressing = 0;
1486
1487 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1488 /* Any upper-dword bits set? */
1489 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1490 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1491 /* Ok, a 64bit DMA mask is applicable. */
1492 ha->flags.enable_64bit_addressing = 1;
1493 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1494 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1495 return;
1496 }
1497 }
1498
1499 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1500 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1501 }
1502
1503 static void
1504 qla2x00_enable_intrs(struct qla_hw_data *ha)
1505 {
1506 unsigned long flags = 0;
1507 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1508
1509 spin_lock_irqsave(&ha->hardware_lock, flags);
1510 ha->interrupts_on = 1;
1511 /* enable risc and host interrupts */
1512 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1513 RD_REG_WORD(&reg->ictrl);
1514 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1515
1516 }
1517
1518 static void
1519 qla2x00_disable_intrs(struct qla_hw_data *ha)
1520 {
1521 unsigned long flags = 0;
1522 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1523
1524 spin_lock_irqsave(&ha->hardware_lock, flags);
1525 ha->interrupts_on = 0;
1526 /* disable risc and host interrupts */
1527 WRT_REG_WORD(&reg->ictrl, 0);
1528 RD_REG_WORD(&reg->ictrl);
1529 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1530 }
1531
1532 static void
1533 qla24xx_enable_intrs(struct qla_hw_data *ha)
1534 {
1535 unsigned long flags = 0;
1536 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1537
1538 spin_lock_irqsave(&ha->hardware_lock, flags);
1539 ha->interrupts_on = 1;
1540 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1541 RD_REG_DWORD(&reg->ictrl);
1542 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1543 }
1544
1545 static void
1546 qla24xx_disable_intrs(struct qla_hw_data *ha)
1547 {
1548 unsigned long flags = 0;
1549 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1550
1551 if (IS_NOPOLLING_TYPE(ha))
1552 return;
1553 spin_lock_irqsave(&ha->hardware_lock, flags);
1554 ha->interrupts_on = 0;
1555 WRT_REG_DWORD(&reg->ictrl, 0);
1556 RD_REG_DWORD(&reg->ictrl);
1557 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1558 }
1559
1560 static int
1561 qla2x00_iospace_config(struct qla_hw_data *ha)
1562 {
1563 resource_size_t pio;
1564 uint16_t msix;
1565 int cpus;
1566
1567 if (pci_request_selected_regions(ha->pdev, ha->bars,
1568 QLA2XXX_DRIVER_NAME)) {
1569 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1570 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1571 pci_name(ha->pdev));
1572 goto iospace_error_exit;
1573 }
1574 if (!(ha->bars & 1))
1575 goto skip_pio;
1576
1577 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1578 pio = pci_resource_start(ha->pdev, 0);
1579 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1580 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1581 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1582 "Invalid pci I/O region size (%s).\n",
1583 pci_name(ha->pdev));
1584 pio = 0;
1585 }
1586 } else {
1587 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1588 "Region #0 no a PIO resource (%s).\n",
1589 pci_name(ha->pdev));
1590 pio = 0;
1591 }
1592 ha->pio_address = pio;
1593 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1594 "PIO address=%llu.\n",
1595 (unsigned long long)ha->pio_address);
1596
1597 skip_pio:
1598 /* Use MMIO operations for all accesses. */
1599 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1600 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1601 "Region #1 not an MMIO resource (%s), aborting.\n",
1602 pci_name(ha->pdev));
1603 goto iospace_error_exit;
1604 }
1605 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1606 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1607 "Invalid PCI mem region size (%s), aborting.\n",
1608 pci_name(ha->pdev));
1609 goto iospace_error_exit;
1610 }
1611
1612 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1613 if (!ha->iobase) {
1614 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1615 "Cannot remap MMIO (%s), aborting.\n",
1616 pci_name(ha->pdev));
1617 goto iospace_error_exit;
1618 }
1619
1620 /* Determine queue resources */
1621 ha->max_req_queues = ha->max_rsp_queues = 1;
1622 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1623 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1624 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1625 goto mqiobase_exit;
1626
1627 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1628 pci_resource_len(ha->pdev, 3));
1629 if (ha->mqiobase) {
1630 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1631 "MQIO Base=%p.\n", ha->mqiobase);
1632 /* Read MSIX vector size of the board */
1633 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1634 ha->msix_count = msix;
1635 /* Max queues are bounded by available msix vectors */
1636 /* queue 0 uses two msix vectors */
1637 if (ql2xmultique_tag) {
1638 cpus = num_online_cpus();
1639 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1640 (cpus + 1) : (ha->msix_count - 1);
1641 ha->max_req_queues = 2;
1642 } else if (ql2xmaxqueues > 1) {
1643 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1644 QLA_MQ_SIZE : ql2xmaxqueues;
1645 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1646 "QoS mode set, max no of request queues:%d.\n",
1647 ha->max_req_queues);
1648 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1649 "QoS mode set, max no of request queues:%d.\n",
1650 ha->max_req_queues);
1651 }
1652 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1653 "MSI-X vector count: %d.\n", msix);
1654 } else
1655 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1656 "BAR 3 not enabled.\n");
1657
1658 mqiobase_exit:
1659 ha->msix_count = ha->max_rsp_queues + 1;
1660 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1661 "MSIX Count:%d.\n", ha->msix_count);
1662 return (0);
1663
1664 iospace_error_exit:
1665 return (-ENOMEM);
1666 }
1667
1668
1669 static int
1670 qla83xx_iospace_config(struct qla_hw_data *ha)
1671 {
1672 uint16_t msix;
1673 int cpus;
1674
1675 if (pci_request_selected_regions(ha->pdev, ha->bars,
1676 QLA2XXX_DRIVER_NAME)) {
1677 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1678 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1679 pci_name(ha->pdev));
1680
1681 goto iospace_error_exit;
1682 }
1683
1684 /* Use MMIO operations for all accesses. */
1685 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1686 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1687 "Invalid pci I/O region size (%s).\n",
1688 pci_name(ha->pdev));
1689 goto iospace_error_exit;
1690 }
1691 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1692 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1693 "Invalid PCI mem region size (%s), aborting\n",
1694 pci_name(ha->pdev));
1695 goto iospace_error_exit;
1696 }
1697
1698 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1699 if (!ha->iobase) {
1700 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1701 "Cannot remap MMIO (%s), aborting.\n",
1702 pci_name(ha->pdev));
1703 goto iospace_error_exit;
1704 }
1705
1706 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1707 /* 83XX 26XX always use MQ type access for queues
1708 * - mbar 2, a.k.a region 4 */
1709 ha->max_req_queues = ha->max_rsp_queues = 1;
1710 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1711 pci_resource_len(ha->pdev, 4));
1712
1713 if (!ha->mqiobase) {
1714 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1715 "BAR2/region4 not enabled\n");
1716 goto mqiobase_exit;
1717 }
1718
1719 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1720 pci_resource_len(ha->pdev, 2));
1721 if (ha->msixbase) {
1722 /* Read MSIX vector size of the board */
1723 pci_read_config_word(ha->pdev,
1724 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1725 ha->msix_count = msix;
1726 /* Max queues are bounded by available msix vectors */
1727 /* queue 0 uses two msix vectors */
1728 if (ql2xmultique_tag) {
1729 cpus = num_online_cpus();
1730 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1731 (cpus + 1) : (ha->msix_count - 1);
1732 ha->max_req_queues = 2;
1733 } else if (ql2xmaxqueues > 1) {
1734 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1735 QLA_MQ_SIZE : ql2xmaxqueues;
1736 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1737 "QoS mode set, max no of request queues:%d.\n",
1738 ha->max_req_queues);
1739 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1740 "QoS mode set, max no of request queues:%d.\n",
1741 ha->max_req_queues);
1742 }
1743 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1744 "MSI-X vector count: %d.\n", msix);
1745 } else
1746 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1747 "BAR 1 not enabled.\n");
1748
1749 mqiobase_exit:
1750 ha->msix_count = ha->max_rsp_queues + 1;
1751
1752 qlt_83xx_iospace_config(ha);
1753
1754 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1755 "MSIX Count:%d.\n", ha->msix_count);
1756 return 0;
1757
1758 iospace_error_exit:
1759 return -ENOMEM;
1760 }
1761
1762 static struct isp_operations qla2100_isp_ops = {
1763 .pci_config = qla2100_pci_config,
1764 .reset_chip = qla2x00_reset_chip,
1765 .chip_diag = qla2x00_chip_diag,
1766 .config_rings = qla2x00_config_rings,
1767 .reset_adapter = qla2x00_reset_adapter,
1768 .nvram_config = qla2x00_nvram_config,
1769 .update_fw_options = qla2x00_update_fw_options,
1770 .load_risc = qla2x00_load_risc,
1771 .pci_info_str = qla2x00_pci_info_str,
1772 .fw_version_str = qla2x00_fw_version_str,
1773 .intr_handler = qla2100_intr_handler,
1774 .enable_intrs = qla2x00_enable_intrs,
1775 .disable_intrs = qla2x00_disable_intrs,
1776 .abort_command = qla2x00_abort_command,
1777 .target_reset = qla2x00_abort_target,
1778 .lun_reset = qla2x00_lun_reset,
1779 .fabric_login = qla2x00_login_fabric,
1780 .fabric_logout = qla2x00_fabric_logout,
1781 .calc_req_entries = qla2x00_calc_iocbs_32,
1782 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1783 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1784 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1785 .read_nvram = qla2x00_read_nvram_data,
1786 .write_nvram = qla2x00_write_nvram_data,
1787 .fw_dump = qla2100_fw_dump,
1788 .beacon_on = NULL,
1789 .beacon_off = NULL,
1790 .beacon_blink = NULL,
1791 .read_optrom = qla2x00_read_optrom_data,
1792 .write_optrom = qla2x00_write_optrom_data,
1793 .get_flash_version = qla2x00_get_flash_version,
1794 .start_scsi = qla2x00_start_scsi,
1795 .abort_isp = qla2x00_abort_isp,
1796 .iospace_config = qla2x00_iospace_config,
1797 .initialize_adapter = qla2x00_initialize_adapter,
1798 };
1799
1800 static struct isp_operations qla2300_isp_ops = {
1801 .pci_config = qla2300_pci_config,
1802 .reset_chip = qla2x00_reset_chip,
1803 .chip_diag = qla2x00_chip_diag,
1804 .config_rings = qla2x00_config_rings,
1805 .reset_adapter = qla2x00_reset_adapter,
1806 .nvram_config = qla2x00_nvram_config,
1807 .update_fw_options = qla2x00_update_fw_options,
1808 .load_risc = qla2x00_load_risc,
1809 .pci_info_str = qla2x00_pci_info_str,
1810 .fw_version_str = qla2x00_fw_version_str,
1811 .intr_handler = qla2300_intr_handler,
1812 .enable_intrs = qla2x00_enable_intrs,
1813 .disable_intrs = qla2x00_disable_intrs,
1814 .abort_command = qla2x00_abort_command,
1815 .target_reset = qla2x00_abort_target,
1816 .lun_reset = qla2x00_lun_reset,
1817 .fabric_login = qla2x00_login_fabric,
1818 .fabric_logout = qla2x00_fabric_logout,
1819 .calc_req_entries = qla2x00_calc_iocbs_32,
1820 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1821 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1822 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1823 .read_nvram = qla2x00_read_nvram_data,
1824 .write_nvram = qla2x00_write_nvram_data,
1825 .fw_dump = qla2300_fw_dump,
1826 .beacon_on = qla2x00_beacon_on,
1827 .beacon_off = qla2x00_beacon_off,
1828 .beacon_blink = qla2x00_beacon_blink,
1829 .read_optrom = qla2x00_read_optrom_data,
1830 .write_optrom = qla2x00_write_optrom_data,
1831 .get_flash_version = qla2x00_get_flash_version,
1832 .start_scsi = qla2x00_start_scsi,
1833 .abort_isp = qla2x00_abort_isp,
1834 .iospace_config = qla2x00_iospace_config,
1835 .initialize_adapter = qla2x00_initialize_adapter,
1836 };
1837
1838 static struct isp_operations qla24xx_isp_ops = {
1839 .pci_config = qla24xx_pci_config,
1840 .reset_chip = qla24xx_reset_chip,
1841 .chip_diag = qla24xx_chip_diag,
1842 .config_rings = qla24xx_config_rings,
1843 .reset_adapter = qla24xx_reset_adapter,
1844 .nvram_config = qla24xx_nvram_config,
1845 .update_fw_options = qla24xx_update_fw_options,
1846 .load_risc = qla24xx_load_risc,
1847 .pci_info_str = qla24xx_pci_info_str,
1848 .fw_version_str = qla24xx_fw_version_str,
1849 .intr_handler = qla24xx_intr_handler,
1850 .enable_intrs = qla24xx_enable_intrs,
1851 .disable_intrs = qla24xx_disable_intrs,
1852 .abort_command = qla24xx_abort_command,
1853 .target_reset = qla24xx_abort_target,
1854 .lun_reset = qla24xx_lun_reset,
1855 .fabric_login = qla24xx_login_fabric,
1856 .fabric_logout = qla24xx_fabric_logout,
1857 .calc_req_entries = NULL,
1858 .build_iocbs = NULL,
1859 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1860 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1861 .read_nvram = qla24xx_read_nvram_data,
1862 .write_nvram = qla24xx_write_nvram_data,
1863 .fw_dump = qla24xx_fw_dump,
1864 .beacon_on = qla24xx_beacon_on,
1865 .beacon_off = qla24xx_beacon_off,
1866 .beacon_blink = qla24xx_beacon_blink,
1867 .read_optrom = qla24xx_read_optrom_data,
1868 .write_optrom = qla24xx_write_optrom_data,
1869 .get_flash_version = qla24xx_get_flash_version,
1870 .start_scsi = qla24xx_start_scsi,
1871 .abort_isp = qla2x00_abort_isp,
1872 .iospace_config = qla2x00_iospace_config,
1873 .initialize_adapter = qla2x00_initialize_adapter,
1874 };
1875
1876 static struct isp_operations qla25xx_isp_ops = {
1877 .pci_config = qla25xx_pci_config,
1878 .reset_chip = qla24xx_reset_chip,
1879 .chip_diag = qla24xx_chip_diag,
1880 .config_rings = qla24xx_config_rings,
1881 .reset_adapter = qla24xx_reset_adapter,
1882 .nvram_config = qla24xx_nvram_config,
1883 .update_fw_options = qla24xx_update_fw_options,
1884 .load_risc = qla24xx_load_risc,
1885 .pci_info_str = qla24xx_pci_info_str,
1886 .fw_version_str = qla24xx_fw_version_str,
1887 .intr_handler = qla24xx_intr_handler,
1888 .enable_intrs = qla24xx_enable_intrs,
1889 .disable_intrs = qla24xx_disable_intrs,
1890 .abort_command = qla24xx_abort_command,
1891 .target_reset = qla24xx_abort_target,
1892 .lun_reset = qla24xx_lun_reset,
1893 .fabric_login = qla24xx_login_fabric,
1894 .fabric_logout = qla24xx_fabric_logout,
1895 .calc_req_entries = NULL,
1896 .build_iocbs = NULL,
1897 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1898 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1899 .read_nvram = qla25xx_read_nvram_data,
1900 .write_nvram = qla25xx_write_nvram_data,
1901 .fw_dump = qla25xx_fw_dump,
1902 .beacon_on = qla24xx_beacon_on,
1903 .beacon_off = qla24xx_beacon_off,
1904 .beacon_blink = qla24xx_beacon_blink,
1905 .read_optrom = qla25xx_read_optrom_data,
1906 .write_optrom = qla24xx_write_optrom_data,
1907 .get_flash_version = qla24xx_get_flash_version,
1908 .start_scsi = qla24xx_dif_start_scsi,
1909 .abort_isp = qla2x00_abort_isp,
1910 .iospace_config = qla2x00_iospace_config,
1911 .initialize_adapter = qla2x00_initialize_adapter,
1912 };
1913
1914 static struct isp_operations qla81xx_isp_ops = {
1915 .pci_config = qla25xx_pci_config,
1916 .reset_chip = qla24xx_reset_chip,
1917 .chip_diag = qla24xx_chip_diag,
1918 .config_rings = qla24xx_config_rings,
1919 .reset_adapter = qla24xx_reset_adapter,
1920 .nvram_config = qla81xx_nvram_config,
1921 .update_fw_options = qla81xx_update_fw_options,
1922 .load_risc = qla81xx_load_risc,
1923 .pci_info_str = qla24xx_pci_info_str,
1924 .fw_version_str = qla24xx_fw_version_str,
1925 .intr_handler = qla24xx_intr_handler,
1926 .enable_intrs = qla24xx_enable_intrs,
1927 .disable_intrs = qla24xx_disable_intrs,
1928 .abort_command = qla24xx_abort_command,
1929 .target_reset = qla24xx_abort_target,
1930 .lun_reset = qla24xx_lun_reset,
1931 .fabric_login = qla24xx_login_fabric,
1932 .fabric_logout = qla24xx_fabric_logout,
1933 .calc_req_entries = NULL,
1934 .build_iocbs = NULL,
1935 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1936 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1937 .read_nvram = NULL,
1938 .write_nvram = NULL,
1939 .fw_dump = qla81xx_fw_dump,
1940 .beacon_on = qla24xx_beacon_on,
1941 .beacon_off = qla24xx_beacon_off,
1942 .beacon_blink = qla83xx_beacon_blink,
1943 .read_optrom = qla25xx_read_optrom_data,
1944 .write_optrom = qla24xx_write_optrom_data,
1945 .get_flash_version = qla24xx_get_flash_version,
1946 .start_scsi = qla24xx_dif_start_scsi,
1947 .abort_isp = qla2x00_abort_isp,
1948 .iospace_config = qla2x00_iospace_config,
1949 .initialize_adapter = qla2x00_initialize_adapter,
1950 };
1951
1952 static struct isp_operations qla82xx_isp_ops = {
1953 .pci_config = qla82xx_pci_config,
1954 .reset_chip = qla82xx_reset_chip,
1955 .chip_diag = qla24xx_chip_diag,
1956 .config_rings = qla82xx_config_rings,
1957 .reset_adapter = qla24xx_reset_adapter,
1958 .nvram_config = qla81xx_nvram_config,
1959 .update_fw_options = qla24xx_update_fw_options,
1960 .load_risc = qla82xx_load_risc,
1961 .pci_info_str = qla24xx_pci_info_str,
1962 .fw_version_str = qla24xx_fw_version_str,
1963 .intr_handler = qla82xx_intr_handler,
1964 .enable_intrs = qla82xx_enable_intrs,
1965 .disable_intrs = qla82xx_disable_intrs,
1966 .abort_command = qla24xx_abort_command,
1967 .target_reset = qla24xx_abort_target,
1968 .lun_reset = qla24xx_lun_reset,
1969 .fabric_login = qla24xx_login_fabric,
1970 .fabric_logout = qla24xx_fabric_logout,
1971 .calc_req_entries = NULL,
1972 .build_iocbs = NULL,
1973 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1974 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1975 .read_nvram = qla24xx_read_nvram_data,
1976 .write_nvram = qla24xx_write_nvram_data,
1977 .fw_dump = qla82xx_fw_dump,
1978 .beacon_on = qla82xx_beacon_on,
1979 .beacon_off = qla82xx_beacon_off,
1980 .beacon_blink = NULL,
1981 .read_optrom = qla82xx_read_optrom_data,
1982 .write_optrom = qla82xx_write_optrom_data,
1983 .get_flash_version = qla82xx_get_flash_version,
1984 .start_scsi = qla82xx_start_scsi,
1985 .abort_isp = qla82xx_abort_isp,
1986 .iospace_config = qla82xx_iospace_config,
1987 .initialize_adapter = qla2x00_initialize_adapter,
1988 };
1989
1990 static struct isp_operations qla8044_isp_ops = {
1991 .pci_config = qla82xx_pci_config,
1992 .reset_chip = qla82xx_reset_chip,
1993 .chip_diag = qla24xx_chip_diag,
1994 .config_rings = qla82xx_config_rings,
1995 .reset_adapter = qla24xx_reset_adapter,
1996 .nvram_config = qla81xx_nvram_config,
1997 .update_fw_options = qla24xx_update_fw_options,
1998 .load_risc = qla82xx_load_risc,
1999 .pci_info_str = qla24xx_pci_info_str,
2000 .fw_version_str = qla24xx_fw_version_str,
2001 .intr_handler = qla8044_intr_handler,
2002 .enable_intrs = qla82xx_enable_intrs,
2003 .disable_intrs = qla82xx_disable_intrs,
2004 .abort_command = qla24xx_abort_command,
2005 .target_reset = qla24xx_abort_target,
2006 .lun_reset = qla24xx_lun_reset,
2007 .fabric_login = qla24xx_login_fabric,
2008 .fabric_logout = qla24xx_fabric_logout,
2009 .calc_req_entries = NULL,
2010 .build_iocbs = NULL,
2011 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2012 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2013 .read_nvram = NULL,
2014 .write_nvram = NULL,
2015 .fw_dump = qla8044_fw_dump,
2016 .beacon_on = qla82xx_beacon_on,
2017 .beacon_off = qla82xx_beacon_off,
2018 .beacon_blink = NULL,
2019 .read_optrom = qla8044_read_optrom_data,
2020 .write_optrom = qla8044_write_optrom_data,
2021 .get_flash_version = qla82xx_get_flash_version,
2022 .start_scsi = qla82xx_start_scsi,
2023 .abort_isp = qla8044_abort_isp,
2024 .iospace_config = qla82xx_iospace_config,
2025 .initialize_adapter = qla2x00_initialize_adapter,
2026 };
2027
2028 static struct isp_operations qla83xx_isp_ops = {
2029 .pci_config = qla25xx_pci_config,
2030 .reset_chip = qla24xx_reset_chip,
2031 .chip_diag = qla24xx_chip_diag,
2032 .config_rings = qla24xx_config_rings,
2033 .reset_adapter = qla24xx_reset_adapter,
2034 .nvram_config = qla81xx_nvram_config,
2035 .update_fw_options = qla81xx_update_fw_options,
2036 .load_risc = qla81xx_load_risc,
2037 .pci_info_str = qla24xx_pci_info_str,
2038 .fw_version_str = qla24xx_fw_version_str,
2039 .intr_handler = qla24xx_intr_handler,
2040 .enable_intrs = qla24xx_enable_intrs,
2041 .disable_intrs = qla24xx_disable_intrs,
2042 .abort_command = qla24xx_abort_command,
2043 .target_reset = qla24xx_abort_target,
2044 .lun_reset = qla24xx_lun_reset,
2045 .fabric_login = qla24xx_login_fabric,
2046 .fabric_logout = qla24xx_fabric_logout,
2047 .calc_req_entries = NULL,
2048 .build_iocbs = NULL,
2049 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2050 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2051 .read_nvram = NULL,
2052 .write_nvram = NULL,
2053 .fw_dump = qla83xx_fw_dump,
2054 .beacon_on = qla24xx_beacon_on,
2055 .beacon_off = qla24xx_beacon_off,
2056 .beacon_blink = qla83xx_beacon_blink,
2057 .read_optrom = qla25xx_read_optrom_data,
2058 .write_optrom = qla24xx_write_optrom_data,
2059 .get_flash_version = qla24xx_get_flash_version,
2060 .start_scsi = qla24xx_dif_start_scsi,
2061 .abort_isp = qla2x00_abort_isp,
2062 .iospace_config = qla83xx_iospace_config,
2063 .initialize_adapter = qla2x00_initialize_adapter,
2064 };
2065
2066 static struct isp_operations qlafx00_isp_ops = {
2067 .pci_config = qlafx00_pci_config,
2068 .reset_chip = qlafx00_soft_reset,
2069 .chip_diag = qlafx00_chip_diag,
2070 .config_rings = qlafx00_config_rings,
2071 .reset_adapter = qlafx00_soft_reset,
2072 .nvram_config = NULL,
2073 .update_fw_options = NULL,
2074 .load_risc = NULL,
2075 .pci_info_str = qlafx00_pci_info_str,
2076 .fw_version_str = qlafx00_fw_version_str,
2077 .intr_handler = qlafx00_intr_handler,
2078 .enable_intrs = qlafx00_enable_intrs,
2079 .disable_intrs = qlafx00_disable_intrs,
2080 .abort_command = qla24xx_async_abort_command,
2081 .target_reset = qlafx00_abort_target,
2082 .lun_reset = qlafx00_lun_reset,
2083 .fabric_login = NULL,
2084 .fabric_logout = NULL,
2085 .calc_req_entries = NULL,
2086 .build_iocbs = NULL,
2087 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2088 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2089 .read_nvram = qla24xx_read_nvram_data,
2090 .write_nvram = qla24xx_write_nvram_data,
2091 .fw_dump = NULL,
2092 .beacon_on = qla24xx_beacon_on,
2093 .beacon_off = qla24xx_beacon_off,
2094 .beacon_blink = NULL,
2095 .read_optrom = qla24xx_read_optrom_data,
2096 .write_optrom = qla24xx_write_optrom_data,
2097 .get_flash_version = qla24xx_get_flash_version,
2098 .start_scsi = qlafx00_start_scsi,
2099 .abort_isp = qlafx00_abort_isp,
2100 .iospace_config = qlafx00_iospace_config,
2101 .initialize_adapter = qlafx00_initialize_adapter,
2102 };
2103
2104 static struct isp_operations qla27xx_isp_ops = {
2105 .pci_config = qla25xx_pci_config,
2106 .reset_chip = qla24xx_reset_chip,
2107 .chip_diag = qla24xx_chip_diag,
2108 .config_rings = qla24xx_config_rings,
2109 .reset_adapter = qla24xx_reset_adapter,
2110 .nvram_config = qla81xx_nvram_config,
2111 .update_fw_options = qla81xx_update_fw_options,
2112 .load_risc = qla81xx_load_risc,
2113 .pci_info_str = qla24xx_pci_info_str,
2114 .fw_version_str = qla24xx_fw_version_str,
2115 .intr_handler = qla24xx_intr_handler,
2116 .enable_intrs = qla24xx_enable_intrs,
2117 .disable_intrs = qla24xx_disable_intrs,
2118 .abort_command = qla24xx_abort_command,
2119 .target_reset = qla24xx_abort_target,
2120 .lun_reset = qla24xx_lun_reset,
2121 .fabric_login = qla24xx_login_fabric,
2122 .fabric_logout = qla24xx_fabric_logout,
2123 .calc_req_entries = NULL,
2124 .build_iocbs = NULL,
2125 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2126 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2127 .read_nvram = NULL,
2128 .write_nvram = NULL,
2129 .fw_dump = qla27xx_fwdump,
2130 .beacon_on = qla24xx_beacon_on,
2131 .beacon_off = qla24xx_beacon_off,
2132 .beacon_blink = qla83xx_beacon_blink,
2133 .read_optrom = qla25xx_read_optrom_data,
2134 .write_optrom = qla24xx_write_optrom_data,
2135 .get_flash_version = qla24xx_get_flash_version,
2136 .start_scsi = qla24xx_dif_start_scsi,
2137 .abort_isp = qla2x00_abort_isp,
2138 .iospace_config = qla83xx_iospace_config,
2139 .initialize_adapter = qla2x00_initialize_adapter,
2140 };
2141
2142 static inline void
2143 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2144 {
2145 ha->device_type = DT_EXTENDED_IDS;
2146 switch (ha->pdev->device) {
2147 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2148 ha->device_type |= DT_ISP2100;
2149 ha->device_type &= ~DT_EXTENDED_IDS;
2150 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2151 break;
2152 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2153 ha->device_type |= DT_ISP2200;
2154 ha->device_type &= ~DT_EXTENDED_IDS;
2155 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2156 break;
2157 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2158 ha->device_type |= DT_ISP2300;
2159 ha->device_type |= DT_ZIO_SUPPORTED;
2160 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2161 break;
2162 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2163 ha->device_type |= DT_ISP2312;
2164 ha->device_type |= DT_ZIO_SUPPORTED;
2165 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2166 break;
2167 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2168 ha->device_type |= DT_ISP2322;
2169 ha->device_type |= DT_ZIO_SUPPORTED;
2170 if (ha->pdev->subsystem_vendor == 0x1028 &&
2171 ha->pdev->subsystem_device == 0x0170)
2172 ha->device_type |= DT_OEM_001;
2173 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2174 break;
2175 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2176 ha->device_type |= DT_ISP6312;
2177 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2178 break;
2179 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2180 ha->device_type |= DT_ISP6322;
2181 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2182 break;
2183 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2184 ha->device_type |= DT_ISP2422;
2185 ha->device_type |= DT_ZIO_SUPPORTED;
2186 ha->device_type |= DT_FWI2;
2187 ha->device_type |= DT_IIDMA;
2188 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2189 break;
2190 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2191 ha->device_type |= DT_ISP2432;
2192 ha->device_type |= DT_ZIO_SUPPORTED;
2193 ha->device_type |= DT_FWI2;
2194 ha->device_type |= DT_IIDMA;
2195 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2196 break;
2197 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2198 ha->device_type |= DT_ISP8432;
2199 ha->device_type |= DT_ZIO_SUPPORTED;
2200 ha->device_type |= DT_FWI2;
2201 ha->device_type |= DT_IIDMA;
2202 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2203 break;
2204 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2205 ha->device_type |= DT_ISP5422;
2206 ha->device_type |= DT_FWI2;
2207 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2208 break;
2209 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2210 ha->device_type |= DT_ISP5432;
2211 ha->device_type |= DT_FWI2;
2212 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2213 break;
2214 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2215 ha->device_type |= DT_ISP2532;
2216 ha->device_type |= DT_ZIO_SUPPORTED;
2217 ha->device_type |= DT_FWI2;
2218 ha->device_type |= DT_IIDMA;
2219 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2220 break;
2221 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2222 ha->device_type |= DT_ISP8001;
2223 ha->device_type |= DT_ZIO_SUPPORTED;
2224 ha->device_type |= DT_FWI2;
2225 ha->device_type |= DT_IIDMA;
2226 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2227 break;
2228 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2229 ha->device_type |= DT_ISP8021;
2230 ha->device_type |= DT_ZIO_SUPPORTED;
2231 ha->device_type |= DT_FWI2;
2232 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2233 /* Initialize 82XX ISP flags */
2234 qla82xx_init_flags(ha);
2235 break;
2236 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2237 ha->device_type |= DT_ISP8044;
2238 ha->device_type |= DT_ZIO_SUPPORTED;
2239 ha->device_type |= DT_FWI2;
2240 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2241 /* Initialize 82XX ISP flags */
2242 qla82xx_init_flags(ha);
2243 break;
2244 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2245 ha->device_type |= DT_ISP2031;
2246 ha->device_type |= DT_ZIO_SUPPORTED;
2247 ha->device_type |= DT_FWI2;
2248 ha->device_type |= DT_IIDMA;
2249 ha->device_type |= DT_T10_PI;
2250 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2251 break;
2252 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2253 ha->device_type |= DT_ISP8031;
2254 ha->device_type |= DT_ZIO_SUPPORTED;
2255 ha->device_type |= DT_FWI2;
2256 ha->device_type |= DT_IIDMA;
2257 ha->device_type |= DT_T10_PI;
2258 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2259 break;
2260 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2261 ha->device_type |= DT_ISPFX00;
2262 break;
2263 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2264 ha->device_type |= DT_ISP2071;
2265 ha->device_type |= DT_ZIO_SUPPORTED;
2266 ha->device_type |= DT_FWI2;
2267 ha->device_type |= DT_IIDMA;
2268 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2269 break;
2270 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2271 ha->device_type |= DT_ISP2271;
2272 ha->device_type |= DT_ZIO_SUPPORTED;
2273 ha->device_type |= DT_FWI2;
2274 ha->device_type |= DT_IIDMA;
2275 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2276 break;
2277 }
2278
2279 if (IS_QLA82XX(ha))
2280 ha->port_no = ha->portnum & 1;
2281 else {
2282 /* Get adapter physical port no from interrupt pin register. */
2283 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2284 if (IS_QLA27XX(ha))
2285 ha->port_no--;
2286 else
2287 ha->port_no = !(ha->port_no & 1);
2288 }
2289
2290 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2291 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2292 ha->device_type, ha->port_no, ha->fw_srisc_address);
2293 }
2294
2295 static void
2296 qla2xxx_scan_start(struct Scsi_Host *shost)
2297 {
2298 scsi_qla_host_t *vha = shost_priv(shost);
2299
2300 if (vha->hw->flags.running_gold_fw)
2301 return;
2302
2303 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2304 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2305 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2306 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2307 }
2308
2309 static int
2310 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2311 {
2312 scsi_qla_host_t *vha = shost_priv(shost);
2313
2314 if (!vha->host)
2315 return 1;
2316 if (time > vha->hw->loop_reset_delay * HZ)
2317 return 1;
2318
2319 return atomic_read(&vha->loop_state) == LOOP_READY;
2320 }
2321
2322 /*
2323 * PCI driver interface
2324 */
2325 static int
2326 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2327 {
2328 int ret = -ENODEV;
2329 struct Scsi_Host *host;
2330 scsi_qla_host_t *base_vha = NULL;
2331 struct qla_hw_data *ha;
2332 char pci_info[30];
2333 char fw_str[30], wq_name[30];
2334 struct scsi_host_template *sht;
2335 int bars, mem_only = 0;
2336 uint16_t req_length = 0, rsp_length = 0;
2337 struct req_que *req = NULL;
2338 struct rsp_que *rsp = NULL;
2339 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2340 sht = &qla2xxx_driver_template;
2341 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2342 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2343 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2344 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2345 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2346 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2347 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2348 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2349 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2350 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2351 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2352 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2353 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2354 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271) {
2355 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2356 mem_only = 1;
2357 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2358 "Mem only adapter.\n");
2359 }
2360 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2361 "Bars=%d.\n", bars);
2362
2363 if (mem_only) {
2364 if (pci_enable_device_mem(pdev))
2365 goto probe_out;
2366 } else {
2367 if (pci_enable_device(pdev))
2368 goto probe_out;
2369 }
2370
2371 /* This may fail but that's ok */
2372 pci_enable_pcie_error_reporting(pdev);
2373
2374 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2375 if (!ha) {
2376 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2377 "Unable to allocate memory for ha.\n");
2378 goto probe_out;
2379 }
2380 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2381 "Memory allocated for ha=%p.\n", ha);
2382 ha->pdev = pdev;
2383 ha->tgt.enable_class_2 = ql2xenableclass2;
2384
2385 /* Clear our data area */
2386 ha->bars = bars;
2387 ha->mem_only = mem_only;
2388 spin_lock_init(&ha->hardware_lock);
2389 spin_lock_init(&ha->vport_slock);
2390 mutex_init(&ha->selflogin_lock);
2391 mutex_init(&ha->optrom_mutex);
2392
2393 /* Set ISP-type information. */
2394 qla2x00_set_isp_flags(ha);
2395
2396 /* Set EEH reset type to fundamental if required by hba */
2397 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2398 IS_QLA83XX(ha) || IS_QLA27XX(ha))
2399 pdev->needs_freset = 1;
2400
2401 ha->prev_topology = 0;
2402 ha->init_cb_size = sizeof(init_cb_t);
2403 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2404 ha->optrom_size = OPTROM_SIZE_2300;
2405
2406 /* Assign ISP specific operations. */
2407 if (IS_QLA2100(ha)) {
2408 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2409 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2410 req_length = REQUEST_ENTRY_CNT_2100;
2411 rsp_length = RESPONSE_ENTRY_CNT_2100;
2412 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2413 ha->gid_list_info_size = 4;
2414 ha->flash_conf_off = ~0;
2415 ha->flash_data_off = ~0;
2416 ha->nvram_conf_off = ~0;
2417 ha->nvram_data_off = ~0;
2418 ha->isp_ops = &qla2100_isp_ops;
2419 } else if (IS_QLA2200(ha)) {
2420 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2421 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2422 req_length = REQUEST_ENTRY_CNT_2200;
2423 rsp_length = RESPONSE_ENTRY_CNT_2100;
2424 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2425 ha->gid_list_info_size = 4;
2426 ha->flash_conf_off = ~0;
2427 ha->flash_data_off = ~0;
2428 ha->nvram_conf_off = ~0;
2429 ha->nvram_data_off = ~0;
2430 ha->isp_ops = &qla2100_isp_ops;
2431 } else if (IS_QLA23XX(ha)) {
2432 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2433 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2434 req_length = REQUEST_ENTRY_CNT_2200;
2435 rsp_length = RESPONSE_ENTRY_CNT_2300;
2436 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2437 ha->gid_list_info_size = 6;
2438 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2439 ha->optrom_size = OPTROM_SIZE_2322;
2440 ha->flash_conf_off = ~0;
2441 ha->flash_data_off = ~0;
2442 ha->nvram_conf_off = ~0;
2443 ha->nvram_data_off = ~0;
2444 ha->isp_ops = &qla2300_isp_ops;
2445 } else if (IS_QLA24XX_TYPE(ha)) {
2446 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2447 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2448 req_length = REQUEST_ENTRY_CNT_24XX;
2449 rsp_length = RESPONSE_ENTRY_CNT_2300;
2450 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2451 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2452 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2453 ha->gid_list_info_size = 8;
2454 ha->optrom_size = OPTROM_SIZE_24XX;
2455 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2456 ha->isp_ops = &qla24xx_isp_ops;
2457 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2458 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2459 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2460 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2461 } else if (IS_QLA25XX(ha)) {
2462 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2463 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2464 req_length = REQUEST_ENTRY_CNT_24XX;
2465 rsp_length = RESPONSE_ENTRY_CNT_2300;
2466 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2467 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2468 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2469 ha->gid_list_info_size = 8;
2470 ha->optrom_size = OPTROM_SIZE_25XX;
2471 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2472 ha->isp_ops = &qla25xx_isp_ops;
2473 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2474 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2475 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2476 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2477 } else if (IS_QLA81XX(ha)) {
2478 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2479 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2480 req_length = REQUEST_ENTRY_CNT_24XX;
2481 rsp_length = RESPONSE_ENTRY_CNT_2300;
2482 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2483 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2484 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2485 ha->gid_list_info_size = 8;
2486 ha->optrom_size = OPTROM_SIZE_81XX;
2487 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2488 ha->isp_ops = &qla81xx_isp_ops;
2489 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2490 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2491 ha->nvram_conf_off = ~0;
2492 ha->nvram_data_off = ~0;
2493 } else if (IS_QLA82XX(ha)) {
2494 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2495 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2496 req_length = REQUEST_ENTRY_CNT_82XX;
2497 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2498 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2499 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2500 ha->gid_list_info_size = 8;
2501 ha->optrom_size = OPTROM_SIZE_82XX;
2502 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2503 ha->isp_ops = &qla82xx_isp_ops;
2504 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2505 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2506 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2507 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2508 } else if (IS_QLA8044(ha)) {
2509 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2510 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2511 req_length = REQUEST_ENTRY_CNT_82XX;
2512 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2513 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2514 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2515 ha->gid_list_info_size = 8;
2516 ha->optrom_size = OPTROM_SIZE_83XX;
2517 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2518 ha->isp_ops = &qla8044_isp_ops;
2519 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2520 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2521 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2522 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2523 } else if (IS_QLA83XX(ha)) {
2524 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2525 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2526 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2527 req_length = REQUEST_ENTRY_CNT_24XX;
2528 rsp_length = RESPONSE_ENTRY_CNT_2300;
2529 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2530 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2531 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2532 ha->gid_list_info_size = 8;
2533 ha->optrom_size = OPTROM_SIZE_83XX;
2534 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2535 ha->isp_ops = &qla83xx_isp_ops;
2536 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2537 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2538 ha->nvram_conf_off = ~0;
2539 ha->nvram_data_off = ~0;
2540 } else if (IS_QLAFX00(ha)) {
2541 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2542 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2543 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2544 req_length = REQUEST_ENTRY_CNT_FX00;
2545 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2546 ha->isp_ops = &qlafx00_isp_ops;
2547 ha->port_down_retry_count = 30; /* default value */
2548 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2549 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
2550 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
2551 ha->mr.fw_hbt_en = 1;
2552 ha->mr.host_info_resend = false;
2553 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
2554 } else if (IS_QLA27XX(ha)) {
2555 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2556 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2557 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2558 req_length = REQUEST_ENTRY_CNT_24XX;
2559 rsp_length = RESPONSE_ENTRY_CNT_2300;
2560 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2561 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2562 ha->gid_list_info_size = 8;
2563 ha->optrom_size = OPTROM_SIZE_83XX;
2564 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2565 ha->isp_ops = &qla27xx_isp_ops;
2566 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2567 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2568 ha->nvram_conf_off = ~0;
2569 ha->nvram_data_off = ~0;
2570 }
2571
2572 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2573 "mbx_count=%d, req_length=%d, "
2574 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2575 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2576 "max_fibre_devices=%d.\n",
2577 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2578 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2579 ha->nvram_npiv_size, ha->max_fibre_devices);
2580 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2581 "isp_ops=%p, flash_conf_off=%d, "
2582 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2583 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2584 ha->nvram_conf_off, ha->nvram_data_off);
2585
2586 /* Configure PCI I/O space */
2587 ret = ha->isp_ops->iospace_config(ha);
2588 if (ret)
2589 goto iospace_config_failed;
2590
2591 ql_log_pci(ql_log_info, pdev, 0x001d,
2592 "Found an ISP%04X irq %d iobase 0x%p.\n",
2593 pdev->device, pdev->irq, ha->iobase);
2594 mutex_init(&ha->vport_lock);
2595 init_completion(&ha->mbx_cmd_comp);
2596 complete(&ha->mbx_cmd_comp);
2597 init_completion(&ha->mbx_intr_comp);
2598 init_completion(&ha->dcbx_comp);
2599 init_completion(&ha->lb_portup_comp);
2600
2601 set_bit(0, (unsigned long *) ha->vp_idx_map);
2602
2603 qla2x00_config_dma_addressing(ha);
2604 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2605 "64 Bit addressing is %s.\n",
2606 ha->flags.enable_64bit_addressing ? "enable" :
2607 "disable");
2608 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
2609 if (ret) {
2610 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2611 "Failed to allocate memory for adapter, aborting.\n");
2612
2613 goto probe_hw_failed;
2614 }
2615
2616 req->max_q_depth = MAX_Q_DEPTH;
2617 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
2618 req->max_q_depth = ql2xmaxqdepth;
2619
2620
2621 base_vha = qla2x00_create_host(sht, ha);
2622 if (!base_vha) {
2623 ret = -ENOMEM;
2624 qla2x00_mem_free(ha);
2625 qla2x00_free_req_que(ha, req);
2626 qla2x00_free_rsp_que(ha, rsp);
2627 goto probe_hw_failed;
2628 }
2629
2630 pci_set_drvdata(pdev, base_vha);
2631
2632 host = base_vha->host;
2633 base_vha->req = req;
2634 if (IS_QLA2XXX_MIDTYPE(ha))
2635 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
2636 else
2637 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2638 base_vha->vp_idx;
2639
2640 /* Setup fcport template structure. */
2641 ha->mr.fcport.vha = base_vha;
2642 ha->mr.fcport.port_type = FCT_UNKNOWN;
2643 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2644 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2645 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2646 ha->mr.fcport.scan_state = 1;
2647
2648 /* Set the SG table size based on ISP type */
2649 if (!IS_FWI2_CAPABLE(ha)) {
2650 if (IS_QLA2100(ha))
2651 host->sg_tablesize = 32;
2652 } else {
2653 if (!IS_QLA82XX(ha))
2654 host->sg_tablesize = QLA_SG_ALL;
2655 }
2656 host->max_id = ha->max_fibre_devices;
2657 host->cmd_per_lun = 3;
2658 host->unique_id = host->host_no;
2659 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
2660 host->max_cmd_len = 32;
2661 else
2662 host->max_cmd_len = MAX_CMDSZ;
2663 host->max_channel = MAX_BUSES - 1;
2664 /* Older HBAs support only 16-bit LUNs */
2665 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2666 ql2xmaxlun > 0xffff)
2667 host->max_lun = 0xffff;
2668 else
2669 host->max_lun = ql2xmaxlun;
2670 host->transportt = qla2xxx_transport_template;
2671 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
2672
2673 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2674 "max_id=%d this_id=%d "
2675 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2676 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
2677 host->this_id, host->cmd_per_lun, host->unique_id,
2678 host->max_cmd_len, host->max_channel, host->max_lun,
2679 host->transportt, sht->vendor_id);
2680
2681 que_init:
2682 /* Alloc arrays of request and response ring ptrs */
2683 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2684 ql_log(ql_log_fatal, base_vha, 0x003d,
2685 "Failed to allocate memory for queue pointers..."
2686 "aborting.\n");
2687 goto probe_init_failed;
2688 }
2689
2690 qlt_probe_one_stage1(base_vha, ha);
2691
2692 /* Set up the irqs */
2693 ret = qla2x00_request_irqs(ha, rsp);
2694 if (ret)
2695 goto probe_init_failed;
2696
2697 pci_save_state(pdev);
2698
2699 /* Assign back pointers */
2700 rsp->req = req;
2701 req->rsp = rsp;
2702
2703 if (IS_QLAFX00(ha)) {
2704 ha->rsp_q_map[0] = rsp;
2705 ha->req_q_map[0] = req;
2706 set_bit(0, ha->req_qid_map);
2707 set_bit(0, ha->rsp_qid_map);
2708 }
2709
2710 /* FWI2-capable only. */
2711 req->req_q_in = &ha->iobase->isp24.req_q_in;
2712 req->req_q_out = &ha->iobase->isp24.req_q_out;
2713 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2714 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
2715 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
2716 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2717 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2718 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2719 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
2720 }
2721
2722 if (IS_QLAFX00(ha)) {
2723 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2724 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2725 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2726 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2727 }
2728
2729 if (IS_P3P_TYPE(ha)) {
2730 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2731 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2732 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2733 }
2734
2735 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2736 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2737 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2738 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2739 "req->req_q_in=%p req->req_q_out=%p "
2740 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2741 req->req_q_in, req->req_q_out,
2742 rsp->rsp_q_in, rsp->rsp_q_out);
2743 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2744 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2745 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2746 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2747 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2748 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
2749
2750 if (ha->isp_ops->initialize_adapter(base_vha)) {
2751 ql_log(ql_log_fatal, base_vha, 0x00d6,
2752 "Failed to initialize adapter - Adapter flags %x.\n",
2753 base_vha->device_flags);
2754
2755 if (IS_QLA82XX(ha)) {
2756 qla82xx_idc_lock(ha);
2757 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2758 QLA8XXX_DEV_FAILED);
2759 qla82xx_idc_unlock(ha);
2760 ql_log(ql_log_fatal, base_vha, 0x00d7,
2761 "HW State: FAILED.\n");
2762 } else if (IS_QLA8044(ha)) {
2763 qla8044_idc_lock(ha);
2764 qla8044_wr_direct(base_vha,
2765 QLA8044_CRB_DEV_STATE_INDEX,
2766 QLA8XXX_DEV_FAILED);
2767 qla8044_idc_unlock(ha);
2768 ql_log(ql_log_fatal, base_vha, 0x0150,
2769 "HW State: FAILED.\n");
2770 }
2771
2772 ret = -ENODEV;
2773 goto probe_failed;
2774 }
2775
2776 if (IS_QLAFX00(ha))
2777 host->can_queue = QLAFX00_MAX_CANQUEUE;
2778 else
2779 host->can_queue = req->num_outstanding_cmds - 10;
2780
2781 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2782 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2783 host->can_queue, base_vha->req,
2784 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2785
2786 if (ha->mqenable) {
2787 if (qla25xx_setup_mode(base_vha)) {
2788 ql_log(ql_log_warn, base_vha, 0x00ec,
2789 "Failed to create queues, falling back to single queue mode.\n");
2790 goto que_init;
2791 }
2792 }
2793
2794 if (ha->flags.running_gold_fw)
2795 goto skip_dpc;
2796
2797 /*
2798 * Startup the kernel thread for this host adapter
2799 */
2800 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
2801 "%s_dpc", base_vha->host_str);
2802 if (IS_ERR(ha->dpc_thread)) {
2803 ql_log(ql_log_fatal, base_vha, 0x00ed,
2804 "Failed to start DPC thread.\n");
2805 ret = PTR_ERR(ha->dpc_thread);
2806 goto probe_failed;
2807 }
2808 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2809 "DPC thread started successfully.\n");
2810
2811 /*
2812 * If we're not coming up in initiator mode, we might sit for
2813 * a while without waking up the dpc thread, which leads to a
2814 * stuck process warning. So just kick the dpc once here and
2815 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2816 */
2817 qla2xxx_wake_dpc(base_vha);
2818
2819 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2820
2821 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2822 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2823 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2824 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2825
2826 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2827 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2828 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2829 INIT_WORK(&ha->idc_state_handler,
2830 qla83xx_idc_state_handler_work);
2831 INIT_WORK(&ha->nic_core_unrecoverable,
2832 qla83xx_nic_core_unrecoverable_work);
2833 }
2834
2835 skip_dpc:
2836 list_add_tail(&base_vha->list, &ha->vp_list);
2837 base_vha->host->irq = ha->pdev->irq;
2838
2839 /* Initialized the timer */
2840 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
2841 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2842 "Started qla2x00_timer with "
2843 "interval=%d.\n", WATCH_INTERVAL);
2844 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2845 "Detected hba at address=%p.\n",
2846 ha);
2847
2848 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
2849 if (ha->fw_attributes & BIT_4) {
2850 int prot = 0, guard;
2851 base_vha->flags.difdix_supported = 1;
2852 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2853 "Registering for DIF/DIX type 1 and 3 protection.\n");
2854 if (ql2xenabledif == 1)
2855 prot = SHOST_DIX_TYPE0_PROTECTION;
2856 scsi_host_set_prot(host,
2857 prot | SHOST_DIF_TYPE1_PROTECTION
2858 | SHOST_DIF_TYPE2_PROTECTION
2859 | SHOST_DIF_TYPE3_PROTECTION
2860 | SHOST_DIX_TYPE1_PROTECTION
2861 | SHOST_DIX_TYPE2_PROTECTION
2862 | SHOST_DIX_TYPE3_PROTECTION);
2863
2864 guard = SHOST_DIX_GUARD_CRC;
2865
2866 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2867 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2868 guard |= SHOST_DIX_GUARD_IP;
2869
2870 scsi_host_set_guard(host, guard);
2871 } else
2872 base_vha->flags.difdix_supported = 0;
2873 }
2874
2875 ha->isp_ops->enable_intrs(ha);
2876
2877 if (IS_QLAFX00(ha)) {
2878 ret = qlafx00_fx_disc(base_vha,
2879 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2880 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2881 QLA_SG_ALL : 128;
2882 }
2883
2884 ret = scsi_add_host(host, &pdev->dev);
2885 if (ret)
2886 goto probe_failed;
2887
2888 base_vha->flags.init_done = 1;
2889 base_vha->flags.online = 1;
2890 ha->prev_minidump_failed = 0;
2891
2892 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2893 "Init done and hba is online.\n");
2894
2895 if (qla_ini_mode_enabled(base_vha))
2896 scsi_scan_host(host);
2897 else
2898 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2899 "skipping scsi_scan_host() for non-initiator port\n");
2900
2901 qla2x00_alloc_sysfs_attr(base_vha);
2902
2903 if (IS_QLAFX00(ha)) {
2904 ret = qlafx00_fx_disc(base_vha,
2905 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2906
2907 /* Register system information */
2908 ret = qlafx00_fx_disc(base_vha,
2909 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2910 }
2911
2912 qla2x00_init_host_attr(base_vha);
2913
2914 qla2x00_dfs_setup(base_vha);
2915
2916 ql_log(ql_log_info, base_vha, 0x00fb,
2917 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
2918 ql_log(ql_log_info, base_vha, 0x00fc,
2919 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2920 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2921 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2922 base_vha->host_no,
2923 ha->isp_ops->fw_version_str(base_vha, fw_str));
2924
2925 qlt_add_target(ha, base_vha);
2926
2927 return 0;
2928
2929 probe_init_failed:
2930 qla2x00_free_req_que(ha, req);
2931 ha->req_q_map[0] = NULL;
2932 clear_bit(0, ha->req_qid_map);
2933 qla2x00_free_rsp_que(ha, rsp);
2934 ha->rsp_q_map[0] = NULL;
2935 clear_bit(0, ha->rsp_qid_map);
2936 ha->max_req_queues = ha->max_rsp_queues = 0;
2937
2938 probe_failed:
2939 if (base_vha->timer_active)
2940 qla2x00_stop_timer(base_vha);
2941 base_vha->flags.online = 0;
2942 if (ha->dpc_thread) {
2943 struct task_struct *t = ha->dpc_thread;
2944
2945 ha->dpc_thread = NULL;
2946 kthread_stop(t);
2947 }
2948
2949 qla2x00_free_device(base_vha);
2950
2951 scsi_host_put(base_vha->host);
2952
2953 probe_hw_failed:
2954 if (IS_QLA82XX(ha)) {
2955 qla82xx_idc_lock(ha);
2956 qla82xx_clear_drv_active(ha);
2957 qla82xx_idc_unlock(ha);
2958 }
2959 if (IS_QLA8044(ha)) {
2960 qla8044_idc_lock(ha);
2961 qla8044_clear_drv_active(ha);
2962 qla8044_idc_unlock(ha);
2963 }
2964 iospace_config_failed:
2965 if (IS_P3P_TYPE(ha)) {
2966 if (!ha->nx_pcibase)
2967 iounmap((device_reg_t *)ha->nx_pcibase);
2968 if (!ql2xdbwr)
2969 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
2970 } else {
2971 if (ha->iobase)
2972 iounmap(ha->iobase);
2973 if (ha->cregbase)
2974 iounmap(ha->cregbase);
2975 }
2976 pci_release_selected_regions(ha->pdev, ha->bars);
2977 kfree(ha);
2978 ha = NULL;
2979
2980 probe_out:
2981 pci_disable_device(pdev);
2982 return ret;
2983 }
2984
2985 static void
2986 qla2x00_shutdown(struct pci_dev *pdev)
2987 {
2988 scsi_qla_host_t *vha;
2989 struct qla_hw_data *ha;
2990
2991 if (!atomic_read(&pdev->enable_cnt))
2992 return;
2993
2994 vha = pci_get_drvdata(pdev);
2995 ha = vha->hw;
2996
2997 /* Notify ISPFX00 firmware */
2998 if (IS_QLAFX00(ha))
2999 qlafx00_driver_shutdown(vha, 20);
3000
3001 /* Turn-off FCE trace */
3002 if (ha->flags.fce_enabled) {
3003 qla2x00_disable_fce_trace(vha, NULL, NULL);
3004 ha->flags.fce_enabled = 0;
3005 }
3006
3007 /* Turn-off EFT trace */
3008 if (ha->eft)
3009 qla2x00_disable_eft_trace(vha);
3010
3011 /* Stop currently executing firmware. */
3012 qla2x00_try_to_stop_firmware(vha);
3013
3014 /* Turn adapter off line */
3015 vha->flags.online = 0;
3016
3017 /* turn-off interrupts on the card */
3018 if (ha->interrupts_on) {
3019 vha->flags.init_done = 0;
3020 ha->isp_ops->disable_intrs(ha);
3021 }
3022
3023 qla2x00_free_irqs(vha);
3024
3025 qla2x00_free_fw_dump(ha);
3026 }
3027
3028 /* Deletes all the virtual ports for a given ha */
3029 static void
3030 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3031 {
3032 struct Scsi_Host *scsi_host;
3033 scsi_qla_host_t *vha;
3034 unsigned long flags;
3035
3036 mutex_lock(&ha->vport_lock);
3037 while (ha->cur_vport_count) {
3038 spin_lock_irqsave(&ha->vport_slock, flags);
3039
3040 BUG_ON(base_vha->list.next == &ha->vp_list);
3041 /* This assumes first entry in ha->vp_list is always base vha */
3042 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3043 scsi_host = scsi_host_get(vha->host);
3044
3045 spin_unlock_irqrestore(&ha->vport_slock, flags);
3046 mutex_unlock(&ha->vport_lock);
3047
3048 fc_vport_terminate(vha->fc_vport);
3049 scsi_host_put(vha->host);
3050
3051 mutex_lock(&ha->vport_lock);
3052 }
3053 mutex_unlock(&ha->vport_lock);
3054 }
3055
3056 /* Stops all deferred work threads */
3057 static void
3058 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3059 {
3060 /* Flush the work queue and remove it */
3061 if (ha->wq) {
3062 flush_workqueue(ha->wq);
3063 destroy_workqueue(ha->wq);
3064 ha->wq = NULL;
3065 }
3066
3067 /* Cancel all work and destroy DPC workqueues */
3068 if (ha->dpc_lp_wq) {
3069 cancel_work_sync(&ha->idc_aen);
3070 destroy_workqueue(ha->dpc_lp_wq);
3071 ha->dpc_lp_wq = NULL;
3072 }
3073
3074 if (ha->dpc_hp_wq) {
3075 cancel_work_sync(&ha->nic_core_reset);
3076 cancel_work_sync(&ha->idc_state_handler);
3077 cancel_work_sync(&ha->nic_core_unrecoverable);
3078 destroy_workqueue(ha->dpc_hp_wq);
3079 ha->dpc_hp_wq = NULL;
3080 }
3081
3082 /* Kill the kernel thread for this host */
3083 if (ha->dpc_thread) {
3084 struct task_struct *t = ha->dpc_thread;
3085
3086 /*
3087 * qla2xxx_wake_dpc checks for ->dpc_thread
3088 * so we need to zero it out.
3089 */
3090 ha->dpc_thread = NULL;
3091 kthread_stop(t);
3092 }
3093 }
3094
3095 static void
3096 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3097 {
3098 if (IS_QLA82XX(ha)) {
3099
3100 iounmap((device_reg_t *)ha->nx_pcibase);
3101 if (!ql2xdbwr)
3102 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3103 } else {
3104 if (ha->iobase)
3105 iounmap(ha->iobase);
3106
3107 if (ha->cregbase)
3108 iounmap(ha->cregbase);
3109
3110 if (ha->mqiobase)
3111 iounmap(ha->mqiobase);
3112
3113 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
3114 iounmap(ha->msixbase);
3115 }
3116 }
3117
3118 static void
3119 qla2x00_clear_drv_active(scsi_qla_host_t *vha)
3120 {
3121 struct qla_hw_data *ha = vha->hw;
3122
3123 if (IS_QLA8044(ha)) {
3124 qla8044_idc_lock(ha);
3125 qla8044_clear_drv_active(ha);
3126 qla8044_idc_unlock(ha);
3127 } else if (IS_QLA82XX(ha)) {
3128 qla82xx_idc_lock(ha);
3129 qla82xx_clear_drv_active(ha);
3130 qla82xx_idc_unlock(ha);
3131 }
3132 }
3133
3134 static void
3135 qla2x00_remove_one(struct pci_dev *pdev)
3136 {
3137 scsi_qla_host_t *base_vha;
3138 struct qla_hw_data *ha;
3139
3140 /*
3141 * If the PCI device is disabled that means that probe failed and any
3142 * resources should be have cleaned up on probe exit.
3143 */
3144 if (!atomic_read(&pdev->enable_cnt))
3145 return;
3146
3147 base_vha = pci_get_drvdata(pdev);
3148 ha = base_vha->hw;
3149
3150 qla2x00_wait_for_hba_ready(base_vha);
3151
3152 set_bit(UNLOADING, &base_vha->dpc_flags);
3153
3154 if (IS_QLAFX00(ha))
3155 qlafx00_driver_shutdown(base_vha, 20);
3156
3157 qla2x00_delete_all_vps(ha, base_vha);
3158
3159 if (IS_QLA8031(ha)) {
3160 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3161 "Clearing fcoe driver presence.\n");
3162 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3163 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3164 "Error while clearing DRV-Presence.\n");
3165 }
3166
3167 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3168
3169 qla2x00_dfs_remove(base_vha);
3170
3171 qla84xx_put_chip(base_vha);
3172
3173 /* Disable timer */
3174 if (base_vha->timer_active)
3175 qla2x00_stop_timer(base_vha);
3176
3177 base_vha->flags.online = 0;
3178
3179 qla2x00_destroy_deferred_work(ha);
3180
3181 qlt_remove_target(ha, base_vha);
3182
3183 qla2x00_free_sysfs_attr(base_vha, true);
3184
3185 fc_remove_host(base_vha->host);
3186
3187 scsi_remove_host(base_vha->host);
3188
3189 qla2x00_free_device(base_vha);
3190
3191 scsi_host_put(base_vha->host);
3192
3193 qla2x00_clear_drv_active(base_vha);
3194
3195 qla2x00_unmap_iobases(ha);
3196
3197 pci_release_selected_regions(ha->pdev, ha->bars);
3198 kfree(ha);
3199 ha = NULL;
3200
3201 pci_disable_pcie_error_reporting(pdev);
3202
3203 pci_disable_device(pdev);
3204 }
3205
3206 static void
3207 qla2x00_free_device(scsi_qla_host_t *vha)
3208 {
3209 struct qla_hw_data *ha = vha->hw;
3210
3211 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3212
3213 /* Disable timer */
3214 if (vha->timer_active)
3215 qla2x00_stop_timer(vha);
3216
3217 qla25xx_delete_queues(vha);
3218
3219 if (ha->flags.fce_enabled)
3220 qla2x00_disable_fce_trace(vha, NULL, NULL);
3221
3222 if (ha->eft)
3223 qla2x00_disable_eft_trace(vha);
3224
3225 /* Stop currently executing firmware. */
3226 qla2x00_try_to_stop_firmware(vha);
3227
3228 vha->flags.online = 0;
3229
3230 /* turn-off interrupts on the card */
3231 if (ha->interrupts_on) {
3232 vha->flags.init_done = 0;
3233 ha->isp_ops->disable_intrs(ha);
3234 }
3235
3236 qla2x00_free_irqs(vha);
3237
3238 qla2x00_free_fcports(vha);
3239
3240 qla2x00_mem_free(ha);
3241
3242 qla82xx_md_free(vha);
3243
3244 qla2x00_free_queues(ha);
3245 }
3246
3247 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3248 {
3249 fc_port_t *fcport, *tfcport;
3250
3251 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3252 list_del(&fcport->list);
3253 qla2x00_clear_loop_id(fcport);
3254 kfree(fcport);
3255 fcport = NULL;
3256 }
3257 }
3258
3259 static inline void
3260 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
3261 int defer)
3262 {
3263 struct fc_rport *rport;
3264 scsi_qla_host_t *base_vha;
3265 unsigned long flags;
3266
3267 if (!fcport->rport)
3268 return;
3269
3270 rport = fcport->rport;
3271 if (defer) {
3272 base_vha = pci_get_drvdata(vha->hw->pdev);
3273 spin_lock_irqsave(vha->host->host_lock, flags);
3274 fcport->drport = rport;
3275 spin_unlock_irqrestore(vha->host->host_lock, flags);
3276 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3277 qla2xxx_wake_dpc(base_vha);
3278 } else {
3279 fc_remote_port_delete(rport);
3280 qlt_fc_port_deleted(vha, fcport);
3281 }
3282 }
3283
3284 /*
3285 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3286 *
3287 * Input: ha = adapter block pointer. fcport = port structure pointer.
3288 *
3289 * Return: None.
3290 *
3291 * Context:
3292 */
3293 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3294 int do_login, int defer)
3295 {
3296 if (IS_QLAFX00(vha->hw)) {
3297 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3298 qla2x00_schedule_rport_del(vha, fcport, defer);
3299 return;
3300 }
3301
3302 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3303 vha->vp_idx == fcport->vha->vp_idx) {
3304 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3305 qla2x00_schedule_rport_del(vha, fcport, defer);
3306 }
3307 /*
3308 * We may need to retry the login, so don't change the state of the
3309 * port but do the retries.
3310 */
3311 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3312 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3313
3314 if (!do_login)
3315 return;
3316
3317 if (fcport->login_retry == 0) {
3318 fcport->login_retry = vha->hw->login_retry_count;
3319 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3320
3321 ql_dbg(ql_dbg_disc, vha, 0x2067,
3322 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3323 fcport->port_name, fcport->loop_id, fcport->login_retry);
3324 }
3325 }
3326
3327 /*
3328 * qla2x00_mark_all_devices_lost
3329 * Updates fcport state when device goes offline.
3330 *
3331 * Input:
3332 * ha = adapter block pointer.
3333 * fcport = port structure pointer.
3334 *
3335 * Return:
3336 * None.
3337 *
3338 * Context:
3339 */
3340 void
3341 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
3342 {
3343 fc_port_t *fcport;
3344
3345 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3346 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
3347 continue;
3348
3349 /*
3350 * No point in marking the device as lost, if the device is
3351 * already DEAD.
3352 */
3353 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3354 continue;
3355 if (atomic_read(&fcport->state) == FCS_ONLINE) {
3356 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3357 if (defer)
3358 qla2x00_schedule_rport_del(vha, fcport, defer);
3359 else if (vha->vp_idx == fcport->vha->vp_idx)
3360 qla2x00_schedule_rport_del(vha, fcport, defer);
3361 }
3362 }
3363 }
3364
3365 /*
3366 * qla2x00_mem_alloc
3367 * Allocates adapter memory.
3368 *
3369 * Returns:
3370 * 0 = success.
3371 * !0 = failure.
3372 */
3373 static int
3374 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3375 struct req_que **req, struct rsp_que **rsp)
3376 {
3377 char name[16];
3378
3379 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3380 &ha->init_cb_dma, GFP_KERNEL);
3381 if (!ha->init_cb)
3382 goto fail;
3383
3384 if (qlt_mem_alloc(ha) < 0)
3385 goto fail_free_init_cb;
3386
3387 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3388 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3389 if (!ha->gid_list)
3390 goto fail_free_tgt_mem;
3391
3392 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3393 if (!ha->srb_mempool)
3394 goto fail_free_gid_list;
3395
3396 if (IS_P3P_TYPE(ha)) {
3397 /* Allocate cache for CT6 Ctx. */
3398 if (!ctx_cachep) {
3399 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3400 sizeof(struct ct6_dsd), 0,
3401 SLAB_HWCACHE_ALIGN, NULL);
3402 if (!ctx_cachep)
3403 goto fail_free_gid_list;
3404 }
3405 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3406 ctx_cachep);
3407 if (!ha->ctx_mempool)
3408 goto fail_free_srb_mempool;
3409 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3410 "ctx_cachep=%p ctx_mempool=%p.\n",
3411 ctx_cachep, ha->ctx_mempool);
3412 }
3413
3414 /* Get memory for cached NVRAM */
3415 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3416 if (!ha->nvram)
3417 goto fail_free_ctx_mempool;
3418
3419 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3420 ha->pdev->device);
3421 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3422 DMA_POOL_SIZE, 8, 0);
3423 if (!ha->s_dma_pool)
3424 goto fail_free_nvram;
3425
3426 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3427 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3428 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3429
3430 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
3431 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3432 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3433 if (!ha->dl_dma_pool) {
3434 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3435 "Failed to allocate memory for dl_dma_pool.\n");
3436 goto fail_s_dma_pool;
3437 }
3438
3439 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3440 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3441 if (!ha->fcp_cmnd_dma_pool) {
3442 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3443 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
3444 goto fail_dl_dma_pool;
3445 }
3446 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3447 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3448 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
3449 }
3450
3451 /* Allocate memory for SNS commands */
3452 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3453 /* Get consistent memory allocated for SNS commands */
3454 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
3455 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
3456 if (!ha->sns_cmd)
3457 goto fail_dma_pool;
3458 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
3459 "sns_cmd: %p.\n", ha->sns_cmd);
3460 } else {
3461 /* Get consistent memory allocated for MS IOCB */
3462 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3463 &ha->ms_iocb_dma);
3464 if (!ha->ms_iocb)
3465 goto fail_dma_pool;
3466 /* Get consistent memory allocated for CT SNS commands */
3467 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
3468 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
3469 if (!ha->ct_sns)
3470 goto fail_free_ms_iocb;
3471 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3472 "ms_iocb=%p ct_sns=%p.\n",
3473 ha->ms_iocb, ha->ct_sns);
3474 }
3475
3476 /* Allocate memory for request ring */
3477 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3478 if (!*req) {
3479 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3480 "Failed to allocate memory for req.\n");
3481 goto fail_req;
3482 }
3483 (*req)->length = req_len;
3484 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3485 ((*req)->length + 1) * sizeof(request_t),
3486 &(*req)->dma, GFP_KERNEL);
3487 if (!(*req)->ring) {
3488 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3489 "Failed to allocate memory for req_ring.\n");
3490 goto fail_req_ring;
3491 }
3492 /* Allocate memory for response ring */
3493 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3494 if (!*rsp) {
3495 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3496 "Failed to allocate memory for rsp.\n");
3497 goto fail_rsp;
3498 }
3499 (*rsp)->hw = ha;
3500 (*rsp)->length = rsp_len;
3501 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3502 ((*rsp)->length + 1) * sizeof(response_t),
3503 &(*rsp)->dma, GFP_KERNEL);
3504 if (!(*rsp)->ring) {
3505 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3506 "Failed to allocate memory for rsp_ring.\n");
3507 goto fail_rsp_ring;
3508 }
3509 (*req)->rsp = *rsp;
3510 (*rsp)->req = *req;
3511 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3512 "req=%p req->length=%d req->ring=%p rsp=%p "
3513 "rsp->length=%d rsp->ring=%p.\n",
3514 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3515 (*rsp)->ring);
3516 /* Allocate memory for NVRAM data for vports */
3517 if (ha->nvram_npiv_size) {
3518 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
3519 ha->nvram_npiv_size, GFP_KERNEL);
3520 if (!ha->npiv_info) {
3521 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3522 "Failed to allocate memory for npiv_info.\n");
3523 goto fail_npiv_info;
3524 }
3525 } else
3526 ha->npiv_info = NULL;
3527
3528 /* Get consistent memory allocated for EX-INIT-CB. */
3529 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3530 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3531 &ha->ex_init_cb_dma);
3532 if (!ha->ex_init_cb)
3533 goto fail_ex_init_cb;
3534 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3535 "ex_init_cb=%p.\n", ha->ex_init_cb);
3536 }
3537
3538 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3539
3540 /* Get consistent memory allocated for Async Port-Database. */
3541 if (!IS_FWI2_CAPABLE(ha)) {
3542 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3543 &ha->async_pd_dma);
3544 if (!ha->async_pd)
3545 goto fail_async_pd;
3546 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3547 "async_pd=%p.\n", ha->async_pd);
3548 }
3549
3550 INIT_LIST_HEAD(&ha->vp_list);
3551
3552 /* Allocate memory for our loop_id bitmap */
3553 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3554 GFP_KERNEL);
3555 if (!ha->loop_id_map)
3556 goto fail_async_pd;
3557 else {
3558 qla2x00_set_reserved_loop_ids(ha);
3559 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3560 "loop_id_map=%p.\n", ha->loop_id_map);
3561 }
3562
3563 return 0;
3564
3565 fail_async_pd:
3566 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
3567 fail_ex_init_cb:
3568 kfree(ha->npiv_info);
3569 fail_npiv_info:
3570 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3571 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3572 (*rsp)->ring = NULL;
3573 (*rsp)->dma = 0;
3574 fail_rsp_ring:
3575 kfree(*rsp);
3576 fail_rsp:
3577 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3578 sizeof(request_t), (*req)->ring, (*req)->dma);
3579 (*req)->ring = NULL;
3580 (*req)->dma = 0;
3581 fail_req_ring:
3582 kfree(*req);
3583 fail_req:
3584 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3585 ha->ct_sns, ha->ct_sns_dma);
3586 ha->ct_sns = NULL;
3587 ha->ct_sns_dma = 0;
3588 fail_free_ms_iocb:
3589 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3590 ha->ms_iocb = NULL;
3591 ha->ms_iocb_dma = 0;
3592 fail_dma_pool:
3593 if (IS_QLA82XX(ha) || ql2xenabledif) {
3594 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3595 ha->fcp_cmnd_dma_pool = NULL;
3596 }
3597 fail_dl_dma_pool:
3598 if (IS_QLA82XX(ha) || ql2xenabledif) {
3599 dma_pool_destroy(ha->dl_dma_pool);
3600 ha->dl_dma_pool = NULL;
3601 }
3602 fail_s_dma_pool:
3603 dma_pool_destroy(ha->s_dma_pool);
3604 ha->s_dma_pool = NULL;
3605 fail_free_nvram:
3606 kfree(ha->nvram);
3607 ha->nvram = NULL;
3608 fail_free_ctx_mempool:
3609 mempool_destroy(ha->ctx_mempool);
3610 ha->ctx_mempool = NULL;
3611 fail_free_srb_mempool:
3612 mempool_destroy(ha->srb_mempool);
3613 ha->srb_mempool = NULL;
3614 fail_free_gid_list:
3615 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3616 ha->gid_list,
3617 ha->gid_list_dma);
3618 ha->gid_list = NULL;
3619 ha->gid_list_dma = 0;
3620 fail_free_tgt_mem:
3621 qlt_mem_free(ha);
3622 fail_free_init_cb:
3623 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3624 ha->init_cb_dma);
3625 ha->init_cb = NULL;
3626 ha->init_cb_dma = 0;
3627 fail:
3628 ql_log(ql_log_fatal, NULL, 0x0030,
3629 "Memory allocation failure.\n");
3630 return -ENOMEM;
3631 }
3632
3633 /*
3634 * qla2x00_free_fw_dump
3635 * Frees fw dump stuff.
3636 *
3637 * Input:
3638 * ha = adapter block pointer
3639 */
3640 static void
3641 qla2x00_free_fw_dump(struct qla_hw_data *ha)
3642 {
3643 if (ha->fce)
3644 dma_free_coherent(&ha->pdev->dev,
3645 FCE_SIZE, ha->fce, ha->fce_dma);
3646
3647 if (ha->eft)
3648 dma_free_coherent(&ha->pdev->dev,
3649 EFT_SIZE, ha->eft, ha->eft_dma);
3650
3651 if (ha->fw_dump)
3652 vfree(ha->fw_dump);
3653 if (ha->fw_dump_template)
3654 vfree(ha->fw_dump_template);
3655
3656 ha->fce = NULL;
3657 ha->fce_dma = 0;
3658 ha->eft = NULL;
3659 ha->eft_dma = 0;
3660 ha->fw_dumped = 0;
3661 ha->fw_dump_cap_flags = 0;
3662 ha->fw_dump_reading = 0;
3663 ha->fw_dump = NULL;
3664 ha->fw_dump_len = 0;
3665 ha->fw_dump_template = NULL;
3666 ha->fw_dump_template_len = 0;
3667 }
3668
3669 /*
3670 * qla2x00_mem_free
3671 * Frees all adapter allocated memory.
3672 *
3673 * Input:
3674 * ha = adapter block pointer.
3675 */
3676 static void
3677 qla2x00_mem_free(struct qla_hw_data *ha)
3678 {
3679 qla2x00_free_fw_dump(ha);
3680
3681 if (ha->mctp_dump)
3682 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3683 ha->mctp_dump_dma);
3684
3685 if (ha->srb_mempool)
3686 mempool_destroy(ha->srb_mempool);
3687
3688 if (ha->dcbx_tlv)
3689 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3690 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3691
3692 if (ha->xgmac_data)
3693 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3694 ha->xgmac_data, ha->xgmac_data_dma);
3695
3696 if (ha->sns_cmd)
3697 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3698 ha->sns_cmd, ha->sns_cmd_dma);
3699
3700 if (ha->ct_sns)
3701 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3702 ha->ct_sns, ha->ct_sns_dma);
3703
3704 if (ha->sfp_data)
3705 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3706
3707 if (ha->ms_iocb)
3708 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3709
3710 if (ha->ex_init_cb)
3711 dma_pool_free(ha->s_dma_pool,
3712 ha->ex_init_cb, ha->ex_init_cb_dma);
3713
3714 if (ha->async_pd)
3715 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3716
3717 if (ha->s_dma_pool)
3718 dma_pool_destroy(ha->s_dma_pool);
3719
3720 if (ha->gid_list)
3721 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3722 ha->gid_list, ha->gid_list_dma);
3723
3724 if (IS_QLA82XX(ha)) {
3725 if (!list_empty(&ha->gbl_dsd_list)) {
3726 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3727
3728 /* clean up allocated prev pool */
3729 list_for_each_entry_safe(dsd_ptr,
3730 tdsd_ptr, &ha->gbl_dsd_list, list) {
3731 dma_pool_free(ha->dl_dma_pool,
3732 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3733 list_del(&dsd_ptr->list);
3734 kfree(dsd_ptr);
3735 }
3736 }
3737 }
3738
3739 if (ha->dl_dma_pool)
3740 dma_pool_destroy(ha->dl_dma_pool);
3741
3742 if (ha->fcp_cmnd_dma_pool)
3743 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3744
3745 if (ha->ctx_mempool)
3746 mempool_destroy(ha->ctx_mempool);
3747
3748 qlt_mem_free(ha);
3749
3750 if (ha->init_cb)
3751 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
3752 ha->init_cb, ha->init_cb_dma);
3753 vfree(ha->optrom_buffer);
3754 kfree(ha->nvram);
3755 kfree(ha->npiv_info);
3756 kfree(ha->swl);
3757 kfree(ha->loop_id_map);
3758
3759 ha->srb_mempool = NULL;
3760 ha->ctx_mempool = NULL;
3761 ha->sns_cmd = NULL;
3762 ha->sns_cmd_dma = 0;
3763 ha->ct_sns = NULL;
3764 ha->ct_sns_dma = 0;
3765 ha->ms_iocb = NULL;
3766 ha->ms_iocb_dma = 0;
3767 ha->init_cb = NULL;
3768 ha->init_cb_dma = 0;
3769 ha->ex_init_cb = NULL;
3770 ha->ex_init_cb_dma = 0;
3771 ha->async_pd = NULL;
3772 ha->async_pd_dma = 0;
3773
3774 ha->s_dma_pool = NULL;
3775 ha->dl_dma_pool = NULL;
3776 ha->fcp_cmnd_dma_pool = NULL;
3777
3778 ha->gid_list = NULL;
3779 ha->gid_list_dma = 0;
3780
3781 ha->tgt.atio_ring = NULL;
3782 ha->tgt.atio_dma = 0;
3783 ha->tgt.tgt_vp_map = NULL;
3784 }
3785
3786 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3787 struct qla_hw_data *ha)
3788 {
3789 struct Scsi_Host *host;
3790 struct scsi_qla_host *vha = NULL;
3791
3792 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3793 if (host == NULL) {
3794 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3795 "Failed to allocate host from the scsi layer, aborting.\n");
3796 goto fail;
3797 }
3798
3799 /* Clear our data area */
3800 vha = shost_priv(host);
3801 memset(vha, 0, sizeof(scsi_qla_host_t));
3802
3803 vha->host = host;
3804 vha->host_no = host->host_no;
3805 vha->hw = ha;
3806
3807 INIT_LIST_HEAD(&vha->vp_fcports);
3808 INIT_LIST_HEAD(&vha->work_list);
3809 INIT_LIST_HEAD(&vha->list);
3810
3811 spin_lock_init(&vha->work_lock);
3812
3813 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
3814 ql_dbg(ql_dbg_init, vha, 0x0041,
3815 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3816 vha->host, vha->hw, vha,
3817 dev_name(&(ha->pdev->dev)));
3818
3819 return vha;
3820
3821 fail:
3822 return vha;
3823 }
3824
3825 static struct qla_work_evt *
3826 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
3827 {
3828 struct qla_work_evt *e;
3829 uint8_t bail;
3830
3831 QLA_VHA_MARK_BUSY(vha, bail);
3832 if (bail)
3833 return NULL;
3834
3835 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
3836 if (!e) {
3837 QLA_VHA_MARK_NOT_BUSY(vha);
3838 return NULL;
3839 }
3840
3841 INIT_LIST_HEAD(&e->list);
3842 e->type = type;
3843 e->flags = QLA_EVT_FLAG_FREE;
3844 return e;
3845 }
3846
3847 static int
3848 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
3849 {
3850 unsigned long flags;
3851
3852 spin_lock_irqsave(&vha->work_lock, flags);
3853 list_add_tail(&e->list, &vha->work_list);
3854 spin_unlock_irqrestore(&vha->work_lock, flags);
3855 qla2xxx_wake_dpc(vha);
3856
3857 return QLA_SUCCESS;
3858 }
3859
3860 int
3861 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
3862 u32 data)
3863 {
3864 struct qla_work_evt *e;
3865
3866 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
3867 if (!e)
3868 return QLA_FUNCTION_FAILED;
3869
3870 e->u.aen.code = code;
3871 e->u.aen.data = data;
3872 return qla2x00_post_work(vha, e);
3873 }
3874
3875 int
3876 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3877 {
3878 struct qla_work_evt *e;
3879
3880 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
3881 if (!e)
3882 return QLA_FUNCTION_FAILED;
3883
3884 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3885 return qla2x00_post_work(vha, e);
3886 }
3887
3888 #define qla2x00_post_async_work(name, type) \
3889 int qla2x00_post_async_##name##_work( \
3890 struct scsi_qla_host *vha, \
3891 fc_port_t *fcport, uint16_t *data) \
3892 { \
3893 struct qla_work_evt *e; \
3894 \
3895 e = qla2x00_alloc_work(vha, type); \
3896 if (!e) \
3897 return QLA_FUNCTION_FAILED; \
3898 \
3899 e->u.logio.fcport = fcport; \
3900 if (data) { \
3901 e->u.logio.data[0] = data[0]; \
3902 e->u.logio.data[1] = data[1]; \
3903 } \
3904 return qla2x00_post_work(vha, e); \
3905 }
3906
3907 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3908 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3909 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3910 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
3911 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3912 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
3913
3914 int
3915 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3916 {
3917 struct qla_work_evt *e;
3918
3919 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3920 if (!e)
3921 return QLA_FUNCTION_FAILED;
3922
3923 e->u.uevent.code = code;
3924 return qla2x00_post_work(vha, e);
3925 }
3926
3927 static void
3928 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3929 {
3930 char event_string[40];
3931 char *envp[] = { event_string, NULL };
3932
3933 switch (code) {
3934 case QLA_UEVENT_CODE_FW_DUMP:
3935 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3936 vha->host_no);
3937 break;
3938 default:
3939 /* do nothing */
3940 break;
3941 }
3942 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3943 }
3944
3945 int
3946 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3947 uint32_t *data, int cnt)
3948 {
3949 struct qla_work_evt *e;
3950
3951 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3952 if (!e)
3953 return QLA_FUNCTION_FAILED;
3954
3955 e->u.aenfx.evtcode = evtcode;
3956 e->u.aenfx.count = cnt;
3957 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3958 return qla2x00_post_work(vha, e);
3959 }
3960
3961 void
3962 qla2x00_do_work(struct scsi_qla_host *vha)
3963 {
3964 struct qla_work_evt *e, *tmp;
3965 unsigned long flags;
3966 LIST_HEAD(work);
3967
3968 spin_lock_irqsave(&vha->work_lock, flags);
3969 list_splice_init(&vha->work_list, &work);
3970 spin_unlock_irqrestore(&vha->work_lock, flags);
3971
3972 list_for_each_entry_safe(e, tmp, &work, list) {
3973 list_del_init(&e->list);
3974
3975 switch (e->type) {
3976 case QLA_EVT_AEN:
3977 fc_host_post_event(vha->host, fc_get_event_number(),
3978 e->u.aen.code, e->u.aen.data);
3979 break;
3980 case QLA_EVT_IDC_ACK:
3981 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3982 break;
3983 case QLA_EVT_ASYNC_LOGIN:
3984 qla2x00_async_login(vha, e->u.logio.fcport,
3985 e->u.logio.data);
3986 break;
3987 case QLA_EVT_ASYNC_LOGIN_DONE:
3988 qla2x00_async_login_done(vha, e->u.logio.fcport,
3989 e->u.logio.data);
3990 break;
3991 case QLA_EVT_ASYNC_LOGOUT:
3992 qla2x00_async_logout(vha, e->u.logio.fcport);
3993 break;
3994 case QLA_EVT_ASYNC_LOGOUT_DONE:
3995 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3996 e->u.logio.data);
3997 break;
3998 case QLA_EVT_ASYNC_ADISC:
3999 qla2x00_async_adisc(vha, e->u.logio.fcport,
4000 e->u.logio.data);
4001 break;
4002 case QLA_EVT_ASYNC_ADISC_DONE:
4003 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4004 e->u.logio.data);
4005 break;
4006 case QLA_EVT_UEVENT:
4007 qla2x00_uevent_emit(vha, e->u.uevent.code);
4008 break;
4009 case QLA_EVT_AENFX:
4010 qlafx00_process_aen(vha, e);
4011 break;
4012 }
4013 if (e->flags & QLA_EVT_FLAG_FREE)
4014 kfree(e);
4015
4016 /* For each work completed decrement vha ref count */
4017 QLA_VHA_MARK_NOT_BUSY(vha);
4018 }
4019 }
4020
4021 /* Relogins all the fcports of a vport
4022 * Context: dpc thread
4023 */
4024 void qla2x00_relogin(struct scsi_qla_host *vha)
4025 {
4026 fc_port_t *fcport;
4027 int status;
4028 uint16_t next_loopid = 0;
4029 struct qla_hw_data *ha = vha->hw;
4030 uint16_t data[2];
4031
4032 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4033 /*
4034 * If the port is not ONLINE then try to login
4035 * to it if we haven't run out of retries.
4036 */
4037 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4038 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
4039 fcport->login_retry--;
4040 if (fcport->flags & FCF_FABRIC_DEVICE) {
4041 if (fcport->flags & FCF_FCP2_DEVICE)
4042 ha->isp_ops->fabric_logout(vha,
4043 fcport->loop_id,
4044 fcport->d_id.b.domain,
4045 fcport->d_id.b.area,
4046 fcport->d_id.b.al_pa);
4047
4048 if (fcport->loop_id == FC_NO_LOOP_ID) {
4049 fcport->loop_id = next_loopid =
4050 ha->min_external_loopid;
4051 status = qla2x00_find_new_loop_id(
4052 vha, fcport);
4053 if (status != QLA_SUCCESS) {
4054 /* Ran out of IDs to use */
4055 break;
4056 }
4057 }
4058
4059 if (IS_ALOGIO_CAPABLE(ha)) {
4060 fcport->flags |= FCF_ASYNC_SENT;
4061 data[0] = 0;
4062 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4063 status = qla2x00_post_async_login_work(
4064 vha, fcport, data);
4065 if (status == QLA_SUCCESS)
4066 continue;
4067 /* Attempt a retry. */
4068 status = 1;
4069 } else {
4070 status = qla2x00_fabric_login(vha,
4071 fcport, &next_loopid);
4072 if (status == QLA_SUCCESS) {
4073 int status2;
4074 uint8_t opts;
4075
4076 opts = 0;
4077 if (fcport->flags &
4078 FCF_FCP2_DEVICE)
4079 opts |= BIT_1;
4080 status2 =
4081 qla2x00_get_port_database(
4082 vha, fcport, opts);
4083 if (status2 != QLA_SUCCESS)
4084 status = 1;
4085 }
4086 }
4087 } else
4088 status = qla2x00_local_device_login(vha,
4089 fcport);
4090
4091 if (status == QLA_SUCCESS) {
4092 fcport->old_loop_id = fcport->loop_id;
4093
4094 ql_dbg(ql_dbg_disc, vha, 0x2003,
4095 "Port login OK: logged in ID 0x%x.\n",
4096 fcport->loop_id);
4097
4098 qla2x00_update_fcport(vha, fcport);
4099
4100 } else if (status == 1) {
4101 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4102 /* retry the login again */
4103 ql_dbg(ql_dbg_disc, vha, 0x2007,
4104 "Retrying %d login again loop_id 0x%x.\n",
4105 fcport->login_retry, fcport->loop_id);
4106 } else {
4107 fcport->login_retry = 0;
4108 }
4109
4110 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
4111 qla2x00_clear_loop_id(fcport);
4112 }
4113 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4114 break;
4115 }
4116 }
4117
4118 /* Schedule work on any of the dpc-workqueues */
4119 void
4120 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4121 {
4122 struct qla_hw_data *ha = base_vha->hw;
4123
4124 switch (work_code) {
4125 case MBA_IDC_AEN: /* 0x8200 */
4126 if (ha->dpc_lp_wq)
4127 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4128 break;
4129
4130 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4131 if (!ha->flags.nic_core_reset_hdlr_active) {
4132 if (ha->dpc_hp_wq)
4133 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4134 } else
4135 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4136 "NIC Core reset is already active. Skip "
4137 "scheduling it again.\n");
4138 break;
4139 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4140 if (ha->dpc_hp_wq)
4141 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4142 break;
4143 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4144 if (ha->dpc_hp_wq)
4145 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4146 break;
4147 default:
4148 ql_log(ql_log_warn, base_vha, 0xb05f,
4149 "Unknow work-code=0x%x.\n", work_code);
4150 }
4151
4152 return;
4153 }
4154
4155 /* Work: Perform NIC Core Unrecoverable state handling */
4156 void
4157 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4158 {
4159 struct qla_hw_data *ha =
4160 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
4161 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4162 uint32_t dev_state = 0;
4163
4164 qla83xx_idc_lock(base_vha, 0);
4165 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4166 qla83xx_reset_ownership(base_vha);
4167 if (ha->flags.nic_core_reset_owner) {
4168 ha->flags.nic_core_reset_owner = 0;
4169 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4170 QLA8XXX_DEV_FAILED);
4171 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4172 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4173 }
4174 qla83xx_idc_unlock(base_vha, 0);
4175 }
4176
4177 /* Work: Execute IDC state handler */
4178 void
4179 qla83xx_idc_state_handler_work(struct work_struct *work)
4180 {
4181 struct qla_hw_data *ha =
4182 container_of(work, struct qla_hw_data, idc_state_handler);
4183 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4184 uint32_t dev_state = 0;
4185
4186 qla83xx_idc_lock(base_vha, 0);
4187 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4188 if (dev_state == QLA8XXX_DEV_FAILED ||
4189 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4190 qla83xx_idc_state_handler(base_vha);
4191 qla83xx_idc_unlock(base_vha, 0);
4192 }
4193
4194 static int
4195 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4196 {
4197 int rval = QLA_SUCCESS;
4198 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4199 uint32_t heart_beat_counter1, heart_beat_counter2;
4200
4201 do {
4202 if (time_after(jiffies, heart_beat_wait)) {
4203 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4204 "Nic Core f/w is not alive.\n");
4205 rval = QLA_FUNCTION_FAILED;
4206 break;
4207 }
4208
4209 qla83xx_idc_lock(base_vha, 0);
4210 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4211 &heart_beat_counter1);
4212 qla83xx_idc_unlock(base_vha, 0);
4213 msleep(100);
4214 qla83xx_idc_lock(base_vha, 0);
4215 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4216 &heart_beat_counter2);
4217 qla83xx_idc_unlock(base_vha, 0);
4218 } while (heart_beat_counter1 == heart_beat_counter2);
4219
4220 return rval;
4221 }
4222
4223 /* Work: Perform NIC Core Reset handling */
4224 void
4225 qla83xx_nic_core_reset_work(struct work_struct *work)
4226 {
4227 struct qla_hw_data *ha =
4228 container_of(work, struct qla_hw_data, nic_core_reset);
4229 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4230 uint32_t dev_state = 0;
4231
4232 if (IS_QLA2031(ha)) {
4233 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4234 ql_log(ql_log_warn, base_vha, 0xb081,
4235 "Failed to dump mctp\n");
4236 return;
4237 }
4238
4239 if (!ha->flags.nic_core_reset_hdlr_active) {
4240 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4241 qla83xx_idc_lock(base_vha, 0);
4242 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4243 &dev_state);
4244 qla83xx_idc_unlock(base_vha, 0);
4245 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4246 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4247 "Nic Core f/w is alive.\n");
4248 return;
4249 }
4250 }
4251
4252 ha->flags.nic_core_reset_hdlr_active = 1;
4253 if (qla83xx_nic_core_reset(base_vha)) {
4254 /* NIC Core reset failed. */
4255 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4256 "NIC Core reset failed.\n");
4257 }
4258 ha->flags.nic_core_reset_hdlr_active = 0;
4259 }
4260 }
4261
4262 /* Work: Handle 8200 IDC aens */
4263 void
4264 qla83xx_service_idc_aen(struct work_struct *work)
4265 {
4266 struct qla_hw_data *ha =
4267 container_of(work, struct qla_hw_data, idc_aen);
4268 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4269 uint32_t dev_state, idc_control;
4270
4271 qla83xx_idc_lock(base_vha, 0);
4272 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4273 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4274 qla83xx_idc_unlock(base_vha, 0);
4275 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4276 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4277 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4278 "Application requested NIC Core Reset.\n");
4279 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4280 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4281 QLA_SUCCESS) {
4282 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4283 "Other protocol driver requested NIC Core Reset.\n");
4284 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4285 }
4286 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4287 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4288 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4289 }
4290 }
4291
4292 static void
4293 qla83xx_wait_logic(void)
4294 {
4295 int i;
4296
4297 /* Yield CPU */
4298 if (!in_interrupt()) {
4299 /*
4300 * Wait about 200ms before retrying again.
4301 * This controls the number of retries for single
4302 * lock operation.
4303 */
4304 msleep(100);
4305 schedule();
4306 } else {
4307 for (i = 0; i < 20; i++)
4308 cpu_relax(); /* This a nop instr on i386 */
4309 }
4310 }
4311
4312 static int
4313 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4314 {
4315 int rval;
4316 uint32_t data;
4317 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4318 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4319 struct qla_hw_data *ha = base_vha->hw;
4320 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4321 "Trying force recovery of the IDC lock.\n");
4322
4323 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4324 if (rval)
4325 return rval;
4326
4327 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4328 return QLA_SUCCESS;
4329 } else {
4330 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4331 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4332 data);
4333 if (rval)
4334 return rval;
4335
4336 msleep(200);
4337
4338 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4339 &data);
4340 if (rval)
4341 return rval;
4342
4343 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4344 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4345 ~(idc_lck_rcvry_stage_mask));
4346 rval = qla83xx_wr_reg(base_vha,
4347 QLA83XX_IDC_LOCK_RECOVERY, data);
4348 if (rval)
4349 return rval;
4350
4351 /* Forcefully perform IDC UnLock */
4352 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4353 &data);
4354 if (rval)
4355 return rval;
4356 /* Clear lock-id by setting 0xff */
4357 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4358 0xff);
4359 if (rval)
4360 return rval;
4361 /* Clear lock-recovery by setting 0x0 */
4362 rval = qla83xx_wr_reg(base_vha,
4363 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4364 if (rval)
4365 return rval;
4366 } else
4367 return QLA_SUCCESS;
4368 }
4369
4370 return rval;
4371 }
4372
4373 static int
4374 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4375 {
4376 int rval = QLA_SUCCESS;
4377 uint32_t o_drv_lockid, n_drv_lockid;
4378 unsigned long lock_recovery_timeout;
4379
4380 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4381 retry_lockid:
4382 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4383 if (rval)
4384 goto exit;
4385
4386 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4387 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4388 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4389 return QLA_SUCCESS;
4390 else
4391 return QLA_FUNCTION_FAILED;
4392 }
4393
4394 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4395 if (rval)
4396 goto exit;
4397
4398 if (o_drv_lockid == n_drv_lockid) {
4399 qla83xx_wait_logic();
4400 goto retry_lockid;
4401 } else
4402 return QLA_SUCCESS;
4403
4404 exit:
4405 return rval;
4406 }
4407
4408 void
4409 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4410 {
4411 uint16_t options = (requester_id << 15) | BIT_6;
4412 uint32_t data;
4413 uint32_t lock_owner;
4414 struct qla_hw_data *ha = base_vha->hw;
4415
4416 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4417 retry_lock:
4418 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4419 == QLA_SUCCESS) {
4420 if (data) {
4421 /* Setting lock-id to our function-number */
4422 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4423 ha->portnum);
4424 } else {
4425 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4426 &lock_owner);
4427 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
4428 "Failed to acquire IDC lock, acquired by %d, "
4429 "retrying...\n", lock_owner);
4430
4431 /* Retry/Perform IDC-Lock recovery */
4432 if (qla83xx_idc_lock_recovery(base_vha)
4433 == QLA_SUCCESS) {
4434 qla83xx_wait_logic();
4435 goto retry_lock;
4436 } else
4437 ql_log(ql_log_warn, base_vha, 0xb075,
4438 "IDC Lock recovery FAILED.\n");
4439 }
4440
4441 }
4442
4443 return;
4444
4445 /* XXX: IDC-lock implementation using access-control mbx */
4446 retry_lock2:
4447 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4448 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4449 "Failed to acquire IDC lock. retrying...\n");
4450 /* Retry/Perform IDC-Lock recovery */
4451 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4452 qla83xx_wait_logic();
4453 goto retry_lock2;
4454 } else
4455 ql_log(ql_log_warn, base_vha, 0xb076,
4456 "IDC Lock recovery FAILED.\n");
4457 }
4458
4459 return;
4460 }
4461
4462 void
4463 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4464 {
4465 uint16_t options = (requester_id << 15) | BIT_7, retry;
4466 uint32_t data;
4467 struct qla_hw_data *ha = base_vha->hw;
4468
4469 /* IDC-unlock implementation using driver-unlock/lock-id
4470 * remote registers
4471 */
4472 retry = 0;
4473 retry_unlock:
4474 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4475 == QLA_SUCCESS) {
4476 if (data == ha->portnum) {
4477 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4478 /* Clearing lock-id by setting 0xff */
4479 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4480 } else if (retry < 10) {
4481 /* SV: XXX: IDC unlock retrying needed here? */
4482
4483 /* Retry for IDC-unlock */
4484 qla83xx_wait_logic();
4485 retry++;
4486 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4487 "Failed to release IDC lock, retyring=%d\n", retry);
4488 goto retry_unlock;
4489 }
4490 } else if (retry < 10) {
4491 /* Retry for IDC-unlock */
4492 qla83xx_wait_logic();
4493 retry++;
4494 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4495 "Failed to read drv-lockid, retyring=%d\n", retry);
4496 goto retry_unlock;
4497 }
4498
4499 return;
4500
4501 /* XXX: IDC-unlock implementation using access-control mbx */
4502 retry = 0;
4503 retry_unlock2:
4504 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4505 if (retry < 10) {
4506 /* Retry for IDC-unlock */
4507 qla83xx_wait_logic();
4508 retry++;
4509 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4510 "Failed to release IDC lock, retyring=%d\n", retry);
4511 goto retry_unlock2;
4512 }
4513 }
4514
4515 return;
4516 }
4517
4518 int
4519 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4520 {
4521 int rval = QLA_SUCCESS;
4522 struct qla_hw_data *ha = vha->hw;
4523 uint32_t drv_presence;
4524
4525 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4526 if (rval == QLA_SUCCESS) {
4527 drv_presence |= (1 << ha->portnum);
4528 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4529 drv_presence);
4530 }
4531
4532 return rval;
4533 }
4534
4535 int
4536 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4537 {
4538 int rval = QLA_SUCCESS;
4539
4540 qla83xx_idc_lock(vha, 0);
4541 rval = __qla83xx_set_drv_presence(vha);
4542 qla83xx_idc_unlock(vha, 0);
4543
4544 return rval;
4545 }
4546
4547 int
4548 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4549 {
4550 int rval = QLA_SUCCESS;
4551 struct qla_hw_data *ha = vha->hw;
4552 uint32_t drv_presence;
4553
4554 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4555 if (rval == QLA_SUCCESS) {
4556 drv_presence &= ~(1 << ha->portnum);
4557 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4558 drv_presence);
4559 }
4560
4561 return rval;
4562 }
4563
4564 int
4565 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4566 {
4567 int rval = QLA_SUCCESS;
4568
4569 qla83xx_idc_lock(vha, 0);
4570 rval = __qla83xx_clear_drv_presence(vha);
4571 qla83xx_idc_unlock(vha, 0);
4572
4573 return rval;
4574 }
4575
4576 static void
4577 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4578 {
4579 struct qla_hw_data *ha = vha->hw;
4580 uint32_t drv_ack, drv_presence;
4581 unsigned long ack_timeout;
4582
4583 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4584 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4585 while (1) {
4586 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4587 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4588 if ((drv_ack & drv_presence) == drv_presence)
4589 break;
4590
4591 if (time_after_eq(jiffies, ack_timeout)) {
4592 ql_log(ql_log_warn, vha, 0xb067,
4593 "RESET ACK TIMEOUT! drv_presence=0x%x "
4594 "drv_ack=0x%x\n", drv_presence, drv_ack);
4595 /*
4596 * The function(s) which did not ack in time are forced
4597 * to withdraw any further participation in the IDC
4598 * reset.
4599 */
4600 if (drv_ack != drv_presence)
4601 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4602 drv_ack);
4603 break;
4604 }
4605
4606 qla83xx_idc_unlock(vha, 0);
4607 msleep(1000);
4608 qla83xx_idc_lock(vha, 0);
4609 }
4610
4611 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4612 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4613 }
4614
4615 static int
4616 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4617 {
4618 int rval = QLA_SUCCESS;
4619 uint32_t idc_control;
4620
4621 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4622 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4623
4624 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4625 __qla83xx_get_idc_control(vha, &idc_control);
4626 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4627 __qla83xx_set_idc_control(vha, 0);
4628
4629 qla83xx_idc_unlock(vha, 0);
4630 rval = qla83xx_restart_nic_firmware(vha);
4631 qla83xx_idc_lock(vha, 0);
4632
4633 if (rval != QLA_SUCCESS) {
4634 ql_log(ql_log_fatal, vha, 0xb06a,
4635 "Failed to restart NIC f/w.\n");
4636 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4637 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4638 } else {
4639 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4640 "Success in restarting nic f/w.\n");
4641 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4642 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4643 }
4644
4645 return rval;
4646 }
4647
4648 /* Assumes idc_lock always held on entry */
4649 int
4650 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4651 {
4652 struct qla_hw_data *ha = base_vha->hw;
4653 int rval = QLA_SUCCESS;
4654 unsigned long dev_init_timeout;
4655 uint32_t dev_state;
4656
4657 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4658 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4659
4660 while (1) {
4661
4662 if (time_after_eq(jiffies, dev_init_timeout)) {
4663 ql_log(ql_log_warn, base_vha, 0xb06e,
4664 "Initialization TIMEOUT!\n");
4665 /* Init timeout. Disable further NIC Core
4666 * communication.
4667 */
4668 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4669 QLA8XXX_DEV_FAILED);
4670 ql_log(ql_log_info, base_vha, 0xb06f,
4671 "HW State: FAILED.\n");
4672 }
4673
4674 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4675 switch (dev_state) {
4676 case QLA8XXX_DEV_READY:
4677 if (ha->flags.nic_core_reset_owner)
4678 qla83xx_idc_audit(base_vha,
4679 IDC_AUDIT_COMPLETION);
4680 ha->flags.nic_core_reset_owner = 0;
4681 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4682 "Reset_owner reset by 0x%x.\n",
4683 ha->portnum);
4684 goto exit;
4685 case QLA8XXX_DEV_COLD:
4686 if (ha->flags.nic_core_reset_owner)
4687 rval = qla83xx_device_bootstrap(base_vha);
4688 else {
4689 /* Wait for AEN to change device-state */
4690 qla83xx_idc_unlock(base_vha, 0);
4691 msleep(1000);
4692 qla83xx_idc_lock(base_vha, 0);
4693 }
4694 break;
4695 case QLA8XXX_DEV_INITIALIZING:
4696 /* Wait for AEN to change device-state */
4697 qla83xx_idc_unlock(base_vha, 0);
4698 msleep(1000);
4699 qla83xx_idc_lock(base_vha, 0);
4700 break;
4701 case QLA8XXX_DEV_NEED_RESET:
4702 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4703 qla83xx_need_reset_handler(base_vha);
4704 else {
4705 /* Wait for AEN to change device-state */
4706 qla83xx_idc_unlock(base_vha, 0);
4707 msleep(1000);
4708 qla83xx_idc_lock(base_vha, 0);
4709 }
4710 /* reset timeout value after need reset handler */
4711 dev_init_timeout = jiffies +
4712 (ha->fcoe_dev_init_timeout * HZ);
4713 break;
4714 case QLA8XXX_DEV_NEED_QUIESCENT:
4715 /* XXX: DEBUG for now */
4716 qla83xx_idc_unlock(base_vha, 0);
4717 msleep(1000);
4718 qla83xx_idc_lock(base_vha, 0);
4719 break;
4720 case QLA8XXX_DEV_QUIESCENT:
4721 /* XXX: DEBUG for now */
4722 if (ha->flags.quiesce_owner)
4723 goto exit;
4724
4725 qla83xx_idc_unlock(base_vha, 0);
4726 msleep(1000);
4727 qla83xx_idc_lock(base_vha, 0);
4728 dev_init_timeout = jiffies +
4729 (ha->fcoe_dev_init_timeout * HZ);
4730 break;
4731 case QLA8XXX_DEV_FAILED:
4732 if (ha->flags.nic_core_reset_owner)
4733 qla83xx_idc_audit(base_vha,
4734 IDC_AUDIT_COMPLETION);
4735 ha->flags.nic_core_reset_owner = 0;
4736 __qla83xx_clear_drv_presence(base_vha);
4737 qla83xx_idc_unlock(base_vha, 0);
4738 qla8xxx_dev_failed_handler(base_vha);
4739 rval = QLA_FUNCTION_FAILED;
4740 qla83xx_idc_lock(base_vha, 0);
4741 goto exit;
4742 case QLA8XXX_BAD_VALUE:
4743 qla83xx_idc_unlock(base_vha, 0);
4744 msleep(1000);
4745 qla83xx_idc_lock(base_vha, 0);
4746 break;
4747 default:
4748 ql_log(ql_log_warn, base_vha, 0xb071,
4749 "Unknow Device State: %x.\n", dev_state);
4750 qla83xx_idc_unlock(base_vha, 0);
4751 qla8xxx_dev_failed_handler(base_vha);
4752 rval = QLA_FUNCTION_FAILED;
4753 qla83xx_idc_lock(base_vha, 0);
4754 goto exit;
4755 }
4756 }
4757
4758 exit:
4759 return rval;
4760 }
4761
4762 void
4763 qla2x00_disable_board_on_pci_error(struct work_struct *work)
4764 {
4765 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4766 board_disable);
4767 struct pci_dev *pdev = ha->pdev;
4768 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4769
4770 ql_log(ql_log_warn, base_vha, 0x015b,
4771 "Disabling adapter.\n");
4772
4773 set_bit(UNLOADING, &base_vha->dpc_flags);
4774
4775 qla2x00_delete_all_vps(ha, base_vha);
4776
4777 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4778
4779 qla2x00_dfs_remove(base_vha);
4780
4781 qla84xx_put_chip(base_vha);
4782
4783 if (base_vha->timer_active)
4784 qla2x00_stop_timer(base_vha);
4785
4786 base_vha->flags.online = 0;
4787
4788 qla2x00_destroy_deferred_work(ha);
4789
4790 /*
4791 * Do not try to stop beacon blink as it will issue a mailbox
4792 * command.
4793 */
4794 qla2x00_free_sysfs_attr(base_vha, false);
4795
4796 fc_remove_host(base_vha->host);
4797
4798 scsi_remove_host(base_vha->host);
4799
4800 base_vha->flags.init_done = 0;
4801 qla25xx_delete_queues(base_vha);
4802 qla2x00_free_irqs(base_vha);
4803 qla2x00_free_fcports(base_vha);
4804 qla2x00_mem_free(ha);
4805 qla82xx_md_free(base_vha);
4806 qla2x00_free_queues(ha);
4807
4808 scsi_host_put(base_vha->host);
4809
4810 qla2x00_unmap_iobases(ha);
4811
4812 pci_release_selected_regions(ha->pdev, ha->bars);
4813 kfree(ha);
4814 ha = NULL;
4815
4816 pci_disable_pcie_error_reporting(pdev);
4817 pci_disable_device(pdev);
4818 pci_set_drvdata(pdev, NULL);
4819
4820 }
4821
4822 /**************************************************************************
4823 * qla2x00_do_dpc
4824 * This kernel thread is a task that is schedule by the interrupt handler
4825 * to perform the background processing for interrupts.
4826 *
4827 * Notes:
4828 * This task always run in the context of a kernel thread. It
4829 * is kick-off by the driver's detect code and starts up
4830 * up one per adapter. It immediately goes to sleep and waits for
4831 * some fibre event. When either the interrupt handler or
4832 * the timer routine detects a event it will one of the task
4833 * bits then wake us up.
4834 **************************************************************************/
4835 static int
4836 qla2x00_do_dpc(void *data)
4837 {
4838 int rval;
4839 scsi_qla_host_t *base_vha;
4840 struct qla_hw_data *ha;
4841
4842 ha = (struct qla_hw_data *)data;
4843 base_vha = pci_get_drvdata(ha->pdev);
4844
4845 set_user_nice(current, MIN_NICE);
4846
4847 set_current_state(TASK_INTERRUPTIBLE);
4848 while (!kthread_should_stop()) {
4849 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4850 "DPC handler sleeping.\n");
4851
4852 schedule();
4853 __set_current_state(TASK_RUNNING);
4854
4855 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4856 goto end_loop;
4857
4858 if (ha->flags.eeh_busy) {
4859 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4860 "eeh_busy=%d.\n", ha->flags.eeh_busy);
4861 goto end_loop;
4862 }
4863
4864 ha->dpc_active = 1;
4865
4866 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4867 "DPC handler waking up, dpc_flags=0x%lx.\n",
4868 base_vha->dpc_flags);
4869
4870 qla2x00_do_work(base_vha);
4871
4872 if (IS_P3P_TYPE(ha)) {
4873 if (IS_QLA8044(ha)) {
4874 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4875 &base_vha->dpc_flags)) {
4876 qla8044_idc_lock(ha);
4877 qla8044_wr_direct(base_vha,
4878 QLA8044_CRB_DEV_STATE_INDEX,
4879 QLA8XXX_DEV_FAILED);
4880 qla8044_idc_unlock(ha);
4881 ql_log(ql_log_info, base_vha, 0x4004,
4882 "HW State: FAILED.\n");
4883 qla8044_device_state_handler(base_vha);
4884 continue;
4885 }
4886
4887 } else {
4888 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4889 &base_vha->dpc_flags)) {
4890 qla82xx_idc_lock(ha);
4891 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4892 QLA8XXX_DEV_FAILED);
4893 qla82xx_idc_unlock(ha);
4894 ql_log(ql_log_info, base_vha, 0x0151,
4895 "HW State: FAILED.\n");
4896 qla82xx_device_state_handler(base_vha);
4897 continue;
4898 }
4899 }
4900
4901 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4902 &base_vha->dpc_flags)) {
4903
4904 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4905 "FCoE context reset scheduled.\n");
4906 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4907 &base_vha->dpc_flags))) {
4908 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4909 /* FCoE-ctx reset failed.
4910 * Escalate to chip-reset
4911 */
4912 set_bit(ISP_ABORT_NEEDED,
4913 &base_vha->dpc_flags);
4914 }
4915 clear_bit(ABORT_ISP_ACTIVE,
4916 &base_vha->dpc_flags);
4917 }
4918
4919 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4920 "FCoE context reset end.\n");
4921 }
4922 } else if (IS_QLAFX00(ha)) {
4923 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4924 &base_vha->dpc_flags)) {
4925 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4926 "Firmware Reset Recovery\n");
4927 if (qlafx00_reset_initialize(base_vha)) {
4928 /* Failed. Abort isp later. */
4929 if (!test_bit(UNLOADING,
4930 &base_vha->dpc_flags)) {
4931 set_bit(ISP_UNRECOVERABLE,
4932 &base_vha->dpc_flags);
4933 ql_dbg(ql_dbg_dpc, base_vha,
4934 0x4021,
4935 "Reset Recovery Failed\n");
4936 }
4937 }
4938 }
4939
4940 if (test_and_clear_bit(FX00_TARGET_SCAN,
4941 &base_vha->dpc_flags)) {
4942 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4943 "ISPFx00 Target Scan scheduled\n");
4944 if (qlafx00_rescan_isp(base_vha)) {
4945 if (!test_bit(UNLOADING,
4946 &base_vha->dpc_flags))
4947 set_bit(ISP_UNRECOVERABLE,
4948 &base_vha->dpc_flags);
4949 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4950 "ISPFx00 Target Scan Failed\n");
4951 }
4952 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4953 "ISPFx00 Target Scan End\n");
4954 }
4955 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
4956 &base_vha->dpc_flags)) {
4957 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
4958 "ISPFx00 Host Info resend scheduled\n");
4959 qlafx00_fx_disc(base_vha,
4960 &base_vha->hw->mr.fcport,
4961 FXDISC_REG_HOST_INFO);
4962 }
4963 }
4964
4965 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4966 &base_vha->dpc_flags)) {
4967
4968 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4969 "ISP abort scheduled.\n");
4970 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4971 &base_vha->dpc_flags))) {
4972
4973 if (ha->isp_ops->abort_isp(base_vha)) {
4974 /* failed. retry later */
4975 set_bit(ISP_ABORT_NEEDED,
4976 &base_vha->dpc_flags);
4977 }
4978 clear_bit(ABORT_ISP_ACTIVE,
4979 &base_vha->dpc_flags);
4980 }
4981
4982 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4983 "ISP abort end.\n");
4984 }
4985
4986 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4987 &base_vha->dpc_flags)) {
4988 qla2x00_update_fcports(base_vha);
4989 }
4990
4991 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4992 int ret;
4993 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4994 if (ret != QLA_SUCCESS)
4995 ql_log(ql_log_warn, base_vha, 0x121,
4996 "Failed to enable receiving of RSCN "
4997 "requests: 0x%x.\n", ret);
4998 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4999 }
5000
5001 if (IS_QLAFX00(ha))
5002 goto loop_resync_check;
5003
5004 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
5005 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5006 "Quiescence mode scheduled.\n");
5007 if (IS_P3P_TYPE(ha)) {
5008 if (IS_QLA82XX(ha))
5009 qla82xx_device_state_handler(base_vha);
5010 if (IS_QLA8044(ha))
5011 qla8044_device_state_handler(base_vha);
5012 clear_bit(ISP_QUIESCE_NEEDED,
5013 &base_vha->dpc_flags);
5014 if (!ha->flags.quiesce_owner) {
5015 qla2x00_perform_loop_resync(base_vha);
5016 if (IS_QLA82XX(ha)) {
5017 qla82xx_idc_lock(ha);
5018 qla82xx_clear_qsnt_ready(
5019 base_vha);
5020 qla82xx_idc_unlock(ha);
5021 } else if (IS_QLA8044(ha)) {
5022 qla8044_idc_lock(ha);
5023 qla8044_clear_qsnt_ready(
5024 base_vha);
5025 qla8044_idc_unlock(ha);
5026 }
5027 }
5028 } else {
5029 clear_bit(ISP_QUIESCE_NEEDED,
5030 &base_vha->dpc_flags);
5031 qla2x00_quiesce_io(base_vha);
5032 }
5033 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5034 "Quiescence mode end.\n");
5035 }
5036
5037 if (test_and_clear_bit(RESET_MARKER_NEEDED,
5038 &base_vha->dpc_flags) &&
5039 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
5040
5041 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5042 "Reset marker scheduled.\n");
5043 qla2x00_rst_aen(base_vha);
5044 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
5045 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5046 "Reset marker end.\n");
5047 }
5048
5049 /* Retry each device up to login retry count */
5050 if ((test_and_clear_bit(RELOGIN_NEEDED,
5051 &base_vha->dpc_flags)) &&
5052 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5053 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
5054
5055 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5056 "Relogin scheduled.\n");
5057 qla2x00_relogin(base_vha);
5058 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5059 "Relogin end.\n");
5060 }
5061 loop_resync_check:
5062 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
5063 &base_vha->dpc_flags)) {
5064
5065 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5066 "Loop resync scheduled.\n");
5067
5068 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
5069 &base_vha->dpc_flags))) {
5070
5071 rval = qla2x00_loop_resync(base_vha);
5072
5073 clear_bit(LOOP_RESYNC_ACTIVE,
5074 &base_vha->dpc_flags);
5075 }
5076
5077 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5078 "Loop resync end.\n");
5079 }
5080
5081 if (IS_QLAFX00(ha))
5082 goto intr_on_check;
5083
5084 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5085 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5086 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5087 qla2xxx_flash_npiv_conf(base_vha);
5088 }
5089
5090 intr_on_check:
5091 if (!ha->interrupts_on)
5092 ha->isp_ops->enable_intrs(ha);
5093
5094 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
5095 &base_vha->dpc_flags)) {
5096 if (ha->beacon_blink_led == 1)
5097 ha->isp_ops->beacon_blink(base_vha);
5098 }
5099
5100 if (!IS_QLAFX00(ha))
5101 qla2x00_do_dpc_all_vps(base_vha);
5102
5103 ha->dpc_active = 0;
5104 end_loop:
5105 set_current_state(TASK_INTERRUPTIBLE);
5106 } /* End of while(1) */
5107 __set_current_state(TASK_RUNNING);
5108
5109 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5110 "DPC handler exiting.\n");
5111
5112 /*
5113 * Make sure that nobody tries to wake us up again.
5114 */
5115 ha->dpc_active = 0;
5116
5117 /* Cleanup any residual CTX SRBs. */
5118 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5119
5120 return 0;
5121 }
5122
5123 void
5124 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
5125 {
5126 struct qla_hw_data *ha = vha->hw;
5127 struct task_struct *t = ha->dpc_thread;
5128
5129 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
5130 wake_up_process(t);
5131 }
5132
5133 /*
5134 * qla2x00_rst_aen
5135 * Processes asynchronous reset.
5136 *
5137 * Input:
5138 * ha = adapter block pointer.
5139 */
5140 static void
5141 qla2x00_rst_aen(scsi_qla_host_t *vha)
5142 {
5143 if (vha->flags.online && !vha->flags.reset_active &&
5144 !atomic_read(&vha->loop_down_timer) &&
5145 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
5146 do {
5147 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5148
5149 /*
5150 * Issue marker command only when we are going to start
5151 * the I/O.
5152 */
5153 vha->marker_needed = 1;
5154 } while (!atomic_read(&vha->loop_down_timer) &&
5155 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
5156 }
5157 }
5158
5159 /**************************************************************************
5160 * qla2x00_timer
5161 *
5162 * Description:
5163 * One second timer
5164 *
5165 * Context: Interrupt
5166 ***************************************************************************/
5167 void
5168 qla2x00_timer(scsi_qla_host_t *vha)
5169 {
5170 unsigned long cpu_flags = 0;
5171 int start_dpc = 0;
5172 int index;
5173 srb_t *sp;
5174 uint16_t w;
5175 struct qla_hw_data *ha = vha->hw;
5176 struct req_que *req;
5177
5178 if (ha->flags.eeh_busy) {
5179 ql_dbg(ql_dbg_timer, vha, 0x6000,
5180 "EEH = %d, restarting timer.\n",
5181 ha->flags.eeh_busy);
5182 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5183 return;
5184 }
5185
5186 /*
5187 * Hardware read to raise pending EEH errors during mailbox waits. If
5188 * the read returns -1 then disable the board.
5189 */
5190 if (!pci_channel_offline(ha->pdev)) {
5191 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
5192 if (w == 0xffff)
5193 /*
5194 * Schedule this on the default system workqueue so that
5195 * all the adapter workqueues and the DPC thread can be
5196 * shutdown cleanly.
5197 */
5198 schedule_work(&ha->board_disable);
5199 }
5200
5201 /* Make sure qla82xx_watchdog is run only for physical port */
5202 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
5203 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5204 start_dpc++;
5205 if (IS_QLA82XX(ha))
5206 qla82xx_watchdog(vha);
5207 else if (IS_QLA8044(ha))
5208 qla8044_watchdog(vha);
5209 }
5210
5211 if (!vha->vp_idx && IS_QLAFX00(ha))
5212 qlafx00_timer_routine(vha);
5213
5214 /* Loop down handler. */
5215 if (atomic_read(&vha->loop_down_timer) > 0 &&
5216 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5217 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
5218 && vha->flags.online) {
5219
5220 if (atomic_read(&vha->loop_down_timer) ==
5221 vha->loop_down_abort_time) {
5222
5223 ql_log(ql_log_info, vha, 0x6008,
5224 "Loop down - aborting the queues before time expires.\n");
5225
5226 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5227 atomic_set(&vha->loop_state, LOOP_DEAD);
5228
5229 /*
5230 * Schedule an ISP abort to return any FCP2-device
5231 * commands.
5232 */
5233 /* NPIV - scan physical port only */
5234 if (!vha->vp_idx) {
5235 spin_lock_irqsave(&ha->hardware_lock,
5236 cpu_flags);
5237 req = ha->req_q_map[0];
5238 for (index = 1;
5239 index < req->num_outstanding_cmds;
5240 index++) {
5241 fc_port_t *sfcp;
5242
5243 sp = req->outstanding_cmds[index];
5244 if (!sp)
5245 continue;
5246 if (sp->type != SRB_SCSI_CMD)
5247 continue;
5248 sfcp = sp->fcport;
5249 if (!(sfcp->flags & FCF_FCP2_DEVICE))
5250 continue;
5251
5252 if (IS_QLA82XX(ha))
5253 set_bit(FCOE_CTX_RESET_NEEDED,
5254 &vha->dpc_flags);
5255 else
5256 set_bit(ISP_ABORT_NEEDED,
5257 &vha->dpc_flags);
5258 break;
5259 }
5260 spin_unlock_irqrestore(&ha->hardware_lock,
5261 cpu_flags);
5262 }
5263 start_dpc++;
5264 }
5265
5266 /* if the loop has been down for 4 minutes, reinit adapter */
5267 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
5268 if (!(vha->device_flags & DFLG_NO_CABLE)) {
5269 ql_log(ql_log_warn, vha, 0x6009,
5270 "Loop down - aborting ISP.\n");
5271
5272 if (IS_QLA82XX(ha))
5273 set_bit(FCOE_CTX_RESET_NEEDED,
5274 &vha->dpc_flags);
5275 else
5276 set_bit(ISP_ABORT_NEEDED,
5277 &vha->dpc_flags);
5278 }
5279 }
5280 ql_dbg(ql_dbg_timer, vha, 0x600a,
5281 "Loop down - seconds remaining %d.\n",
5282 atomic_read(&vha->loop_down_timer));
5283 }
5284 /* Check if beacon LED needs to be blinked for physical host only */
5285 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
5286 /* There is no beacon_blink function for ISP82xx */
5287 if (!IS_P3P_TYPE(ha)) {
5288 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5289 start_dpc++;
5290 }
5291 }
5292
5293 /* Process any deferred work. */
5294 if (!list_empty(&vha->work_list))
5295 start_dpc++;
5296
5297 /* Schedule the DPC routine if needed */
5298 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5299 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5300 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
5301 start_dpc ||
5302 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5303 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
5304 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5305 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
5306 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
5307 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
5308 ql_dbg(ql_dbg_timer, vha, 0x600b,
5309 "isp_abort_needed=%d loop_resync_needed=%d "
5310 "fcport_update_needed=%d start_dpc=%d "
5311 "reset_marker_needed=%d",
5312 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5313 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5314 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5315 start_dpc,
5316 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5317 ql_dbg(ql_dbg_timer, vha, 0x600c,
5318 "beacon_blink_needed=%d isp_unrecoverable=%d "
5319 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
5320 "relogin_needed=%d.\n",
5321 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5322 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5323 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5324 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
5325 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
5326 qla2xxx_wake_dpc(vha);
5327 }
5328
5329 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5330 }
5331
5332 /* Firmware interface routines. */
5333
5334 #define FW_BLOBS 11
5335 #define FW_ISP21XX 0
5336 #define FW_ISP22XX 1
5337 #define FW_ISP2300 2
5338 #define FW_ISP2322 3
5339 #define FW_ISP24XX 4
5340 #define FW_ISP25XX 5
5341 #define FW_ISP81XX 6
5342 #define FW_ISP82XX 7
5343 #define FW_ISP2031 8
5344 #define FW_ISP8031 9
5345 #define FW_ISP27XX 10
5346
5347 #define FW_FILE_ISP21XX "ql2100_fw.bin"
5348 #define FW_FILE_ISP22XX "ql2200_fw.bin"
5349 #define FW_FILE_ISP2300 "ql2300_fw.bin"
5350 #define FW_FILE_ISP2322 "ql2322_fw.bin"
5351 #define FW_FILE_ISP24XX "ql2400_fw.bin"
5352 #define FW_FILE_ISP25XX "ql2500_fw.bin"
5353 #define FW_FILE_ISP81XX "ql8100_fw.bin"
5354 #define FW_FILE_ISP82XX "ql8200_fw.bin"
5355 #define FW_FILE_ISP2031 "ql2600_fw.bin"
5356 #define FW_FILE_ISP8031 "ql8300_fw.bin"
5357 #define FW_FILE_ISP27XX "ql2700_fw.bin"
5358
5359
5360 static DEFINE_MUTEX(qla_fw_lock);
5361
5362 static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
5363 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5364 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5365 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5366 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5367 { .name = FW_FILE_ISP24XX, },
5368 { .name = FW_FILE_ISP25XX, },
5369 { .name = FW_FILE_ISP81XX, },
5370 { .name = FW_FILE_ISP82XX, },
5371 { .name = FW_FILE_ISP2031, },
5372 { .name = FW_FILE_ISP8031, },
5373 { .name = FW_FILE_ISP27XX, },
5374 };
5375
5376 struct fw_blob *
5377 qla2x00_request_firmware(scsi_qla_host_t *vha)
5378 {
5379 struct qla_hw_data *ha = vha->hw;
5380 struct fw_blob *blob;
5381
5382 if (IS_QLA2100(ha)) {
5383 blob = &qla_fw_blobs[FW_ISP21XX];
5384 } else if (IS_QLA2200(ha)) {
5385 blob = &qla_fw_blobs[FW_ISP22XX];
5386 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5387 blob = &qla_fw_blobs[FW_ISP2300];
5388 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5389 blob = &qla_fw_blobs[FW_ISP2322];
5390 } else if (IS_QLA24XX_TYPE(ha)) {
5391 blob = &qla_fw_blobs[FW_ISP24XX];
5392 } else if (IS_QLA25XX(ha)) {
5393 blob = &qla_fw_blobs[FW_ISP25XX];
5394 } else if (IS_QLA81XX(ha)) {
5395 blob = &qla_fw_blobs[FW_ISP81XX];
5396 } else if (IS_QLA82XX(ha)) {
5397 blob = &qla_fw_blobs[FW_ISP82XX];
5398 } else if (IS_QLA2031(ha)) {
5399 blob = &qla_fw_blobs[FW_ISP2031];
5400 } else if (IS_QLA8031(ha)) {
5401 blob = &qla_fw_blobs[FW_ISP8031];
5402 } else if (IS_QLA27XX(ha)) {
5403 blob = &qla_fw_blobs[FW_ISP27XX];
5404 } else {
5405 return NULL;
5406 }
5407
5408 mutex_lock(&qla_fw_lock);
5409 if (blob->fw)
5410 goto out;
5411
5412 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
5413 ql_log(ql_log_warn, vha, 0x0063,
5414 "Failed to load firmware image (%s).\n", blob->name);
5415 blob->fw = NULL;
5416 blob = NULL;
5417 goto out;
5418 }
5419
5420 out:
5421 mutex_unlock(&qla_fw_lock);
5422 return blob;
5423 }
5424
5425 static void
5426 qla2x00_release_firmware(void)
5427 {
5428 int idx;
5429
5430 mutex_lock(&qla_fw_lock);
5431 for (idx = 0; idx < FW_BLOBS; idx++)
5432 release_firmware(qla_fw_blobs[idx].fw);
5433 mutex_unlock(&qla_fw_lock);
5434 }
5435
5436 static pci_ers_result_t
5437 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5438 {
5439 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5440 struct qla_hw_data *ha = vha->hw;
5441
5442 ql_dbg(ql_dbg_aer, vha, 0x9000,
5443 "PCI error detected, state %x.\n", state);
5444
5445 switch (state) {
5446 case pci_channel_io_normal:
5447 ha->flags.eeh_busy = 0;
5448 return PCI_ERS_RESULT_CAN_RECOVER;
5449 case pci_channel_io_frozen:
5450 ha->flags.eeh_busy = 1;
5451 /* For ISP82XX complete any pending mailbox cmd */
5452 if (IS_QLA82XX(ha)) {
5453 ha->flags.isp82xx_fw_hung = 1;
5454 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5455 qla82xx_clear_pending_mbx(vha);
5456 }
5457 qla2x00_free_irqs(vha);
5458 pci_disable_device(pdev);
5459 /* Return back all IOs */
5460 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
5461 return PCI_ERS_RESULT_NEED_RESET;
5462 case pci_channel_io_perm_failure:
5463 ha->flags.pci_channel_io_perm_failure = 1;
5464 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
5465 return PCI_ERS_RESULT_DISCONNECT;
5466 }
5467 return PCI_ERS_RESULT_NEED_RESET;
5468 }
5469
5470 static pci_ers_result_t
5471 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5472 {
5473 int risc_paused = 0;
5474 uint32_t stat;
5475 unsigned long flags;
5476 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5477 struct qla_hw_data *ha = base_vha->hw;
5478 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5479 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5480
5481 if (IS_QLA82XX(ha))
5482 return PCI_ERS_RESULT_RECOVERED;
5483
5484 spin_lock_irqsave(&ha->hardware_lock, flags);
5485 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5486 stat = RD_REG_DWORD(&reg->hccr);
5487 if (stat & HCCR_RISC_PAUSE)
5488 risc_paused = 1;
5489 } else if (IS_QLA23XX(ha)) {
5490 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5491 if (stat & HSR_RISC_PAUSED)
5492 risc_paused = 1;
5493 } else if (IS_FWI2_CAPABLE(ha)) {
5494 stat = RD_REG_DWORD(&reg24->host_status);
5495 if (stat & HSRX_RISC_PAUSED)
5496 risc_paused = 1;
5497 }
5498 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5499
5500 if (risc_paused) {
5501 ql_log(ql_log_info, base_vha, 0x9003,
5502 "RISC paused -- mmio_enabled, Dumping firmware.\n");
5503 ha->isp_ops->fw_dump(base_vha, 0);
5504
5505 return PCI_ERS_RESULT_NEED_RESET;
5506 } else
5507 return PCI_ERS_RESULT_RECOVERED;
5508 }
5509
5510 static uint32_t
5511 qla82xx_error_recovery(scsi_qla_host_t *base_vha)
5512 {
5513 uint32_t rval = QLA_FUNCTION_FAILED;
5514 uint32_t drv_active = 0;
5515 struct qla_hw_data *ha = base_vha->hw;
5516 int fn;
5517 struct pci_dev *other_pdev = NULL;
5518
5519 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5520 "Entered %s.\n", __func__);
5521
5522 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5523
5524 if (base_vha->flags.online) {
5525 /* Abort all outstanding commands,
5526 * so as to be requeued later */
5527 qla2x00_abort_isp_cleanup(base_vha);
5528 }
5529
5530
5531 fn = PCI_FUNC(ha->pdev->devfn);
5532 while (fn > 0) {
5533 fn--;
5534 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5535 "Finding pci device at function = 0x%x.\n", fn);
5536 other_pdev =
5537 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5538 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5539 fn));
5540
5541 if (!other_pdev)
5542 continue;
5543 if (atomic_read(&other_pdev->enable_cnt)) {
5544 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5545 "Found PCI func available and enable at 0x%x.\n",
5546 fn);
5547 pci_dev_put(other_pdev);
5548 break;
5549 }
5550 pci_dev_put(other_pdev);
5551 }
5552
5553 if (!fn) {
5554 /* Reset owner */
5555 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5556 "This devfn is reset owner = 0x%x.\n",
5557 ha->pdev->devfn);
5558 qla82xx_idc_lock(ha);
5559
5560 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5561 QLA8XXX_DEV_INITIALIZING);
5562
5563 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5564 QLA82XX_IDC_VERSION);
5565
5566 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
5567 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5568 "drv_active = 0x%x.\n", drv_active);
5569
5570 qla82xx_idc_unlock(ha);
5571 /* Reset if device is not already reset
5572 * drv_active would be 0 if a reset has already been done
5573 */
5574 if (drv_active)
5575 rval = qla82xx_start_firmware(base_vha);
5576 else
5577 rval = QLA_SUCCESS;
5578 qla82xx_idc_lock(ha);
5579
5580 if (rval != QLA_SUCCESS) {
5581 ql_log(ql_log_info, base_vha, 0x900b,
5582 "HW State: FAILED.\n");
5583 qla82xx_clear_drv_active(ha);
5584 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5585 QLA8XXX_DEV_FAILED);
5586 } else {
5587 ql_log(ql_log_info, base_vha, 0x900c,
5588 "HW State: READY.\n");
5589 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5590 QLA8XXX_DEV_READY);
5591 qla82xx_idc_unlock(ha);
5592 ha->flags.isp82xx_fw_hung = 0;
5593 rval = qla82xx_restart_isp(base_vha);
5594 qla82xx_idc_lock(ha);
5595 /* Clear driver state register */
5596 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5597 qla82xx_set_drv_active(base_vha);
5598 }
5599 qla82xx_idc_unlock(ha);
5600 } else {
5601 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5602 "This devfn is not reset owner = 0x%x.\n",
5603 ha->pdev->devfn);
5604 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
5605 QLA8XXX_DEV_READY)) {
5606 ha->flags.isp82xx_fw_hung = 0;
5607 rval = qla82xx_restart_isp(base_vha);
5608 qla82xx_idc_lock(ha);
5609 qla82xx_set_drv_active(base_vha);
5610 qla82xx_idc_unlock(ha);
5611 }
5612 }
5613 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5614
5615 return rval;
5616 }
5617
5618 static pci_ers_result_t
5619 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5620 {
5621 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
5622 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5623 struct qla_hw_data *ha = base_vha->hw;
5624 struct rsp_que *rsp;
5625 int rc, retries = 10;
5626
5627 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5628 "Slot Reset.\n");
5629
5630 /* Workaround: qla2xxx driver which access hardware earlier
5631 * needs error state to be pci_channel_io_online.
5632 * Otherwise mailbox command timesout.
5633 */
5634 pdev->error_state = pci_channel_io_normal;
5635
5636 pci_restore_state(pdev);
5637
5638 /* pci_restore_state() clears the saved_state flag of the device
5639 * save restored state which resets saved_state flag
5640 */
5641 pci_save_state(pdev);
5642
5643 if (ha->mem_only)
5644 rc = pci_enable_device_mem(pdev);
5645 else
5646 rc = pci_enable_device(pdev);
5647
5648 if (rc) {
5649 ql_log(ql_log_warn, base_vha, 0x9005,
5650 "Can't re-enable PCI device after reset.\n");
5651 goto exit_slot_reset;
5652 }
5653
5654 rsp = ha->rsp_q_map[0];
5655 if (qla2x00_request_irqs(ha, rsp))
5656 goto exit_slot_reset;
5657
5658 if (ha->isp_ops->pci_config(base_vha))
5659 goto exit_slot_reset;
5660
5661 if (IS_QLA82XX(ha)) {
5662 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5663 ret = PCI_ERS_RESULT_RECOVERED;
5664 goto exit_slot_reset;
5665 } else
5666 goto exit_slot_reset;
5667 }
5668
5669 while (ha->flags.mbox_busy && retries--)
5670 msleep(1000);
5671
5672 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5673 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
5674 ret = PCI_ERS_RESULT_RECOVERED;
5675 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5676
5677
5678 exit_slot_reset:
5679 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5680 "slot_reset return %x.\n", ret);
5681
5682 return ret;
5683 }
5684
5685 static void
5686 qla2xxx_pci_resume(struct pci_dev *pdev)
5687 {
5688 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5689 struct qla_hw_data *ha = base_vha->hw;
5690 int ret;
5691
5692 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5693 "pci_resume.\n");
5694
5695 ret = qla2x00_wait_for_hba_online(base_vha);
5696 if (ret != QLA_SUCCESS) {
5697 ql_log(ql_log_fatal, base_vha, 0x9002,
5698 "The device failed to resume I/O from slot/link_reset.\n");
5699 }
5700
5701 pci_cleanup_aer_uncorrect_error_status(pdev);
5702
5703 ha->flags.eeh_busy = 0;
5704 }
5705
5706 static const struct pci_error_handlers qla2xxx_err_handler = {
5707 .error_detected = qla2xxx_pci_error_detected,
5708 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5709 .slot_reset = qla2xxx_pci_slot_reset,
5710 .resume = qla2xxx_pci_resume,
5711 };
5712
5713 static struct pci_device_id qla2xxx_pci_tbl[] = {
5714 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5715 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5716 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5717 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5718 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5719 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5720 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5721 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5722 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
5723 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
5724 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5725 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
5726 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
5727 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
5728 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
5729 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5730 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
5731 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
5732 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
5733 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
5734 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
5735 { 0 },
5736 };
5737 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5738
5739 static struct pci_driver qla2xxx_pci_driver = {
5740 .name = QLA2XXX_DRIVER_NAME,
5741 .driver = {
5742 .owner = THIS_MODULE,
5743 },
5744 .id_table = qla2xxx_pci_tbl,
5745 .probe = qla2x00_probe_one,
5746 .remove = qla2x00_remove_one,
5747 .shutdown = qla2x00_shutdown,
5748 .err_handler = &qla2xxx_err_handler,
5749 };
5750
5751 static const struct file_operations apidev_fops = {
5752 .owner = THIS_MODULE,
5753 .llseek = noop_llseek,
5754 };
5755
5756 /**
5757 * qla2x00_module_init - Module initialization.
5758 **/
5759 static int __init
5760 qla2x00_module_init(void)
5761 {
5762 int ret = 0;
5763
5764 /* Allocate cache for SRBs. */
5765 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
5766 SLAB_HWCACHE_ALIGN, NULL);
5767 if (srb_cachep == NULL) {
5768 ql_log(ql_log_fatal, NULL, 0x0001,
5769 "Unable to allocate SRB cache...Failing load!.\n");
5770 return -ENOMEM;
5771 }
5772
5773 /* Initialize target kmem_cache and mem_pools */
5774 ret = qlt_init();
5775 if (ret < 0) {
5776 kmem_cache_destroy(srb_cachep);
5777 return ret;
5778 } else if (ret > 0) {
5779 /*
5780 * If initiator mode is explictly disabled by qlt_init(),
5781 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5782 * performing scsi_scan_target() during LOOP UP event.
5783 */
5784 qla2xxx_transport_functions.disable_target_scan = 1;
5785 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5786 }
5787
5788 /* Derive version string. */
5789 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
5790 if (ql2xextended_error_logging)
5791 strcat(qla2x00_version_str, "-debug");
5792
5793 qla2xxx_transport_template =
5794 fc_attach_transport(&qla2xxx_transport_functions);
5795 if (!qla2xxx_transport_template) {
5796 kmem_cache_destroy(srb_cachep);
5797 ql_log(ql_log_fatal, NULL, 0x0002,
5798 "fc_attach_transport failed...Failing load!.\n");
5799 qlt_exit();
5800 return -ENODEV;
5801 }
5802
5803 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5804 if (apidev_major < 0) {
5805 ql_log(ql_log_fatal, NULL, 0x0003,
5806 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
5807 }
5808
5809 qla2xxx_transport_vport_template =
5810 fc_attach_transport(&qla2xxx_transport_vport_functions);
5811 if (!qla2xxx_transport_vport_template) {
5812 kmem_cache_destroy(srb_cachep);
5813 qlt_exit();
5814 fc_release_transport(qla2xxx_transport_template);
5815 ql_log(ql_log_fatal, NULL, 0x0004,
5816 "fc_attach_transport vport failed...Failing load!.\n");
5817 return -ENODEV;
5818 }
5819 ql_log(ql_log_info, NULL, 0x0005,
5820 "QLogic Fibre Channel HBA Driver: %s.\n",
5821 qla2x00_version_str);
5822 ret = pci_register_driver(&qla2xxx_pci_driver);
5823 if (ret) {
5824 kmem_cache_destroy(srb_cachep);
5825 qlt_exit();
5826 fc_release_transport(qla2xxx_transport_template);
5827 fc_release_transport(qla2xxx_transport_vport_template);
5828 ql_log(ql_log_fatal, NULL, 0x0006,
5829 "pci_register_driver failed...ret=%d Failing load!.\n",
5830 ret);
5831 }
5832 return ret;
5833 }
5834
5835 /**
5836 * qla2x00_module_exit - Module cleanup.
5837 **/
5838 static void __exit
5839 qla2x00_module_exit(void)
5840 {
5841 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
5842 pci_unregister_driver(&qla2xxx_pci_driver);
5843 qla2x00_release_firmware();
5844 kmem_cache_destroy(srb_cachep);
5845 qlt_exit();
5846 if (ctx_cachep)
5847 kmem_cache_destroy(ctx_cachep);
5848 fc_release_transport(qla2xxx_transport_template);
5849 fc_release_transport(qla2xxx_transport_vport_template);
5850 }
5851
5852 module_init(qla2x00_module_init);
5853 module_exit(qla2x00_module_exit);
5854
5855 MODULE_AUTHOR("QLogic Corporation");
5856 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5857 MODULE_LICENSE("GPL");
5858 MODULE_VERSION(QLA2XXX_VERSION);
5859 MODULE_FIRMWARE(FW_FILE_ISP21XX);
5860 MODULE_FIRMWARE(FW_FILE_ISP22XX);
5861 MODULE_FIRMWARE(FW_FILE_ISP2300);
5862 MODULE_FIRMWARE(FW_FILE_ISP2322);
5863 MODULE_FIRMWARE(FW_FILE_ISP24XX);
5864 MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux kernel - Deliverables
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