2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 #include <linux/delay.h>
10 #include <linux/vmalloc.h>
11 #include <asm/uaccess.h>
14 * NVRAM support routines
18 * qla2x00_lock_nvram_access() -
22 qla2x00_lock_nvram_access(struct qla_hw_data
*ha
)
25 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
27 if (!IS_QLA2100(ha
) && !IS_QLA2200(ha
) && !IS_QLA2300(ha
)) {
28 data
= RD_REG_WORD(®
->nvram
);
29 while (data
& NVR_BUSY
) {
31 data
= RD_REG_WORD(®
->nvram
);
35 WRT_REG_WORD(®
->u
.isp2300
.host_semaphore
, 0x1);
36 RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
38 data
= RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
39 while ((data
& BIT_0
) == 0) {
42 WRT_REG_WORD(®
->u
.isp2300
.host_semaphore
, 0x1);
43 RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
45 data
= RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
51 * qla2x00_unlock_nvram_access() -
55 qla2x00_unlock_nvram_access(struct qla_hw_data
*ha
)
57 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
59 if (!IS_QLA2100(ha
) && !IS_QLA2200(ha
) && !IS_QLA2300(ha
)) {
60 WRT_REG_WORD(®
->u
.isp2300
.host_semaphore
, 0);
61 RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
66 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
68 * @data: Serial interface selector
71 qla2x00_nv_write(struct qla_hw_data
*ha
, uint16_t data
)
73 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
75 WRT_REG_WORD(®
->nvram
, data
| NVR_SELECT
| NVR_WRT_ENABLE
);
76 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
78 WRT_REG_WORD(®
->nvram
, data
| NVR_SELECT
| NVR_CLOCK
|
80 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
82 WRT_REG_WORD(®
->nvram
, data
| NVR_SELECT
| NVR_WRT_ENABLE
);
83 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
88 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
91 * @nv_cmd: NVRAM command
93 * Bit definitions for NVRAM command:
98 * Bit 15-0 = write data
100 * Returns the word read from nvram @addr.
103 qla2x00_nvram_request(struct qla_hw_data
*ha
, uint32_t nv_cmd
)
106 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
110 /* Send command to NVRAM. */
112 for (cnt
= 0; cnt
< 11; cnt
++) {
114 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
116 qla2x00_nv_write(ha
, 0);
120 /* Read data from NVRAM. */
121 for (cnt
= 0; cnt
< 16; cnt
++) {
122 WRT_REG_WORD(®
->nvram
, NVR_SELECT
| NVR_CLOCK
);
123 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
126 reg_data
= RD_REG_WORD(®
->nvram
);
127 if (reg_data
& NVR_DATA_IN
)
129 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
130 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
135 WRT_REG_WORD(®
->nvram
, NVR_DESELECT
);
136 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
144 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
145 * request routine to get the word from NVRAM.
147 * @addr: Address in NVRAM to read
149 * Returns the word read from nvram @addr.
152 qla2x00_get_nvram_word(struct qla_hw_data
*ha
, uint32_t addr
)
158 nv_cmd
|= NV_READ_OP
;
159 data
= qla2x00_nvram_request(ha
, nv_cmd
);
165 * qla2x00_nv_deselect() - Deselect NVRAM operations.
169 qla2x00_nv_deselect(struct qla_hw_data
*ha
)
171 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
173 WRT_REG_WORD(®
->nvram
, NVR_DESELECT
);
174 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
179 * qla2x00_write_nvram_word() - Write NVRAM data.
181 * @addr: Address in NVRAM to write
182 * @data: word to program
185 qla2x00_write_nvram_word(struct qla_hw_data
*ha
, uint32_t addr
, uint16_t data
)
189 uint32_t nv_cmd
, wait_cnt
;
190 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
192 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
193 qla2x00_nv_write(ha
, 0);
194 qla2x00_nv_write(ha
, 0);
196 for (word
= 0; word
< 8; word
++)
197 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
199 qla2x00_nv_deselect(ha
);
202 nv_cmd
= (addr
<< 16) | NV_WRITE_OP
;
205 for (count
= 0; count
< 27; count
++) {
207 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
209 qla2x00_nv_write(ha
, 0);
214 qla2x00_nv_deselect(ha
);
216 /* Wait for NVRAM to become ready */
217 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
218 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
219 wait_cnt
= NVR_WAIT_CNT
;
222 DEBUG9_10(qla_printk(KERN_WARNING
, ha
,
223 "NVRAM didn't go ready...\n"));
227 word
= RD_REG_WORD(®
->nvram
);
228 } while ((word
& NVR_DATA_IN
) == 0);
230 qla2x00_nv_deselect(ha
);
233 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
234 for (count
= 0; count
< 10; count
++)
235 qla2x00_nv_write(ha
, 0);
237 qla2x00_nv_deselect(ha
);
241 qla2x00_write_nvram_word_tmo(struct qla_hw_data
*ha
, uint32_t addr
,
242 uint16_t data
, uint32_t tmo
)
247 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
251 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
252 qla2x00_nv_write(ha
, 0);
253 qla2x00_nv_write(ha
, 0);
255 for (word
= 0; word
< 8; word
++)
256 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
258 qla2x00_nv_deselect(ha
);
261 nv_cmd
= (addr
<< 16) | NV_WRITE_OP
;
264 for (count
= 0; count
< 27; count
++) {
266 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
268 qla2x00_nv_write(ha
, 0);
273 qla2x00_nv_deselect(ha
);
275 /* Wait for NVRAM to become ready */
276 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
277 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
280 word
= RD_REG_WORD(®
->nvram
);
282 ret
= QLA_FUNCTION_FAILED
;
285 } while ((word
& NVR_DATA_IN
) == 0);
287 qla2x00_nv_deselect(ha
);
290 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
291 for (count
= 0; count
< 10; count
++)
292 qla2x00_nv_write(ha
, 0);
294 qla2x00_nv_deselect(ha
);
300 * qla2x00_clear_nvram_protection() -
304 qla2x00_clear_nvram_protection(struct qla_hw_data
*ha
)
307 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
308 uint32_t word
, wait_cnt
;
309 uint16_t wprot
, wprot_old
;
311 /* Clear NVRAM write protection. */
312 ret
= QLA_FUNCTION_FAILED
;
314 wprot_old
= cpu_to_le16(qla2x00_get_nvram_word(ha
, ha
->nvram_base
));
315 stat
= qla2x00_write_nvram_word_tmo(ha
, ha
->nvram_base
,
316 __constant_cpu_to_le16(0x1234), 100000);
317 wprot
= cpu_to_le16(qla2x00_get_nvram_word(ha
, ha
->nvram_base
));
318 if (stat
!= QLA_SUCCESS
|| wprot
!= 0x1234) {
320 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
321 qla2x00_nv_write(ha
, 0);
322 qla2x00_nv_write(ha
, 0);
323 for (word
= 0; word
< 8; word
++)
324 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
326 qla2x00_nv_deselect(ha
);
328 /* Enable protection register. */
329 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
330 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
331 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
332 for (word
= 0; word
< 8; word
++)
333 qla2x00_nv_write(ha
, NVR_DATA_OUT
| NVR_PR_ENABLE
);
335 qla2x00_nv_deselect(ha
);
337 /* Clear protection register (ffff is cleared). */
338 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
339 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
340 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
341 for (word
= 0; word
< 8; word
++)
342 qla2x00_nv_write(ha
, NVR_DATA_OUT
| NVR_PR_ENABLE
);
344 qla2x00_nv_deselect(ha
);
346 /* Wait for NVRAM to become ready. */
347 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
348 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
349 wait_cnt
= NVR_WAIT_CNT
;
352 DEBUG9_10(qla_printk(KERN_WARNING
, ha
,
353 "NVRAM didn't go ready...\n"));
357 word
= RD_REG_WORD(®
->nvram
);
358 } while ((word
& NVR_DATA_IN
) == 0);
363 qla2x00_write_nvram_word(ha
, ha
->nvram_base
, wprot_old
);
369 qla2x00_set_nvram_protection(struct qla_hw_data
*ha
, int stat
)
371 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
372 uint32_t word
, wait_cnt
;
374 if (stat
!= QLA_SUCCESS
)
377 /* Set NVRAM write protection. */
379 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
380 qla2x00_nv_write(ha
, 0);
381 qla2x00_nv_write(ha
, 0);
382 for (word
= 0; word
< 8; word
++)
383 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
385 qla2x00_nv_deselect(ha
);
387 /* Enable protection register. */
388 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
389 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
390 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
391 for (word
= 0; word
< 8; word
++)
392 qla2x00_nv_write(ha
, NVR_DATA_OUT
| NVR_PR_ENABLE
);
394 qla2x00_nv_deselect(ha
);
396 /* Enable protection register. */
397 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
398 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
399 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
400 for (word
= 0; word
< 8; word
++)
401 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
403 qla2x00_nv_deselect(ha
);
405 /* Wait for NVRAM to become ready. */
406 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
407 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
408 wait_cnt
= NVR_WAIT_CNT
;
411 DEBUG9_10(qla_printk(KERN_WARNING
, ha
,
412 "NVRAM didn't go ready...\n"));
416 word
= RD_REG_WORD(®
->nvram
);
417 } while ((word
& NVR_DATA_IN
) == 0);
421 /*****************************************************************************/
422 /* Flash Manipulation Routines */
423 /*****************************************************************************/
425 #define OPTROM_BURST_SIZE 0x1000
426 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
428 static inline uint32_t
429 flash_conf_addr(struct qla_hw_data
*ha
, uint32_t faddr
)
431 return ha
->flash_conf_off
| faddr
;
434 static inline uint32_t
435 flash_data_addr(struct qla_hw_data
*ha
, uint32_t faddr
)
437 return ha
->flash_data_off
| faddr
;
440 static inline uint32_t
441 nvram_conf_addr(struct qla_hw_data
*ha
, uint32_t naddr
)
443 return ha
->nvram_conf_off
| naddr
;
446 static inline uint32_t
447 nvram_data_addr(struct qla_hw_data
*ha
, uint32_t naddr
)
449 return ha
->nvram_data_off
| naddr
;
453 qla24xx_read_flash_dword(struct qla_hw_data
*ha
, uint32_t addr
)
457 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
459 WRT_REG_DWORD(®
->flash_addr
, addr
& ~FARX_DATA_FLAG
);
460 /* Wait for READ cycle to complete. */
463 (RD_REG_DWORD(®
->flash_addr
) & FARX_DATA_FLAG
) == 0 &&
464 rval
== QLA_SUCCESS
; cnt
--) {
468 rval
= QLA_FUNCTION_TIMEOUT
;
472 /* TODO: What happens if we time out? */
474 if (rval
== QLA_SUCCESS
)
475 data
= RD_REG_DWORD(®
->flash_data
);
481 qla24xx_read_flash_data(scsi_qla_host_t
*vha
, uint32_t *dwptr
, uint32_t faddr
,
485 struct qla_hw_data
*ha
= vha
->hw
;
487 /* Dword reads to flash. */
488 for (i
= 0; i
< dwords
; i
++, faddr
++)
489 dwptr
[i
] = cpu_to_le32(qla24xx_read_flash_dword(ha
,
490 flash_data_addr(ha
, faddr
)));
496 qla24xx_write_flash_dword(struct qla_hw_data
*ha
, uint32_t addr
, uint32_t data
)
500 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
502 WRT_REG_DWORD(®
->flash_data
, data
);
503 RD_REG_DWORD(®
->flash_data
); /* PCI Posting. */
504 WRT_REG_DWORD(®
->flash_addr
, addr
| FARX_DATA_FLAG
);
505 /* Wait for Write cycle to complete. */
507 for (cnt
= 500000; (RD_REG_DWORD(®
->flash_addr
) & FARX_DATA_FLAG
) &&
508 rval
== QLA_SUCCESS
; cnt
--) {
512 rval
= QLA_FUNCTION_TIMEOUT
;
519 qla24xx_get_flash_manufacturer(struct qla_hw_data
*ha
, uint8_t *man_id
,
524 ids
= qla24xx_read_flash_dword(ha
, flash_conf_addr(ha
, 0x03ab));
526 *flash_id
= MSB(ids
);
528 /* Check if man_id and flash_id are valid. */
529 if (ids
!= 0xDEADDEAD && (*man_id
== 0 || *flash_id
== 0)) {
530 /* Read information using 0x9f opcode
531 * Device ID, Mfg ID would be read in the format:
532 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
533 * Example: ATMEL 0x00 01 45 1F
534 * Extract MFG and Dev ID from last two bytes.
536 ids
= qla24xx_read_flash_dword(ha
, flash_conf_addr(ha
, 0x009f));
538 *flash_id
= MSB(ids
);
543 qla2xxx_find_flt_start(scsi_qla_host_t
*vha
, uint32_t *start
)
545 const char *loc
, *locations
[] = { "DEF", "PCI" };
546 uint32_t pcihdr
, pcids
;
548 uint8_t *buf
, *bcode
, last_image
;
549 uint16_t cnt
, chksum
, *wptr
;
550 struct qla_flt_location
*fltl
;
551 struct qla_hw_data
*ha
= vha
->hw
;
552 struct req_que
*req
= ha
->req_q_map
[0];
555 * FLT-location structure resides after the last PCI region.
558 /* Begin with sane defaults. */
561 if (IS_QLA24XX_TYPE(ha
))
562 *start
= FA_FLASH_LAYOUT_ADDR_24
;
563 else if (IS_QLA25XX(ha
))
564 *start
= FA_FLASH_LAYOUT_ADDR
;
565 else if (IS_QLA81XX(ha
))
566 *start
= FA_FLASH_LAYOUT_ADDR_81
;
567 /* Begin with first PCI expansion ROM header. */
568 buf
= (uint8_t *)req
->ring
;
569 dcode
= (uint32_t *)req
->ring
;
573 /* Verify PCI expansion ROM header. */
574 qla24xx_read_flash_data(vha
, dcode
, pcihdr
>> 2, 0x20);
575 bcode
= buf
+ (pcihdr
% 4);
576 if (bcode
[0x0] != 0x55 || bcode
[0x1] != 0xaa)
579 /* Locate PCI data structure. */
580 pcids
= pcihdr
+ ((bcode
[0x19] << 8) | bcode
[0x18]);
581 qla24xx_read_flash_data(vha
, dcode
, pcids
>> 2, 0x20);
582 bcode
= buf
+ (pcihdr
% 4);
584 /* Validate signature of PCI data structure. */
585 if (bcode
[0x0] != 'P' || bcode
[0x1] != 'C' ||
586 bcode
[0x2] != 'I' || bcode
[0x3] != 'R')
589 last_image
= bcode
[0x15] & BIT_7
;
591 /* Locate next PCI expansion ROM. */
592 pcihdr
+= ((bcode
[0x11] << 8) | bcode
[0x10]) * 512;
593 } while (!last_image
);
595 /* Now verify FLT-location structure. */
596 fltl
= (struct qla_flt_location
*)req
->ring
;
597 qla24xx_read_flash_data(vha
, dcode
, pcihdr
>> 2,
598 sizeof(struct qla_flt_location
) >> 2);
599 if (fltl
->sig
[0] != 'Q' || fltl
->sig
[1] != 'F' ||
600 fltl
->sig
[2] != 'L' || fltl
->sig
[3] != 'T')
603 wptr
= (uint16_t *)req
->ring
;
604 cnt
= sizeof(struct qla_flt_location
) >> 1;
605 for (chksum
= 0; cnt
; cnt
--)
606 chksum
+= le16_to_cpu(*wptr
++);
608 qla_printk(KERN_ERR
, ha
,
609 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum
);
610 qla2x00_dump_buffer(buf
, sizeof(struct qla_flt_location
));
611 return QLA_FUNCTION_FAILED
;
614 /* Good data. Use specified location. */
616 *start
= (le16_to_cpu(fltl
->start_hi
) << 16 |
617 le16_to_cpu(fltl
->start_lo
)) >> 2;
619 DEBUG2(qla_printk(KERN_DEBUG
, ha
, "FLTL[%s] = 0x%x.\n", loc
, *start
));
624 qla2xxx_get_flt_info(scsi_qla_host_t
*vha
, uint32_t flt_addr
)
626 const char *loc
, *locations
[] = { "DEF", "FLT" };
627 const uint32_t def_fw
[] =
628 { FA_RISC_CODE_ADDR
, FA_RISC_CODE_ADDR
, FA_RISC_CODE_ADDR_81
};
629 const uint32_t def_boot
[] =
630 { FA_BOOT_CODE_ADDR
, FA_BOOT_CODE_ADDR
, FA_BOOT_CODE_ADDR_81
};
631 const uint32_t def_vpd_nvram
[] =
632 { FA_VPD_NVRAM_ADDR
, FA_VPD_NVRAM_ADDR
, FA_VPD_NVRAM_ADDR_81
};
633 const uint32_t def_vpd0
[] =
634 { 0, 0, FA_VPD0_ADDR_81
};
635 const uint32_t def_vpd1
[] =
636 { 0, 0, FA_VPD1_ADDR_81
};
637 const uint32_t def_nvram0
[] =
638 { 0, 0, FA_NVRAM0_ADDR_81
};
639 const uint32_t def_nvram1
[] =
640 { 0, 0, FA_NVRAM1_ADDR_81
};
641 const uint32_t def_fdt
[] =
642 { FA_FLASH_DESCR_ADDR_24
, FA_FLASH_DESCR_ADDR
,
643 FA_FLASH_DESCR_ADDR_81
};
644 const uint32_t def_npiv_conf0
[] =
645 { FA_NPIV_CONF0_ADDR_24
, FA_NPIV_CONF0_ADDR
,
646 FA_NPIV_CONF0_ADDR_81
};
647 const uint32_t def_npiv_conf1
[] =
648 { FA_NPIV_CONF1_ADDR_24
, FA_NPIV_CONF1_ADDR
,
649 FA_NPIV_CONF1_ADDR_81
};
652 uint16_t cnt
, chksum
;
654 struct qla_flt_header
*flt
;
655 struct qla_flt_region
*region
;
656 struct qla_hw_data
*ha
= vha
->hw
;
657 struct req_que
*req
= ha
->req_q_map
[0];
659 ha
->flt_region_flt
= flt_addr
;
660 wptr
= (uint16_t *)req
->ring
;
661 flt
= (struct qla_flt_header
*)req
->ring
;
662 region
= (struct qla_flt_region
*)&flt
[1];
663 ha
->isp_ops
->read_optrom(vha
, (uint8_t *)req
->ring
,
664 flt_addr
<< 2, OPTROM_BURST_SIZE
);
665 if (*wptr
== __constant_cpu_to_le16(0xffff))
667 if (flt
->version
!= __constant_cpu_to_le16(1)) {
668 DEBUG2(qla_printk(KERN_INFO
, ha
, "Unsupported FLT detected: "
669 "version=0x%x length=0x%x checksum=0x%x.\n",
670 le16_to_cpu(flt
->version
), le16_to_cpu(flt
->length
),
671 le16_to_cpu(flt
->checksum
)));
675 cnt
= (sizeof(struct qla_flt_header
) + le16_to_cpu(flt
->length
)) >> 1;
676 for (chksum
= 0; cnt
; cnt
--)
677 chksum
+= le16_to_cpu(*wptr
++);
679 DEBUG2(qla_printk(KERN_INFO
, ha
, "Inconsistent FLT detected: "
680 "version=0x%x length=0x%x checksum=0x%x.\n",
681 le16_to_cpu(flt
->version
), le16_to_cpu(flt
->length
),
687 cnt
= le16_to_cpu(flt
->length
) / sizeof(struct qla_flt_region
);
688 for ( ; cnt
; cnt
--, region
++) {
689 /* Store addresses as DWORD offsets. */
690 start
= le32_to_cpu(region
->start
) >> 2;
692 DEBUG3(qla_printk(KERN_DEBUG
, ha
, "FLT[%02x]: start=0x%x "
693 "end=0x%x size=0x%x.\n", le32_to_cpu(region
->code
), start
,
694 le32_to_cpu(region
->end
) >> 2, le32_to_cpu(region
->size
)));
696 switch (le32_to_cpu(region
->code
) & 0xff) {
698 ha
->flt_region_fw
= start
;
700 case FLT_REG_BOOT_CODE
:
701 ha
->flt_region_boot
= start
;
704 ha
->flt_region_vpd_nvram
= start
;
706 ha
->flt_region_vpd
= start
;
709 if (!ha
->flags
.port0
)
710 ha
->flt_region_vpd
= start
;
712 case FLT_REG_NVRAM_0
:
714 ha
->flt_region_nvram
= start
;
716 case FLT_REG_NVRAM_1
:
717 if (!ha
->flags
.port0
)
718 ha
->flt_region_nvram
= start
;
721 ha
->flt_region_fdt
= start
;
723 case FLT_REG_NPIV_CONF_0
:
725 ha
->flt_region_npiv_conf
= start
;
727 case FLT_REG_NPIV_CONF_1
:
728 if (!ha
->flags
.port0
)
729 ha
->flt_region_npiv_conf
= start
;
736 /* Use hardcoded defaults. */
739 if (IS_QLA24XX_TYPE(ha
))
741 else if (IS_QLA25XX(ha
))
743 else if (IS_QLA81XX(ha
))
745 ha
->flt_region_fw
= def_fw
[def
];
746 ha
->flt_region_boot
= def_boot
[def
];
747 ha
->flt_region_vpd_nvram
= def_vpd_nvram
[def
];
748 ha
->flt_region_vpd
= ha
->flags
.port0
?
749 def_vpd0
[def
]: def_vpd1
[def
];
750 ha
->flt_region_nvram
= ha
->flags
.port0
?
751 def_nvram0
[def
]: def_nvram1
[def
];
752 ha
->flt_region_fdt
= def_fdt
[def
];
753 ha
->flt_region_npiv_conf
= ha
->flags
.port0
?
754 def_npiv_conf0
[def
]: def_npiv_conf1
[def
];
756 DEBUG2(qla_printk(KERN_DEBUG
, ha
, "FLT[%s]: boot=0x%x fw=0x%x "
757 "vpd_nvram=0x%x vpd=0x%x nvram=0x%x fdt=0x%x flt=0x%x "
758 "npiv=0x%x.\n", loc
, ha
->flt_region_boot
, ha
->flt_region_fw
,
759 ha
->flt_region_vpd_nvram
, ha
->flt_region_vpd
, ha
->flt_region_nvram
,
760 ha
->flt_region_fdt
, ha
->flt_region_flt
, ha
->flt_region_npiv_conf
));
764 qla2xxx_get_fdt_info(scsi_qla_host_t
*vha
)
766 #define FLASH_BLK_SIZE_4K 0x1000
767 #define FLASH_BLK_SIZE_32K 0x8000
768 #define FLASH_BLK_SIZE_64K 0x10000
769 const char *loc
, *locations
[] = { "MID", "FDT" };
770 uint16_t cnt
, chksum
;
772 struct qla_fdt_layout
*fdt
;
773 uint8_t man_id
, flash_id
;
775 struct qla_hw_data
*ha
= vha
->hw
;
776 struct req_que
*req
= ha
->req_q_map
[0];
778 wptr
= (uint16_t *)req
->ring
;
779 fdt
= (struct qla_fdt_layout
*)req
->ring
;
780 ha
->isp_ops
->read_optrom(vha
, (uint8_t *)req
->ring
,
781 ha
->flt_region_fdt
<< 2, OPTROM_BURST_SIZE
);
782 if (*wptr
== __constant_cpu_to_le16(0xffff))
784 if (fdt
->sig
[0] != 'Q' || fdt
->sig
[1] != 'L' || fdt
->sig
[2] != 'I' ||
788 for (cnt
= 0, chksum
= 0; cnt
< sizeof(struct qla_fdt_layout
) >> 1;
790 chksum
+= le16_to_cpu(*wptr
++);
792 DEBUG2(qla_printk(KERN_INFO
, ha
, "Inconsistent FDT detected: "
793 "checksum=0x%x id=%c version=0x%x.\n", chksum
, fdt
->sig
[0],
794 le16_to_cpu(fdt
->version
)));
795 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt
, sizeof(*fdt
)));
800 mid
= le16_to_cpu(fdt
->man_id
);
801 fid
= le16_to_cpu(fdt
->id
);
802 ha
->fdt_wrt_disable
= fdt
->wrt_disable_bits
;
803 ha
->fdt_erase_cmd
= flash_conf_addr(ha
, 0x0300 | fdt
->erase_cmd
);
804 ha
->fdt_block_size
= le32_to_cpu(fdt
->block_size
);
805 if (fdt
->unprotect_sec_cmd
) {
806 ha
->fdt_unprotect_sec_cmd
= flash_conf_addr(ha
, 0x0300 |
807 fdt
->unprotect_sec_cmd
);
808 ha
->fdt_protect_sec_cmd
= fdt
->protect_sec_cmd
?
809 flash_conf_addr(ha
, 0x0300 | fdt
->protect_sec_cmd
):
810 flash_conf_addr(ha
, 0x0336);
815 qla24xx_get_flash_manufacturer(ha
, &man_id
, &flash_id
);
818 ha
->fdt_wrt_disable
= 0x9c;
819 ha
->fdt_erase_cmd
= flash_conf_addr(ha
, 0x03d8);
821 case 0xbf: /* STT flash. */
822 if (flash_id
== 0x8e)
823 ha
->fdt_block_size
= FLASH_BLK_SIZE_64K
;
825 ha
->fdt_block_size
= FLASH_BLK_SIZE_32K
;
827 if (flash_id
== 0x80)
828 ha
->fdt_erase_cmd
= flash_conf_addr(ha
, 0x0352);
830 case 0x13: /* ST M25P80. */
831 ha
->fdt_block_size
= FLASH_BLK_SIZE_64K
;
833 case 0x1f: /* Atmel 26DF081A. */
834 ha
->fdt_block_size
= FLASH_BLK_SIZE_4K
;
835 ha
->fdt_erase_cmd
= flash_conf_addr(ha
, 0x0320);
836 ha
->fdt_unprotect_sec_cmd
= flash_conf_addr(ha
, 0x0339);
837 ha
->fdt_protect_sec_cmd
= flash_conf_addr(ha
, 0x0336);
840 /* Default to 64 kb sector size. */
841 ha
->fdt_block_size
= FLASH_BLK_SIZE_64K
;
845 DEBUG2(qla_printk(KERN_DEBUG
, ha
, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
846 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc
, mid
, fid
,
847 ha
->fdt_erase_cmd
, ha
->fdt_protect_sec_cmd
,
848 ha
->fdt_unprotect_sec_cmd
, ha
->fdt_wrt_disable
,
849 ha
->fdt_block_size
));
853 qla2xxx_get_flash_info(scsi_qla_host_t
*vha
)
857 struct qla_hw_data
*ha
= vha
->hw
;
859 if (!IS_QLA24XX_TYPE(ha
) && !IS_QLA25XX(ha
) && !IS_QLA81XX(ha
))
862 ret
= qla2xxx_find_flt_start(vha
, &flt_addr
);
863 if (ret
!= QLA_SUCCESS
)
866 qla2xxx_get_flt_info(vha
, flt_addr
);
867 qla2xxx_get_fdt_info(vha
);
873 qla2xxx_flash_npiv_conf(scsi_qla_host_t
*vha
)
875 #define NPIV_CONFIG_SIZE (16*1024)
878 uint16_t cnt
, chksum
;
880 struct qla_npiv_header hdr
;
881 struct qla_npiv_entry
*entry
;
882 struct qla_hw_data
*ha
= vha
->hw
;
884 if (!IS_QLA24XX_TYPE(ha
) && !IS_QLA25XX(ha
) && !IS_QLA81XX(ha
))
887 ha
->isp_ops
->read_optrom(vha
, (uint8_t *)&hdr
,
888 ha
->flt_region_npiv_conf
<< 2, sizeof(struct qla_npiv_header
));
889 if (hdr
.version
== __constant_cpu_to_le16(0xffff))
891 if (hdr
.version
!= __constant_cpu_to_le16(1)) {
892 DEBUG2(qla_printk(KERN_INFO
, ha
, "Unsupported NPIV-Config "
893 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
894 le16_to_cpu(hdr
.version
), le16_to_cpu(hdr
.entries
),
895 le16_to_cpu(hdr
.checksum
)));
899 data
= kmalloc(NPIV_CONFIG_SIZE
, GFP_KERNEL
);
901 DEBUG2(qla_printk(KERN_INFO
, ha
, "NPIV-Config: Unable to "
902 "allocate memory.\n"));
906 ha
->isp_ops
->read_optrom(vha
, (uint8_t *)data
,
907 ha
->flt_region_npiv_conf
<< 2, NPIV_CONFIG_SIZE
);
909 cnt
= (sizeof(struct qla_npiv_header
) + le16_to_cpu(hdr
.entries
) *
910 sizeof(struct qla_npiv_entry
)) >> 1;
911 for (wptr
= data
, chksum
= 0; cnt
; cnt
--)
912 chksum
+= le16_to_cpu(*wptr
++);
914 DEBUG2(qla_printk(KERN_INFO
, ha
, "Inconsistent NPIV-Config "
915 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
916 le16_to_cpu(hdr
.version
), le16_to_cpu(hdr
.entries
),
921 entry
= data
+ sizeof(struct qla_npiv_header
);
922 cnt
= le16_to_cpu(hdr
.entries
);
923 for (i
= 0; cnt
; cnt
--, entry
++, i
++) {
925 struct fc_vport_identifiers vid
;
926 struct fc_vport
*vport
;
928 memcpy(&ha
->npiv_info
[i
], entry
, sizeof(struct qla_npiv_entry
));
930 flags
= le16_to_cpu(entry
->flags
);
933 if ((flags
& BIT_0
) == 0)
936 memset(&vid
, 0, sizeof(vid
));
937 vid
.roles
= FC_PORT_ROLE_FCP_INITIATOR
;
938 vid
.vport_type
= FC_PORTTYPE_NPIV
;
940 vid
.port_name
= wwn_to_u64(entry
->port_name
);
941 vid
.node_name
= wwn_to_u64(entry
->node_name
);
943 DEBUG2(qla_printk(KERN_INFO
, ha
, "NPIV[%02x]: wwpn=%llx "
944 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt
,
945 vid
.port_name
, vid
.node_name
, le16_to_cpu(entry
->vf_id
),
946 entry
->q_qos
, entry
->f_qos
));
948 if (i
< QLA_PRECONFIG_VPORTS
) {
949 vport
= fc_vport_create(vha
->host
, 0, &vid
);
951 qla_printk(KERN_INFO
, ha
,
952 "NPIV-Config: Failed to create vport [%02x]: "
953 "wwpn=%llx wwnn=%llx.\n", cnt
,
954 vid
.port_name
, vid
.node_name
);
962 qla24xx_unprotect_flash(scsi_qla_host_t
*vha
)
964 struct qla_hw_data
*ha
= vha
->hw
;
965 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
967 if (ha
->flags
.fac_supported
)
968 return qla81xx_fac_do_write_enable(vha
, 1);
970 /* Enable flash write. */
971 WRT_REG_DWORD(®
->ctrl_status
,
972 RD_REG_DWORD(®
->ctrl_status
) | CSRX_FLASH_ENABLE
);
973 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
975 if (!ha
->fdt_wrt_disable
)
978 /* Disable flash write-protection, first clear SR protection bit */
979 qla24xx_write_flash_dword(ha
, flash_conf_addr(ha
, 0x101), 0);
980 /* Then write zero again to clear remaining SR bits.*/
981 qla24xx_write_flash_dword(ha
, flash_conf_addr(ha
, 0x101), 0);
987 qla24xx_protect_flash(scsi_qla_host_t
*vha
)
990 struct qla_hw_data
*ha
= vha
->hw
;
991 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
993 if (ha
->flags
.fac_supported
)
994 return qla81xx_fac_do_write_enable(vha
, 0);
996 if (!ha
->fdt_wrt_disable
)
997 goto skip_wrt_protect
;
999 /* Enable flash write-protection and wait for completion. */
1000 qla24xx_write_flash_dword(ha
, flash_conf_addr(ha
, 0x101),
1001 ha
->fdt_wrt_disable
);
1002 for (cnt
= 300; cnt
&&
1003 qla24xx_read_flash_dword(ha
, flash_conf_addr(ha
, 0x005)) & BIT_0
;
1009 /* Disable flash write. */
1010 WRT_REG_DWORD(®
->ctrl_status
,
1011 RD_REG_DWORD(®
->ctrl_status
) & ~CSRX_FLASH_ENABLE
);
1012 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
1018 qla24xx_erase_sector(scsi_qla_host_t
*vha
, uint32_t fdata
)
1020 struct qla_hw_data
*ha
= vha
->hw
;
1021 uint32_t start
, finish
;
1023 if (ha
->flags
.fac_supported
) {
1025 finish
= start
+ (ha
->fdt_block_size
>> 2) - 1;
1026 return qla81xx_fac_erase_sector(vha
, flash_data_addr(ha
,
1027 start
), flash_data_addr(ha
, finish
));
1030 return qla24xx_write_flash_dword(ha
, ha
->fdt_erase_cmd
,
1031 (fdata
& 0xff00) | ((fdata
<< 16) & 0xff0000) |
1032 ((fdata
>> 16) & 0xff));
1036 qla24xx_write_flash_data(scsi_qla_host_t
*vha
, uint32_t *dwptr
, uint32_t faddr
,
1041 uint32_t sec_mask
, rest_addr
;
1043 dma_addr_t optrom_dma
;
1044 void *optrom
= NULL
;
1045 struct qla_hw_data
*ha
= vha
->hw
;
1047 /* Prepare burst-capable write on supported ISPs. */
1048 if ((IS_QLA25XX(ha
) || IS_QLA81XX(ha
)) && !(faddr
& 0xfff) &&
1049 dwords
> OPTROM_BURST_DWORDS
) {
1050 optrom
= dma_alloc_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
,
1051 &optrom_dma
, GFP_KERNEL
);
1053 qla_printk(KERN_DEBUG
, ha
,
1054 "Unable to allocate memory for optrom burst write "
1055 "(%x KB).\n", OPTROM_BURST_SIZE
/ 1024);
1059 rest_addr
= (ha
->fdt_block_size
>> 2) - 1;
1060 sec_mask
= ~rest_addr
;
1062 ret
= qla24xx_unprotect_flash(vha
);
1063 if (ret
!= QLA_SUCCESS
) {
1064 qla_printk(KERN_WARNING
, ha
,
1065 "Unable to unprotect flash for update.\n");
1069 for (liter
= 0; liter
< dwords
; liter
++, faddr
++, dwptr
++) {
1070 fdata
= (faddr
& sec_mask
) << 2;
1072 /* Are we at the beginning of a sector? */
1073 if ((faddr
& rest_addr
) == 0) {
1074 /* Do sector unprotect. */
1075 if (ha
->fdt_unprotect_sec_cmd
)
1076 qla24xx_write_flash_dword(ha
,
1077 ha
->fdt_unprotect_sec_cmd
,
1078 (fdata
& 0xff00) | ((fdata
<< 16) &
1079 0xff0000) | ((fdata
>> 16) & 0xff));
1080 ret
= qla24xx_erase_sector(vha
, fdata
);
1081 if (ret
!= QLA_SUCCESS
) {
1082 DEBUG9(qla_printk(KERN_WARNING
, ha
,
1083 "Unable to erase sector: address=%x.\n",
1089 /* Go with burst-write. */
1090 if (optrom
&& (liter
+ OPTROM_BURST_DWORDS
) <= dwords
) {
1091 /* Copy data to DMA'ble buffer. */
1092 memcpy(optrom
, dwptr
, OPTROM_BURST_SIZE
);
1094 ret
= qla2x00_load_ram(vha
, optrom_dma
,
1095 flash_data_addr(ha
, faddr
),
1096 OPTROM_BURST_DWORDS
);
1097 if (ret
!= QLA_SUCCESS
) {
1098 qla_printk(KERN_WARNING
, ha
,
1099 "Unable to burst-write optrom segment "
1100 "(%x/%x/%llx).\n", ret
,
1101 flash_data_addr(ha
, faddr
),
1102 (unsigned long long)optrom_dma
);
1103 qla_printk(KERN_WARNING
, ha
,
1104 "Reverting to slow-write.\n");
1106 dma_free_coherent(&ha
->pdev
->dev
,
1107 OPTROM_BURST_SIZE
, optrom
, optrom_dma
);
1110 liter
+= OPTROM_BURST_DWORDS
- 1;
1111 faddr
+= OPTROM_BURST_DWORDS
- 1;
1112 dwptr
+= OPTROM_BURST_DWORDS
- 1;
1117 ret
= qla24xx_write_flash_dword(ha
,
1118 flash_data_addr(ha
, faddr
), cpu_to_le32(*dwptr
));
1119 if (ret
!= QLA_SUCCESS
) {
1120 DEBUG9(printk("%s(%ld) Unable to program flash "
1121 "address=%x data=%x.\n", __func__
,
1122 vha
->host_no
, faddr
, *dwptr
));
1126 /* Do sector protect. */
1127 if (ha
->fdt_unprotect_sec_cmd
&&
1128 ((faddr
& rest_addr
) == rest_addr
))
1129 qla24xx_write_flash_dword(ha
,
1130 ha
->fdt_protect_sec_cmd
,
1131 (fdata
& 0xff00) | ((fdata
<< 16) &
1132 0xff0000) | ((fdata
>> 16) & 0xff));
1135 ret
= qla24xx_protect_flash(vha
);
1136 if (ret
!= QLA_SUCCESS
)
1137 qla_printk(KERN_WARNING
, ha
,
1138 "Unable to protect flash after update.\n");
1141 dma_free_coherent(&ha
->pdev
->dev
,
1142 OPTROM_BURST_SIZE
, optrom
, optrom_dma
);
1148 qla2x00_read_nvram_data(scsi_qla_host_t
*vha
, uint8_t *buf
, uint32_t naddr
,
1153 struct qla_hw_data
*ha
= vha
->hw
;
1155 /* Word reads to NVRAM via registers. */
1156 wptr
= (uint16_t *)buf
;
1157 qla2x00_lock_nvram_access(ha
);
1158 for (i
= 0; i
< bytes
>> 1; i
++, naddr
++)
1159 wptr
[i
] = cpu_to_le16(qla2x00_get_nvram_word(ha
,
1161 qla2x00_unlock_nvram_access(ha
);
1167 qla24xx_read_nvram_data(scsi_qla_host_t
*vha
, uint8_t *buf
, uint32_t naddr
,
1172 struct qla_hw_data
*ha
= vha
->hw
;
1174 /* Dword reads to flash. */
1175 dwptr
= (uint32_t *)buf
;
1176 for (i
= 0; i
< bytes
>> 2; i
++, naddr
++)
1177 dwptr
[i
] = cpu_to_le32(qla24xx_read_flash_dword(ha
,
1178 nvram_data_addr(ha
, naddr
)));
1184 qla2x00_write_nvram_data(scsi_qla_host_t
*vha
, uint8_t *buf
, uint32_t naddr
,
1190 unsigned long flags
;
1191 struct qla_hw_data
*ha
= vha
->hw
;
1195 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1196 qla2x00_lock_nvram_access(ha
);
1198 /* Disable NVRAM write-protection. */
1199 stat
= qla2x00_clear_nvram_protection(ha
);
1201 wptr
= (uint16_t *)buf
;
1202 for (i
= 0; i
< bytes
>> 1; i
++, naddr
++) {
1203 qla2x00_write_nvram_word(ha
, naddr
,
1204 cpu_to_le16(*wptr
));
1208 /* Enable NVRAM write-protection. */
1209 qla2x00_set_nvram_protection(ha
, stat
);
1211 qla2x00_unlock_nvram_access(ha
);
1212 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1218 qla24xx_write_nvram_data(scsi_qla_host_t
*vha
, uint8_t *buf
, uint32_t naddr
,
1224 struct qla_hw_data
*ha
= vha
->hw
;
1225 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1229 /* Enable flash write. */
1230 WRT_REG_DWORD(®
->ctrl_status
,
1231 RD_REG_DWORD(®
->ctrl_status
) | CSRX_FLASH_ENABLE
);
1232 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
1234 /* Disable NVRAM write-protection. */
1235 qla24xx_write_flash_dword(ha
, nvram_conf_addr(ha
, 0x101), 0);
1236 qla24xx_write_flash_dword(ha
, nvram_conf_addr(ha
, 0x101), 0);
1238 /* Dword writes to flash. */
1239 dwptr
= (uint32_t *)buf
;
1240 for (i
= 0; i
< bytes
>> 2; i
++, naddr
++, dwptr
++) {
1241 ret
= qla24xx_write_flash_dword(ha
,
1242 nvram_data_addr(ha
, naddr
), cpu_to_le32(*dwptr
));
1243 if (ret
!= QLA_SUCCESS
) {
1244 DEBUG9(qla_printk(KERN_WARNING
, ha
,
1245 "Unable to program nvram address=%x data=%x.\n",
1251 /* Enable NVRAM write-protection. */
1252 qla24xx_write_flash_dword(ha
, nvram_conf_addr(ha
, 0x101), 0x8c);
1254 /* Disable flash write. */
1255 WRT_REG_DWORD(®
->ctrl_status
,
1256 RD_REG_DWORD(®
->ctrl_status
) & ~CSRX_FLASH_ENABLE
);
1257 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
1263 qla25xx_read_nvram_data(scsi_qla_host_t
*vha
, uint8_t *buf
, uint32_t naddr
,
1268 struct qla_hw_data
*ha
= vha
->hw
;
1270 /* Dword reads to flash. */
1271 dwptr
= (uint32_t *)buf
;
1272 for (i
= 0; i
< bytes
>> 2; i
++, naddr
++)
1273 dwptr
[i
] = cpu_to_le32(qla24xx_read_flash_dword(ha
,
1274 flash_data_addr(ha
, ha
->flt_region_vpd_nvram
| naddr
)));
1280 qla25xx_write_nvram_data(scsi_qla_host_t
*vha
, uint8_t *buf
, uint32_t naddr
,
1283 struct qla_hw_data
*ha
= vha
->hw
;
1284 #define RMW_BUFFER_SIZE (64 * 1024)
1287 dbuf
= vmalloc(RMW_BUFFER_SIZE
);
1289 return QLA_MEMORY_ALLOC_FAILED
;
1290 ha
->isp_ops
->read_optrom(vha
, dbuf
, ha
->flt_region_vpd_nvram
<< 2,
1292 memcpy(dbuf
+ (naddr
<< 2), buf
, bytes
);
1293 ha
->isp_ops
->write_optrom(vha
, dbuf
, ha
->flt_region_vpd_nvram
<< 2,
1301 qla2x00_flip_colors(struct qla_hw_data
*ha
, uint16_t *pflags
)
1303 if (IS_QLA2322(ha
)) {
1304 /* Flip all colors. */
1305 if (ha
->beacon_color_state
== QLA_LED_ALL_ON
) {
1307 ha
->beacon_color_state
= 0;
1308 *pflags
= GPIO_LED_ALL_OFF
;
1311 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
1312 *pflags
= GPIO_LED_RGA_ON
;
1315 /* Flip green led only. */
1316 if (ha
->beacon_color_state
== QLA_LED_GRN_ON
) {
1318 ha
->beacon_color_state
= 0;
1319 *pflags
= GPIO_LED_GREEN_OFF_AMBER_OFF
;
1322 ha
->beacon_color_state
= QLA_LED_GRN_ON
;
1323 *pflags
= GPIO_LED_GREEN_ON_AMBER_OFF
;
1328 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1331 qla2x00_beacon_blink(struct scsi_qla_host
*vha
)
1333 uint16_t gpio_enable
;
1335 uint16_t led_color
= 0;
1336 unsigned long flags
;
1337 struct qla_hw_data
*ha
= vha
->hw
;
1338 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1340 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1342 /* Save the Original GPIOE. */
1343 if (ha
->pio_address
) {
1344 gpio_enable
= RD_REG_WORD_PIO(PIO_REG(ha
, gpioe
));
1345 gpio_data
= RD_REG_WORD_PIO(PIO_REG(ha
, gpiod
));
1347 gpio_enable
= RD_REG_WORD(®
->gpioe
);
1348 gpio_data
= RD_REG_WORD(®
->gpiod
);
1351 /* Set the modified gpio_enable values */
1352 gpio_enable
|= GPIO_LED_MASK
;
1354 if (ha
->pio_address
) {
1355 WRT_REG_WORD_PIO(PIO_REG(ha
, gpioe
), gpio_enable
);
1357 WRT_REG_WORD(®
->gpioe
, gpio_enable
);
1358 RD_REG_WORD(®
->gpioe
);
1361 qla2x00_flip_colors(ha
, &led_color
);
1363 /* Clear out any previously set LED color. */
1364 gpio_data
&= ~GPIO_LED_MASK
;
1366 /* Set the new input LED color to GPIOD. */
1367 gpio_data
|= led_color
;
1369 /* Set the modified gpio_data values */
1370 if (ha
->pio_address
) {
1371 WRT_REG_WORD_PIO(PIO_REG(ha
, gpiod
), gpio_data
);
1373 WRT_REG_WORD(®
->gpiod
, gpio_data
);
1374 RD_REG_WORD(®
->gpiod
);
1377 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1381 qla2x00_beacon_on(struct scsi_qla_host
*vha
)
1383 uint16_t gpio_enable
;
1385 unsigned long flags
;
1386 struct qla_hw_data
*ha
= vha
->hw
;
1387 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1389 ha
->fw_options
[1] &= ~FO1_SET_EMPHASIS_SWING
;
1390 ha
->fw_options
[1] |= FO1_DISABLE_GPIO6_7
;
1392 if (qla2x00_set_fw_options(vha
, ha
->fw_options
) != QLA_SUCCESS
) {
1393 qla_printk(KERN_WARNING
, ha
,
1394 "Unable to update fw options (beacon on).\n");
1395 return QLA_FUNCTION_FAILED
;
1398 /* Turn off LEDs. */
1399 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1400 if (ha
->pio_address
) {
1401 gpio_enable
= RD_REG_WORD_PIO(PIO_REG(ha
, gpioe
));
1402 gpio_data
= RD_REG_WORD_PIO(PIO_REG(ha
, gpiod
));
1404 gpio_enable
= RD_REG_WORD(®
->gpioe
);
1405 gpio_data
= RD_REG_WORD(®
->gpiod
);
1407 gpio_enable
|= GPIO_LED_MASK
;
1409 /* Set the modified gpio_enable values. */
1410 if (ha
->pio_address
) {
1411 WRT_REG_WORD_PIO(PIO_REG(ha
, gpioe
), gpio_enable
);
1413 WRT_REG_WORD(®
->gpioe
, gpio_enable
);
1414 RD_REG_WORD(®
->gpioe
);
1417 /* Clear out previously set LED colour. */
1418 gpio_data
&= ~GPIO_LED_MASK
;
1419 if (ha
->pio_address
) {
1420 WRT_REG_WORD_PIO(PIO_REG(ha
, gpiod
), gpio_data
);
1422 WRT_REG_WORD(®
->gpiod
, gpio_data
);
1423 RD_REG_WORD(®
->gpiod
);
1425 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1428 * Let the per HBA timer kick off the blinking process based on
1429 * the following flags. No need to do anything else now.
1431 ha
->beacon_blink_led
= 1;
1432 ha
->beacon_color_state
= 0;
1438 qla2x00_beacon_off(struct scsi_qla_host
*vha
)
1440 int rval
= QLA_SUCCESS
;
1441 struct qla_hw_data
*ha
= vha
->hw
;
1443 ha
->beacon_blink_led
= 0;
1445 /* Set the on flag so when it gets flipped it will be off. */
1447 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
1449 ha
->beacon_color_state
= QLA_LED_GRN_ON
;
1451 ha
->isp_ops
->beacon_blink(vha
); /* This turns green LED off */
1453 ha
->fw_options
[1] &= ~FO1_SET_EMPHASIS_SWING
;
1454 ha
->fw_options
[1] &= ~FO1_DISABLE_GPIO6_7
;
1456 rval
= qla2x00_set_fw_options(vha
, ha
->fw_options
);
1457 if (rval
!= QLA_SUCCESS
)
1458 qla_printk(KERN_WARNING
, ha
,
1459 "Unable to update fw options (beacon off).\n");
1465 qla24xx_flip_colors(struct qla_hw_data
*ha
, uint16_t *pflags
)
1467 /* Flip all colors. */
1468 if (ha
->beacon_color_state
== QLA_LED_ALL_ON
) {
1470 ha
->beacon_color_state
= 0;
1474 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
1475 *pflags
= GPDX_LED_YELLOW_ON
| GPDX_LED_AMBER_ON
;
1480 qla24xx_beacon_blink(struct scsi_qla_host
*vha
)
1482 uint16_t led_color
= 0;
1484 unsigned long flags
;
1485 struct qla_hw_data
*ha
= vha
->hw
;
1486 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1488 /* Save the Original GPIOD. */
1489 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1490 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1492 /* Enable the gpio_data reg for update. */
1493 gpio_data
|= GPDX_LED_UPDATE_MASK
;
1495 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
1496 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1498 /* Set the color bits. */
1499 qla24xx_flip_colors(ha
, &led_color
);
1501 /* Clear out any previously set LED color. */
1502 gpio_data
&= ~GPDX_LED_COLOR_MASK
;
1504 /* Set the new input LED color to GPIOD. */
1505 gpio_data
|= led_color
;
1507 /* Set the modified gpio_data values. */
1508 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
1509 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1510 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1514 qla24xx_beacon_on(struct scsi_qla_host
*vha
)
1517 unsigned long flags
;
1518 struct qla_hw_data
*ha
= vha
->hw
;
1519 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1521 if (ha
->beacon_blink_led
== 0) {
1522 /* Enable firmware for update */
1523 ha
->fw_options
[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL
;
1525 if (qla2x00_set_fw_options(vha
, ha
->fw_options
) != QLA_SUCCESS
)
1526 return QLA_FUNCTION_FAILED
;
1528 if (qla2x00_get_fw_options(vha
, ha
->fw_options
) !=
1530 qla_printk(KERN_WARNING
, ha
,
1531 "Unable to update fw options (beacon on).\n");
1532 return QLA_FUNCTION_FAILED
;
1535 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1536 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1538 /* Enable the gpio_data reg for update. */
1539 gpio_data
|= GPDX_LED_UPDATE_MASK
;
1540 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
1541 RD_REG_DWORD(®
->gpiod
);
1543 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1546 /* So all colors blink together. */
1547 ha
->beacon_color_state
= 0;
1549 /* Let the per HBA timer kick off the blinking process. */
1550 ha
->beacon_blink_led
= 1;
1556 qla24xx_beacon_off(struct scsi_qla_host
*vha
)
1559 unsigned long flags
;
1560 struct qla_hw_data
*ha
= vha
->hw
;
1561 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1563 ha
->beacon_blink_led
= 0;
1564 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
1566 ha
->isp_ops
->beacon_blink(vha
); /* Will flip to all off. */
1568 /* Give control back to firmware. */
1569 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1570 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1572 /* Disable the gpio_data reg for update. */
1573 gpio_data
&= ~GPDX_LED_UPDATE_MASK
;
1574 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
1575 RD_REG_DWORD(®
->gpiod
);
1576 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1578 ha
->fw_options
[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL
;
1580 if (qla2x00_set_fw_options(vha
, ha
->fw_options
) != QLA_SUCCESS
) {
1581 qla_printk(KERN_WARNING
, ha
,
1582 "Unable to update fw options (beacon off).\n");
1583 return QLA_FUNCTION_FAILED
;
1586 if (qla2x00_get_fw_options(vha
, ha
->fw_options
) != QLA_SUCCESS
) {
1587 qla_printk(KERN_WARNING
, ha
,
1588 "Unable to get fw options (beacon off).\n");
1589 return QLA_FUNCTION_FAILED
;
1597 * Flash support routines
1601 * qla2x00_flash_enable() - Setup flash for reading and writing.
1605 qla2x00_flash_enable(struct qla_hw_data
*ha
)
1608 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1610 data
= RD_REG_WORD(®
->ctrl_status
);
1611 data
|= CSR_FLASH_ENABLE
;
1612 WRT_REG_WORD(®
->ctrl_status
, data
);
1613 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1617 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1621 qla2x00_flash_disable(struct qla_hw_data
*ha
)
1624 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1626 data
= RD_REG_WORD(®
->ctrl_status
);
1627 data
&= ~(CSR_FLASH_ENABLE
);
1628 WRT_REG_WORD(®
->ctrl_status
, data
);
1629 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1633 * qla2x00_read_flash_byte() - Reads a byte from flash
1635 * @addr: Address in flash to read
1637 * A word is read from the chip, but, only the lower byte is valid.
1639 * Returns the byte read from flash @addr.
1642 qla2x00_read_flash_byte(struct qla_hw_data
*ha
, uint32_t addr
)
1645 uint16_t bank_select
;
1646 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1648 bank_select
= RD_REG_WORD(®
->ctrl_status
);
1650 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
1651 /* Specify 64K address range: */
1652 /* clear out Module Select and Flash Address bits [19:16]. */
1653 bank_select
&= ~0xf8;
1654 bank_select
|= addr
>> 12 & 0xf0;
1655 bank_select
|= CSR_FLASH_64K_BANK
;
1656 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1657 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1659 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1660 data
= RD_REG_WORD(®
->flash_data
);
1662 return (uint8_t)data
;
1665 /* Setup bit 16 of flash address. */
1666 if ((addr
& BIT_16
) && ((bank_select
& CSR_FLASH_64K_BANK
) == 0)) {
1667 bank_select
|= CSR_FLASH_64K_BANK
;
1668 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1669 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1670 } else if (((addr
& BIT_16
) == 0) &&
1671 (bank_select
& CSR_FLASH_64K_BANK
)) {
1672 bank_select
&= ~(CSR_FLASH_64K_BANK
);
1673 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1674 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1677 /* Always perform IO mapped accesses to the FLASH registers. */
1678 if (ha
->pio_address
) {
1681 WRT_REG_WORD_PIO(PIO_REG(ha
, flash_address
), (uint16_t)addr
);
1683 data
= RD_REG_WORD_PIO(PIO_REG(ha
, flash_data
));
1686 data2
= RD_REG_WORD_PIO(PIO_REG(ha
, flash_data
));
1687 } while (data
!= data2
);
1689 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1690 data
= qla2x00_debounce_register(®
->flash_data
);
1693 return (uint8_t)data
;
1697 * qla2x00_write_flash_byte() - Write a byte to flash
1699 * @addr: Address in flash to write
1700 * @data: Data to write
1703 qla2x00_write_flash_byte(struct qla_hw_data
*ha
, uint32_t addr
, uint8_t data
)
1705 uint16_t bank_select
;
1706 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1708 bank_select
= RD_REG_WORD(®
->ctrl_status
);
1709 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
1710 /* Specify 64K address range: */
1711 /* clear out Module Select and Flash Address bits [19:16]. */
1712 bank_select
&= ~0xf8;
1713 bank_select
|= addr
>> 12 & 0xf0;
1714 bank_select
|= CSR_FLASH_64K_BANK
;
1715 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1716 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1718 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1719 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1720 WRT_REG_WORD(®
->flash_data
, (uint16_t)data
);
1721 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1726 /* Setup bit 16 of flash address. */
1727 if ((addr
& BIT_16
) && ((bank_select
& CSR_FLASH_64K_BANK
) == 0)) {
1728 bank_select
|= CSR_FLASH_64K_BANK
;
1729 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1730 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1731 } else if (((addr
& BIT_16
) == 0) &&
1732 (bank_select
& CSR_FLASH_64K_BANK
)) {
1733 bank_select
&= ~(CSR_FLASH_64K_BANK
);
1734 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1735 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1738 /* Always perform IO mapped accesses to the FLASH registers. */
1739 if (ha
->pio_address
) {
1740 WRT_REG_WORD_PIO(PIO_REG(ha
, flash_address
), (uint16_t)addr
);
1741 WRT_REG_WORD_PIO(PIO_REG(ha
, flash_data
), (uint16_t)data
);
1743 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1744 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1745 WRT_REG_WORD(®
->flash_data
, (uint16_t)data
);
1746 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1751 * qla2x00_poll_flash() - Polls flash for completion.
1753 * @addr: Address in flash to poll
1754 * @poll_data: Data to be polled
1755 * @man_id: Flash manufacturer ID
1756 * @flash_id: Flash ID
1758 * This function polls the device until bit 7 of what is read matches data
1759 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1760 * out (a fatal error). The flash book recommeds reading bit 7 again after
1761 * reading bit 5 as a 1.
1763 * Returns 0 on success, else non-zero.
1766 qla2x00_poll_flash(struct qla_hw_data
*ha
, uint32_t addr
, uint8_t poll_data
,
1767 uint8_t man_id
, uint8_t flash_id
)
1775 /* Wait for 30 seconds for command to finish. */
1777 for (cnt
= 3000000; cnt
; cnt
--) {
1778 flash_data
= qla2x00_read_flash_byte(ha
, addr
);
1779 if ((flash_data
& BIT_7
) == poll_data
) {
1784 if (man_id
!= 0x40 && man_id
!= 0xda) {
1785 if ((flash_data
& BIT_5
) && cnt
> 2)
1796 * qla2x00_program_flash_address() - Programs a flash address
1798 * @addr: Address in flash to program
1799 * @data: Data to be written in flash
1800 * @man_id: Flash manufacturer ID
1801 * @flash_id: Flash ID
1803 * Returns 0 on success, else non-zero.
1806 qla2x00_program_flash_address(struct qla_hw_data
*ha
, uint32_t addr
,
1807 uint8_t data
, uint8_t man_id
, uint8_t flash_id
)
1809 /* Write Program Command Sequence. */
1810 if (IS_OEM_001(ha
)) {
1811 qla2x00_write_flash_byte(ha
, 0xaaa, 0xaa);
1812 qla2x00_write_flash_byte(ha
, 0x555, 0x55);
1813 qla2x00_write_flash_byte(ha
, 0xaaa, 0xa0);
1814 qla2x00_write_flash_byte(ha
, addr
, data
);
1816 if (man_id
== 0xda && flash_id
== 0xc1) {
1817 qla2x00_write_flash_byte(ha
, addr
, data
);
1821 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1822 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1823 qla2x00_write_flash_byte(ha
, 0x5555, 0xa0);
1824 qla2x00_write_flash_byte(ha
, addr
, data
);
1830 /* Wait for write to complete. */
1831 return qla2x00_poll_flash(ha
, addr
, data
, man_id
, flash_id
);
1835 * qla2x00_erase_flash() - Erase the flash.
1837 * @man_id: Flash manufacturer ID
1838 * @flash_id: Flash ID
1840 * Returns 0 on success, else non-zero.
1843 qla2x00_erase_flash(struct qla_hw_data
*ha
, uint8_t man_id
, uint8_t flash_id
)
1845 /* Individual Sector Erase Command Sequence */
1846 if (IS_OEM_001(ha
)) {
1847 qla2x00_write_flash_byte(ha
, 0xaaa, 0xaa);
1848 qla2x00_write_flash_byte(ha
, 0x555, 0x55);
1849 qla2x00_write_flash_byte(ha
, 0xaaa, 0x80);
1850 qla2x00_write_flash_byte(ha
, 0xaaa, 0xaa);
1851 qla2x00_write_flash_byte(ha
, 0x555, 0x55);
1852 qla2x00_write_flash_byte(ha
, 0xaaa, 0x10);
1854 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1855 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1856 qla2x00_write_flash_byte(ha
, 0x5555, 0x80);
1857 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1858 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1859 qla2x00_write_flash_byte(ha
, 0x5555, 0x10);
1864 /* Wait for erase to complete. */
1865 return qla2x00_poll_flash(ha
, 0x00, 0x80, man_id
, flash_id
);
1869 * qla2x00_erase_flash_sector() - Erase a flash sector.
1871 * @addr: Flash sector to erase
1872 * @sec_mask: Sector address mask
1873 * @man_id: Flash manufacturer ID
1874 * @flash_id: Flash ID
1876 * Returns 0 on success, else non-zero.
1879 qla2x00_erase_flash_sector(struct qla_hw_data
*ha
, uint32_t addr
,
1880 uint32_t sec_mask
, uint8_t man_id
, uint8_t flash_id
)
1882 /* Individual Sector Erase Command Sequence */
1883 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1884 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1885 qla2x00_write_flash_byte(ha
, 0x5555, 0x80);
1886 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1887 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1888 if (man_id
== 0x1f && flash_id
== 0x13)
1889 qla2x00_write_flash_byte(ha
, addr
& sec_mask
, 0x10);
1891 qla2x00_write_flash_byte(ha
, addr
& sec_mask
, 0x30);
1895 /* Wait for erase to complete. */
1896 return qla2x00_poll_flash(ha
, addr
, 0x80, man_id
, flash_id
);
1900 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1901 * @man_id: Flash manufacturer ID
1902 * @flash_id: Flash ID
1905 qla2x00_get_flash_manufacturer(struct qla_hw_data
*ha
, uint8_t *man_id
,
1908 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1909 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1910 qla2x00_write_flash_byte(ha
, 0x5555, 0x90);
1911 *man_id
= qla2x00_read_flash_byte(ha
, 0x0000);
1912 *flash_id
= qla2x00_read_flash_byte(ha
, 0x0001);
1913 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1914 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1915 qla2x00_write_flash_byte(ha
, 0x5555, 0xf0);
1919 qla2x00_read_flash_data(struct qla_hw_data
*ha
, uint8_t *tmp_buf
,
1920 uint32_t saddr
, uint32_t length
)
1922 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1923 uint32_t midpoint
, ilength
;
1926 midpoint
= length
/ 2;
1928 WRT_REG_WORD(®
->nvram
, 0);
1929 RD_REG_WORD(®
->nvram
);
1930 for (ilength
= 0; ilength
< length
; saddr
++, ilength
++, tmp_buf
++) {
1931 if (ilength
== midpoint
) {
1932 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
1933 RD_REG_WORD(®
->nvram
);
1935 data
= qla2x00_read_flash_byte(ha
, saddr
);
1944 qla2x00_suspend_hba(struct scsi_qla_host
*vha
)
1947 unsigned long flags
;
1948 struct qla_hw_data
*ha
= vha
->hw
;
1949 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1952 scsi_block_requests(vha
->host
);
1953 ha
->isp_ops
->disable_intrs(ha
);
1954 set_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
1957 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1958 WRT_REG_WORD(®
->hccr
, HCCR_PAUSE_RISC
);
1959 RD_REG_WORD(®
->hccr
);
1960 if (IS_QLA2100(ha
) || IS_QLA2200(ha
) || IS_QLA2300(ha
)) {
1961 for (cnt
= 0; cnt
< 30000; cnt
++) {
1962 if ((RD_REG_WORD(®
->hccr
) & HCCR_RISC_PAUSE
) != 0)
1969 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1973 qla2x00_resume_hba(struct scsi_qla_host
*vha
)
1975 struct qla_hw_data
*ha
= vha
->hw
;
1978 clear_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
1979 set_bit(ISP_ABORT_NEEDED
, &vha
->dpc_flags
);
1980 qla2xxx_wake_dpc(vha
);
1981 qla2x00_wait_for_chip_reset(vha
);
1982 scsi_unblock_requests(vha
->host
);
1986 qla2x00_read_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
1987 uint32_t offset
, uint32_t length
)
1989 uint32_t addr
, midpoint
;
1991 struct qla_hw_data
*ha
= vha
->hw
;
1992 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1995 qla2x00_suspend_hba(vha
);
1998 midpoint
= ha
->optrom_size
/ 2;
2000 qla2x00_flash_enable(ha
);
2001 WRT_REG_WORD(®
->nvram
, 0);
2002 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
2003 for (addr
= offset
, data
= buf
; addr
< length
; addr
++, data
++) {
2004 if (addr
== midpoint
) {
2005 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
2006 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
2009 *data
= qla2x00_read_flash_byte(ha
, addr
);
2011 qla2x00_flash_disable(ha
);
2014 qla2x00_resume_hba(vha
);
2020 qla2x00_write_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
2021 uint32_t offset
, uint32_t length
)
2025 uint8_t man_id
, flash_id
, sec_number
, data
;
2027 uint32_t addr
, liter
, sec_mask
, rest_addr
;
2028 struct qla_hw_data
*ha
= vha
->hw
;
2029 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
2032 qla2x00_suspend_hba(vha
);
2037 /* Reset ISP chip. */
2038 WRT_REG_WORD(®
->ctrl_status
, CSR_ISP_SOFT_RESET
);
2039 pci_read_config_word(ha
->pdev
, PCI_COMMAND
, &wd
);
2041 /* Go with write. */
2042 qla2x00_flash_enable(ha
);
2043 do { /* Loop once to provide quick error exit */
2044 /* Structure of flash memory based on manufacturer */
2045 if (IS_OEM_001(ha
)) {
2046 /* OEM variant with special flash part. */
2047 man_id
= flash_id
= 0;
2052 qla2x00_get_flash_manufacturer(ha
, &man_id
, &flash_id
);
2054 case 0x20: /* ST flash. */
2055 if (flash_id
== 0xd2 || flash_id
== 0xe3) {
2057 * ST m29w008at part - 64kb sector size with
2058 * 32kb,8kb,8kb,16kb sectors at memory address
2066 * ST m29w010b part - 16kb sector size
2067 * Default to 16kb sectors
2072 case 0x40: /* Mostel flash. */
2073 /* Mostel v29c51001 part - 512 byte sector size. */
2077 case 0xbf: /* SST flash. */
2078 /* SST39sf10 part - 4kb sector size. */
2082 case 0xda: /* Winbond flash. */
2083 /* Winbond W29EE011 part - 256 byte sector size. */
2087 case 0xc2: /* Macronix flash. */
2088 /* 64k sector size. */
2089 if (flash_id
== 0x38 || flash_id
== 0x4f) {
2094 /* Fall through... */
2096 case 0x1f: /* Atmel flash. */
2097 /* 512k sector size. */
2098 if (flash_id
== 0x13) {
2099 rest_addr
= 0x7fffffff;
2100 sec_mask
= 0x80000000;
2103 /* Fall through... */
2105 case 0x01: /* AMD flash. */
2106 if (flash_id
== 0x38 || flash_id
== 0x40 ||
2108 /* Am29LV081 part - 64kb sector size. */
2109 /* Am29LV002BT part - 64kb sector size. */
2113 } else if (flash_id
== 0x3e) {
2115 * Am29LV008b part - 64kb sector size with
2116 * 32kb,8kb,8kb,16kb sector at memory address
2122 } else if (flash_id
== 0x20 || flash_id
== 0x6e) {
2124 * Am29LV010 part or AM29f010 - 16kb sector
2130 } else if (flash_id
== 0x6d) {
2131 /* Am29LV001 part - 8kb sector size. */
2137 /* Default to 16 kb sector size. */
2144 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
2145 if (qla2x00_erase_flash(ha
, man_id
, flash_id
)) {
2146 rval
= QLA_FUNCTION_FAILED
;
2151 for (addr
= offset
, liter
= 0; liter
< length
; liter
++,
2154 /* Are we at the beginning of a sector? */
2155 if ((addr
& rest_addr
) == 0) {
2156 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
2157 if (addr
>= 0x10000UL
) {
2158 if (((addr
>> 12) & 0xf0) &&
2160 flash_id
== 0x3e) ||
2162 flash_id
== 0xd2))) {
2164 if (sec_number
== 1) {
2185 } else if (addr
== ha
->optrom_size
/ 2) {
2186 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
2187 RD_REG_WORD(®
->nvram
);
2190 if (flash_id
== 0xda && man_id
== 0xc1) {
2191 qla2x00_write_flash_byte(ha
, 0x5555,
2193 qla2x00_write_flash_byte(ha
, 0x2aaa,
2195 qla2x00_write_flash_byte(ha
, 0x5555,
2197 } else if (!IS_QLA2322(ha
) && !IS_QLA6322(ha
)) {
2199 if (qla2x00_erase_flash_sector(ha
,
2200 addr
, sec_mask
, man_id
,
2202 rval
= QLA_FUNCTION_FAILED
;
2205 if (man_id
== 0x01 && flash_id
== 0x6d)
2210 if (man_id
== 0x01 && flash_id
== 0x6d) {
2211 if (sec_number
== 1 &&
2212 addr
== (rest_addr
- 1)) {
2215 } else if (sec_number
== 3 && (addr
& 0x7ffe)) {
2221 if (qla2x00_program_flash_address(ha
, addr
, data
,
2222 man_id
, flash_id
)) {
2223 rval
= QLA_FUNCTION_FAILED
;
2229 qla2x00_flash_disable(ha
);
2232 qla2x00_resume_hba(vha
);
2238 qla24xx_read_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
2239 uint32_t offset
, uint32_t length
)
2241 struct qla_hw_data
*ha
= vha
->hw
;
2244 scsi_block_requests(vha
->host
);
2245 set_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
2248 qla24xx_read_flash_data(vha
, (uint32_t *)buf
, offset
>> 2, length
>> 2);
2251 clear_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
2252 scsi_unblock_requests(vha
->host
);
2258 qla24xx_write_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
2259 uint32_t offset
, uint32_t length
)
2262 struct qla_hw_data
*ha
= vha
->hw
;
2265 scsi_block_requests(vha
->host
);
2266 set_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
2268 /* Go with write. */
2269 rval
= qla24xx_write_flash_data(vha
, (uint32_t *)buf
, offset
>> 2,
2272 clear_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
2273 scsi_unblock_requests(vha
->host
);
2279 qla25xx_read_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
2280 uint32_t offset
, uint32_t length
)
2283 dma_addr_t optrom_dma
;
2286 uint32_t faddr
, left
, burst
;
2287 struct qla_hw_data
*ha
= vha
->hw
;
2291 if (length
< OPTROM_BURST_SIZE
)
2294 optrom
= dma_alloc_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
,
2295 &optrom_dma
, GFP_KERNEL
);
2297 qla_printk(KERN_DEBUG
, ha
,
2298 "Unable to allocate memory for optrom burst read "
2299 "(%x KB).\n", OPTROM_BURST_SIZE
/ 1024);
2305 faddr
= offset
>> 2;
2307 burst
= OPTROM_BURST_DWORDS
;
2312 rval
= qla2x00_dump_ram(vha
, optrom_dma
,
2313 flash_data_addr(ha
, faddr
), burst
);
2315 qla_printk(KERN_WARNING
, ha
,
2316 "Unable to burst-read optrom segment "
2317 "(%x/%x/%llx).\n", rval
,
2318 flash_data_addr(ha
, faddr
),
2319 (unsigned long long)optrom_dma
);
2320 qla_printk(KERN_WARNING
, ha
,
2321 "Reverting to slow-read.\n");
2323 dma_free_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
,
2324 optrom
, optrom_dma
);
2328 memcpy(pbuf
, optrom
, burst
* 4);
2335 dma_free_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
, optrom
,
2341 return qla24xx_read_optrom_data(vha
, buf
, offset
, length
);
2345 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2347 * @pcids: Pointer to the FCODE PCI data structure
2349 * The process of retrieving the FCODE version information is at best
2350 * described as interesting.
2352 * Within the first 100h bytes of the image an ASCII string is present
2353 * which contains several pieces of information including the FCODE
2354 * version. Unfortunately it seems the only reliable way to retrieve
2355 * the version is by scanning for another sentinel within the string,
2356 * the FCODE build date:
2358 * ... 2.00.02 10/17/02 ...
2360 * Returns QLA_SUCCESS on successful retrieval of version.
2363 qla2x00_get_fcode_version(struct qla_hw_data
*ha
, uint32_t pcids
)
2365 int ret
= QLA_FUNCTION_FAILED
;
2366 uint32_t istart
, iend
, iter
, vend
;
2367 uint8_t do_next
, rbyte
, *vbyte
;
2369 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
2371 /* Skip the PCI data structure. */
2373 ((qla2x00_read_flash_byte(ha
, pcids
+ 0x0B) << 8) |
2374 qla2x00_read_flash_byte(ha
, pcids
+ 0x0A));
2375 iend
= istart
+ 0x100;
2377 /* Scan for the sentinel date string...eeewww. */
2380 while ((iter
< iend
) && !do_next
) {
2382 if (qla2x00_read_flash_byte(ha
, iter
) == '/') {
2383 if (qla2x00_read_flash_byte(ha
, iter
+ 2) ==
2386 else if (qla2x00_read_flash_byte(ha
,
2394 /* Backtrack to previous ' ' (space). */
2396 while ((iter
> istart
) && !do_next
) {
2398 if (qla2x00_read_flash_byte(ha
, iter
) == ' ')
2405 * Mark end of version tag, and find previous ' ' (space) or
2406 * string length (recent FCODE images -- major hack ahead!!!).
2410 while ((iter
> istart
) && !do_next
) {
2412 rbyte
= qla2x00_read_flash_byte(ha
, iter
);
2413 if (rbyte
== ' ' || rbyte
== 0xd || rbyte
== 0x10)
2419 /* Mark beginning of version tag, and copy data. */
2421 if ((vend
- iter
) &&
2422 ((vend
- iter
) < sizeof(ha
->fcode_revision
))) {
2423 vbyte
= ha
->fcode_revision
;
2424 while (iter
<= vend
) {
2425 *vbyte
++ = qla2x00_read_flash_byte(ha
, iter
);
2432 if (ret
!= QLA_SUCCESS
)
2433 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
2437 qla2x00_get_flash_version(scsi_qla_host_t
*vha
, void *mbuf
)
2439 int ret
= QLA_SUCCESS
;
2440 uint8_t code_type
, last_image
;
2441 uint32_t pcihdr
, pcids
;
2444 struct qla_hw_data
*ha
= vha
->hw
;
2446 if (!ha
->pio_address
|| !mbuf
)
2447 return QLA_FUNCTION_FAILED
;
2449 memset(ha
->bios_revision
, 0, sizeof(ha
->bios_revision
));
2450 memset(ha
->efi_revision
, 0, sizeof(ha
->efi_revision
));
2451 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
2452 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
2454 qla2x00_flash_enable(ha
);
2456 /* Begin with first PCI expansion ROM header. */
2460 /* Verify PCI expansion ROM header. */
2461 if (qla2x00_read_flash_byte(ha
, pcihdr
) != 0x55 ||
2462 qla2x00_read_flash_byte(ha
, pcihdr
+ 0x01) != 0xaa) {
2464 DEBUG2(qla_printk(KERN_DEBUG
, ha
, "No matching ROM "
2466 ret
= QLA_FUNCTION_FAILED
;
2470 /* Locate PCI data structure. */
2472 ((qla2x00_read_flash_byte(ha
, pcihdr
+ 0x19) << 8) |
2473 qla2x00_read_flash_byte(ha
, pcihdr
+ 0x18));
2475 /* Validate signature of PCI data structure. */
2476 if (qla2x00_read_flash_byte(ha
, pcids
) != 'P' ||
2477 qla2x00_read_flash_byte(ha
, pcids
+ 0x1) != 'C' ||
2478 qla2x00_read_flash_byte(ha
, pcids
+ 0x2) != 'I' ||
2479 qla2x00_read_flash_byte(ha
, pcids
+ 0x3) != 'R') {
2480 /* Incorrect header. */
2481 DEBUG2(qla_printk(KERN_INFO
, ha
, "PCI data struct not "
2482 "found pcir_adr=%x.\n", pcids
));
2483 ret
= QLA_FUNCTION_FAILED
;
2488 code_type
= qla2x00_read_flash_byte(ha
, pcids
+ 0x14);
2489 switch (code_type
) {
2490 case ROM_CODE_TYPE_BIOS
:
2491 /* Intel x86, PC-AT compatible. */
2492 ha
->bios_revision
[0] =
2493 qla2x00_read_flash_byte(ha
, pcids
+ 0x12);
2494 ha
->bios_revision
[1] =
2495 qla2x00_read_flash_byte(ha
, pcids
+ 0x13);
2496 DEBUG3(qla_printk(KERN_DEBUG
, ha
, "read BIOS %d.%d.\n",
2497 ha
->bios_revision
[1], ha
->bios_revision
[0]));
2499 case ROM_CODE_TYPE_FCODE
:
2500 /* Open Firmware standard for PCI (FCode). */
2502 qla2x00_get_fcode_version(ha
, pcids
);
2504 case ROM_CODE_TYPE_EFI
:
2505 /* Extensible Firmware Interface (EFI). */
2506 ha
->efi_revision
[0] =
2507 qla2x00_read_flash_byte(ha
, pcids
+ 0x12);
2508 ha
->efi_revision
[1] =
2509 qla2x00_read_flash_byte(ha
, pcids
+ 0x13);
2510 DEBUG3(qla_printk(KERN_DEBUG
, ha
, "read EFI %d.%d.\n",
2511 ha
->efi_revision
[1], ha
->efi_revision
[0]));
2514 DEBUG2(qla_printk(KERN_INFO
, ha
, "Unrecognized code "
2515 "type %x at pcids %x.\n", code_type
, pcids
));
2519 last_image
= qla2x00_read_flash_byte(ha
, pcids
+ 0x15) & BIT_7
;
2521 /* Locate next PCI expansion ROM. */
2522 pcihdr
+= ((qla2x00_read_flash_byte(ha
, pcids
+ 0x11) << 8) |
2523 qla2x00_read_flash_byte(ha
, pcids
+ 0x10)) * 512;
2524 } while (!last_image
);
2526 if (IS_QLA2322(ha
)) {
2527 /* Read firmware image information. */
2528 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
2530 memset(dbyte
, 0, 8);
2531 dcode
= (uint16_t *)dbyte
;
2533 qla2x00_read_flash_data(ha
, dbyte
, ha
->flt_region_fw
* 4 + 10,
2535 DEBUG3(qla_printk(KERN_DEBUG
, ha
, "dumping fw ver from "
2537 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte
, 8));
2539 if ((dcode
[0] == 0xffff && dcode
[1] == 0xffff &&
2540 dcode
[2] == 0xffff && dcode
[3] == 0xffff) ||
2541 (dcode
[0] == 0 && dcode
[1] == 0 && dcode
[2] == 0 &&
2543 DEBUG2(qla_printk(KERN_INFO
, ha
, "Unrecognized fw "
2544 "revision at %x.\n", ha
->flt_region_fw
* 4));
2546 /* values are in big endian */
2547 ha
->fw_revision
[0] = dbyte
[0] << 16 | dbyte
[1];
2548 ha
->fw_revision
[1] = dbyte
[2] << 16 | dbyte
[3];
2549 ha
->fw_revision
[2] = dbyte
[4] << 16 | dbyte
[5];
2553 qla2x00_flash_disable(ha
);
2559 qla24xx_get_flash_version(scsi_qla_host_t
*vha
, void *mbuf
)
2561 int ret
= QLA_SUCCESS
;
2562 uint32_t pcihdr
, pcids
;
2565 uint8_t code_type
, last_image
;
2567 struct qla_hw_data
*ha
= vha
->hw
;
2570 return QLA_FUNCTION_FAILED
;
2572 memset(ha
->bios_revision
, 0, sizeof(ha
->bios_revision
));
2573 memset(ha
->efi_revision
, 0, sizeof(ha
->efi_revision
));
2574 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
2575 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
2579 /* Begin with first PCI expansion ROM header. */
2580 pcihdr
= ha
->flt_region_boot
<< 2;
2583 /* Verify PCI expansion ROM header. */
2584 qla24xx_read_flash_data(vha
, dcode
, pcihdr
>> 2, 0x20);
2585 bcode
= mbuf
+ (pcihdr
% 4);
2586 if (bcode
[0x0] != 0x55 || bcode
[0x1] != 0xaa) {
2588 DEBUG2(qla_printk(KERN_DEBUG
, ha
, "No matching ROM "
2590 ret
= QLA_FUNCTION_FAILED
;
2594 /* Locate PCI data structure. */
2595 pcids
= pcihdr
+ ((bcode
[0x19] << 8) | bcode
[0x18]);
2597 qla24xx_read_flash_data(vha
, dcode
, pcids
>> 2, 0x20);
2598 bcode
= mbuf
+ (pcihdr
% 4);
2600 /* Validate signature of PCI data structure. */
2601 if (bcode
[0x0] != 'P' || bcode
[0x1] != 'C' ||
2602 bcode
[0x2] != 'I' || bcode
[0x3] != 'R') {
2603 /* Incorrect header. */
2604 DEBUG2(qla_printk(KERN_INFO
, ha
, "PCI data struct not "
2605 "found pcir_adr=%x.\n", pcids
));
2606 ret
= QLA_FUNCTION_FAILED
;
2611 code_type
= bcode
[0x14];
2612 switch (code_type
) {
2613 case ROM_CODE_TYPE_BIOS
:
2614 /* Intel x86, PC-AT compatible. */
2615 ha
->bios_revision
[0] = bcode
[0x12];
2616 ha
->bios_revision
[1] = bcode
[0x13];
2617 DEBUG3(qla_printk(KERN_DEBUG
, ha
, "read BIOS %d.%d.\n",
2618 ha
->bios_revision
[1], ha
->bios_revision
[0]));
2620 case ROM_CODE_TYPE_FCODE
:
2621 /* Open Firmware standard for PCI (FCode). */
2622 ha
->fcode_revision
[0] = bcode
[0x12];
2623 ha
->fcode_revision
[1] = bcode
[0x13];
2624 DEBUG3(qla_printk(KERN_DEBUG
, ha
, "read FCODE %d.%d.\n",
2625 ha
->fcode_revision
[1], ha
->fcode_revision
[0]));
2627 case ROM_CODE_TYPE_EFI
:
2628 /* Extensible Firmware Interface (EFI). */
2629 ha
->efi_revision
[0] = bcode
[0x12];
2630 ha
->efi_revision
[1] = bcode
[0x13];
2631 DEBUG3(qla_printk(KERN_DEBUG
, ha
, "read EFI %d.%d.\n",
2632 ha
->efi_revision
[1], ha
->efi_revision
[0]));
2635 DEBUG2(qla_printk(KERN_INFO
, ha
, "Unrecognized code "
2636 "type %x at pcids %x.\n", code_type
, pcids
));
2640 last_image
= bcode
[0x15] & BIT_7
;
2642 /* Locate next PCI expansion ROM. */
2643 pcihdr
+= ((bcode
[0x11] << 8) | bcode
[0x10]) * 512;
2644 } while (!last_image
);
2646 /* Read firmware image information. */
2647 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
2650 qla24xx_read_flash_data(vha
, dcode
, ha
->flt_region_fw
+ 4, 4);
2651 for (i
= 0; i
< 4; i
++)
2652 dcode
[i
] = be32_to_cpu(dcode
[i
]);
2654 if ((dcode
[0] == 0xffffffff && dcode
[1] == 0xffffffff &&
2655 dcode
[2] == 0xffffffff && dcode
[3] == 0xffffffff) ||
2656 (dcode
[0] == 0 && dcode
[1] == 0 && dcode
[2] == 0 &&
2658 DEBUG2(qla_printk(KERN_INFO
, ha
, "Unrecognized fw "
2659 "revision at %x.\n", ha
->flt_region_fw
* 4));
2661 ha
->fw_revision
[0] = dcode
[0];
2662 ha
->fw_revision
[1] = dcode
[1];
2663 ha
->fw_revision
[2] = dcode
[2];
2664 ha
->fw_revision
[3] = dcode
[3];
2671 qla2xxx_is_vpd_valid(uint8_t *pos
, uint8_t *end
)
2673 if (pos
>= end
|| *pos
!= 0x82)
2677 if (pos
>= end
|| *pos
!= 0x90)
2681 if (pos
>= end
|| *pos
!= 0x78)
2688 qla2xxx_get_vpd_field(scsi_qla_host_t
*vha
, char *key
, char *str
, size_t size
)
2690 struct qla_hw_data
*ha
= vha
->hw
;
2691 uint8_t *pos
= ha
->vpd
;
2692 uint8_t *end
= pos
+ ha
->vpd_size
;
2695 if (!IS_FWI2_CAPABLE(ha
) || !qla2xxx_is_vpd_valid(pos
, end
))
2698 while (pos
< end
&& *pos
!= 0x78) {
2699 len
= (*pos
== 0x82) ? pos
[1] : pos
[2];
2701 if (!strncmp(pos
, key
, strlen(key
)))
2704 if (*pos
!= 0x90 && *pos
!= 0x91)
2710 if (pos
< end
- len
&& *pos
!= 0x78)
2711 return snprintf(str
, size
, "%.*s", len
, pos
+ 3);